Datasheet SMD99F-5012, SMD99F-5012MC2, SMD99F-5016, SMD99F-5016MC2, SMD99F-5020 Datasheet (Datadelay)

SMD99F

Doc #97017 DATA DELAY DEVICES, INC. 1

1/30/97 3 Mt. Prospect Ave. Clifton, NJ 07013

5-TAP, TTL-INTERFACED
FIXED DELAY LINE
(SERIES SMD99F)

FEATURES PACKAGES

• Five equally spaced outputs

• Designed for surface mounting

• Low profile (0.175 maximum height)

• Input & outputs fully TTL interfaced & buffered

• 10 T2L fan-out capability

FUNCTIONAL DESCRIPTION

The SMD99F-series device is a 5-tap digitally buffered delay line. The
signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an
amount determined by the device dash number (See Table). For dash
numbers less than 5025, the total delay of the line is measured from T1 to
T5. The nominal tap-to-tap delay increment is given by one-fourth of the
total delay, and the inherent delay from IN to T1 is nominally 3.5ns. For dash numbers greater than or
equal to 5025, the total delay of the line is measured from IN to T5. The nominal tap-to-tap delay
increment is given by one-fifth of this number.

SERIES SPECIFICATIONS

• Minimum input pulse width: 40% of total delay

• Output rise time: 2ns typical

• Supply voltage: 5VDC ± 5%

• Supply current: I

CCL

= 32ma typical

I

CCH

= 7ma typical

• Operating temperature: 0° to 70° C

• Temp. coefficient of total delay: 100 PPM/°C

25% 25% 25% 25%

VCC GNDIN T1 T2 T3 T4 T5

Functional diagram for dash numbers < 5025

3.5ns

20% 20% 20% 20% 20%

VCC GNDIN T1 T2 T3 T4 T5

Functional diagram for dash numbers >= 5025

1997 Data Delay Devices

data

delay
devices, inc.



3

1

4
6

7

14

12
10

8

IN

T2
T4

GND

VDD

T1
T3
T5

14
13
12
11
10

9
8

1
2
3
4
5
6
7

IN
N/C
N/C

T2

N/C

T4

GND

VCC
N/C
T1
N/C
T3
N/C
T5

Commercial

SMD99F-xx

Military

SMD99F-xxMC2

PIN DESCRIPTIONS

IN Signal Input
T1-T5 Tap Outputs
VCC +5 Volts
GND Ground

DASH NUMBER SPECIFICATIONS

Part

Number

Total

Delay (ns)

Delay Per

Tap (ns)

SMD99F-5004

4 ± 1.0 * 1.0 ± 0.5

SMD99F-5006

6 ± 1.0 * 1.5 ± 0.5

SMD99F-5008

8 ± 2.0 * 2.0 ± 1.0

SMD99F-5010

10 ± 2.0 * 2.5 ± 1.0

SMD99F-5012

12 ± 2.0 * 3.0 ± 1.0

SMD99F-5016

16 ± 2.0 * 4.0 ± 1.5

SMD99F-5020

20 ± 3.0 * 5.0 ± 2.0

SMD99F-5025

25 ± 3.0 5.0 ± 2.0

SMD99F-5030

30 ± 3.0 6.0 ± 2.0

SMD99F-5035

35 ± 3.0 7.0 ± 2.0

SMD99F-5040

40 ± 3.0 8.0 ± 2.0

SMD99F-5045

45 ± 3.0 9.0 ± 3.0

SMD99F-5050

50 ± 3.0 10.0 ± 3.0

SMD99F-5060

60 ± 3.0 12.0 ± 3.0

SMD99F-5075

75 ± 4.0 15.0 ± 3.0

SMD99F-5100

100 ± 5.0 20.0 ± 3.0

SMD99F-5125

125 ± 6.5 25.0 ± 3.0

SMD99F-5150

150 ± 7.5 30.0 ± 3.0

SMD99F-5175

175 ± 8.0 35.0 ± 4.0

SMD99F-5200

200 ± 10.0 40.0 ± 4.0

SMD99F-5250

250 ± 12.5 50.0 ± 5.0

* Total delay is referenced to first tap output
Input to first tap = 3.5ns ±± 1ns

NOTE: Any dash number between 5004 and 5250

not shown is also available.

SMD99F

Doc #97017 DATA DELAY DEVICES, INC. 2

1/30/97 Tel: [phone] Fax: [phone] http://www.datadelay.com

APPLICATION NOTES

HIGH FREQUENCY RESPONSE

The SMD99F tolerances are guaranteed for input
pulse widths and periods greater than those
specified in the test conditions. Although the
device will function properly for pulse widths as
small as 40% of the total delay and periods as
small as 80% of the total delay (for a symmetric
input), the delays may deviate from their values
at low frequency. However, for a given input
condition, the deviation will be repeatable from
pulse to pulse. Contact technical support at Data

Delay Devices if your application requires device
testing at a specific input condition.

POWER SUPPLY BYPASSING

The SMD99F relies on a stable power supply to
produce repeatable delays within the stated
tolerances. A 0.1uf capacitor from VCC to GND,
located as close as possible to the VCC pin, is
recommended. A wide VCC trace and a clean
ground plane should be used.

DEVICE SPECIFICATIONS

TABLE 1: ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL MIN MAX UNITS NOTES

DC Supply Voltage V

CC

-0.3 7.0 V

Input Pin Voltage V

IN

-0.3 VDD+0.3 V

Storage Temperature T

STRG

-55 150 C

Lead Temperature T

LEAD

300 C 10 sec

TABLE 2: DC ELECTRICAL CHARACTERISTICS

(0C to 70C, 4.75V to 5.25V)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

High Level Output Voltage V

OH

2.5 3.4 V VCC = MIN, IOH = MAX
VIH = MIN, VIL = MAX

Low Level Output Voltage V

OL

0.35 0.5 V VCC = MIN, IOL = MAX
VIH = MIN, VIL = MAX

High Level Output Current I

OH

-1.0 mA

Low Level Output Current I

OL

20.0 mA

High Level Input Voltage V

IH

2.0 V

Low Level Input Voltage V

IL

0.8 V

Input Clamp Voltage V

IK

-1.2 V VCC = MIN, II = I

IK

Input Current at Maximum
Input Voltage

I

IHH

0.1 mA VCC = MAX, VI = 7.0V

High Level Input Current I

IH

20

µA

VCC = MAX, VI = 2.7V

Low Level Input Current I

IL

-0.6 mA VCC = MAX, VI = 0.5V

Short-circuit Output Current I

OS

-60 -150 mA VCC = MAX
Output High Fan-out 25 Unit
Output Low Fan-out 12.5 Load

SMD99F

Doc #97017 DATA DELAY DEVICES, INC. 3

1/30/97 3 Mt. Prospect Ave. Clifton, NJ 07013

PACKAGE DIMENSIONS

.350 TYP.

SMD99F-xx (Commercial)

1

7 8

.510
MAX.

14

.020

4
6

12
10

.510 MAX.

.480 MAX.

.150

.100

.150

.050

.150CL

.175 MAX.

.015

.050 MIN.

.001 MIN.

.780±.020

.882

±.005

1 2 3 4 5 6 7

8

.020 TYP.

.040
TYP.

.100

.090

.600

.280
MAX.

.590

MAX.

.010±.002

.050

±.010

.710

±.005

.007

±.005

91011121314

SMD99F-xxMC2 (Military)

SMD99F

Doc #97017 DATA DELAY DEVICES, INC. 4

1/30/97 Tel: [phone] Fax: [phone] http://www.datadelay.com

DELAY LINE AUTOMATED TESTING

TEST CONDITIONS

INPUT: OUTPUT:
Ambient Temperature: 25oC ± 3oC Load: 1 FAST-TTL Gate
Supply Voltage (Vcc): 5.0V ± 0.1V C

load

: 5pf ± 10%

Input Pulse: High = 3.0V ± 0.1V Threshold: 1.5V (Rising & Falling)

Low = 0.0V ± 0.1V

Source Impedance: 50Ω Max.
Rise/Fall Time: 3.0 ns Max. (measured

between 0.6V and 2.4V )

Pulse Width: PWIN = 1.5 x Total Delay
Period: PERIN = 10 x Total Delay

NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.

T1

OUT

TRIGINREF

TRIG

Test Setup

DEVICE UNDER

TEST (DUT)

TIME INTERVAL

COUNTER

PULSE

GENERATOR

COMPUTER

SYSTEM

PRINTER

INT2T3T4T5

Timing Diagram For Testing

T

RISE

T

FALL

PER

IN

PW

IN

T

RISE

T

FALL

0.6V

0.6V

1.5V

1.5V

2.4V

2.4V

1.5V

1.5V

V

IH

V

IL

V

OH

V

OL

INPUT
SIGNAL

OUTPUT
SIGNAL