Cypress Semiconductor CY7C68013-56PVC, CY7C68013-56LFC, CY7C68013-128AC, CY7C68013-100AC Datasheet

CY7C68013

CY7C68013

EZ-USB FX2™ USB Microcontroller
High-speed USB Peripheral Controller

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600

Document #: 38-08012 Rev. *C Revised December 19, 2002

CY7C68013

TABLE OF CONTENTS

1.0 EZ-USB FX2™ FEATURES ............................................................................................................. 6

2.0 APPLICATIONS ...............................................................................................................................7

3.0 FUNCTIONAL OVERVIEW ............ .. .. .. .. .................................... .. .. .. .................................... .. .. ........7

3.1 USB Signaling Speed ........................................................................................ .. .......................7

3.2 8051 Microprocessor ................ .. .................... .. .................... ........................................ .. ............7

2

3.3 I

C-compatible Bus .....................................................................................................................8

3.4 Buses ..........................................................................................................................................8

3.5 USB Boot Methods .....................................................................................................................9

3.6 ReNumeration™ ......................................................................................................................... 9

3.7 Bus Powered Applications ..........................................................................................................9

3.8 Interrupt System ........................................................................................................................10

3.9 Reset and Wakeup ....................... .................... .. .................... .. .................... .. ..........................11

3.10 Program/Data RAM .................................................................................................................11

3.11 Register Addresses .................................................................................................................14

3.12 Endpoint RAM .......................................... .. ............................................. ................................ 14

3.13 Externa l F IF O in te rface ............................................... .......................................... ..................16

3.14 GPIF ........................................................................................................................................16

3.15 USB Uploads and Downloads ............................. .. ......................... .. .. .. ......................... .. ........17

3.16 Autopointer Access .................................................. .. ...................... .. ...................... ...............17

2

3.17 I

C-compatible Controller ........................................................................................................17

4.0 PIN ASSIGNMENTS .............................. .................... .. .................... .. .................... ........................18

4.1 CY7C68013 Pin Descriptions .................. .............................................................. ...................24

5.0 REGISTER SUMMARY ..................................... ........................................... .. .. ..............................31

6.0 ABSOLUTE MAXIMUM RATINGS ................................................................................................37

7.0 OPERATING CONDITIONS .................................................. .. .................... .................... .. .............37

8.0 DC CHARACTERISTICS ................................ .. ........................... .. .. .. ........................... .. .. .............37

8.1 USB Transceiver .......................................................................................................................37

9.0 AC ELECTRICAL CHARACTERISTICS ........... .. .................... .. .................... .. .................... ..........38

9.1 USB Transceiver .......................................................................................................................38

9.2 Program Memory Read ............................ .. ................................................. .. ............................38

9.3 Data Memory Read ................... .. ...................... .. .. ............................................ ........................39

9.4 Data Memory Write ...................................................................................................................40

9.5 GPIF Synchronous Signals ........................................................... ................................ ............41

9.6 Slave FIFO Synchronous Read ..................................................................................... ...........42

9.7 Slave FIFO A s y nc h r o no u s R e ad ..............................................................................................43

9.8 Slave FIFO Synchronous Write ..................... ................................. ..........................................43

9.9 Slave FIFO Asynchronous W rite ......... ............... .......................................................................44

9.10 Slave FIFO Synchronous Packet End Strobe .........................................................................44

9.11 Slave FIFO Asynchronous Packet End Strobe .......................................................................45

9.12 Slave FIFO Output Enable ......................................................................................................45

9.13 Slave FIFO A d d re s s to F la g s /D a t a ......... ................ .......................................... ......................45

9.14 Slave FIFO S y n ch r o n ou s A d d re s s ............................ .......................................... ....................46

9.15 Slave FIFO Asynchronous Address ................................... .....................................................46

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CY7C68013

10.0 ORDERING INFORMATION ................................................................. .. .. ............................... ....46

11.0 PACKAGE DIAGRAMS ............................................. .................................... .. .. ..........................47

12.0 PCB LAYOUT RECOMMENDATIONS ......................... .. .. .. .. ................................ .. .. .. .. .. .............50

13.0 QUAD FLAT PACKAGE NO LEADS (QFN) PACKAGE DESIGN NOTES .................... .. ..........50

Document #: 38-08012 Rev. *C Page 3 of 52

CY7C68013

LIST OF FIGURES

Figure 1-1. Blo c k Di a gr a m .......................... .......................................... ...................................................6

Figure 3-1. Internal Code Memory, EA = 0........................... ....................................... .. .................. ......12

Figure 3-2. External Code Memory, EA = 1................................ .................. .................... .....................13

Figure 3-3. Endpoint Configuration........................................................................................................15

Figure 4-1. Signals.................................................................................................................................19

Figure 4-2. CY7C68013 128-pin TQFP Pin Assignment.......................................................................20

Figure 4-3. CY7C68013 100-pin TQFP Pin Assignment.......................................................................21

Figure 4-4. CY7C68013 56-pin SSOP Pin Assignment.........................................................................22

Figure 4-5. CY7C68013 56-pin QFN Pin Assignment.......................................... .................................23

Figure 9-1. Pro g r a m M e m o ry R ead T i ming Diagram.... .. .......................................................................38

Figure 9-2. Data Memory Read Timing Diagram...................................................................................39

Figure 9-3. Data M e m o r y Wr ite T im ing Diagram......................................... ............................ .............. 40

Figure 9-4. GPIF Synchronous Signals Timing Diagram .......................................................................41

Figure 9-5. Slave FIFO Synchronous Read Timing Diagram...................................... .. ........................42

Figure 9-6. Slave FIFO Asynchronous Read Timing Diagram ..............................................................43

Figure 9-7. Slave FIFO Synchronous Write Timing Diagram ........................... .. ...................... .............43

Figure 9-8. Slave FIFO Asynchronous Write Timing Diagram...................... .. .......................................44

Figure 9-9. Slave FIFO Synchronous Packet End Strobe Timing Diagram...........................................44

Figure 9-10. Slave FIFO Asynchronous Packet End Strobe Timing Diagram.......................................45

Figure 9-11. Slave FIFO Output Enable Timing Diagram......................................................................45

Figure 9-12. Slave FIFO Address to Flags/Data Timing Diagram ......................................................... 45

Figure 9-13. Slave FIFO Synchronous Address Timing Diagram..........................................................46

Figure 9-14. Slave FIFO Asynchronous Address Timing Diagram................................... .....................46

Figure 11-1. 56-lead Shrunk Small Outline Package O56.................................... .................................47

Figure 11-2. 56-lead Quad Flatpack No Lead Package (8 × 8 mm) LF56................................ .............47

Figure 11-3. 100-Pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A101 .........................................48

Figure 11-4. 128-Lead Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A128 ......................................49

Figure 13-1. Cross-section of the Area Underneath the QFN Package ................................................50

Figure 13-2. P lo t of th e S o ld e r Ma s k (White Area)............. ... ............... .......................................... .......50

Figure 13-3. X -r a y im ag e o f th e as s e mb ly................................................ .............................................51

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CY7C68013

LIST OF TABLES

Table 3-1. Special Function Registers ................................. ..................... .................... ..........................9

Table 3-2. Default ID Values for FX2 ................... .. .................... .. .................... .. .....................................9

Table 3-3. INT2 USB Interrupts ................................................... ...................... .................... ...............10

Table 3-4. Individual FIFO/GPIF Interr upt Sources .......... .. ..................................................................11

Table 3-5. Default Full-Speed Alternate Setti ngs ................................... .................... .. ........................15

Table 3-6. Default High-Speed Alternate Settings .......................................................... ......................16

Table 3-7. Strap Boot EEPROM Address Lines to These Values ........................................... .............18

Table 4-1. FX2 Pin Descriptions ............................ ................................. ................ ..............................24

Table 5-1. FX2 Register Summary ............................... .................... .................... .................... ............31

Table 8-1. DC Characteristics ................... .................... .................... .................... ................................37

Table 9-1. Program Memory Read Parameters ............................................. .. .................... .. ...............38

Table 9-2. Data Memory Read Parameters .................... .. ........................................ .................... .. ......39

Table 9-3. Data Memory Write Parameters ............................... ..................................................... ......40

Table 9-4. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK .............................41

Table 9-5. GPIF Synchronous Signals Parameters wit h Externally Sourced IFCLK ............................41

Table 9-6. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK .......................42

Table 9-7. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK .....................42

Table 9-8. Slave FIFO Asynchronous Read Parameters ............................................. .................... .. ..43

Table 9-9. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK .......................43

Table 9-10. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK ....................44

Table 9-11. Slave FIFO Asynchronous Write Parameters wi th Internally Sourced IFCLK ............. .. ....44

Table 9-12. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK 44
Table 9-13. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK 45

Table 9-14. Slave FIFO Asynchronous Packet End Strobe Parameters ............................... ...............45

Table 9-15. Slave FIFO Output Enable Parameters ........................................................ .. ...................45

Table 9-16. Slave FIFO Address to Flags/Data Parameters ....................... .. .................. .. .................. .46

Table 9-17. Slave FIFO Synchronous Address Parameters .................................................................46

Table 9-18. Slave FIFO Asynchronous Address Parameters ............................... ................................46

Table 10-1. Ordering Information ................................ ....................................... .................. .................46

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CY7C68013

1.0 EZ-USB FX2 Features

Cypress’s EZ-USB FX2 is the world’s first USB 2.0 integrated microcontroller. By integrating the USB 2.0 transceiver, SIE,
enhanced 805 1 microcontroll er, and a programmable peri pheral interfac e in a single chip, Cypr ess has created a ver y cost­effective solution that provides superior time-to-market advantages. The ingenious architecture of FX2 results in data transfer
rates of 56 Mbytes per second, the maximum allowable USB 2.0 bandwidth, while still using a low-cost 8051 microcontroller in
a package as small as a 56 SSOP. Because it incorporates the USB 2.0 transceiver, the FX2 is more economical, providing a
smaller footprint solution than USB 2.0 SIE or external transceiver implementations. With EZ-USB FX2, the Cypress Smart SIE
handles most of th e USB 1.1 and 2 .0 protocol in hardware, freeing th e embedded micr ocontroller fo r application-spec ific functions
and decreasing development time to ensure USB compatibility. The General Programmable Interface (GPIF) and Master/Slave
Endpoint FIFO (8- or 16- bit data bus) provides an easy and glue les s int erfa ce to p op ula r in terfaces such as
PCMCIA, and most DSP/processors.

Four packages are defined for the family: 56 SSOP, 56 QFN, 100 TQFP, and 128 TQFP.

24 MHz

Ext. XTAL

High-performance micro
using standard tools
with lower-power options

FX2

ATA, UTOPIA, EPP,

Data (8)

Compatible

Additional I/Os (24)

GPIF

Address (16) / Data Bus (8)

4 kB

FIFO

FIFO and endpoint memory
(master or slave operation)

2

I

C

Master

ADDR (9)

Integrated

full- and high-speed

XCVR

D+

D–

x20

V

CC

PLL

1.5k
connected for

full speed

USB

2.0

XCVR

Enhanced USB core
Simplifies 8051 core

/0.5
/1.0
/2.0

CY

Smart

USB

1.1/2.0

Engine

Address (16)

8051 Core

12/24/48 MHz,

four clocks/cycle

8.5 kB
RAM

“Soft Configuration”

Easy firmware changes

Figure 1-1. Block Diagram

• Single-chip integrated USB 2.0 Transceiver, SIE, and Enhanced 8051 Microprocessor

• Software: 8051 runs from internal RAM, which is:
—Downloaded via USB, or
—Loaded from EEPROM
—External memory device (128-pin configuration only)

• Four programmable BULK/INTERRUPT/ISOCHRONOUS endpoints
—Buffering options: double, triple and quad

• 8- or 16-bit external data interface

• GPIF
—Allows direct connection to most parallel interfaces; 8- and 16-bit

—Programmable waveform descriptors and configuration registers to define waveforms
—Supports multiple Ready (RDY) inputs and Control (CTL) outputs

• Integrated, industry standard 8051 with enhanced features:
—Up to 48-MHz clock rate

—Four clocks per instruction cycle
—Two USARTS

RDY (6)
CTL (6)

8/16

Abundant I/O

including two USARTS

General
programmable I/F
to ASIC/DSP or bus

standards such as

ATAPI, EPP, etc.

Up to 96 MBytes/s

burst rate

Document #: 38-08012 Rev. *C Page 6 of 52

—Three counter/timers
—Expanded interrupt system
—Two data pointers

• Supports bus powered applications by using renumeration

• 3.3V operation

• Smart Serial Interface Engine

• Vectored USB interrupts

• Separate data buffers for the SETUP and DATA portions of a CONTROL transfer

• Integrated I

• 48-MHz, 24-MHz, or 12-MHz 8051 operation

• Four integrated FIFOs
—Brings glue and FIFOs inside for lower system cost

—Automatic conversion to and from 16-bit buses
—Master or slave operation
—FIFOs can use externally supplied clock or asynchronous strobes
—Easy interface to ASIC and DSP ICs

• Special autovectors for FIFO and GPIF interrupts

• Up to 40 general purpose I/Os

• Four package options—128-pin TQFP, 100-pin TQFP, 56-pin QFN and 56-pin SSOP.

2

C-compatible controller, runs at 100 or 400 kHz

2.0 Applications

CY7C68013

• DSL modems

• ATA interface

• Memory card readers

• Legacy conversion devices

• Cameras

• Scanners

• Home PNA

• Wireless LAN

• MP3 players

• Networking.

The “Reference Designs” section of the c ypress website provides additio nal tools for ty pical USB 2.0 app lications. Eac h reference
design comes complete with firmware source and object code, schematics, and documentation. Please visit
http://www.cypress.com for more information.

3.0 Functional Overview

3.1 USB Signaling Speed

FX2 operates at two of the three rates defined in the Universal Serial Bus Specification Revision 2.0, dated April 27, 2000:

• Full speed, with a signaling bit rate of 12 Mbps

• High speed, with a si gnaling bit rate of 480 Mbps

FX2 does not support the low-speed signaling mode of 1.5 Mbps.

3.2 8051 Microprocessor

The 8051 microprocessor embedded in the FX2 family has 256 bytes of register RAM, an expanded interrupt system, three
timer/counters, and two USARTs.

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CY7C68013

3.2.1 8051 Clock Frequency

FX2 has an on-chip oscillator circuit that uses an external 24-MHz (±100 ppm) crystal with the following characteristics:

• Parallel resonant

• Fundamental mode

• 500-µW drive level

• 20–33 pF (5% tolerance) load capacitors.

An on-chip PLL multiplies the 24-MH z oscill ator up to 48 0 MHz, as requi red by the trans ceive r/PHY, and internal counter s divide
it down for use as the 80 51 cloc k. The defau lt 8051 cloc k freq uency is 1 2 MHz. The c lock frequen cy o f the 8051 can b e cha nged
by the 8051 through the CPUCS register, dynamically.

The CLKOUT pin, which can be tri-stated and inverted using internal control bits, outputs the 50% duty cycle 8051 clock, at the
selected 8051 clock frequency—48, 24, or 12 MHz.

3.2.2 USARTS

FX2 contains two standard 8051 USARTs, addressed via Special Function Register (SFR) bits. The USART interface pins are
available on separate I/O pins, and are not multiplexed with port pins.

UART0 and UAR T1 can operate using an internal clock at 230 KBaud with no more than 1% ba ud rate error . 230-KBaud operation
is achieved by an internally deriv ed clock sour ce that generates overflow pulses at the appropriat e time. The intern al clock ad justs
for the 8051 clock rate (48, 24, 12 MHz) such that it always presents the correct frequency for 230-KBaud operation.

Note. 1 15-KBau d operatio n is also p ossible by programm ing the 8 051 SMOD0 or SMOD 1 bits to a “1” fo r UART 0 and/or UA RT1,
respectively.

3.2.3 Special Function Registers

Certain 8051 SFR addresses are populated to provide fast access to critical FX2 functions. These SFR additions are shown in
Table 3-1. Bold type indicates non-standard, enhanced 8051 registers.

The two SFR rows that end with “0” and “8” contain bit-addressable registers. The four I/O ports A–D use the SFR addresses
used in the standard 8051 for ports 0–3, which are not implemented in FX2.

Because of the faster and more efficient SFR addressing, the FX2 I/O ports are not addressable in external RAM space (using
the MOVX instruction).

3.3 I2C-compatible Bus

FX2 supports the I2C-compatible bus as a master only at 100/400 kbps. SCL and SDA pins have open-drain outputs and
hysteresis inputs. These signals must be pulled up to 3.3V, even if no I

2

C-compatible device is connected.

3.4 Buses

All packages: 8- or 16-bit “FIFO” bidirectional data bus, multiplexed on I/O ports B and D. 128-pin package: adds 16-bit output­only 8051 address bus, 8-bit bidirectional data bus.

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CY7C68013

Table 3-1. Special Function Registers

x8x 9x Ax Bx CxDxExFx

0
1SP EXIF
2DPL0 MPAGE
3DPH0
4 DPL1
5 DPH1
6 DPS
7PCON
8 TCON SCON0 IE IP T2CON EICON EIE EIP
9 TMOD SBUF0
ATL0AUTOPTRH1 EP2468STAT EP01STAT RCAP2L

BTL1AUTOPTRL1 EP24FIFOFLGS GPIFTRIG RCAP2H
CTH0reserved EP68FIFOFLGS TL2
DTH1AUTOPTRH2 GPIFSGLDATH TH2
E CKCON AUTOPTRL2 GPIFSGLDATLX
F reserved AUTOPTRSETUP GPIFSGLDATLNOX

IOA IOB IOC IOD SCON1 PSW ACC B

INT2CLR IOE SBUF1
INT4CLR OEA

OEB
OEC
OED
OEE

3.5 USB Boot Methods

During the power-u p s equ en ce, in ternal logic checks the I2C-compatible port for the connection of an EEPROM whose first byte
is either 0xC0 or 0xC2. If found, it uses the VID/PID/DID values in the EEPROM in place of the internally stored values (0xC0),
or it boot-loads the EEPROM contents into internal RAM (0xC2). If no EEPROM is detected, FX2 enumerates using internally
stored descriptors. The default ID values for FX2 are VID/PID/DID (0x04B4, 0x8613, 0xxxyy).

Table 3-2. Default ID Values for FX2

Default VID/PID/DID

Vendor ID 0x04B4 Cypress Semiconductor
Prod ID 0x8613 EZ-USB FX2
Device release 0xXXYY Depends on revision (0x04 for Rev E)

2

Note. The I
detection method does not work properly.

3.6 ReNumeration

Because the FX2’s configuration is soft, one chip can take on the identities of multiple distinct USB devices.
When first plugged into USB, the FX2 enumerates automatically and downloads firmware and USB descriptor tables over the

USB cable. Next, the FX2 enumerates again, this time as a device defined by the downloaded information. This patented two­step process, called ReNumeration
has occurred.

Two control bits in the USBCS (USB Control and Status) register control the ReNumeration process: DISCON and RENUM. To
simulate a USB disconnect, the firmware sets DISCON to 1. To reconnect, the firmware clears DISCON to 0.

Before reconnecting, the fi rmwa re se t s or clears the RENUM bi t to in dic at e wheth er the firmware o r t he Defa ul t USB Device wil l
handle device requests over endpoint zero: if RENUM = 0, the Default USB Device will handle device requests; if RENUM = 1,
the firmware will.

C-compatible bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this

™

™

, happens instantl y when the dev ice is plugged in, with no hint tha t the in itial down load ste p

3.7 Bus Powered Applications

Bus powered applicat ions requi re the FX2 to enum erate in a un configure d mode with le ss then 100 mA. To do this, the FX2 must
enumerate in the full speed mode and then, when configured, renumerate in high speed mode. For an example of the benefits
and limitations of this renumeration process see the application note titled “Bus Powered Enumeration with FX2”.

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CY7C68013

3.8 Interrupt System

3.8.1 INT2 Interrupt Request and Enable Registers

FX2 implements an autovector feature for INT2 and INT4. There are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF) vectors.
See FX2 TRM for more details.

3.8.2 USB-Interrupt Autovectors

The main USB interrupt is sh ared by 27 interru pt sources . To save the code and processi ng time that normally wou ld be required
to identify the individual USB interrupt source, the FX2 p rovides a second l evel of interrupt vec toring, c alled Aut ovectorin g. When
a USB interrupt is asse rted, the FX2 pushes the program counter onto its stack then jumps to addres s 0x0043, where it expects
to find a “jump” instruction to the USB Interrupt service routine.

The FX2 jump instruction is encoded as follows.

Table 3-3. INT2 USB Interrupts

USB INTERRUPT TABLE FOR INT2

Priority INT2VEC Value Source Notes

1 00 SUDAV SETUP Data Available
2 04 SOF Start of Frame (or microframe)
3 08 SUTOK Setup Token Received
4 0C SUSPEND USB Suspend request
5 10 USB RESET Bus reset
6 14 HISPEED Entered high speed operation
7 18 EP0ACK FX2 ACK’d the CONTROL Handshake
8 1C reserved

9 20 EP0-IN EP0-IN ready to be loaded with data
10 24 EP0-OUT EP0-OUT has USB data
11 28 EP1-IN EP1-IN ready to be loaded with data
12 2C EP1-OUT EP1-OUT has USB data
13 30 EP2 IN: buffer available. OUT: buffer has data
14 34 EP4 IN: buffer available. OUT: buffer has data
15 38 EP6 IN: buffer available. OUT: buffer has data
16 3C EP8 IN: buffer available. OUT: buffer has data
17 40 IBN IN-Bulk-NAK (any IN endpoint)
18 44 reserved
19 48 EP0PING EP0 OUT was Pinged and it NAK’d
20 4C EP1PING EP1 OUT was Pinged and it NAK’d
21 50 EP2PING EP2 OUT was Pinged and it NAK’d
22 54 EP4PING EP4 OUT was Pinged and it NAK’d
23 58 EP6PING EP6 OUT was Pinged and it NAK’d
24 5C EP8PING EP8 OUT was Pinged and it NAK’d
25 60 ERRLIMIT Bus errors exceeded the programmed limit
26 64 reserved
27 68 reserved
28 6C reserved
29 70 EP2ISOERR ISO EP2 OUT PID sequence error
30 74 EP4ISOERR ISO EP4 OUT PID sequence error
31 78 EP6ISOERR ISO EP6 OUT PID sequence error
32 7C EP8ISOERR ISO EP8 OUT PID sequence error

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CY7C68013

If Autovectoring is enabled (AV2EN = 1 in the INTSETUP register), the FX2 substitutes its INT2VEC byte. Therefore, if the high
byte (“page”) of a jump-table address is preloaded at location 0x0044, the automatically-inserted INT2VEC byte at 0x0045 will
direct the jump to the correct address out of the 27 addresses within the page.

3.8.3 FIFO/GPIF Interrupt (INT4)

Just as the USB Interrupt is shared among 27 individual USB-interrupt sources, the FIFO/GPIF interrupt is shared among 14
individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, like the USB Interrupt, can employ autovectoring. Table 3-4 shows the
priority and INT4VEC values for the 14 FIFO/GPIF interrupt sources

Table 3-4. Individual FIFO/GPIF Interrupt Sources

Priority INT4VEC Value Source Notes

1 80 EP2PF Endpoint 2 Programmable Flag
2 84 EP4PF Endpoint 4 Programmable Flag
3 88 EP6PF Endpoint 6 Programmable Flag
4 8C EP8PF Endpoint 8 Programmable Flag
5 90 EP2EF Endpoint 2 Empty Flag
6 94 EP4EF Endpoint 4 Empty Flag
7 98 EP6EF Endpoint 6 Empty Flag
8 9C EP8EF Endpoint 8 Empty Flag

9 A0 EP2FF Endpoint 2 Full Flag
10 A4 EP4FF Endpoint 4 Full Flag
11 A8 EP6FF Endpoint 6 Full Flag
12 AC EP8FF Endpoint 8 Full Flag
13 B0 GPIFDONE GPIF Operation Complete
14 B4 GPIFWF GPIF Waveform

If Autovectoring is enabled (AV4EN = 1 in the INTSETUP register), the FX2 substitutes its INT4VEC byte. Therefore, if the high
byte (“page”) of a jump-table address is preloaded at location 0x0054, the automatically-inserted INT4VEC byte at 0x0055 will
direct the jump to the correct address out of the 14 address es within the page . When the ISR occurs, the FX2 p ushes the program
counter onto its stack then jumps to address 0x0053, where it expects to find a “jump” instruction to the ISR Interrupt service
routine.

3.9 Reset and Wakeup

3.9.1 Reset Pin

An input pin (RESET#) reset s th e chi p. This pin has h ysteresi s and is a ctive LO W. The internal PLL stabil izes approxim ately 200
µs after V

3.9.2 Wakeup Pins

The 8051 puts itself and the rest of the chip into a power-down mode by setting PCON.0 = 1. This stops the oscillator and PLL.
When WAKEUP is asserted by e xternal logic , the osc illator res tarts and after th e PLL stabi lizes, a nd the 8051 receives a wak eup
interrupt. This applies whether or not FX2 is connected to the USB.

The FX2 exits the power down (USB suspend) state using one of the following methods:

• USB bus signals resume

• External logic asserts the WAKEUP pin

• External logic asserts the PA3/WU2 pi n.

The second wakeup pin, WU2, can also be configured as a general purpose I/O pin. This allows a simple external R-C network
to be used as a periodic wakeup source.

has reached 3.3V. Typically, an external RC network (R = 100k, C = 0.1 µF) is used to provide the RESET# signal.

CC

3.10 Program/Data RAM

3.10.1 Size

The FX2 has eight kbytes of internal program/data RAM, where PSEN#/RD# signals are internally ORed to allow the 8051 to
access it as both program and data memory. No USB control registers appear in this space.

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CY7C68013

Two memory maps are shown in the following diagrams:

Figure 3-1 Internal Code Memory, EA = 0
Figure 3-2 External Code Memory, EA = 1.

3.10.2 Internal Code Memory, EA = 0

This mode implement s the in tern al ei ght-kbyte block of RAM (starting at 0) as combined code and data memory. When external
RAM or ROM is added, the external read and write strobes are suppressed for memory spaces that exist inside the chip. This
allows the user to connect a 64-kbyte memory without requiring address decodes to keep clear of internal memory spaces.

Only the internal eight kbytes and scratch pad 0.5 kbytes R AM spaces have the following access:

• USB download

• USB upload

• Setup data pointer

2

• I

C-compatible interface boot load.

Inside FX2 Outside FX2

FFFF

E200
E1FF

0.5 kbytes RAM

Data (RD#,WR#)*

E000

7.5 kbytes
US B regs and
4k EP buffers
(RD#,WR#)

(OK to populate
data memory
here—RD#/WR#
strobes are not
active)

48 kbytes
External
Data
Memory
(RD#,WR#)

56 kbytes
External
Code
Memory
(PSEN#)

1FFF

Eight kbytes RAM
Code and Data
(PSEN#,RD#,WR#)*

0000

(Ok to populate
data memory
here—RD#/WR#
strobes are not
active)

Data Code

(OK to populate
program
memory here—
PSEN# strobe
is not active)

*SUDPTR, USB upload/download, I2C-compatible interface boot access

Figure 3-1. Internal Code Memory, EA = 0

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CY7C68013

3.10.3 External Code Memory, EA = 1

The bottom eight k bytes of pr ogram me mory is exte rnal, and th erefore the bottom ei ght kbytes of int ernal RAM is access ible onl y
as data memory.

Inside FX2 Outside FX2

FFFF

E200
E1FF

0.5 kbytes RAM

Data (RD#,WR#)*

E000

1FFF

7.5 kbytes
USB regs and
4k EP buffers
(RD#,WR#)

(OK to populate
data memory
here—RD#/WR#
strobes are not
active)

48 kbytes
External
Data
Memory
(RD#,WR#)

64 kbytes
External
Code
Memory
(PSEN#)

(Ok to populate
data memory
here—RD#/WR#
strobes are not
active)

Data Code

0000

Eight kbytes
RAM
Data
(RD#,WR#)*

*SUDPTR, USB upload/download, I2C-compatible interface boot access

Figure 3-2. External Code Memory, EA = 1

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3.11 Register Addresses

FFFF

4 kbytes EP2-EP8 buffers

F000
EFFF

2 kbytes RESERVED

E800
E7FF

E7C0
E7BF

E780
E77F

E740
E73F

E700
E6FF

E600
E5FF

E480
E47F

E400
E3FF

E200
E1FF

E000

64 bytes EP1IN

64 bytes EP1OUT

64 bytes EP0 IN/OUT

64 bytes RESERVED

256 bytes Registers

384 bytes RESERVED

128 bytes GPIF Waveforms

512 bytes RESERVED

(8 × 512)

512 bytes

8051 xdata RAM

CY7C68013

3.12 Endpoint RAM

3.12.1 Size

• 3 × 64 bytes (Endpoints 0 and 1)

• 8 × 512 bytes (Endpoints 2, 4, 6, 8)

3.12.2 Organization

• EP0 Bidirectional endpoint zero, 64-byte buffer

• EP1IN, EP1OUT 64-byte buffers, bulk or interrupt

• EP2,4,6,8 Eight 512-byte buffers, bulk, interrupt, or isochronous. EP2 and 6 can be either double, triple, or quad

3.12.3 Setup Data Buffer

A separate eight-byte buffer at 0xE6B8-0xE6BF holds the SETUP data from a CONTROL transfer.

buffered. For high-speed endpoint configuration options, see Figure 3-3.

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3.12.4 Endpoint Configurations (High-speed Mode)

EP0 IN&OUT

EP1 IN

EP1 OUT

64
64
64

64
64
64

CY7C68013

64
64
64

64
64
64

64
64
64

64
64
64

EP2

EP4

EP6

EP8

512

512

512

512

512

512

512

512

512

512

EP2 EP2

512

512

512

512

EP6 EP6

512

512

1024

1024

1024

1024

512

512

EP2

512

512

EP6

512

512

512

EP8 EP8

512

EP2

1024

1024

1024

512

512

1024

1024

EP2

1024

1024

Figure 3-3. Endpoint Configuration

Endpoints 0 an d 1 are the same for every co nfigurat ion. Endpo int 0 is t he only CO NTROL endp oint, and endpoi nt 1 can be e ither
BULK or INTERRUPT. T o the left of the vertical line, the user may pick different configurations for EP2&4 and EP6&8, since none
of the 512-byte buffers are combined between these endpoint groups. An example endpoint configuration would be:

EP2—1024 double buffered; EP6—512 quad buffered.
To the right of the vertical line, buffers are shared between EP2–8, and therefore only entire columns may be chosen.

3.12.5 Default Full-Speed Alternate Settings
Table 3-5. Default Full-Speed Alternate Settings

[1, 2]

Alternate Setting 0 1 2 3

ep0 64 64 64 64
ep1out 0 64 bulk 64 int 64 int
ep1in 0 64 bulk 64 int 64 int
ep2 0 64 bulk out (2×) 64 int out (2×) 64 iso out (2×)
ep4 0 64 bulk out (2×) 64 bulk out (2×) 64 bulk out (2×)
ep6 0 64 bulk in (2×) 64 int in (2×)64 iso in (2×)
ep8 0 64 bulk in (2×) 64 bulk in (2×) 64 bulk in (2×)

Notes:

1. “0” means “not implemented.”

2. “2x” means “double buf fered.”

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CY7C68013

3.12.6 Default High-Speed Alternate Settings
Table 3-6. Default High-Speed Alternate Settings

[1, 2]

Alternate Setting 0 1 2 3

ep0 64646464
ep1out 0 512 bulk
ep1in 0 512 bulk

[3]
[3]

64 int 64 int

64 int 64 int
ep2 0 512 bulk out (2×) 512 int out (2×) 512 iso out (2×)
ep4 0 512 bulk out (2×) 512 bulk out (2×) 512 bulk out (2×)
ep6 0 512 bulk in (2×) 512 int in (2×) 512 iso in (2×)
ep8 0 512 bulk in (2×) 512 bulk in (2×) 512 bulk in (2×)

Note:

3. Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1.

3.13 External FIF O inte rface

3.13.1 Architecture

The FX2 slave FIFO architecture has eight 512-byte blocks in the endpoint RAM that directly serve as FIFO memories, and are
controlled by FIFO control signals (such as IFCLK, SLCS#, SLRD, SLWR, SLOE, PKTEND, and flags).

In operation, some of the eight RAM blocks fill or empty from the SIE, while the others are connected to the I/O transfer logic.
The transfer logic takes two forms, the GPIF for internally generated control signals, or the slave FIFO interface for externally
controlled transfers.

3.13.2 Master/Slave Control Signals

The FX2 endpoint FIFOS are impleme nte d as eig ht phy sic all y dis tin ct 256x16 RAM blocks. The 8051/SIE can switch any of the
RAM blocks betwee n tw o dom ai ns , th e USB (SIE) domain and the 8051-I/O Unit doma in. This switching is done virtually inst a n­taneously, giving essentially zero transfer time between “USB FIFOS” and “Slave FIFOS.” Since they are physically the same
memory, no bytes are actually transferred between buffers.

At any given time, some RAM blocks are fi lling/ emp tying with USB dat a unde r SIE control, whi le other RA M blocks are avail able
to the 8051 and/or t he I /O control unit. The RAM blocks operate as s in gle -po rt in the USB domain, and dual-port in the 805 1-I/O
domain. The blocks can be configured as single, double, triple, or quad buffered as previously shown.

The I/O control unit implements either an internal-master (M for master) or external-master (S for Slave) interface.
In Master (M) mode, the GPIF internally control s FIFOADR[1 ..0] to select a FIFO. The RDY pins (two in the 56-pin pa ckag e, si x

in the 100-pin and 128-pin packages) can be used as flag inputs from an external FIFO or other logic if desired. The GPIF can
be run from either an internally derived clock or externally supplied clock (IFCLK), at a rate that transfers data up to 96
Megabytes/s (48 MHz).

In Slave (S) mode, the FX2 accepts either an internally derived clock or externally supplied clock (IFCLK, max. frequency 48
MHz) and SLCS#, SL RD, SL WR, SL OE, PKTEND signal s from exte rnal logic. Each endpoint ca n individu ally be selec ted for byte
or word operation by an internal configuration bit, and a Slave FIFO Output Enable signal SLOE enables data of the selected
width. External logic must insure that the output enable signal is inactive when writing data to a slave FIFO. The slave interface
can also operate asynchronously, where the SLRD and SLWR signals act directly as strobes, rather than a clock qualifier as in
synchronous mode. The signals SLRD, SLWR, SLOE and PKTEND are gated by the signal SLCS#.

3.13.3 GPIF and FIFO Clock Rates

An 8051 register bit se lec t s one of two frequencies for the internally suppli ed i nte rfac e c lo ck: 30 MHz and 48 MHz. Alternatively,
an externally supp lied clock of 5 M Hz – 48 MHz feedin g the IFCLK pin can b e used as the inte rface clock. IFCLK can be configured
to function as an output clock when the GPIF and FIFOs are internally clocked. An output enable bit in the IFCONFIG register
turns this clock output off, if desired. Another bit within the IFCONFIG register will invert the IFCLK signal whether internally or
externally sourced.

3.14 GPIF

The GPIF is a flex ible 8- or 16-bit p arallel i nterface d riven by a user-prog rammabl e finite s tate m achine. It allows the CY7C68 013
to perform local bus mastering, and can implement a wide variety of protocols such as ATA interface, printer parallel port, and
Utopia.

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