Cypress Semiconductor CY7C1399-20VCT, CY7C1399-20VC, CY7C1399-15ZCT, CY7C1399-15ZC, CY7C1399-15VCT Datasheet

32K x 8 3.3V Static RAM

CY7C1399

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
March 25

,

1999

Features

• Single 3.3V power supply

• Ideal for low-voltage cache memory applications

• High speed
—12/15 ns

• Low active power
—255 mW (max.)

• Low CMOS standby power (L)

—

180 µW (max.), f=f

MAX

• 2.0V data retention (L)

—

40 µW

• Low-power alpha immune 6T cell

• Plastic SOJ and TSOP packaging

Functional Description

The CY7C1399 is a high- performance 3.3V CMOS Sta tic RAM
organized as 3 2,768 w ords by 8 bi ts. Easy m emory e xpans ion

is provided by an active LOW Chip Enable (CE

) and active

LOW Output Enable (OE

) and three-state drivers. The device
has an automatic power-down feature, reducing the power
consumption by more than 95% when deselected.

An active LOW Write Enable signal (WE

) contro ls th e w r iting/

reading operation of the memory. When CE

and WE inputs

are both LOW, data on the eight data input/output pins (I/O

0

through I/O7) is written i nto the m emory locat ion a ddre ssed b y
the address present on the address pins (A

0

through A14).
Reading the device is accomplished by selecting the device
and enabling the outputs, CE

and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con­tents of the location addressed by the information on address
pins is present on the eight data input/output pins.

The input/out put pins rem ain in a high- impedance s tate unless
the chip is selected, outputs are enabled, and Write Enable
(WE

) is HIGH. The CY7C1399 is available in 28-pin standard

300-mil-wide SOJ and TSOP Type I packages.

Logic Block Diagram

Pin Configurations

C1399–1

C1399–2

1
2
3
4
5
6
7
8
9
10
11

14

15

16

20
19
18
17

21

24
23
22

Top View

SOJ

12
13

25

28
27
26

GND

A

6

A

7

A

8

A

9

A

10

A

11

A

12

A

13

WE

V

CC

A

4

A

3

A

2

A

1

I/O

7

I/O

6

I/O

5

I/O

4

A

14

A

5

I/O

0

I/O

1

I/O

2

CE

OE
A

0

I/O

3

A

1

A

2

A

3

A

4

A

5

A

6

A

7

A

8

COLUMN

DECODER

ROW DECODER

SENSE AMPS

INPUT BUFFER

POWER

DOWN

WE

OE

I/O

0

CE

I/O

1

I/O

2

I/O

3

32K x 8
ARRAY

I/O

7

I/O

6

I/O

5

I/O

4

A

9

A

0

A

11A13A12

A

14

A

10

Selection Guide

7C1399–12 7C1399–15 7C1399–20 7C1399–25 7C1399–35

Maximum Access Time (ns) 12 15 20 25 35
Maximum Operating Current (mA) 60 55 50 45 40
Maximum CMOS Standby Cur rent (µA) 500 500 500 500 500
Maximum CMOS Standby Cur rent (µA) L50 50 50 50 50

CY7C1399

2

Maximum Ratings

(Above whic h the useful lif e ma y be impai red. F or user gui de­lines, not tested.)

Storage Temperature ........................ .........–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on V

CC

to Relative GND

[1]

....–0.5V to +4.6V

DC V oltage Applied to Outputs
in High Z State

[1]

....................................–0.5V to VCC + 0.5V

DC Input Voltage

[1]

.................................–0.5V to VCC + 0.5V

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage .......... .............................. .. >2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current.............................. ................... .. . >200 mA

Pin Configuration

22
23
24
25
26

27
28
1
2

5

10

11

15
14
13
12

16

19
18
17

Top View

TSOP

3
4

20

21

7

6

8

9

OE

A

1

A

2

A

3

A

4

WE

V

CC

A

5

A

6

A

7

A

8

A

9

A

0

CE
I/O

7

I/O

6

I/O

5

GND
I/O

2

I/O

1

I/O

4

I/O

0

A

14

A

10

A

11

A

13

A

12

C1399–3

I/O

3

Operating Range

Range

Ambient

Temperature

V

CC

Commercial 0°C to +70°C 3.3V ±300 mV
Industrial –40°C to +85°C 3.3V ±300 mV

Electrical Characteristics

Over the Ope rating Range

[1]

7C1399–12 7C1399–15 7C1399–20

Parameter Description Test Conditions Min. Max. Min. Max. Min. Max. Unit

V

OH

Output HIGH Voltage VCC = Min., IOH = –2.0 mA 2.4 2.4 2.4 V

V

OL

Output LOW Voltage VCC = Min., IOL = 4.0 mA 0.4 0.4 0.4 V

V

IH

Input HIGH Voltage 2.2 V

CC

+0.3V

2.2 V

CC

+0.3V

2.2 V

CC

+0.3V

V

V

IL

Input LOW Voltage –0.3 0.8 –0.3 0.8 –0.3 0.8 V

I

IX

Input Load Current –1 +1 –1 +1 –1 +1

µA

I

OZ

Output Leakage
Current

GND ≤ VI ≤ VCC,
Output Disabled

–5 +5 –5 +5 –5 +5

µA

I

OS

Output Short
Circuit Current

[2]

VCC = Max., V

OUT

= GND –300 –300 –300 mA

I

CC

VCC Operating

Supply Current

VCC = Max., I

OUT

= 0 mA,

f = f

MAX

= 1/t

RC

60 55 50 mA

I

SB1

Automatic CE Power-Down

Current — TTL Inputs

Max. VCC, CE ≥ VIH,
V

IN

≥ VIH, or V

IN

≤ V

IL

,f = f

MAX

5 5 5 mA

L3 3 3

I

SB2

Automatic CE Power-Down

Current — CMOS Inputs

[3]

Max. VCC, CE ≥ V

CC

– 0.3V , VIN ≥

V

CC

– 0.3V, or VIN ≤ 0. 3V,

WE ≥V

CC

– 0.3V or WE ≤0.3V ,

f=f

MAX

500 500 500

µA

L50 50 50

Notes:

1. Minimum voltage is equal to –2.0V for pulse durations of less than 20 ns.

2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.

3. Device draws low standby current regardless of switching on the addresses.

CY7C1399

3

Electrical Characteristics

Over the Operating Range(continued)

7C1399–25 7C1399–35

Parameter Description Test Conditions Min. Max. Min. Max. Unit

V

OH

Outp ut HIGH Voltage VCC = Min., IOH = –2.0 mA 2.4 2.4 V

V

OL

Output LOW Voltage VCC = Min., IOL = 4.0 mA 0.4 0.4 V

V

IH

Input HIGH Voltage 2.2 V

CC

+0.3V

2.2 V

CC

+0.3V

V

V

IL

Input LOW Voltage –0.3 0.8 –0.3 0.8 V

I

IX

Input Load Current –1 +1 –1 +1

µA

I

OZ

Output Leakage Current GND ≤ VI ≤ VCC,

Output Disabled

–5 +5 –5 +5

µA

I

OS

Output Short Circuit
Current

[2]

VCC = Max., V

OUT

= GND –300 –300 mA

I

CC

VCC Operating
Supply Current

VCC = Max., I

OUT

= 0 mA,

f = f

MAX

= 1/t

RC

45 40 mA

I

SB1

Automa tic CE P ower -Down
Current — TTL Inputs

Max. VCC, CE ≥ VIH,
V

IN

≥ VIH, or V

IN

≤ V

IL

,

f = f

MAX

5 5 mA

L 3 3 mA

I

SB2

Automa tic CE P ower -Down
Current — CMOS Inputs

[3]

Max. VCC, CE ≥ VCC–0.3V , VIN ≥
V

CC

– 0.3V, or VIN ≤ 0.3V,

WE≥V

CC

–0.3V or WE≤ 0.3V,

f=f

MAX

500 500

µA

L 50 50

µA

Capacitance

[4]

Parameter Description Test Conditions Max. Unit

CIN: Addresses Input Capacitance TA = 25°C, f = 1 MHz, VCC = 3.3V 5 pF
CIN: Controls 6 pF
C

OUT

Output Capacitance 6 pF

AC Test Loads and Waveforms

Note:

4. T ested initially and after any design or process changes that may affect these parameters.

3.0V

3.3V

OUTPUT

R1 317

Ω

R2
351

Ω

C

L

INCLUDING

JIG AND

SCOPE

GND

90%

10%

90%

10%

≤

3ns

≤

3

ns

OUTPUT 1.73V

Equivalent t o: THÉVENIN EQ UIVALENT

ALL INPUT PULSES

C1399–4

167

Ω