Cypress Semiconductor CY7C1041BL-17ZC, CY7C1041BL-17VC, CY7C1041BL-15ZC, CY7C1041BL-15VC, CY7C1041B-25ZI Datasheet
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1CY7C1041B
CY7C1041B
256K x 16 Static RAM
Features
written into the location specified on the address pins (A
through A17). If Byte High Enable (BHE) is LOW, then data
• High speed
—tAA = 12 ns
• Low active power
—1540 mW (max.)
• Low CMOS standby power (L version)
—2.75 mW (max.)
• 2.0V Data Retention (400 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE
and OE features
Functional Description
The CY7C1041B is a high-perf ormance CMOS st atic RAM organized as 262,144 words by 16 bits.
Writing to the device is accomplished by taking Chip Enable
) and Write Enable (WE) inputs L OW. If Byte Low Enable
(CE
) is LOW, then data from I/O pins (I/O0 through I/O7), is
(BLE
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A
through A17).
0
Reading fr om th e device is accom pli shed by tak ing Chip E nable (CE
Enable (WE
) and Output Enable (OE) LOW while forcing the Wri te
) HIGH. I f Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O
then data from memory will appear on I/O
to I/O7. If Byte High Enable (BHE) is LOW,
0
truth table at the bac k of this data sheet f or a complete description of read and write modes.
The input/output pins (I/O
high-impedance state when the device is deselected (CE
through I/O15) are placed in a
0
HIGH), the outputs are disab led (OE HIGH), the BHE and BLE
are disable d (BHE, BLE HIGH), or du ring a write operation (CE
LOW, and WE LOW).
The CY7C1041B is available in a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout.
Logic Block Diagram Pin Configuration
A
A
A
A
A
CC
SS
A
A
A
A
A
0
1
2
3
4
0
1
2
3
4
5
6
7
5
6
7
8
9
SOJ
TSOP II
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
A
A
ROW DECODER
6
7
8
256K x 16
ARRAY
1024 x 4096
SENSE AMPS
I/O0 – I/O
I/O8 – I/O
7
15
CE
I/O
I/O
I/O
I/O
V
COLUMN
DECODER
V
I/O
I/O
11
14
15
12
A13A
AAA
16
17
A
BHE
WE
CE
OE
9
10
A
A
A
I/O
I/O
WE
BLE
1041B–1
to I/O15. See the
8
A
17
A
16
A
15
OE
BHE
BLE
I/O
15
I/O
14
I/O
13
I/O
12
V
SS
V
CC
I/O
11
I/O
10
I/O
9
I/O
8
NC
A
14
A
13
A
12
A
11
A
10
1041B–2
0
Selection Guide
7C1041B-12 7C1041B-15 7C1041B-17 7C1041B-20 7C1041B-25
Maximum Access Time (ns) 12 15 17 20 25
Maximum Operating Current (mA) Com’l 200 190 180 170 160
Ind’l 220 210 200 190 180
Maximum CMOS Standby Current
(mA)
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Com’l 3 3 3 3 3
Com’l L- 0.5 0.5 0.5 0.5
Ind’l - 6 6 6 6
March 23, 2001
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature –65°C to +150°C
Ambient Temperature with
Po wer Applied–55°C to +125°C
Supply Voltage on V
DC Voltage Applied to Outputs
in High Z State
[1]
to Relative GND
CC
–0.5V to VCC + 0.5V
[1]
–0.5V to +7.0V
CY7C1041B
[1]
DC Input Voltage
Current into Outputs (LOW)20 mA
Operating Range
Range
Commercial 0°C to +70°C 5V ± 0.5
Industrial –40°C to +85°C
–0.5V to VCC + 0.5V
Ambient
Temperature
[2]
V
CC
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Notes:
1. V
2. T
A
Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 2.4 V
Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 0.4 V
Input HIGH Voltage 2.2 V
Input LOW Voltage
Input Load Current GND < VI < V
Output Leakage
Current
VCC Operating
Supply Current
Automatic CE
Power-Down Current
—TTL Inputs
Automatic CE
Power-Down Current
—CMOS Inputs
(min.) = –2.0V for pulse dur ations of le ss than 20 ns.
IL
is the case temper atur e.
[1]
GND < V
Output Disabled
VCC = Max.,
f = f
MAX
Max. VCC, CE > V
VIN > VIH or
VIN < VIL, f = f
Max. V
CC
> VCC – 0.3V,
CE
> VCC – 0.3V,
V
IN
or VIN < 0.3V, f = 0
OUT
= 1/t
,
CC
< VCC,
RC
MAX
Com’l 200 190 180 mA
Ind’l 220 210 200 mA
IH
Com’l 3 3 3 mA
Com’l L - 0.5 0.5 mA
Ind’l - 6 6 mA
7C1041B-12 7C1041B-15 7C1041B-17
Min. Max. Min. Max. Min. Max. Unit
CC
+ 0.5
2.2 V
CC
+ 0.5
2.2 V
CC
+ 0.5
V
–0.5 0.8 –0.5 0.8 –0.5 0.8 V
–1 +1 –1 +1 –1 +1 µA
–1 +1 –1 +1 –1 +1 µA
40 40 40 mA
2
CY7C1041B
Electrical Characteristics
Over the Operating Range (continued)
Test Conditions 7C1041B-20 7C1041B-25
Parameter Description Min. Max. Min. Max. Unit
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Capacitance
Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V
Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 V
Input HIGH Voltage 2.2 V
Input LOW Voltage
Input Load Current GND < VI < V
Output Leakage
Current
VCC Operating
Supply Current
Automatic CE
Power-Down Current
—TTL Inputs
Automatic CE
Power-Down Current
—CMOS Inputs
[3]
[1]
GND < V
Output Disabled
VCC = Max.,
f = f
MAX
Max. VCC, CE > V
VIN > VIH or
VIN < VIL, f = f
Max. VCC,
CE > VCC – 0.3V,
> VCC – 0.3V,
V
IN
or V
OUT
= 1/t
RC
< 0.3V, f = 0
IN
CC
< VCC,
MAX
–0.5 0.8 –0.5 0.8 V
–1 +1 –1 +1 µA
–1 +1 –1 +1 µA
Com’l 170 160 mA
Ind’l 190 180 mA
IH
Com’l 3 3 mA
Com’l L 0.5 0.5 mA
Ind’l 6 6 mA
CC
+ 0.5
40 40 mA
2.2 VCC + 0.5 V
Parameter Description Test Conditions Max. Unit
C
IN
C
OUT
Input Capacitance TA = 25°C, f = 1 MHz,
I/O Capacitance 8 pF
VCC = 5.0V
8pF
AC Test Loads and Waveforms
ALL INPUT PULSES
90%
10%
30 pF
R1 481Ω
(a)
THÉ
167Ω
R2
255Ω
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
1.73V
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
Equivalent to: VENIN EQUIVALENT
OUTPUT
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
5 pF
R1 481Ω
(b)
R2
255Ω
1041B–3
3.0V
GND
≤ 3 ns ≤ 3
90%
10%
ns
1041B–4
3
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