Cypress Semiconductor CY7C1032-8JCT, CY7C1032-8JC, CY7C1032-10JCT, CY7C1032-10JC, CY7C1031-8JCT Datasheet
...
64K x 18 Synchronous
Cache RAM
CY7C1031
CY7C1032
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
November 30, 1999
Features
• Supports 66-MHz Pen tium® microproces sor cache systems with zero wait states
• 64K by 18 common I/O
• Fast clock-to-output times
—8.5 ns
• T wo-bit wraparound counter supporting Pentium microprocessor and 486 burst sequence (7C1031)
• T wo-bit wraparound counter supporting l inear burst sequence (7C1032)
• Separate processor and controller address strobes
• Synchronous self-timed write
• Direct interfac e with the pro cessor and e xte rnal cac he
controller
• Asynchr onous output enable
• I/Os capable of 3.3V operation
• JEDEC-standard pinout
• 52-pin PLCC packaging
Functional Description
The CY7C1031 and CY7C1032 are 64K by 18 synchronous
cache RAMs designed to interface with high-speed microprocessors with minimum glue logic. Maximum acces s delay f rom
clock rise is 8.5 ns. A 2-bit on-chip counter captures the first
address in a burst and increments the address automatically
for the r e st of the burst ac cess .
The CY7C1031 is designed for Intel ® P entium and i 486 CPUbased systems; its counter follows the burst sequence of the
Pentium a nd t he i486 pr ocessors . The CY7C103 2 is ar chit ect ed for pr oces sors wi th linea r b urst se quences . Bu rst ac cesses
can be initiated with the processor address strobe (ADSP
) or
the cache controller address strobe (ADSC
) inpu ts. A ddr ess
advancement is con trolled b y th e address adva ncement ( AD V
)
input.
A synchronous sel f-t imed wri te me chanism i s pro vided to sim -
plify the write interface. A synchronous chip select input and
an asynchronous output enable input provide easy control for
bank selection and output three-state contr ol.
Logic Block Diagram Pin Configuration
1031–1
Top View
PLCC
1031–2
18
16 14
14
2
2
16
99
99
18
CLK
TIMING
CONTROL
ADDR
REG
ADV
LOGIC
REGISTER
64K X 9
RAM ARRAY
64K X 9
RAM ARRAY
OE
1
7C1031
8
9
10
11
12
13
14
15
16
17
18
19
20
46
45
44
43
42
41
40
39
38
37
36
35
34
2122 23 24 25 26 27 28 29 30 31 32 33
765432 525150494847
AAA
A
CC
AAAAA
A
GND
A
CLK
CS
A
DQ
8
DQ
9
V
CCQ
V
SSQ
DQ
10
DQ
11
DQ
12
DQ
13
V
SSQ
V
CCQ
DQ
14
DQ
15
DP
1
A
7C1032
A
DP
0
DQ
7
DQ
6
V
CCQ
V
SSQ
DQ
5
DQ
4
DQ
3
DQ
2
V
SSQ
V
CCQ
DQ
1
DQ
0
A
OE
ADV
ADSP
ADSC
WL
WH
A15–A
0
DAT A
IN
ADSP
ADSC
WH
WL
WH
WL
DQ15–DQ
0
DP1–DP
0
A
0
1
ADV
CS
2
3
4
5
6
7
8910
151413
12
11
V
[1]
[1]
Selection G uide
7C1031–8
7C1032–8
7C1031–10
7C1032–10
7C1031–12
7C1032–12
Maximum Access Time (ns) 8.5 10 12
Maximum Operating Current (mA) Commercial 280 280 230
Intel and Pentium are trademarks of Intel Corporation.
Note:
1. DP
0
and DP1 are functionally equivalent to DQx.
CY7C1031
CY7C1032
2
Functional Description
(continued)
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are satisfied at clock rise: (1) CS
is LOW and (2) ADSP is LOW.
ADSP
-triggered write cycles are completed in two clock peri-
ods. The addres s at A
0
through A15 is loaded into the addr ess
register and address advancement logic and delivered to the
RAM core. The wri te signal i s ignored i n this c ycle because the
cache tag or other external logic uses this clock period to perform address comparisons or protection checks. If the write is
allowed to proceed, the write input to the CY7C1031 and
CY7C1032 will be pulled LOW before the next clock rise.
ADSP
is ignored if CS is HIGH.
If WH
, WL, or both ar e LOW at the next clock rise, informat ion
presented at DQ
0
–DQ15 and DP0–DP1 will be written into the
location s pecified b y th e address adv ancem ent l ogic. WL
con-
trols the writing of DQ
0
–DQ7 and DP0 while WH controls the
writing of DQ
8
–DQ15 and DP1. Because the CY7C1031 and
CY7C1032 are com m on-I/O devices, the out put enable signal
(OE
) must be deasserted before data from the CPU is deliv-
ered to DQ
0
–DQ15 and DP0–DP1. As a safety pr ecaution, the
appropriate data l ines are th ree-st at ed in the cy cl e where WH
,
WL
, or both are sampled LOW, regardless of the state of the
OE
input.
Single Write Accesses Initiated by ADSC
This write access i s ini tiated when the f ol lowi ng condi t ions ar e
satisfied at rising edge of the clock: (1) CS
is LOW, (2) ADSC
is LOW, and (3) WH or WL are LOW. ADSC-triggered accesses are completed in a single clock cycle.
The address at A
0
through A15 is loaded into the address register and address adv ancement l ogic and deliver ed to the RAM
core. Information presented at DQ
0
–DQ15 and DP0–DP1 will
be written into the location specified by the address advancement logic. Since the CY7C1 031 a nd the CY7C1032 are common-I/O dev ic es, t he outpu t en able signal (OE
) must be deasserted befor e data from t he c ache cont r oller i s d eliv ered to the
data and parity lines. As a safety precaution, the appropriate
data and parity lines are three-stated in the cycle where WH
and WL are sampled LOW regardless of the state of the OE
input.
Single Read Accesses
A single re ad access is ini ti ated when the following conditions
are satisfied at clock rise: (1) CS
is LOW, (2) ADSP or ADSC
is LOW, and (3) WH and WL are HIGH. The address at A
0
through A15 is stored int o the address advancement l ogic and
delivered to the RAM core. If the output enable (OE
) signal is
asserted (LOW), data will be available at the data outputs a
maximum of 8.5 ns after clock rise. ADSP
is ignored if CS is
HIGH.
Burst Sequences
The CY7C1031 provides a 2-bit wraparound counter, fed by
pins A
0–A1
, that implements the In tel 8048 6 and P enti um processor’s address burst sequence (see Table 1). Note that the
burst sequence depends on the first burst address.
The CY7C1032 provide s a two- bit wr aparound count er , fed by
pins A
0–A1
, that implements a linear address burst sequence (see
T abl e 2).
Application Example
Figure 1 sho ws a 512-K byte sec ondary cach e for the P enti um
microprocessor using four CY7C1031 cache RAMs.
T able 1. Counter Implementation for the Intel
Pentium/80486 Processor’s Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A
X + 1, Ax
A
X + 1, Ax
A
X + 1, Ax
A
X + 1, Ax
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
T able 2. Counter Implementation for a Linear Seque nce
First
Address
Second
Address
Third
Address
Fourth
Address
A
X + 1
, A
x
A
X + 1
, A
x
A
X + 1
, A
x
A
X + 1
, A
x
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
CY7C1031
CY7C1032
3
Figure 1. Cache Using Four CY7C1031s
PENTIUM
CLK
DAT A
ADR
66-MHz OSC
CACHE
CLK
DAT A
ADR
CLK
DAT A
ADR
MATCH
DIRTY
VALI D
MATCH
DIRTY
VALI D
CD
ADSP
ADSC ADV OE WH0,
WL
0
CACHE
CONTROLLER
CLK
DAT A
ADR
ADSP
ADSC
ADV
OE
WH, WL
512 KB
7C1031
INTERFACE TO
MAIN MEMORY
WH,WL
WH,WL
WH,WL
WH1,
WL
1
WH2,
WL
2
WH3,
WL
3
2 2 22
ADS
PROCESSOR
TAG
Pin Definitions
Signal Name Type # of Pins Description
V
CC
Input 1
+5V Power
V
CCQ
Input 4
+5V or 3.3V (Outputs)
GND Input 1 Ground
V
SSQ
Input 4 Ground (Outputs)
CLK Input 1 Clock
A15 – A
0
Input 16 Address
ADSP Input 1 Address Strobe from Processor
ADSC Input 1 Address Strobe from Cache Controller
WH Input 1 Write Enable – High Byte
WL Input 1 Wr ite Enable – Low Byte
ADV Input 1 Advance
OE Input 1 Output Enable
CS Input 1 Chip Select
DQ15–DQ
0
Input/Output 16 Regular Data
DP1–DP
0
Input/Output 2 Parity Data
CY7C1031
CY7C1032
4
Pin Descriptions
Signal Name I/O Description
Input Signals
CLK I Clock signal. It is used to capture th e address, the data to be written, and th e following con trol
signals: ADSP
, ADSC, CS , WH, WL, and ADV. It i s also used to advan ce t he on-ch ip aut o-a ddress-
increment logic (when the appropriate cont rol signals have been set).
A15–A
0
I Sixteen address lines used to select one of 64K locations . They are capt ured in an on-chi p register
on the rising edge of CLK if ADSP
or ADSC is LOW. The rising edge of the clock also loads the
lower tw o addr ess l ines, A
1–A0
, into the on- chi p auto- address- incr ement logi c if ADSP or ADSC is
LOW.
ADSP I Address strobe from processor. This signal is sampled at the rising edge of CLK. When this input
and/or ADSC
is asserted, A0–A15 will be captured i n the on-chi p address reg ister . It also allows th e
lower two addr ess bits to be loaded into the on-chip auto-address-increment logic. If both ADSP
and ADSC
are asserted at the rising edge of CLK, onl y ADSP will be recogni zed. The ADSP input
should be connected to the ADS
output of the processor. ADSP is ignored when CS is HIGH.
ADSC I Address strobe from cache controll er . This si gnal is sampl ed at the rising edge of CLK. When this
input and/o r ADSP
is asserted, A0–A15 will be captured in the on-chip addr ess register. It also allows
the lower two address bi ts to be loaded into the on-chip aut o-addres s-inc rement log ic. The ADSC
input should not be connected to the ADS
output of the processor.
WH I Write signal for the high-order half of the RAM arra y. This signal is sampled by the rising edge of
CLK. If WH
is sampled as LOW, i.e., asserted, the control logic will per form a self-timed write of
DQ
15
–DQ8 and DP1 from the on-chip data register into the selected RAM location. There is one
exception to thi s. If ADS P
, WH, and CS are asserted (LOW) at the risin g edge of CLK, the write
signal, WH
, is ignored . No te th a t AD S P h as no ef fect on WH if CS is HIGH.
WL I Write signal for the low-or der hal f of the RAM array. This signal is sampled by the risi ng edge of
CLK. If WL
is sampled as LOW, i.e., asserted, the control logic will per form a self-timed write of
DQ
7
–DQ0 and DP0 from the on-chip data regis ter into the selected RAM locat ion. There is one
exception to thi s. If ADS P
, WL, and CS are asserted (LOW) at the risi ng edge of CLK, the write
signal, WL
, is ignored. Note that ADSP has no effect on WL if CS is HIG H .
ADV I Advance. This signal is sampled by the rising edge of CLK. When it is asserted, it automatically
increments the 2-bit on-chip auto-address-increment counter. In the CY7C1032, the address will
be incremented linearl y. In the CY7C1031, the address will be incremented accordin g to th e Pentium/486 bu rst sequenc e. This signal is i gnored if ADSP
or ADSC is asserted concur rently with CS.
Note that ADSP
has no effect on ADV if CS is HIGH.
CS I Chip select. This signal is sampled by the rising edge of CLK. If CS is HIGH and ADSC is LOW,
the SRAM is deselected. If CS
is LOW and ADSC or ADSP is LO W, a new address is captured by
the address register. If CS
is HIGH, ADSP is ignored.
OE I Output enabl e. This signal is an as ynchrono us inpu t t hat co ntrol s the d irect ion of t he data I/O pins .
If OE
is asserted (LO W), the dat a pins a re output s, and the SRAM c an b e r ead (as long as CS was
asserted when it was sampl ed at the beginni ng of the cy cle). If OE
is deasserted (HIGH), the data
I/O pins will be three-stated, functioning as inputs, and the SRAM can be written.
Bidirectional Signals
DQ15–DQ
0
I/O Sixteen bidirect ional data I/O lines. DQ15–DQ8 are inputs to and outputs from the high-order hal f
of the RAM array, while DQ
7
–DQ0 are inputs to and outputs from the low-order half of the RAM
array. As inputs, they feed into an on-chip data register that is triggered by the ris ing edge of CLK.
As outputs, they carry the data read from the selected location in the RAM array. The direction of
the data pi ns is con trolled by OE
: when OE is HIGH, the data pins are thre e-stated and can be used
as inputs; when OE
is LOW, the data pins are driven by the outpu t buffers and ar e outputs.
DQ
15
–DQ8 and DQ7–DQ0 are also t hree-stated when WH and WL, respectively, is sampled LOW
at clock rise.
DP1–DP
0
I/O Two bidirectional data I/O l ines. These oper at e in e xac tly the sam e manner as DQ15–DQ0, but are
named differently because their primary purpose is to store parity bits, while the DQs’ primary
purpose is to store ordi nary dat a bits. DP
1
is an input to and an output from the high-order half of
the RAM array, while DP
0
is an input to and an output from the low er- order half of the RAM array.
CY7C1031
CY7C1032
5
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .......... .. ............ ...........–65
°
C to +150°C
Ambient Temperature with
Power Applied...............................................–55
°
C to +125°C
Supply Voltage on V
CC
Relative to GND..... .......... .–0.5V to +7.0V
DC V oltage Applied to Outputs
in High Z State
[2]
........ ........ ... .... ....... .... ... .... ......–0.5V to VCC + 0.5V
DC Input Voltage
[2]
........ ....... .... .... ....... ... .... .... ..–0.5V to VCC + 0.5V
Curre n t in to Out p ut s (L OW ).................................. ... .. .. 20 mA
Static Discharge Voltage ........... .............. ................. >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current............. .. ............ .. ....................... >200 mA
Operating Range
Range
Ambient
Temperature
[3]
V
CC
V
CCQ
Com’l 0°C to +70°C 5V ± 5% 3.0V to V
CC
Electrical Characteristics
Over the Operating Range
[4]
Parameter Description Test Conditions
7C1031-8
7C1032-8
7C1031-10
7C1032-10
7C1031-12
7C1032-12
UnitMin. Max. Min. Max. Min. Max.
V
OH
Output HIGH Voltage VCC = Min.,
I
OH
= –4.0 m A
2.4 V
CCQ
2.4 V
CCQ
2.4 V
CCQ
V
V
OL
Output LOW Voltage VCC = Min.,
I
OL
= 8.0 mA
0.4 0.4 0.4 V
V
IH
Input HIGH Voltage 2.2 VCC
+ 0.3V
2.2 VCC
+ 0.3V
2.2 VCC
+ 0.3V
V
V
IL
Input LOW Voltage
[2]
–0.3 0.8 –0.3 0.8 –0.3 0.8 V
I
X
Input Load Current GND ≤ VI ≤ V
CC
–11–11–11µA
I
OZ
Output Leakage
Current
GND ≤ VI ≤ V
CC,
Output Disabled
–55–55–55µA
I
OS
Output Short Circuit
Current
[5]
V
CC
= Max., V
OUT
= GND –300 –300 –300 mA
I
CC
V
CC
Operating
Supply Current
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
CYC
Com’l 280 280 230 mA
I
SB1
Autom a t i c C E
Power-Down
Current—TTL Inputs
Max. V
CC
, CS ≥
V
IH
, VIN ≥ VIH or
V
IN
≤ VIL, f = f
MAX
Com’l808060mA
I
SB2
Autom a t i c C E
Po wer-Down Current —
CMOS Inputs
Max. V
CC
, CS ≥
V
CC
– 0.3V , VIN ≥
V
CC
– 0.3V or VIN ≤
0.3V, f = 0
[6]
Com’l303030mA
Capacitance
[7]
Parameter Description Tes t Condi tions Max. Unit
C
IN
: Addr e s ses Input Capacitance TA = 25°C, f = 1 MHz,
V
CC
= 5.0V
Com’l4.5 pF
C
IN
: Other Inputs Com’l5 pF
C
OUT
Output Capacitance Com’l8 pF
Notes:
2. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.
3. T
A
is the case tem per ature.
4. See the last page for Group A subgroup testing information.
5. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
6. Inputs are disabled, clock is allowed to run at speed.
7. Tested initially and after any design or process changes that may affect these parameters.
CY7C1031
CY7C1032
6
AC Test Loads and Waveforms
3.0V
GND
90%
10%
90%
10%
≤
3ns
≤
3
ns
OUTPUT
R1
R2
5pF
INCLUDING
JIGAND
SCOPE
(a) (b)
ALL INPUT PULSES
1031–3
1031–4
OUTPUT
R
L
=50
Ω
Z
0
=50
Ω
V
L
=1.5V
V
CCQ
[8]
Switchin g C h ar acteristic s
Over the Operating Range
[9]
Parameter Description
7C1031-8
7C1032-8
7C1031-10
7C1032-10
7C1031-12
7C1032-12
Min. Max. Min. Max. Min. Max. Unit
t
CYC
Clock Cycle Time 15
[10]
20 20 ns
t
CH
Clock HIGH 5 8 8 ns
t
CL
Clock LOW 5 8 8 ns
t
AS
Address Set-Up Before CLK Rise 2.5 2.5 2.5 ns
t
AH
Address Hold After CLK Rise 0.5 0.5 0.5 ns
t
CDV
Data Ou tp u t Valid After CL K Rise 8.5 1 0 12 n s
t
DOH
Data Output Hold After CLK Rise 3 3 3 ns
t
ADS
ADSP, ADSC S e t-U p B efore CL K Rise 2.5 2.5 2 .5 n s
t
ADSH
ADSP, ADSC Hold After CLK Rise 0.5 0.5 0.5 ns
t
WES
WH, WL Set-Up Before CLK Rise 2.5 2.5 2.5 ns
t
WEH
WH, WL Hold After CLK Rise 0.5 0.5 0.5 ns
t
ADVS
ADV Set-Up Before CLK Rise 2.5 2.5 2.5 ns
t
ADVH
ADV Hold After CLK Ris e 0.5 0.5 0.5 ns
t
DS
Data Input Set-Up Bef ore CLK Rise 2.5 2.5 2.5 ns
t
DH
Data Input Hold After CLK Rise 0.5 0.5 0.5 ns
t
CSS
Chip Sel e ct Se t- U p 2.5 2.5 2.5 ns
t
CSH
Chip Select Hold After CLK Rise 0.5 0.5 0.5 ns
t
CSOZ
Chip Select Sampled to Output High Z
[11]
262627ns
t
EOZ
OE HIGH to Output High Z
[11]
262627ns
t
EOV
OE LOW to Output V alid 5 5 6 ns
t
WEOZ
WH or WL Sampled LO W to Output High Z
[11, 12]
567ns
t
WEOV
WH or WL Sampled HIGH to Output Valid
[12]
8.5 10 12 ns
Notes:
8. Resistor values for V
CCQ
= 5V are: R1 = 1179Ω and R2 = 868Ω. Resistor v alues f or V
CCQ
= 3.3V are R1 = 317Ω and R2 = 348Ω.
9. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V , input pulse levels of 0 to 3.0V, and output
loading of the specified I
OL/IOH
and load capacit ance. Sh own i n (a) a nd (b) of A C Test Loads.
10. Do not use the burst mode, if device operates at a frequency above 50 MHz.
11. t
CSOZ
, t
EOZ
, and t
WEOZ
are specified wit h a load capac itance of 5 pF as in part ( b) of A C Test Loads. Transition is measured ± 500 mV from steady-sta te v ol tage .
12. At any given voltage and temperature, t
WEOZ
min. is less than t
WEOV
min.
CY7C1031
CY7C1032
7
Switching Waveforms
Single Read
[13]
Singl e Write Timing: Write In itiate d by ADSP
Notes:
13. OE
is LOW thr oughout this oper at ion.
14. If ADSP is asserted while CS is HIGH, ADSP will be ignored.
15. ADSP has no eff ect on ADV, WL, and WH if CS is HI GH.
t
CL
t
AS
t
AH
t
ADS
t
ADSH
t
CH
t
CSS
t
CSH
t
WES
t
WEH
t
CDV
t
DOH
t
CYC
CLK
ADDRESS
ADSP
or
ADSC
WH,WL
DAT A OUT
1031–6
CS
[14]
[15]
1031–5
t
CL
t
AS
t
AH
t
ADS
t
ADSH
t
CH
t
CSS
t
CSH
t
WES
t
WEH
t
DS
t
DH
t
EOZ
CLK
ADDRESS
ADSP
DA TA IN
DAT A OUT
OE
CS
WH,WL
[15]
CY7C1031
CY7C1032
8
Singl e Write Timing: Write In itiate d by ADSC
Burst Read Sequence with Four Accesses
Switching Waveforms
(continued )
1031–7
t
CL
t
AS
t
AH
t
ADS
t
ADSH
t
CH
t
CSS
t
CSH
t
WES
t
WEH
t
DS
t
DH
t
EOZ
CLK
ADDRESS
ADSC
WH, WL
DA TA IN
DAT A OUT
OE
CS
t
WEH
t
ADVH
DAT A0 DA TA3DAT A2DA TA1
1031–8
OE
t
CSH
t
AS
t
AH
t
ADS
t
ADSH
t
ADVS
t
WES
t
CDV
t
DOH
CLK
ADDRESS
ADV
DAT A OUT
ADSP
or
ADSC
OE
CS
WH,WL
t
CSS
[14]
[15]
[15]
CY7C1031
CY7C1032
9
Output (Controlled by OE
)
Write Burst Timing: Write Initiated by ADSC
Switching Waveforms
(continued )
1031–9
t
EOV
OE
DA TA OUT
t
EOZ
1031–10
t
CSS
DA TA0 DA TA1 DA TA3
t
CSH
t
WES
t
WEH
DA TA2
t
ADStADSH
t
ADStADSH
t
AS
t
AH
t
DS
t
DH
CLK
CS
ADSP
WH
,WL
ADDR
OE
DA TA
ADSC
ADV
t
ADVStADVH
[14]
CY7C1031
CY7C1032
10
Write Burst Timing: Write Initiated by ADSP
Switching Waveforms
(continued )
t
ADSH
t
ADS
DA TA0
1031–11
t
CSStCSH
t
AS
t
AH
DAT A1 DA TA2 DATA3
t
ADVStADVH
t
DS
t
DH
CLK
CS
WH,
WL
OE
ADSC
ADSP
ADDR
ADV
DA TA
[15]
[14]
[15]
CY7C1031
CY7C1032
11
Output Timing (Contro ll ed by CS
)
Output Timing (Controlled by WH
/ WL)
Switching Waveforms
(continued )
t
CSStCSH
1031–12
t
CSS
t
CSH
t
CDV
t
CSOZ
CLK
CS
DAT A OUT
t
ADS
t
ADSH
t
ADStADSH
ADSC
t
ADS
t
ADS
1031–13
CLK
t
WEOZ
t
WEOV
WH, WL
DAT A OUT
t
WES
t
WEH
t
ADSH
t
ADSH
ADSCand
ADSP
Truth Table
Input
CS ADSP ADSC ADV WH or WL CLK Address Operation
H X L X X L→H N/A Chip deselected
H L H H H L→H Same address as
previous cycle
Read cycle (ADSP ignored)
H L H L H L→H Incremented burst
address
Read cycle, in bu rst sequence
(ADS P
ignored)
H L H H L L→H Same address as
previous cycle
Write cycle (ADSP ignored)
H L H L L L→H Incremented burst
address
Write cycle, in burst sequence
(ADS P
ignored)
L L X X X L→H External Read cycle, begin burst
L H L X H L→H External Read cycle, begin burst
L H L X L L→H External Write cycle, begin burst
X H H L L L→H Incremented burst
address
Write cycle, in burst sequence
X H H L H L→H Incremented burst
address
Read cycle, in bu rst sequence
X H H H L L→H Same address as
previous cycle
Write cycle
X H H H H L→H Same address as
previous cycle
Read cycle
CY7C1031
CY7C1032
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it con vey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Document #: 38–00219–C
Ordering Information
Speed
(ns) Ordering Code
Package
Name Packag e Type
Operating
Range
8 CY7C1031-8JC J69 52-Lead Plastic Leaded Chip Carrier Commercial
10 CY7C1031-10JC J69 52-Lead Plastic Leaded Chip Carrier Commercial
12 CY7C1031-12JC J69 52-Lead Plastic Leaded Chip Carrier Commercial
Speed
(ns) Ordering Code
Package
Name Packag e Type
Operating
Range
8 CY7C1032-8JC J69 52-Lead Plastic Leaded Chip Carrier Commercial
10 CY7C1032-10JC J69 52-Lead Plastic Leaded Chip Carrier Commercial
12 CY7C1032-12JC J69 52-Lead Plastic Leaded Chip Carrier Commercial
Package Diagrams
52-Lead Plastic Leaded Chip Carrier J69
51-85004-A
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