Cypress Semiconductor CY2292FI, CY2292F, CY2291FI, CY2291F Datasheet

CY2291
Three-PLL General Purpose
EPROM Programmable Clock Generator
Features Benefits Three integrated phase-locked loops EPROM programmability Factory-programmable (CY2291) or field-programmable
(CY2291F) device options Low-skew, low-jitter, high-accuracy outputs Power-management options (Shutdown, OE, Suspend) Frequency select option Smooth slewing on CPUCLK Configurable 3.3V or 5V operation 20-pin SOIC Package
Selector Guide
Part Number Outputs Input Frequency Range Output Frequency Range Specifics
CY2291 8 10 MHz–25 MHz (external crysta l)
1 MHz–30 MHz (reference clock)
CY2291I 8 10 MHz–25 MHz (external crysta l)
1 MHz–30 MHz (reference clock)
CY2291F 8 10 MHz–25 MHz (external crysta l)
1 MHz–30 MHz (reference clock)
CY2291FI 8 10 MHz–25 MHz (external crysta l)
1 MHz–30 MHz (reference clock)
Generates up to 3 custom fr equencies from external sources Easy customizati on and fast turnaround Programming support av ailable for all opportunities
Meets critical industry standard timing requirements Supports low-power applications 8 user-selectable frequencies on CPU PLL Allows downstream PLLs to stay locked on CPUCLK output Enables applic ation compatibil it y Industry-standard packaging saves on board space
76.923 kHz–100 MHz (5V)
76.923 kHz–80 MHz (3.3V)
76.923 kHz–90 MHz (5V)
76.923 kHz–66.6 MHz (3.3V)
76.923 kHz–90 MHz (5V)
76.923 kHz–66.6 MHz (3.3V)
76.923 kHz–80 MHz (5V)
76.923 kHz–60.0 MHz (3.3V)
Fac tory Prog rammable Commercial Temperature
Fac tory Prog rammable Industrial Temperature
Field Programmable
Commercial Temperature
Field Programmable
Industrial Temperature
Logic Block Diagram
32XIN 32XOUT XTALIN
XTALOUT
S0 S1
S2/SUSPEND
SHUTDOWN
OE
OSC.
OSC. XBUF
CPLL
(8 BIT)
UPLL
(10 BIT)
SPLL
(8 BIT)
/
/1,2,4
/1,2,4,8
/1,2,3,4,5,6 /8,10,12,13 /20,24,26,40 /48,52,96,104
/2,3,4
CONFIG EPROM
MUX
32K
CPUCLK
CLKA
CLKB
CLKC
CLKD
CLKF
Cypress Semiconductor Corporation
3901 North First Street San Jose CA 95134 408-943-2600 June 14, 2000, rev. **
CY2291
Pin Configurations
CY2291
20-pin SOIC
32K
CLKC
V
DD
GND
XBUF CLKD
1 2 3 4 5 6 7 8
9 10
20 19 18 17 16
15 14
13 12 11
32XIN V
BATT
SHUTDOWN
S2/SUSPEND V
DD
S1 S0
CLKF CLKA CLKB
/OE
32XOUT
XTALIN
XTALOUT
CPUCLK
Pin Summary
Name Pin Number Description
32XOUT 1 32.768 kHz crystal feedback. 32K 2 32.768 kHz output (always active if V CLKC 3 Configurable clock output C. V
DD
4, 16 Voltage supply. GND 5 G round. XTALIN XTALOUT
[1]
[1, 2]
6 Reference crystal input or external referen ce clock input.
7 Reference crystal feedbac k. XBUF 8 Buffered reference clock output. CLKD 9 Configurable clock output D. CPUCLK 10 CPU frequency clock output. CLKB 11 Configurable clock output B. CLKA 12 Configurable clock out put A. CLKF 13 Configurable clock output F. S0 14 CPU clock select input, bit 0. S1 15 CPU clock select input, bit 1. S2/SUSPEND 17 CPU clock selec t i nput, bit 2. Optionally enables suspend feature when LOW. SHUTDOWN/OE 18 Places outputs in three-state
places outputs in three-state
V
BATT
19 Battery supply for 32.768-kHz circuit.
[4]
condition and shuts do wn chip when LO W . Optionally, only
[4]
condition and does not shut down chip when LOW.
32XIN 20 32.768-kHz crystal input.
Notes:
1. For best accuracy, use a parallel-resonant crystal, C
2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to crystal).
3. Please refer to application note Understanding the CY2291, CY2292 and CY2295 for more information.
4. The CY2291 has weak pull-downs on all outputs (except 32K). Hence, when a three-state condition is forced on the outputs, the output pins are pulled LOW.
≈ 17 pF or 18 pF.
LOAD
is present).
BATT
[3]
2
CY2291
Operation
The CY2291 is a third-generation family of clock generators. The CY2291 is upwardl y compatible with the industry standard ICD2023 and ICD2028 and cont inue s the ir trad itio n by pro vid­ing a high level of customizable feat ures to meet the diverse clock generation needs of modern motherboards and other synchronous systems.
All parts provide a highly configurable set of clocks for PC motherboard applications. Each of the four configurable clock outputs (CLKA–CLKD) can be as si gned 1 of 3 0 freq uencies i n any combination. Multiple outputs configured for the same or
[3]
related providing on-chip buffering for heavily loaded signals.
The CY2291 can be config ured f or either 5V or 3.3 V operation. The internal ROM t abl es use EPROM techno log y, allowing ful l customization of output frequencies. The reference oscillator has been designed for 10-MHz to 25-MHz crystals, providing additional f le xi bility. No ext ernal componen ts are requir ed wit h this crystal. Alternatively, an external reference clock of fre­quency between 1 MHz and 30 MHz can be used. Customers using the 32-kHz oscil lator shoul d connect a 10-M resist or i n parallel with the 32-kHz crystal.
frequencies will have low (<500 ps) skew, in effect
Output Configuration
The CY2291 has five independ ent frequency sources on-c hip. These are the 32-kHz oscillator, the reference oscillator, and three Phase-Locked Loops (PLLs). Each PLL has a specific function. The System PLL (SPLL) driv es the CLKF output and provides fix e d outpu t frequen cies on the confi gur abl e outputs . The SPLL offers the most output frequency divider options. The CPU PLL (CPLL) is controlled by the select inputs (S0–S2) to provide eight user-selectable frequencies with smooth slewing between frequencies. The Utility PLL (UPLL) provides the most accurate cloc k. It is often used fo r misce lla­neous frequenci es not provi ded by the other freque ncy sourc­es.
All configurations are EPROM programmable , providing short sample and p roduction le ad times . Pl ease ref er to the appli ca­tion note Understanding the CY22 91, CY2292, and CY2295 for information on configuri ng the part.
Pow er Saving Featur es
The SHUTDOWN/OE input three-states the outputs when pulled LOW (the 32-kHz cloc k output is not affec ted). If syst em
shutdown is enabled, a LOW on this pin also shuts off the PLLs, co unters, the refer ence oscillat or, and all other active components. Th e r esult ing cu rr ent on the V than 50 µA (for Commercial Temp. or 100 µA for Industrial Temp.) plus 15 µA max. for the 32-kHz subsystem and is typ­ically 10 µA. After lea ving shutdown mode , the PLLs will have to re-lock. All outputs except 32K have a weak pull-down so that the outputs do not float when three-stated.
The S2/SUSPEND input can be configured to shut down a customizabl e set of output s and/ or PLLs , when LO W. All PLLs and any of the outputs e xcept 32K can be shut off in n early any combin a tion. Th e o n ly limita tio n is that if a PLL i s s hu t o ff, a l l outputs derived from it must also be shut off. Suspending a PLL shuts off all associated logic, while suspending an output simply for ces a three-state condi ti on.
The CPUCLK can slew (transition) smoot hly between 8 MHz and the maximum output frequency (100 MHz at 5V/80 MHz at 3.3V for Commercial Temp. parts or 90 M Hz at 5V/66. 6 MHz at 3.3V for Industrial Temp. and for field-programmed parts). This feature is extremely useful in “Green” PC and laptop ap­plications, where reducing the frequency of operation can re­sult in considerab le pow er savi ngs . This feat ure meets all 486 and Pent ium® processor slewing requirements .
[3]
pins will be less
DD
[4]
CyClocks™ Software
CyClocks is an ea sy-to- use applic ation that allo ws y ou to con ­figure any one o f the EPR OM pr ogra mmabl e c lock s offered by Cypress. You may spec ify t he inpu t fre quency, PLL and output frequencies, and differ ent functional options. Please note the output frequency ranges in this data sheet when specifying them in CyClocks to ensure that you stay within the limits. CyClocks also has a powe r calculat ion f eat ure that allo ws you to see the power consumption of your specific configuration. You can download a copy of CyClocks for free on Cypress’s website at www.cypress. com .
Cypress FTG Programmer
The Cypress Frequency Timing Generator (FTG) Program­mers is a portable programmer designed to custom program our family of EPROM Field Progr ammable Cloc k Devices . The FTG program mers conn ect to a PC s erial port and all ow users of CyClocks software to quickly and easily prog ram any of t he CY2291F, CY2292F, CY2071AF, and CY2907F devices. The ordering code for th e Cypress FTG Programmer is CY3670.
3
Maximum Ratings
CY2291
(Abov e which the useful lif e m ay be impaired. For user guide­lines, not tested.)
Suppl y Voltage............ ... ......... .......... .......... .. . –0.5V to +7.0V
DC Input Voltage............................................ –0.5V to +7.0V
Storage Temperature ............................. ....–65°C to +1 5 0°C
Operating Conditions
[5]
Max. Soldering T emperature (10 sec)..........................260°C
Junction Temperature...................................................150°C
Pack age Power Dissipation................................... ...750 mW
Static Discharge Voltage.............................................>
2000V
(per MIL-STD-883, Method 3015)
Parameter Description Part N umbers Min. Ma x. Unit
V V V T
C C f
REF
A
DD DD BATT
LOAD LOAD
Supply Voltage, 5.0V operation All 4.5 5.5 V Supply Voltage, 3.3V operation All 3.0 3.6 V Battery Backup Voltage All 2.0 5.5 V Commercial Operating Temperature, Ambient CY2291/CY2291F 0 +70 Industrial Operating Temperature, Ambient CY2291I/CY2291FI
40
+85 Max. Load Capacitance 5.0V Operation All 25 pF Max. Load Capacitance 3.3V Operation All 15 pF External Reference Crystal All 10.0 25.0 MHz External Referen ce Clock
[6, 7, 8 ]
All 1 30 MHz
Electrical Characteristics, Commercial 5.0V
Parameter Description Conditions Min. Typ. Max. Unit
V
OH
V
OL
V
OH–32
V
OL–32
V
IH
V
IL
I
IH
I
IL
I
OZ
I
DD
I
DDS
I
BATT
Notes:
5. Electrical parameters are guaranteed by design with these operating conditions, unless otherwise noted.
6. External input reference clock must have a duty cycle between 40% and 60%, measured at V
7. Please refer to application note Crystal Oscillator Topics for information on AC-coupling the external input reference clock.
8. The oscillator circuit is optimized for a crystal reference and for external reference clocks up to 20 MHz. For external reference clocks above 20 MHz, it is recommended that a 150Ω pull-up resistor to V
9. Xtal inputs have CMOS thresholds.
10. Load = Max., VIN = 0V or VDD, Typical (–104) configuration, CPUCLK = 66 MHz. Other configurations will vary. Power can be approximated by the following formula (multiply by 0.65 for 3V operation): IDD=10+0.06(F
HIGH-Level Output Voltage IOH = 4.0 mA 2.4 V LOW-Level Output Voltage IOL = 4.0 mA 0.4 V
32.768-kHz HIGH-Level Output Voltage
32.768-kHz LOW-Level
IOH = 0.5 mA V
BATT
0.5
IOL = 0.5 mA 0.4 V
Output Voltage HIGH-Level Input Voltage LOW-Level Input Voltage
[9]
Except crystal pins 2.0 V
[9]
Except crystal pins 0.8 V Input HIGH Current VIN = VDD–0.5V <1 10 Input LOW Current VIN = +0.5V <1 10 Output Leakage Current Three-state outputs 250 VDD Supply Current
[10]
VDD = VDD Max., 5V operati on 75 100 mA Commercial
VDD Powe r Supply Current in Shutdown Mode
V
Power Supply
BATT
Current
[10]
Shutdown active,
excluding V
V
BATT
be connected to the Xout pin.
DD
BATT
= 3.0V 5 15
CPLL+FUPLL
+2•F
CY2291/CY2291F 10 50
/2.
DD
)+0.27(F
SPLL
CLKA+FCLKB+FCLKC+FCLKD+FCPUCLK+FCLKF+FXBUF
).
°C °C
V
µA µA µA
µA
µA
4
CY2291
Electrical Characteristics, Commercial 3.3V
Parameter Description Conditions Min. Typ. Max. Unit
V
OH
V
OL
V
OH–32
V
OL–32
V
IH
V
IL
I
IH
I
IL
I
OZ
I
DD
I
DDS
I
BATT
HIGH-Level Output Voltage IOH = 4.0 mA 2.4 V LOW-Level Output Voltage IOL = 4.0 mA 0.4 V
32.768-kHz HIGH-Level Output Voltage
32.768-kHz LOW-Level
IOH = 0.5 mA V
BATT
0.5
IOL = 0.5 mA 0.4 V Output Voltage
HIGH-Level Input Voltage LOW-Level Input Voltage
[9]
Except crystal pins 2.0 V
[9]
Except crystal pins 0.8 V Input HIGH Current VIN = VDD–0.5V <1 10 µA Input LOW Current VIN = +0.5V <1 10 µA Output Leakage Current Three-state outputs 250 µA
[10]
[10]
= VDD Max., 3.3V operat ion 50 65 mA
V
DD
Shutdown active,
excluding V
V
BATT
BATT
= 3.0V 5 15 µA
CY2291/CY2291F 10 50 µA
VDD Supply Current Commercial
VDD Powe r Supply Current in Shutdown Mode
V
Power Supply
BATT
Current
V
Electrical Characteristics, Industrial 5.0V
Parameter Description Conditions Min. Typ. Max. Unit
V
OH
V
OL
V
OH–32
V
OL–32
V
IH
V
IL
I
IH
I
IL
I
OZ
I
DD
I
DDS
I
BATT
HIGH-Level Output Voltage IOH = 4.0 mA 2.4 V LOW-Level Output Voltage IOL = 4.0 mA 0.4 V
32.76 8 -kHz H I G H - Level Output Voltage
32.76 8 -kHz LOW- Leve l
IOH = 0.5 mA V
BATT
0.5
IOL = 0.5 mA 0.4 V
Output Voltage HIGH-Level Input Voltage LOW-Level Input Voltage
[9]
Except crystal pins 2.0 V
[9]
Except crystal pins 0.8 V Input HIGH Current VIN = VDD–0.5V < 1 10 µA Input LOW Current VIN = +0.5V < 1 10 µA Output Leakage Current Three-state output s 250 µA
[10]
[10]
= VDD Max., 5V operati on 75 110 mA
V
DD
Shutdown active,
excluding V
BATT
BATT
= 3.0V 5 15 µA
CY2291I/CY2291FI 10 100 µA
VDD Supply Current Industrial
VDD Po wer Supply Current in Shutdown Mode
V
Po wer Supply Current V
BATT
V
5
CY2291
Electrical Characteristics, Industrial 3.3V
Parameter Description Conditions Min. Typ. Max. Unit
V
OH
V
OL
V
OH–32
V
OL–32
V
IH
V
IL
I
IH
I
IL
I
OZ
I
DD
I
DDS
I
BATT
HIGH-Level Output Voltage IOH = 4.0 mA 2.4 V LOW-Level Output Voltage IOL = 4.0 mA 0.4 V
32.768-kHz HIGH-Level Output Voltage
32.768-kHz LOW-Level
IOH = 0.5 mA V
BATT
0.5
IOL = 0.5 mA 0.4 V
Output Voltage HIGH-Level Input Voltage LOW-Level Input Voltage
[9]
Except crystal pins 2.0 V
[9]
Except crystal pins 0.8 V Input HIGH Current VIN = VDD–0.5V < 1 10 µA Input LOW Current VIN = +0.5V < 1 10 µA Output Leakage Current Three-state outputs 250 µA VDD Supply Current
[10]
= VDD max., 3.3V operat ion 50 70 mA
V
DD
Industrial VDD Power Supply Current in
Shutdown Mode V
Power Supply Current V
BATT
[10]
Shutdown active,
excluding V
BATT
BATT
= 3.0V 5 15 µA
CY2291I/CY2291FI 10 100 µA
V
6
CY2291
Switching Characteristics, Commer ci al 5.0V
Parameter Name Description Min. Typ. Max. Uni t
t
1
Output Peri od Clock output range,
5V operation
Output Duty
[11]
Cycle
Duty cycle fo r outputs, define d as t2 ÷ t f
> 66 MH Z
OUT
Duty cycle fo r outputs, define d as t f
< 66 MHZ
OUT
t t t
t
t
t
t
t
t
t
t
3 4 5
6
7
8
9A
9B
9C
9D
10A
Rise Time Output clock rise time Fall Time Output cloc k fall time Output Disable
Time Output Enable
Time Skew Skew delay between any identi cal or related ou t-
Time for output to enter three-state mode after SHUTDOWN
/OE goes LOW
Time for output to leave three-state mode after SHUTDOWN
[3, 12, 15]
puts
/OE goes HIGH
CPUCLK Slew Frequency transition rate 1.0 20.0 MHz/
Clock Jitter
[14]
Peak-to-peak period jitter (t9A Max. – t9A min.), % of cl ock period (f
Clock Jitter
Clock Jitter
Clock Jitter
Lock Time for
[14]
[14]
[14]
Peak-to-peak period jitter (t9B Max. – t9B min.) (4 MHz <
f
OUT
< 16 MHz)
Peak- to-peak period jitter (16 MHz < f
OUT <
50 MHz)
Peak- to-peak period jitter (f
> 50 MHz)
OUT
Lock Time from Power-Up <25 50 ms
CPLL
t
10B
Lock Time for UPLL and SPLL
Lock Time from Power-Up <0.25 1 ms
Slew Limits CPU PLL Slew Limits CY2291 8 100 MHz
Notes:
11. XBUF duty cycle depends on XTALIN duty cycle.
12. Measured at 1.4V.
13. Measured between 0.4V and 2.4V.
14. Jitter varies with configuration. All standard configurations sample tested at the factory conform to this limit. For more information on jitter, please refer to the application note: Jitter in PLL-Based Systems.
15. CLKF is not guaranteed to be in phase with CLKA-D, even if it is referenced off the same PLL.
CY2291 10
CY2291F 11.1
[12]
1
[12]
÷ t
2
1
[13]
[13]
(100 MHz)
(90 MHz)
40% 50% 60%
45% 50% 55%
35ns
2.5 4 ns
13000
(76.923 kHz)
13000
(76.923 kHz)
10 15 ns
10 15 ns
< 0.25 0.5 ns
<0.5 1 %
< 4 MHz)
OUT
<0.7 1 ns
<400 500 ps
<250 350 ps
CY2291F 8 90 MHz
ns
ns
ms
7
CY2291
Switching Characteristics, Commer ci al 3.3V
Parameter Name Description Min. Typ. Max. Unit
t
t t t
t
t
t
t
t
t
t
t
t
1
3 4 5
6
7
8
9A
9B
9C
9D
10A
10B
Output Period Clock output range, 3.3V
operation
Output Duty
[11]
Cycle
Duty cycle for outputs, defined as t2 ÷ t f
> 66 MHZ
OUT
Duty cycle for outputs, defined as t f
< 66 MHZ
OUT
Rise Time Output clock rise time Fall Time Output clock fall time Output Disable
Time Output Enable
Time Skew Skew delay between any identic al or related
Time for out put to enter thr ee-state mode af ter SHUTDOWN
/OE goes LOW
Time for output to leave three-state mode after SHUTDOWN
outputs
/OE goes HIGH
[3, 12, 15]
CPUCLK Slew Frequency transition rate 1.0 20.0 MHz/
Clock J it t er
Clock J it t er
Clock J it t er
Clock J it t er
Lock Time for
[14]
[14]
[14]
[14]
Peak -to-peak p eriod jitt er (t9A Max. – t9A min.), % of clock period (f
OUT
Peak -to-p eak period jitter (t9B Max. – t9B min.) (4 MHz <
f
OUT
< 16 MH z )
Peak -to-peak period jitter (16 MHz < f
OUT <
50 MHz)
Peak -to-peak period jitter (f
> 50 MHz)
OUT
Lock Time from Power-Up <25 50 ms
CPLL Lock Time for
Lock Time from Power-Up <0.25 1 ms
UPLL and SPLL Slew Limits CPU PLL Slew Limits CY2291 8 80 MHz
CY2291 12.5
CY2291F 15
[12]
1
[12]
÷ t
2
1
[13]
[13]
(80 MHz)
(66.6 MHz)
40% 50% 60%
45% 50% 55%
35ns
2.54ns
13000
(76.923 kHz)
13000
(76.923 kHz)
10 15 ns
10 15 ns
< 0.25 0.5 ns
<0.5 1 %
< 4 MHz)
<0.7 1 ns
<400 500 ps
<250 350 ps
CY2291F 8 66.6 MHz
ns
ns
ms
8
CY2291
Switching Characteristics, Industrial 5.0V
Parameter Name Description Min. Typ. Max. Unit
t
t t t
t
t
t
t
t
t
t
t
t
1
3 4 5
6
7
8
9A
9B
9C
9D
10A
10B
Output Period Clock output ran ge,
5V operation
Output Duty
[11]
Cycle
Duty cycle for outputs, defined as t2 ÷ t f
> 66 MHZ
OUT
Duty cycle for outputs, defined as t f
< 66 MHZ
OUT
Rise Time Output clock rise time Fall Time Output clock fall time Output Disable
Time Output Enable
Time Skew Skew delay between any identic al or related
Time for out put to ent er thr ee-st ate mod e after SHUTDOWN
/OE goes LOW
Time for o utp ut to lea v e three- state mode af ter SHUTDOWN
outputs
/OE goes HIGH
[3, 12, 15]
CPUCLK Slew Frequency transition rate 1.0 20.0 MHz/
Clock J it t er
Clock J it t er
Clock J it t er
Clock J it t er
Lock Time for
[14]
[14]
[14]
[14]
Peak -to-p eak peri od ji tter (t9A Max. – t9A min. ), % of clock period (f
OUT
Peak -to-peak period jitter (t9B Max. – t9B min.) (4 MHz <
f
OUT
< 16 MH z )
Peak -to-peak period jitter (16 MHz < f
OUT <
50 MHz)
Peak -to-peak period jitter (f
> 50 MHz)
OUT
Lock Time from Power-Up <25 50 m s
CPLL Lock Time for
Lock Time from Power-Up <0.25 1 ms
UPLL and SPLL Slew Limits CPU PLL Slew Limits CY2291I 8 90 MHz
CY2291I 11.1
CY2291FI 12.5
[12]
1
[12]
÷ t
2
1
[13]
[13]
(90 MHz)
(80 MHz)
40% 50% 60%
45% 50% 55%
35ns
2.54ns
13000
(76.923 kHz)
13000
(76.923 kHz)
10 15 ns
10 15 ns
< 0.25 0.5 ns
<0.5 1 %
< 4 MHz)
<0.7 1 ns
<400 500 ps
<250 350 ps
CY2291FI 8 80 MHz
ns
ns
ms
9
CY2291
Switching Characteristics, Industrial 3.3V
Parameter Name Description Min. Typ. Max. Unit
t
t t t
t
t
t
t
t
t
t
t
t
1
3 4 5
6
7
8
9A
9B
9C
9D
10A
10B
Output Period Clock out put r ange, 3 .3V
operation
Output Duty
[11]
Cycle
Duty cycle for outputs, defined as t2 ÷ t f
> 66 MHZ
OUT
Duty cycle for outputs, defined as t f
< 66 MHZ
OUT
Rise Time Output clock rise time Fall Time Output clock fall time Output Disable
Time Output Enable
Time Skew Skew delay between an y identical or related out-
Time for output to ent er three-state mode after SHUTDOWN
/OE goes LOW
Time for output to le ave three-state mode after SHUTDOWN
[3, 12 , 15]
puts
/OE goes HIGH
CPUCLK Slew Frequency transiti on rate 1.0 20.0 MHz/
Clock Jitt er
Clock Jitt er
Clock Jitt er
Clock Jitt er
Lock Tim e for
[14]
[14]
[14]
[14]
Peak- to-peak period jitter (t9A Max. – t9A min.), % of clock period (f
OUT
Peak-to-peak period jitter (t9B Max. – t9B min.) (4 MHz <
f
OUT
< 16 MHz)
Peak-to-peak period jitter (16 MHz < f
OUT <
50 MHz)
Peak-to-peak period jitter (f
> 50 MHz)
OUT
Lock Time from Power-Up <25 50 ms
CPLL Lock Tim e for
Lock Time from Power-Up <0.25 1 ms
UPLL and SPLL Slew Limits CPU PLL Slew Limits CY2291I 8 66.6 MHz
CY2291I 15
CY2291FI 16.66
[12]
1
[12]
÷ t
2
1
[13]
[13]
(66.6 MHz)
(60 MHz)
40% 50% 60%
45% 50% 55%
35ns
2.54ns
13000
(76.923 kHz)
13000
(76.923 kHz)
10 15 ns
10 15 ns
< 0.25 0.5 ns
<0.5 1 %
< 4 MHz )
<0.7 1 ns
<400 500 ps
<250 350 ps
CY2291FI 8 60 MHz
ns
ns
ms
Switching Waveforms
All Outputs, Duty Cycle and Rise/Fall Time
t
2
OUTPUT
t
3
t
1
t
4
10
CY2291
Switching Waveforms
Output Three-State Timing
OE
ALL
THREE-STATE
OUTPUTS
CLK Outputs Jitter and Skew
CLK
OUTPUT
RELATED
CLK
CPU Frequency Change
(continued)
[4]
t
5
t
9A
t
6
t
7
SELECT
CPU
Test Cir cuit
V
V
OLD SELECT NEW SELECT STABLE
F
old
t8&t
DD
0.1µF
OUTPUTS
DD
0.1µF GND
F
10
new
CLK out
C
LOAD
11
CY2291
Ordering Information
Package
Ordering Code
CY2291SC–XXX S5 20-Pin SOIC Commercial 5.0V CY2291SL–XXX S5 20-Pin SOIC Commercial 3.3V CY2291F S5 20-Pin SOIC Commercial 3.3V or 5. 0V CY2291SI–XXX S5 20-Pin SOIC Industrial 3.3V or 5.0V CY2291FI S5 20-Pin SOIC Industrial 3.3V or 5.0V
Document #: 38- 00945-** CyClocks is a trademark of Cypress Semiconductor Corporation.
Pent ium is a registered trademark of Intel Corporation.
Name
Package Type
Custom Configuration Request Procedure
The CY229x are EPROM-pr ogrammab le devices that ma y be configured i n the factory or in the field b y a Cypress Field Applica tion Engineer (FAE). The output frequencies requested will be matched as closely as the internal PLL divider and multiplier options allow. All custom requests must be submitted to your local Cypress FAE or sales representative. The method to use to request custom configurations is:
Use CyClocks software. This software automatically calculates the output frequencies that can be generated by the CY229x devices and provides a print-out of final pinout which can be submitted (in electronic or print format) to your local FAE or sales representative. The CyClocks software is available free of charge from the Cypress website (http://www.cypress.com) or from your local sales representative.
Once the custom request has been processed you will receive a part number with a 3-digit extension (e.g., CY2292SC-128) specific to the frequencies and pinout of your device. This will be the part number used for samples request s and production orders.
Operating
Range
Operating
Voltage
Package Chara cteristics
Package
20-pin SOIC 125 25 9271
θ
JA
(C/W)
(C/W) Transistor Count
θ
JC
12
Package Diagram
CY2291
20-Lead (300-Mil) Molded SOIC S5
51-85024-A
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it con vey or imply any lice nse under patent or other rights. Cypress Semicondu ctor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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