CYPRESS W228B User Manual

PRELIMINARY

FTG for Integ rated Core Logic with 133- MH z FSB

Features

• Maximized EMI suppression usi ng Cypress’s Spread
Spec trum te chnol ogy

• T w o copies of CPU clock at 66/100/1 33 MHz

• Twelve copies of 100 MHz SDRAM clocks

• One copy of PCI cloc k

• One copy of APIC cloc k at 33 MHz, syn chronous to CPU
clock

• T wo copies of 4 8-MHz cloc k (non-spre ad spectrum) op­timized for USB reference input and video dot cloc k

• Three copies of 3V 66-MHz fixed clock

• One copy of 14.3181 8-MHz reference cl ock

• Power down control

2

•I

C™ interface for turning off unused clocks

Key Specific ati o n s

CPU, SDRAM Outputs Cycle-to-Cycle Jitt er:.... .. ........ 250 ps

APIC, 48-MHz, 3V66, PCI Outputs

Cycle-to-Cycle Jitter:................................................... 500 ps

APIC, SDRAM Output Skew:...................................... 250 ps

W228B

CPU, 3V66 O ut p u t Skew: ............. .......... .. .......... .. .......175 ps

PCI Output Skew:........................................................500 ps

CPU to SDRAM Skew (@ 133 MHz):.........................±0.5 ns

CPU to SDRAM Skew (@ 100 MHz):.................4.5 to 5.5 ns

CPU to 3V 6 6 Skew (@ 66 MH z ): . .......... .. ..........7 . 0 to 8. 0 ns

3V66 to PCI Skew (3V66 lead):..........................1.5 to 3.5 ns

PCI to AP IC S kew: . ... ......... ... ......... ... .......... ......... ... ... ± 0 . 5 n s

T able 1. Pin Selectable Functions

Tristate# FSEL0 FSEL1 CPU SDRAM

0 0 x Three-state Three-state
0 1 x Test Test
1 0 0 66 MHz 100 MHz
1 1 0 100 MHz 100 MHz
1 0 1 133 MHz 133 MHz
1 1 1 133 MHz 100 MHz

Block Diagram

X1
X2

SDATA

SCLK

FSEL1:0

VDDA

Tristate#

PWRDWN#

VDDA

PLL 1

XTAL

OSC

I2C

Logic

PLL2

PLL REF FREQ

Divider,

Delay,

and

Phase

Control

Logic

VDDQ3

VDDQ2

2

VDDQ3

2

13

VDDQ3

REF0/FSEL1

CPU0:1

APIC

3V66_0:1
3V66_AGP

PCI0_ICH

PCI1

SDRAM0:12

USB

DOT

Pin Configuration

APIC

VDDQ2

GND

REF0/FSEL1*

VDDQ3

GND
VDDQ3
3V66_0
3V66_1

3V66_AGP

GND
VDDQ3

PCI0_ICH

PCI1

GND

FSEL0

GNDA

VDDA

PWRDWN#

SCLK

SDATA

GND
VDDQ3

USB
DOT

Tristate#

Note:

1. Internal pull-down resistors present on input marked with *.
Design should not solely rely on internal pull-down resister to
set I/O pin LOW.

X1
X2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

[1]

W228B

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

VDDQ2
GND
CPU0
CPU1
GND
SDRAM0
SDRAM1
VDDQ3
GND
SDRAM2
SDRAM3
SDRAM4
VDDQ3
GND
SDRAM5
SDRAM6
VDDQ3
GND
SDRAM7
SDRAM8
SDRAM9
VDDQ3
GND
SDRAM10
SDRAM11
VDDQ3
GND
SDRAM12

I2C is a trademark of Philips Corporation. Intel is a registered trademark of Intel Corporation.

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Febuary 18, 2000, rev. *B

PRELIMINARY

Pin Definitions

Pin Name Pin No.

REF0/FSEL1 4 I/O

X1 6 I

X2 7 O

PCI0_ICH,
PCI1

3V66_0:2,
3V66_AGP

USB 26 O
DOT 27 O
Tristate#,

FSEL0
PWRDWN# 21 I

CPU0:1 54, 53 O

SDRAM0:12 51, 50, 47, 46,

APIC 1 O

SDATA 23 I/O Data pin for I
SCLK 22 I Clock pin for I
VDDQ3 5, 9, 14, 25, 31,

VDDA 20 P

VDDQ2 2, 56 P

GND 3, 8, 13, 17, 24,

GNDA 19 G

15, 16 O

10, 11, 12 O

28, 18 I

45, 42, 41, 38,
37, 36, 33, 32,

29

35, 40, 44, 49

30, 34, 39, 43,

48, 52, 55

Pin

Ty pe Pin Description

Reference Cloc k:

option fo r CPU fre quency selection. See Table 1 for detailed descriptions.

Crystal Input:

14.318-MHz crystal co nnection or as an external reference frequency input.

Crystal Output:

ternal reference, this pin must be lef t unconnected.

PCI Clock 0 through 1:

turned off via I

66-MHz Clock Output:

USB Clock Output:
Dot Clock Output:
Clock Function Selection pins:

tions. See Table 1 for detailed descriptions.

Power-Down Control:

vice in power -down mode when held LOW.

CPU Clock Outputs:

port. Output frequencie s run at 66 MHz, 100 MHz, or 133 MHz depending on the
configura ti on of SEL0:1 and SEL133. Voltage swi ng set by VDDQ2.

SDRAM Clock Outputs:

O

individually turned off via I

Synchronous APIC Cloc k Outputs :

PCI clock outputs (33 MHz). Voltage swing set by VDDQ2.

3.3V Power Connection:

P

buffers, 3V66 output buffers, reference output buffers, and 48 -MHz output buff ers.
Connect to 3.3V.

3.3V Power Connection:

3.3V.

2.5V Power Connection:

nect to 2.5V or 3.3V.

Ground Connections:

G

plane.

Ground Connections:

plane.

W228B

3.3V 14.318-MHz cloc k output. This pin also serves as a strap

This pin has dual functi ons. It can be used as an ext ernal

A connection f or an external 14.318-MHz crystal. If using an ex-

2

C interface.

2

C circuitry.

2

C circuitry.

3.3V 33-MHz PCI clock outpu ts. PCI1 can be i ndividually

3.3V fix ed 66-MHz clock.

3.3V fixed 48-MHz , non-spread spectrum USB clock output.

3.3V 48-MHz, non-spread spectrum signal.
LVTTL-compatible input to select device func-

LVTTL-compatible asynchronous input that places t he de-

Clock outputs for the host bus interface and integrated test

3.3V outputs running at 100 MHz. SDRAM0:12 can be

2

C interface.

Clock outputs running sync hronous wi th the

Power suppl y for SDRAM output buffers, PCI output

Power supply for core logic, PLL circuitry. Connect to

Power supply for IOAPIC and CPU output buffers. Con-

Connect all ground pins to the common system ground

Connect all ground pins to the common system ground

2

PRELIMINARY

V

DD

10 k

10k

Ω

Ω

W228B

Power-on
Reset
Timer

Output
Buffer

Output Three-state

Hold
Output
Low

QD

Data

Latch

(Load Option 1)

(Load Option 0)

Figure 1. Input Logic Selection Through Resistor Load Option

W228B

Output Strapping Resistor

Series Termination Resistor

Clock Load

Overview

tor should be used. Figure 1 shows a suggested method for

strapping res istor connections.
The W228B is a highly integrated fr equency timing generator,
supplying all the required clock sources for an Intel® architec­ture platform using graphics in tegrated core logic.

Functional Description

I/O Pin Operation

REF0/FSEL1 is a dual-purpose l/O pin. Upon po wer- up the pi n
acts as a logic input for FSEL1 selecti on (see Table 1 and Table

2). If the pin is strapped to a HIGH state externally, CPU will
be strappe d LOW. CPU clock outputs wi ll be determined b y the
status of SEL0:1 i nput pins. An external 10- kΩ strapping r esis-

After 2 ms, the pin becomes an output. Assuming the power

supply has stabilized by then, the specified output frequency

is delivered on the pins. If the power supply has not yet

reached full value , output frequency initially may be below tar-

get but will increase to target once supply voltage has stabi-

lized. In either case, a short output clock cycle may be pro-

duced from the CPU clock outputs when the outputs are

enabled.

Pin Selectable Functions

Table 2 outlines the device functions selectable through

Tr istate# and FSEL0:1. Specific outputs available at each pin

are detailed in Ta ble 2 below.

Table 2. CK Whitney Truth Table

Tristate# FSEL0 FSEL1 CPU SDRAM 3V66 PCI 48MHz REF APIC Notes

0 0 X Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 2
0 1 X TCLK/4 TCLK/4 TCLK/6 TCLK/12 TCLK/2 TCLK TCLK/12 4, 5
1 0 0 66 MHz 100 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 33 MHz 3, 6, 7
1 1 0 100 MHz 100 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 33 MHz 3, 6, 7
1 0 1 133 MHz 133 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 33 MHz 3, 6, 7
1 1 1 133 MHz 100 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 33 MHz 3, 6, 7

Notes:

2. Provided for board-level “bed of nails” testing.

3. “Normal” mode of operation.

4. TCLK is a test clock overdriven on the XTAL_IN input during test mode.

5. Required for DC output impedance verification.

6. Range of reference frequency allowed is min. = 14.316 MHz, nominal = 14.31818 MHz, max. = 14.32 MHz.

7. Frequency accuracy of 48 MHz must be +167 PPM to match USB default.

3

PRELIMINARY

W228B

Offsets Among Clock Signal Groups

Figure 2 and Figur e 3 represe nt the pha se r elation shi p amon g
the different groups of clock outputs from W228B when it is
providing a 66-MHz CPU clock and a 100-MHz CPU clock,

0 ns

CPU 66-MHz

SDRAM 100-MHz

3V66 66-MHz

PCI 33-MHz

APIC33-MHz

REF 14.318-MHz

USB 48-MHz
DOT 48-MHz

Cycle Repeat

Figure 2. Group Offset Waveforms (66-MHz CPU/100-MHz SDRAM Clock)

respectively. It should be noted that when the CPU clock is

operating at 100 MHz, CPU cloc k out put is 18 0 deg rees out of

phase with SDRAM clock outputs.

40 ns30 ns20 ns10 ns

CPU 100-MHz

SDRAM 100-MHz

3V66 66-MHz

PCI 33-MHz

APIC 33-MHz

REF 14.318-MHz

USB 48-MHz
DOT 48-MHz

0 ns

Cycle Repeat

Figure 3. Group Offset Waveforms (100-MHz CPU/100- MHz SDRAM Clock)

40 ns30 ns20 ns10 ns

4

PRELIMINARY

W228B

CPU 133-MHz

SDRAM 100-MHz

3V66 66-MHz

PCI 33-MHz

APIC 33-MHz

REF 14.318-MHz

USB 48-MHz
DOT 48-MHz

CPU 100-MHz

0 ns

Cycle Repeats

Figure 4. Group Offset Waveforms (133-MHz CPU/100- MHz SDRAM Clock)

0 ns

Cycle Repeat

40 ns30 ns20 ns10 ns

40 ns30 ns20 ns10 ns

SDRAM 100-MHz

3V66 66-MHz

PCI 33-MHz

APIC 33-MHz

REF 14.318-MHz

USB 48-MHz
DOT 48-MHz

Figure 5. Group Offset Waveforms (133-MHz CPU/133- MHz SDRAM Clock)

5

PRELIMINARY

W228B

Power Down Control

W228B prov ides one PWRDWN# signal to place the de vice in lo w-power mode. In low-power mode, th e PLLs are turned of f and
all clock outputs are driven LOW.

0ns 25ns 50ns 75ns

Center

1 2

VCO Internal

CPU 100MHz

3V66 66MHz

PCI 33MHz

APIC 33MHz

PwrDwn

SDRAM 100MHz

REF 14.318MHz

USB 48MHz

Figure 6. W218 PWRDWN# Timing Diagram

[8, 9, 10, 11]

T able 3. W228B Maximum Allowed Current

Condition

Powerdown Mode

W228B

Max. 2.5V supply consumption

Max. discrete cap loads,

V

= 2.625V

All static inputs = V

DDQ2

DDQ3

or V

10 mA 10 mA

SS

Max. 3.3V supply consumpti on

Max. discrete cap loads

V

= 3.465V

All static inputs = V

DDQ3

DDQ3

or V

SS

(PWRDWN# = 0)
Full Active 66 MHz

70 mA 280 mA

FSEL1:0 = 00 (PWRDWN# =1)
Full Active 100 MHz

100 mA 280 mA

FSEL1:0 = 01 (PWRDWN# =1)
Full Active 133 MHz

TBD TBD

FSEL1:0 = 11 (PWRDWN# =1)

Notes:

8. Once the PWRDWN# signal is sampled LOW for two consecutive rising edges of CPU, clocks of interest will be held LOW on the next HIGH-to-LOW transition.

9. PWRDWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W228B.

10. The shaded sections on the SDRAM, REF, and USB clocks indicate “don’t care” states.

11. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz.

6

PRELIMINARY

W228B

Spread Spectrum Frequency Tim ing G enera to r

The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occu pies. By increas ing
the bandwidth of the fundamental and its harmonics, the am­plitudes of the radiated electromagnetic emissions are re­duced. This effect is depicted in Figure 7.

As shown in Figure 7, a harmonic of a modulated clock has a
much low er amplitu de than that of an un modulated si gnal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:

dB = 6.5 + 9*log

(P) + 9*log10(F)

10

Spread

Spectrum

Enabled

EMI Reduction

Where P is the percenta ge of de vi ation and F is the frequen cy

in MHz where the reduction is measured.

The output clock is modulated with a waveform depicted in

Figure 8. This waveform, as discussed in “Spread Spectrum

Clock Generation f or the Reducti on of Radiated Emissio ns” by

Bush, Fessler, and Hardin produces the maximum reduction

in the amplitude of radiated electromagnetic emissions. The

deviation selected for this chip is –0.5% of the selected fre-

quency. Figure 8 details the Cypress spreading pattern.

Cypress does off er optio ns with more spr ead and great er EMI

reduction. Contact your local Sales representative for details

on these devices.

Spread Spectrum clocking is activated or deactivated by se-

lecting the appropriate value for bit 3 in data byte 0 of the I

2

data stream. Refer to page 9 for more details.

Non-

Spread

Spectrum

C

Figure 7. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation

MAX.

10%

20%

30%

40%

50%

60%

70%

80%

FREQUENCY

MIN.

90%

100%

10%

20%

30%

40%

50%

60%

70%

80%

90%

Figure 8. Typica l Modulation Profile

7

100%

PRELIMINARY

W228B

1 bit 7 bits 1 1 8 bits 1

Start bit Slave Address R/W Ack Command Code Ack Byte Count = N

Ack Data Byte 1 Ack Data Byte 2 Ack ... Data Byte N Ack Stop

1 bit 8 bits 1 8 bits 1 8 bits 1 1

Figure 9. An Example of a Block Write

Seria l D a ta Interfa c e

The W228B features a two-pin, serial data interface that can
be used to configure i nternal register settings that control pa r­ticular de vice functions.

Data Protocol

The clock dri ver serial protocol accepts onl y block writes fr om
the controller. The bytes must be accessed in sequenti al order
from lo west to hi ghest by te with t he abilit y to s top afte r any
complete byte has been transferred. Index ed bytes are not al ­lowed.

A bloc k write be gins wit h a sla ve address an d a write conditi on.
After the command code the core logic issues a byte count
which describes how many more bytes will follow in the mes­sage. If the host had 20 bytes to send, the first byte would be
the number 20 (14h), followed b y the 20 bytes of data. The byte
count ma y not be 0. A bl ock write command i s allowed to t rans-

T able 4. Example of Possible Byte Count Value

Byte Count Byte Notes

MSB LSB
0000 0000 Not allowe d. Must have at least one byte.
0000 0001 Dat a for functional and frequency select register (currently byte 0 in spec)
0000 0010 Reads first two bytes of data (byte 0 then byte1)
0000 0011 Reads first three bytes (byte 0, 1, 2 in order)
0000 0100 Reads first four bytes (byte 0, 1, 2, 3 in order)
0000 0101 Reads first five bytes (byte 0, 1, 2, 3, 4 in order)
0000 0110 Reads first six bytes (byte 0, 1, 2, 3, 4, 5 in or der)
0000 0111 Reads first seven byt es (byte 0, 1, 2, 3, 4, 5, 6 in order)
0010 0000 Max. byte count supported = 32

[12]

fer a maximum of 32 data bytes. The slave receiver address
for W228B is 110100 10. Figure 9 sho ws an e xample of a bl ock
write.

The command code and the byte count bytes are required as
the first two b yte s of any t ransfer. W228B expect s a command
code of 0000 0000. The byte count byte is the number of ad­ditional bytes required for the transfer, not counting the com­mand code and byte count bytes. Additionally, the byte count
byte is required to be a minimum of 1 byte and a maximum of
32 bytes to satisfy the above requirement. Tabl e 4 shows an
example of a possible byte count value.

A transfer is considered valid after the acknowledge bit corre­sponding to the byte count is read by t he controller. The com­mand code and byte count bytes are ignored by the W228B.
However, these bytes must be included in the data write se­quence to maintain proper byte allocation.

[13]

[13]

T able 5. Serial Data Interface Control Func ti ons Sum mary

Control Function Description Common Application

Output Disable Any individual clock output(s) can be disabled.

Disabled out puts are actively held LOW.

Unused outputs are disabl ed to reduce EMI and sys­tem power. Examples are clock outputs to unused
PCI slots.

Spread Spectrum

Enables or dis ables spread spectrum cl ocking. For EMI reduction.

Enabling
(Reserved) Reserved function f or future de vice re vision or pro-

No user appli cation. Re gister bit must be writ ten as 0.

duction device testing.

Notes:

12. The acknowledgment bit is returned by the slave/receiver (W228B).

13. Data Bytes 3 to 7 are reserved.

8

PRELIMINARY

W228B

W228B Serial Configuration Map

1. The serial bit s will be read by the c lock driver in the fol lowing
order:

Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte 0: Control Regist er (1 = Enable, 0 = Disable)

Bit Pin# Name Pin Description

Bit 7 - Reser ved Reserved
Bit 6 - Reser ved Reserved
Bit 5 - Reser ved Reserved
Bit 4 - Reser ved Reserved
Bit 3 - Spread Spectrum (1 = On/0 = Off) (Disabled/Enabled)
Bit 2 27 DOT (Active/Inactive)
Bit 1 26 USB (Active/Inactive)
Bit 0 -- Reserved Reserved

Byte 1: Control Regist er (1 = Enable, 0 = Disable)

Bit Pin# Name Pin Description

Bit 7 38 SDRAM7 (Active/Inactive)
Bit 6 41 SDRAM6 (Active/Inactive)
Bit 5 42 SDRAM5 (Active/Inactive)
Bit 4 45 SDRAM4 (Active/Inactive)
Bit 3 46 SDRAM3 (Active/Inactive)
Bit 2 47 SDRAM2 (Active/Inactive)
Bit 1 50 SDRAM1 (Active/Inactive)
Bit 0 51 SDRAM0 (Active/Inactive)

[14]

[14]

2. All unused register bits (reserved and N/A) should be writ­ten to a “0” level.

3. All register bits labeled “Initialize to 0" must be written to
zero during initialization. Failure to do so may result in high­er than normal operating cur rent.

4. Only Byte 0, 1, and 2 are def in ed in W228B . Byte 3 t o Byte
7 are reserved and must be writte n to “zero.”

Byte 2: Control Regist er (1 = Enable, 0 = Disable)

Bit Pin# Name Pin Description

Bit 7 12 3V66_AGP (Active/Inactive)
Bit 6 29 SDRAM12 (Active/Inactive)
Bit 5 32 SDRAM11 (Active/Inactive)
Bit 4 33 SDRAM10 (Active/Inactive)
Bit 3 36 SDRAM9 (Active/Inactive)
Bit 2 37 SDRAM8 (Active/Inactive)
Bit 1 16 PCI1 (Active/Inactive)
Bit 0 - (Reserved) (Reserved)

Note:

14. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be
configured during the normal modes of operation.

[14]

9

PRELIMINARY

Byte 3: Reserved Register (1 = Enable, 0 = Disab le)

Bit Pin# Name Pin Description

Bit 7 - Reser ved Drive to ’0’ (Active/Inactive)
Bit 6 - Reser ved Drive to ’0’ (Active/Inactive)
Bit 5 - Reser ved Drive to ’0’ (Active/Inactive)
Bit 4 - Reser ved Drive to ’0’ (Active/Inactive)
Bit 3 - Reser ved Drive to ’0’ (Active/Inactive)
Bit 2 - Reser ved Drive to ’0’ (Active/Inactive)
Bit 1 Res erved Drive to ’0’ (Active/Inactive)
Bit 0 - SDRAM 133-MHz Mode Enable

Default is Disabled = ’0’, Enabled = ’1’

Byte 4: Reserved Register (1 = Enable, 0 = Disab le)

Bit Pin# Name Pin Description

Bit 7 - Reser ved Drive to ’0’ (Active/Inactive)
Bit 6 - Reser ved Drive to ’0’ (Active/Inactive)
Bit 5 - Reser ved Drive to ’0’ (Active/Inactive)
Bit 4 - Reser ved Drive to ’0’ (Active/Inactive)
Bit 3 - Reser ved Drive to ’0’ (Active/Inactive)
Bit 2 - Reser ved Drive to ’0’ (Active/Inactive)
Bit 1 Res erved Drive to ’0’ (Active/Inactive)
Bit 0 - Reser ved Drive to ’0’ (Active/Inactive)

(Disabled/Enabled)

W228B

10

PRELIMINARY

W228B

DC Electr i cal C h ar acteristics

Absolute Maximum DC Power Supply

Parameter Description Min. Max. Unit

V

DD3

V

DDQ2

V

DDQ3

T

S

Absolute Maximum DC I/O

Parameter Description Min. Max. Unit

V

ih3

V

il3

ESD prot. Input ESD Protection 2000 V

DC Operating Requirements

Parameter Description Condition Min. Max. Unit

V

DD3

V

DDQ3

V

DDQ2

3.3V±5%

V

DD3 =

V

ih3

V

il3

I

il

DDQ2 =
oh2
ol2
DDQ3 =
oh3
ol3
DDQ3 =
poh3
pol3

2.5V±5%

3.3V±5%

3.3V±5%

V
V
V
V
V
V
V
V
V

3.3V Core Supply Voltage –0.5 4.6 V

2.5V I/O Supply Voltage –0.5 3.6 V

3.3V Supply Voltage –0.5 4.6 V
Storage Temperature –65 150 °C

3.3V Input High Voltage –0.5 4.6 V

3.3V Input Low Voltage –0.5 V

3.3V Core Supply Voltage 3.3V±5% 3.135 3.465 V

3.3V I/O Supply Voltage 3.3V±5% 3.135 3.465 V

2.5V I/O Supply Voltage 2.5V±5% 2.375 2.625 V

3.3V Input High Voltage V

DD3

3.3V Input Low Voltage V
Input Leakage Curr ent

[15]

0<Vin<V

DD3

2.0 V
– 0.3 0.8 V

SS

+ 0.3 V

DD

–5+5µA

2.5V Output High Voltage Ioh=(–1 mA) 2.0 V

2.5V Output Low Voltage Iol=(1 mA) 0.4 V

3.3V Output High Voltage Ioh=(–1 mA) 2.4 V

3.3V Output Low Voltage Iol=(1 mA) 0.4 V

PCI Bus Output High Voltage Ioh=(–1 mA) 2.4 V
PCI Bus Output Low Voltage Iol=(1 mA) 0.55 V

C

in

C

xtal

C

out

L

pin

T

a

Note:

15. Input Leakage Current does not include inputs with pull-up or pull-down resistors.

Input Pin Capacitance 5 pF
Xtal Pin Capacitance 13.5 22.5 pF
Output Pin Capacitance 6 pF
Pin Inductance 0 7 nH
Ambient Temperature No Airflow 0 70 °C

11

AC Electrical Characteristics

PRELIMINARY

W228B

TA = 0°C to +70°C, V
f

= 14.31818 MHz

XTL

Spread Spectrum functi on turned off

AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock o utput.

[16]

= 3.3V±5%, V

DDQ3

DDQ2

= 2.5V±5%

AC Electrical Characteristics

66.6-MHz Host 100-MHz Host 133-MHz Host

Parameter Description

T

Period

T

HIGH

T

LOW

T

RISE

T

FALL

T

Period

T

HIGH

T

LOW

T

RISE

T

FALL

T

Period

T

HIGH

T

LOW

T

RISE

T

FALL

Host/CPUCLK Peri od 15.0 15.5 10.0 10.5 7.5 8.0 ns 16
Host/CPUCLK High Time 5.2 N/A 3.0 N/A 1.87 N/A ns 19
Host/CPUCLK Low Time 5.0 N/A 2.8 N/A 1.67 N/A ns 20
Host/CPUCLK Rise Time 0.4 1.6 0.4 1.6 0.4 1.6 ns
Host/CPUCLK Fal l Ti m e 0.4 1.6 0.4 1.6 0.4 1.6 ns

SDRAM CLK Period (100-MHz) 10.0 10.5 10.0 10.5 10.0 10.5 ns 16
SDRAM CLK High Time (100-MHz) 3.0 N/A 3.0 N/A 3.0 N/A ns 19
SDRAM CLK Low Time (100-MHz) 2.8 N/A 2.8 N/A 2.8 N/A ns 20
SDRAM CLK Rise Time (100-MHz) 0.4 1.6 0.4 1.6 0.4 1.6 ns
SDRAM CLK Fall Time (100-M Hz) 0.4 1.6 0.4 1.6 0.4 1.6 ns

SDRAM CLK Period (133-MHz) 7.5 8.0 7.5 8.0 7.5 8.0 ns 16
SDRAM CLK High Time (133-MHz) 1.87 N/A 1.87 N/A 1.87 N/A ns 19
SDRAM CLK Low Time (133-MHz) 1.67 N/A 1.67 N/A 1.67 N/A ns 20
SDRAM CLK Rise Time (133-MHz) 0.4 1.6 0.4 1.6 0.4 1.6 ns
SDRAM CLK Fall Time (133-M Hz) 0.4 1.6 0.4 1.6 .04 1.6 ns

Unit NotesMin. Max. Min. Max. Min. Max.

T

Period

T

HIGH

T

LOW

T

RISE

T

FALL

T

Period

T

HIGH

T

LOW

T

RISE

T

FALL

T

Period

T

HIGH

T

LOW

T

RISE

T

FALL

Notes:

16. Period, jitter, offset, and skew measured on rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks.

17. T

HIGH

18. T

LOW

19. The time specified is measured from when V
and operating within specification.

20. T

RISE

APIC 33-MHz CLK Period 30.0 N/A 30.0 N/A 30.0 N/A ns 16
APIC 33-MHz CLK High Time 12.0 N/A 12.0 N/A 12.0 N/A ns 19
APIC 33-MHz CLK Low Time 12.0 N/A 12.0 N/A 12.0 N/A ns 20
APIC CLK Rise Time 0.4 1.6 0.4 1.6 0.4 1.6 ns
APIC CLK Fall Time 0.4 1.6 0.4 1.6 0.4 1.6 ns

3V66 CLK Period 15.0 16.0 15.0 16.0 15.0 16.0 ns 16, 18
3V66 CLK High Time 5.25 N/A 5.25 N/A 5.25 N/A ns 19
3V66 CLK Low Time 5.05 N/A 5.05 N/A 5.05 N/A ns 20
3V66 CLK Rise Time 0.5 2.0 0.5 2.0 0.5 2.0 ns
3V66 CLK Fall Time 0.5 2.0 0.5 2.0 0.5 2.0 ns

PCI CLK Period 30.0 N/A 30.0 N/A 30.0 N/A ns 16, 17
PCI CLK High Time 12.0 N/A 12.0 N/A 12.0 N/A ns 19
PCI CLK Low Time 12.0 N/A 12.0 N/A 12.0 N/A ns 20
PCI CLK Rise Time 0.5 2.0 0.5 2.0 0.5 2.0 ns
PCI CLK Fall Time 0.5 2.0 0.5 2.0 0.5 2.0 ns

is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.

is measured at 0.4V for all outputs.

and T

are measured as a transition through the threshold region Vol = 0.4V and Voh = 2.0V (1 mA) JEDEC specification.

FAL L

achieves its nominal operating level (typical condition V

DDQ3

= 3.3V) until the frequency output is stable

DDQ3

12

PRELIMINARY

W228B

AC Electrical Characteristics

(continued)

66.6-MHz Host 100-MHz Host 133-MHz Host

Parameter Description

tp
tp
t

stable

ZL
LZ

, tp
, tp

Output Enable Delay (All outputs) 1.0 10.0 1. 0 10.0 1.0 10.0 ns

ZH

Output Disable Delay (All outputs) 1.0 10.0 1.0 10.0 1.0 10.0 ns

ZH

All Clock Stabilizati on from Power- Up 3 3 3 ms

Group Skew and Jitte r Limi ts

Out p ut Group Pin-Pin Skew M ax . Cycle - C y cle Jit ter D uty Cycle No m V dd

CPU 175 ps 250 ps 45/55 2.5V 1.25V

SDRAM 250 ps 250 ps 45/55 3.3V 1.5V

APIC 250 ps 500 ps 45/55 2.5V 1.25V

48MHz 250 ps 500 ps 45/55 3.3V 1.5V

3V66 175 ps 500 ps 45/55 3.3V 1.5V

PCI 500 ps 500 ps 45/55 3.3V 1.5V

REF N/A 1000 ps 45/55 3.3V 1.5V

Test Point

Test Load

T

PERIOD

Duty Cycle

Clock Out put Wave

2.5V Clock in g
Interface

1.25

Output
Buffer

T

HIGH

2.0

0.4

Unit NotesMin. Max. Min. Max. Min. Max.

Skew, Ji t t er

Measure Point

T

LOW

T

RISE

3.3V Clocking
Interface

2.4

1.5

0.4

T

RISE

T

FALL

T

HIGH

T

FALL

Figure 10. Output Buffer

Ordering Information

Ordering Code

W228B H 56-pin SSOP (300 mils)

Document #: 38-00883-B

Package

Name Package Type

T

PERIOD

Duty Cycle

T

LOW

13

Layout Dia gra m

PRELIMINARY

W228B

C2

G

C1

+3.3V Supply

FB

0.005 µF

C4

G G

G

G

G

G V

10 µF

C3

1
2

3
4

5
6

7
8
9

10

11
12

13
14

V

DDQ3

G

G

G

G

V

+2.5V Supply

10 µF

G

FB

0.005 µF

G

C2

G

V

DDQ2

C1

V

56

V

G

55
54

53

V

G

52
51

G

50

V

49

G

G

48

G

47
46
45

G

G

W228B

V

G

44
43

G

VDDQ3

5

15
16

G

17
19

G

G

20

Core

V

G

21
22
23

G

24

PLL2

25
26
27

G

28

F C2 & C4 = 0.005

µ

Bypass = 0 .1 µF

C5

C6

G

G

FB = Dale ILB1206 - 300 (300 Ω @ 100 MHz)

C1 & C3 = 10–22

G = VIA to GND plane layer V =VIA to respective supply plane layer

Each supply plane or strip should have a

Note:

All V

DD

Ω

42
41

G

V

40

G

3918
38

37

G

36

V

35

G

34
33
32

V

31
30

G

29

µF

C5 = 47

ferr ite bead and capacitors

F

µ

G

G

G

C6 = 0.1

F

µ

14

Package Diagram

PRELIMINARY

56-Pin Shrink Small Outline P ackage (SSOP, 300 mils)

W228B

Summary of nominal dimensions in inches:
Body Width: 0.296

Lead Pitch: 0.025
Body Length: 0.625
Body Height: 0.102

© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it con vey or imply any lice nse under patent or other rights. Cypress Semicondu ctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.