CYPRESS W228B User Manual
PRELIMINARY
FTG for Integ rated Core Logic with 133- MH z FSB
Features
• Maximized EMI suppression usi ng Cypress’s Spread
Spec trum te chnol ogy
• T w o copies of CPU clock at 66/100/1 33 MHz
• Twelve copies of 100 MHz SDRAM clocks
• One copy of PCI cloc k
• One copy of APIC cloc k at 33 MHz, syn chronous to CPU
clock
• T wo copies of 4 8-MHz cloc k (non-spre ad spectrum) optimized for USB reference input and video dot cloc k
• Three copies of 3V 66-MHz fixed clock
• One copy of 14.3181 8-MHz reference cl ock
• Power down control
2
•I
C™ interface for turning off unused clocks
Key Specific ati o n s
CPU, SDRAM Outputs Cycle-to-Cycle Jitt er:.... .. ........ 250 ps
APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter:................................................... 500 ps
APIC, SDRAM Output Skew:...................................... 250 ps
W228B
CPU, 3V66 O ut p u t Skew: ............. .......... .. .......... .. .......175 ps
PCI Output Skew:........................................................500 ps
CPU to SDRAM Skew (@ 133 MHz):.........................±0.5 ns
CPU to SDRAM Skew (@ 100 MHz):.................4.5 to 5.5 ns
CPU to 3V 6 6 Skew (@ 66 MH z ): . .......... .. ..........7 . 0 to 8. 0 ns
3V66 to PCI Skew (3V66 lead):..........................1.5 to 3.5 ns
PCI to AP IC S kew: . ... ......... ... ......... ... .......... ......... ... ... ± 0 . 5 n s
T able 1. Pin Selectable Functions
Tristate# FSEL0 FSEL1 CPU SDRAM
0 0 x Three-state Three-state
0 1 x Test Test
1 0 0 66 MHz 100 MHz
1 1 0 100 MHz 100 MHz
1 0 1 133 MHz 133 MHz
1 1 1 133 MHz 100 MHz
Block Diagram
X1
X2
SDATA
SCLK
FSEL1:0
VDDA
Tristate#
PWRDWN#
VDDA
PLL 1
XTAL
OSC
I2C
Logic
PLL2
PLL REF FREQ
Divider,
Delay,
and
Phase
Control
Logic
VDDQ3
VDDQ2
2
VDDQ3
2
13
VDDQ3
REF0/FSEL1
CPU0:1
APIC
3V66_0:1
3V66_AGP
PCI0_ICH
PCI1
SDRAM0:12
USB
DOT
Pin Configuration
APIC
VDDQ2
GND
REF0/FSEL1*
VDDQ3
GND
VDDQ3
3V66_0
3V66_1
3V66_AGP
GND
VDDQ3
PCI0_ICH
PCI1
GND
FSEL0
GNDA
VDDA
PWRDWN#
SCLK
SDATA
GND
VDDQ3
USB
DOT
Tristate#
Note:
1. Internal pull-down resistors present on input marked with *.
Design should not solely rely on internal pull-down resister to
set I/O pin LOW.
X1
X2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
[1]
W228B
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDQ2
GND
CPU0
CPU1
GND
SDRAM0
SDRAM1
VDDQ3
GND
SDRAM2
SDRAM3
SDRAM4
VDDQ3
GND
SDRAM5
SDRAM6
VDDQ3
GND
SDRAM7
SDRAM8
SDRAM9
VDDQ3
GND
SDRAM10
SDRAM11
VDDQ3
GND
SDRAM12
I2C is a trademark of Philips Corporation. Intel is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Febuary 18, 2000, rev. *B
PRELIMINARY
Pin Definitions
Pin Name Pin No.
REF0/FSEL1 4 I/O
X1 6 I
X2 7 O
PCI0_ICH,
PCI1
3V66_0:2,
3V66_AGP
USB 26 O
DOT 27 O
Tristate#,
FSEL0
PWRDWN# 21 I
CPU0:1 54, 53 O
SDRAM0:12 51, 50, 47, 46,
APIC 1 O
SDATA 23 I/O Data pin for I
SCLK 22 I Clock pin for I
VDDQ3 5, 9, 14, 25, 31,
VDDA 20 P
VDDQ2 2, 56 P
GND 3, 8, 13, 17, 24,
GNDA 19 G
15, 16 O
10, 11, 12 O
28, 18 I
45, 42, 41, 38,
37, 36, 33, 32,
29
35, 40, 44, 49
30, 34, 39, 43,
48, 52, 55
Pin
Ty pe Pin Description
Reference Cloc k:
option fo r CPU fre quency selection. See Table 1 for detailed descriptions.
Crystal Input:
14.318-MHz crystal co nnection or as an external reference frequency input.
Crystal Output:
ternal reference, this pin must be lef t unconnected.
PCI Clock 0 through 1:
turned off via I
66-MHz Clock Output:
USB Clock Output:
Dot Clock Output:
Clock Function Selection pins:
tions. See Table 1 for detailed descriptions.
Power-Down Control:
vice in power -down mode when held LOW.
CPU Clock Outputs:
port. Output frequencie s run at 66 MHz, 100 MHz, or 133 MHz depending on the
configura ti on of SEL0:1 and SEL133. Voltage swi ng set by VDDQ2.
SDRAM Clock Outputs:
O
individually turned off via I
Synchronous APIC Cloc k Outputs :
PCI clock outputs (33 MHz). Voltage swing set by VDDQ2.
3.3V Power Connection:
P
buffers, 3V66 output buffers, reference output buffers, and 48 -MHz output buff ers.
Connect to 3.3V.
3.3V Power Connection:
3.3V.
2.5V Power Connection:
nect to 2.5V or 3.3V.
Ground Connections:
G
plane.
Ground Connections:
plane.
W228B
3.3V 14.318-MHz cloc k output. This pin also serves as a strap
This pin has dual functi ons. It can be used as an ext ernal
A connection f or an external 14.318-MHz crystal. If using an ex-
2
C interface.
2
C circuitry.
2
C circuitry.
3.3V 33-MHz PCI clock outpu ts. PCI1 can be i ndividually
3.3V fix ed 66-MHz clock.
3.3V fixed 48-MHz , non-spread spectrum USB clock output.
3.3V 48-MHz, non-spread spectrum signal.
LVTTL-compatible input to select device func-
LVTTL-compatible asynchronous input that places t he de-
Clock outputs for the host bus interface and integrated test
3.3V outputs running at 100 MHz. SDRAM0:12 can be
2
C interface.
Clock outputs running sync hronous wi th the
Power suppl y for SDRAM output buffers, PCI output
Power supply for core logic, PLL circuitry. Connect to
Power supply for IOAPIC and CPU output buffers. Con-
Connect all ground pins to the common system ground
Connect all ground pins to the common system ground
2
PRELIMINARY
V
DD
10 k
10k
Ω
Ω
W228B
Power-on
Reset
Timer
Output
Buffer
Output Three-state
Hold
Output
Low
QD
Data
Latch
(Load Option 1)
(Load Option 0)
Figure 1. Input Logic Selection Through Resistor Load Option
W228B
Output Strapping Resistor
Series Termination Resistor
Clock Load
Overview
tor should be used. Figure 1 shows a suggested method for
strapping res istor connections.
The W228B is a highly integrated fr equency timing generator,
supplying all the required clock sources for an Intel® architecture platform using graphics in tegrated core logic.
Functional Description
I/O Pin Operation
REF0/FSEL1 is a dual-purpose l/O pin. Upon po wer- up the pi n
acts as a logic input for FSEL1 selecti on (see Table 1 and Table
2). If the pin is strapped to a HIGH state externally, CPU will
be strappe d LOW. CPU clock outputs wi ll be determined b y the
status of SEL0:1 i nput pins. An external 10- kΩ strapping r esis-
After 2 ms, the pin becomes an output. Assuming the power
supply has stabilized by then, the specified output frequency
is delivered on the pins. If the power supply has not yet
reached full value , output frequency initially may be below tar-
get but will increase to target once supply voltage has stabi-
lized. In either case, a short output clock cycle may be pro-
duced from the CPU clock outputs when the outputs are
enabled.
Pin Selectable Functions
Table 2 outlines the device functions selectable through
Tr istate# and FSEL0:1. Specific outputs available at each pin
are detailed in Ta ble 2 below.
Table 2. CK Whitney Truth Table
Tristate# FSEL0 FSEL1 CPU SDRAM 3V66 PCI 48MHz REF APIC Notes
0 0 X Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 2
0 1 X TCLK/4 TCLK/4 TCLK/6 TCLK/12 TCLK/2 TCLK TCLK/12 4, 5
1 0 0 66 MHz 100 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 33 MHz 3, 6, 7
1 1 0 100 MHz 100 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 33 MHz 3, 6, 7
1 0 1 133 MHz 133 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 33 MHz 3, 6, 7
1 1 1 133 MHz 100 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 33 MHz 3, 6, 7
Notes:
2. Provided for board-level “bed of nails” testing.
3. “Normal” mode of operation.
4. TCLK is a test clock overdriven on the XTAL_IN input during test mode.
5. Required for DC output impedance verification.
6. Range of reference frequency allowed is min. = 14.316 MHz, nominal = 14.31818 MHz, max. = 14.32 MHz.
7. Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
3
PRELIMINARY
W228B
Offsets Among Clock Signal Groups
Figure 2 and Figur e 3 represe nt the pha se r elation shi p amon g
the different groups of clock outputs from W228B when it is
providing a 66-MHz CPU clock and a 100-MHz CPU clock,
0 ns
CPU 66-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
APIC33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Cycle Repeat
Figure 2. Group Offset Waveforms (66-MHz CPU/100-MHz SDRAM Clock)
respectively. It should be noted that when the CPU clock is
operating at 100 MHz, CPU cloc k out put is 18 0 deg rees out of
phase with SDRAM clock outputs.
40 ns30 ns20 ns10 ns
CPU 100-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
APIC 33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
0 ns
Cycle Repeat
Figure 3. Group Offset Waveforms (100-MHz CPU/100- MHz SDRAM Clock)
40 ns30 ns20 ns10 ns
4
PRELIMINARY
W228B
CPU 133-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
APIC 33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
CPU 100-MHz
0 ns
Cycle Repeats
Figure 4. Group Offset Waveforms (133-MHz CPU/100- MHz SDRAM Clock)
0 ns
Cycle Repeat
40 ns30 ns20 ns10 ns
40 ns30 ns20 ns10 ns
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
APIC 33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Figure 5. Group Offset Waveforms (133-MHz CPU/133- MHz SDRAM Clock)
5
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