CYPRESS W219B User Manual

PRELIMINARY

Frequency Generator for Integrated Core Logi c

Features

• Maximized EMI suppression using Cypress’s Spread
Spectrum technology

• Low jitter and tightly controlled clock skew

• Highly integrated device provi ding clocks requ ired for
CPU, core logic, and SDRAM

• Two copies of CPU clock

• Nine copies of SDRAM clock

• Seven copies of PCI clock

• One copy of synchronous APIC clock

• Three copies of 66-MHz outputs

• Two copies of 48-MHz outputs

• One copy of selectable 24- or 48-MHz clock

• One copy of double strength 14.31818-MHz reference
clock

• Power-down control

• SMBus interface for turning off unused clocks

Key Specifications

CPU, SDRAM Outputs Cycle-to-Cycle Jitter: .............250 ps

APIC, 48-MHz, 3V66, PCI Outputs

Cycle-to-Cycle Jitter:............................... ....................500 ps

CPU, 3V66 Output Skew:...........................................175 ps

SDRAM, APIC, 48-MHz Output Skew:....................... 250 ps

PCI Output Skew:....................................................... 500 ps

CPU to SDRAM Skew (@ 133 MHz) .......................± 0.5 ns

CPU to SDRAM Skew (@ 100 MHz).................4.5 to 5.5 ns

CPU to 3V66 Skew (@ 66 MHz)........................7.0 to 8.0 ns

3V66 to PCI Skew (3V66 lead).......................... 1.5 to 3.5 ns

PCI to APIC Skew.....................................................± 0.5 ns

Block Diagram

PWR_DWN#

SDATA

SCLK

(FS0:4*)

X1

XTAL

X2

OSC

SMBus
Logic

PLL 1

PLL2

PLL REF FREQ

Divider,

Delay,

and

Phase

Control

Logic

/2

VDDQ3

REF2X/FS3*

VDDQ2
CPU0:1

2

APIC

VDDQ3

3V66_0:2

2

PCI0/FS0*
PCI1/FS1*

PCI2/FS2*
PCI3:6

5

SDRAM0:8

9

VDDQ3

48MHz_0
48MHz_1/FS 4*

SI0/24_48#MHz*

W219B

with 133-MHz FSB

Table 1. Frequency Selections

FS4 FS3 FS2 FS1 FS0 CPU SDRAM 3V66 PCI APIC SS

0 0 0 0 0 75.3 113.0 75.3 37.6 18.8 OFF
0 0 0 0 1 95.0 95.0 63.3 31.6 15.8 –0.6%
0 0 0 1 0 129.0 129.0 86.0 43.0 21.5 OFF
0 0 0 1 1 150.0 113.0 75.3 37.6 18.8 OFF
0 0 1 0 0 150.0 150.0 75.0 37.5 18.7 OFF
0 0 1 0 1 110.0 110.0 73.0 36.6 18.3 OFF
0 0 1 1 0 140.0 140.0 70.0 35.0 17.5 OFF
0 0 1 1 1 144.0 108.0 72.0 36.0 18.0 OFF
0 1 0 0 0 68.3 102.5 68.3 34.1 17.0 OFF
0 1 0 0 1 105.0 105.0 70.0 35.0 17.5 OFF
0 1 0 1 0 138.0 138.0 69.0 34.5 17.0 OFF
0 1 0 1 1 140.0 105.0 70.0 35.0 17.5 OFF
0 1 1 0 0 66.8 100.2 66.8 33.4 16.7 ±0.45%
0 1 1 0 1 100.2 100.2 66.8 33.4 16.7 ±0.45%
0 1 1 1 0 133.6 133.6 66.8 33.4 16.7 ±0.45%
0 1 1 1 1 133.6 100.2 66.8 33.4 16.7 ±0.45%
1 0 0 0 0 157.3 118.0 78.6 39.3 19.6 OFF
1 0 0 0 1 160.0 120.0 80.0 40.0 20.0 OFF
1 0 0 1 0 146.6 110.0 73.3 36.6 18.3 OFF
1 0 0 1 1 122.0 91.5 61.0 30.5 15.2 –0.6%
1 0 1 0 0 127.0 127.0 84.6 42.3 21.1 OFF
1 0 1 0 1 122.0 122.0 81.3 40.6 20.3 –0.6%
1 0 1 1 0 117.0 117.0 78.0 39.0 19.5 OFF
1 0 1 1 1 114.0 114.0 76.0 38.0 19.0 OFF
1 1 0 0 0 80.0 120.0 80.0 40.0 20.0 OFF
1 1 0 0 1 78.0 117.0 78.0 39.0 19.5 OFF
1 1 0 1 0 166.0 124.5 83.0 41.5 20.7 OFF
1 1 0 1 1 133.6 133.6 89.0 44.5 22.2 OFF
1 1 1 0 0 66.6 100.0 66.6 33.3 16.6 –0.6%
1 1 1 0 1 100.0 100.0 66.6 33.3 16.6 –0.6%
1 1 1 1 0 133.3 133.3 66.6 33.3 16.6 –0.6%
1 1 1 1 1 133.3 100.0 66.6 33.3 16.6 –0.6%

Pin Configuration

REF2x/FS3*

VDDQ3

VDDQ3
3V66_0
3V66_1
3V66_2

FS0*/PCI0
FS1*/PCI1

FS2*/PCI2

VDDQ3

48MHz_0

FS4*/48MHz_1

SI0/24_48#MHz*

VDDQ3

Note:

1. Internal 250K pull-down or pull up resistors present on inputs
marked with * or ^ respectively. Design should not rely solely on
internal pull-up or pull down resistor to set I/O pins HIGH or LOW
respectively.

GND

GND

GND
PCI3
PCI4

PCI5
PCI6
GND

1
2

X1

3

X2

4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

[1]

VDDQ2

48
47

APIC

46

VDDQ2

45

CPU0

44

CPU1

43

GND

42

VDDQ3

41

SDRAM0

40

SDRAM1
SDRAM2

39

W219B

38
37
36
35
34
33
32
31
30
29
28
27
26
25

GND
SDRAM3
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
SDRAM8
GND
PWR_DWN#
SCLK
VDDQ3
GND
SDATA

^

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07220 Rev. *A Revised December 21,2002

PRELIMINARY

I

W219B

Pin Definitions

Pin Name Pin No.

REF2x/FS3 1 I/O Reference Clock with 2x Drive/Frequency Select 3: 3.3V 14.3 18-MHz c lock out-

X1 3 I Crystal Input: This pin has dual functions. It can be used as an external 14.318-

X2 4 I Crystal Output: An input connection for an external 14.318-MHz crystal connec-

PCI0/FS0 11 I/O PCI Clock 0/Frequency Selection 0 : 3.3V 33-MHz PCI clock outputs. This pin also

PCI1/FS1 12 I/O PCI Clock 1/Frequency Selection 1 : 3.3V 33-MHz PCI clock outputs. This pin also

PCI2/FS2 13 I/O PCI Clock 2/Frequency Selection 2 : 3.3V 33-MHz PCI clock outputs. This pin also

PCI3:6 15, 16, 18, 19 O PCI Clock 3 through 6: 3.3V 33-MHz PCI clock outputs. PCI0:6 can be individually

3V66_0:2 7, 8, 9 O 66-MHz Clock Output: 3.3V output clocks. The operating frequency is controlled

48MHz_0 21 O 48-MHz Clock Output: 3.3V fixed 48-MHz, non-spread spectrum clock output.
48MHz_1/

FS4

SIO/
24_48#MHz

PWR_DWN# 29 I Power Down Control: LVTTL-compatible input that places the device in power-

CPU0:1 45, 44 O CPU Clock Outputs: Clock outputs for the host bu s inter face. O utput fre quenc ies

SDRAM0:8 41, 40, 39, 37,

APIC 47 O Synchronous APIC Clock Outputs: Clock outputs ru nning syn chrono us wi th the

SDATA 25 I/O Data pin for SMBus circuitry.
SCLK 28 I Clock pin for SMBus circuitry.
VDDQ3 2, 6, 17, 24, 27,

VDDQ2 46, 48 P 2.5V Power Connection: Power supply for IOAPIC and CPU o utput buffers. Con-

GND 5, 10, 14, 20, 26,

22 I/O 48-MHz Clock Output/Frequency Selection 4: 3.3V fixed 48-MHz, non-spread

23 I/O Clock Output for Super I/O: This is the input clock for a Super I/O (SIO) device.

36, 35, 33, 32,

31

34, 42

30, 38, 43,

Pin

Type Pin Description

put. This pin also serves as the select strap to determine device ope rating frequency
as described in Table 1.

MHz crystal connection or as an external reference frequency input.

tion. If using an external reference, this pin must be left unconnected.

serves as the s elect st rap to det ermine d evice operating frequenc y as de scribed in
Table 1.

serves as the s elect st rap to det ermine d evice operating frequenc y as de scribed in
Table 1.

serves as the s elect st rap to det ermine d evice operating frequenc y as de scribed in
Table 1.

turned off via SMBus interface.

by FS0:4 (see Table 1).

spectrum clock ou tput. This pin al so serv es as the select strap t o determi ne devi ce
operating frequency as described in Table 1.

During power-up, it als o serves as a selection s trap. If it is sampled HIGH, the output
frequency for SIO is 24 MHz. If the input is sampled LOW, the output is 48 MHz.

down mode when held LOW.

depending on the configuration of FS0:4. Voltage swing is set by VDDQ2.

O SDRAM Clock Outputs: 3.3V outputs for SDRAM. The operating frequency is

controlled by FS0:4 (see Table 1).

PCI clock outputs. Voltage swing set by VDDQ2.

P 3.3V Power Con nection: Power supply for SDRAM output buffers, PCI outpu t buff-

ers, reference output buffers and 48-MHz output buffers. Connect to 3.3V.

nect to 2.5V or 3.3V.

G Ground Connections: Connect all ground pins to the common system ground

plane.

Document #: 38-07220 Rev. *A Page 2 of 15

PRELIMINARY

W219B

Power-on
Reset
Timer

Output Three-state

Figure 1. Input Logic Selection Through Resistor Load Option

Overview

The W219B is a highl y i nteg rate d frequency timing gene rator,
supplying all the requi red clock sou rces for an Intel® architec-
ture platform using graphics integrated core logic.

Functional Description

I/O Pin Operation

Pin # 1, 1 1, 12, 13, 22, and 23 are dual-purpose l/O pins . Upon
power-up the pin acts as a logic input. An external 10-kΩ strap­ping resistor should be used. Figure 1 shows a suggested
method for strapping resistor conn ec tio ns .

After 2 ms, the pin becomes an output. Assuming the power
supply has stabilized by then, the specified output frequency

Output
Buffer

Hold
Output
Low

QD

Data

Latch

W219B

Output Strapping Resistor

Series Termination Resistor

Clock Load

10k

Ω

is delivered on the pins. If the power supply has not yet
reached full value, o utput frequen cy initia lly may be below tar­get but will increase to target once supply voltage has stabi­lized. In either case, a short output clock cycle may be pro­duced from the CPU clock outputs when the outputs are
enabled.

Offsets Among Clock Signal Groups

Figure 2 and Figure 3 represent the phase relationship amon g
the different groups of clo ck outputs from W219B when it is
providing a 66-MHz CPU clock and a 100-MHz CPU clock,
respectively. It should be noted that when CPU clock is oper­ating at 100 MHz, CPU clock output is 180 degrees out of
phase with SDRAM clock outputs.

CPU 66-MHz

SDRAM 100-MHz

3V66 66-MHz

PCI 33-MHz

REF 14.318-MHz

USB 48-MHz
APIC

0 ns

CPU 66 Period

SDRAM 100 Period

Hub-PC

Figure 2. Group Offset Waveforms (66.8 CPU Clock, 100.2 SDRAM Clock)

40 ns30 ns20 ns10 ns

Document #: 38-07220 Rev. *A Page 3 of 15

CPU 100-MHz

SDRAM 100-MHz

3V66 66-MH z

PCI 33-MHz

REF 14.318-MHz

USB 48-MHz

APIC

0 ns

PRELIMINARY

40 ns30 ns20 ns10 ns

CPU 100 Period

SDRAM 100 Period

Hub-PC

W219B

Figure 3. Group Offset Waveforms (100.2 CPU Clock, 100.2 SDRAM Clock)

Power-Down Control

W219B provides one PWRDWN # s ignal to pla ce the d evic e in low-p ower mo de. In low -powe r mode , the PLLs a re turne d of f an d
all clock outputs are driven LOW.

0 ns 25 ns 50 ns 75 ns

Center

1 2

VCO Internal

CPU 100MHz

3V66 66MHz

APIC 33MHz

PCI 33MHz

PwrDwn

SDRAM 100MHz

REF 14.318MHz

USB 48MHz

Figure 4. PWRDWN# Timing Diagram

Notes:

2. Once the PWRDWN# signal is sampled LOW for two consecutive rising edges of CPU, clocks of interest will be held LOW on the next HIGH-to-LOW transition.

3. PWRDWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W219B.

4. The shaded sections on the SDRAM, REF, and USB clocks indicate “Don’t Care” states.

5. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz.

[2, 3, 4, 5]

Document #: 38-07220 Rev. *A Page 4 of 15

PRELIMINARY

Spread Spectrum Frequency Timing Generator

The device generates a clock that is frequency modulated in
order to increase th e bandwidt h that it occu pies. By inc reasing
the bandwidth of the fundamental and its harmonics, the am­plitudes of the radiated electromagnetic emissions are re­duced. This effect is depicted in Figure 5.

As shown in Figure 5, a harmonic of a modulated clock has a
much lower amplit ude than that of an unmodulated si gnal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:

dB = 6.5 + 9*log

SSFTG

Amplitude (dB)

(P) + 9*log10(F)

10

Typical Clock

W219B

Where P is the pe rcentage of deviation and F is the frequenc y
in MHz where the reduction is measured.

The output clock is modulated with a waveform depicted in
Figure 6. This waveform, as discusse d in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emi ssions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is ±0.45% or –0.6% of the se­lected frequency. Figure 6 details the Cypress spreading pat­tern. Cypress does of fer option s with more spread a nd greater
EMI reduction. Con tact your l ocal Sales re presen tative for d e­tails on these devices.

EMI Reduction

Spread

Spectrum

Enabled

Amplitude (dB)

Non-

Spread

Spectrum

Frequency Span (MHz)

Center Spread

Frequency Span (MHz)

Down Spread

Figure 5. Clock Harmonic with and without SSCG Modu lation Frequency Do main Representation

MAX.

10%

20%

30%

40%

50%

60%

70%

80%

FREQUENCY

MIN.

90%

100%

10%

20%

30%

40%

50%

60%

70%

80%

Figure 6. Typical Modulation Profile

90%

100%

Document #: 38-07220 Rev. *A Page 5 of 15