CYPRESS CY2292 User Manual
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CY2292
Three-PLL General-Purpose
EPROM Programmable Clock Generato
Features
• Three integrated phase-locked loops
• EPROM programmability
• Factory-programmable (CY2292) or field-programmable (CY2292F) device options
• Low-skew, low-jitter, high-accuracy outputs
• Power-management options (Shutdown, OE, Suspend)
• Frequency select option
• Smooth slewing on CPUCLK
• Configurable 3.3V or 5V operation
• 16-pin SOIC Package (TSSOP: F only)
Benefits
• Generates up to three custom frequencies from
external sources
• Easy customization and fast turnaround
• Programming support available for all opportunities
• Meets critical industry standard timing requirements
• Supports low-power applications
• Eight user-selectable frequencies on CPU PLL
• Allows downstream PLLs to stay locked on CPUCLK
output
• Enables application compatibility
• Industry-standard packaging saves on board space
Selector Guide
Part Number Outputs Input Frequency Range Output Frequency Range Specifics
CY2292 6 10 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
CY2292I 6 10 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
CY2292F 6 10 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
CY2292FI 6 10 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
CY2292FZ 6 10 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
76.923 kHz–100 MHz (5V)
76.923 kHz–80 MHz (3.3V)
76.923 kHz–90 MHz (5V)
76.923 kHz–66.6 MHz (3.3V)
76.923 kHz–90 MHz (5V)
76.923 kHz–66.6 MHz (3.3V)
76.923 kHz–80 MHz (5V)
76.923 kHz–60.0 MHz (3.3V)
76.923 kHz–90 MHz (5V)
76.923 kHz–66.6 MHz (3.3V)
Factory Programmable
Commercial Temperature
Factory Programmable
Industrial Temperature
Field Programmable
Commercial Temperature
Field Programmable
Industrial Temperature
Field Programmable
Commercial Temperature
Logic Block Diagram
XTALIN
XTALOUT
S2/SUSPEND
SHUTDOWN
S0
S1
OE
.
OSC.
CPLL
(8 BIT)
UPLL
(10 BIT)
SPLL
(8 BIT)
/
/1,2,4
/1,2,4,8
/1,2,3,4,5,6
/8,10,12,13
/20,24,26,40
/48,52,96,104
CONFIG
EPROM
MUX
XBUF
CPUCLK
CLKA
CLKB
CLKC
CLKD
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07449 Rev. *B Revised October 12, 2004
CY2292
Pin Configurations
CY2292
16-pin SOIC
CLKC
V
DD
GND
XTALIN
XTALOUT
XBUF
CLKD
CPUCLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Pin Summary
Name
CLKC 1 Configurable clock output C.
V
DD
GND 3, 11 Ground.
XTALIN
XTALOUT
[1]
[1, 2]
XBUF 6 Buffered reference clock output.
CLKD 7 Configurable clock output D.
CPUCLK 8 CPU frequency clock output.
CLKB 9 Configurable clock output B.
CLKA 10 Configurable clock output A.
S0 12 CPU clock select input, bit 0.
S1 13 CPU clock select input, bit 1.
S2/SUSPEND
SHUTDOWN/OE 16 Places outputs in three-state
Pin Number
CY2292 Description
2, 14 Voltage supply.
4 Reference crystal input or external reference clock input.
5 Reference crystal feedback.
15 CPU clock select input, bit 2. Optionally enables suspend feature when LOW.
[4]
places outputs in three-state
[4]
SHUTDOWN/OE
S2/SUSPEND
V
DD
S1
S0
GND
CLKA
CLKB
[3]
condition and shuts down chip when LOW. Optionally, only
condition and does not shut down chip when LOW.
Operation
this crystal. Alternatively, an external reference clock of
frequency between 1 MHz and 30 MHz can be used.
The CY2292 is a third-generation family of clock generators.
The CY2292 is upwardly compatible with the industry standard
Output Configuration
ICD2023 and ICD2028 and continues their tradition by
providing a high level of customizable features to meet the
diverse clock generation needs of modern motherboards and
other synchronous systems.
All parts provide a highly configurable set of clocks for PC
motherboard applications. Each of the four configurable clock
outputs (CLKA–CLKD) can be assigned 1 of 30 frequencies in
any combination. Multiple outputs configured for the same or
[3]
related
frequencies will have low (≤ 500 ps) skew, in effect
providing on-chip buffering for heavily loaded signals.
The CY2292 can be configured for either 5V or 3.3V operation.
The internal ROM tables use EPROM technology, allowing full
customization of output frequencies. The reference oscillator
has been designed for 10-MHz to 25-MHz crystals, providing
additional flexibility. No external components are required with
Notes:
1. For best accuracy, use a parallel-resonant crystal, C
2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to crystal).
3. Please refer to application note “Understanding the CY2291, CY2292 and CY2295” for more information.
4. The CY2292 has weak pull-downs on all outputs. Hence, when a three-state condition is forced on the outputs, the output pins are pulled LOW.
≈ 17 pF or 18 pF.
LOAD
The CY2292 has four independent frequency sources on-chip.
These are the reference oscillator, and three Phase-Locked
Loops (PLLs). Each PLL has a specific function. The System
PLL (SPLL) provides fixed output frequencies on the config-
urable outputs. The SPLL offers the most output frequency
divider options. The CPU PLL (CPLL) is controlled by the
select inputs (S0–S2) to provide eight user-selectable
frequencies with smooth slewing between frequencies. The
Utility PLL (UPLL) provides the most accurate clock. It is often
used for miscellaneous frequencies not provided by the other
frequency sources.
All configurations are EPROM programmable, providing short
sample and production lead times. Please refer to the appli-
cation note Understanding the CY2291, CY2292, and CY2295
for information on configuring the part.
Document #: 38-07449 Rev. *B Page 2 of 11
CY2292
Power-Saving Features
The SHUTDOWN/OE input three-states the outputs when
pulled LOW. If system shutdown is enabled, a LOW on this pin
also shuts off the PLLs, counters, the reference oscillator, and
all other active components. The resulting current on the V
pins will be less than 50 µA (for commercial temperature or
100 µA for industrial temperature). After leaving shutdown
mode, the PLLs will have to relock. All outputs have a weak
pull-down so that the outputs do not float when three-stated.
The S2/SUSPEND input can be configured to shut down a
customizable set of outputs and/or PLLs, when LOW. All PLLs
and any of the outputs can be shut off in nearly any combination. The only limitation is that if a PLL is shut off, all outputs
derived from it must also be shut off. Suspending a PLL shuts
off all associated logic, while suspending an output simply
forces a three-state condition.
The CPUCLK can slew (transition) smoothly between 20 MHz
and the maximum output frequency (100 MHz at 5V/80 MHz
at 3.3V for Commercial Temp. parts or 90 MHz at 5V/66.6 MHz
at 3.3V for Industrial Temp. and for field-programmed parts).
This feature is extremely useful in “Green” PC and laptop
applications, where reducing the frequency of operation can
result in considerable power savings. This feature meets all
486 and Pentium
®
processor slewing requirements.
[3]
DD
[4]
CyClocks Software
CyClocks is an easy-to-use application that allows you to
configure any one of the EPROM-programmable clocks
offered by Cypress. You may specify the input frequency, PLL
and output frequencies, and different functional options.
Please note the output frequency ranges in this data sheet
when specifying them in CyClocks to ensure that you stay
within the limits. CyClocks also has a power calculation feature
that allows you to see the power consumption of your specific
configuration. You can download a copy of CyClocks for free
on Cypress’s web site at www.cypress.com.
Cypress FTG Programmer
The Cypress Frequency Timing Generator (FTG) Programmer
is a portable programmer designed to custom program our
family of EPROM Field Programmable Clock Devices. The
FTG programmers connect to a PC serial port and allow users
of CyClocks software to quickly and easily program any of the
CY2291F, CY2292F, CY2071AF, and CY2907F devices. The
ordering code for the Cypress FTG Programmer is CY3670.
Custom Configuration Request Procedure
The CY229x are EPROM-programmable devices that may be
configured in the factory or in the field by a Cypress Field Appli-
cation Engineer (FAE). The output frequencies requested will
be matched as closely as the internal PLL divider and multi-
plier options allow. All custom requests must be submitted to
your local Cypress FAE or sales representative. The method
to use to request custom configurations is:
Use CyClocks software. This software automatically calcu-
lates the output frequencies that can be generated by the
CY229x devices and provides a print-out of final pinout which
can be submitted (in electronic or print format) to your local
FAE or sales representative. The CyClocks software is
available free of charge from the Cypress web site
(http://www.cypress.com) or from your local sales represen-
tative.
Once the custom request has been processed you will receive
a part number with a 3-digit extension (e.g., CY2292SC-128)
specific to the frequencies and pinout of your device. This will
be the part number used for samples requests and production
orders.
Document #: 38-07449 Rev. *B Page 3 of 11
CY2292
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Supply Voltage............................................... –0.5V to +7.0V
DC Input Voltage............................................–0.5V to +7.0V
Storage Temperature ................................. –65°C to +150°C
Max. Soldering Temperature (10 sec) ......................... 260°C
Junction Temperature .................................................. 150°C
Package Power Dissipation...................................... 750 mW
Static Discharge Voltage.............................................≤ 2000V
(per MIL-STD-883, Method 3015)
Operating Conditions
[5]
Parameter Description Part Numbers Min. Max. Unit
V
DD
V
DD
T
A
Supply Voltage, 5.0V operation All 4.5 5.5 V
Supply Voltage, 3.3V operation All 3.0 3.6 V
Commercial Operating Temperature, Ambient CY2292/CY2292F 0 +70 °C
Industrial Operating Temperature, Ambient CY2292I/CY2292FI −40 +85 °C
C
C
f
REF
LOAD
LOAD
Max. Load Capacitance 5.0V Operation All 25 pF
Max. Load Capacitance 3.3V Operation All 15 pF
External Reference Crystal All 10.0 25.0 MHz
External Reference Clock
[6, 7, 8]
All 1 30 MHz
Electrical Characteristics, Commercial 5.0V
Parameter Description Conditions Min. Typ. Max. Unit
V
V
V
V
I
IH
I
IL
I
OZ
I
DD
I
DDS
OH
OL
IH
IL
HIGH-Level Output Voltage IOH = 4.0 mA 2.4 V
LOW-Level Output Voltage IOL = 4.0 mA 0.4 V
[9]
[9]
Except crystal pins 2.0 V
Except crystal pins 0.8 V
– 0.5V <1 10 µA
DD
HIGH-Level Input Voltage
LOW-Level Input Voltage
Input HIGH Current VIN = V
Input LOW Current VIN = +0.5V <1 10 µA
Output Leakage Current Three-state outputs 250 µA
VDD Supply Current
VDD Power Supply Current in Shutdown Mode
[10]
Commercial VDD = VDD max., 5V operation 75 100 mA
[10]
Shutdown active CY2292/CY2292F 10 50 µA
Electrical Characteristics, Commercial 3.3V
Parameter Description Conditions Min. Typ. Max. Unit
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
I
OZ
I
DD
I
DDS
Notes:
5. Electrical parameters are guaranteed by design with these operating conditions, unless otherwise noted.
6. External input reference clock must have a duty cycle between 40% and 60%, measured at V
7. Please refer to application note “Crystal Oscillator Topics” for information on AC-coupling the external input reference clock.
8. The oscillator circuit is optimized for a crystal reference and for external reference clocks up to 20 MHz. For external reference clocks above 20 MHz, it is
recommended that a 150Ω pull-up resistor to V
9. Xtal inputs have CMOS thresholds.
10. Load = Max., V
formula (multiply by 0.65 for 3V operation): I
Document #: 38-07449 Rev. *B Page 4 of 11
HIGH-Level Output Voltage IOH = 4.0 mA 2.4 V
LOW-Level Output Voltage IOL = 4.0 mA 0.4 V
HIGH-Level Input Voltage
LOW-Level Input Voltage
Input HIGH Current VIN = V
[9]
[9]
Except crystal pins 2.0 V
Except crystal pins 0.8 V
– 0.5V < 1 10 µA
DD
Input LOW Current VIN = +0.5V < 1 10 µA
Output Leakage Current Three-state outputs 250 µA
VDD Supply Current
VDD Power Supply Current in Shutdown Mode
= 0V or VDD, Typical (–104) configuration, CPUCLK = 66 MHz. Other configurations will vary. Power can be approximated by the following
IN
[10]
Commercial VDD = VDD Max., 3.3V operation 50 65 mA
[10]
Shutdown active CY2292/CY2292F 10 50 µA
/2.
DD
be connected to the Xout pin.
DD
=10+0.06•(F
DD
CPLL+FUPLL
+2•F
SPLL
)+0.27•(F
CLKA+FCLKB+FCLKC+FCLKD+FCPUCLK+FXBUF
).
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