CYPRESS CY22050 User Manual
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CY22050
One-PLL General Purpose
Flash Programmable Clock Generato
Features Benefits
• Integrated phase-locked loop (PLL) Internal PLL to generate six outputs up to 200 MHz. Able to generate
• Commercial and Industrial operation Performance guaranteed for applications that require an extended temper-
• Flash-programmable Reprogrammable technology allows easy customization, quick turnaround
• Field-programmable In-house programming of samples and prototype quantities is available
• Low-skew, low-jitter, high-accuracy outputs High performance suited for commercial, industrial, networking, telecomm
• 3.3V operation with 2.5V output option Application compatibility in standard and low-power systems.
• 16-lead TSSOP Industry standard packaging saves on board space.
custom frequencies from an external reference crystal or a driven source.
ature range.
on design changes and product performance enhancements, and better
inventory control. Parts can be reprogrammed up to 100 times, reducing
inventory of custom parts and providing an easy method for upgrading
existing designs.
using the CY3672 FTG Development Kit. Production quantities are
available through Cypress’s value-added distribution partners or by using
third party programmers from BP Microsystems, HiLo Systems, and
others.
and other general-purpose applications.
Part Number Outputs Input Frequency Range Output Frequency Range Specifications
CY22050FC 6 8 MHz–30 MHz (external crystal)
1 MHz–133 MHz (driven clock)
CY22050FI 6 8 MHz–30 MHz (external crystal)
1 MHz–133 MHz (driven clock)
Logic Block Diagram
XIN
XOUT
OE
Pin Configuration
OSC.
Q
Φ
P
AVDD
AVDD
PWRDWN
LCLK1
LCLK2
VCO
PLL
AVSS
XIN
VDD
AVSS
VSSL
VSS
1
2
3
4
5
6
7
8
80 kHz–200 MHz (3.3V)
80 KHz–166.6 MHz (2.5V)
80 kHz–166.6 MHz (3.3V)
80 KHz–150 MHz (2.5V)
Divider
Bank 1
Divider
Bank 2
VDDL
VSSLVDD
PWRDWN
XOUT
16
15
CLK6
14
CLK5
13
VSS
12
LCLK4
11
VDDL
10
OE
9
LCLK3
Field-programmable
commercial temperature
Field-programmable
industrial temperature
Output
Select
Matrix
LCLK1
LCLK2
LCLK3
LCLK4
CLK5
CLK6
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07006 Rev. *D Revised January 29, 2005
CY22050 Pin Summary
Name Pin Number Description
XIN 1 Reference Input. Driven by a crystal (8 MHz–30 MHz) or external clock (1 MHz–133 MHz).
Programmable input load capacitors allow for maximum flexibility in selecting a crystal, based
on manufacturer, process, performance, or quality.
VDD 2 3.3V voltage supply
AVD D 3 3.3V analog voltage supply
PWRDWN
LCLK1 7 Configurable clock output 1 at V
LCLK2 8 Configurable clock output 2 at V
LCLK3 9 Configurable clock output 3 at V
LCLK4 12 Configurable clock output 4 at V
XOUT
[1]
4 Power Down. When pin 4 is driven LOW, the CY22050 will go into shut-down mode.
AVSS 5 Analog ground
VSSL 6 LCLK ground
DDL
DDL
DDL
OE
[1]
10 Output Enable. When pin 10 is driven LOW, all outputs are three-stated.
VDDL 11 LCLK voltage supply (2.5V or 3.3V)
DDL
VSS 13 Ground
CLK5 14 Configurable clock output 5 (3.3V)
CLK6 15 Configurable clock output 6 (3.3V)
[2]
16 Reference output
level (3.3V or 2.5V)
level (3.3V or 2.5V)
level (3.3V or 2.5V)
level (3.3V or 2.5V)
CY22050
Functional Description
The CY22050 is the next-generation programmable FTG
(frequency timing generator) for use in networking, telecommunication, datacom, and other general-purpose applications.
The CY22050 offers up to six configurable outputs in a 16-pin
TSSOP, running off a 3.3V power supply. The on-chip
reference oscillator is designed to run off an 8–30-MHz crystal,
or a 1–133-MHz external clock signal.
The CY22050 has a single PLL driving 6 programmable output
clocks. The output clocks are derived from the PLL or the
reference frequency (REF). Output post dividers are available
for either. Four of the outputs can be set as 3.3V or 2.5V, for
use in a wide variety of portable and low-power applications.
Field Programming the CY22050F
The CY22050 is programmed at the package level, i.e., in a
programmer socket. The CY22050 is flash-technology based,
so the parts can be reprogrammed up to 100 times. This allows
for fast and easy design changes and product updates, and
eliminates any issues with old and out-of-date inventory.
Samples and small prototype quantities can be programmed
on the CY3672 programmer. Cypress’s value-added distribution partners and third-party programming systems from BP
Microsystems, HiLo Systems, and others are available for
large-production quantities.
CyClocksRT Software
CyClocksRT™ is an easy-to-use software application that
allows the user to custom-configure the CY22050. Users can
specify the REF, PLL frequency, output frequencies and/or
post-dividers, and different functional options. CyClocksRT
outputs an industry-standard JEDEC file used for
programming the CY22050.
CyClocksRT can be downloaded free of charge from the
Cypress website at http://www.cypress.com.
CY3672 FTG Development Kit
The Cypress CY3672 FTG Development Kit comes complete
with everything needed to design with the CY22050 and
program samples and small prototype quantities. The kit
comes with the latest version of CyClocksRT and a small
portable programmer that connects to a PC serial port for
on-the-fly programming of custom frequencies.
The JEDEC file output of CyClocksRT can be downloaded to
the portable programmer for small-volume programming, or
for use with a production programming system for larger
volumes.
Applications
Controlling Jitter
Jitter is defined in many ways, including: phase noise,
long-term jitter, cycle-to-cycle jitter, period jitter, absolute jitter,
and deterministic jitter. These jitter terms are usually given in
terms of rms, peak-to-peak, or in the case of phase noise
dBC/Hz with respect to the fundamental frequency. Actual
jitter is dependent on XIN jitter and edge rate, number of active
outputs, output frequencies, V
and output load.
Power supply noise and clock output loading are two major
system sources of clock jitter. Power supply noise can be
mitigated by proper power supply decoupling (0.1-µF ceramic
cap) of the clock and ensuring a low-impedance ground to the
(2.5V or 3.3V), temperature,
DDL
Notes:
1. The CY22050 has no internal pull-up or pull-down resistors. PWRDWN
2. Float XOUT if XIN is driven by an external clock source.
and OE pins need to be driven as appropriate or tied to power or ground.
Document #: 38-07006 Rev. *D Page 2 of 9
CY22050
chip. Reducing capacitive clock output loading to a minimum
lowers current spikes on the clock edges and thus reduces
jitter.
Reducing the total number of active outputs will also reduce
jitter in a linear fashion. However, it is better to use two outputs
to drive two loads than one output to drive two loads.
The rate and magnitude that the PLL corrects the VCO
frequency is directly related to jitter performance. If the rate is
too slow, then long term jitter and phase noise will be poor.
Therefore, to improve long-term jitter and phase noise,
reducing Q to a minimum is advisable. This technique will
increase the speed of the phase frequency detector, which in
turn drives the input voltage of the VCO. In a similar manner,
increasing P until the VCO is near its maximum rated speed
will also decrease long term jitter and phase noise. For
example: input reference of 12 MHz; desired output frequency
of 33.3 MHz. One might arrive at the following solution: Set
Q = 3, P = 25, Post Div = 3. However, the best jitter results will
be Q = 2, P = 50, Post Div = 9.
For additional information, refer to the application note, “Jitter
in PLL-based Systems: Causes, Effects, and Solutions,”
available at http://www.cypress.com (click on “Application
Notes”), or contact your local Cypress Field Applications
Engineer.
CY22050 Frequency Calculation
The CY22050 is an extremely flexible clock generator with up
to six individual outputs, generated from an integrated PLL.
There are four variables used to determine the final output
frequency. They are: the input REF, the P and Q dividers, and
the post divider. The three basic formulas for determining the
final output frequency of a CY22150-based design are:
• CLK = ((REF * P)/Q)/Post Divider
• CLK = REF/Post Divider
•CLK = REF
The basic PLL block diagram is shown in Figure 1. Each of the
six clock outputs has a total of seven output options available
to it. There are six post divider options: /2 (two of these), /3, /4,
/DIV1N, and DIV2N. DIV1N and DIV2N are separately calculated and can be independent of each other. The post divider
options can be applied to the calculated PLL frequency or to
the REF directly.
In addition to the six post divider options, the seventh option
bypasses the PLL and passes the REF directly to the crosspoint switch matrix.
Clock Output Settings: Crosspoint Switch
Matrix
Each of the six clock outputs can come from any of seven
unique frequency sources. The crosspoint switch matrix
defines which source is attached to each individual clock
output. Although it may seem that there are an unlimited
number of divider options, there are several rules that should
be taken into account when selecting divider options.
Divider Bank 1
/DIV1N
REF
Q
PFD
VCO
/2
/3
P
Divider Bank 2
/4
/2
/DIV2N
Figure 1. Basic PLL Block Diagram
Clock Output Divider Definition and Notes
None Clock output source is the reference input frequency
/DIV1N Clock output uses a generated /DIV1N option from Divider Bank 1. Allowable values for DIV1N are
4 to 127. If Divider Bank 1 is not being used, set DIV1N to 8.
/2 Clock output uses a fixed /2 option from Divider Bank 1. If this option is used, DIV1N must be divisible
by 4.
/3 Clock output uses a fixed /3 option from Divider Bank 1. If this option is used, set DIV1N to 6.
/DIV2N Clock output uses a generated /DIV2N option from Divider Bank 2. Allowable values for DIV2N are
/2 Clock output uses a fixed /2 option from Divider Bank 2. If this option is used, DIV2N must be divisible
/4 Clock output 2 uses a fixed /4 option from Divider Bank 2. If this option is used, DIV2N must be
4 to 127. If Divider Bank 2 is not being used, set DIV2N to 8.
by 4.
divisible by 8.
Crosspoint
Switch
Matrix
LCLK1
LCLK2
LCLK3
LCLK4
CLK5
CLK6
Document #: 38-07006 Rev. *D Page 3 of 9
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