The information in this document is subject to change without prior notice in order to
improve reliability, design, and function and does not represent a commitment on the
part of CyberResearch, Inc.
In no event will CyberResearch, Inc. be liable for direct, indirect, special, incidental, or
consequential damages arising out of the use of or inability to use the product or
documentation, even if advised of the possibility of such damages.
This document contains proprietary information protected by copyright. All rights are
reserved. No part of this manual may be reproduced by any mechanical, electronic,
or other means in any form without prior written permission of CyberResearch, Inc.
TRADEMARKS
“CyberResearch” and “CPBF PMX-233” are trademarks of CyberResearch, Inc.
Other product names mentioned herein are used for identification purposes only and
may be trademarks and/or registered trademarks of their respective companies.
• NOTICE •
CyberResearch, Inc. does not authorize any CyberResearch product for use in life
support systems, medical equipment, and/or medical devices without the written
approval of the President of CyberResearch, Inc. Life support devices and systems are
devices or systems which are intended for surgical implantation into the body, or to
support or sustain life and whose failure to perform can be reasonably expected to
result in injury. Other medical equipment includes devices used for monitoring, data
acquisition, modification, or notification purposes in relation to to life support, life
sustaining, or vital statistic recording. CyberResearch products are not designed with
the components required, are not subject to the testing required, and are not submitted
to the certification required to ensure a level of reliability appropriate for the treatment
and diagnosis of humans.
The CPBF PMX-233 is a PISA/ISA Bus Industrial Single Board (I.S.B.) The
board design combine together with all necessary input and output effects
interfaces which makes it an ideal all-in-one industrial single board computer.
The board design with 100 MHz internal bus clock rate architecture.
The advance PISA/ISA Bus add-on connection of CPBF PMX-233 allows the user
could easily obtain both ISA’s 16-bit PISA slot for suitable plug into a small size
system with 8/16/32 bit operation. One set of PC/104 bus connectors is for industrial
PC/104 board add-ins. The board is also design with an ESS® Solo1 3D sound
interface which provides an ideal sound adapter in any sound application. The
IDE interface with DMA33/66 access of mode 4 to IDE drive interface architecture,
supports a maximum 66 MB/sec in data transfer rating to 2 pieces IDE drive
connection. The board also provides an on-board 10/100Based LAN for easy
network connection.
A single Flash chip holds the system BIOS, and you can change the Flash BIOS
via the Utility Update. The advanced IR port also provide a faster data transmission.
You can also use the DOS version of the "DiskOnChip¯Í" socket by issuing
commands from the DOS prompt without the necessity of other software
supports up to 144MB.
The board design, with Intel® 69000 VGA, provides internal connections to a VGA
monitor and/or flat panel. The VGA supports up to 1280x1024 @ 256 colors resolution.
The CPBF PMX-233 support SDRAM memory in a one DIMM socket. This gives
you the flexibility of configuring your system from 8 to 256MB DRAM by using the
most economical DIMM memory modules for its on board system SDRAM.
If a non-expect program cause halts, the on board Watchdog Timer (WDT) will
automatically reset the CPU or generate an interrupt. The WDT is designed with
pure hardware and doesn’t need any arithmetical functions of a real-time clock
chip. This ensures the reliability in an unmanned or standalone system.
3
Page 8
4
Page 9
1.1 Major Features
?? 75~500MHz CPU for Intel
Cyrix 6x86
?? ALi M1541, M1543 chipsets
?? One DIMM socket provides up to 256MB
?? Fast PCI DMA33/66 controller support two IDE disk drives
?? 100MHz system clock support
?? Four RS-232 serial ports, include 16C550 UART with 16-byte FIFO
?? One enhanced bi-directional parallel port supports SPP/ECP/EPP
?? On board PS/2 Keyboard and PS/2 Mouse connector
?? On board SMC 37C669 super I/O chipset
?? On board 69000 CRT/Panel display controller
?? On board ESS Solo1 3D Sound
?? DiskOnChip memory size up to 144MB
?? Single +5V support
?? PC/104 Bus support
?? ATX Power Function support
?? CPU Temperature Alarm support
®
Pentium® MMXTM, Tillamook, AMD K5/K6,
5
Page 10
1.2 Specifications
• CPU: 75~500MHz CPU for Intel®Pentium® MMXTM, Tillmook, AMD K5/K6,
Cyrix 6x86
• Bus Interface: ISA Bus
• Memory: One DIMM socket provides up to 256MB
• Cache Memory: 512KB pipeline burst
• Chipset: ALi M1541/M1543
• I/O Chipset: SMC 37C669
• VGA: 69000 with 2MB memory supports CRT/panel display up to 1280x1024, at
256 colors
• IDE: Two IDE disk drives support DMA33/66 transfer rate up to 33/66MB/sec
• Floppy: Supports up to two floppy disk drives
• Parallel Port: Supports SPP/ECP/EPP
• LAN: Intel® 82559 10/100Based LAN
• Sound: ESS Solo1 3D Sound
• Serial Port: Four RS-232 serial ports include 16C550 UART with 16-byte
FIFO
• • PC/104: PC/104 connector for 16-bit ISA Bus
• IR: One IrDA TX/RX header
• USB: Supports two USB ports
• Keyboard: PS/2 6-pin Mini Din or 5-pin connector
• Mouse: PS/2 6-pin Mini Din
• DiskOnChip: Socket for DiskOnChip and memory size up to 144MB
• BIOS: Award Y2K PnP Flash BIOS
• Watchdog Timer: Set 1, 2, 10, 20, 110, 220 seconds activity trigger with
The delivery package of CPBF PMX-233 includes all following items:
• CPBF PMX-233 Industrial Single Board
• One Printer
• One IDE Port Flat Cable
• One FDD Port Flat Cable
• Two RS-232 Port Flat Cable
• One Sound Interface Cable
• Utility CD Disk
• User’s Manual
Please contact CyberResearch if any of these items are missing or
damaged when purchasing. Please keep all parts of the delivery
package with packing materials in case of you want to ship or store
the product in future.
7
Page 12
Chapter-2
Hardware Installation
This chapter provides the information on how to install the hardware of
CPBF PMX-233. Please follow sections 1.3, 2.1 and 2.2 in unpacking
the card. Then follow the jumpers switch setting, the watchdog, and
the DiskOnChip address sections, etc.
2.1 Caution of Static Electricity
The CPBF PMX-233 has been well package with an anti-static bag in
protect its sensitive computer components and circuitry from the damage
of static electric discharge.
Note: DO NOT TOUCH THE BOARD OR ANY OTHER SENSITIVE
COMPONENTS WITHOUT ALL NECESSARY ANTI-STATIC
PROTECTION.
You should follow the steps as following to protect the board in against the
static electric discharge whenever you handle the board:
1. Please use a grounding wrist strap whenever handling the CPBF PMX-233.Firmly clip the strap's alligator clip to the end of the shielded wire lead
from a grounded object. Please put on and connect the strap before
handle the CPBF PMX-233 for harmlessly discharging any static electricity
through the strap.
2. Please put any components, parts or tools on an anti-static pad whenever
you work on them outside the computer. You may also use the anti-static
bag instead the pad. Please contact your local supplier for necessary
anti-static equipment.
8
Page 13
2.2 Caution on Unpacking and Before Installation
First of all, please follow with all necessary steps of section 2.1 to
protection the CPBF PMX-233 from electrical discharge. Referring to
section 1.3, please check the delivery package again with following steps:
1. Unpack the CPBF PMX-233, retaining all of the packing material,
manual and diskette, etc.
2. If any of the components are losy or drop from the board, DO NOT INSTALL
THE BOARD.
3. Iif there is any visual damaged to the board, DO NOT INSTALLTHE BOARD.
4. Thoughly check your optional parts (i.e., CPU, SRAM, DRAM, CD-ROM,
etc.) to confirm that all necessary jumper settings and CMOS settingsare correct. Please reference the jumper settings in this manual as well.
5. Thoughly check your external devices (i.e., add-on cards, driver type,
etc.) for completed add-in or connection and correct CMOS setup.
Please reference the information connector connections in this
manual.
6. Please keep all necessary manuals and diskettes in a good condition
in case you need to re-install if you change your operating system or
other operations.
9
Page 14
2.3 CPBF PMX-233 Layout
10
Page 15
2.4 Quick Listing of Jumpers
JP1 ( 1-6 ) CPU‘s Core / Bus Clock-Ratio setting
JP1 (7-16) CPU‘s Vcore Voltage level selection setting
JP2 ATX power switch
JP3 Hard Drive Active LED connector
JP4 CPU Temperature Alarm Enabled/Disabled
JP5 69000 Active Select.
JP6 Panel Voltage Select
JP7 CPU clock in Select
JP8 DiskOnChip™ Address & Time of Watchdog
JP9 LAN speed LED
JP10 LAN Link Integrity LED
JP11 LAN Enabled/Disabled Select
JP12 LCD Panel connector
JP13 LAN Activity LED
JP14 Watchdog Timer Active Select
JP16 Sound Connector
JP17 Audio out & Mic in connector
JP18 Audio Line In connector
JP19 Dual/Single Voltage Select
A jumper pin-set is ON as a shorted circuit with a plastic cap inserted over
two pins. A jumper pin-set is OFF as a open circuit with a plastic cap
inserted over one or no pin(s) between pins. The below figure 2.2 shows the
examples of different jumper pin-set setting as ON or OFF in this manual.
Figure 2.2
All jumper pin-set already has its default setting with the plastic cap
inserted as ON, or without the plastic cap inserted as OFF. The default
setting may reference in this manual with a " * " symbol in front of the
selected item.
13
Page 18
2.7 VGA Controller
The on board 69000 chipset provides with up to 1280x1024 @ 256 colors
resolution. The board provides the user the ability to auto disable VGA if
another PCI-bus display card is pluged in into the PCI slot.
There is no need to set any jumper to disable the on-board VGA if any 2nd
PCI-bus VGA card is pluged into the PCI slot.
If you want to disable VGA by Hardware, you can select JP5.
JP5: VGA Controller
*1-2 ON
2-3 OFF
2.8 DiskOnChip Address Setting
The CPBF PMX-233 provides an U8 socket to install the DiskOnChip
module.
A JP8 may select the starting memory address of the DiskOnChip
(D.O.C.) for avoid the mapping area with any other memory devices. If you
have other memory devices in the system, please set both at different
memory address mapping.
JP8: DiskOnChip? Address
PIN NO. Address
*1-2 D000
3-4 D800
The D.O.C. function allows the system to be used without FDD or HDD. The
D.O.C. may be formatted as driver C: or driver A:. The user may also use the DOS
commands such as FORMAT, SYS, COPY, XCOPY, DISCOPY and DISKCOMP,
etc. This means that the D.O.C. may be used as drive A if the system works
without FDD-A for ambient application. Please contact with your supplier for
different sized D.O.C. modules.
14
Page 19
2.9 Setting the CPU
*
* *
*
*
*
*
*
*
*
* *
*
*
The CPBF PMX-233 provides all possibility in jumper setting for types
of CPU with JP1 (7-16) for CPU Vcore Voltage, JP7 (1-8) for internal Host
Bus Clock Rate and JP1 (1-6) for CPU Clock-in Multiplex Weighted Value
setting as following. For Dual Voltage and Tillamook CPU, JP19 ON.
Please contact with your CPU’s supplier in getting the information
for correct settings. Any wrong settings may cause CPU damage.
• JP9: Dual/Single Voltage Select
JP19 DESCRIPTION
ON Dual Voltage
OFF Single Voltage
2.10 Watchdog Timer
There are three access cycles of Watchdog Timer: Enable, Refresh
and Disable. The Enable cycle should proceed by READ PORT 443H. The
Disable cycle should proceed by READ PORT 045H. A continue Enable
cycle after a first Enable cycle means Refresh.
If the Enable cycle is active, a Refresh cycle is requested before the
time-out period for restarting counts the WDT Timer's period. Otherwise, it
will assume that the program operation is abnormal when the time
counting over the period preset of WDT Timer. A System Reset signal to
start again or a NMI cycle to the CPU comes if over.
The JP14 is using to select the active function of watchdog timer in
disable the watchdog timer, or presetting the watchdog timer activity at
the reset trigger, or presetting the watchdog timer activity at the NMI
trigger.
• JP14: Watchdog Active Type Setting
JP14 DESCRIPTION
*2-3 System Reset
1-2 Active NMI
OFF disable Watchdog timer
16
Page 21
• JP8(5-10): WDT Time - Out Period
PERIOD 5-6 7-8 9-10
*1 sec ON ON ON
2 sec OFF ON ON
10 sec ON OFF ON
20 sec OFF OFF ON
110 sec ON ON OFF
220 sec OFF ON OFF
The Watchdog timer is disabled after the system Power On. The
watchdog timer can be enabled by an Enable cycle by reading the
control port (443H), a Refresh cycle by reading the control port (443H)
and a Disable cycle by reading the Watchdog timer disable control port
(045H). After a Enable cycle of WDT, the user must constantly proceed a
Refresh cycle to WDT before its period setting comes at the end of every
1, 2, 10, 20, 110 or 220 seconds
(Please reference to the selection table of JP8 for WDT Time-Out period
setting). If the Refresh cycle does not activatebefore the WDT
period cycle, the on-board WDT architecture will issue a Reset or
NMI cycle to the system.
The Watchdog Timer is controlled by two I/O ports.
443H I/O Read The Enable cycle.
443H I/O Read The Refresh cycle.
045H I/O Read The Disable cycle.
17
Page 22
The following sample programs shows how to Enable, Disable and
Refresh the Watchdog timer:
WDT_EN_RF EQU 0433H
WDT_DIS EQU 0045H
WT_Enable PUSH AX ; keep AX DX
PUSH DX
MOV DX,WDT_EN_RF ; enable the watchdog timer
IN AL,DX POP DX ; get back AX, DX
POP AX
RET
WT_Refresh PUSH AX ; keep AX, DX
PUSH DX
MOV DX,WDT_ET_RF ; refresh the watchdog timer
IN AL,DX
POP DX ; get back AX, DX
POP AX
RET
WT_DISABLE PUSH AX
PUSH DX
MOV DX,WDT_DIS ; disable the watchdog timer
IN AL,DX
POP DX ; get back AX, DX
POP AX
RET
2.11 System Memory SDRAM
The CPBF PMX-233 provides SDRAM memory on board with one DIMM
socket for maximum 256MB capacity.
18
Page 23
19
Page 24
Chapter-3
Connection
This chapter gives all necessary information for the peripheral's
connections, switches and indicators.
3.1 VGA Connectors
The HCPBF PMX-233 provides one external connector for the VGA
monitor connection.
• CN18: 15-pin CRT Connector
PIN NO. DESCRIPTION PIN NO. DESCRIPTION
1 RED 2 GREEN
3 BLUE 4 NC
5 GND 6 GND
7 GND 8 GND
9 NC 10 GND
11 NC 12 NC
13 HSYNC 14 VSYNC
15 NC
20
Page 25
3.2 Serial Ports Connectors
TheCPBF PMX-233 offers four high-speed NSIGC550 compatible UARTS
with Read/ Receive 16-byte FIFO serial ports with two DB-9 external connectors
and four internal 10-pin header connectors.
One standard 40-pin header daisy-chain driver connector provides as CN3
with following pin assignment. Total two IDE (Integrated Device
Electronics) drivers may connect.
• CN3: IDE Connector
PIN NO. DESCRIPTION PIN NO.
1 RESET 2 GROUND
3 DATA 7 4 DATA 8
5 DATA 6 6 DATA 9
7 DATA 5 8 DATA 10
9 DATA 4 10 DATA 11
11 DATA 3 12 DATA 12
13 DATA 2 14 DATA 13
15 DATA 1 16 DATA 14
17 DATA 0 18 DATA 15
19 GROUND 20 N/C
21 N/C 22 GROUND
23 IOW# 24 GROUND
25 IOR# 26 GROUND
27 N/C 28 BALE - DEFAULT
29 N/C 30 GROUND# -DEFAULT
31 INTERRUPT 32 IOCS16#-DEFAULT
33 SA1 34 N/C
35 SA0 36 SA2
37 HDC CS0 38 HDC CS1#
39 HDD ACTIVE 40 GROUND
DESCRIPTION
24
Page 29
3.6 Parallel Port Connector
A standard 26-pin flat cable driver connector provides as CN11 with
following pin assignment for connection to a parallel printer:
• CN11: Parallel Port Connector
PIN NO.
1 STROBE 2 DATA 0
3 DATA 1 4 DATA 2
5 DATA 3 6 DATA 4
7 DATA 5 8 DATA 6
9 DATA 7 10 ACKNOWLEDGE
The HCPBF PMX-233 has an on board ESS® Solo1 3D sound interface.
The following are the connectors of LINE IN, AUXB and MIC/SPEAKER
connectors.
The LINE IN and AUXB connectors are for audio sound input. The LINE IN
provides for 4pin connection, and AUXB provides for 3-pin connection.
• JP18: LINE IN Connector
PIN NO. DESCRIPTION
1 LINE L
2 GND
3 LINE R
• JP16: AUXB Connector
• JP17: MIC/SPEAKER Connector
PIN NO. DESCRIPTION PIN NO. DESCRIPTION
With MIC/SPEAKER cable, user may connect R/L Speaker to the AOUTL
and AOUTR pins of JP18, and connect Microphone to the MIC pin of JP17.
4 GND
PIN NO. DESCRIPTION
1 AUXAL
2 GND
3 AUXAR
1 AOUTL Red
3 GND Black
5 MIC Red
7 GND Black
2 AOUTR White
4 GND Key
6 N.C. White
8 GND Key
27
Page 32
3.11 Fast Ethernet Connector
The Fast Ethernet controller provides with 32-bit performance, PCI-bus
master capability, and full compliance with IEEE 802.3 10/100Based-T
specifications.
For 10/100Base-T operation, please connect the network connection by
plugging one end of the cable into the RJ-45 of the CN17 Connector.
• CN17: RJ-45 Connector
PIN NO. DESCRIPTION PIN NO. DESCRIPTION
1 TX+ 2 TX3 RX+ 4 NC
5 NC 6 RX7 NC 8 NC
3.12 PC/104 Bus Connection
The CPBF’s PC/104 expansion bus provides a connection to all kinds
of PC/104 modules. The PC/104 bus has become the industrial
embedded 16-bit PC standard bus. You can easily install thousandsof types of PC/104 modules from hundreds of vendors world-wide.
The detailed pin assignment of the PC/104 espansion bus connectors
CN9 and CN10 are specified in the following tables.
Note : The PC/104 connector allows to directly plug-in
Stack-thru PC/104 modules without the PC/104 mounting
kit.
The CPBF PMX-233 provides a 50-pin 2.0 mm pitch header
connector (JP12) for 3.3V Flat panel connection with following
pin-assignment.
+12V 1 2 +12V
GND 3 4 GND
+3V PVcc 5 6 ENAVdd
FPVee 7 8 GND
P
P
P
P
P
P
P
P
P
P
P
P
P
SHFCLK 35 36 FLM
M 37 38 LP
GND 39 40 ENABKL
P26 41 42 P27
P28
P30 45 46 P31
P32 47 48 P33
P34 49 50 P35
• JP6: Panel Power Selection
JP6 DESCRIPTION
1-2 3.3V Power
2-3 5V Power
9 10 P1
0
11 12 P3
2
13 14 P5
4
15 16 P7
6
17 18 P9
8
19 20 P11
10
21 22 P13
12
23 24 P15
14
25 26 P17
16
27 28 P19
18
29 30 P21
20
31 32 P23
22
33 34 P25
24
43 44 P29
30
Page 35
3.14 USB Ports Connector
The CPBF PMX-233 provides one 8-pin connector for USB-0 & USB-1
ports. Please refer to the following default pin information.
• CN12: USB Port Connectors
PIN NO. USB-0 PIN NO. USB-1
1 VCC 2 VCC
3 USB PO- 4 USB P15 USB PO+ 6 USB P1+
7 GND 8 GND
31
Page 36
Chapter-4
AWARD BIOS Setup
The CPBF PMX-233 uses Award PCI/ISA BIOS for the system
configuration. The Award BIOS setup program is designed to provide
the maximum flexibility in configuring the system by offering various
options which could be selected for end-user requirements. This
chapter is written to assist you in the proper usage of these features.
To access AWARD PCI/ISA BIOS Setup program, press <Del> key
during memory testing when first power on. The Main Menu will be
displayed at this time.
32
Page 37
4.1 Main Menu
Once you enter the Award BIOS CMOS Setup Utility, the Main Menu
will appear on the screen. The Main Menu allows you to select from
several setup functions and two exit choices. Use the arrow keys to
select among the items and press <Enter> to enter the sub-menu.
ROM PCI/ISA BIOS (2A5KKD2B)
CMOS SETUP UTILITY
AWARD SOFTWARE, INC.
STANDARD CMOS SETUP
INTEGRATED PERIPHERALS
BIOS FEATURES SETUP
CHIPSET FEATURES SETUP
POWER MANGEMENT SETUP
PNP/PCI CONFIGURATION
LOAD BIOS DEFAULTS
LOAD SETUP DEFAULTS
Esc : Quit
F10 : Save & Exit
SUPERVISOR PASSWORD
USER PASSWORD
IDE HDD AUTO DETECTION
HDD LOW LEVEL FORMAT
SAVE & EXIT SETUP
EXIT WITHOUT SAVING
???? : Select Item
(Shift)F2 : Change Color
Note that a brief description of each highlighted selection appears at
the bottom of the screen.
33
Page 38
4.2 Standard CMOS Setup
:
:
:
:
The Standard Setup is used for the basic hardware system
configuration. The main function is for Data/Time and Floppy/Hard
Disk Drive settings. Please refer to the following screen for the setup.
When the IDE hard disk drive you are using is larger than 528MB,
please set the HDD mode to LBA mode. Please use the IDE Setup
Utility in BIOS SETUP to install the HDD correctly.
ROM PCI/ISA BIOS (2A5KKD2B)
STANDARD CMOS SETUP
AWARD SOFTWARE, INC.
Data (mm:dd:yy) : Fri, Oct 19 1999
Time (hh:mm:ss) : 00:00:00
Driver C ? Auto ( 0Mb) 0 0 0 0 0 Auto
Driver D ? Auto ( 0Mb) 0 0 0 0 0 Auto
CYLS HEAD PRECOMP LANDZ SECTOR MODE
Drive A
Drive B
LCD&CRT
Halt On
ESC : Quit
F1 : Help
1.44M ,
3.5in.
None Base Memory :
CRT Extended Memory :
Other Memory :
No Errors Total Memory :
???? : Select Item
(Shift) F2: Change Color
PU/PD/ + / - : Modify
640K
130048K
384K
131072K
34
Page 39
4.3 BIOS Features Setup
This section allows you to configure your system for the basic
operation. You have the opportunity to select the system’s default
speed, boot -up sequence, keyboard operation, shadowing and
security.
ROM PCI/ISA BIOS (2A5KKD2B)
BIOS FEATURES SETUP
AWARD SOFTWARE, INC.
Virus Warning : Disabled Video BIOS Shadow : Enabled
CPU Internal Cache : Enabled C8000-CBF
FF
External Cache : Enabled CC000-CFF
FF
Quick Power On Self Test : Disabled D0000-D3F
FF
Boot Sequence : A,C,SCSI D4000-D7F
FF
Swap Floppy Drive : Disabled D8000-DBF
FF
Boot Up Floppy Seek : Enabled DC000-DFF
FF
Boot Up NumLock Status : On Cyrix 6x86/MII CPUID : Enabled
Boot Up System Speed : High
Gate A20 Option : Fast
Typematic Rate Setting : Disabled
Typematic Rate (Chars/Sec) : 6
Typematic Delay (Msec) : 250
Security Option : Setup
PCI/VGA Palette Snoop : Disabled
Assign IRQ For VGA : Enabled ESC : Quit ??? ? : Select
OS Select For DRAM > 64MB : Non-OS2 F1 : Help PU/PD/+/-: Modify
Report No FDD For WIN 95 : Yes F5 : Old Values (Shift) F2 : Color
G6 : Load BIOS Defaults
G7 : Load Setup Defaults
Shadow : Disabled
Shadow : Disabled
Shadow : Disabled
Shadow : Disabled
Shadow : Disabled
Shadow : Disabled
Item
35
Page 40
36
Page 41
4.4 Chipset Features Setup
Host Read DRAM Command
This section allows you to configure the system based on the specific
features of the installed chipset. This chipset manages bus speeds
and the acce ss to the system memory resources, such as DRAM and
the external cache. It also coordinates the communications between
the conventional ISA and PCI buses. It must be stated that these
items should never be altered. The default settings have been chosen
because they provide the best operating conditions for your system.
You might consider and make any changes only if you discover that
the data has been lost while using your system.
ROM PCI/ISA BIOS (2A5KKD2B)
CHIPSET FEATURES SETUP
AWARD SOFTWARE, INC.
Auto Configuration : Enabled
AT Bus Clock : CLK2/4
L2 TA RAM Size : 8
DRAM Timing : Nomal
SDRAM CAS Latency : 3
Pipilined Function : Enabled
Graphics Aperture Size : 64 MB
DRAM Date Integrity Mode : Disabled
Memory Hole At 15M -16M : Disabled
Data Merge : Disabled F1 : Help PU/PD/+/-: Modify
IO Recovery Period : 1 us F5 : Old Values (Shift) F2 : Color
Auto Detect DIMM/PCI Slk
Spread Spectrum
The IDE hard drive controllers can support up to two separate hard
drives. These drives have a master/slave relationship which is
determined by the cabling configuration used to attach them to the
controller. Your system supports two IDE controllers--a primary and a
secondary--so you can install up to four separate hard disks.
PIO means Programmed Input /Output. Rather than having the BIOS
issue a series of commands to affect the transfer to or from the disk
drive, PIO allows the BIOS to tell the controller what it wants and then
let the controller and the CPU perform the complete task by them.
This is much simpler and more efficient (also faster).
ROM PCI/ISA BIOS (2A5KKD2B)
INTEGRATED PERIPHERALS
AWARD SOFTWARE, INC.
On-Chip Primary IDE : Enabled
Master PIO : Auto
Slave PIO : Auto KBC clock source : 8 MHz
Master Ultra DMA : Auto Onboard FDC Controller : Enabled
Slave Ultra DMA : Auto Onboard UART Port 1 : 3F8/IRQ4
IDE HDD Block Mode : Enabled Onboard Parallel Port : 378/IRQ7
On-Chip USB Controller : Disabled Parallel Port Mode :
Init Display First : PCI Slot Onboard IrDA Port : Disabled
Ring/Wake On LAN
Control
RTC Alarm Controller : Disabled Onboard Serial Port 3 : 3E8
Power On Function : Button Only LCD Panel Type : Panel 5
Onboard UART Port 2 : 2F8/IRQ3
ECP Mode Use DMA : 3
: Disabled
Serial Part 3 Use IRQ : IRQ10
Onboard Serial Port 4 : 2E8
Serial Port 4 Use IRQ : IRQ11
38
Page 43
Panel# Panel Type
0 1024*768 Dual Scan STN Color Panel
1 128*1024 TFT Color Panel
2 640*480 Dual Scan STN Color Panel
3 800*600 Dual Scan STN Color Panel
4 640*480 Sharp TFT Color Panel
5 640*480 18-bit TFT Color Panel
6 1024*768 TFT Color Panel
7 800*600 TFT Color Panel
8 800*600 TFT Color Panel (Large BIOS ONLY)
9 800*600 TF T Color Panel (Large BIOS ONLY)
10 800*600 Dual Scan STN Color Panel (Large BIOS ONLY)
11 800*600 Dual Scan STN Color Panel (Large BIOS ONLY)
12 1024*768 TFT Color Panel (Large BIOS ONLY)
13 1280*1024 Dual Scan STN Color Panel (Large BIOS ONLY)
14 1024*600 Dual Scan STN Color Panel (Lange BIOS ONLY)
15 1024*600 TFT Color Panel (Lange BIOS ONLY)
39
Page 44
4.6 Power Management Setup
The Power Management Setup allows user to configure the system for
saving energy in a most effective way while operating in a manner
consistent with his own style of computer use.
ROM PCI/ISA BIOS (2A5KKD2B)
POWER MANAGEMENT SETUP
AWARD SOFTWARE, INC.
Power Management : User Define
PM Control by APM : Yes Power Button Mode : Instant-off
MODEM Use IRQ : 3 DOCK I/O SMI : Disabled
Video Off Option : Susp, stby
->Off
Video Off Method : DPMS
Support
** PM Times **
HDD Off After : Disabled
Doze Mode : Disabled
Standby Mode : Disabled
Suspend Mode : Disabled
FAN Off Option : Suspend->