The information in this document is subject to change without prior notice
in order to improve reliability, design, and function and does not represent
a commitment on the part of CyberResearch, Inc.
In no event will CyberResearch, Inc. be liable for direct, indirect, special,
incidental, or consequential damages arising out of the use of or inability
to use the product or documentation, even if advised of the possibility of
such damages.
This document contains proprietary information protected by copyright.
All rights are reserved. No part of this manual may be reproduced by any
mechanical, electronic, or other means in any form without prior written
permission of CyberResearch, Inc.
Trademarks
“CyberResearch,” and “CEGC Series,” are trademarks of CyberResearch,
Inc. Other product names mentioned herein are used for identification
purposes only and may be trademarks and/or registered trademarks of
their respective companies.
• NOTICE •
CyberResearch, Inc. does not authorize any CyberResearch product for
use in life support systems, medical equipment, and/or medical devices
without the written approval of the President of CyberResearch, Inc. Life
support devices and systems are devices or systems which are intended
for surgical implantation into the body, or to support or sustain life and
whose failure to perform can be reasonably expected to result in injury.
Other medical equipment includes devices used for monitoring, data
acquisition, modification, or notification purposes in relation to life
support, life sustaining, or vital statistic recording. CyberResearch
products are not designed with the components required, are not subject
to the testing required, and are not submitted to the certification required
to ensure a level of reliability appropriate for the treatment and diagnosis of
humans.
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Warnings appear where overlooked details may cause damage to the equipment or result
in personal injury. Warnings should be taken seriously. Warnings are easy to recognize.
The word “warning” is written as “WARNING,” both capitalized and bold and is followed by
text. The text is the warning message. A warning message is shown below:
WARNING:
This is an example of a warning message. Failure to adhere to warning
messages may result in permanent damage to the CEGC or personal
injury to the user. Please take warning messages seriously.
CAUTION!
Cautionary messages should also be heeded to help reduce the chance of losing data or
damaging the CEGC. Cautions are easy to recognize. The word “caution” is written as
“CAUTION,” both capitalized and bold and is followed. The italicized text is the cautionary
message. A caution message is shown below:
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CAUTION:
This is an example of a caution message. Failure to adhere to cautions
messages may result in permanent damage to the CEGC. Please take
caution messages seriously.
NOTE:
These messages inform the reader of essential but non-critical information. These
messages should be read carefully as any directions or instructions contained therein can
help avoid making mistakes. Notes are easy to recognize. The word “note” is written as
“NOTE,” both capitalized and bold and is followed by text. The text is the cautionary
message. A note message is shown below:
NOTE:
This is an example of a note message. Notes should always be read.
Notes contain critical information about the CEGC. Please take note
messages seriously.
If any of the components listed in the checklist below are missing,
please do not proceed with the installation. Please contact a
CyberResearch sales representative at sales@cyberresearch.com
visit the CyberResearch website (http://www.cyberresearch.com
The items listed below should all be included in the CEGC package.
1 x CEGC single board computer
1 x IDE cable
1 x PS/2 Keyboard and mouse Y-cable
1 x Keyboard and mouse cable with Mini DIN
2 x SATA power cables
4 x SATA cables
1 x Dual RS-232 cable
1 x USB cable
1 x Mini jumper pack
1 x Utility CD
Images of the above items are shown in Chapter 3.
or
.)
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1.1 Overview
Figure Error! No text of specified style in document.-1: CEGC PICMG 1.3 CPU Card
The CEGC PICMG 1.3 form factor CPU card (Figure Error! No text of specified style in
document.-1) is an LGA775 Intel® Core™2 Quad, Intel® Core™2 Duo or Intel® Celeron
CPU processor platform. Both 45nm core (Wolfdale, Yorkfield) and 65nm core (Conroe)
processors are supported. (For a full list of supported processors please refer to Section
2.3)
Up to four 2.0 GB 667 MHz or 800 MHz un-buffered DDR2 SDRAM DIMM are supported
by the Mobile Intel® Q35 graphics memory controller hub (GMCH). The Intel® Q35 GMCH
also has a single PCI Express x16 (PCIe x16) expansion lane for a PCIe x16 graphics
card on the backplane.
The integrated Intel® ICH9DO I/O controller hub (ICH) supports six SATA II drives with
data transfer speeds of 3.0 Gbps with SATA RAID configuration support. Twelve USB 2.0
channels, four expansion PCIe x1 channels and four expansion PCI channels provide
flexible expansion options. Support for a (optional) trusted platform module (TPM)
provides additional system security during system boot-up. High Definition Audio (HDA)
support ensures an HDA audio kit can be easily implemented on the CEGC.
The CEGC PICMG 1.3 form CPU card has the following backplane expansion options:
1 x PCIe x16 graphics card
4 x PCIe x1 expansion cards
4 x PCI expansion cards
1.1.2 CEGC Features
Some of the CEGC features are listed below.
Supports the following Intel® LGA775 processors:
o Intel® Core™2 Duo (45nm and 65nm)
o Intel® Core™2 Quad (45nm and 65nm)
o Intel® Celeron (65nm)
Supports four 240-pin 2GB 667MHz or 800 MHz DDR2 DIMMs
Six SATA II drives with transfer rates of 3. 0 Gbps supported
Two Ultra ATA 133, Ultra ATA 100, Ultra ATA 66 or Ultra ATA 33 IDE HDDs
supported
Twelve USB 2.0 devices supported (eight onboard an d four on the backplane)
Dual GbE Ethernet connectors
PICMG 1.3 form factor
RoHS compliant
Supports ATX power supplies
1.2 CEGC Overview
1.2.1 CEGC Overview Photo
The CEGC has a wide variety of peripheral interface connectors. Figure Error ! No text of
specified style in document.-2 is a labeled photo of the peripheral interface connectors
on the CEGC.
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Figure Error! No text of specified style in document.-2: CEGC Overview [Front
View]
1.2.2 CEGC Peripheral Connectors and Jumpers
The CEGC has the following connectors on-board:
1 x ATX power connector
1 x Audio connector
1 x Digital input/output (DIO) connector
2 x Fan connectors
1 x Front panel connector
1 x IDE disk drive connector
1 x Infrared interface connector
1 x Keyboard/mouse connector
6 x Serial ATA II (SATA II) drive connectors
2 x Serial port connectors
1 x TPM connector
1 x SDVO control connector
3 x USB 2.0 connectors
The Yorkfield core Intel® Core™2 Quad CPU is a 45nm LGA775 processor.
2.3.3 Supported Intel® Core™2 Duo (Wolfdale) Processors
The Wolfdale core Intel® Core™2 Duo CPU is a 45nm LGA775 processor.
2.3.4 Supported Intel® Core™2 Duo (Conroe-2M) Processors
Table Error! No text of specified style in document.-2 lists the Conroe-2M core Intel® Core™2 Duo processors supported on the CEGC. All the processors in Table Error! No
text of specified style in document.-2 are 65nm LGA775 processors with the following
features:
Enhanced Halt S tate (C1E)
Enhance Intel® Speedstep® Technology
Execute Disable Bit
Intel® EM64T
Intel® Thermal Monitor 2
Intel® Virtualization Technology (Only on E6400)
Intel® Dual Core Technology
Table Error! No text of specified style in document.-2 lists the Conroe L core Intel® Celeron processors supported on the CEGC. All the processors in Table Error! No text o f
specified style in document.-2 are 65nm LGA775 processors with the following
features:
Execute Disable Bit
Processor # CPU Speed FSB Speed Cache Size
440 1.86 GHz 533 MHz 1 MB
Table Error! No text of specified style in document.-3: Supported
Intel® Core™2 Duo (Conroe) Processors
2.4 Intel® Q35 Northbridge Chipset
2.4.1 Intel® Q35 Northbridge Chipset
The Intel® Q35 Northbridge chipset is an advanced Graphics and Memory Controller Hub
(GMCH) that supports a range of Intel® processors including 45nm Wolfdale dual core
and Yorkfield quad core and 65nm Conroe core processors. The Intel® Q35 Northbridge
supports 1333 MHz, 1066 MHz, or 800 MHz FSB and up to 8.0 GB of 667 MHz or 800
MHz DDR2 SDRAM. The Intel® Q35 Northbridge is interfaced to an Intel® ICH9DO
Southbridge chipset through a Direct Media Interface (DMI) communications link.
Intel®
Q35 Front Side Bus (FSB) Support
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The Intel® Q35 Northbridge supports processors with the following FSB speeds:
800 MHz
1066 MHz
1333 MHz
The LGA775 socket, Intel® Q35 Northbridge and the FSB are shown in Figure Error! No
text of specified style in document.-6.
Figure Error! No text of specified style in document.-6: Front Side Bus (FSB)
2.4.3 Intel® Q35 Memory Controller
The memory controller on the Intel® Q35 Northbridge can support up to 8.0 GB of DDR2
SDRAM. Four DDR2 SDRAM DIMM sockets on the CEGC are interfaced to the Intel®
Q35 Northbridge memory controller. The DDR2 sockets are shown in Figure Error! No text of specified style in document.-7.
The Intel® Q35 Graphics and Display Features can be configured in
the Northbridge BIOS configuration screen. Please refer to Section
6.7.1 on page 153.
The Intel® Q35 GMCH integrated graphics device (IGD) has 3D, 2D and video
capabilities. The Unified Memory Architecture (UMA) uses up to 256 MB of Dynamic Video
Memory Technology (DVMT) for graphics memory. External graphics accelerators on the
PCIe graphics (PEG) port are supported but cannot work simultaneou sly with the IGD.
2.4.6 Intel® Q35 SDVO and Analog Display Features
The Intel® Q35 GMCH provides access to:
A progressive scan analog monitor
An SDVO monitor
2.4.6.1 Intel® Q35 SDVO Capabilities
A Serial Digital Video Output (SDVO) communications bus is multiplexed to eight of the
sixteen PCIe ports on the Intel® Q35. The SDVO interface provides 1.0 MHz point-to-point
connectivity between the Intel® 35 and an SDVO device. The CEGC provides support for
a single SDVO device on a compatible CyberResearch backplane. The SDVO device is
installed in the PCIe x16 expansion slot and the SDVO function enabled by connecting a
3-pin SDVO control connector on the CEGC to a corresponding control connector on the
CyberResearch backplane. The SDVO control connector on the CEGC is shown in Figure Error! No text of specified style in document.-8.
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Figure Error! No text of specified style in document.-8: SDVO Connector
Some of the capabilities of the Intel® Q35 SDVO port are listed below:
Multiplexed with the PCIe x16 graphics port signals
Drives pixel clocks up to 270 MHz
Supports a single-channel SDVO device.
Digital display channels can drive a variety of SDVO devices including
o TMDS
o TV-Out
Only works with the IGD
3x3 Built In full panel scalar
180 degree Hardware screen rotation
270 MHz dot clock on each 12-bit interface
Supports flat panels up to 2048 x 1536 @ 60 Hz or digital CRT/HDTV at 1920
x1080 @ 85 Hz
Supports Hot-Plug and Display
Supports TMDS transmitters or TV -out encoders
ADD2/Media Expansion card that use the PCIe graphics x16 connector
2.4.6.2 Intel® Q35 Analog Display Capabilities
A single external female DB-15 (VGA) connector interfaces an analog display to an analog
CRT port on the Intel® Q35 GMCH. The VGA connector is shown in Figure Error! No text of specified style in document.-9.
Figure Error! No text of specified style in document.-9: VGA Connector
Some of the capabilities of the Intel® Q35 analog CRT port are listed below:
400 MHz Integrated 24-bit RAMDAC
Up to 2048x1536 @ 75 Hz refresh
Hardware Color Cursor Support
DDC2B Compliant Interface
2.4.7 Intel® Q35 Direct Media Interface (DMI)
The Direct Media Interface (DMI) is the communication bus between the Intel® Q35
GMCH and the ICH9DO I/O controller hub (ICH). The DMI is a high-speed interface that
integrates advanced priority-based servicing and allows for concurrent traffic and true
isochronous transfer capabilities. The DMI is shown in Figure Error! No text of specified style in document.-10.
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Figure Error! No text of specified style in document.-10: DMI Chip-to-Chip
Connection
Some of the features of the DMI include:
2.0 GBps point-to-point DMI to ICH9DO (1.0 GBps in each direction)
100 MHz reference clock (shared with PCI Express* Graphics Attach)
32-bit downstream addressing
APIC and MSI interrupt messaging support
Message Signaled Interrupt (MSI) messages
SMI, SCI and SERR error indication
2.5 Intel® ICH9DO Southbridge Chipset
2.5.1 Intel® ICH9DO Overview
Intel® ICH9DO Southbridge is an advanced I/O controller hub (ICH) connected to the
Intel® Q35 Northbridge through a DMI connection. The Intel® ICH9DO has six PCIe x1
ports, supports up to twelve USB 2.0 devices, six 3.0 Gbps SATA II drives with Intel®
Matrix Storage Technology (ACHI, RAID 0, RAID 1, RAID 5 or RAID 10), and comes with
an integrated GbE controller that is interfaced to an external RJ-45 connector. A
High-Definition audio (HDA) controller can be connected to an HDA codec on an optional
audio kit. Four PCI Masters provide PCI expansion capabilities on a compatible PICMG
The ICH9DO Southbridge chipset on the CEGC has the features listed below.
Complies with PCI Express Base Specification, Revision 11
Complies with PCI Local Bus Spe cificati on, Revision 2.3 and su pports 33MHz
PCI operations
Supports ACPI Power Management Logic
Contains:
o Enhanced DMA controller
o Interrupt controller
o Timer functions
Integrated SATA host controller with DMA operations on six ports with data
transfer rates up to 1.5 Gbps
Supports twelve USB 2.0 devices with six UHCI controllers and two EHCI
controller
Complies with System Management Bus (SMBus) Specification, V ersion 2.0
Supports Intel
Supports Intel
Contains Low Pin Count (LPC) interface
Supports Firmware Hub (FWH) interface
Serial Peripheral Interface (SPI) for Serial and Shared Flash
Intel® Quiet System technology
®
High Definition Audio
®
Matrix storage technology
2.5.3 Intel® ICH9DO High Definition Audio Implementation
NOTE:
The CyberResearch® audio kit is optional. If a CyberResearch audio kit
is required please us directly by sending an email to
sales@cyberresearch.com
.
A RealTek ALC883 7.1+2 channel High Definition Audio (HDA) codec on an optional
CyberResearch
®
HDA audio kit is connected to a 10-pin onboard audio connector that is
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interfaced through the Intel® High Definition Audio serial link to the HDA controller
integrated on the Intel® ICH9DO. The audio connector is shown in Figure Error! No text
of specified style in document.-11.
Figure Error! No text of specified style in document.-11: Audio Connector
NOTE:
If an HDA audio kit is going to be installed on the backplane, the HDA
controller must be enabled in the BIOS settings. To enable the HDA
controller please refer to Section 0 (the
SouthBridge Configuration menu) on page 156.
The ALC883 codec provides 10 DAC channels that simultaneously support 7.1 sound
playback, plus two channels of independent stereo sound output (multiple streaming)
through the front panel stereo output. Flexible mixing, mute, and fine gain control functions
provide a complete integrated audio solution for home entertainment PCs.
Gigabit Ethernet (1000 Mbps) is only supported in S0.
The Intel® ICH9DO Southbridge integrated GbE controller is interfaced to an Intel®
82566DM Gigabit LAN connect device through the Gigabit LAN Connect Interface (GLCI).
The GLCI is shared with the PCIe x1 port 6. The Intel® 82566DM connects the Intel®
ICH9DO Southbridge integrated GbE controller to an external RJ-45 Ethernet LAN
connector to provide GbE access.
NOTE:
To enable the Intel® ICH9DO GbE Wake-on LAN function, the
Wake-on LAN function must be enabled in the BIOS. Please refer to
Section 0 (the
SouthBridge Configuration menu) on page 156.
Some of the features of the Intel® ICH9DO GbE controller are listed below.
Supports multi speeds including 10 Mbps, 100 Mbps and 1000 Mbps
Can operate in full-duplex mode at all supported speeds
Can operate at half-duplex at 10 MBps and 100 MBps
Adheres to the IEEE 802.3x Flow Control Specification.
Configurable LED operation for customization of LED display.
64-bit address master support for system using more than 4 GB of physical
memory.
Configurable receive and transmit data FIFO, programmable in 1 KB
increments.
Intelligent interrupt generation to enhance driver performance.
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Compliance with Advanced Configuration and Power Interface
Compliance with PCI Power Management standards.
ACPI register set and power down functionality supporting D0 & D3 states.
Full wake-up support (APM and ACPI).
Magic Packet wake-up enable with unique MAC address.
Fragmented UDP checksum off load for package reassembly.
Jumbo frames supported.
2.5.4.1 Intel® 82566DM Gigabit LAN Connect Device
One of the external RJ-45 Ethernet LAN connectors is interfaced to an Intel® 82566DM
Gigabit LAN connect device. The Intel® 82566DM is a compact, single-port integrated
physical layer (PHY) device interfaced directly to the Intel® ICH9DO Ethernet controller
through the GLCI. The Intel® ICH9DO Ethernet controller has its own Media Access
Controller (MAC). The Intel® 82566DM Gigabit LAN connect device is shown in Figure
Error! No text of specified style in document.-12.
Figure Error! No text of specified style in document.-12: Intel® 82566DM Gigabit
LAN Connect Device
Some of the features of the Intel® 82556DM are listed below:
10 Mbps, 100 Mbps, or 1000 Mbps
Supports Intel® Active Management Technology
Supports Intel® Virtualization Technology through the Intel® Virtual Gigabit
Network Connection.
Can support legacy ASF2.0.
Shared SPI flash with system BIOS
Integrated linear voltage regulator
TCP/UDP checksum and segmentation offload
Receive side scaling
Dual TX and RX queues
802.1p and 802.1q
2.5.5 Intel® ICH9DO Low Pin Count (LPC) Interface
The ICH9DO LPC interface complies with the LPC 1.1 specifications. The LPC bus from
the ICH9DO is connected to the following components:
BIOS chipset
Super I/O chipset
Trusted Platform Module (TPM) co nnector
2.5.6 Intel® ICH9DO PCI Interface
The PCI interface on the ICH9DO is compliant with the PCI Revision 2.3 implementation.
Some of the features of the PCI interface are listed below.
PCI Revision 2.3 compliant
33MHz
5V tolerant PCI signals (except PME#)
Integrated PCI arbiter supports up to four PCI bus masters
The PCI bus masters are interfaced to the following onboard components:
Two backplane PCI channels
One ITE IT8211 PCI IDE controller
One IT8209 PCI bridge
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The bus masters interfaced to the two backplane PCI channels and the two PCI channels
that come from the PCI bridge are all interfaced to the PCI edge connector on the bottom
of the CEGC as specified by the PICMG 1.3 form factor.
2.5.7 Intel® ICH9DO PCIe x1 Bus
The Intel® ICH9DO Southbridge chipset has six PCIe x1 lanes. The four PCIe lanes are
interfaced through a PCIe edge connector at the bottom of the CPU card through a
compatible half-size backplane to either four PCIe x1 expansion cards or one PCIe x4
expansion card on.
One of the remaining PCIe x1 lanes is connected to an Intel® 82566DM GbE controller
and the other PCIe x1 lane is connected to an Intel® 82573L GbE controller.
For more detailed information, please refer to Section 2.6.3.
2.5.8 Intel® ICH9DO Real Time Clock
256 bytes of battery backed RAM is provided by the Motorola MC146818B real time clock
(RTC) integrated into the ICH9DO. The RTC operates on a 3V battery and 32.768KHz
crystal. The RTC keeps track of the time and stores system data even when the system is
turned off.
2.5.9 Intel® ICH9DO SATA Controller
NOTE:
That SATA drive mode is set in the BIOS. Please refer to the Section
6.3.2 on IDE Configuration on page 113 and Sectio n 6.3.5.1 on AHCI
Configuration on page 129.
The ICH9DO SATA supports three modes of operation:
Native IDE enabled operating system: Two controllers enable all six ports
on the bus. Controller 1 supports Port 0, Port 1, Port 2 and Port 3. Controller 2
supports Ports 4 and Port 5.
Legacy operating system is used: One controller is enabled and only
supports Port 0, Port 1, Port 2 and Port 3.
AHCI or RAID mode: One controller supports all six ports including, Port 0,
Port 1, Port 2, Port 3, Port 4 and Port 5.
In the AHCI or RAID mode, 3.0 Gbps data transfer speeds are supported. The SATA drive
connectors are shown in Figure Error! No text of specified style in document.-13.
Figure Error! No text of specified style in document.-13: SATA Drive Connectors
2.5.10 Intel® ICH9DO Serial Peripheral Interface (SPI) BIOS
The 4-pin SPI is connected to an SPI BIOS chip. A licensed copy of AMI BIOS is
preinstalled on the SPI BIOS chip. A master-slave protocol is used for communication on
the SPI bus. The slave is connected to the Intel® ICH9DO Southbridge and is
implemented as a tri-state bus.
2.5.11 Intel® ICH9DO USB Controller
2.5.11.1 Intel® ICH9DO USB Controller Overview
The ICH9DO comprises six full/low speed USB controllers that support the standard
Universal Host Controller Interface (UHCI) Revision 1.1. Each controller supports two
USB devices ensuring up to twelve USB 1.1 devices can be connected to the CEGC.
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The ICH9DO also comprises two high-speed Enhanced Host Controller Interface (EHCI)
controllers. Each EHCI controller supports six USB 2.0 devices ensuring twelve USB 2.0
devices can be connected to the CEGC. EHCI controllers facilitate data transfer speeds of
480 Mbps
Port routing logic on the ICH9DO determines whether a UHCI or an EHCI controller
controls a USB port.
2.5.11.2 CEGC USB Implementation
Only eight of the Intel® ICH9DO USB ports are implemented on the CEGC. Two USB
ports (USB Port 1 and USB Port 2) are connected to two external connectors and six USB
ports (USB Port 3 to USB Port 8) are connected to three 8-pin onboard pin-headers. See
Figure Error! No text of specified style in document.-14.
Figure Error! No text of specified style in document.-14: Onboard USB
Implementation
2.5.11.3 Backplane USB Implementation
The remaining four Intel® ICH9DO USB ports (USB Port 9 to USB Port 8) are interfaced to
the backplane through the USB edge connector on the bottom of the CPU card. See
Figure Error! No text of specified style in document.-15. These four remaining USB
ports are implemented through connectors on the backplane.
Figure Error! No text of specified style in document.-15: USB Edge connector
2.6 CEGC PCIe Bus Components
2.6.1 PCIe Bus Overview
The CEGC has one PCIe x16 channel from the Intel® Q35 Northbridge and six PCIe x1
lanes from the Intel® ICH9DO Southbridge. The PCIe bus lanes are interfaced to the
following devices.
One PCIe x16 lane is connected to one PCIe x16 graphics card on a
compatible backplane
Four PCIe x1 lanes are connected to four PCIe x1 expansion cards on a
compatible backplane
One PCIe x1 lanes are connected to two Intel® PCIe GbE connectors
One PCIe x1 is shared with the Intel® ICH9DO Gigabit LAN Connect
Interface (GLCI), which is connected to a Intel® 82566DM Gigabit platform
LAN connect device
2.6.2 PCIe x16 Expansion
The Intel® Q35 Northbridge chipset has one PCIe x16 port reserved for a PCIe x16
graphics card. The PCIe x16 lane is interfaced to a PCIe x16 slot on a compatible
backplane through two separate edge connectors on the bottom of the CPU card. The
PCIe x16 graphics card is then installed on the PCIe x16 slot on the backplane. The PCIe
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x16 edge connector is shown in Figure Error! No text of specified style in
document.-16.
Figure Error! No text of specified style in document.-16: PCIe x16 Edge connector
2.6.3 PCIe x1 Expansion
Four of the six PCIe x1 expansion channels on the CEGC are interfaced to four PCIe x1
connectors on a backplane through an edge connector on the bottom of the CPU card.
The PCIe x1 edge connector is shown in Figure Error! No text of specified style in
document.-17.
Figure Error! No text of specified style in document.-17: PCIe x1 Edge connector
(Four Lanes)
An RJ-45 Ethernet LAN connector is interfaced directly to an Intel® 82573L PCIe GbE
controller. The Intel® 82573L PCIe GbE controller is a compact, single-port integrated
physical layer (PHY) device with its own Memory Access Controller (MAC) and interfaced
to the Intel® ICH9DO Southbridge through a PCIe x1 lane. The Intel® 82573L GbE
controllers is shown in Figure Error! No text of specified style in document.-18 below.
Figure Error! No text of specified style in document.-18: Intel® 82573L PCIe GbE
Controller
Some of the features of the Intel® 82573L are listed below:
2 Gbps peak bandwidth per direction
PCI Express Rev 1.0a specification
High bandwidth density per pin
Wide, pipelined internal data path architecture
Optimized transmit (Tx) and receive (Rx) queues
32 KB configurable Rx and Tx first-in/first-out (FIFO)
IEEE 802.3x*-compliant flow-control support with software controllable pause
times and threshold values
Programmable host memory Rx buffers (256 B-16 KB)
Descriptor ring management hardware for Tx and Rx
Mechanism for reducing interrupts from Tx/Rx operations
Integrated PHY for 10/100/1000 Mbps (full- and half-duplex)
IEEE 802.3ab* auto-negotiation support
IEEE 802.3ab PHY compliance and compatibility
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Tx/Rx IP,TCP,and UDP checksum offloading
Tx TCP segmentation
IEEE 802.1q* Virtual Local Area Network (VLAN) support with VLAN tag
insertion, stripping, and packet filtering for up to 4096 VLAN tags
Boot ROM Preboot eXecution Environment (PXE) Flash interface support
SDG 3.0,WfM 3.0 and PC2001 compliant
Wake on LAN support
2.7 PCI Bus Components
2.7.1 PCI Bus Overview
The PCI bus is connected to the components listed below:
The PCI bus complies with PCI Local Bus Specification, Revision 2.3 and sup ports 33MHz
PCI operations.
2.7.2 ITE IT8211 ATA Controller Chipset
The 40-pin IDE connector on the CEGC is connected to the ATA/ATAPI-6 ITE IT8211 ATA
controller chipset, which is then connected to the Intel® ICH9DO Southbridge ch ipset. The
controller and connector are shown in Figure Error! No text of specified style in document.-19 below.
Figure Error! No text of specified style in document.-19: ATA controller
Two ATA/ATAPI-6 hard disks can be connected to the IDE connector. Specifications for
the ITE IT8211 are listed below.
Compatible with ATA/ATAPI-6 specifications
Supports ANSI ATA proposal PIO modes 0, 1, 2, 3, and 4 with flow control,
DMA modes 0, 1, and 2 and Ultra DMA modes 0, 1, 2, 3, 4, 5 and 6.
512 bytes FIFO for data transfer per IDE channel
Supports pre-fetch and post-write function for PIO mode.
2.7.3 ITE IT8209 PCI Arbiter
One of the Intel® ICH9DO Southbridge PCI lanes is connected to an ITE IT8209 PCI
arbiter. One set of SYSGNT# and SYSREQ# on the ITE IT8209 supports three PCI
Masters thereby enabling the CEGC to support an additional two PCI Masters. The ITE
IT8209 PCI arbiter is shown in Figure Error! No text of specified style in document.-20
below.
Figure Error! No text of specified style in document.-20: PCI Arbiter
One of the PCI masters on the ITE IT8209 PCI arbiter is connected to the Intel® ICH9DO
Southbridge. The remaining two are connected to the PCI edge connector to facilitate PCI
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expansion on the backplane. Some of the features of the ITE IT8209 PCI arbiter are listed
below:
The PCI interface edge connector is connected to two PCI Masters on the ICH9DO
Southbridge and to two PCI masters on the ITE IT8209 PCI arbiter. The PCI bus edge
connector on the CEGC is interfaced to the PCI bus on the backplane thereby connecting
the PCI backplane expansion boards to the Intel® ICH9DO Southbridge. The PCI bus
edge connector is shown in Figure Error! No text of specified style in document.-21.
Figure Error! No text of specified style in document.-21: PCI Edge connector
Connection
The PCI is interfaced to four standard PCI expansion cards a compatible PICMG 1.3
backplane.
2.8 LPC Bus Components
2.8.1 LPC Bus Overview
The LPC bus is connected to components listed below:
A TPM connector on the CEGC is interfaced to the Intel® ICH9DO Southbridge through
the LPC bus. The TPM connector is shown in Figure Error! No text of spe cified style in
document.-22 below.
Figure Error! No text of specified style in document.-22: TPM Connector
The Intel® ICH9DO Southbridge supports TPM version 1.1 and TPM version 1.2 devices
for enhanced security. Three TPM are available from CyberResearch. The three TPMs
are listed below:
For more information about these modules please refer to Chapter 3 or contact
CyberResearch at sales@cyberresearch.com
.
2.8.3 Super I/O chipset
The ITE IT8718F Super I/O chipset is connected to the Intel® ICH9DO Southbridge
through the LPC bus. ITE IT8718F Super I/O chipset is shown in Figure Error! No text of specified style in document.-23 below.
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Figure Error! No text of specified style in document.-23: ITE IT8718F Super I/O
The ITE IT8718F is an LPC interface-based Super I/O device that comes with an
integrated Environment Controller. Some of the features of the iTE IT8718F chipset are
listed below:
PC98/99/2001, ACPI and LANDesk Compliant
Enhanced Hardware Monitor
Fan Speed Controller
Multi curve for one fan control
Multi sensor for one fan control
Single +5V Power Supply
Two 16C550 UARTs for serial port control
Keyboard Controller
48 General Purpose I/O Pins
Watchdog T i mer
Serial IRQ Support
SmartGuardian Controller
ITE automatic power-failure resume and power button debounce
Some of the Super I/O features are described in more detail below:
The LPC interface on the Super I/O complies with the Low Pin Count Specification Rev.
1.0. The LPC interface supports both LDRQ# and SERIRQ protocols as well as PCI PME#
interfaces.
2.8.3.2 Super I/O 16C550 UARTs
The onboard Super I/O has two integrated 16C550 UARTs that can support the following:
Two standard serial ports (COM1 and COM2)
IrDa 1.0 and ASKIR protocols
2.8.3.3 Super I/O Enhanced Hardware Monitor
The Super I/O Enhanced Hardware Monitor monitors three thermal inputs, VBAT
internally, and eight voltage monitor inputs. These hardware parameters are reported in
the BIOS and can be read from the BIOS Hardware Health Configuration menu.
2.8.3.4 Super I/O Fan Speed Controller
The Super I/O fan speed controller enables the system to monitor the speed of the fan.
One of the pins on the fan connector is reserved for fan speed detection and interfaced to
the fan speed controller on the Super I/O. The fan speed is then reported in the BIOS.
2.8.3.5 Super I/O Keyboard and Mouse Controller
The Super I/O keyboard and mouse controller is compatible with the following
specifications.
8042 compatible
Asynchronous access to two data registers and one status register
Compatible with 8042 software
PS/2 mouse supported
Port 92 supported
Interrupt and polling modes supported
Fast Gate A20 and Hardware Keyboard Reset
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8-bit timer/counter
The keyboard and mouse controller controller is interfaced to a keyboard and mouse
connected to the backplane through the board-to-board connectors.
2.8.3.6 Super I/O GPIO Ports
The Super I/O has 48 programmable GPIO ports of which 16 are implemented on the
CEGC. The GPIO connector has 16 programmable bits, 8-bit input and 8-bit output.
2.8.3.7 Super I/O Infrared
The Super I/O has dedicated infrared (IrDA) pins that are interfaced to an IrDA connector.
The IrDA connector is compatible with the following standards:
ASKIR
SIR
2.8.4 Super I/O Watchdog Timer
The super I/O wathdog timer has a maximum time resolution of 1 minute or 1 second with
a maximum or either 65,535 minutes or 65,535 seconds.
2.9 Ethernet LAN Controllers
The CEGC CPU card has two GbE controllers. The CEGC LAN connections are shown in
Figure Error! No text of specified style in document.-24.
Figure Error! No text of specified style in document.-24: LAN Connections
The first GbE controller, is an Intel® 82537L PCIe GbE controller and is the interface
between the Intel® ICH9DO Southbridge controller and the LAN1 RJ-45 Ethernet
connector.
The second GbE controller is integrated on the Intel® ICH9DO Southbridge and i nterfaced
to the LAN2 RJ-45 Ethernet LAN connector through an Intel® 82566DM Gigabit Platform
LAN Connect device. The Intel® 82566DM is connected directly to the GbE controller on
the Intel® ICH9DO Southbridge through the GLCI, which is shared with the PCIe x1 port
6.
Both of these Ethernet controllers have been described in detail in earlier sections. For
further details please refer to the relevant sections:
A cooling fan and heat sink must be installed on the CPU. Thermal paste must be
smeared on the lower side of the heat sink before it is mounted on the CPU. Heat sinks
are also mounted on the Northbridge and Southbridge chipsets to ensure the operating
temperature of these chips remain low.
2.10.3 Power Consumption
Table Error! No text of specified style in document.-4 shows the power consumption
parameters for the CEGC running 3D Mark® 2001 SE330 with a 2.66 GHz E6700 Intel®
Core™2 Duo processor with a 1066 MHz FSB and four 2.0GB 667MHz DDR2 DIMMs.
Voltage Current
+3.3V 3.0A
+5.0V 5.1A
+12V 4.23A
5Vsb 0.28A
Table Error! No text of specified
style in document.-4: Power
Consumption
2.11 Expansion Options
2.11.1 Expansion Options Overview
A number of compatible CyberResearch PICMG 1.3 backplanes and chassis can be used
to develop and expanded system. Please visit our website or call us for additional detail.
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Failure to take ESD precautions during the installation of the CEGC
may result in permanent damage to the CEGC and severe injury to the
user.
Electrostatic discharge (ESD) can cause serious damage to electronic components,
including the CEGC. Dry climates are especially susceptible to ESD. It is therefore critical
that whenever the CEGC, or any other electrical component is handled, the following
anti-static precautions are strictly adhered to.
Wear an anti-static wristband: - Wearing a simple anti-static wristband can
help to prevent ESD from damaging the board.
Self-grounding:- Before handling the board touch any grounded conducting
material. During the time the board is handled, frequently touch any
conducting materials that are connected to the ground.
Use an anti-static pad: When configuring the CEGC, place it on an
antic-static pad. This re duces the possibility of ESD damaging the CEGC.
Only handle the edges of the PCB:-: When handling the PCB, hold the PCB
by the edges.
3.2 Unpacking
3.2.1 Unpacking Precautions
When the CEGC is unpacked, please do the following:
Follow the anti-static precautions outlined in Section 3.1.
Make sure the packing box is facing upwards so the CEGC does not fall out of
the box.
Make sure all the components shown in Section 3.3 are present.
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3.3 Unpacking Checklist
NOTE:
If some of the components listed in the checklist below are missing,
please do not proceed with the installation. Contact a CyberResearch
sales representative directly. To contact CyberResearch sales
representative, please send an email to sales@cyberresearch.com
3.3.1 Package Contents
The CEGC is shipped with the following components:
Section 4.1.2 shows peripheral interface connector locations. Section 4.1.2 lists all the peripheral interface connectors seen in Section 4.1.2.
4.1.1 CEGC Layout
Figure Error! No text of specified style in document.-25 shows the on-board peripheral
connectors, rear panel peripheral connectors and on-board jumpers.
Figure Error! No text of specified style in document.-25: Connector and Jumper
Locations
4.1.2 Peripheral Interface Connectors
Table Error! No text of specified style in document.-7 shows a list of the peripheral
interface connectors on the CEGC. Detailed descriptions of these connectors can be
found below.
Connector Type Label
ATX power connector 4-pin ATX connector CPU12V1
Audio connector 10-pin header AUDIO1
Cooling fan connector, CPU 4-pin wafer CPU_FAN1
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Cooling fan connector, System 3-pin wafer CPU_SYS1
Digital input/output connector 10-pin header DIO1
Keyboard and mouse connector 6-pin wafer KB/MS1
Front panel connector 10-pin header F_PANEL1
IDE Interface connector 40-pin box header IDE1
Infrared (IrDA) connector 5-pin header IR1
SDVO connector 3-pin header SDVO1
Serial ATA drive connector 7-pin SATA SATA1
Serial ATA drive connector 7-pin SATA SATA2
Serial ATA drive connector 7-pin SATA SATA3
Serial ATA drive connector 7-pin SATA SATA4
Serial ATA drive connector 7-pin SATA SATA5
Serial ATA drive connector 7-pin SATA SATA6
Serial port connector (COM1) 10-pin box header COM1
Serial port connector (COM2) 10-pin box header COM2
TPM connector 20-pin header TPM1
USB connectors 8-pin header USB1
USB connectors 8-pin header USB2
USB connectors 8-pin header USB3
Table Error! No text of specified style in document.-7: Peripheral Interface Connectors
4.1.3 External Interface Panel Connectors
Table Error! No text of specified style in document.-8 lists the rear panel connectors o n
the CEGC. Detailed descriptions of these connectors can be found in Section 4.3 on
page 71.
Table Error! No text of specified style in document.-8: Rear Panel Connectors
4.2 Internal Peripheral Connectors
Internal peripheral connectors are found on the motherboard and are only accessible
when the motherboard is outside of the chassis. T his sect ion h as c omplete des cript ion s of
all the internal, peripheral connectors on the CEGC.
4.2.1 ATX Power Connector
CN Label:
CN Type:
CN Location: See Figure Error! No text of specified style in document.-26
CN Pinouts: See Table Error! No text of specified style in document.-9
The 4-pin ATX power connector is connected to an ATX power supply and powers the
CPU.
CPU12V1
4-pin ATX power connector (1x4)
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Figure Error! No text of specified style in document.-26: ATX Power Connector Location
PIN NO. DESCRIPTION
1 GND
2 GND
3 +12V
4 +12V
Table Error! No text of specified style in document.-9: AT Power Connector Pinouts
CN Location: See Figure Error! No text of specified style in document.-27
CN Pinouts: See Table Error! No text of specified style in document.-10
NOTE:
The CyberResearch® HDA audio kit is optional. If an HDA audio kit is
required please contact a sales representative directly by sending an
email to sales@cyberresearch.com
The 9-pin audio connector is interfaced on the one side to the high-definition audio (HDA)
controller on the Intel® ICH9DO Southbridge and to an external HDA codec.
.
NOTE:
If an HDA audio kit is going to be installed on the backplane, the HDA
controller must be enabled in the BIOS settings. To enable the HDA
controller please refer to Section 6.7.2 (the
SouthBridge Configuration menu) on page 156.
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Figure Error! No text of specified style in document.-27: Audio Connector Location
(9-pin)
PIN NO. DESCRIPTION PIN NO. DESCRIPTION
1 SYNC 2 BITCLK
3 SDOUT 4 PCBEEP
5 SDIN 6 RST#
7 VCC 8 GND
9 +12V 10 N/C
Table Error! No text of specified style in document.-10: Audio
Connector Pinouts
CN Location: See Figure Error! No text of specified
style in document.-28
CN Pinouts: See Table Error! No text of specified
style in document.-11
The digital input/output connector is managed through a Super I/O chip. The DIO
connector pins are user programmable. To see details on how to program the DIO chip,
please refer to Appendix B.
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Figure Error! No text of specified style in document.-28: DIO
Connector Connector Locations
PIN NO. DESCRIPTION PIN NO. DESCRIPTION
1 Input 0 2 Output 0
3 Input 1 4 Output 1
5 Input 2 6 Output 2
7 Input 3 8 Output 3
9 Input 4 10 Output 4
11 Input 5 12 Output 5
13 Input 6 14 Output 6
15 Input 7 16 Output 7
17 GND 18 +5V
Table Error! No text of specified style in document.-11:
DIO Connector Connector Pinouts
4.2.4 Fan Connector, CPU (12V, 4-pin)
CN Label:
CN Type:
CN Location: See Figure Error! No text of specified style in document.-29
CN Pinouts: See Table Error! No text of specified style in document.-12
The CPU cooling fan connector provides a 12V, 500mA current to a CPU cooling fan. The
connector has a "rotation" pin to get rotation signals from fans and notify the system so the
system BIOS can recognize the fan speed. Please note that only specified fans can issue
the rotation signals.
Figure Error! No text of specified style in document.-29: +12V Fan Connector Location
PIN NO. DESCRIPTION
1 GND
2 +12VCC
3 Rotation Signal
4 Control
Table Error! No text of specified style in document.-12: +12V Fan Connector
Pinouts
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4.2.5 Fan Connector, System (+12V)
CN Label:
CN Type:
SYS_FAN1
3-pin header
CN Location: See Figure Error! No text of specified style in document.-30
CN Pinouts: See Table Error! No text of specified style in document.-13
The system cooling fan connector provides a 12V, 500mA current to a system cooling
fan.. The connector has a "rotation" pin to get rotation signals from fans and notify the
system so the system BIOS can recognize the fan speed. Please note that only specified
fans can issue the rotation signals.
Figure Error! No text of specified style in document.-30: +12V Fan Connector Location
Figure Error! No text of specified style in document.-34:
Keyboard/Mouse Connector Location
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PIN NO. DESCRIPTION
1 +5V KB DATA
2 MS DATA
3 MS CLK
4 KB DATA
5 KB CLK
6 GROUND
Table Error! No text of specified style in document.-17: Keyboard/Mouse Connector
Pinouts
4.2.10 SATA Drive Connectors
CN Label:
CN Type:
SATA1, SATA2, SATA3, SATA4, SATA5. and SATA6
7-pin SATA drive connectors
CN Location: See Figure Error! No text of specified style in document.-35
CN Pinouts: See Table Error! No text of specified style in document.-18
The six SATA drive connectors are each connected to second generation SATA drives.
Second generation SATA drives transfer data at speeds as high as 300 Mbps. The SATA
drives can be configured in a RAID configuration.
Figure Error! No text of specified style in document.-35: SATA Drive Connector
Locations
PIN NO. DESCRIPTION
1 GND
2 TX+
3 TX4 GND
5 RX6 RX+
7 GND
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Table Error! No text of specified style in
document.-18: SATA Drive Connector
Pinouts
4.2.11 Serial Port Connector (COM1, COM 2)
CN Label:
CN Type:
CN Location: See Figure Error! No text of specified style in document.-36
CN Pinouts: See Table Error! No text of specified style in document.-19
The 10-pin serial port connector provides a second RS-232 serial communications
channel. The COM 2 serial port connector can be connected to external RS-232 serial port
devices.
Figure Error! No text of specified style in document.-36: Serial Connector
Pinout Locations
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PIN NO. DESCRIPTION PIN NO. DESCRIPTION
1 Data Carrier Direct (DCD) 2 Data Set Ready (DSR)
3 Receive Data (RXD) 4 Request To Send (RTS)
5 Transmit Data (TXD) 6 Clear To Send (CTS)
7 Data Terminal Ready (DTR) 8 Ring Indicator (RI)
9 Ground (GND) 10 N/C
Table Error! No text of specified style in document.-19: Serial Connector Pinouts
4.2.12 Trusted Platform Module (TPM) Connector
CN Label:
CN Type:
TPM1
40-pin header (2x20)
CN Location: See Figure Error! No text of specified style in document.-38
CN Pinouts: See Table Error! No text of specified style in document.-21
The Trusted Platform Module (TPM) connector secures the system on bootup. An optional
TPM (see packing list in Chapter 3) can be connected to the TPM connector.
Figure Error! No text of specified style in document.-37: TPM Connector Pinout Locations
PIN NO. DESCRIPTION PIN NO. DESCRIPTION
1 LCLK 2 GND2
3 LFRAME# 4 KEY
5 LRESET# 6 +5V
7 LAD3 8 LAD2
9 +3V 10 LAD1
11 LAD0 12 GND3
13 SCL 14 SDA
15 SB3V 16 SERIRQ
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17 GND1 18 GLKRUN#
19 LPCPD# 20 LDRQ#
Table Error! No text of specified style in document.-20: TPM
Connector Pinouts
4.2.13 SDVO Control Connector
CN Label:
CN Type:
SDVO1
3-pin header (1x3)
CN Location: See Figure Error! No text of specified style in document.-38
CN Pinouts: See Table Error! No text of specified style in document.-21
If an SDVO graphics card is installed on the PCIe x16 expansion slot on the backplane,
the 1x3 pin Serial Digital Video Output (SDVO) control connector must be connected to a
corresponding SDVO control connector on a compatible CyberResearch backplane.
Figure Error! No text of specified style in document.-38:SDVO Connector Pinout
Locations
PIN NO. DESCRIPTION
1 EXP_EN
2 SDVO_CLOCK
3 SDVO_DATA
Table Error! No text of specified style in document.-21: SDVO Connector Pinouts
4.2.14 USB Connectors (Internal)
CN Label:
CN Type:
USB1, USB2 and USB3
8-pin header (2x4)
CN Location: See Figure Error! No text of specified style in document.-39
CN Pinouts: See Table Error! No text of specified style in document.-22
The 2x4 USB pin connectors each provide connectivity to two USB 1.1 or two USB 2.0
ports. Each USB connector can support two USB devices.. Additional external USB ports
are found on the rear panel. The USB ports are used for I/O bus expansion.
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Figure Error! No text of specified style in document.-39: USB Connector Pinout
Locations
Figure Error! No text of specified style in document.-40 shows the CEGC external
peripheral interface connector (EPIC) panel. The CEGC EPIC panel consists of the
following:
1 x DVI connector
1 x PS/2 connector
2 x RJ-45 LAN connectors
Figure Error! No text of specified style in document.-40: CEGC External Peripheral
Interface Connector
4.3.1 LAN Connectors
CN Label:
CN Type:
CN Location: See Figure Error! No text of specified style in document.-40
CN Pinouts: See Table Error! No text of specified style in document.-23
The CEGC is equipped with two built-in RJ-45 Ethernet controllers. The controllers can
connect to the LAN through two RJ-45 LAN connectors. There are two LEDs on the
connector indicating the status of LAN. The pin assignments are listed in the following
table:
PIN DESCRIPTION PIN DESCRIPTION
LAN1 and LAN2
RJ-45
1 TXA+ 5 TXC-
2 TXA- 6 TXB3 TXB+ 7 TXD+
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4 TXC+ 8 TXD-
Table Error! No text of specified style in document.-23:
LAN Pinouts
Figure Error! No text of specified style in document.-41: RJ-45
Ethernet Connector
The RJ-45 Ethernet connector has two status LEDs, one green and one yello w. The green
LED indicates activity on the port and the yellow LED indicates the port is linked. See
Table Error! No text of specified style in document.-24.
STATUS
ORANGE 10/100 LAN YELLOW Linked
GREEN GbE LAN
DESCRIPTION STATUS DESCRIPTION
Table Error! No text of specified style in document.-24: RJ-45 Ethernet
Connector LEDs
4.3.2 USB Connector
CN Label:
CN T ype:
CN Location: See Figure Error! No text of specified style in document.-40
CN Pinouts: See Table Error! No text of specified style in document.-25
USB_1 and USB_2
USB port
The CEGC has four external USB 2.0 ports. The ports connect to both USB 2.0 and USB