CTLST CAT28F102T14I-45T, CAT28F102T14A-90T, CAT28F102T14A-70T, CAT28F102T14A-55T, CAT28F102T14A-45T Datasheet

CAT28F102

1 Megabit CMOS Flash Memory

FEATURES

Licensed Intel

second source

■ Fast Read Access Time: 45/55/70/90 ns

■ Low Power CMOS Dissipation:

–Active: 30 mA max (CMOS/TTL levels)
–Standby: 1 mA max (TTL levels)
–Standby: 100 µA max (CMOS levels)

■ High Speed Programming:

–10 µs per byte
–1 Sec Typ Chip Program

■ 0.5 Seconds Typical Chip-Erase

■ 12.0V ± 5% Programming and Erase Voltage

■ Commercial,Industrial and Automotive

Temperature Ranges

DESCRIPTION

The CAT28F102 is a high speed 64K x 16-bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after-sale
code updates. Electrical erasure of the full memory
contents is achieved typically within 0.5 second.

It is pin and Read timing compatible with standard
EPROM and E2PROM devices. Programming and Erase
are performed through an operation and verify algo­rithm. The instructions are input via the I/O bus, using a

■ 64K x 16 Word Organization

■ Stop Timer for Program/Erase

■ On-Chip Address and Data Latches

■ JEDEC Standard Pinouts:

–40-pin DIP
–44-pin PLCC
–40-pin TSOP

■ 100,000 Program/Erase Cycles

■ 10 Year Data Retention

■ Electronic Signature

two write cycle scheme. Address and Data are latched
to free the I/O bus and address bus during the write
operation.

The CAT28F102 is manufactured using Catalyst’s ad­vanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 40-pin DIP, 44-pin PLCC, or 40-pin TSOP
packages.

BLOCK DIAGRAM

WE

CE
OE

A0–A

15

VOL TAGE VERIFY

© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

COMMAND
REGISTER

SWITCH

ERASE VOL TAGE

SWITCH

PROGRAM VOLTA GE

SWITCH

Y-DECODER

X-DECODER

ADDRESS LATCH

1

CE, OE LOGIC

I/O0–I/O

I/O BUFFERS

DATA

LATCH

1,048,576-BIT

15

Y-GATING

MEMORY

ARRAY

SENSE

AMP

28F101-1

Doc. No. 25038-0A 2/98 F-1

CAT28F102

PIN CONFIGURATION PIN FUNCTIONS

Pin Name Type Function

A0–A

15

Input Address Inputs for

memory addressing

I/O
I/O
I/O

V

I/O
I/O

NC
I/O
I/O
I/O
I/O

SS

12

10

PLCC Package (N)

13

15

14

I/O

I/O

6 5 2 1 44 41 40

7
8

11

4

9
10

9

11

8

12
13
14

7

15

6

16

5

17

4

18 19 22 23 24 27 28

20

2

I/O3I/O

DIP Package (P)

PP

CE

15
14
13
12
11
10

SS

OE

1
2
3
4
5
6
7
8
9

9

10

8

11
12

7

13

6

14

5

15

4

16

3

17

2

18

1

19

0

20

V

I/O
I/O
I/O
I/O
I/O
I/O

I/O
I/O

V

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

I/O

1

I/O

21

PP

CC

NC

CE

V

3

0

OE

I/O

40
39
38
37
36
35
34
33
32
31
30

29
28
27
26
25
24
23
22
21

NC

V

0

A

V
WE
NC
A
A
A
A
A
A
A
V
A
A
A
A
A
A
A
A

A

43

25

CC

15
14
13
12
11
10
9

SS
8

7
6
5
4
3
2
1

0

WE

42

26

1

A

NC

2

A

14

A15A

39
38
37
36
35
34
33
32
31
30
29

4

A3A

28F101-2

A
A
A
A
A
V
NC
A
A
A
A

13
12
11
10
9

SS

8
7
6
5

A

9

A

10

A

11

A

12

A

13

A

14

A

15

NC
WE

V

CC

V

PP
CE

I/O

15

I/O

14

I/O

13

I/O

12

I/O

11

I/O

10

I/O

9

I/O

8

A
A
A
A
A
A
A
A
A

GND

A

A

10

A

11

A

12

A

13

A

14

A

15

NC

WE

V

CC

I/O0–I/O
CE Input Chip Enable
OE Input Output Enable
WE Input Write Enable

V

V

V

NC No Connect

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

1

0

2

1

3

2

4

3

5

4

6

5

7

6

8

7

9

8

10
11

9

12
13
14
15
16
17
18
19
20

15

CC
SS
PP

TSOP Package (T14)

Reverse TSOP Package (T14R)

I/O Data Input/Output

Voltage Supply
Ground
Program/Erase

Voltage Supply

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

28F102 TSOP2

V

SS

A

8

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

OE
I/O

0

I/O

1

I/O

2

I/O

3

I/O

4

I/O

5

I/O

6

I/O

7

V

SS

28F101-3

OE

I/O

0

I/O

1

I/O

2

I/O

3

I/O

4

I/O

5

I/O

6

I/O

7

GND
I/O

8

I/O

9

I/O

10

I/O

11

I/O

12

I/O

13

I/O

14

I/O

15

V

PP

CE

Doc. No. 25038-0A 2/98 F-1

2

CAT28F102

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias ................... –55°C to +95°C

Storage Temperature....................... –65°C to +150°C

Voltage on Any Pin with

Respect to Ground

Voltage on Pin A9 with

Respect to Ground

VPP with Respect to Ground

during Program/Erase

VCC with Respect to Ground

(1)

........... –0.6V to +VCC + 2.0V

(1)

................... –2.0V to +13.5V

(1)

.............. –0.6V to +14.0V

(1)

............ –2.0V to +7.0V

*COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.

Package Power Dissipation

Capability (TA = 25°C).................................. 1.0 W

Lead Soldering Temperature (10 secs) ............ 300°C

Output Short Circuit Current

(2)

........................ 100 mA

RELIABILITY CHARACTERISTICS

Symbol Parameter Min. Max. Units Test Method

(3)

N
T
V
I

LTH

END

DR

ZAP

(3)

(3)

(3)(4)

Endurance 100K Cycles/Byte MIL-STD-883, Test Method 1033
Data Retention 10 Years MIL-STD-883, Test Method 1008
ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
Latch-Up 100 mA JEDEC Standard 17

CAPACITANCE TA = 25°C, f = 1.0 MHz

Limits

Symbol Test Min Max. Units Conditions

(3)

C

IN

(3)

C

OUT

(3)

C

VPP

Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.

Input Pin Capacitance 6 pF V
Output Pin Capacitance 10 pF V

IN
OUT

= 0V

= 0V

VPP Supply Capacitance 25 pF VPP = 0V

3

Doc. No. 25038-0A 2/98 F-1

CAT28F102

D.C. OPERATING CHARACTERISTICS

VCC = +5V ±10%, unless otherwise specified

Limits

Symbol Parameter Min. Max. Unit Test Conditions

I

LI

I

LO

I

SB1

Input Leakage Current ±1 µAV

= VCC or V

IN

SS

VCC = 5.5V, OE = V

Output Leakage Current ±1 µAV

= VCC or VSS,

OUT

VCC = 5.5V, OE = V

VCC Standby Current CMOS 100 µA CE = VCC ±0.5V,

VCC = 5.5V

IH

IH

I

SB2

I

CC1

I

CC2

I

CC3

I

CC4

I

PPS

I

PP1

I

PP2

I

PP3

I

PP4

V
V
V
V
V
V
V
V
I

ID

V

IL
ILC
OL
IH
IHC
OH1
OH2
ID

(1)

LO

VCC Standby Current TTL 1 mA CE = VIH, VCC = 5.5V
VCC Active Read Current 50 mA VCC = 5.5V, CE = VIL,

I

= 0mA, f = 6 MHz

OUT

(1)

VCC Programming Current 30 mA VCC = 5.5V,

Programming in Progress

(1)

VCC Erase Current 30 mA VCC = 5.5V,

Erasure in Progress

(1)

VCC Prog./Erase Verify Current 30 mA VCC = 5.5V, Program or

Erase Verify in Progress
VPP Standby Current ±10 µAVPP = V
VPP Read Current 100 µAVPP = V

(1)

VPP Programming Current 50 mA VPP = V

PPL
PPH
PPH

,

Programming in Progress

(1)

VPP Erase Current 30 mA VPP = V

PPH

,

Erasure in Progress

(1)

VPP Prog./Erase Verify Current 5 mA VPP = V

, Program or

PPH

Erase Verify in Progress
Input Low Level TTL –0.5 0.8 V
Input Low Level CMOS –0.5 0.8 V
Output Low Level 0.45 V IOL = 5.8mA, VCC = 4.5V
Input High Level TTL 2 VCC+0.5 V
Input High Level CMOS VCC*0.7 VCC+0.5 V
Output High Level TTL 2.4 V IOH = –2.5mA, VCC = 4.5V
Output High Level CMOS VCC-0.4 V IOH = –400µA, VCC = 4.5V
A9 Signature Voltage 11.4 13.0 V A9 = V
A9 Signature Current 200 µAA

= V

9

ID
ID

VCC Erase/Prog. Lockout Voltage 2.5 V

Supply Characteristics

VCC VCC Supply Voltage 4.5 5.5 V 28F102-70, 90
VCC VCC Supply Voltage 4.75 5.25 V 28F102-55, -45
V
V

Doc. No. 25038-0A 2/98 F-1

VPP During Read Operations 0 6.5 V

PPL

VPP During Read/Erase/Program 11.4 12.6 V

PPH

4

CAT28F102

A.C. CHARACTERISTICS, Read Operation

VCC = +5V ±10%, unless otherwise specified

JEDEC Standard 28F102-45

Vcc=5V+5%

(7)

28F102-55

Vcc=5V+5%

Symbol Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max Unit

(7)

28F102-70

(7)

28F102- 90

(8)

t

AVAV

t

ELQV

t

AVQV

t

GLQV

t

AXQX

t

RC

t

CE

t

ACC

t

OE

t

OH

Read Cycle Time 45 55 70 90 ns
CE Access Time 45 55 70 90 ns
Address Access Time 45 55 70 90 ns
OE Access Time 20 25 28 35 ns
Output Hold from Address 0 0 0 0 ns

OE/CE Chan

t

GLQX

t

ELQX

t

GHQZ

t

EHQZ

t

WHGL

(1)(2)

(1)(6)

t

OLZ

t

LZ

t

DF

(1)(6)

(1)(2)

OE to Output in Low-Z 0 0 0 0 ns
CE to Output in Low-Z 0 0 0 0 ns
OE High to Output High-Z 15 15 18 20 ns

- CE High to Output High-Z 15 15 25 30 ns
Write Recovery Time Before 6 6 6 6 µs

Read

Figure 1. A.C. Testing Input/Output Waveform

2.4 V
INPUT PULSE LEVELS REFERENCE POINTS

0.45 V

Figure 2. A.C. Testing Load Circuit (example)

(3)(4)(5)

2.0 V

0.8 V

5108 FHD F03

1.3V

1N914

3.3K

DEVICE
UNDER

TEST

CL = 100 pF

Figure 3. High Speed A.C. Testing Input/Output Waveform

3V

2.4 V
INPUT PULSE LEVELS REFERENCE POINTS

0.0

0.45 V

Figure 4. High Speed A.C. Testing Load Circuit (example)

DEVICE
UNDER

TEST

Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.
(3) Input Rise and Fall Times (10% to 90%) < 10 ns.
(4) Input Pulse Levels = 0.45V and 2.4V. For high speed input pulse levels 0.0V and 3.0V.
(5) Input and Output Timing Reference = 0.8V and 2.0V. For high speed input and output timing reference=1.5V.
(6) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.
(7) For Load and Reference Points see Figures 3 and 4
(8) For Load and Reference Points see Figures 1 and 2

2.0 V

1.5V

0.8 V

1.3V

OUT

CL INCLUDES JIG CAPACITANCE

(3)(4)(5)

1N914

3.3K

OUT

CL = 100 pF

30

CL INCLUDES JIG CAPACITANCE

5108 FHD F04

5

Doc. No. 25038-0A 2/98 F-1

CAT28F102

A.C. CHARACTERISTICS, Program/Erase Operation

VCC = +5V ±10%, unless otherwise specified.

JEDEC

Standard

28F102-45 28F102-55 28F102-70 28F102-90

VCC = +5V ±5%

VCC = +5V ±5%

Symbol Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

t

AVAV

t

AVWL

t

WLAX

t

DVWH

t

WHDX

t

ELWL

t

WHEH

t

WLWH

t

WHWL

t

WHWH1

t

WHWH2

t

WHGL

t

WC

t

AS

t

AH

t

DS

t

DH

t

CS

t

CH

t

WP

t

WPH

(2)

- Program Pulse Width 10 10 10 10 µs

(2)

- Erase Pulse Width 9.5 9.5 9.5 9.5 ms

Write Cycle Time 45 55 70 90 ns
Address Setup Time 0 0 0 0 ns
Address Hold Time 30 30 35 40 ns
Data Setup Time 30 30 35 40 ns
Data Hold Time 10 10 10 10 ns

CE Setup Time 0 0 0 0 ns
CE Hold Time 0 0 0 0 ns
WE Pulse Width 30 30 35 40 ns
WE High Pulse Width 20 20 20 20 ns

- Write Recovery Time 6 6 6 6 µs
Before Read

t

GHWL

- Read Recovery Time 0 0 0 0 µs
Before Write

t

VPEL

- VPP Setup Time to CE 100 100 100 100 ns

Erase and Programming Performance

(1)

28F102-45 28F102-55 28F102-70 28F102-90

Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
Chip Erase Time

Chip Program Time

Note:
(1) Please refer to Supply characteristics for the value of V

switched, V
(2) Program and Erase operations are controlled by internal stop timers.
(3) ‘Typicals’ are not guaranteed, but based on characterization data. Data taken at 25°C, 12.0V VPP.
(4) Minimum byte programming time (excluding system overhead) is 16 µs (10 µs program + 6 µs write recovery), while maximum is 400 µs/

byte (16 µs x 25 loops). Max chip programming time is specified lower than the worst case allowed by the programming algorithm since

most bytes program significantly faster than the worst case byte.
(5) Excludes 00H Programming prior to Erasure.

(3)(5)

(3)(4)

can be ground, less than VCC + 2.0V or a no connect with a resistor tied to ground.

PPL

0.5 10 0.5 10 0.5 10 0.5 10 sec
1 6.5 1 6.5 1 6.5 1 6.5 sec

PPH

and V

. The VPP supply can be either hardwired or switched. If VPP is

PPL

Doc. No. 25038-0A 2/98 F-1

6

CAT28F102

FUNCTION TABLE

(1)

Mode CE OE WE V

Read V
Output Disable V
Standby V
Signature (MFG) V
Signature (Device) V
Program/Erase V
Write Cycle V
Read Cycle V
Output Disable V
Standby V

Pins

PP

IL
IL
IH
IL
IL
IL
IL
IL
IL
IH

V

IL

V

IH

XXV

V

IL

V

IL

V

IH

V

IH

V

IL

V

IH

XXV

V

IH

V

IH

V

IH

V

IH

V

IL

V

IL

V

IH

V

IH

V

PPL

X High-Z

PPL

V

PPL

X 0051H A0 = VIH, A9 = 12V

V

PPH

V

PPH

V

PPH

V

PPH
PPH

I/O Notes

D

OUT

High-Z
0031H A0 = VIL, A9 = 12V

D

D
D

OUT

IN
IN

See Command Table
During Write Cycle

During Write Cycle
High-Z During Write Cycle
High-Z During Write Cycle

WRITE COMMAND TABLE

Commands are written into the command register in one or two write cycles. The command register can be altered
only when VPP is high and the instruction byte is latched on the rising edge of WE. Write cycles also internally latch
addresses and data required for programming and erase operations.

Pins

First Bus Cycle Second Bus Cycle

Mode Operation Address D

IN

Set Read Write X XX00H Read A

Operation Address D

IN

IN

D

D

OUT

OUT

Read Sig. (MFG) Write X XX90H Read 0000 0031H
Read Sig. (Device) Write X XX90H Read 0001 0051H
Erase Write X XX20H Write X XX20H
Erase Verify Write A

IN

Program Write X XX40H Write A
Program Verify Write X XXC0H Read X D

XXA0H Read X D

IN

D

IN

OUT

OUT

Reset Write X XXFFH Write X XXFFH

Note:
(1) Logic Levels: X = Logic ‘Do not care’ (VIH, VIL, V

PPL

, V

PPH

)

7

Doc. No. 25038-0A 2/98 F-1

CAT28F102

READ OPERATIONS

Read Mode

A Read operation is performed with both CE and OE low
and with WE high. VPP can be either high or low,
however, if VPP is high, the Set READ command has to
be sent before reading data (see Write Operations). The
data retrieved from the I/O pins reflects the contents of
the memory location corresponding to the state of the 16
address pins. The respective timing waveforms for the
read operation are shown in Figure 5. Refer to the AC
Read characteristics for specific timing parameters.

Signature Mode

The signature mode allows the user to identify the IC
manufacturer and the type of device while the device
resides in the target system. This mode can be activated
in either of two ways; through the conventional method
of applying a high voltage (12V) to address pin A9 or by
sending an instruction to the command register (see
Write Operations).

The conventional mode is entered as a regular READ
mode by driving the CE and OE pins low (with WE high),
and applying the required high voltage on address pin A
while all other address lines are held at VIL.

A Read cycle from address 0000H retrieves the binary
code for the IC manufacturer on outputs I/O0 to I/O15:

CATALYST Code = 0000 0000 0011 0001 (0031H)

A Read cycle from address 0001H retrieves the binary
code for the device on outputs I/O0 to I/O15.

28F102 Code = 0000 0000 0101 0001 (0051H)

Standby Mode

With CE at a logic-high level, the CAT28F102 is placed
in a standby mode where most of the device circuitry is
disabled, thereby substantially reducing power con­sumption. The outputs are placed in a high-impedance
state.

9

Figure 5. A.C. Timing for Read Operation

POWER UP

ADDRESSES

CE (E)

OE (G)

WE (W)

HIGH-Z

DATA (I/O)

STANDBY DEVICE AND

ADDRESS SELECTION

t

WHGL

t

GLQX

ADDRESS STABLE

t

AVAV

(t

)

OLZ

t

(tLZ)

ELQX

t

(t

AVQV

ACC

OUPUTS

ENABLED

(tRC)

t

GLQV

)

(tOE)

DA T A VALID STANDBY

t

EHQZ(tDF

t

GHQZ

t

(tCE)

ELQV

OUTPUT VALID

t

AXQX(tOH

POWER DOWN

)

(tDF)

)

HIGH-Z

Doc. No. 25038-0A 2/98 F-1

28F102 F05

28F102 Fig. 6

8

CAT28F102

WRITE OPERATIONS

The following operations are initiated by observing the
sequence specified in the Write Command Table.

Read Mode

The device can be put into a standard READ mode by
initiating a write cycle with XX00H on the data bus. The
subsequent read cycles will be performed similar to a
standard EPROM or E2PROM Read.

Signature Mode

An alternative method for reading device signature (see
Read Operations Signature Mode), is initiated by writing
the code XX90H into the command register while keep­ing VPP high. A read cycle from address 0000H with CE
and OE low (and WE high) will output the device signa­ture.

CATALYST Code = 0000 0000 0011 0001 (0031H)

Figure 6. A.C. Timing for Erase Operation

A Read cycle from address 0001H retrieves the binary
code for the device on outputs I/O0 to I/O7.

28F102 Code = 0000 0000 0101 0001 (0051H)

Erase Mode

During the first Write cycle, the command XX20H is
written into the command register. In order to commence
the erase operation, the identical command of XX20H
has to be written again into the register. This two-step
process ensures against accidental erasure of the
memory contents. The final erase cycle will be stopped
at the rising edge of WE, at which time the Erase Verify
command (XXA0H) is sent to the command register.
During this cycle, the address to be verified is sent to the
address bus and latched when WE goes low. An inte­grated stop timer allows for automatic timing control over
this operation, eliminating the need for a maximum
erase timing specification. Refer to AC Characteristics
(Program/Erase) for specific timing parameters.

VCC POWER-UP

ADDRESSES

CE (E)

OE (G)

WE (W)

DATA (I/O)

V

V

& STANDBY

5.0V

CC

0V

V

PPH

PP

V

PPL

t

GHWL

HIGH-Z

SETUP ERASE

COMMAND

t

WC

t

CS

t

CH

t

WPH

t

WP

t

DS

t

VPEL

DATA IN
= XX20H

ERASE

COMMAND

t

WC

t

DH
t

DS

ERASING ERASE VERIFY

t

AS

t

CH

t

CS

t

WHWH2

t

WP

t

DH

DATA IN
= XX20H

COMMAND

t

WC

t

WP

t

DS

t

AH

DATA IN
= XXA0H

ERASE

VERIFICATION

t

RC

t

CH

t

WHGL

t

DH

t

OLZ

OE

t
t

LZ
CE

t

VCC POWER-DOWN/

VALID

DATA OUT

STANDBY

t

EHQZ

t

DF

t

OH

28F102 Fig. 6

28F102 F06

9

Doc. No. 25038-0A 2/98 F-1

CAT28F102

Figure 7. Chip Erase Algorithm

START ERASURE

APPLY V

PROGRAM ALL

BYTES TO 0000H

PLSCNT = 0

WRITE ERASE

SETUP COMMAND

WRITE ERASE

PPH

INITIALIZE

ADDRESS

INITIALIZE

COMMAND

(1)

BUS

OPERATION

STANDBY

WRITE

WRITE

COMMAND COMMENTS

VPP RAMPS TO V

(OR VPP HARDWIRED)

ALL BYTES SHALL BE

PROGRAMMED TO 00

BEFORE AN ERASE

OPERATION

INITIALIZE ADDRESS

PLSCNT = PULSE COUNT

ERASE

ERASE

DATA = XX20H

DATA = XX20H

PPH

INCREMENT

ADDRESS

TIME OUT 10ms

WRITE ERASE

VERIFY COMMAND

TIME OUT 6µs

READ DATA

FROM DEVICE

DATA =

FFH?

NO

LAST

ADDRESS?

WRITE READ

COMMAND

YES

YES

NO

NO

INC PLSCNT

= 1000 ?

YES

WRITE

READ

STANDBY

WRITE

ERASE

VERIFY

READ

WAIT

ADDRESS = BYTE TO VERIFY

DATA = XXA0H

STOPS ERASE OPERA TION

WAIT

READ BYTE TO

VERIFY ERASURE

COMPARE OUTPUT TO FF

INCREMENT PULSE COUNT

DATA = 0000H

RESETS THE REGISTER

FOR READ OPERATION

APPLY V

COMPLETED

Note:
(1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.

Doc. No. 25038-0A 2/98 F-1

PPL

ERASURE

APPLY V

ERASE

ERROR

PPL

STANDBY

10

VPP RAMPS TO V

(OR VPP HARDWIRED)

PPL

28F101-07

CAT28F102

ADDRESSES

CE (E)

OE (G)

WE (W)

DATA (I/O)

V

CC

V

PP

t

WC

t

WC

t

RC

t

AS

t

AH

t

CS

t

CH

t

CS

t

CH

t

CH

t

EHQZ

t

DF

t

GHWL

t

WPH

t

WHWH1

t

WHGL

t

WP

t

DS

HIGH-Z

DATA IN
= XX 40H

DATA IN

DATA IN
= XX C0H

VALID

DATA OUT

t

DH

t

WP

t

DH

t

DS

t

DS

t

WP

t

DH

t

OLZ

t

OE

t

OH

t

LZ

t

CE

t

VPEL

V

PPH

V

PPL

0V

5.0V

VCC POWER-UP

& STANDBY

SETUP PROGRAM

COMMAND

LATCH ADDRESS

& DATA

PROGRAMMING

PROGRAM

VERIFY

COMMAND

PROGRAM

VERIFICATION

VCC POWER-DOWN/

STANDBY

Erase-Verify Mode

The Erase-verify operation is performed on every byte
after each erase pulse to verify that the bits have been
erased.

Programming Mode

The programming operation is initiated using the pro­gramming algorithm of Figure 9. During the first write
cycle, the command XX40H is written into the command
register. During the second write cycle, the address of
the memory location to be programmed is latched on the
falling edge of WE, while the data is latched on the rising
edge of WE. The program operation terminates with the
next rising edge of WE. An integrated stop timer allows
for automatic timing control over this operation, eliminat­ing the need for a maximum program timing specifica­tion. Refer to AC Characteristics (Program/Erase) for
specific timing parameters.

Figure 8. A.C. Timing for Programming Operation

Program-Verify Mode

A Program-verify cycle is performed to ensure that all
bits have been correctly programmed following each
byte programming operation. The specific address is
already latched from the write cycle just completed, and
stays latched until the verify is completed. The Program­verify operation is initiated by writing XXC0H into the
command register. An internal reference generates the
necessary high voltages so that the user does not need
to modify VCC. Refer to AC Characteristics (Program/
Erase) for specific timing parameters.

11

28F102 F07

Doc. No. 25038-0A 2/98 F-1

CAT28F102

Figure 9. Programming Algorithm

START

PROGRAMMING

APPLY V

PLSCNT = 0

WRITE SETUP

PROG. COMMAND

WRITE PROG. CMD

ADDR AND DAT A

TIME OUT 10µs

PPH

INITIALIZE
ADDRESS

(1)

BUS

OPERATION

STANDBY

1ST WRITE

CYCLE

2ND WRITE

CYCLE

COMMAND COMMENTS

VPP RAMPS TO V

(OR VPP HARDWIRED)

INITIALIZE ADDRESS

INITIALIZE PULSE COUNT

PLSCNT = PULSE COUNT

WRITE
SETUP

PROGRAM

DATA = XX40H

VALID ADDRESS AND DA T A

WAIT

PPH

INCREMENT

ADDRESS

WRITE PROGRAM

VERIFY COMMAND

TIME OUT 6µs

READ DATA

FROM DEVICE

VERIFY
DATA ?

NO

LAST

ADDRESS?

WRITE READ

COMMAND

APPLY V

YES

YES

PPL

NO

INC

PLSCNT

= 25 ?

APPLY V

NO

YES

PPL

1ST WRITE

CYCLE

READ

STANDBY

1ST WRITE

CYCLE

STANDBY

PROGRAM

VERIFY

READ

DATA = XXC0H

WAIT

READ BYTE TO VERIFY

PROGRAMMING

COMPARE DATA OUTPUT

TO DATA EXPECTED

DATA = XX00H

SETS THE REGISTER FOR

READ OPERATION

VPP RAMPS TO V

(OR VPP HARDWIRED)

PPL

PROGRAMMING

COMPLETED

Note:
(1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.

Doc. No. 25038-0A 2/98 F-1

PROGRAM

ERROR

12

28F101-09

CAT28F102

Abort/Reset

An Abort/Reset command is available to allow the user
to safely abort an erase or program sequence. Two
consecutive program cycles with XXFFH on the data
bus will abort an erase or a program operation. The
abort/reset operation can interrupt at any time in a
program or erase operation and the device is reset to the
Read Mode.

DATA PROTECTION

1. Power Supply Voltage
When the power supply voltage (VCC) is less than 2.5V,

the device ignores WE signal.

2. Write Inhibit
When CE and OE are terminated to the low level, write

mode is not set.

POWER UP/DOWN PROTECTION

The CAT28F102 offers protection against inadvertent
programming during VPP and VCC power transitions.
When powering up the device there is no power-on
sequencing necessary. In other words, VPP and V

CC

may power up in any order. Additionally VPP may be
hardwired to V

independent of the state of VCC and

PPH

any power up/down cycling. The internal command
register of the CAT28F102 is reset to the Read Mode on
power up.

POWER SUPPLY DECOUPLING

To reduce the effect of transient power supply voltage
spikes, it is good practice to use a 0.1µF ceramic
capacitor between VCC and VSS and VPP and VSS. These
high-frequency capacitors should be placed as close as
possible to the device for optimum decoupling.

Figure 10. Alternate A.C. Timing for Program Operation

VCC POWER-UP

& STANDBY

ADDRESSES

WE (E)

OE (G)

CE (W)

DATA (I/O)

V

CC

V

PP

5.0V
0V
V

PPH

V

PPL

SETUP PROGRAM

COMMAND

t

GHEL

t

DVEH

HIGH-Z

t

WC

t

EHWH

t

VPEL

t

AVEL

t

WLEL

t

EHEL

DATA IN
= XX40H

LATCH ADDRESS

& DATA

t

ELAX

t

WLEL

t

EHDX

DATA IN

PROGRAMMING

t

EHWH

t

WLEL

t

EHEH

t

ELEH

t

t

DVEH

EHDX

PROGRAM

VERIFY

COMMAND

t

ELEH

t

DVEH

t

WC

t

DATA IN
= XXC0H

EHWH

t

EHGL

VERIFICATION

t

OE

t

EHDX

t

OLZ

t

LZ

t

CE

PROGRAM

t

RC

DATA OUT

VCC POWER-DOWN/

STANDBY

t

EHQZ

t

DF

t

OH

VALID

28F102 F10

13

Doc. No. 25038-0A 2/98 F-1

CAT28F102

ALTERNATE CE-CONTROLLED WRITES

VCC = +5V ±10%, unless otherwise specified.

28F102-45 28F102-55 28F102-70 28F102-90

JEDEC Standard

VCC = +5V ±5%

Symbol Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

t

AVAV WC

t

AVEL

t

ELAX

t

DVEH

t

EHDX tDH

t

EHGL

t

AS

t

AH

t

DS

- Write Recovery Time Before 6 6 6 6 µs

Write Cycle Time 45 55 70 90 ns
Address Setup Time 0 0 0 0 ns
Address Hold Time 30 30 35 40 ns
Data Setup Time 30 30 35 40 ns
Data Hold Time 10 10 10 10 ns

Read

VCC = +5V ±5%

t

GHEL

- Read Recovery Time Before 0 0 0 0 µs
Write

t

WLEL

t

EHWHtWH

t

ELEH

t

EHEL

t

VPEL

t

WS

WE Setup Time Before CE 00 0 0 ns
WE Hold Time After CE 00 0 0 ns

t

CP

t

CPH

-V

Write Pulse Width 30 30 35 40 ns
Write Pulse Width High 20 20 20 20 ns

Setup Time to CE Low 100 100 100 100 ns

PP

ORDERING INFORMATION

Prefix Device # Suffix

28F102 N

Product
Number

Optional
Company ID

I

Temperature Range

Blank = Commercial (0˚ - 70˚C)
I = Industrial (-40˚ - 85˚C)
A = Automotive (-40˚ - 105˚C)*

Package

N: PLCC
P: PDIP
T14: TSOP
T14R: TSOP

-90CA T

Speed

45: 45ns
55: 55ns
70: 70ns
90: 90ns

T

Tape & Reel

T: 500/Reel

*-40o to + 125oC is available upon request

Note:
(1) The device used in the above example is a CAT28F102NI-90T (PLCC, Industrial Temperature, 90 ns access time, Tape & Reel).

Doc. No. 25038-0A 2/98 F-1

14