CTLST CAT25C16UA-1.8TE13, CAT25C16U14I-TE13, CAT25C16U14I-1.8TE13, CAT25C16U14A-TE13, CAT25C16U14A-1.8TE13 Datasheet

Advanced Information

CAT25C01/02/04/08/16

1K/2K/4K/8K/16K SPI Serial CMOS E2PROM

FEATURES

■ 10 MHz SPI Compatible

■ 1.8 to 6.0 Volt Operation

■ Hardware and Software Protection

■ Zero Standby Current

■ Low Power CMOS Technology

■ SPI Modes (0,0 & 1,1)

■ Commercial, Industrial and Automotive

Temperature Ranges

DESCRIPTION

■ 1,000,000 Program/Erase Cycles

■ 100 Year Data Retention

■ Self-Timed Write Cycle

■ 8-Pin DIP/SOIC, 8/14-Pin TSSOP and 8-Pin MSOP

■ 16/32-Byte Page Write Buffer

■ Block Write Protection

– Protect 1/4, 1/2 or all of E2PROM Array

The CAT25C01/02/04/08/16 is a 1K/2K/4K/8K/16K Bit
SPI Serial CMOS E2PROM internally organized as
128x8/256x8/512x8/1024x8/2048x8 bits. Catalyst’s ad­vanced CMOS Technology substantially reduces de­vice power requirements. The CAT25C01/02/04 fea­tures a 16-byte page write buffer. The 25C08/16 fea­tures a 32-byte page write buffer.The device operates
via the SPI bus serial interface and is enabled though a
Chip Select (CS). In addition to the Chip Select, the clock

PIN CONFIGURATION

TSSOP Package (U14)

1

CS

SO

2
3

NC

NC

4

NC NC

WP

6

V

7

SS

14

VCC

13

HOLD

12

NC

11

NC

10

5

9

SCK
SI

8

PIN FUNCTIONS

Pin Name Function

SO Serial Data Output
SCK Serial Clock

WP Write Protect
V

CC

V

SS

CS Chip Select
SI Serial Data Input
HOLD Suspends Serial Input
NC No Connect

+1.8V to +6.0V Power Supply
Ground

SOIC Package (S)

1

8

V

CC

7

HOLD

6

SCK

5

SI

V

CS

SO

WP

SS

2
3
4

MSOP Package (R)*

1

8

CS

2

SO

3

WP

4

V

SS

*CAT 25C01/02 only

V

CC

7

HOLD

6

SCK

5

SI

input (SCK), data in (SI) and data out (SO) are required
to access the device. The HOLD pin may be used to
suspend any serial communication without resetting the
serial sequence. The CAT25C01/02/04/08/16 is de­signed with software and hardware write protection
features including Block Write protection. The device is
available in 8-pin DIP, 8-pin SOIC, 8-pin MSOP and 8/
14-pin TSSOP packages.

DIP Package (P)

1

CS

2

SO

3

WP

V

SS

4

8

V

CC

7

HOLD

6

SCK

5

SI

TSSOP Package (U)

1

CS

2

SO

3

WP

4

V

SS

BLOCK DIAGRAM

SENSE AMPS

SHIFT REGISTERS

COLUMN

DECODERS

E2PROM

ARRAY

DATA IN

STORAGE

HIGH VOL T A GE/

TIMING CONTROL

SO

SI

CS

WP

HOLD

SCK

WORD ADDRESS

BUFFERS

I/O

CONTROL

SPI

CONTROL

LOGIC

BLOCK

PROTECT

LOGIC

STATUS

REGISTER

CONTROL LOGIC

XDEC

8

V

7

HOLD

6

SCL

5

SI

25C128 F02

CC

© 1999 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

1

Doc. No. 25067-00 5/00

CAT25C01/02/04/08/16

Advanced Information

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias ................. –55°C to +125°C

Storage Temperature....................... –65°C to +150°C

Voltage on any Pin with

Respect to V

with Respect to V

V

CC

Package Power Dissipation

Capability (Ta = 25°C)................................... 1.0W

(1)

.................. –2.0V to +VCC +2.0V

SS

................................ –2.0V to +7.0V

SS

*COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica­tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor­mance and reliability.

Lead Soldering Temperature (10 secs) ............ 300°C

Output Short Circuit Current

(2)

........................ 100 mA

RELIABILITY CHARACTERISTICS

Symbol Parameter Min. Max. Units Reference Test Method

(3)

N
T
V
I

LTH

END

DR

ZAP

(3)

(3)

(3)(4)

Endurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033
Data Retention 100 Years MIL-STD-883, Test Method 1008
ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
Latch-Up 100 mA JEDEC Standard 17

D.C. OPERATING CHARACTERISTICS

VCC = +1.8V to +6.0V, unless otherwise specified.

Limits

Symbol Parameter Min. Typ. Max. Units Test Conditions

I

CC1

Power Supply Current 5 mA VCC = 5V @ 5MHz
(Operating Write) SO=open; CS=Vss

I

CC2

I

SB

I

LI

I

LO

Power Supply Current 3 mA VCC = 5.5V
(Operating Read) F

Power Supply Current 0 µA CS = V

= 5MHz

CLK

CC

(Standby) VIN = VSS or V
Input Leakage Current 2 µA
Output Leakage Current 3 µAV

= 0V to VCC,

OUT

CC

CS = 0V

(3)

V

IL

(3)

V

IH

V

OL1

V

OH1

V

OL2

V

OH2

Input Low Voltage -1 VCC x 0.3 V
Input High Voltage VCC x 0.7 V
Output Low Voltage 0.4 V
Output High Voltage VCC - 0.8 V

+ 0.5 V

CC

4.5V≤VCC<5.5V
IOL = 3.0mA
IOH = -1.6mA

Output Low Voltage 0.2 V 1.8V≤VCC<2.7V
Output High Voltage VCC-0.2 V IOL = 150µA

IOH = -100µA

Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.

Doc. No. 25067-00 5/00

2

Advanced Information

Figure 1. Sychronous Data Timing

V

IH

CS

V

IL

t

CSS

V

SCK

SO

Note: Dashed Line= mode (1, 1) – ––––

A.C. CHARACTERISTICS

IH

V

IL

V

IH

SI

V

IL

V

OH

HI-Z

V

OL

t

SU

VALID IN

t

WH

CAT25C01/02/04/08/16

t

CS

t

CSH

t

WL

t

H

t

RI

t

FI

t

V

t

HO

t

DIS

HI-Z

Limits

1.8V-6.0V 2.5V-6.0V 4.5V-5.5V Test

SYMBOL PARAMETER Min. Max. Min. Max. Min. Max. UNITS Conditions

t

SU

t

H

t

WH

t

WL

f

SCK

t

LZ

t

RI

t

FI

t

HD

t

CD

t

WC

t

V

t

HO

t

DIS

(1)

(1)

Data Setup Time 50 20 20 ns VIH = 2.4V
Data Hold Time 50 20 20 ns CL = 100pF
SCK High Time 250 75 40 ns VOL = 0.8V
SCK Low Time 250 75 40 ns VOH = 2.0v
Clock Frequency DC 1 DC 5 DC 10 MHz
HOLD to Output Low Z 50 50 50 ns
Input Rise Time 2 2 2 µs
Input Fall Time 2 2 2 µs

HOLD Setup Time 100 40 40 ns
HOLD Hold Time 100 40 40 ns CL = 100pF

CL = 50pF

Write Cycle Time 10 5 5 ms
Output Valid from Clock Low 250 80 80 ns
Output Hold Time 0 0 0 ns
Output Disable Time 250 75 75 ns

t

HZ

t

CS

t

CSS

t

CSH

t

WPS

t

WPH

NOTE:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

HOLD to Output High Z 150 50 50 ns
CS High Time 500 100 100 ns
CS Setup Time 500 100 100 ns
CS Hold Time 500 100 100 ns
WP Setup Time 150 50 50 ns
WP Hold Time 150 50 50 ns

3

Doc. No. 25067-00 5/00