CTLST CAT24WC65J-TE13, CAT24WC65J-1.8TE13, CAT24WC65KI-TE13, CAT24WC65KI-1.8TE13, CAT24WC65KA-TE13 Datasheet
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Preliminary
CAT24WC33/65
32K/64K-Bit I2C Serial CMOS E2PROM
FEATURES
■ 400 KHz I
■ 1.8 to 6 Volt Read and Write Operation
■ Cascadable for up to Eight Devices
■ 32-Byte Page Write Buffer
■ Self-Timed Write Cycle with Auto-Clear
■ 8-Pin DIP or 8-Pin SOIC
■ Schmitt Trigger Inputs for Noise Protection
DESCRIPTION
2
C Bus Compatible*
■ Zero Standby Current
■ Commercial, Industrial and Automotive Tem-
perature Ranges
■ Write Protection
–Bottom 1/4 Array Protected When WP at V
■ 1,000,000 Program/Erase Cycles
■ 100 Year Data Retention
IH
The CAT24WC33/65 is a 32K/64K-bit Serial CMOS
E2PROM internally organized as 4096/8192 words of 8
bits each. Catalyst’s advanced CMOS technology sub-
CAT24WC33/65 features a 32-byte page write buffer.
The device operates via the I2C bus serial interface and
is available in 8-pin DIP or 8-pin SOIC packages.
stantially reduces device power requirements. The
PIN CONFIGURATION BLOCK DIAGRAM
DIP Package (P)
1
A
0
A
1
A
2
V
SS
8
2
7
3
6
4
5
SOIC Package (J,K)
1
A
0
A
1
A
2
V
SS
8
2
7
3
6
4
5
V
CC
WP
SCL
SDA
V
CC
WP
SCL
SDA
24WC33/65 F01
EXTERNAL LOAD
V
CC
V
SS
SDA
WP
D
OUT
ACK
WORD ADDRESS
BUFFERS
STAR T/STOP
LOGIC
CONTROL
LOGIC
PIN FUNCTIONS
Pin Name Function
A0, A1, A2 Device Address Inputs
XDEC
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
128/256
E2PROM
128/256 X 256
DATA IN STORAGE
256
SDA Serial Data/Address
SCL Serial Clock
WP Write Protect
V
CC
V
SS
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
+1.8V to +6V Power Supply
Ground
SCL
A
A1
A2
1
STATE COUNTERS
0
SLAVE
ADDRESS
COMPARATORS
HIGH VOL TAGE/
TIMING CONTROL
24WC33/65 F02
Doc. No. 25064-00 2/98 S-1
PreliminaryCAT24WC33/65
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
(1)
........... –2.0V to +V
CC
+ 2.0V
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol Parameter Min. Max. Units Reference Test Method
(3)
N
T
V
I
LTH
END
DR
ZAP
(3)
(3)
(3)(4)
Endurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033
Data Retention 100 Years MIL-STD-883, Test Method 1008
ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
Latch-up 100 mA JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
Limits
Symbol Parameter Min. Typ. Max. Units Test Conditions
I
I
I
I
V
V
V
V
CC
SB
LI
LO
IL
IH
OL1
OL2
(5)
Power Supply Current 3 mA f
= 100 KHz
SCL
Standby Current (VCC = 5V) 0 µAVIN = GND or V
Input Leakage Current 10 µAVIN = GND to V
Output Leakage Current 10 µAV
= GND to V
OUT
Input Low Voltage –1 VCC x 0.3 V
Input High Voltage VCC x 0.7 VCC + 0.5 V
Output Low Voltage (VCC = +3.0V) 0.4 V IOL = 3.0 mA
Output Low Voltage (VCC = +1.8V) 0.5 V IOL = 1.5 mA
CC
CC
CC
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol Test Max. Units Conditions
(3)
C
I/O
(3)
C
IN
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(5) Standby current (ISB ) = 0 µA (<900 nA).
Input/Output Capacitance (SDA) 8 pF V
Input Capacitance (A0, A1, A2, SCL, WP) 6 pF V
I/O
IN
= 0V
= 0V
Doc. No. 25064-00 2/98 S-1
2
Preliminary CAT24WC33/65
A.C. CHARACTERISTICS
VCC = +1.8V to +6V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol Parameter 1.8V, 2.5V 4.5V-5.5V
Min. Max. Min. Max. Units
F
SCL
(1)
T
I
t
AA
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
(1)
t
R
(1)
t
F
t
SU:STO
t
DH
(1)
Clock Frequency 100 400 kHz
Noise Suppression Time 200 200 ns
Constant at SCL, SDA Inputs
SCL Low to SDA Data Out 3.5 1 µs
and ACK Out
Time the Bus Must be Free Before 4.7 1.2 µs
a New Transmission Can Start
Start Condition Hold Time 4 0.6 µs
Clock Low Period 4.7 1.2 µs
Clock High Period 4 0.6 µs
Start Condition Setup Time 4.7 0.6 µs
(for a Repeated Start Condition)
Data In Hold Time 0 0 ns
Data In Setup Time 50 50 ns
SDA and SCL Rise Time 1 0.3 µs
SDA and SCL Fall Time 300 300 ns
Stop Condition Setup Time 4 0.6 µs
Data Out Hold Time 100 100 ns
Power-Up Timing
(1)(2)
Symbol Parameter Max. Units
t
PUR
t
PUW
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
Power-Up to Read Operation 1 ms
Power-Up to Write Operation 1 ms
are the delays required from the time VCC is stable until the specified operation can be initiated.
PUW
Write Cycle Limits
Symbol Parameter Min. Typ. Max Units
t
WR
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
Write Cycle Time 10 ms
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
3
Doc. No. 25064-00 2/98 S-1
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