CTLST CAT24WC64PI-TE13, CAT24WC64PI-1.8TE13, CAT24WC64PA-1.8TE13, CAT24WC64P-TE13, CAT24WC64P-1.8TE13 Datasheet
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1
D
OUT
ACK
SENSE AMPS
SHIFT REGISTERS
CONTROL
LOGIC
WORD ADDRESS
BUFFERS
STAR T/STOP
LOGIC
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
E2PROM
128/256 X 256
V
CC
EXTERNAL LOAD
COLUMN
DECODERS
XDEC
DATA IN STORAGE
HIGH VOL TAGE/
TIMING CONTROL
V
SS
WP
SCL
A
0
A1
A2
SDA
128/256
256
V
CC
WP
SCL
SDA
1
2
3
4
8
7
6
5
A
0
V
CC
WP
SCL
SDA
1
2
3
4
8
7
6
5
A
1
A
2
V
SS
A
0
A
1
A
2
V
SS
DESCRIPTION
The CAT24WC32/64 is a 32K/64K-bit Serial CMOS
E2PROM internally organized as 4096/8192 words of 8
bits each. Catalyst’s advanced CMOS technology substantially reduces device power requirements. The
Preliminary
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
■ Zero Standby Current
■ Commercial, Industrial and Automotive
Temperature Ranges
■ Write Protection
– Entire Array Protected When WP at V
IH
■ 1,000,000 Program/Erase Cycles
■ 100 Year Data Retention
CAT24WC32/64 features a 32-byte page write buffer.
The device operates via the I2C bus serial interface and
is available in 8-pin DIP or 8-pin SOIC packages.
PIN CONFIGURATION BLOCK DIAGRAM
PIN FUNCTIONS
Pin Name Function
A0, A1, A2 Device Address Inputs
SDA Serial Data/Address
SCL Serial Clock
WP Write Protect
V
CC
+1.8V to +6V Power Supply
V
SS
Ground
24WC32/64 F02
CAT24WC32/64
32K/64K-Bit I2C Serial CMOS E2PROM
■ 400 KHz I
2
C Bus Compatible*
■ 1.8 to 6 Volt Read and Write Operation
■ Cascadable for up to Eight Devices
■ 32-Byte Page Write Buffer
■ Self-Timed Write Cycle with Auto-Clear
■ 8-Pin DIP or 8-Pin SOIC
■ Schmitt Trigger Inputs for Noise Protection
FEATURES
DIP Package (P)
SOIC Package (J,K)
24WC32/64 F01
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 25053-00 2/98 S-1
PreliminaryCAT24WC32/64
2
Doc. No. 25053-00 2/98 S-1
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(1)
........... –2.0V to +V
CC
+ 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100mA
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
RELIABILITY CHARACTERISTICS
Symbol Parameter Min. Max. Units Reference Test Method
N
END
(3)
Endurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033
T
DR
(3)
Data Retention 100 Years MIL-STD-883, Test Method 1008
V
ZAP
(3)
ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
I
LTH
(3)(4)
Latch-up 100 mA JEDEC Standard 17
Limits
Symbol Parameter Min. Typ. Max. Units Test Conditions
I
CC
Power Supply Current 3 mA f
SCL
= 100 KHz
I
SB
(5)
Standby Current (VCC = 5V) 0 µAVIN = GND or V
CC
I
LI
Input Leakage Current 10 µAVIN = GND to V
CC
I
LO
Output Leakage Current 10 µAV
OUT
= GND to V
CC
V
IL
Input Low Voltage –1 VCC x 0.3 V
V
IH
Input High Voltage VCC x 0.7 VCC + 0.5 V
V
OL1
Output Low Voltage (VCC = +3.0V) 0.4 V IOL = 3.0 mA
V
OL2
Output Low Voltage (VCC = +1.8V) 0.5 V IOL = 1.5 mA
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol Test Max. Units Conditions
C
I/O
(3)
Input/Output Capacitance (SDA) 8 pF V
I/O
= 0V
C
IN
(3)
Input Capacitance (A0, A1, A2, SCL, WP) 6 pF V
IN
= 0V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(5) Standby current (ISB ) = 0 µA (<900 nA).
Preliminary CAT24WC32/64
3
Doc. No. 25053-00 2/98 S-1
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
A.C. CHARACTERISTICS
VCC = +1.8V to +6V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol Parameter 1.8V, 2.5 V 4.5V-5.5V
Min. Max. Min. Max. Units
F
SCL
Clock Frequency 100 400 kHz
T
I
(1)
Noise Suppression Time 200 200 ns
Constant at SCL, SDA Inputs
t
AA
SCL Low to SDA Data Out 3.5 1 µs
and ACK Out
t
BUF
(1)
Time the Bus Must be Free Before 4.7 1.2 µs
a New Transmission Can Start
t
HD:STA
Start Condition Hold Time 4 0.6 µs
t
LOW
Clock Low Period 4.7 1.2 µs
t
HIGH
Clock High Period 4 0.6 µs
t
SU:STA
Start Condition Setup Time 4.7 0.6 µs
(for a Repeated Start Condition)
t
HD:DAT
Data In Hold Time 0 0 ns
t
SU:DAT
Data In Setup Time 50 50 ns
t
R
(1)
SDA and SCL Rise Time 1 0.3 µs
t
F
(1)
SDA and SCL Fall Time 300 300 ns
t
SU:STO
Stop Condition Setup Time 4 0.6 µs
t
DH
Data Out Hold Time 100 100 ns
Power-Up Timing
(1)(2)
Symbol Parameter Max. Units
t
PUR
Power-Up to Read Operation 1 ms
t
PUW
Power-Up to Write Operation 1 ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time VCC is stable until the specified operation can be initiated.
Write Cycle Limits
Symbol Parameter Min. Typ. Max Units
t
WR
Write Cycle Time 10 ms
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