CTLST CAT24WC256KA-3TE13, CAT24WC256KA-1.8TE13, CAT24WC256K-TE13, CAT24WC256K-3TE13, CAT24WC256K-1.8TE13 Datasheet

1

A1

NC

V

SS

A1
NC

V

CC

WP
SCL
SDA

1
2
3
4

8
7
6
5

A0

V

CC

WP
SCL
SDA

1
2
3
4

8
7
6
5

V

SS

A0

PIN FUNCTIONS

Pin Name Function

A0, A1 Address Inputs
SDA Serial Data/Address
SCL Serial Clock
WP Write Protect
V

CC

+1.8V to +6.0V Power Supply

V

SS

Ground

NC No Connect

DESCRIPTION

The CAT24WC256 is a 256K-bit Serial CMOS E2PROM
internally organized as 32,768 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements. The

Preliminary

* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.

■ Write Protect Feature

– Entire Array Protected When WP at V

IH

■ 100,000 Program/Erase Cycles

■ 100 Year Data Retention

■ 8-Pin DIP or 8-Pin SOIC

CAT24WC256 features a 64-byte page write buffer. The
device operates via the I2C bus serial interface and is
available in 8-pin DIP or 8-pin SOIC packages.

PIN CONFIGURATION

BLOCK DIAGRAM

24WC256 F02

CAT24WC256

256K-Bit I2C Serial CMOS E2PROM

■ 1MHz I

2

C Bus Compatible*

■ 1.8 to 6 Volt Operation

■ Low Power CMOS Technology

■ 64-Byte Page Write Buffer

■ Self-Timed Write Cycle with Auto-Clear

■ Commercial, Industrial and Automotive

Temperature Ranges

FEATURES

DIP Package (P)

SOIC Package (K)

24WC256 F01

© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

D

OUT

ACK

SENSE AMPS

SHIFT REGISTERS

CONTROL

LOGIC

WORD ADDRESS

BUFFERS

STAR T/STOP

LOGIC

STATE COUNTERS
SLAVE

ADDRESS
COMPARATORS

E2PROM
512X512

V

CC

EXTERNAL LOAD

COLUMN

DECODERS

XDEC

DATA IN STORAGE

HIGH VOL TAGE/

TIMING CONTROL

V

SS

WP

SCL

SDA

512

512

A0
A1

Doc. No. 25061-00 6/99 S-1

PreliminaryCAT24WC256

2

Doc. No. 25061-00 6/99 S-1

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias ................. –55°C to +125°C

Storage Temperature....................... –65°C to +150°C

Voltage on Any Pin with

Respect to Ground

(1)

........... –2.0V to +V

CC

+ 2.0V

VCC with Respect to Ground ............... –2.0V to +7.0V

Package Power Dissipation

Capability (Ta = 25°C)................................... 1.0W

Lead Soldering Temperature (10 secs)............ 300°C

Output Short Circuit Current

(2)

........................ 100mA

*COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.

RELIABILITY CHARACTERISTICS

Symbol Parameter Min. Max. Units Reference Test Method

N

END

(3)

Endurance 100,000 Cycles/Byte MIL-STD-883, Test Method 1033

T

DR

(3)

Data Retention 100 Years MIL-STD-883, Test Method 1008

V

ZAP

(3)

ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015

I

LTH

(3)(4)

Latch-up 100 mA JEDEC Standard 17

CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V

Symbol Test Max. Units Conditions

C

I/O

(3)

Input/Output Capacitance (SDA) 8 pF V

I/O

= 0V

C

IN

(3)

Input Capacitance (SCL, WP, A0, A1) 6 pF V

IN

= 0V

Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(5) Standby current (ISB ) = 0 µA (<900 nA).

Limits

Symbol Parameter Min. Typ. Max. Units Test Conditions

I

CC1

Power Supply Current - Read 1 mA f

SCL

= 100 KHz

VCC=5V

I

CC2

Power Supply Current - Write

3mAf

SCL

= 100KHz

VCC=5V

I

SB

(5)

Standby Current 0 µAVIN = GND or V

CC

VCC=5V

I

LI

Input Leakage Current 1 µAVIN = GND to V

CC

I

LO

Output Leakage Current 1 µAV

OUT

= GND to V

CC

V

IL

Input Low Voltage –1 VCC x 0.3 V

V

IH

Input High Voltage VCC x 0.7 VCC + 0.5 V

V

OL1

Output Low Voltage (VCC = +3.0V) 0.4 V IOL = 3.0 mA

V

OL2

Output Low Voltage (VCC = +1.8V) 0.5 V IOL = 1.5 mA

D.C. OPERATING CHARACTERISTICS

VCC = +1.8V to +6.0V, unless otherwise specified.

Preliminary CAT24WC256

3

Doc. No. 25061-00 6/99 S-1

Power-Up Timing

(2)(3)

Symbol Parameter Max. Units

t

PUR

Power-Up to Read Operation 1 ms

t

PUW

Power-Up to Write Operation 1 ms

Note:
(1) AC measurement conditions:
RL (connects to VCC): 0.3VCC to 0.7 V

CC

Input rise and fall times: < 50ns
Input and output timing reference voltages: 0.5 V

CC

(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t

PUR

and t

PUW

are the delays required from the time VCC is stable until the specified operation can be initiated.

The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus

interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.

A.C. CHARACTERISTICS

VCC = +1.8V to +6V, unless otherwise specified

Output Load is 1 TTL Gate and 100pF

Read & Write Cycle Limits

Symbol Parameter VCC=1.8V - 6.0V VCC=2.5V - 6.0V VCC=3.0V - 5.5V

Min. Max. Min. Max. Min. Max. Units

F

SCL

Clock Frequency 100 400 1000 kHz

t

AA

SCL Low to SDA Data Out 0.1 3.5 0.05 0.9 0.05 0.55 µs
and ACK Out

t

BUF

(2)

Time the Bus Must be Free Before 4.7 1.2 0.5 µs
a New Transmission Can Start

t

HD:STA

Start Condition Hold Time 4.0 0.6 0.25 µs

t

LOW

Clock Low Period 4.7 1.2 0.6 µs

t

HIGH

Clock High Period 4.0 0.6 0.4 µs

t

SU:STA

Start Condition Setup Time 4.0 0.6 0.25 µs
(for a Repeated Start Condition)

t

HD:DAT

Data In Hold Time 0 0 0 ns

t

SU:DAT

Data In Setup Time 100 100 100 ns

t

R

(2)

SDA and SCL Rise Time 1.0 0.3 0.3 µs

t

F

(2)

SDA and SCL Fall Time 300 300 100 ns

t

SU:STO

Stop Condition Setup Time 4.7 0.6 0.25 µs

t

DH

Data Out Hold Time 100 50 50 ns

t

WR

Write Cycle Time 10 10 5 ms