CTLST CAT24C44SI-TE13, CAT24C44SA-TE13, CAT24C44S-TE13, CAT24C44PI-TE13, CAT24C44PA-TE13 Datasheet

CAT24C44

256-Bit Serial Nonvolatile CMOS Static RAM

FEATURES

■ Single 5V Supply

■ Infinite E

■ CMOS and TTL Compatible I/O

■ Low CMOS Power Consumption:

2

PROM to RAM Recall

–Active: 3 mA Max.
–Standby: 30 µA Max.

■ Power Up/Down Protection

■ 10 Year Data Retention

DESCRIPTION

The CAT24C44 Serial NVRAM is a 256-bit nonvolatile
memory organized as 16 words x 16 bits. The high
speed Static RAM array is bit for bit backed up by a
nonvolatile E2PROM array which allows for easy trans­fer of data from RAM array to E2PROM (STORE) and
from E2PROM to RAM (RECALL). STORE operations
are completed in 10ms max. and RECALL operations
typically within 1.5µs. The CAT24C44 features unlimited
RAM write operations either through external RAM
writes or internal recalls from E2PROM. Internal false

■ JEDEC Standard Pinouts:

–8-pin DIP
–8-pin SOIC

■ 100,000 Program/Erase Cycles (E

■ Auto Recall on Power-up

■ Commercial, Industrial and Automotive

2

PROM)

Temperature Ranges

store protection circuitry prohibits STORE operations
when VCC is less than 3.5V (typical) ensuring E2PROM
data integrity.

The CAT24C44 is manufactured using Catalyst’s ad­vanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles (E2PROM) and
has a data retention of 10 years. The device is available
in JEDEC approved 8-pin plastic DIP and SOIC pack­ages.

PIN CONFIGURATION

DIP Package (P)

SK

1
2

DI

3
4

8
7
6
5

V

CC

STORE
RECALL
V

SS

CE

DO

© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

SOIC Package (S)

1

CE
SK

DI

DO

8

2

7

3

6

4

5

V

CC

STORE
RECALL
V

SS

5157 FHD F01

PIN FUNCTIONS

Pin Name Function

SK Serial Clock
DI Serial Input
DO Serial Data Output
CE Chip Enable

RECALL Recall
STORE Store

V

CC

V

SS

1

+5V
Ground

Doc. No. 25019-0A 2/98 N-1

CAT24C44

BLOCK DIAGRAM

CE

DI

SK

ROW

DECODE

INSTRUCTION

REGISTER

E2PROM ARRAY

STATIC RAM

ARRAY

256-BIT

COLUMN
DECODE

RECALL
STORE

CONTROL

LOGIC

STORE
RECALL

DO
V

CC

V

SS

MODE SELECTION

INSTRUCTION

DECODE

(1)(2)

4-BIT

COUNTER

Software Write Enable Previous Recall

Mode

Hardware Recall

(3)

STORESTORE

STORE

STORESTORE

1 0 NOP X X

RECALLRECALL

RECALL Instruction Latch Latch

RECALLRECALL

Software Recall 1 1 RCL X X
Hardware Store

(3)

0 1 NOP SET TRUE

Software Store 1 1 STO SET TRUE

X = Don’t Care

POWER-UP TIMING

(4)

Symbol Parameter Min. Max. Units

VCCSR VCC Slew Rate 0.5 0.005 V/m

t

pur

Power-Up to Read Operations 200 µs

5157 FHD F09

t

puw

Note:
(1) The store operation has priority over all the other operations.
(2) The store operation is inhibited when VCC is below ≈ 3.5V.
(3) NOP designates that the device is not currently executing an instruction.
(4) This parameter is tested initially and after a design or process change that affects the parameter.

Doc. No. 25019-0A 2/98 N-1

Power-Up to Write or Store Operation 5 ms

2

CAT24C44

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias ................. –55°C to +125°C

Storage Temperature....................... –65°C to +150°C

Voltage on Any Pin with

Respect to Ground

VCC with Respect to Ground ............... –2.0V to +7.0V

Package Power Dissipation

Capability (Ta = 25°C)................................... 1.0W

(2)

.............–2.0 to +VCC +2.0V

*COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica­tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor­mance and reliability.

Lead Soldering Temperature (10 secs)............ 300°C

Output Short Circuit Current

(3)

........................ 100 mA

RELIABILITY CHARACTERISTICS

Symbol Parameter Min. Max. Units Reference Test Method

(1)

N
T
V
I

LTH

END
DR
ZAP

(1)

(1)

(1)(4)

Endurance 100,000 Cycles/Byte MIL-STD-883, Test Method 1033
Data Retention 10 Years MIL-STD-883, Test Method 1008
ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
Latch-Up 100 mA JEDEC Standard 17

D.C. OPERATING CHARACTERISTICS

VCC = 5V ±10%, unless otherwise specified.

Limits

Symbol Parameter Min. Typ. Max. Unit Conditions

I

CCO

Current Consumption (Operating) 3 mA Inputs = 5.5V, TA = 0°C

All Outputs Unloaded

I

SB

I

LI

I

LO

V

IH

V

IL

V

OH

V

OL

Current Consumption (Standby) 30 µA CE = V

IL

Input Current 2 µA0 ≤ VIN ≤ 5.5V
Output Leakage Current 10 µA0 ≤ V
High Level Input Voltage 2 V

CC

V

OUT

≤ 5.5V

Low Level Input Voltage 0 0.8 V
High Level Output Voltage 2.4 V IOH = –2mA
Low Level Output Voltage 0.4 V IOL = 4.2mA

CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V

Symbol Parameter Max. Unit Conditions

(1)

C

I/O

(1)

C

IN

Input/Output Capacitance 10 pF V
Input Capacitance 6 pF V

I/O

IN

= 0V

= 0V

Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns.

Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.

3

Doc. No. 25019-0A 2/98 N-1