CTLST CAT24C643PA-30TE13, CAT24C643PA-28TE13, CAT24C643PA-25TE13, CAT24C643P-45TE13, CAT24C643P-42TE13 Datasheet

Advanced

CAT24C323(32K), CAT24C643 (64K)

Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer

FEATURES

■ Watchdog Timer Input (WDI)

■ Programmable Reset Threshold

■ 400 KHz I

2

C Bus Compatible

■ 2.7 to 6 Volt Operation

■ Low Power CMOS Technology

■ 32 - Byte Page Write Buffer

■ Built-in inadvertent write protection

— V

Lock Out

CC

DESCRIPTION

The CAT24C323/643 is a single chip solution to three
popular functions of EEPROM memory, precision reset
controller and watchdog timer. The 24C323(32K) and
24C643 (64K) feature a I2C Serial CMOS EEPROM
Catalyst advanced CMOS technology substantially re­duces device power requirements. The 24C323/643
features a 32-byte page and is available in 8-pin DIP or
8-pin SOIC packages.

PIN CONFIGURATION

24C323/643*

WDI

RESET

WP

V

SS

V

CC

RESET
SCL
SDA

■ Active High or Low Reset Outputs

— Precision Power Supply Voltage Monitoring
— 5V, 3.3V and 3V options

■ 1,000,000 Program/Erase Cycles

■ 100 Year Data Retention

■ 8-Pin DIP or 8-Pin SOIC

■ Commercial, Industrial and Automotive

Temperature Ranges

The reset function of the 24C323/643 protects the sys­tem during brown out and power up/down conditions.
During system failure the watchdog timer feature pro­tects the microcontroller with a reset signal. 24C323
features active low reset on pin 2 and active high reset
on pin 7. 24C323/643 features watchdog timer on the
WDI input pin (pin 1).

BLOCK DIAGRAM

EXTERNAL LOAD

D

OUT

ACK

V

CC

V

SS

WORD ADDRESS

BUFFERS

SENSE AMPS

SHIFT REGISTERS

COLUMN

DECODERS

*All products offered in P and J packages

PIN FUNCITONS

Pin Name Function

SDA Serial Data/Address
RESET/RESET Reset I/O
SCL Clock Input
Vcc Power Supply
V

SS

WDI Watchdog Timer Input
WP Write Protect

© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

Ground

SDA

WP

START/ST OP

LOGIC

XDEC

CONTROL

LOGIC

RESET Controller

High

WATCHDOG

Precision

Vcc Monitor

WDI RESET/RESET

1

E2PROM

DATA IN STORAGE

HIGH VOL T A GE/

TIMING CONTROL

STATE COUNTERS
SLAVE

ADDRESS
COMPARATORS

Doc. No. 25084-00 12/98

SCL

CAT24C323/643

Advanced

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias....................–55°C to +125°C

COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.

Storage Temperature........................ –65°C to +150°C

Voltage on Any Pin with

Respect to Ground

(1)

..............–2.0V to +V

CC

+ 2.0V

VCC with Respect to Ground..................–2.0V to +7.0V

These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica­tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor­mance and reliability.

Package Power Dissipation

Capability (Ta = 25°C)1.0W.................................1.0W

Lead Soldering Temperature (10 secs)...............300°C

Output Short Circuit Current

(2)

..........................100mA

RELIABILITY CHARACTERISTICS

Symbol Parameter Min. Max. Units Reference Test Method

(3)

N

END

(3)

T

DR

(3)

V

ZAP

(3)(4)

I

LTH

D.C. OPERATING CHARACTERISTICS

VCC = +2.7V to +6.0V, unless otherwise specified.

Endurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033
Data Retention 100 Years MIL-STD-883, Test Method 1008
ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
Latch-up 100 mA JEDEC Standard 17

Limits

Symbol Parameter Min. Typ. Max. Units Test Conditions

I

CC

Power Supply Current 3 mA f

= 100 KHz

SCL

Isb Standby Current 40 µA Vcc=3.3V

50 µA Vcc=5

ILI Input Leakage Current 2 µA VIN=GND or V
ILO Output Leakage Current 10 µA VIN=GND or V

V
V
V

IL

IH
OL

Input Low Voltage –1 VCC x 0.3 V
Input High Voltage VCC x 0.7 VCC + 0.5 V
Output Low Voltage (SDA) 0.4 V IOL = 3 mA, VCC = 3.0V

CC
CC

CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol Test Max. Units Conditions

(3)

C

I/O

(3)

C

IN

Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.

Input/Output Capacitance (SDA) 8 pF V
Input Capacitance (SCL) 6 pF V

I/O

IN

= 0V

= 0V

Doc. No. 25084-00 12/98

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Advanced

CAT24C323/643

A.C. CHARACTERISTICS

VCC=2.7V to 6.0V unless otherwise specified.
Output Load is 1 TTL Gate and 100pF

Read & Write Cycle Limits

Symbol Parameter VCC=2.7V - 6V VCC=4.5V - 5.5V

Min. Max. Min. Max. Units

F

SCL

(1)

T

I

t

AA

t

BUF

t

HD:STA

t

LOW

t

HIGH

t

SU:STA

t

HD:DAT

t

SU:DAT

(1)

t

R

(1)

t

F

t

SU:STO

t

DH

(1)

Clock Frequency 100 400 kHz
Noise Suppression Time 200 200 ns

Constant at SCL, SDA Inputs
SCL Low to SDA Data Out 3.5 1 µs

and ACK Out
Time the Bus Must be Free Before 4.7 1.2 µs

a New Transmission Can Start
Start Condition Hold Time 4 0.6 µs
Clock Low Period 4.7 1.2 µs
Clock High Period 4 0.6 µs
Start Condition Setup Time 4.7 0.6 µs

(for a Repeated Start Condition)
Data In Hold Time 0 0 ns
Data In Setup Time 50 50 ns
SDA and SCL Rise Time 1 0.3 µs
SDA and SCL Fall Time 300 300 ns
Stop Condition Setup Time 4 0.6 µs
Data Out Hold Time 100 100 ns

Power-Up Timing

(1)(2)

Symbol Parameter Max. Units

t

PUR

t

PUW

Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t

PUR

and t

are the delays required from the time VCC is stable until the specified operation can be initiated.

PUW

Power-up to Read Operation 1 ms
Power-up to Write Operation 1 ms

Write Cycle Limits

Symbol Parameter Min. Typ. Max Units

t

WR

Write Cycle Time 10 ms

The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase
cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device
does not respond to its slave address.

3

Doc. No. 25084-00 12/98

CAT24C323/643

RESET CIRCUIT CHARACTERISTICS

Symbol Parameter Min. Max. Units

Advanced

t

GLITCH

V

RT

V

OLRS

V

OHRS

Glitch Reject Pulse Width 100 ns
Reset Threshold Hystersis 15 mV
Reset Output Low Voltage (I

=1mA) 0.4 V

OLRS

Reset Output High Voltage Vcc-0.75 V
Reset Threshold (Vcc=5V) 4.50 4.75

(24CXXX-45)
Reset Threshold (Vcc=5V) 4.25 4.50

(24CXXX-42)

V

TH

Reset Threshold (Vcc=3.3V) 3.00 3.15
(24CXXX-30)

Reset Threshold (Vcc=3.3V) 2.85 3.00
(24CXXX-28)

Reset Threshold (Vcc=3V) 2.55 2.70
(24CXXX-25)

t

PURST Power-Up Reset Timeout 130 270 ms

t

RPD V

V

RVALID

to RESET Output Delay 5 µs

TH

RESET Output Valid 1 V

V

Doc. No. 25084-00 12/98

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