CTLST CAT24C643PA-30TE13, CAT24C643PA-28TE13, CAT24C643PA-25TE13, CAT24C643P-45TE13, CAT24C643P-42TE13 Datasheet

Advanced

CAT24C323(32K), CAT24C643 (64K)

Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer

FEATURES

■ Watchdog Timer Input (WDI)

■ Programmable Reset Threshold

■ 400 KHz I

2

C Bus Compatible

■ 2.7 to 6 Volt Operation

■ Low Power CMOS Technology

■ 32 - Byte Page Write Buffer

■ Built-in inadvertent write protection

— V

Lock Out

CC

DESCRIPTION

The CAT24C323/643 is a single chip solution to three
popular functions of EEPROM memory, precision reset
controller and watchdog timer. The 24C323(32K) and
24C643 (64K) feature a I2C Serial CMOS EEPROM
Catalyst advanced CMOS technology substantially re­duces device power requirements. The 24C323/643
features a 32-byte page and is available in 8-pin DIP or
8-pin SOIC packages.

PIN CONFIGURATION

24C323/643*

WDI

RESET

WP

V

SS

V

CC

RESET
SCL
SDA

■ Active High or Low Reset Outputs

— Precision Power Supply Voltage Monitoring
— 5V, 3.3V and 3V options

■ 1,000,000 Program/Erase Cycles

■ 100 Year Data Retention

■ 8-Pin DIP or 8-Pin SOIC

■ Commercial, Industrial and Automotive

Temperature Ranges

The reset function of the 24C323/643 protects the sys­tem during brown out and power up/down conditions.
During system failure the watchdog timer feature pro­tects the microcontroller with a reset signal. 24C323
features active low reset on pin 2 and active high reset
on pin 7. 24C323/643 features watchdog timer on the
WDI input pin (pin 1).

BLOCK DIAGRAM

EXTERNAL LOAD

D

OUT

ACK

V

CC

V

SS

WORD ADDRESS

BUFFERS

SENSE AMPS

SHIFT REGISTERS

COLUMN

DECODERS

*All products offered in P and J packages

PIN FUNCITONS

Pin Name Function

SDA Serial Data/Address
RESET/RESET Reset I/O
SCL Clock Input
Vcc Power Supply
V

SS

WDI Watchdog Timer Input
WP Write Protect

© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

Ground

SDA

WP

START/ST OP

LOGIC

XDEC

CONTROL

LOGIC

RESET Controller

High

WATCHDOG

Precision

Vcc Monitor

WDI RESET/RESET

1

E2PROM

DATA IN STORAGE

HIGH VOL T A GE/

TIMING CONTROL

STATE COUNTERS
SLAVE

ADDRESS
COMPARATORS

Doc. No. 25084-00 12/98

SCL

CAT24C323/643

Advanced

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias....................–55°C to +125°C

COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.

Storage Temperature........................ –65°C to +150°C

Voltage on Any Pin with

Respect to Ground

(1)

..............–2.0V to +V

CC

+ 2.0V

VCC with Respect to Ground..................–2.0V to +7.0V

These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica­tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor­mance and reliability.

Package Power Dissipation

Capability (Ta = 25°C)1.0W.................................1.0W

Lead Soldering Temperature (10 secs)...............300°C

Output Short Circuit Current

(2)

..........................100mA

RELIABILITY CHARACTERISTICS

Symbol Parameter Min. Max. Units Reference Test Method

(3)

N

END

(3)

T

DR

(3)

V

ZAP

(3)(4)

I

LTH

D.C. OPERATING CHARACTERISTICS

VCC = +2.7V to +6.0V, unless otherwise specified.

Endurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033
Data Retention 100 Years MIL-STD-883, Test Method 1008
ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
Latch-up 100 mA JEDEC Standard 17

Limits

Symbol Parameter Min. Typ. Max. Units Test Conditions

I

CC

Power Supply Current 3 mA f

= 100 KHz

SCL

Isb Standby Current 40 µA Vcc=3.3V

50 µA Vcc=5

ILI Input Leakage Current 2 µA VIN=GND or V
ILO Output Leakage Current 10 µA VIN=GND or V

V
V
V

IL

IH
OL

Input Low Voltage –1 VCC x 0.3 V
Input High Voltage VCC x 0.7 VCC + 0.5 V
Output Low Voltage (SDA) 0.4 V IOL = 3 mA, VCC = 3.0V

CC
CC

CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol Test Max. Units Conditions

(3)

C

I/O

(3)

C

IN

Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.

Input/Output Capacitance (SDA) 8 pF V
Input Capacitance (SCL) 6 pF V

I/O

IN

= 0V

= 0V

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2

Advanced

CAT24C323/643

A.C. CHARACTERISTICS

VCC=2.7V to 6.0V unless otherwise specified.
Output Load is 1 TTL Gate and 100pF

Read & Write Cycle Limits

Symbol Parameter VCC=2.7V - 6V VCC=4.5V - 5.5V

Min. Max. Min. Max. Units

F

SCL

(1)

T

I

t

AA

t

BUF

t

HD:STA

t

LOW

t

HIGH

t

SU:STA

t

HD:DAT

t

SU:DAT

(1)

t

R

(1)

t

F

t

SU:STO

t

DH

(1)

Clock Frequency 100 400 kHz
Noise Suppression Time 200 200 ns

Constant at SCL, SDA Inputs
SCL Low to SDA Data Out 3.5 1 µs

and ACK Out
Time the Bus Must be Free Before 4.7 1.2 µs

a New Transmission Can Start
Start Condition Hold Time 4 0.6 µs
Clock Low Period 4.7 1.2 µs
Clock High Period 4 0.6 µs
Start Condition Setup Time 4.7 0.6 µs

(for a Repeated Start Condition)
Data In Hold Time 0 0 ns
Data In Setup Time 50 50 ns
SDA and SCL Rise Time 1 0.3 µs
SDA and SCL Fall Time 300 300 ns
Stop Condition Setup Time 4 0.6 µs
Data Out Hold Time 100 100 ns

Power-Up Timing

(1)(2)

Symbol Parameter Max. Units

t

PUR

t

PUW

Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t

PUR

and t

are the delays required from the time VCC is stable until the specified operation can be initiated.

PUW

Power-up to Read Operation 1 ms
Power-up to Write Operation 1 ms

Write Cycle Limits

Symbol Parameter Min. Typ. Max Units

t

WR

Write Cycle Time 10 ms

The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase
cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device
does not respond to its slave address.

3

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CAT24C323/643

RESET CIRCUIT CHARACTERISTICS

Symbol Parameter Min. Max. Units

Advanced

t

GLITCH

V

RT

V

OLRS

V

OHRS

Glitch Reject Pulse Width 100 ns
Reset Threshold Hystersis 15 mV
Reset Output Low Voltage (I

=1mA) 0.4 V

OLRS

Reset Output High Voltage Vcc-0.75 V
Reset Threshold (Vcc=5V) 4.50 4.75

(24CXXX-45)
Reset Threshold (Vcc=5V) 4.25 4.50

(24CXXX-42)

V

TH

Reset Threshold (Vcc=3.3V) 3.00 3.15
(24CXXX-30)

Reset Threshold (Vcc=3.3V) 2.85 3.00
(24CXXX-28)

Reset Threshold (Vcc=3V) 2.55 2.70
(24CXXX-25)

t

PURST Power-Up Reset Timeout 130 270 ms

t

RPD V

V

RVALID

to RESET Output Delay 5 µs

TH

RESET Output Valid 1 V

V

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4

Advanced

CAT24C323/643

PIN DESCRIPTIONS

WDI: WATCHDOG INPUT

If there is no transition on the WDI for more than 1.6
seconds, the watchdog timer times out.

WP: WRITE PROTECT
If the pin is tied to VCC the entire memory array becomes
Write Protected (READ only). When the pin is tied to V
or left floating normal read/write operations are allowed
to the device.

SCL: SERIAL CLOCK
The serial clock input clocks all data transferred into or
out of the device.

RESET/

RESETRESET

RESET: RESET I/O

RESETRESET

These are open drain pins and can be used as reset
trigger inputs. By forcing a reset condition on the pins the
device will initiate and maintain a reset condition for
approximately 200ms. RESET pin must be connected
through a pull-down and RESET pin must be connected
through a pull-up device.

SDA: SERIAL DATA/ADDRESS
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs.

DEVICE OPERATION

Reset Controller Description

The CAT24CXXX provides a precision RESET control­ler that ensures correct system operation during brown­out and power up/down conditions. It is configured

SS

with open drain RESET outputs. During power-up, the
RESET outputs remain active until VCC reaches the
V

threshold and will continue driving the outputs for

TH

approximately 200ms (t
the t

timeout interval, the device will cease to drive

PURST

) after reaching V

PURST

TH.

After

reset outputs. At this point the reset outputs will be pulled
up or down by their respective pull up/pull down devices.
During power-down, the RESET outputs will begin driv­ing active when VCC falls below V
outputs will be valid so long as VCC is >1.0V (V

The RESET

TH.

RVALID

The RESET pins are I/Os; therefore, the CAT24CXXX
can act as a signal conditioning circuit for an externally
applied reset. The inputs are level triggered; that is, the
RESET input in the 24CXXX will initiate a reset timeout
after detecting a high and the RESET input in the
24CXXX will initiate a reset timeout after detecting a low.

Watchdog Timer

The Watchdog Timer provides an independent protec­tion for microcontrollers. During a system failure, the
CAT24CXXX will respond with a reset signal after a
time-out interval of 1.6 seconds for a lack of activity. The
24C323/643 is designed with a WDI input pin for the
Watchdog Timer function. For the 24C323/643, if the
microcontroller does not toggle the WDI input pin within

1.6 seconds, the Watchdog Timer times out. This will
generate a reset condition on reset outputs. The Watch­dog Timer is cleared by any transition on WDI.

As long as the reset signal is asserted, the Watchdog
Timer will not count and will stay cleared.

).

Figure 1. RESET Output Timing

V

TH

V

RVALID

V

CC

RESET

RESET

t

PURST

t

GLITCH

5

t

RPD

t

PURST

t

RPD

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CAT24C323/643

Advanced

Hardware Data Protection

The 24CXXX is designed with the following hardware
data protection features to provide a high degree of data
integrity.

(1) The 24CXXX features a WP pin. When WP pin is tied
high the entire memory array becomes write protected
(read only).

(2) The VCC sense provides write protection when V
falls below the reset threshold value (VTH). The VCC lock
out inhibits writes to the serial EEPROM whenever V
falls below (power down) VTH or until VCC reaches the
reset threshold (power up) VTH.

Figure 2. Bus Timing

t

F

t

LOW

SCL

t

SU:STA

SDA IN

SDA OUT

t

HD:STA

t

AA

t

HIGH

t

HD:DAT

CC

CC

Reset Threshold Voltage

From the factory the 24CXXX is offered in five different
variations of reset threshold voltages. They are 4.50-

4.75V, 4.25-4.50V, 3.00-3.15V, 2.85-3.00V and 2.55-

2.70V. To provide added flexibility to design engineers
using this product, the 24CXXX is designed with an
additional feature of programming the reset threshold
voltage. This allows the user to change the existing
reset threshold voltage to one of the other four reset
threshold voltages. Once the reset threshold voltage is
selected it will not change even after cycling the power,
unless the user uses the programmer to change the
reset threshold voltage. However, the programming
function is available only through third party programmer
manufacturers. Please call Catalyst for a list of program­mer manufacturers who support this function.

t

R

t

LOW

t

SU:DAT

t

DH

t

SU:STO

t

BUF

Figure 3. Write Cycle Timing

SCL

SDA

BYTE n

Figure 4. Start/Stop Timing

SDA

SCL

ACK8TH BIT

START BIT

STOP
CONDITION

t

WR

START
CONDITION

STOP BIT

ADDRESS

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6

Advanced

CAT24C323/643

FUNCTIONAL DESCRIPTION

The CAT24CXXX supports the I2C Bus data transmis­sion protocol. This Inter-Integrated Circuit Bus protocol
defines any device that sends data to the bus to be a
transmitter and any device receiving data to be a re­ceiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24CXXX
operates as a Slave device. Both the Master device and
Slave device can operate as either transmitter or re­ceiver, but the Master device controls which mode is
activated.

I2C BUS PROTOCOL

The features of the I2C bus protocol are defined as
follows:

(1) Data transfer may be initiated only when the bus is
not busy.

(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes in
the data line while the clock line is high will be interpreted
as a START or STOP condition.

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.

DEVICE ADDRESSING

The Master begins a transmission by sending a START
condition. The Master sends the address of the particu­lar slave device it is requesting. The four most significant
bits of the 8-bit slave address are fixed as 1010.
The next three bits are don’t care. The last bit of the slave
address specifies whether a Read or Write operation is
to be performed. When this bit is set to 1, a Read
operation is selected, and when set to 0, a Write opera­tion is selected.

After the Master sends a START condition and the slave
address byte, the CAT24CXXX monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24CXXX then performs a Read or Write operation
depending on the state of the R/W bit.

START Condition

The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24CXXX monitors the
SDA and SCL lines and will not respond until this
condition is met.

Figure 5. Acknowledge Timing

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

Figure 6. Slave Address Bits

START

1

89

ACKNOWLEDGE

101 0XXXRW

7

Doc. No. 25084-00 12/98

CAT24C323/643

ACKNOWLEDGE

Advanced

After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledg­ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.

The CAT24CXXX responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8­bit byte.

When the CAT24CXXX begins a READ mode it trans­mits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this ac­knowledge, the CAT24CXXX will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.

WRITE OPERATIONS

Byte Write

In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
t he Slave generates an acknowledge, the Master sends
a 8-bit address that is to be written into the address
pointers of the CAT24CXXX. After receiving another
acknowledge from the Slave, the Master device trans­mits the data to be written into the addressed memory

location. The CAT24CXXX acknowledges once more
and the Master generates the STOP condition. At this
time, the device begins an internal programming cycle to
nonvolatile memory. While the cycle is in progress, the
device will not respond to any request from the Master
device.

Page Write

The 24CXXX writes up to 32 bytes of data in a single
write cycle, using the Page Write operation. The page
write operation is initiated in the same manner as the
byte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
to send up to 31 additional bytes. After each byte has
been transmitted, CAT24CXXX will respond with an
acknowledge, and internally increment the lower order
address bits by one. The high order bits remain un­changed.

If the Master transmits more than 32 bytes before
sending the STOP condition, the address counter ‘wraps
around’, and previously transmitted data will be overwrit­ten.

When all 32 bytes are received, and the STOP condi
tion has been sent by the Master, the internal program­ming cycle begins. At this point, all received data is
written to the CAT24CXXX in a single write cycle.

Figure 7. Byte Write Timing

S
T

BUS ACTIVITY :

MASTER

SDA LINE

A
R
T

S

Figure 8. Page Write Timing

S
T
A

BUS ACTIVITY:

MASTER

SDA LINE

* = Don't care bit for 24C323
X= Don't care bit

R
T

S

SLAVE

ADDRESS

SLAVE

ADDRESS

A15–A

XXX

A

C

K

A
C
K

BYTE ADDRESS

8

*

S

BYTE ADDRESS

A15–A

8

XXX

*

A7–A

0

A
C
K

A7–A

0

A

C

K

A

C

K

A
C
K

DATA

A
C
K

DATA

T

O

P

P

A
C
K

S
T

DATA n+31DAT

A

A

C

C

K

K

O
P

P

A
C
K

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8

Advanced

Acknowledge Polling

CAT24C323/643

Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host’s write operation,
CAT24CXXX initiates the internal write cycle. ACK poll­ing can be initiated immediately. This involves issuing
the start condition followed by the slave address for a
write operation. If CAT24CXXX is still busy with the write
operation, no ACK will be returned. If
CAT24CXXX has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.

WRITE PROTECTION

The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to VCC, the entire memory array is

Figure 9. Immediate Address Read Timing

protected and becomes read only. The CAT24CXXX
will accept both slave and byte addresses, but the
memory location accessed is protected from program­ming by the device's failure to send an acknowledge
after the first byte of data is received.

READ OPERATIONS

The READ operation for the CAT24CXXX is initiated in
the same manner as the write operation with one excep­tion, that R/W bit is set to one. Three different READ
operations are possible: Immediate/Current Address
READ, Selective/Random READ and Sequential READ.

S
T

BUS ACTIVITY:

MASTER

SDA LINE

SCL

SDA 8TH BIT

A
R
T

S

89

SLAVE

ADDRESS

S
T
O
P

P

A

C

K

DATA

N
O

A
C
K

STOPNO ACKDATA OUT

24C1601Fig.8

9

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CAT24C323/643

Immediate/Current Address Read

Advanced

The CAT24CXXX’s address counter contains the ad­dress of the last byte accessed, incremented by one. In
other words, if the last READ or WRITE access was to
address N, the READ immediately following would ac­cess data from address N+1. If N=E (where E=4095 for
24C323 and E=8191 for 24C643),then the counter will
‘wrap around’ to address 0 and continue to clock out
data. After the CAT24CXXX receives its slave address
information (with the R/W bit set to one), it issues an
acknowledge, then transmits the 8-bit byte requested.
The master device does not send an acknowledge, but
will generate a STOP condition.

Selective/Random Read

Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’ write operation by sending the START condi­tion, slave address and byte addresses of the location it
wishes to read. After CAT24CXXX acknowledges, the
Master device sends the START condition and the slave
address again, this time with the R/W bit set to one.
The CAT24CXXX then responds with its acknowledge
and sends the 8-bit byte requested. The master device

does not send an acknowledge but will generate a STOP
condition.

Sequential Read

The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24CXXX sends the initial 8-bit
byte requested, the Master will respond with an ac
knowledge which tells the device it requires more data.
The CAT24CXXX will continue to output an 8-bit byte for
each acknowledge sent by the Master. The operation
will terminate when the Master fails to respond with an
acknowledge, thus sending the STOP condition.

The data being transmitted from CAT24CXXX is output­ted sequentially with data from address N followed by
data from address N+1. The READ operation address
counter increments all of the CAT24CXXX address bits
so that the entire memory array can be read during one
operation. If more than E (where E= 4095 for 24C323
and E=8191 for 24C643) bytes are read out, the counter
will ‘wrap around’ and continue to clock out data bytes.

Figure 10. Selective Read Timing

S
T
A

BUS ACTIVITY :

MASTER

SDA LINE

R
T

S

SLAVE

ADDRESS

A
C
K

Figure 11. Sequential Read Timing

BUS ACTIVITY :

MASTER

SDA LINE

* = Don't care bit for 24WC32
X= Don't care bit

SLAVE

ADDRESS

A
C
K

A15–A

XXX*

A
C
K

S
T

BYTE ADDRESS SLAVE

8

DATA n+1

A7–A

0

A
C
K

A
C
K

A
R
T

S

A
C
K

DATA n+2

ADDRESS

A
C
K

S
T

DATA

A
C
K

DATA n+xDATA n

O
P

P

N
O
A
C
K

S
T
O
P

P

N
O

A
C
K

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10

Advanced

Ordering Information

Prefix Device # Suffix

CAT24C323/643

CAT

Optional
Company ID

24C323

Product
Number

24C323: 32K
24C643: 64K

J

I TE13

Temperature Range

Blank = Commercial (0˚ to 70˚C)
I = Industrial (-40˚ to 85˚C)
A = Automotive (-40˚to +105˚C)

Package

P: PDIP
J: SOIC (JEDEC)

Reset Threshold
V oltage

45: 4.5-4.75V
42: 4.25-4.5V

-30

Tape & Reel

TE13: 2000/Reel

30: 3.0-3.15V
28: 2.85-3.0V

* -40˚ to +125˚C is available upon request

Note:
(1) The device used in the above example is a CAT24C323JI-30TE13 (32Doc. No. -00 12/98K I2C Memory, SOIC, Industrial Temperature, 3.0-

3.15V Reset Threshold Voltage, Tape and Reel)

25: 2.55-2.7V

11

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CAT24C323/643

Advanced

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12