This document is designed to allow printing as an 8 ½ x 11-inch hardcopy that will fit into a standard 3-ring
binder. Provided below is a title block that can be copied and/or cut out and placed into a slip or taped onto
the edge of the binder.
Deskpro EXS and Deskpro W orkstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
and the Intel 850 Chipset
TRG
Reader Feedback
Please feel free to send any quest i ons, suggestions, co rrections, o r comments regarding this
document please to the following email address:
CPCG.Training@compaq.com
When responding, please state the title and edition of the referenced document.
Technical Reference Guide
NOTICE
The information in this document is subject to change without notice.
COMPAQ COMPUTER CORPORATION SHALL NOT BE LIABLE FOR TECHNICAL OR
EDITORIAL ERRORS OR OMISSIONS HEREIN; NOR FOR INCIDENTAL OR
CONSEQUENTIAL DAMAGES RESULTING FROM THE FURNISHING, PERFORMANCE,
OR USE OF THIS MATERIAL. IT IS THE RESPONSIBILITY OF MANUFACTURERS TO
ENSURE THAT DEVICES DESIGNED TO BE USED WITH COMPAQ PRODUCTS
COMPLY WITH FCC CLASS B EMISSIONS REQUIREMENTS.
This guide contains information protected by copyright. Except for use in connection with the
described Compaq product, no part of this document may be photocopied or reproduced in any
form without prior written consent from Compaq Computer Corporation.
2000 Compaq Computer Corporation
All rights reserved. Published in the USA
Compaq, Deskpro, LTE, Contura, Presario, ProLinea
Registered U.S. Patent and Trademark Office
Product names mentioned in this document may be trademarks and/or registered trademarks of other companies.
“Microsoft ,” “MS-DOS,” “Windows,” and “Windows NT” a r e registered trademarks of Microsoft Cor poration.
“Celeron,” “Pentium” and “MMX” are registered t rademarks of Intel Corporation.
For more information regarding specifications and Compaq-specific parts please contact Compaq
Computer Corporation.
Technical Reference Guide
Compaq Deskpro EXS and Workstation 300 Series Personal Computers
First Edition - December 2000
Document Number 13YR-1200A-WWEN
for
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
i
Technical Reference Guide
ii
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
xiii
Technical Reference Guide
T
5–19. USB C
ABLE
T
5–20. USB C
ABLE
T
5–21. AC’97 A
ABLE
T
5–22. AC’97 A
ABLE
T
5–23. A
ABLE
T
5–24. AOL E
ABLE
T
5–25. R
ABLE
T
7-1. B
ABLE
T
ABLE
T
ABLE
T
ABLE
T
ABLE
T
ABLE
T
ABLE
T
ABLE
T
ABLE
T
ABLE
T
ABLE
T
ABLE
T
ABLE
T
ABLE
T
ABLE
T
ABLE
T
ABLE
T
ABLE
T
ABLE
T
ABLE
T
ABLE
T
ABLE
T
ABLE
T
ABLE
T
ABLE
OOT BLOCK CODES
7-2. B
OOT ERROR CODES
7-3. S
7-4. C
7-5. PNP BIOS F
7-6. APM BIOS F
A–1. B
A–2. P
A–3. S
A–4. M
A–5. K
A–6. P
A–7. V
A–8. D
A–9. S
A–10. S
A–11. S
A–12. H
A–13. H
A–14. V
A–15. A
A–16. DVD/CD-ROM D
A–17. N
A–18. SCSI I
A–19. P
ONNECTOR PINOUT
ABLE LENGTH DATA
UDIO CONTROLLER
UDIO CODEC CONTROL REGISTERS
UDIO SUBSYSTEM SPECIFICATIONS
VENTS
EMOTE SYSTEM ALERT EVENTS
ETUP UTILITY FUNCTIONS
LIENT MANAGEMENT FUNCTIONS
UNCTIONS
UNCTIONS
EEP/KEYBOARD
OWER-ON SELF TEST
YSTEM ERROR MESSAGES
EMORY ERROR MESSAGES
EYBOARD ERROR MESSAGES
RINTER ERROR MESSAGES
IDEO (GRAPHICS
ISKETTE DRIVE ERROR MESSAGES
ERIAL INTERFACE ERROR MESSAGES
ERIAL INTERFACE ERROR MESSAGES
YSTEM STATUS ERROR MESSAGES
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
xv
Technical Reference Guide
This page is intentionally blank.
xvi
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition –- December 2000
Chapter 1
INTRODUCTION
Technical Reference Guide
1.
Chapter 1 INTRODUCTION
1.1 ABOUT THIS GUIDE
This guide provides technical information about Compaq Deskpro Personal Computers that feature
the Intel Pentium 4 processor and the Intel 850 chipset. This document includes information
regarding system design, function, and features that can be use d by programmers, engineers,
technicians, and system administrators.
This guide and any applicable addendums are available online at the following location:
The chapters of this guide primarily describe the hardware and firmware elements and primarily
deal with the system board and the power supply assembly. The appendices contain general
information about standard peripheral devices such as the keyboard.
1.1.2 ADDITIONAL INFORMATION S O URCES
For more information on chipset components mentioned in this guide refer to the indicated
manufacturers’ documentation, which may be available at the following online sources:
♦ Compaq Computer Corpo ration: http://www.compaq.com
♦ Intel Corporation: http://www.intel.com
♦ Standard Microsystems Corporation: http://www.smsc.com
1.2 MODEL NUMBERING CONVENTION
The model numbering convention for Compaq Deskpro units is as follows:
XXX/XNNN/NNX/N/NNNxxx
NIC/Modem: blank = none, n = NIC, m = modem
Graphics: blank = integrated, a = AIMM, v = nVIDIA
Removable storage: b = CD/CDRW, c = CD, d = DVD, r = CDRW, z = ZIP
Memory (in MB)
OS type (9 = Dual install Win95/98, 4 = Win NT 4.0, 6 = Dual install Win NT/2000)
Chipset type (e = 850)
Hard drive size (in GB)
Processor speed (in MHz)
Processor type: C = Celeron; P = Pentium
Form factor: D = Desktop, M = Minitower
Deskpro series: EX = EXS, WK = Workstation
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
1-1
First Edition – December 2000
Chapter 1 Introduction
1.3 NOTATIONAL CONVENTIONS
1.3.1 VALUES
Hexadecimal values are indicated by a numerical or alpha-numerical value followed by the letter
“h.” Binary values are indicated by a value of ones and zeros followed by the letter “b.”
Numerical values that have no succeeding letter can be assumed to be decimal.
1.3.2 RANGES
Ranges or limits for a parameter are shown using the following methods:
Example A:Bits <7..4> = bits 7, 6, 5, and 4.
Example B:IRQ3-7, 9 = IRQ signals 3 thro ugh 7, and IRQ signal 9
1.3.3 SIGNAL LABELS
Signal names are indicated using abbreviations, acronyms, or, if possible, the full signal name in
all capital letters. Signals that are meant to be active (asserted) low are indicated with a dash
immediately following the name.
1.3.4 REGISTER NOTATION AND USAGE
This guide uses sta ndard Intel naming co nventions in discussing the microprocessor ’s (CPU)
internal registers. Registers that are accessed through programmable I/O using an indexing scheme
are indicated using the following format:
03C5.17h
Index port
Data port
In the example above, register 03C5.17h is accessed by writing the index port value 17h to the
index address (03C4h), followed by a write to or a read from port 03C5h.
1.3.5 BIT NOTATION
Bit values are labeled with bit <0> representing the least-significant bit (LSb) and bit <7>
representing the most-significant bit (MSb) of a byte. Bytes, words, double words, and quad words
are typically shown with most-significant portions on the left or top and the least-significant
portions on the right or bottom respectively.
1-2
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition – December 2000
1.4 COMMON ACRONYMS AND ABBREVIATIONS
Table 1-1 lists the acronyms and abbreviations used in this guide.
Table 1–1. Acronyms and Abbreviations
Table 1-1.
Acronyms and Abbreviations
Acronym/AbbreviationDescription
Aampere
ACalternating current
ACPIAdvanced Configuration and Power Interfac e
A/Danalog-to-digital
AGPAccelerated graphics port
APIapplicat i on programming interface
APICAdvanced Programmable I n t errupt Controller
APMadvanced power management
AOLAlert-On-LAN™
ASICapplication-specific integrated circuit
AT1) attention (modem commands) 2) 286-based PC arc hi tecture
ATAAT attachment (IDE protocol)
ATAPIAT attachment w/packet interface extensions
AVIaudio-video int erl eaved
AVGAAdvanced VGA
AWGAmerican Wire Gauge (specifi cation)
BATBasic assurance test
BCDbinary-coded decimal
BIOSbasic input/output system
bissecond/new revision
BNCBayonet Neill-Concelman (connector t ype)
bps or b/sbits per second
BSPBootstrap processor
BTOBuilt to order
CAScolumn address strobe
CDcompact disk
CD-ROMcompact disk read-onl y memory
CDScompact disk system
CGAcolor graphics adapter
ChChannel, chapter
cmcentimeter
CMCcache/memory controller
CMOScomplimentary metal-oxide semiconduct o r (configuration memory)
Cntlrcontroller
Cntrlcontrol
codeccompressor/decompressor
CPQCompaq
CPUcentral processing unit
CRIMMContinuity (blank) RIMM
CRTcathode ray tube
CSMCompaq system management / Compaq server management
DACdigital-to-analog converter
DCdirect current
DCHDOS compatibility hole
DDCDisplay Data Channel
DFdirect i on flag
Technical Reference Guide
Continued
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition – December 2000
1-3
Chapter 1 Introduction
Table 1-1. Acronyms and Abbreviations Continued
Acronym/AbbreviationDescription
DIMMdual inline memory module
DINDeutche IndustriNorm (connector standard)
DIPdual inline package
DMAdirect memory access
DMIDesktop management i nterface
dpidots per i nch
DRAMdynami c random access memory
DRQdata request
EDIDextended display identification data
EDOextended data out (RAM type)
EEPROMelect ri cally eraseable PROM
EGAenhanced graphics adapter
EIAElec tronic Industry Ass ociation
EISAextended ISA
EPPenhanced parallel port
EIDEenhanced IDE
ESCDExtended System Configuration Data (format)
EVEnvironmental Variable (data)
ExCAExchangeable Card Architecture
FIFOfirst in / first out
FLflag (register)
FMfrequency modulation
FPMfast page mode (RAM type)
FPUFloating point unit (numeric or math coprocessor)
FPSFrames per second
ftFoot/feet
GBgigabyte
GMCHGraphics/memory controller hub
GNDground
GPIOgeneral purpose I/ O
GPOCgeneral purpose open-coll ector
GARTGraphics address re-mapping t abl e
GUIgraphics user interface
hhexadecimal
HWhardware
hexhexadecimal
HzHertz (cycles-per-second)
ICHI/O controller hub
IDEintegrated drive element
IEEEInst i t ute of Electrical and El ectronic Engineers
IFinterrupt flag
I/Finterface
ininch
INTinterrupt
I/Oinput/output
IPLinitial program loader
IrDAInfraRed Data Assoc i ation
IRQinterrupt request
ISAindust ry standard architecture
Kb / KBkilobits / kilobytes (x 1024 bits / x 1024 bytes)
Kb/skilobits per second
kgkilogram
KHzkilohertz
kvkilovolt
Continued
1-4
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition – December 2000
Technical Reference Guide
Table 1-1. Acronyms and Abbreviations Continued
Acronym/AbbreviationDescription
lbpound
LANlocal area net work
LCDliquid crystal displ a y
LEDlight-emitting diode
LIFlow insertion force (socket)
LPCLow pin count
LSIlarge scale integration
LSb / LSBleast significant bi t / least signific ant byte
LUNlogical unit (SCSI)
mMeter
MCHMemory controller hub
MMXmultimedia extensions
MPEGMotion Pic ture Experts Group
msmillisecond
MSb / MSBmost significant bit / most significant byte
muxmultiplex
MVAmot i on vi deo acceleration
MVWmotion video window
n
NICnetwork interface card/controller
NiMHnickel-metal hydride
NMInon-maskable interrupt
NRZINon-return-to-zero inverted
nsnanosecond
NTnested task flag
NTSCNational Televi sion Standards Commi t tee
NVRAMnon-volatile random access memory
OSoperating system
PAL1. programmable array logic 2. phase altering line
PCInternet Device
PCAPrinted circuit assembl y
PCIperipheral component interconnect
PCMpulse code modulation
PCMCIAInternet Device Memory Card International Associat i on
PFparity flag
PINpersonal identification number
PIOProgrammed I/O
POSTpower-on self tes t
PROMprogrammable read-only memory
PTRpointer
RAMrandom access memory
RASrow address st robe
rcvrreceiver
RDRAM(Direct) Rambus DRAM
RFresume flag
RGBred/green/blue (monitor input)
RHRelative humidity
RIMMRDRAM inline memory module
RMSroot mean square
ROMread-only memory
RPMrevolutions per minute
RTCreal time clock
variable parameter/value
Continued
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition – December 2000
1-5
Chapter 1 Introduction
Table 1-1. Acronyms and Abbreviations Continued
Acronym/AbbreviationDescription
R/WRead/Write
SCSIsmall comput er system interface
SDRAMSynchronous Dynamic RA M
SECSingle E dge-Connector
SECAMsequential colour avec memoire (sequential color with memory)
SFsign flag
SGRAMSynchronous Graphics RAM
SIMDSingle instruction multipl e data
SIMMsingle i n-l i ne memory module
SITsystem information table
SMARTSelf Monitor Analysis Report Technology
SMIsystem management interrupt
SMMsystem management mode
SMRAMsystem management RAM
SPDserial presence detect
SPDIFSony/Philips Digit al I nt erface (IEC-958 specification)
SPNSpare part number
SPPstandard parallel port
SRAMstatic RAM
SSEStreaming SIMD extensions
STNsuper twist pneumatic
SVGAsuper VGA
SWsoftware
TADtelephone answering device
TAFITemperature-s ensing And Fan control Integrated ci rc ui t
TAMtelephone answering machine
TCPtape carrier package
TFtrap flag
TFTthin-film transistor
TIATelecommunications Inform at i on Administration
TPEtwisted pair ethernet
TPItrack per inch
TTLtransist or-t ransistor logic
TVtelevision
TXtransmit
UARTuniversal asynchronous receiver/transmitter
UDMAUltra DMA
URLUniform resource loc ator
us / µs
USBUniversal Serial Bus
UTPunshielded twisted pair
Vvolt
VESAVideo Electronic Standards Association
VGAvideo graphics adapter
vibvibrato
VLSIvery large scale integration
VRAMVideo RAM
Wwatt
WOLWake-On-LAN
WRAMWindows RAM
ZFzero flag
ZIFzero insertion force (socket )
microsecond
1-6
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition – December 2000
Chapter 2
SYSTEM OVERVIEW
2.Chapter 2 SYSTEM OVERVIEW
2.1 INTRODUCTION
Compaq Deskpro Personal Computers (Figure 2-1) featuring the Intel Pentium 4 processor provide
very high performance for advanced e-business and multimedia applications. This guide covers
Compaq Deskpro EXS Minitower and the Compaq Deskpro Workstation 300 models that feature
the Intel Pentium 4 processor and the Intel 850 chipset.
Technical Reference Guide
Compaq Deskpro EXS Minitower
Compaq Deskpro Workstation 300
Figure 2–1. Compaq Deskpro Personal Computers with Monitors
This chapter includes the following topics:
♦ Features and options (2.2)page 2-2
♦ Mechanical design (2.3)page 2-4
♦ System architecture (2.4)page 2-8
♦ Specifications (2.5)page 2-13
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
2-1
Chapter 2 System Overview
2.2 FEATURES AND OPTIONS
This section describes the standard features and available options.
2.2.1 STANDARD FEATURES
The following standard features are included on all models:
♦ Intel Pentium 4 processor in PPGA423 package
♦ Intel 850 chipset
♦ Dual-channel Dire ct Rambus system memory
♦ Five 33-MHz/32-bit PCI slots
♦ One AGP slot
♦ Embedded Sound Blaster 128 PCI audio
♦ 3.5 inch, 1.44-MB diskette drive
♦ 48x Max CD-ROM drive
♦ IDE controllers with UATA/100 mode support
♦ Hard drive fault prediction
♦ One parallel, two serial, and four USB ports
♦ APM 1.2 power management support
♦ Plug ’n Play compatible (with ESCD support)
♦ Intelligent Manageability support
♦ Energy Star compliant
♦ Security features including:
• Serial/parallel port disable
♦ PS/2 Compaq Easy-Access keyboard w/Windows support
♦ PS/2 Compaq Scroll Mouse
Table 2-1 shows the differences in standard features between the Deskpros:
Table 2-1. StandardFeature Difference Matrix
Table 2-1.
Standard Feature Difference Matrix
Deskpro EXSDeskpro Workstation 300
Form FactorMinitowerConvertible Minitower
Standard Memory Type InstalledNon-ECCECC
Communication devi ce10/100 NIC & V.90 56K Modem10/100 NIC only
Mass Storage:
Interface Type
Drive Type
Standard AGP Graphics CardNVIDIA GeForce2 GTSNVIDIA TNT2 Pro,
UATA100
20- or 40-MB
2-2
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition – December 2000
Ultra 160 SCSI / UATA100
18 GB / 20 GB
NVIDIA Quadro2 MXR,
ELSA Gloria II, or
Matrox Millennium G450
2.2.2 OPTIONS
The following items are available as options for all models and may be included in the standard
configuration of some models:
♦ System Memory:PC800 64-MB RIMM (non-ECC, ECC)
♦ Hard drives/controllers:20-, 40-GB UATA/100 hard drive
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
2-3
Chapter 2 System Overview
2.3 MECHANICAL DESIGN
The following subsections describe the mechanical (physical) aspects of the covered Compaq
Deskpro models.
CAUTION: Voltages are present within the system unit whenever the unit is pluggedinto a live AC outlet, regardless of the “Power On” condition. Always disconnect the
!
power cable from the power outlet and/or from the system unit before handling the
system unit in any way. The following information is intended primarily for
identification purposes only. Before servicing these systems refer to the applicable
Maintenance And Service Guide and/or Service Reference Guide.
2.3.1 CABINET LAYOUTS
2.3.1.1 Front Views
Figure 2-2 shows the front cabinet layouts of the controls and indicators.
5
4
8
1
2
Deskpro EXS
6
7
9
3
ItemDescription
1Power button
2Power LED
3Hard drive act i vity LED
4CD-ROM drive headphone jack
5CD-ROM drive volum e control
6CD-ROM drive act i vi ty LED
7CD-ROM drive door open/cl ose button
81.44-MB diskette drive activit y LE D
91.44-MB diskette drive eject button
5
4
8
1
2
Deskpro Workstation 300
6
7
9
3
Figure 2–2. Front Cabinet Views
2-4
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition – December 2000
2.3.1.2 Rear View
Figure 2-3 shows the rear cabinet layout of the controls and connectors.
10
Technical Reference Guide
1
2
3
4
6
8
9
5
7
11
12
13
14
ItemDescription
1AC line In Connector (115V/230V)
2Line voltage switch
3Parallel I/F connector
4PS/2 keyboard connector
5PS/2 mouse connector
6Serial port A connector
7Serial port B connector
8USB ports (4)
9Microphone In audio jack
10Headphone/ Li ne Out audio jack
11Li ne I n audi o j ack
12Ul tra SCSI connector (some Workstation models only)
13Net work I / F connector
14Graphi cs (RGB) monitor connect or
Figure 2–3. Rear Cabinet View
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
2-5
Chapter 2 System Overview
2.3.2 CHASSIS LAYOUT
For detailed information on servicing the chassis refer to the multimedia training CD-ROM and/or
the maintenance and service guide for these systems.
Figure 2-4 shows the layout for the system in a minitower configuration. This chassis provides:
♦ Three 5 ¼-inch drive bays and two 3 ½-inch drive bays
♦ Easy access to expansion slots and all socketed system board components.
♦ Space for either a µATX- or full ATX-type system board.
Power Supply
Chassis Fan/
Air Baffle
System Board
Back
PCI Slot 1 [1]
PCI Slot 2 [1]
Graphics Card in AGP Slot
PCI Slot 3
PCI Slot 4
PCI Slot 5
NOTE:
Figure 2–4. Chassis Layout, Left Side View
Drive Bays
Front
Processor
Speaker
[1] May be populated with a V.90 56K modem in Deskpro EXS models.
May be populated with an Ultra 160 SCSI adapter in sel ect Workst aton 300 models.
2-6
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition – December 2000
2.3.3 BOARD LAYOUT
These systems use an ATX-type system board. Figure 2-5 shows the location of sockets,
connectors, headers, switches, jumpers, and LEDs.
27
26
25
24
23
Technical Reference Guide
2
1
3
178
5
4
6
9
10
11
12
13
15
22
ItemDescriptionItemDescription
1PCI expansion bus slot connectors15Power supply connector
2AGP slot connector16Secondary IDE connector
3Auxiliary audio input header17Power/LED connector [1]
4Chassis f an header18Primary IDE connector
5Line In, HP/Li ne Out, Mic In connectors19Power supply on / 5V Aux power LED
6USB ports (4)20Disket te drive connector
7Top: Serial port B ; Bottom: serial port A21CMOS clear button
8Top: mouse connector, Bot.: Kybd conn.22Power button LED
9Parallel port connector23Speaker connec tor
10CD audio input header24Bat t ery
11CPU power connector253.3V aux power LED
12Processor socket26AOL/SOS header
13Channel B RIMM sockets 3, 427Password clear jumper [2]
14Channel A RIMM sockets 1, 2----
NOTE:
[1] Connector for power button, Power/HD LEDs, and SCSI HD LEDs.
[2] Jumper instal l ed, password enabled. Jumper removed, password cleared.
192021
18 171416
System Board
(PCA# 010821)
Figure 2–5. System Board Layout
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
2-7
Chapter 2 System Overview
2.4 SYSTEM ARCHITECTURE
These systems feature architecture based on the Intel Pentium 4 processor and the Intel 850 chipset
(Figure 2-6). These components are designed to compliment each other to provide very high
desktop/minitower performance. Key technical highlights of this architecture include:
♦ 1.4 or 1.5-GHz Pentium 4 processor
♦ Quad-pumped Front Side Bus (FSB) for 400-MHz performance
♦ Dual-channel RDRAM controller supporting up to four PC800 RIMMs
♦ Two IDE controllers supporting two UATA-100 hard drives each
♦ Sound Blaster 128 audio subsystem
♦ Five 33-MHz/32-bit PCI slots
♦ AGP 4X slot (1.5-volt support only)
♦ One parallel port
♦ Two serial ports
♦ Four USB ports
♦ PS/2 mouse and keyboard interfaces
The Pentium 4 processor represents Intel’s latest IA-32 microprocessor design and features a
hyper-pipelined, rapid-execution engine for improved system responsiveness and higher execution
throughput. Internet and multimedia performance is improved further with additional str e aming
SIMD extensions (SSE2) designed to expedite video, speech, encryption, and photo processing
tasks.
The 3.2 GB/s throughput of the FSB matches that of the dua l -channel RDRAM used for system
memory, reducing latency and providing high, balanced performance. The 82850 Memory
Controller Hub (MCH) includes an AGP 4X interface supporting a 1.5-VDC graphics card in the
AGP slo t.
The 82801BA I/O Controller Hub (ICH2) and the LPC47B357 I/O Controller components provide
most of the input/output functions listed previously. These systems also include an AGP 4X
graphics card in the AGP slot and an Intel PRO/100+ Management Adapter (NIC) card in a PCI
slot. Some models may also include a modem card and a SCSI host adapter installed in PCI slots.
2-8
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition – December 2000
Pentium 4
p
Processor
Technical Reference Guide
RGB
Graphics
Controller
Card
AGP Slot
UATA/100
Hard Drive
CD
Audio
Audio
Subsystem
Power
Supply
Beep
Audio
AGP
4X
I/F
Pri. IDE
I/F
Sec. IDE
I/F
33-MHz
32-Bit PCI Bus
PCI Slot 5
400- MHz FSB
850 Chipset
82850
MCH
Hub Link
Bus
82801BA
ICH2
PCI Slot 4
RDRAM
Cntlr.
USB
I/F (4)
82802
FWH
Modem Card
PCI Slot 3
Channel A
RDRAM Bus
Channel B
RDRAM Bus
LPC
Bus
V.90
56K
PCI
PC800
RIMM Pair(s)
PC800
RIMM Pair(s)
Serial
I/F (2)
LPC47B357 I/O Controller
Keyboard/
Mouse I/F
Intel
PRO/100+
Mgmt.
Adapter Card
PCI Slot 2
Parallel
I/F
Diskette
I/F
SCSI
Hard Drive
Adaptec
29160N
SCSI
ter Card
Ada
PCI Slot 1
Some Deskpro Workstation 300 model s.
Some Deskpro EXS models.
Figure 2–6. System Architecture, Block diagram
Compaq Deskpro EXS and Workstation 300 Personal Computers
2-9
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
Chapter 2 System Overview
2.4.1 PENTIUM 4 PROCESSOR
These systems feature the Intel Pentium 4 processor featuring Intel’s NetBurst MicroArchitecture. This processor is backward-compatible with software written for the Pentium III/II,
Pentium MMX, Pentium Pro, Pentium, and x86 microprocessors.
Key features of the Pentium 4 processor include:
♦ Hyper-Pipelined Technology for higher p erformance
♦ Rapid Execution Engine with increased throughput and reduced latency
♦ Quad-pumped Front Side Bus (FSB) for balanced performance with RDRAM
♦ Execution Trace Cache for more efficient branch-handling
♦ Improved dynamic execution for higher efficiency
♦ Additional Streaming SIMD Extensions (SSE2) for increased video, audio, and speech
These systems employ a PGA423 zero-insertion-force (ZIF) socket designed for mounting a “FlipChip” (FC-PGA423) processor package (Figure 2-7).
Heat Sink
Retaining Clip
Heat Sink
Retaining Clip
Heat Sink
FC-PGA423
Lock/Unlock
Handle
(Shown in unlock position)
Package
PGA423
Socket
Figure 2–7. Processor Assembly And Mounting
The PGA423 socket allows easy changing/upgrading of the processor. Raising the Lock/Unlock
handle of the socket in the vertical position allows the processor package to be removed or inserted
into the socket. Lowering the Lock/Unlock handle in the down (horizontal) position locks the
processor package in place. The heat sink is placed on top of the processor and held in place by
two retaining clips.
2-10
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition – December 2000
2.4.2 CHIPSET
The chipset consists of a Memory Controller Hub (MCH), an I/O Controller Hub (ICH), and a
FirmWare Hub (FWH). Table 2-2 lists the integrated functions provided by the two types of
chipsets used in these systems.
Table 2-2. Chipset Comparison
ChipsetComponentFunction
85082850 MCHAGP 4X interface
Technical Reference Guide
Table 2-2.
Chipset Comparison
Dual-channel RDRAM controller supporti ng up to 4 PC800 RIMMs
400-MHz FSB
82801BA ICH2PCI bus I/F
LPC bus I/F
SMBus I/F
IDE I/F with UATA/100 support
AC ’97 controller
RTC/CMOS
IRQ controller
Power management logic
USB I/F (4)
8259 and I/O APIC interrupt processing
82802 FWHLoaded with Compaq BIOS
2.4.3 SUPPORT COMPONENTS
Input/output functions not provided by the chipset are handled by other support components. Table
2-3 shows the functions provided by the support components.
Table 2-3. Support Component Functions
Support Component Functions
Component NameFunction
LPC47B357 7 I/O ControllerKeyboard and pointing device I/F
Diskette I/F
Serial I/F (COM1and COM2)
Parallel I/F (LPT1, LPT2, or LP T3)
AGP, PCI reset generati on
ISA serial IRQ converter
Power button and LED control logic
GPIO ports
Digital-to-analog converter
Analog-to-digital converter
Analog I/O
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
2-11
Chapter 2 System Overview
2.4.4 SYSTEM MEMORY
These systems feature a dual-channel Direct Rambus (RDRAM) architecture. Capable of a peak
data throughput of 3.2 GB / s ec., this high-performance memory design represents a new generation
of memory subsystems that can keep pace with ever-increasing processor performance. These
systems each provide a total of four RIMM sockets, all of which will be populated with either
PC800 RDRAM memory modules (RIMMs) or continuity modules (CRIMMs). Up to two
gigabytes of memory may be installed.
Compaq Deskpro EXS systems are shipped with non-ECC PC800 RIMMs. Compaq Deskpro
Workstation 300 systems are shipped with ECC PC800 RIMMs. Both systems support ECC and
non-ECC RIMMs.
2.4.5 MASS STORAGE
All models include a 3.5 inch 1.44-MB diskette drive installed as drive A. Most models also
include a CD-ROM drive. The Deskpro EXS and some Deskpro Workstation 300 models will
include a UATA100 (EIDE) hard drive while select Deskpro Workstation 300 models will include
an Ultra 160 SCSI controller (PCI) card and SCSI hard drive. Standard hard drives feature Drive
Protection System (DPS) support, which uses industry-standard function ATAPI-5 to check drive
integrity. Standard drives also use SMART III technology that tests drive data during periods of
drive inactivity for corruption.
2.4.6 SERIAL, PARALLEL INTERFACES
All models include two serial ports and a parallel port accessible at the rear of the chassis. Each
serial port is RS-232-C/16550-compatible and supports standard baud rates up to 115,200 as well
as high-speed baud rates of 230K and 460K, and uses a DB-9 connector. The parallel interface is
Enhanced Parallel Port (EPP1.9) and Enhanced Capability Port (ECP) compatible, and supports
bi-directional data transfers through a D B-25 connector.
2.4.7 UNIVERSAL SERIAL BUS INTERFACE
All models feature four Universal Serial Bus (USB) ports that provide a 12Mb/s interface for
peripherals. The USB provide s hot plugging/unplugging (Plug ’n Play) functionality.
2-12
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition – December 2000
2.4.8 GRAPHICS SUBSYSTEM
Each of these systems provides an AGP slot that accommodates a Type 1 or Type 2 AGP graphics
adapter (1.5-V only).
Table 2-4 lists the key features of the types of graphics adapters available as standard in these
systems:
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
2-13
Chapter 2 System Overview
2.4.9 AUDIO SUBSYSTEM
All models feature an embedded Sound Blaster 128 PCI audio system using the AC’97 ver. 2.1
specification-based design. The subsystem features a Creative Labs, Inc. ES1373 audio controller
and a Cirrus Logic CS4297A audio codec. The output of the audio codec is applied to a 3-watt
amplifier that drives the chassis’ internal speaker. Standard microphone and line input jacks are
provided as well as a tri-purpose headphone/line/digital output jack that allows the use of
headphones or a pair of powered speakers (optional). The output jack also provides a digital audio
output signal using the Sony/Philips Digital Interface (SPDIF) format (officially known as IEC-
958).
2.5 SPECIFICATIONS
This section includes the environmental, electrical, and physical specifications for the Compaq
Deskpro EXS and Workstation 300 Series Personal Computers. Where provided, metric statistics
are given in parenthesis. All specifications subject to change without notice.
wet bulb temperature
Maximum Altitude10,000 ft (3048 m) [2]30,000 ft (9, 144 m) [2]
NOTE:
[1] Peak input accel erat i on duri ng an 11 ms half-sine shock pulse.
[2] Maximum rate of change: 1500 ft/min.
-24o to 140o F (-30o to 60o C, max.
rate of change < 20°C/Hr )
5-95% Rh @ 38.7o C max.
wet bulb temperature
Table 2-6. Electrical Specifications
Table 2-6.
Electrical Specifications
ParameterU.S.International
Input Line Voltage:
Nominal:
Maximum:
Input Line Frequency Range:
Nominal:
Maximum:
Power Supply:
Maximum Continuous Power
Maximum Line Current Draw
110 - 127 VAC
90 - 132 VAC
50 - 60 Hz
47 - 63 Hz
watts
A
200 - 240 VAC
180 - 264 VAC
50 - 60 Hz
47 - 63 Hz
watts
A
2-14
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition – December 2000
Technical Reference Guide
Table 2-7. Physical Specifications
Table 2-7.
Physical Specifications
ParameterDesktop ConfigurationMinitow er Confi guration
Height6.60 in (16.76 cm)17.65 in (44.83 cm)
Width17.65 in (44. 83 cm)6.60 in (16.76 cm)
Depth17.11 in (43.46 cm)17.11 in (43.46 cm)
Weight (nom.) [1]26 lb (11.8 kg)26 lb (11.8 kg)
Maximum Supported W e i ght [2]100N/A
NOTES:
[1] System weight may vary depending on installed drives/peripheral s.
[2] Assumes reasonable article(s) such as a display monitor and/or another s ystem unit.
Table 2-8. Diskette Drive Specifications
Table 2-8.
Diskette Drive Specifications
(Compaq SP# 179161-001)
ParameterMeasurement
Media Type3.5 in 1.44 MB/720 KB diskette
Height1/3 bay (1 in)
Bytes per Sector512
Sectors per Track:
High Density
Low Density
Tracks per Side:
High Density
Low Density
Read/Write Heads2
Average Access Time:
Track-to-Track (high/low)
Average (high/low)
Settling Time
Latency Average
18
9
80
80
3 ms/6 ms
94 ms/173ms
15 ms
100 ms
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
2-15
Chapter 2 System Overview
Table 2-9. 48x CD-ROM Drive Specifications
48x CD-ROM Drive Specifications
ParameterMeasurement
Interface TypeIDE
Transfer Rate:
Max. Sustained
Burst
Media TypeMode 1,2, Mixed Mode, CD-DA,
Capacity:
Mode 1, 12 cm
Mode 2, 12 cm
8 cm
Center Hole Diameter15 mm
Disc Diameter8/12 cm
Disc Thickness1.2 mm
Track Pitch1.6 um
Laser
Beam Divergence
Output Power
Type
Wave Length
Average Access Time:
Random
Full Stroke
Audio Output Level0.7 Vrms
Cache Buffer128 KB
Table 2-9.
(SP# 187217-B21)
4800 KB/s
16.6 MB/s
Photo CD, Cdi, CD-XA
550 MB
640 MB
180 MB
53.5 +/- 1.5 °
53.6 0.14 mW
GaAs
790 +/- 25 nm
<100 ms
<150 ms
Table 2-10. Hard Drive Specifications
Table 2-10.
Hard Drive Specifications
Parameter18.0 GB20.0 GB40.0 GB
Drive Size3.5”3.5”5.25”
InterfaceUltra 160 SCSIUATA/100UATA/100
Drive Protection System Support?YesYesYes
Transfer Rate (max)160 MB/s100 MB/s100 MB/s
Typical Seek Time (w/sett l i ng) [ 1]
Single Track
Average
Full Stroke
Disk Format (logic al ):
# of Cylinders
# of Data Heads
# of Sectors per Track
Rotation Speed10,000 RPM7200 RPM7200 RPM
Drive Fault PredictionSMART IIISMART IIISMART III
NOTE:
2-16
Compaq Deskpro EXS and Workstation 300 Personal Computers
Actual times may vary depending on specific dri ve installed.
All EMEA units feat ure Qui et Dri ves.
[1] Operates at 66 MB/s in t hese systems.
Featuring the Intel Pentium 4 Processor
1.7 ms
8.5 ms
15 ms
16383
16
63
2.0 ms
9.5 ms
21 ms
16383
16
63
1.0 ms
9.0 ms
20 ms
16383
16
63
First Edition – December 2000
Chapter 3
PROCESSOR/
MEMORY SUBSYSTEM
3.Chapter 3 PROCESSOR/MEMORY SUBSYSTEM
3.1 INTRODUCTION
This chapter describes the processor/memory subsystem of Compaq Deskpro Personal Computers
featuring the Pentium 4 processor. These systems feature the Pentium 4 processor and the 850
chipset (Figure 3-1). The 82850 MCH component of the 850 chipset supports two Direct Rambus
channels, each channel accommodating one or two RIMMs.
♦ Pentium 4 processor [3.2]page 3-2
♦ Memory sub system [3.3]page 3-5
♦ Subsystem configuration {3.4]p age 3-8
XMM1
RIMM
In
Socket
System Memory
XMM2
RIMM
Socket
XMM3
RIMM
Socket
XMM4
RIMM
In
Socket
Compaq Deskpro EXS and Workstation 300 Personal Computers
3-1
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
Chapter 3 Processor/Memory Subsystem
3.2 PENTIUM 4 PROCESSOR
These systems each feature an Intel Pentium 4 processor in a FC-PGA423 package mounted with a
passive heat sink in a PGA423 (W-type) zero-insertion force socket. The mounting socket allows
the processor to be easily changed for servicing and/or upgrading.
3.2.1 PROCESSOR OVERVIEW
The 1.4-/1.5-GHz Intel Pentium 4 processor represents the latest generation of Intel’s IA32-class
of processors. Featuring Intel’s NetBurst architecture, the Pentium 4 processor is designed for
intensive multimedia and internet applications of today and the future while maintaining
compatibility with software written for earlier (Pentium III, Pentium II, Pentium, Celeron, and x86)
microprocessors. Key features of the Pentium 4 processor include:
♦ Hyper-Pipelined Technology – The main processing loop has twice the depth (20 stages) of
the Pentium III allowing for increased processing frequencies.
♦ Execution Trace Cache – A new feature supporting the branch prediction mechanism, the
trace cache stores translated sequences of branching micro-operations (µops) and is checked
when suspected re-occurring branches are detected in the main processing loop. This feature
allows instruction decoding to be removed from the main processing loop.
♦ Rapid Execution Engine – Arithmetic Logic Units (ALUs) run at twice (2x) processing
frequency for higher throughput and reduced latency.
♦ 256-KB Advanced transfer L2 cache – Using 32-byte-wide interface at processing speed, the
L2 cache can provide 48 GB/s perrformance (3x over the Pentium III)
♦ Advanced dynamic execution – Using a larger (4K) branch target buffer and improved
prediction algorithm, branch mis-predictions are reduced by an average of 33 % over the
Pentium III.
♦ Enhanced Floating Point Processor - With 128-bit integer processing and deeper pipelining
the Pentium 4’s FPU provides a 2x performance boost over the Pentium III.
♦ Additional Streaming SIMD extensions (SSE2) – In addition to the SSE support provided by
previous Pentium processors, the Pentium 4 processor includes an additional 144 MMX
instructions, fur t her enhancing:
• Streaming video/audio processing
• Photo/video editing
• Speech recognition
• 3D processing
• Encryption processing
♦ Quad-pumped Front Side Bus (FSB) – The FSB uses a 100-MHz clock for qualifying the
buses’ control signals. However, address information is transferred using a 200-MHz strobe
while data is transferred with a 400-MHz strobe, providing a maximum data transfer rate of
3.2 GB/s. This is a 3x boost over a Pentium III with a 133-MHz FSB. The 3.2 GB/s peak
transfer rate of the FSB balances the 3.2 GB/s maximum transfer capability of the dualchannel Direct Rambus system memory.
3-2
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
Figure 3-1 illustrates the internal architecture of the Pentium 4 processor.
The Pentium 4 increases processing speed with higher clock speeds made possible with hyperpipelined technology that can handle significantly more instructions at a time. Since branch mispredicts would result in serious performance hits with such a long pipeline, the Pentium 4 features
a branch prediction mechanism improved with the addition of an execution trace cache and a
refined prediction algorithm. The execution trace cache can store 12k micro-ops (decoded
instructions dealing with branching sequences) that are checked when re-occurring branches are
processed. Code that is not executed (bypassed) is no longer stored in the L1 cache as was the case
in the Pentium III.
The out-of-order core features Advanced Dynamic Execution, which provides a large window (126
instructions) for execution units to work with. A more accurate branch prediction algorithm, along
with a larger (4-KB) branch target buffer that stores more details on branch history results in a
33% reduction in branch mis-predictions over the Pentium III.
The L1 data cache features a low-latency design for minimum response to cache hits. The 256-KB
advanced transfer L2 cache features a 256-bit (32-byte) interface operating at processing speed.
The L2 cache of the 1.5 GHz Pentium 4 can therefore provide a transfer rate of 48 GB/s.
The combined improvements of the Pentium 4’s CPU core the rapid execution engine’s ALUs to
operate at twice the processing frequency to handle the steady stream of instructions.
The front side bus (FSB) of the Pentium 4 uses a 100-MHz clock but provides Quad-pumped data
transfers. While the Pentium III could transfer 8 bytes of data on a 133-MHz clock cycle the
Pentium 4 can transfer 32 bytes of data on a 100-MHz clock cycle for a throughput rate of 3.2
GB/s, balancing the performance of the dual-Rambus memory subsystem. Address information is
transferred at a 200-MHz rate.
Compaq Deskpro EXS and Workstation 300 Personal Computers
3-3
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
Chapter 3 Processor/Memory Subsystem
The Pentium 4 processor is software-compatible with Celeron, Pentium II, Pentium MMX,
Pentium, and x86 processors, but will require the latest versions of operating system software to
take advantage of the Streaming SIMD extensions (SSE2).
3.2.2 PROCESSOR UPGRADING
All units use the PGA423 ZIF mounting socket and ship with the Pentium 4 processor in a FlipChip (FC-PGA423) package installed with a passive heat sink. The FC-PGA423 package consists
of the processor die mounted “upside down” on a PC board. This arrangement allows the heat sink
to come in direct contact with the processor die. The heat sink and attachment clip are specially
designed provide maximum heat transfer from the processor component.
CAUTION: Attachment of the heat sink to the processor is critical on these systems.
Improper attachment of the heat sink will likely result in a thermal condition.
!
Although the system is designed to detect thermal conditions and automatically shut
down, such a condition could still result in damage to the processor component. Refer to
the applicable Maintenance and Service Guide for processor installation instructions.
3-4
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
3.3 MEMORY SUBSYSTEM
The 82850 MCH features Direct Rambus technology and supports two Rambus channels, each
channel supporting up to two Rambus DRAM modules (RIMMs). Direct Rambus technology
provides a significant improvement in performance over DRAM/SDRAM memory designs and
allows the system memory to keep pace with increasing processor performance. Rambus
technology implements RDRAM devices accessed over a channel specifically designed for high
speed operations.
As shown in Figure 3-3, the conventional DRAM-based memory interface with a transfer rate of
66, 100, or 133 MHz increases bandwidth by widening the data bus. With the current top speed of
133 MHz, a 64-bit SDRAM interface achieves a maximum transfer rate of 1.0 GB/s.
Byte 0
Byte 1
Byte 2
SDRAM
Memory
Controller
Byte 3
Byte 4
Byte 5
Byte 6
DIMM
RDRAM
Memory
Controller
Technical Reference Guide
Byte 0
Byte 1
Byte 2
Byte 3
Ch 1
RIMM
Ch 2
RIMM
Byte 7
SDRAM Interface
64-bit Path
8 bytes @ 133 MHz = 1.0 GB/s
RDRAM Interface (Dual Channel)
32-bit Path
4 bytes @ 400 MHz = 3.2 GB/s (see text)
Figure 3–3. SDRAM/RDRAM Bandwidth Comparison
Although a Rambus channel handles only two bytes per tra nsfer, data is clocked on bot h t he rising
and falling edges of the clock signal, allowing a 400-MHz clock to provide an effective speed of
800 MHz and resulting a transfer rate of 1.6 GB/s. Doubling the number of channels doubles the
throughput. These systems feature dual-c hannel RDRAM architec ture that provi des a maximum
transfer rate of 3.2 GB/s.
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
3-5
First Edition - December 2000
Chapter 3 Processor/Memory Subsystem
3.3.1 RAMBUS ATTRIBUTES
To ensure signal quality during high-speed memory transfers, the Rambus interface design departs
from previous memory interface designs in several key aspects (Figure 3-4). Rambus uses a daisychained signal distribution system that requires that all memory sockets be populated with either a
RIMM or a continuity module (CRIMM) in order to maintain constant load impedance. Rambus
Signaling Levels (RSL) uses a 1.4-volt reference with a 0. 8-volt swing between logic 0 at 1.8 V
and logic 1 at 1.0 V.
On these systems RIMMs (or CRIMMs) must be installed in pairs (one module for each channel).
A maximum of two gigabytes of memory may be installed using 512-MB RIMMs. These systems
ship with PC800 (400-MHz) RIMMs but will also accept PC700 or PC600 RIMMs. A mix of
ECC and non-ECC RIMMs may be installed, although all RIMMs must be ECC to realize ECC
benefits.
RIMM
RIMM or CRIMM (Shown)
RIMM
MCH
Signal Name
ROW 2..03ORSL28 ohm sRow address
COL 4..05ORSL28 ohmsCol umn address
DQA 8..09I/ORSL28 ohmsData byte A (w/parity or ECC bit)
DQB 8..09I/ORSL28 ohmsData byte B (w/parity or ECC bit)
CFM, CFMN2ORSL [2]28 ohms400-MHz Clock -f rom-master for writes
CTM, CTMN2IRSL [2]28 ohms400-MHz Clock-to-master for reads
Vref1--1.4 V--Reference volt age for RSL signals
SIO1I/OCMOS--Serial I/F for initialization & pwr cntrl.
SCK1OCMOS56 ohmsSIO clock ; 1 MHz for configuration,100
CMD1I/OCMOS56 ohmsSeri al I /F config. & power control
Vdd--2.5 V--Power for Rambus ci rcuitry
NOTES:
[1] Relative to the memory controller.
[2] Differential pair with Ep-p swing of 400 to 600 mV.
Channel 1
No. of
Lines
Channel 2
RIMM Sock ets
Rambus Signal Attributes (Each Channel)
Input/
Output [1]
Signal
LevelImpedanceFunction
Bus Termination
MHz for power management.
Figure 3–4. Rambus Channel Signal Distribution and Key Attributes
3-6
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
3.3.2 RAMBUS CHANNEL TRANSACTIONS
Transactions on the Rambus Channel involve packets of control (row or column) bits and packets
of data bits. Each packet consists of eight segments, with even segments transferred on falling
clock edges and odd segments transferred on rising clock edges. A typical operation consists of the
memory controller sending out a 24-bit row packet followed by a 40-bit column packet and then
the 144-bit (128-bit for non-ECC) data packet being either written to or read from RDRAM
(Figure 3-5).
The clock signal is driven by the source device (i.e., by the memory controller during writes, by the
RDRAM device during reads). The row (ROW) and column (COL) signal lines are driven only by
the memory controller and assume the functions provided by the RAS/CAS signals of traditional
memory buses. The ROW and COL signals are also used for power management and defining the
type (read/write) of transaction. The data lines (DQAx/DQBx) are bi-directional, being driven by
the controller during writes and by the RDRAM during reads. There is a specified delay period
between related Row and Column packets (Trc, typically 7 clock cycles) and related column and
data packets (Tcd, typically 8 to 12 clock cycles).
Note that while Figure 3-5 illustrates a single Rambus transaction, actual operation can involve
pipelined transactions where back-to-back column packets are sent followed by back-to-back data
packets. A row packet may be omitted if the row to be accessed is already open. Another important
characteristic is that the ROW, COL, and DQA/DQB signal lines act as independent buses and
simultaneous transfers of row, column, and data information can take place.
Compaq Deskpro EXS and Workstation 300 Personal Computers
3-7
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
Chapter 3 Processor/Memory Subsystem
3.3.3 RDRAM POWER MANAGEMENT
The Rambus architecture provides for power management of each RDRAM device on a RIMM.
RDRAM power management control is compatible with but may also work independently of
ACPI. Power management o f RDRAM is handled through control packets as well as the serial bus.
Aside from complete “system off” state, an RDRAM may be placed in one of four basic power
states:
♦ Active
♦ Standby
♦ Nap
♦ Powerdown
These states are characterized by parameters such as power consumed, refresh method, and the
time required to resume full (Active state) operation. The following table defines the RDRAM
power states.
State
Powerdown1 mWS el fStopped
Nap10 mWMCHOn90 nsLow power state. Can remain in this state for up
Standby250 mWMCHOn20 nsIdle power state automatically entered after a
Active500 mWMCHOn--Full power state. Available to receive control
NOTES:
[1] Per RDRAM device
[2] Transition to Active state
Power
Consumed [1]
Refresh
Method
RDRAM
CLK
3.3.4 RDRAM CONFIGURATION/CONTROL
The Rambus architecture employs a CMOS-level serial bus (SIO, SCK, CMD) similar to that used
on SDRAM-equipped systems. This bus is used for status and control of RDRAM configuration
parameters as well as bringing RDRAM devices out of Powerdown and Nap states. The SIO signal
is bi-directional and daisy-chai ned through all RDRAM devices, alternating from SIO0 to SI O1
between devices . The SCK and CMD signals are applied in parallel to all RDRAM devices. The
SCK signal operates at 1 MHz during configuration and at 100 MHz when commands are issued to
switch RDRAM devices from Powerdown or Nap states.
Exit
Latency [2]
12 µs
RDRAM Functionality
Lowest power state and condition entered after
initialization. Can remain in thi s s tat e indef init ely.
Brought out of Powerdown only by command
over the SIO serial bus.
to 10 µs. Brought out of Nap only by com mand
over the SIO serial bus.
transaction. Available to receive row packets.
Transitions to Act ive or Nap state upon receipt
of specific command on ROW bus .
packets and transm i t or receive data packets.
3-8
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
Technical Reference Guide
(
)
The memory controller and RDRAM are configured by BIOS during POST. Refer to Chapter 8 for
the configuration procedure performed by BIOS.
Figure 3-6 shows the system memory map.
Host,
PCI, AGP Area
Host, PCI,
ISA Area
DOS Compatibility
Area
FFFF FFFFh
FFE0 0000h
FFDF FFFFh
FEC1 0000h
FEC0 FFFFh
FEC0 0000h
FEBF FFFFh
2000 0000h
1FFF FFFFh
0100 0000h
00FF FFFFh
0010 0000h
000F FFFFh
000F 0000h
000E FFFFh
000E 0000h
000D FFFFh
000C 0000h
000B FFFFh
000A 0000h
0009 FFFFh
0008 0000h
0007 FFFFh
High BIOS Area
(2 MB)
PCI Memory
(18 MB)
APIC Config. Space
(64 KB)
PCI Memory
Expansion
(3060 MB)
Host/PCI Memory
Expansion
(496 MB)
Extended Memory
15 MB
System BIOS Area
(64 KB)
Extended BIOS
Area
Option ROM
(128 KB)
Graphics/SMRAM
RAM (128 KB)
Fixed Mem. Area
(128 KB)
4 GB
512 MB
16 MB
1 MB
640 KB
512 KB
Base Memory
(512 KB)
0000 0000h
NOTE: All locations in memory are cacheable. Base memory is always m apped to DRAM. The next 128 KB
fixed memory area can, through t he MCH, be mapped to DRAM or to PCI space. Graphi cs RAM area is
mapped to PCI or AGP loc ations.
Figure 3–6. System Memory Map
Compaq Deskpro EXS and Workstation 300 Personal Computers
3-9
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
Chapter 3 Processor/Memory Subsystem
3.4 SUBSYSTEM CONFIGURATION
The MCH component provides the configuration function for the processor/memory subsystem.
Table 3-1 lists the configuration registers used for setting and checking such parameters as
memory control and PCI bus operation. These registers reside in the PCI Configuration Space and
accessed using the methods described in Chapter 4, section 4.2.
Table 3–1. Host/PCI Bridge Configuration Registers (GMCH, Function 0)
60..67hDRAM Row Boundary01hBChAperture I/F Timer00h
68hFixed DRAM Hole00hBDhLow Priority Timer00h
Register
Reset
Value
Table 3-1.
PCI
Config.
Addr.
R
egister
Reset
Value
NOTES:
3-10
Compaq Deskpro EXS and Workstation 300 Personal Computers
Refer to Intel Inc. documentation for detailed description of registers.
Assume unmark ed l o cations/gaps as reserved.
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
Chapter 4
SYSTEM SUPPORT
4.Chapter 4 SYSTEM SUPPORT
4.1 INTRODUCTION
This chapter covers subjects dealing with basic system architecture and covers the following
topics:
♦ PCI bus overview (4.2)page 4-2
♦ AGP bus overview (4.3)page 4-10
♦ System resources (4.4)page 4-15
♦ System clock distribution (4.5)page 4-20
♦ Real-time clock and configuration memory (4.6) page 4-20
♦ System management (4.7)page 4-31
♦ Register map and miscellaneous functions (4.8) page 4-35
This chapter covers functio ns provided by off-the-shelf chipsets and therefore d escribes only basi c
aspects of these functions as well as information unique to the sytems covered in this guide. For
detailed information on specific components, refer to the applicable manufacturer’s
documentation.
Technical Reference Guide
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
4-1
Chapter 4 System Support
4.2 PCI BUS OVERVIEW
NOTE: This section describes the PCI bus in general and highlights bus implementation
in this particular system. For detailed information regarding PCI bus operation, refer to
the PCI Local Bus Specification Revision 2.2.
This system implements a 32-bit Peripheral Component Interconnect (PCI) bus (spec. 2.2)
operating at 33 MHz. The PCI bus handles a ddress/data transfers through the i dentification of
devices and functions on the bus. A device is typically defined as a component or slot that resides
on the PCI bus (although some compo nents suc h as the MCH and ICH are organized as multiple
devices). A function is defined as the end source or target of the bus transaction. A device may
contain one o r more functions.
In the standard configuration these systems use a hierarchy of three PCI buses (Figure 4-1). The
PCI bus #0 is internal to the MCH/ICH chipset components and is not physically accessible. The
AGP bus that services the AGP slot is designated as PCI bus #1. All PCI slots reside on PCI bus
#2.
82850 MCH Component
Mem. Cnt lr.
Function
Hub Link I/F
PCI
Bus #0
AGP
Bridge
Function
PCI Bus #1
(AGP Bus)
AGP Connector
Hub Link Bus
Hub Link I/F
PCI Bridge
Function
PCI
Bus #2
Not used in these systems.
NIC
I/F
Function
ES1373
Controller
Audio
PCI Connector 1
82801BA ICH2 Component
PCI Bus #0
EIDE
Controller
Function
PCI Connector 2
PCI Connector 3
Figure 4-1. PCI Bus Devices a nd Functions
USB
I/F
Function
PCI Connector 4
PCI Connector 5
SMBus
Controller
Function
LPC
Bridge
Function
AC97
Audio
Function
Compaq Deskpro EXS and Workstation 300 Personal Computers
4-2
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
4.2.1 PCI BUS TRANSACTIONS
The PCI bus consists of a 32-bit path (AD31-00 lines) that uses a multiplexed scheme for handling
both address and data transfers. A bus transaction consists of an address cycle and one or more
data cycles, with each cycle requiring a clock (PCICLK) cycle. High performance is realized
during burst modes in which a transaction with contiguous memory locations requires that only one
address cycle be conducted and subsequent data cycles are completed using auto-incremented
addressing. Four types of address cycles can take place on the PCI bus; I/O, memory,
configuration, and special. Address decoding is distributed (left up to each device on the PCI bus).
4.2.1.1 I/O and Memory Cycles
For I/O and memory cycles, a standard 32-bit address decode (AD31..0) for byte-level addressing
is handled by the appropriate PCI device. For memory addressing, PCI devices decode the
AD31..2 lines for dword-level addressing and check the AD1,0 lines for burst (linearincrementing) mode. In burst mode, subsequent data phases are conducted a dword at a time with
addressing assumed to increment accordingly (four bytes at a time).
Technical Reference Guide
4.2.1.2 Configuration Cycles
Devices on the PCI bus must comply with PCI protocol that allows configuration of that device by
software. In this system, configuration mechanism #1 (as described in the PCI Local Bus
specification Rev. 2.1) is employed. This method uses two 32-bit registers for initiating a
configuration cycle for accessing the configuration space of a PCI device. The configuration
address register (CONFIG_ADDRESS) at 0CF8h holds a value that specifies the PCI bus, PCI
device, and specific register to be accessed. The configuration data register (CONFIG_DATA) at
0CFCh contains the c onfiguration da t a.
PCI Configuration Address Register
I/O Port 0CF8h, R/W, (32-bi t access only)
BitFunctionBitFunction
31Configuration Enable
0 = Disabled
1 = Enable
30..24Reserved - read/write 0s
23..16Bus Number. Selects PCI bus
15..11PCI Device Number. Selects PCI
device for access
10..8Func tion Number. Selects function of
selected PCI device.
7..2Register Index. Specifies config. reg.
1,0Configuration Cycle Type ID.
00 = Type 0
01 = Type 1
PCI Configuration Data Register
I/O Port 0CFCh, R/W, (8-, 16-, 32-bit access)
31..0Configurat i on Data.
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
4-3
Chapter 4 System Support
Two types of configuration cycles are used. A Type 0 (zero) cycle is targeted to a device on the
PCI bus on which the cycle is running. A Type 1 cycle is targeted to a device on a downstream PCI
bus as identified by bus number bits <23..16>. With three or more PCI buses, a PCI bridge may
convert a Type 1 to a Type 0 if it’s destined for a device being serviced by that bridge or it may
forward the Type 1 cycle unmodified if it is destined for a device being serviced by a downstream
bridge. Figure 4-2 shows the configuration cycle format and how the loading of 0CF8h results in a
Type 0 configuration cycle on the PCI bus. The Device Number (bits <15..11> determines which
one of the AD31..11 lines is to be asserted high for the IDSEL signal, which acts as a “chip select”
function for the PCI device to be configure d. The function number (CF8h, bits <10..8> ) is used to
select a particular function within a PCI component.
Register 0CF8h
Results in:
AD31..0
(w/Type 0
Config. Cycle)
3124 2316 1511 108
Reserved
IDSEL (only one signal line asserted)
Bus
Number
Device
Number
Function
Number
Function
Number
72 1 0 [1]
Register
Index
Register
Index
NOTES:
[1] Bits <1,0> : 00 = Type 0 Cycl e, 01 = Type 1 cycle
Type 1 cycle only. Reserved on Type 0 cycle.
Figure 4-2. Configuration Cycle
Table 4-1 shows the standard configuration access data for components and slots residing on a PCI
bus.
Table 4-1. PCI Device Configuration Access Data
[1] Not implem ent ed on these systems.
[2] Value in standard confi guration. Can change if an AGP card with an additional bridge is installed.
[3] Card specific. Refer to appendices.
Compaq Deskpro EXS and Workstation 300 Personal Computers
4-4
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
Configuration
d
Space
Header
Technical Reference Guide
The register index (CF8h, bits <7..2>) identifies the 32-bit location within the configuration space
of the PCI device to be accessed. All PCI devices can contain up to 256 bytes of configuration data
(Figure 4-3), of which the first 64 bytes comprise the configuration space header.
Register
3124 2316 158 70
Device-Specific A rea
Int. LineInt. PinMin. GNTMin. Lat.
Reserved
Reserved
Expansion ROM Base Address
Subsystem Vendor IDSubsystem ID
Card Bus CIS Pointer
Base Address Registers
BISTHdr. Type
Status
Device ID
Line SizeLat. Timer
Command
Vendor ID
Index
FCh
40h
3Ch
38h
34h
30h
2Ch
28h
10h
0Ch
08h
04h
00h
3124 2316 15870
Device-Specific A rea
Bridge Control
Expansion ROM Base Address
Reserved
I/O Base Upper 16 BitsI/O Limit Upper 16 Bits
Prefetchable Limit Upper 32 Bits
Prefetchable Base Upper 32 Bits
Prefetch. Mem. LimitPrefetch. Mem . Base
Memory BaseMemory Limit
n
Base Address Registers
BISTHdr. Type
Status
Device ID
Int. LineInt. Pin
I/O BaseI/O LimitSecondary Status
Pri. Bus #Sec. Bus #Sub. Bus #2
Line SizeLat. Timer
Command
Vendor ID
Register
Index
FCh
40h
3Ch
38h
34h
30h
2Ch
28h
24h
20h
1Ch
18h
10h
0Ch
08h
04h
00h
PCI Configuration Space Type 0
Data required by PCI protocol
Not required
PCI Configuration Space Type 1
Figure 4-3. PCI Configuration Space Mapping
Each PCI device is identified with a vendor ID (assigned to the vendor by the PCI Special Interest
Group) and a device ID (assigned by the vendor). The device and vendor IDs for the devices on
the system board are listed in Table 4-1.
Compaq Deskpro EXS and Workstation 300 Personal Computers
4-5
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
Chapter 4 System Support
4.2.2 PCI BUS MASTER ARBITRATION
The PCI bus supports a bus master/target arbitration scheme. A bus master is a device that has
been granted control of the bus for the purpose of initiating a transaction. A target is a device that
is the recipient of a transaction. The Request (REQ), Grant (GNT), and FRAME signals are used
by PCI bus masters for gaining access to the PCI bus. When a PCI device needs access to the PCI
bus (and does not already own it), the PCI device asserts it’s REQn signal to the PCI bus arbiter (a
function of the system controller component). If the bus is available, the arbiter asserts the GNTn
signal to the requesting device, which then asserts FRAME and conducts the address phase of the
transaction with a target. If the PCI device already owns the bus, a request is not needed and the
device can simply assert FRAME and conduct the transaction. Table 4-2 shows the grant and
request signals assignments for the devices on the PCI bus.
Table 4-2. PCI Bus Mastering Devices
Table 4-2.
PCI Bus Mastering Devices
REQ/GNT LineDevice
REQ0/GNT0PCI Connector Sl ot 1
REQ1/GNT1PCI Connector Sl ot 2
REQ2/GNT2PCI Connector Sl ot 3
REQ3/GNT3PCI Connector Sl ot 4
REQ4/GNT4PCI Connector Sl ot 5
REQ5/GNT5ES1373 Audio Controller
GREQ/GGNTAGP Slot
PCI bus arbitration is based on a round-robin scheme that complies with the fairness algorithm
specified by the PCI specification. The bus parking policy allows for the current PCI bus owner
(excepting the PCI/ISA bridge) to maintain ownership of the bus as long as no request is asserted
by another agent. Note that most CPU-to-DRAM and AGP-to-DRAM accesses can occur
concurrently with PCI traffic, therefore reducing the need for the Host/PCI bridge to compete for
PCI bus ownership.
Compaq Deskpro EXS and Workstation 300 Personal Computers
4-6
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
4.2.3 OPTION ROM MAPPING
During POST, the PCI bus is scanned for devices that contain their own specific firmware in
ROM. Such option ROM data, if detected, is loaded into system memory’s DOS compatibility area
(refer to the system memory map shown in chapter 3).
4.2.4 PCI INTERRUPTS
Eight interrupt signals (INTA- thru INTH-) are available for use by PCI devices. These signals
may be generated by on-board PCI devices or by devices installed in the PCI slots. For more
information on interrupts including PCI interrupt mapping refer to the “System Resources” section
4.4.
4.2.5 PCI POWER MANAGEMENT SUPPORT
This system complies with the PCI Power Management Interface Specification (rev 1.0). The PCI
Power Management Enable (PME-) signal is supported by the chipset and allows compliant PCI
and AGP peripherals to initiate the power management routine.
Technical Reference Guide
4.2.6 PCI SUB-BUSSES
The chipset implements two data busses that are supplementary in operation to the PCI bus:
4.2.6.1 Hub Link Bus
The chipset implements a Hub Link bus between the MCH and the ICH. The Hub Link bus
handles transactions at a 66-MHz rate using PCI-type protocol, and in fact operates as PCI bus #0.
This bus is transparent to software and not accessible for expansion purposes.
4.2.6.2 LPC Bus
The 82801 ICH implements a Low Pin Count (LPC) bus for handling transactions to and from the
47B357 Super I/O Controller as well as the 82802 FWH. The LPC bus transfers data a nibble (4
bits) at a time at a 33-MHz rate. Generally transparent in operation, the LPC bus becomes a factor
primarily during the configuration of DMA channel modes (see section 4.4.3 “DMA”).
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
4-7
Chapter 4 System Support
4.2.7 PCI CONFIGURATION
PCI bus operations require the configuration of certain parameters such as PCI IRQ routing, DMA
channel configura tion, RTC cont rol, port decode ranges, and power management options. The s e
parameters are handled by the LPC I/F bridge function (PCI function #0, device 31) of t he ICH
component and configured through the PCI configuration space registers listed in Table 4-3.
Configuration is provided by BIOS at power-up but re-configurable by software.
Table 4-3. LPC Bridge Configuration Registers (ICH, Function 0)
PCI
Config.
Addr.Register
00, 01hVendor ID8086h8AhDevice 31 Error Status00h
02, 03hDevice ID2410h90, 91hPCI DMA Configuration0000h
04, 05hCommand000FhA0-CFhPower Management
06, 07hStatus0280hD0-D3hGeneral Control0’s
08hRevision ID00hD4-D7hGeneral StatusF00h
0A-0BhClass Code0106hD8hRTC Configuration00h
0EhHeader Type80hE0hLPC COM Port Dec. Range00h
40-43hACPI Base Address1E1hLPC FDD & LPT Dec . Rge00h
44hACPI Control00hE2hLPC Audio Dec. Range80h
4E, 4FhBIOS Control0000hE3hFWH Decode EnableFFh
54hTCO Control00hE4, E5hLPC I/F Dec ode Range 10000h
58-5BhGPIO Base Address1E6, E7hLPC I/F Enables0000h
5ChGPIO Control00hE8hFWH Select00
60-63hINTA-D Rout i ng Cnt rl .80h [1 ]EC, EDhLPC I/ F Decode Range 20000h
64hSerial IRQ Control10hEE, EFhReserved-65-87hReserved--F0hReserved-88hDev. 31 Error Config.00hF2hFunction Disable Register00h
Table 4-3.
LPC Bridge Configuration Registers
(ICH, Function 0, Device 31)
PCI
Reset
Value
Config.
Addr.Register
Reset
Value
NOTE:
Compaq Deskpro EXS and Workstation 300 Personal Computers
4-8
[1] Value for each byte.
Assume unmark ed l ocations/gaps as reserved.
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
4.2.8 PCI CONNECTOR
Technical Reference Guide
B94
A94
A62
B62
B52
A52
B49
A49
B1
A1
Figure 4-4. PCI Bus Connector (32-Bit Type)
Table 4-4. PCI Bus Connector Pinout
Table 4-4.
PCI Bus Connector Pinout
PinB SignalA SignalPinB SignalA SignalPinB SignalA Signal
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
4-9
Chapter 4 System Support
4.3 AGP BUS OVERVIEW
NOTE: This section provides a brief description of AGP bus operation. For a detailed
description of AGP bus operations as supported by these systems refer to the AGPInterface Specification Rev. 2.0 available at the following AGP forum web site:
http://www.agpforum.org/index.htm
The Accelerated Graphics Port (AGP) bus is specifically designed as an economical yet highperformance interface for graphics adapters, especially those designed for 3D operations. The
AGP interface is designed to give graphics adapters dedicated pipelined access to system memory
for the purpose of off-loading texturing, z-buffering, and alpha blend ing used in 3D graphics
operations. By off-loading a large portion of 3D data to system memory the AGP graphics adapter
only require s enough memory for frame b uffer (display image) refreshing.
4.3.1 BUS TRANSACTIONS
The operation of the AGP bus is based on the 66-MHz PCI specification but includes additional
mechanisms to increase bandwidth. During the configuration phase the AGP bus acts in
accordance with PCI protocol. Once graphics data handling operation is initiated, AGP-defined
protocols take effect. The AGP graphics adapter acts generally as the AGP master, but can also
behave as a “PCI” target during fast writes from the MCH.
Key differences between the AGP interface and the PCI interface are as follows:
♦ Address phase and associated data transfer phase are disconnected transactions. Addressing
and data transferring occur as contiguous actions on the PCI bus. On the AGP bus a request
for data and the transfer of data may be separated by other operations.
♦ Commands on the AGP bus specify system memory accesses only. Unlike the PCI bus,
commands involving I/O and configuration are not required or allowed. The system memory
address space used in AGP operations is the same linear space used by PCI memory space
commands, but is further specified by the graphics address re-mapping table (GART) of the
north brid ge component.
♦ Data transactions on the AGP bus involve eight bytes or multiples of eight bytes. The AGP
memory addressing protocol uses 8-byte boundaries as opposed to PCI’s 4-byte boundaries. If
a transfer of less than eight bytes is needed, the remaining bytes are filled with arbitrary data
that is discarded by the target.
♦ Pipelined requests are defined by length or size on the AGP bus. The PCI bus defines transfer
lengths with the FRAME- signal.
There are two basic types of transactions on the AGP bus: data requests (addressing) and data
transfers. These actions are separate from each other.
Compaq Deskpro EXS and Workstation 300 Personal Computers
4-10
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
4.3.1.1 Data Request
Requesting data is accomplished in one of two ways; either multiplexed addressing (using the AD
lines for addressing/data) or demultiplexed (“sideband”) addressing (using the SBA lines for
addressing only and the AD lines for data only). Even though there are only eight SBA li nes (as
opposed to the 32 AD lines) sideband addressing maximizes efficiency and throughput by allowing
the AD lines to be exclusively used for data transfers. Sideband addressing occurs at the same rate
(1X, 2X, or 4X) as data transfers. The differences in rates will be discussed in the next section
describing data transfers. Note also that sideband addressing is limited to 48 bits (address bits 4863 are assumed zero). The MCH component supports both SBA and AD addressing , but the
method and rate is selected by the AGP graphics adapter.
4.3.1.2 Data Transfers
Data transfers use the AD lines and occur as the result of data requests described previously. Each
transaction resulting from a request involves at least eight bytes, requiring the 32 AD lines to
handle at least two transfers per request. The 82850 MCH supports three transfer rates: 1X, 2X,
and 4X. Regardless of the rate used, the speed of the bus clock is constant at 66 MHz. The
following subsections describe how the use of additional strobe signals makes possible higher
transfer rates.
Technical Reference Guide
NOTE: These systems support only 1.5-volt signaling on the AGP bus.
AGP 1X Transfers
During a AGP 1X transfer the 66-MHz CLK signal is used to qualify the control and data signals.
Each 4-byte data transfer is synchronous with one CLK cycle so it takes two CLK cycles for a
minimum 8-byte transfer (Figure 4-5 shows two 8-byte transfers). The GNT- and TRDY- signals
retain their traditional PCI functions. The ST0..3 signals are used for priority encoding, with “000”
for low priority and “001” indicating high priority.
T1T2T3T4T5T6T7
CLK
AD
GNT-
TRDY-
ST0..2
00x
D1AD2AD2BD1B
xxx
xxx
xxx
xxx
xxx
Figure 4-5. AGP 1X Data Transfer (Peak Transfer Rate: 266 MB/s)
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
4-11
Chapter 4 System Support
AGP 2X Transfers
During AGP 2X transfers, clocking is basically the same as in 1X transfers except that the 66-MHz
CLK signal is used to qualify only the control signals. The data bytes are latched by an additional
strobe (AD_STBx) signal so that an 8-byte transfer occurs in one CLK cycle (Figure 4-6). The first
four bytes (DnA) are latched by the receiving agent on the falling edge of AD_STBx and the
second four bytes (DnB) are l atched on the ri sing edge of AD_STBx.
T1T2T3T4T5T6T7
CLK
AD
AD_STBx
GNT-
TRDY-
ST0..2
00x
D1BD2BD3B D4A D4B
D1AD2AD3A
xxx
xxx
xxx
xxx
xxx
Figure 4-6. AGP 2X Data Transfer (Peak Transfer Rate: 532 MB/s)
AGP 4X Transfers
The AGP 4X transfer rate allows sixteen bytes of data to be transferred in one clock cycle. As in
2X transfers the 66-MHz CLK signal is used only for qualifying control signals while strobe
signals are used to latch each 4-byte transfer on the AD lines. As shown in Figure 4-7, 4-byte block
DnA is latched by the falling edge of AD_STBx while DnB is latched by the falling edge of
AD_STBx-.
T1T2T3
CLK
T4
AD
AD_STBx
AD_STBx-
ST0..2
D1AD2AD3AD1BD2BD3B D4A D4B
00xxxxxxxxxx
Figure 4-7. AGP 4X Data Transfer (Peak Transfer Rate: 1064 MB/s)
Compaq Deskpro EXS and Workstation 300 Personal Computers
4-12
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
4.3.2 AGP CONFIGURATION
AGP bus operations require the configuration of certain parameters involving system memory
access by the AGP graphics adapter. The AGP bus interface is configured as a PCI device
integrated within the north bridge (MCH, device 1) component. The AGP function is, from the PCI
bus perspec tive, treated essentially as a PCI/PCI brid ge and configured through PCI configuration
registers (Table 4-6). Configuration is accomplished by BIOS during POST.
NOTE: Configuration of the AGP bus interface involves functions 0 and 1 of the MCH.
Function 0 registers (listed in Table 3-4) include functions that affect basic control
(GART) of the AGP.
Table 4-5. PCI/AGP Bridge Configuration Registers (MCH, Function 1)
PCI/AGP Bridge Function Configuration Registers
PCI
Config.
Addr.Register
00, 01hVendor ID8086h1BhSec. Master Latency Ti mer00h
02, 03hDevice ID2532h1ChI/O Base A ddressF0h
04, 05hCommand0000h1DhI/O Limit Address00h
06, 07hStatus0020h1E, 1FhSec. PCI/PCI Status02A0h
08hRevision ID00h20, 21hMemory Base AddressFFF0h
0A, 0BhClass Code0406h22, 23hMemory Limit Address0000h
0EhHeader Type01h24, 25hPrefetch Mem. Base Addr.FFF0h
18hPrimary Bus Number00h26, 27hPrefetch Mem. Limi t Addr.0000h
19hSecondary Bus Number00h3EhPCI / PCI Bridge Control00h
1AhS ubordi nate Bus Number00h3F-FFhReserved00h
Table 4-5.
(MCH, Function 1)
PCI
Reset
Value
Config.
Addr.Register
Technical Reference Guide
Reset
Value
NOTE:
Assume unmark ed l ocations/gaps as reserved. Refer to Intel documentat i on for detailed
register descriptions.
The AGP graphics adapter (actually its resident controller) is configured as a standard PCI device.
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
4-13
Chapter 4 System Support
A
4.3.3 AGP CONNECTOR
B94
A94
B1
1
A41A46
B41B46
A66
Figure 4-8. 1.5-Volt AGP Bus Connector
Table 4-6. AGP Bus Connector Pinout
Table 4-6.
AGP Bus Connector Pinout
PinA SignalB SignalPinA SignalB SignalPinA SignalB Signal
NC = Not connected
VDDQ = 1.5 VDC, as determined by system board grounding of Type Det- si gnal (pi n A 02).
B66
Compaq Deskpro EXS and Workstation 300 Personal Computers
4-14
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
4.4 SYSTEM RESOURCES
This section describes the availability and basic control of major subsystems, otherwise known as
resource allocation or simply “system resources.” System resources are provided on a priority
basis through hardware interrupts and DMA requests and grants.
4.4.1 INTERRUPTS
The microprocessor uses two types of hardware interrupts; maskable and nonmaskable. A
maskable interrupt can be enabled or disabled within the microprocessor by the use of the STI and
CLI instructions. A nonmaskable interrupt cannot be masked off within the microprocessor,
although it may be inhibited by hardware or software means external to t he microprocessor.
4.4.1.1 Maskable Interrupts
The maskable interrupt is a hardware-generated signal used by peripheral functions within the
system to get the attention of the microprocessor. Peripheral functions produce a unique INTA-H
(PCI) or IRQ0-15 (ISA) signal that is routed to interrupt processing logic that asserts the interrupt
(INTR-) input to the microprocessor. The microprocessor halts execution to determine the source
of the interrupt and then services the peripheral as appropriate. Figure 4-9 shows the routing of
PCI and ISA interrupts. Most I R Qs are routed t hrough the I/O cont roller, which contains a
serializing function. A serialized interrupt stream is applied to the 82801 ICH.
The 82801 ICH2 component can be configured (through the Setup utility) to handle interrupts in
one of two modes of operation:
♦ 8259 mode
♦ APIC mode
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
Microprocessor
4-15
First Edition - December 2000
Chapter 4 System Support
8259 Mode
In 8259-Mode, interrupts IRQ0-IRQ15 are handled in the conventional (AT-system) method using
logic that is the equivalent of two 8259 interrupt controllers. Table 4-7 lists the standard source
configuration for maskable interrupts and their priorities in 8259 mode. If more than one interrupt
is pending, the highest priority (lowest number) is processed first.
Table 4-7. Maskable Interrupt Priorities and Assignments
PrioritySignal LabelSource (Typical)
1IRQ0Interval timer 1, counter 0
2IRQ1Keyboard
3I RQ8-Real-time c l ock
4IRQ9Microtower, game/MIDI port; desk top or minitower, unused.
5IRQ10Unused
6IRQ11Unused
7IRQ12Mouse
8IRQ13Coprocessor (mat h)
9IRQ14IDE primary I/F
10IRQ15IDE secondary I/F
11IRQ3Serial port (COM2)
12IRQ4Serial port (COM1)
13IRQ5Unused
14IRQ6Diskett e dri ve controller
15IRQ7Parallel port (LPT 1)
--IRQ2NOT AVAILABLE (Cascade from interrupt controller 2)
Table 4-7.
Maskable Interrupt Priorities and Assignments
APIC Mode
The Advanced Programmable Interrupt Controller (APIC) mode enhances interrupt-processing
performance with the following advantages:
♦ Eliminating the processor’s interrupt acknowledge cycle by using a separate APIC bus.
♦ Programmable interrupt priority.
♦ Additional interrupts (total of 24).
Eight PCI interrupts are available in APIC mode. The PCI interrupts are evenly distributed to
minimize latency and are hard-wired as follows:
Compaq Deskpro EXS and Workstation 300 Personal Computers
4-16
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
Technical Reference Guide
NOTE: The APIC mode is supported by Windows NT/2000 operating systems. Systems
using the Windows 95 or 98 operating system will need to run in 8259 mode. The mode is
selectable through the Setup utility (access with F10 key during boot sequence).
Maskable Interrupt proc essing is controlled and monitored through standar d AT-type I/O-mapped
registers. These registers are listed in Table 4-8.
Table 4-8. Maskable Interrupt Control Registers
Table 4-8.
Maskable Interrupt Control Registers
I/O PortRegister
020hBase Addres s, Int. Cntlr. 1
021hInitiali zat i on Command Word 2-4, Int. Cntlr. 1
0A0hBase Address, Int. Cntlr. 2
0A1hInitiali zat i on Command Word 2-4, Int. Cntlr. 2
The initialization and operation of the interrupt control registers follows standard AT-type
protocol.
4.4.1.2 Non-Maskable Interrupts
Non-maskable interrupts cannot be masked (inhibited) within the microprocessor itself but may be
maskable by software using logic external to the microprocessor. There are two non-maskable
interrupt signals: the NMI- and the SMI-. These signals have service priority over all maskable
interrupts, with the SMI- having top priority over all interrupts including the NMI-.
NMI- Generation
The Non-Maskable Interrupt (NMI-) signal can be generated by one of the following actions:
♦ Parity errors detected on a PCI bus (activating SERR- or PERR-).
♦ Microprocessor internal error (activating IERRA or IERRB)
The SERR- and P ERR- signals are rout ed through the ICH c omponent, which in turn activa tes the
NMI to the microprocessor.
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
4-17
Chapter 4 System Support
The NMI Status Register at I/O port 061h contains NMI source and status data as follows:
NMI Status Register 61h
BitFunction
7NMI Status:
0 = No NMI from system board pari ty error.
1 = NMI requested, read only
6IOCHK- NMI:
0 = No NMI from IOCHK-
1 = IOCHK- is active (low), NMI requested, read only
5Interval Timer 1, Counter 2 (Speaker) Status
4Refresh Indicator (toggles with every ref resh)
3IOCHK- NMI Enable/Disable:
0 = NMI from IOCHK- enabled
1 = NMI from IOCHK- disabled and c l eared (R/W)
2System Board Parity Error (PERR/SERR) NMI Enable:
0 = Parity error NMI enabled
1 = Parity error NMI disabled and cleared (R/W)
1Speaker Data (R/W)
0Inteval Timer 1, Counter 2 Gate Signal (R/W)
0 = Counter 2 disabled
1 = Counter 2 enabled
Functions not related to NMI activity.
After the active NMI has been processed, status bits <7> or <6> are cleared by pulsing bits <2> or
<3> respectively.
The NMI Enable Register (070h, <7>) is used to enable/disable the NMI signal. Writing 80h to
this register masks generation of the NMI-. Note that the lower six bits of register at I/O port 70h
affect RTC operation and should be considered when changing NMI- generation status.
SMI- Generation
The SMI- (System Management Interrupt) is typically used for power management functions.
When power management is enabled, inactivity timers are monitored. When a timer times out,
SMI- is asserted and invokes the microprocessor’s SMI handler. The SMI- handler works with the
APM BIOS to service the SMI- according to the cause of the timeout.
Although the SMI- is primarily used for power managment the interrupt is also employed for t he
QuickLock/QuickBlank functions as well.
Compaq Deskpro EXS and Workstation 300 Personal Computers
4-18
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
4.4.2 DIRECT MEMORY ACCESS
Direct Memory Access (DMA) is a method by which a device accesses system memory without
involving the microprocesso r. Although the DMA method has been traditionally used to transfer
blocks of data to or from an ISA I/O device, PCI devices may also use DMA operation as well.
The DMA method reduces the amount of CPU interactions with memory, freeing the CPU for
other proce ssing tasks.
NOTE: This section describes DMA in general. For detailed information regarding
DMA operation, refer to the data manual for the Intel 82801BA I/O Controller Hub.
The 82801 ICH2 component includes the equivalent of two 8237 DMA controllers cascaded
together to provide eight DMA channels, each (excepting channel 4) configurable to a specific
device. Table 4-9 lists the default configuration of the DMA channels.
Table 4-9. Default DMA Channel Assignments And Register I/O Ports
All channels in DMA controller 1 operate at a higher priority than those in controller 2. Note that
channel 4 is not available for use other than its cascading function for controller 1. The DMA
controller 2 can transfer words only on an even address boundary. The DMA controller and page
register define a 24-bit address that allows data transfers within the address space of the CPU.
In addition to device configuratio n, each channel can be configured (through PCI Configuration
Registers) for one of two modes of operation:
♦ LPC DMA Mode - Uses the LPC bus to communicate DMA channel control and is
implemented for d evices using DMA through the I/O controller such as the d iskette drive
controller.
♦ PC/PCI DMA Mode - Uses the REQ#/GNT# signals to communicate DMA channel control
and is used by PCI expansion devices.
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
4-19
Chapter 4 System Support
CMOS
4.5 SYSTEM CLOCK DISTRIBUTION
These systems use an Intel CK-type clock generator and crystal for generating the clock signals
required by the system board components. Table 4-10 lists the system board clock signals and how
they are distributed.
Certain clock outputs are turned off during reduced power modes to conserve energy. Clock output
control is handled through the SMBus interface by BIOS.
4.6 REAL-TIME CLOCK AND CONFIGURATION MEMORY
The Real-time clock (RTC) and configuration memory (also referred to as “CMOS”) functions are
provided by the 82801 ICH component and is MC146818-compatible. As shown in the following
figure, the 82801 ICH component provides 256 bytes of battery-backed RAM divided into two
128-byte configuration memory areas. The RTC uses the first 14 bytes (00-0Dh) of the standard
memory area. All locations of the standard memory area (00-7Fh) can be directly accessed using
conventional OUT and IN asse mbl y language instructions thr ough I/O ports 70h/71h, alt hough the
suggested method is to use the INT15 AX=E823h BIOS call.
0Dh
0Ch
0Bh
0Ah
09h
08h
07h
06h
05h
04h
03h
02h
01h
00h
Register D
Register C
Register B
Register A
Date of Month
Day of Week
Hours (Alarm)
Hours (Timer)
Minutes (Alarm)
Minutes (Timer)
Seconds (Alarm)
Seconds (Timer)
Year
Month
82801
Extended Config.
Memory Area
(128 bytes)
Standard Config.
Memory Area
(114 bytes)
RTC Area
(14 bytes)
FFh
80h
7Fh
0Eh
0Dh
00h
Figure 4-10. Configuration Memory Map
A lithium 3-VDC battery is used for maintaining the RTC and configuration memory while the
system is powered down. The battery is located in a battery holder on the system board is replaced
with a Renata CR2032 or equivalent 3-VDC lithium battery.
Compaq Deskpro EXS and Workstation 300 Personal Computers
4-20
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
4.6.1 CLEARING CMOS
The contents of configuration memory (including the Power-On Password) can be cleared by the
following proc edures:
1. Turn off the unit.
2. Disconnect the AC power cord from the outlet and/or system unit.
3. Remove the chassis hood (cover) and insure that no LEDs on the system board are
illuminated.
4. Press and release the CMOS clear button on the system board.
5. Replace the chassis hood (cover).
6. Reconnect the AC power cord to the outlet and/or system unit.
7. Turn the unit on.
To clear only the Power-On Password refer to section 4.7.1.1.
Technical Reference Guide
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
4-21
Chapter 4 System Support
4.6.2 CMOS ARCHIVE AND RESTORE
During the boot sequence the BIOS saves a copy of NVRAM (CMOS contents, password(s) and
other system variables) in a portion of the flash ROM. Should the system become un-usable, the
last good copy of NVRAM data can be restored with the Power Button Override function. This
function is invoked with the following procedure:
1. With the unit powered down, press and release the power button.
2. Immediately after releasing the power button in step 1, press and hold the power button until
the unit powers down. This action will be recorded as a Power Button Override event.
With the next startup sequence the BIOS will detect the occurrence of the Power Button Override
event and will load the backup copy of NVRAM from the ROM to the CMOS.
NOTE: The Power Button Override feature does not allow quick cycling of the system
(turning on then off). If the power cord is disconnected during the POST routine, the
splash screen image may become corrupted, requiring a re-flashing of the ROM (refer to
chapter 8, BIOS ROM).
4.6.3 STANDARD CMOS LOCATIONS
Table 4-14 and the following paragraphs describe standard configuration memory locations 0Ah3Fh. These locations are accessible using OUT/IN assembly language instructions using port
70/71h or BIOS function INT15, AX=E823h.
Table 4-11. Configuration Memory (CMOS) Map
Configuration Memory (CMOS) Map
LocationFunctionLocationFunction
00-0DhReal -t i me clock24hS ys tem board ID
0EhDiagnostic status25hSystem architecture data
0FhSystem reset c ode26hAuxiliary peripheral configuration
10hDi skette drive type27hSpeed control external drive
11hReserved28hExpanded/base mem . size, IRQ12
12hHard dri ve t ype29hMiscellaneous configuration
13hS ecurity functions2AhHard drive timeout
14hEquipment installed2BhSystem inactivity t i meout
15hBase memory size, low byte/KB2ChMonitor timeout, Num Lock Cntrl
16hBase memory size, hi gh byte/KB2DhAdditional flags
17hE xtended memory, low byte/KB2Eh-2FhChecksum of locations 10h-2Dh
18hE xtended memory, high byte/KB30h-31hTotal extended memory tested
19hHard dri ve 1, pri mary controller32hCentury
1AhHard drive 2, primary controller33hMiscellaneous flags set by BIOS
1BhHard drive 1, secondary controller34hInternat i onal l anguage
1ChHard drive 2, secondary c ontroller35hAPM status flags
1DhEnhanced hard drive support36hECC POST test single bit
1EhReserved37h-3FhPower-on password
1FhPower management functions40-FFhFeature Control /Status
NOTES:
Assume unmark ed gaps are reserved.
Table 4-11.
Compaq Deskpro EXS and Workstation 300 Personal Computers
4-22
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
RTC Control Register A, Byte 0Ah
BitFunction
7Update in Progress. Read only.
0 = Time update will not occur before 2444 us
1 = Time update will occur within 2444 us
6..4Divider Chain Control. R/W.
00x = Oscillator disabled.
010 = Normal operation (time base frequency = 32.768 KHz).
11x = Divider chain reset.
3..0Periodic Interrupt Control. R/W. Specifies the periodic i nterrupt interval.
0000 = none 1000 = 3.90625 ms
0001 = 3.90625 ms 1001 = 7.8125 ms
0010 = 7.8125 ms 1010 = 15. 625 ms
0011 = 122.070 us 1011 = 31.25 ms
0100 = 244.141 us 1100 = 62.50 ms
0101 = 488.281 us 1101 = 125 ms
0110 = 976.562 us 1110 = 250 ms
0111 = 1.953125 ms 1111 = 500 ms
RTC Control Register B, Byte 0Bh
BitFunction
7Time Update Enable/disable
0 = Normal operation, 1 = Disable t i me updating for time set
6Periodic Interrupt Enable/Dis abl e.
0 = Disable, 1 = Enable interval specified by Register A
Sunday in April, retreat 1 hour on las t Sunday in
Technical Reference Guide
RTC Status Register C, Byte 0Ch
BitFunction
7If set, interrupt output signal active (read only)
6If set, indicates periodi c interrupt flag
5If set, indicates al arm interrupt
4If set, indicates end-of -update interrupt
3..0Reserved
RTC Status Register D, Byte 0Dh
BitFunction
7RTC Power Status
0 = RTC has lost power
1 = RTC has not lost power
6..0Reserved
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
4-23
Chapter 4 System Support
Configuration Byte 0Eh, Diag nostic Status
Default Value = 00h
This byte contai ns diagnostic status d ata.
Configuration Byte 0Fh, System Reset Code
Default Value = 00h
This byte contains the system reset code.
Configuration Byte 10 h, Diskette Driv e Type
BitFunction
7..4Primary (Drive A) Diskette Drive Type
3..0Secondary (Drive B) Diskette Drive Type
Valid values for bits <7..4> and bits <3..0>:
0010 = 1.2-MB drive
0011 = 720-KB drive
0110 = 2.88-MB drive
(all other values reserved)
0000 = Not installed
0001 = 360-KB drive
0100 = 1.44-MB/1.25-MB drive
Configuration Byte 12h, Hard Drive Type
BitFunction
7..4Primary Controller 1, Hard Drive 1 Type:
0000 = none 1000 = Type 8
0001 = Type 1 1001 = Type 9
0010 = Type 2 1010 = Type 10
0011 = Type 3 1011 = Type 11
0100 = Type 4 1100 = Type 12
0101 = Type 5 1101 = Type 13
0110 = Type 6 1110 = Type 14
0111 = Type 7 1111 = other (use bytes 19h)
3..0Primary Controller 1, Hard Drive 2 Type:
0000 = none 1000 = Type 8
0001 = Type 1 1001 = Type 9
0010 = Type 2 1010 = Type 10
0011 = Type 3 1011 = Type 11
0100 = Type 4 1100 = Type 12
0101 = Type 5 1101 = Type 13
0110 = Type 6 1110 = Type 14
0111 = Type 7 1111 = other (use bytes 1Ah)
Compaq Deskpro EXS and Workstation 300 Personal Computers
0 = Coprocessor not installed
1 = Coprocessor installed
0Diskette Drives Present
0 = No diskette drives inst al l ed
1 = Diskette drive(s) inst al l ed
Configuration Bytes 15h and 16h, Base Memory Size
Default Value = 280h
Bytes 15h and 16h hold a 16-bit value that specifies the base memory size in 1-KB (1024)
increments. Valid base memory sizes are 512 and 640 kilobytes .
Configuration Bytes 17h and 18h, Extended Memory Size
Bytes 17h and 18h hold a 16-bit value that specifies the extended memory size in 1-KB
increments.
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
4-25
Chapter 4 System Support
Configuration Bytes 19 h- 1Ch, Hard Drive Types
Byte 19h contains the hard drive type for drive 1 of the primary controller if byte 12h bits <7..4>
hold 1111b. Byte 1Ah contains the hard drive type for drive 2 of the primary controller if byte 12h
bits <3..0> hold 1111b. Bytes1Bh and 1Ch contain the hard drive types for hard drives 1 and 2 of
the secondary controller.
Configuration Byte 1Dh, Enhanced IDE Hard Drive Support
Default Value = F0h
BitFunction
7EIDE - Drive C (83h)
6EIDE - Drive D (82h)
5EIDE - Drive E (81h)
4EIDE - Drive F (80h)
3..0Reserved
Values for bits <7..4> :
0 = Disable
1 = Enable for auto-configure
Configuration Byte 1Fh, Power Management Functions
Default Value = 00h
BitFunction
7..4Reserved
3Slow Processor Clock for Low Power Mode
0 = Processor runs at full speed
1 = Processor runs at slow speed
2Reserved
1Monitor Off Mode
0 = Turn monitor power off after 45 mi nutes in
standby
1 = Leave monitor power on
0Energy Saver Mode Indicator (Blinking LED)
0 = Disable
1 = Enable
Configuration Byte 24 h, Sy stem Board Identification
Default Value = 7Eh
Configuration memory location 24h holds the system board ID.
0Row 0 Error Detect
0 = No single bit error detected.
1 = Single bit error detected.
Configuration Byte 37h-3Fh, Power-On Password
These eight locations hold the power-on password.
Compaq Deskpro EXS and Workstation 300 Personal Computers
4-30
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
4.7 SYSTEM MANAGEMENT
This section describes functi ons having to do with secur ity, power management, temperature, and
overall status. These functions are handled by hardware and firmware (BIOS) and generally
configured through the Setup utility.
4.7.1 SECURITY FUNCTIONS
These systems include various features that provide different levels of security. Note that this
subsection describes only the hardware functionality (including that supported by Setup) and
does not describe security features that may be provided by the operating system and application
software.
4.7.1.1 Power-On Password
These systems include a power-on password, which may be enabled or disabled (cleared) through
a jumper on the system board. The jumper controls a GPIO input to the 82801 ICH that is checked
during POST. The password is stored in configuration memory (CMOS) and if enabled and then
forgotten by the user will require that either the password be cleared (preferable solution and
described below) or the entire CMOS be cleared (refer to section 4.6).
Technical Reference Guide
To clear the password, use the following procedure:
1. Turn off the system and disconnect the AC power cord from the outlet and/or system unit.
2. Remove the cover (hood). Insure that all system board LEDs are off (not illuminated).
3. Locate the password header/jumper (labeled E49 on these systems) and remove the jumper
from pins 1 and 2 and place on (just) pin 2 (for safekeeping).
4. Replace the cover.
5. Re-connect the AC power cord to the AC outlet and/or system unit.
6. Turn on the system. The POST routine will clear and disable the password.
7. To re-enable the password feature, repeat steps 1-6, replacing the jumper on pins 1 and 2 of
header E49.
4.7.1.2 Setup Password
The Setup utility may be configured to be always changeable or changeable only by entering a
password. The password is held on CMOS and, if forgotten, will require that CMOS be cleared
(refer to section 4.6).
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
4-31
Chapter 4 System Support
4.7.1.3 Cable Lock Provision
These systems include a chassis cutout (on the rear panel) for the attachment of a cable lock
mechanism.
4.7.1.4 I/O Interface Security
The serial, parallel, USB, and diskette interfaces may be disabled individually through the Setup
utility to guard against unauthorized access to a system. In addition, the ability to write to or boot
from a removable med ia drive (such as t he diskette dri ve) may be enabled through the Setup
utility. The disabling of the serial, parallel, and diskette interfaces are a function of the
LPC47B357 I/O controller. The USB ports are controlled through the 82801 ICH.
4.7.2 POWER MANAGEMENT
These systems provide baseline hardware support of ACPI- and APM-compliant firmware and
software. Key power-consuming components (processor, chipset, I/O controller, and fan) can be
placed into a reduced power mode either automatically or by user control. The system can then be
brought bac k up (“wake-up”) by events defined by the ACP I specificati on. The ACPI wake-up
events supported by this system are listed as follows:
ACPI Wake-Up EventS ystem Wakes From
Power ButtonSuspend or soft-off
RTC AlarmSuspend or soft-off
Wake On LAN (w/NIC)Suspend or soft-off
PMESuspend or soft-off
Serial Port RingSuspend or soft-off
USBSuspend only
KeyboardSuspend only
MouseSuspend only
Compaq Deskpro EXS and Workstation 300 Personal Computers
4-32
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
4.7.3 SYSTEM STATUS
These systems provide a visual indication of system boot and ROM flash status through the
keyboard LEDs as listed in table 4-12.
NOTE: The LED indications listed in Table 4-12 are valid only for PS/2-type
keyboards. A USB keyboard will not provide LED status for the listed events, although
audible (beep) indications will occur.
Table 4-12. System Boot/ROM Flash Status LED Indications
System Boot/ROM Flash Status LED Indications
Event
System memory failure [1]BlinkingOffOff
Graphics controller failure [2]OffBlinkingOff
System failure prior t o graphi cs cntlr. initiali zat i on [ 3]OffOffBlinking
ROMPAQ diskette not present , faulty, or drive prob.OnOffOff
Password promptOffOnOff
Invalid ROM detected - flash fai l e dBlinking [4]Blinking [4]Blinking [4]
Keyboard locked in network modeB l i nking [5]Blinking [5]Blinking [5]
Successful boot bl ock ROM flashOn [ 6]On [6]On [6]
NOTES:
[1] Accompanied by 1 short, 2 long audio beeps
[2] Accompanied by 1 l ong, 2 short audio beeps
[3] Accompanied by 2 l ong, 1 short audio beeps
[4] All LEDs will blink in sync twice, accompanied by 1 long and three short audio beeps
[5] LEDs will blink in sequence (NUM Lock, then CA P s Lock, then Scroll Lock)
[6] Accompanied by ri sing audio tone.
Table 4-12.
NUM Lock
LED
Technical Reference Guide
CAPs Lock
LED
Scroll Lock
LED
Table 4-13 lists the operation status codes provided by the power LED on the front of the chassis.
Note that error or problem conditions are reported only by the power LED on the minitower.
Table 4-13. System Operational Status LED Indications
Table 4-13.
System Operational Status LED Indications
System Status
S0: System on (normal operation)Steady greenSteady green
S1: SuspendBlinks green @ 1 HzBlinks green @ 1 Hz
S3: Suspend to RAMBlinks green @ 1 HzBl i nks green @ 1 Hz
S4: Suspend to diskBlinks green @ 0.5 HzBlinks green @ 0.5 Hz
S5: Soft offOff - clearOff - clear
Processor not seatedOff - c l earSteady red
CPU thermal shutdownOff - clearBlinks red @ 4 Hz
ROM errorOff - clearBlinks red @ 1 Hz
Power supply crowbar activatedOff - clearBlinks red @ .5 Hz
System offOff - clearOff
Desktop
Power LED
Minitower
Power LED
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
4-33
First Edition - December 2000
Chapter 4 System Support
4.7.4 TEMPERATURE SENSING AND COOLING
These systems feature a fan integrated into the power supply assembly. A separate chassis fan is
also employed. Both fans are variable-speed type, and typically operate in tandem as long as the
power supply is active (producing 12 VDC). The fans are off in S3 (Suspend-to-RAM) and S5
(Soft-Off) states.
NOTE: These systems are designed to provide optimum cooling with the cover in place.
Operating a system with the cover removed may result in a thermal condition of system
board components, including the processor.
Figure 4-11 shows the fan c ontrol schematic.
Chassis Fan
Header P8
(+)
P1
24
12
8
(-)
Fan
Off
ICH2
SMBus
Processor
Sensing
ASIC
Fan
Sense [1]
Fan CMD
Fan Off-
Therm-
CH Fan CMD
On/Off
Control
82801
ICH2
4
4
3
3
2
2
Power Supply Assembly
Speed
Control
(+)
(-)
PS Fan
CMD
On/Off
Control
PS Fan
(-)
(+)
NOTE:
[1] Will be +12 VDC if c hassis fan is connected and operat ing.
Figure 4-11. Fan Control Block Diagram
An ASIC monitors a thermal diode internal to the processor and provides a Fan CMD signal that
the Speed Control logic of the power supply uses to var y the speed of the fans thr ough the negative
power rail. The turning off of the fans as the result from the system being placed into a Sleep
condition is initiated by the ASIC asserting the Fan Off- signal, which results in the On/Off Control
logic shutting off the +12 volts to the fans.
Typical cooling conditions include the following:
1. Normal – Low fan speed.
2. Hot processor – ASIC directs Speed Control logic to increase speed of fan(s).
3. Hot power supply – Power supply increases speed of fan(s).
4. Sleep state – Fans turned off. Hot processor or power supply will result in starting fans.
Compaq Deskpro EXS and Workstation 300 Personal Computers
4-34
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
Technical Reference Guide
4.8 REGISTER MAP AND MISCELLANEOUS FUNCTIONS
This section contains the system I/O map and information on general-purpose functions of the ICH
and I/O controller.
4.8.1 SYSTEM I/O MAP
Table 4-14 lists the fixed addresses of the input/output (I/O) ports.
Table 4-14. System I/O Map
Table 4-14.
System I/O Map
I/O PortFunction
0000..001FhDMA Controller 1
0020..002DhInterrupt Controll er 1
002E, 002FhIndex, Data Ports to LPC47B357 I/O Controller (primary)
0030..003DhInterrupt Controll er
0040..0042hTimer 1
004E, 004FhIndex, Data Ports to LPC47B357 I/O Controller (secondary)
0170..0177hIDE Controller 2 (active only if standard I/ O space is enabled for primary drive)
01F0..01F7hIDE Controller 1 (active only if standard I/O space is enabled for secondary drive)
0278..027FhParallel Port (LPT 2)
02E8..02EFhSerial Port (COM4)
02F8..02FFhSerial Port (COM2)
0370..0377hDiskette Drive Controller Secondary Address
0376hIDE Controller 2 (active only if standard I/O space is enabled for prim ary dri ve)
0378..037FhParallel Port (LPT 1)
03B0..03DFhGraphics Controller
03BC..03BEhParallel Port (LPT3)
03E8..03EFhSerial Port (COM3)
03F0..03F5hDi skette Drive Controller Primary Addresses
03F6hIDE Controller 1 (act i ve onl y i f standard I/O space is enabled f or sec. drive)
03F8..03FFhSerial Port (COM1)
04D0, 04D1hInterrupt Controller
0678..067FhParallel Port (LPT 2)
0778..077FhParallel Port (LPT 1)
07BC..07BEhParallel Port (LPT3)
0CF8hPCI Configuration Address (dword access onl y )
0CF9hReset Control Register
0CFChPCI Configuration Data (byte, word, or dword acces s)
NOTE:
Assume unmark ed gaps are unused, reserved, or used by functions that employ variable I /O
address mapping. Some ranges may include reserved addres ses.
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
4-35
Chapter 4 System Support
4.8.2 82801 ICH GENERAL PURPOSE FUNCTIONS
The 82801 ICH2 component includes a number of single and multi-purpose pins available as
general-purpose input/output (GPIO) ports. The GPIO ports are configured (enabled/disabled)
during POST by BIOS through the PCI configuratio n registers of the ICH ’s LPC I/F Bridge
(82801, function 0). The GPIO ports are controlled through 64 bytes of I/O space that is mapped
during POST.
Table 4-15 lists the utilization of the ICH’s GPIO ports in the desktop and minitower systems.
Table 4-15. 82801 ICH GPIO Register Utilization (Desktop and Minitower only)
Compaq Deskpro EXS and Workstation 300 Personal Computers
4-36
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
4.8.3 I/O CONTROLLER FUNCTIONS
The I/O controller (used in desktop and minitower systems) contains various functions such as the
keyboard/mouse interfaces, diskette interface, serial interfaces, and parallel interface. While the
control of these interfaces uses standard AT-type I/O addressing (as described in chapter 5) the
configuration of these functions o ccurs through indexed ports using PnP protocol. In these
systems, hardware strapping selects I/O addresses 02Eh/02Fh at reset as the Index/Data ports for
accessing the logical devices within the I/O contoller. Table 4-16 lists the PnP control registers for
the LPC47B357.
Table 4-16 LPC47B357 Control Registers
Table 4-16.
I/O Controller Control Registers
IndexFunctionReset Value
02hConfiguration Cont rol00h
03hReserved
07hLogical Devic e (Interface) Select:
0Bh = Rsvd
20hSuper I/O ID Regi ster (SID)56H
21hRevision-22hLogical Devic e Power Control00h
23hLogical Devic e P ower Management00h
24hPLL / Oscillator Control04h
25-2FhDevice specific [2]--
NOTES:
Refer to LPC47B357 data sheet for detailed register informat i on.
Technical Reference Guide
00h
The configuration registers are accessed through I/O registers 2Eh (index) and 2Fh (data) after the
configuration phase has been activated by writing 55h once to I/O port 2Eh. The BIOS then
initiates each logical device and then deactivates the configuration phase by writing AAh to 2Eh.
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
4-37
Chapter 4 System Support
4.8.3.1 LPC47B357 GPIO Utilization
The LPC47B357 I/O Controller (used in desktop and minitower systems) provides 62 generalpurpose pins that can be individually configured for specific purposes. These pins are configured
through the Runtime registers (logical device 0Ah) during t he system’s configuration phas e of the
boot sequence by the BIOS.
Table 4-17 lists the GPIO registers for the LPC47B357. Note that not all ports are listed as this
table defines only the custom implementation of GPIO ports. Refer to SMC documentation for
standard usage of unlisted GPIO ports.
Table 4-17. LPC47B357 GPIO Register Utilization (Desktop and Minitower only)
LPC47B357 GPIO Port Utilization
GPIOFunctionDirectionGPIOFunctionDirection
10Board rev 1I42ICH SCIO
11Board rev 0I43--NC
12--NC44Hood LockNC
13PME-I45Hood UnlockNC
14WOLNC46ICH SMI-O
15System I D 4 [ 1]I60PCI Slot ResetO
16Processor Fan senseI61AGP S l ot ResetO
17--NC62PWR Button InI
20Pri. IDE 80-pin Cable DetectI63SLP S3I
21Sec. IDE 80-pin Cabl e DetectI64SLP S5I
22--NC65CPU Changed/RemovedO
23System I D 2 [ 1]I66PWR Button OutO
24BIOS fail for AOLO67PS OnO
25System I D 3 [ 1]I70Remote OffI
26Processor PresentI71System ID 0 [1]NC
27--NC72System ID 1 [1]NC
30PS LED Color GrnO73--NC
31PS LED BlinkO74--NC
32Thermal TripI75--NC
332 MB Media IDI76--NC
34FWH Write ProtectO85Pwr SELO
35FWH ResetO86S3 3.3 VDC OnO
36Diskette Mot or BO-----37Diskette Select BO------
NOTE:
NC = Not connected (not used).
[1] System ID (I D4..0) value for these systems = 00111.
Table 4-17.
Compaq Deskpro EXS and Workstation 300 Personal Computers
The desktop and minitower systems utilize the following specialized functions built into the LPC
47B357 I/O Controller:
♦ Power/Hard drive LED control – The I/O controller provides color and blink control for the
front panel LEDs used for indicating system events as listed below:
System StatusPower LEDHD LED
S0: System on (normal operation)St eady greenGreen w/HD activity
S1: SuspendBlinks green @ 1 HzOff
S3: Suspend to RAMB l i nks green @ 1 HzOff
S4: Suspend to diskBlinks green @ 0.5 HzOff
S5: Soft offOff - clearOff
Backplane board not seatedSt eady redSteady red
Processor not seatedSteady redOff
CPU thermal shutdownBlinks red @ 4 HzOff
ROM errorBlinks red @ 1 HzOff
Power supply crowbar activatedBlinks red @ 0.5 HzOff
System offOffOff
♦ I/O security – The parallel, serial, and diskette interfaces may be disabled individually by
software and the LPC47B357’s disabling register locked. If the disabling register is locked, a
system reset through a cold boot is required to gain access to the disabling (Device Disable)
register.
♦ Processor present/speed detection – One of the battery-back general-purpose inputs (GPI26)
of the LPC47B357 detects if the processor has been removed. The occurrence of this event is
passed to the ICH that will, during the next boot sequence, initiate the speed selection routine
for the processor. The speed selection function replaces the manual DIP switch configuration
procedure required on previous systems.
♦ Legacy/ACPI power button mode control – The LPC47B357 receives the pulse signal from
the system’s power button and produces the PS On signal according to the mode (legacy or
ACPI) selected. Refer to chapter 7 for more information regarding power management.
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
4-39
Chapter 4 System Support
This page is intentionally blank.
Compaq Deskpro EXS and Workstation 300 Personal Computers
4-40
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
Chapter 5
INPUT/OUTPUT INTERFACES
5.Chapter 5 INPUT/OUTPUT INTERFACES
5.1 INTRODUCTION
This chapter describes the standard (i.e., system board) interfaces that provide input and output
(I/O) porting of data and specifically discusses interfaces that are controlled through I/O-mapped
registers. The following I/O interfaces are covered in this chapter:
♦ Enhanced IDE interface (5.2)page 5-1
♦ Diskette drive interface (5.3)page 5-4
♦ Serial interfaces (5.4)page 5-8
♦ Parallel interface (5.5)page 5-11
♦ Keyboard/pointing device interface (5.6)page 5-16
♦ Universal serial bus interface (5.7)page 5-22
♦ Audio subsystem (5.8)page 5-26
♦ Network support (5.9)page 5-33
Technical Reference Guide
5.2 ENHANCED IDE INTERFACE
The enhanced IDE (EIDE) interface consists of primary and secondary controllers integrated into
the 82801 ICH2 component of the chipset. Two 40-pin IDE connectors (one for each controller)
are included on the system board. Each controller can be configured independently for the
following modes of operation:
♦ Programmed I/O ( PIO) mode – CPU controls drive transactions through standard I/O mapped
registers of the IDE drive.
♦ 8237 DMA mode – CPU offloads drive transactions using DMA protocol with transfer rates
NOTE: These systems include 80-conductor data cables required for UATA/66 and /100
modes.
5.2.1 IDE PROGRAMMING
The IDE interface is configured as a PCI device during POST and controlled through I/O-mapped
registers at runtime.
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
5-1
Chapter 5 Input/Output Interfaces
Hard drives types not found in the ROM’s parameter table are automatically configured as to
(soft)type by DOS as follows:
Primary controller: drive 0, type 65; drive 1, type 66
Secondary controller: drive 0, type 68; drive 1, type 15
Non-DOS (non-Windows) operating systems may require using Setup (F10) for drive
configuration.
5.2.1.1 IDE Configuration Registers
The IDE controller is configured as a PCI device with bus mastering capability. The PCI
configuration registers for the IDE controller function (PCI device #31, function #1) are listed in
Table 5-1.
Table 5–1. IDE PCI Configuration Registers
00-01hVender ID8086h0F..1FhReserved0’s
02-03hDevice ID244Bh20-23hBMIDE Base Address1
04-05hPCI Command0000h2C, 2DhSubsystem Vender ID0000h
06-07hPCI Stat us0280h2E, 2FhSubs ystem ID0000h
08hRevision ID00h30..3FhReserved0’s
09hProgramming80h40-43hP ri ./Sec. IDE Timi ng0’s
0AhS ub-Cl ass01h44hSlave IDE Timi ng00h
0BhB ase Class Code01h48hSync. DMA Control00h
0DhMaster Latency Tim er00h4A -4B hS ync . DMA Timing0000h
0EhHeader Type00h54hEIDE I/O Config.Register00h
NOTE:
Assume unmark ed gaps are reserved and/or not used.
Table 5-1.
Reset
Value
PCI Conf.
Addr.Register
Reset
Value
5.2.1.2 IDE Bus Master Control Registers
The IDE interface can perform PCI bus master operations using the registers listed in Table 5-2.
These registers occupy 16 bytes of variable I/O space set by software and indicated by PCI
configuration register 20h in the previous table.
Table 5–2. IDE Bus Master Control Registers
Table 5-2.
IDE Bus Master Control Registers
I/O Addr.
Offset
00h1Bus Master IDE Command (Primary)00h
02h1Bus Master IDE Status (Primary)00h
04h4Bus Master IDE Descriptor Pointer (Pri.)0000 0000h
08h1Bus Master IDE Command (Sec ondary)00h
0Ah2Bus Master IDE Status (Secondary)00h
0Ch4Bus Master IDE Descriptor Point er (Sec.)0000 0000h
NOTE:
5-2 Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
Size
(Bytes)Register
Unspecified gaps are reserved, will return indeterminat e data, and should not be written to.
Default
Value
First Edition – December 2000
5.2.2 IDE CONNECTOR
This system uses a standard 40-pin connector for the primary IDE device and connects (via a
cable) to the hard drive installed in the right side drive bay. Note that some signals are re-defined
for UATA/33 and UATA/66 modes, which require a special 80-conductor cable (supplied)
designed to reduce cross-tal k. Device power is supplied through a separate connector.
Figure 5-1. 40-Pin Primary IDE Connector (on system board).
Table 5–3. 40-Pin Primary IDE Connector Pinout
PinSignalDescriptionPinSignalDescription
1RESE T -Reset21DRQDMA Request
2GNDGround22GNDGround
3DD7Data Bit <7>23IOW-I/O Write [1]
4DD8Dat a B i t <8>24GNDGround
5DD6Dat a B i t <6>25IOR-I/O Read [2]
6DD9Dat a B i t <9>26GNDGround
7DD5Dat a B i t <5>27IORDYI/O Channel Ready [ 3]
8DD10Data Bit <10>28CSE LCable Sel ect
9DD4Dat a B i t <4>29DAK-DMA Acknowledge
10DD11Data Bit <11>30GNDGround
11DD3Data Bit <3>31IRQnInterrupt Request [4]
12DD12Data Bit <12>32IO16-16-bit I/O
13DD2Data Bit <2>33DA1Address 1
14DD13Data Bit <13>34DSKPDIAGPass Diagnostics
15DD1Data Bit <1>35DA0Address 0
16DD14Data Bit <14>36DA2Address 2
17DD0Data Bit <0>37CS0-Chip Select
18DD15Data Bit <15>38CS1-Chip Sel ect
19GNDGround39HDACTIVE-Drive Active (f ront panel LED) [5]
20--Key40GNDGround
NOTES:
[1] On UATA/33 and higher modes, re-defined as STOP.
[2] On UATA/33 and higher mode reads , re-defined as DMARDY-.
On UATA/33 and higher mode writes, re-defi ned as STROBE.
[3] On UATA/33 and higher mode reads , re-defined as STROBE-.
On UATA/33 and higher mode writes, re-def i ned as DMARDY-.
[4] Primary connector wired to IRQ14, secondary connector wired to I RQ15.
[5] Pin 39 is used for s pi ndl e sync and drive activity (becom es SPSYNC/DACT-)
when synchronous drives are connected.
Technical Reference Guide
Table 5-3.
40-Pin Primary IDE Connector Pinout
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
5-3
Chapter 5 Input/Output Interfaces
5.3 DISKETTE DRIVE INTERFACE
The diskette drive interface supports up to two diskette drives, each of which use a common cable
connected to a standard 34-pin diskette drive connector. All models come standard with a 3.5-inch
1.44-MB diskette drive installed as drive A. The drive designation is determined by which
connector is used on the diskette drive cable. The drive attached to the end connector is drive A
while the drive attached to the second (next to the end) connector) is drive B.
On all models, the diskette drive interface function is integrated into the LPC47B357 super I/O
component. The internal logic of the I/O controller is software-compatible with standard 82077type logic. The diskette drive controller has three operational phases in the following order:
♦ Command phase - The controller receives the command from the system.
♦ Execution phase - The controller carries out the command.
♦ Results phase - Status and results data is read back from the controller to the system.
The Command phase consists of several bytes written in series from the CPU to the data register
(3F5h/375h). The first byte identifies the command and the remaining bytes define the parameters
of the command. The Main Status register (3F4h/374h) provides data flow control for the diskette
drive controller and must be polled between each byte transfer during the Command phase.
The Execution phase starts as soon as the last byte of the Command phase is received. An
Execution phase may involve the transfer of data to and from the diskette drive, a mechnical
control function of the drive, or an operation that remains internal to the diskette drive controller.
Data transfers (writes or reads) with the diskette drive controller are by DMA, using the DRQ2 and
DACK2- signals for control.
The Results phase consists of the CPU reading a series of status bytes (from the data register
(3F5h/375h)) that indicate the results of the command. Note that some commands do not have a
Result phase, in which case the Execution phase can be followed by a Command phase.
During periods of inactivity, the diskette drive controller is in a non-operation mode known as the
Idle phase.
5-4 Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition – December 2000
5.3.1 DISKETTE DRIVE PROGRAMMING
Programming the diskette drive interface consists of configuration, which occurs typically during
POST, and control, which occurs at runtime.
5.3.1.1 Diskette Drive Interface Configuration
The diskette drive controller must be configured for a specific address and also must be enabled
before it can be used. Address selection and enabling of the diskette drive interface are affected by
firmware through the PnP configuration registers of the 47B357 I/O controller during POST.
The configuration registers are accessed through I/O registers 2Eh (index) and 2Fh (data) after the
configuration phase has been activated by writing 55h to I/O port 2Eh. The diskette drive I/F is
initiated by firmware selecting logical device 0 of the 47B357 using the following sequence:
1. Write 07h to I/O register 2Eh.
2. Write 00h to I/O register 2Fh (this selects the diskette drive I/F).
3. Write 30h to I/O register 2Eh.
4. Write 01h to I/O register 2Fh (this activates the interface).
Technical Reference Guide
Writing AAh to 2Eh deactivates the configuration phase. The diskette drive I/F configuration
registers are listed in the following table:
For detailed configuration register information refer to the SMSC data sheet for the LPC47B357
I/O component.
5.3.1.2 Diskette Drive Interface Control
The BIOS function INT 13 provides basic control of the diskette drive interface. The diskette drive
interface can be controlled by software through the LPC47B357’s I/O-mapped registers listed in
Table 5-5. The diskette drive controller of the LPC47B357 operates in the PC/AT mode in these
systems.
Table 5–5. Diskette Drive Interface Control Registers
Reset
Value
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
5-5
Chapter 5 Input/Output Interfaces
Diskette Drive Interface Control Registers
Pri.
Addr.
3F0h370hStatus Register A:
3F1h371hStatus Register B:
3F2h372hDigital Output Register (DOR):
3F3h373hTape Drive Register (available for compatibility)R/W
3F4h374hMain Status Register (MSR):
3F5h375hData Register:
3F6h376hReserved--
3F7h377hDigital Input Register (DIR):
NOTE: The most recently written data rate value to either DRSR or CCR will be in effect.
Sec.
Addr.RegisterR/W
<7> Interrupt pending
<6> Reserved (always 1)
<5> STEP pin status (ac tive high)
<4> TRK 0 status (active high)
<3> HDSEL status (0 = side 0, 1 = s i de 1)
<2> INDEX status (active high)
<1> WR PRTK stat us (0 = di sk is write protected)
<0> Direction (0 = outward, 1 = inward)
<7,6> Reserved (always 1’s)
<5> DOR bit 0 status
<4> Write data toggle
<3> Read data toggle
<2> WGATE st atus (active high)
<1,0> MTR 2, 1 ON- status (acti ve high)