Compaq 850 User Manual

Technical Reference Guide
For
Compaq Deskpro EXS
and
Compaq Deskpro Workstation 300 Personal Computers
Featuring the
Intel Pentium 4 Processor
And the
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Deskpro EXS and Deskpro W orkstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor and the Intel 850 Chipset
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Technical Reference Guide
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Technical Reference Guide
Compaq Deskpro EXS and Workstation 300 Series Personal Computers
First Edition - December 2000
Document Number 13YR-1200A-WWEN
for
Compaq Deskpro EXS and Workstation 300 Personal Computers Featuring the Intel Pentium 4 Processor
First Edition - December 2000
i
Technical Reference Guide
ii
Compaq Deskpro EXS and Workstation 300 Personal Computers Featuring the Intel Pentium 4 Processor
First Edition –- December 2000
Technical Reference Guide
TABLE OF CONTENTS
CHAPTER 1 INTRODUCTION..................................................................................................................
1.1 ABOUT THIS GUIDE................................................................................................................1-1
1.1.1 USING THIS GUIDE.......................................................................................................... 1-1
1.1.2 ADDITIONAL INFORMATION SOURCES..................................................................... 1-1
1.2 MODEL NUMBERING CONVENTION................................................................................... 1-1
1.3 NOTATIONAL CONVENTIONS.............................................................................................. 1-2
1.3.1 VALUES ............................................................................................................................. 1-2
1.3.2 RANGES.............................................................................................................................1-2
1.3.3 SIGNAL LABELS...............................................................................................................1-2
1.3.4 REGISTER NOTATION AND USAGE............................................................................. 1-2
1.3.5 BIT NOTATION.................................................................................................................1-2
1.4 COMMON ACRONYMS AND ABBREVIATIONS................................................................. 1-3
CHAPTER 2 SYSTEM OVERVIEW..........................................................................................................
2.1 INTRODUCTION....................................................................................................................... 2-1
2.2 FEATURES AND OPTIONS......................................................................................................2-2
2.2.1 STANDARD FEATURES...................................................................................................2-2
2.2.2 OPTIONS............................................................................................................................ 2-3
2.3 MECHANICAL DESIGN........................................................................................................... 2-4
2.3.1 CABINET LAYOUTS ........................................................................................................ 2-4
2.3.2 CHASSIS LAYOUT............................................................................................................2-6
2.3.3 BOARD LAYOUT.............................................................................................................. 2-7
2.4 SYSTEM ARCHITECTURE......................................................................................................2-8
2.4.1 PENTIUM 4 PROCESSOR............................................................................................... 2-10
2.4.2 CHIPSET...........................................................................................................................2-11
2.4.3 SUPPORT COMPONENTS.............................................................................................. 2-11
2.4.4 SYSTEM MEMORY.........................................................................................................2-12
2.4.5 MASS STORAGE............................................................................................................. 2 -12
2.4.6 SERIAL, PARALLEL INTERFACES.............................................................................. 2-12
2.4.7 UNIVERSAL SERIAL BUS INTERFACE ......................................................................2-12
2.4.8 GRAPHICS SUBSYSTEM............................................................................................... 2-13
2.4.9 AUDIO SUBSYSTEM...................................................................................................... 2-14
2.5 SPECIFICATIONS ...................................................................................................................2-14
CHAPTER 3 PROCESSOR/MEMORY SUBSYSTEM............................................................................
3.1 INTRODUCTION....................................................................................................................... 3-1
3.2 PENTIUM 4 PROCESSOR......................................................................................................... 3-2
3.2.1 PROCESSOR OVERVIEW................................................................................................3-2
3.2.2 PROCESSOR UPGRADING.............................................................................................. 3-4
3.3 MEMORY SUBSYSTEM........................................................................................................... 3-5
3.3.1 RAMBUS ATTRIBUTES................................................................................................... 3-6
3.3.2 RAMBUS CHANNEL TRANSACTIONS .........................................................................3-7
3.3.3 RDRAM POWER MANAGEMENT.................................................................................. 3-8
3.3.4 RDRAM CONFIGURATION/CONTROL......................................................................... 3-8
3.4 SUBSYSTEM CONFIGURATION.......................................................................................... 3-10
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CHAPTER 4 SYSTEM SUPPORT..............................................................................................................
4.1 INTRODUCTION....................................................................................................................... 4-1
4.2 PCI BUS OVERVIEW................................................................................................................ 4-2
4.2.1 PCI BUS TRANSACTIONS............................................................................................... 4-3
4.2.2 PCI BUS MASTER ARBITRATION.................................................................................4-6
4.2.3 OPTION ROM MAPPING..................................................................................................4-7
4.2.4 PCI INTERRUPTS............................................................................................................ .. 4-7
4.2.5 PCI POWER MANAGEMENT SUPPORT........................................................................4-7
4.2.6 PCI SUB-BUSSES.............................................................................................................. 4-7
4.2.7 PCI CONFIGURATION..................................................................................................... 4-8
4.2.8 PCI CONNECTOR..............................................................................................................4-9
4.3 AGP BUS OVERVIEW............................................................................................................4-10
4.3.1 BUS TRANSACTIONS....................................................................................................4-10
4.3.2 AGP CONFIGURATION..................................................................................................4-13
4.3.3 AGP CONNECTOR..........................................................................................................4-14
4.4 SYSTEM RESOURCES ...........................................................................................................4-15
4.4.1 INTERRUPTS................................................................................................................... 4-15
4.4.2 DIRECT MEMORY ACCESS..........................................................................................4-19
4.5 SYSTEM CLOCK DISTRIBUTION........................................................................................4-20
4.6 REAL-TIME CLOCK AND CONFIGURATION MEMORY .................................................4-20
4.6.1 CLEARING CMOS........................................................................................................... 4-21
4.6.2 CMOS ARCHIVE AND RESTORE................................................................................. 4-22
4.6.3 STANDARD CMOS LOCATIONS.................................................................................. 4-22
4.7 SYSTEM MANAGEMENT...................................................................................................... 4-31
4.7.1 SECURITY FUNCTIONS ................................................................................................ 4-31
4.7.2 POWER MANAGEMENT................................................................................................4-32
4.7.3 SYSTEM STATUS ........................................................................................................... 4-33
4.7.4 TEMPERATURE SENSING AND COOLING................................................................ 4-34
4.8 REGISTER MAP AND MISCELLANEOUS FUNCTIONS.................................................... 4-35
4.8.1 SYSTEM I/O MAP ........................................................................................................... 4-35
4.8.2 82801 ICH GENERAL PURPOSE FUNCTIONS............................................................ 4-36
4.8.3 I/O CONTROLLER FUNCTIONS .................................................................................. 4-37
CHAPTER 5 INPUT/OUTPUT INTERFACES.........................................................................................
5.1 INTRODUCTION....................................................................................................................... 5-1
5.2 ENHANCED IDE INTERFACE................................................................................................. 5-1
5.2.1 IDE PROGRAMMING....................................................................................................... 5-1
5.2.2 IDE CONNECTOR............................................................................................................. 5-3
5.3 DISKETTE DRIVE INTERFACE.............................................................................................. 5-4
5.3.1 DISKETTE DRIVE PROGRAMMING.................................................................................5-5
5.3.2 DISKETTE DRIVE CONNECTOR...................................................................................... 5-7
5.4 SERIAL INTERFACE................................................................................................................5-8
5.4.1 RS-232 INTERFACE.......................................................................................................... 5-8
5.4.2 SERIAL INTERFACE PROGRAMMING .........................................................................5-9
5.5 PARALLEL INTERFACE........................................................................................................5-11
5.5.1 STANDARD PARALLEL PORT MODE......................................................................... 5-11
5.5.2 ENHANCED PARALLEL PORT MODE ........................................................................5-12
5.5.3 EXTENDED CAPABILITIES PORT MODE .................................................................. 5-12
5.5.4 PARALLEL INTERFACE PROGRAMMING................................................................. 5-13
5.5.5 PARALLEL INTERFACE CONNECTOR...................................................................... 5-15
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5.6 KEYBOARD/POINTING DEVICE INTERFACE................................................................... 5-16
5.6.1 KEYBOARD INTERFACE OPERATION....................................................................... 5-16
5.6.2 POINTING DEVICE INTERFACE OPERATION .......................................................... 5-18
5.6.3 KEYBOARD/POINTING DEVICE INTERFACE PROGRAMMING...........................5-18
5.6.4 KEYBOARD/POINTING DEVICE INTERFACE CONNECTOR..................................5-21
5.7 UNIVERSAL SERIAL BUS INTERFACE .............................................................................. 5-22
5.7.1 USB DATA FORMATS....................................................................................................5-22
5.7.2 USB PROGRAMMING....................................................................................................5-24
5.7.3 USB CONNECTOR.......................................................................................................... 5-25
5.7.4 USB CABLE DATA......................................................................................................... 5-25
5.8 AUDIO SUBSYSTEM..............................................................................................................5-26
5.8.1 FUNCTIONAL ANALYSIS............................................................................................. 5-26
5.8.2 AUDIO CONTROLLER................................................................................................... 5-28
5.8.3 AC97 LINK BUS ..............................................................................................................5-29
5.8.4 AUDIO CODEC ................................................................................................................5-30
5.8.5 AUDIO PROGRAMMING............................................................................................... 5-31
5.8.6 AUDIO SPECIFICATIONS.............................................................................................. 5-32
5.9 NETWORK SUPPORT............................................................................................................. 5-33
5.9.1 PCI VER. 2.2 SUPPORT ..................................................................................................5-33
5.9.2 ALERT-ON-LAN SUPPORT ........................................................................................... 5-33
5.9.3 REMOTE SYSTEM ALERT SUPPORT.......................................................................... 5-35
CHAPTER 6 POWER SUPPLY AND DISTRIBUTION..........................................................................
6.1 INTRODUCTION....................................................................................................................... 6-1
6.2 POWER SUPPLY ASSEMBLY/CONTROL ............................................................................. 6-1
6.2.1 POWER SUPPLY ASSEMBLY.........................................................................................6-2
6.2.2 POWER CONTROL ........................................................................................................... 6-3
6.3 POWER DISTRIBUTION .......................................................................................................... 6-5
6.3.1 3.3/5/12 VDC DISTRIBUTION.......................................................................................... 6-5
6.3.2 LOW VOLTAGE PRODUCTION/DISTRIBUTION......................................................... 6-6
6.4 SIGNAL DISTRIBUTION..........................................................................................................6-7
CHAPTER 7 BIOS ROM.............................................................................................................................
7.1 INTRODUCTION....................................................................................................................... 7-1
7.2 ROM FLASHING ....................................................................................................................... 7-2
7.2.1 UPGRADING...................................................................................................................... 7-2
7.2.2 CHANGEABLE SPLASH SCREEN .................................................................................. 7-3
7.3 BOOT FUNCTIONS................................................................................................................... 7-4
7.3.1 BOOT DEVICE ORDER.................................................................................................... 7-4
7.3.2 NETWORK BOOT (F12) SUPPORT................................................................................. 7-4
7.3.3 MEMORY DETECTION AND CONFIGURATION......................................................... 7-5
7.3.4 BOOT ERROR CODES...................................................................................................... 7-5
7.4 SETUP UTILITY........................................................................................................................7-6
7.5 CLIENT MANAGEMENT FUNCTIONS................................................................................ 7-12
7.5.1 SYSTEM ID AND ROM TYPE........................................................................................ 7-14
7.5.2 EDID RETRIEVE ............................................................................................................. 7-14
7.5.3 TEMPERATURE STATUS..............................................................................................7-14
7.5.4 DRIVE FAULT PREDICTION.........................................................................................7-15
7.6 PNP SUPPORT ......................................................................................................................... 7-15
7.6.1 SMBIOS............................................................................................................................ 7-16
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7.7 POWER MANAGEMENT FUNCTIONS................................................................................7-17
7.7.1 INDEPENDENT PM SUPPORT ...................................................................................... 7-17
7.7.2 ACPI SUPPORT................................................................................................................7-19
7.7.3 APM 1.2 SUPPORT.......................................................................................................... 7-19
7.8 USB LEGACY SUPPORT........................................................................................................ 7-23
A. APPENDIX A ERROR MESSAGES AND CODES...........................................................................
A.1 INTRODUCTION...................................................................................................................... A-1
A.2 BEEP/KEYBOARD LED CODES............................................................................................. A-1
A.3 POWER-ON SELF TEST (POST) MESSAGES ....................................................................... A-2
A.4 SYSTEM ERROR MESSAGES (1 A.5 MEMORY ERROR MESSAGES (2 A.6 KEYBOARD ERROR MESSAGES (30 A.7 PRINTER ERROR ME SSAGES ( 4 A.8 VIDEO (GRAPHICS) ERROR MESSAGES (5 A.9 DISKETTE DRIVE ERROR MESSAGES (6 A.10 SERIAL INTERFACE ERROR MESSAGES (1 1 A.11 MODEM COMMUNICATIONS ERROR MESSAGES (12 A.12 SYSTEM STATUS ERROR MESSAGES (16 A.13 HARD DRIVE ERROR MESSAGES (17 A.14 HARD DRIVE ERROR MESSAGES (19 A.15 VIDEO (GRAPHICS) ERROR MESSAGES (24 A.16 AUDIO ERROR MESSAGES (3206­A.17 DVD/CD-ROM ERROR MESSAGES (33 A.18 NETWORK INTERFACE ERROR MESSAGES (60 A.19 SCSI INTERFACE ERROR MESSAGES (65 A.20 POINTING DEVICE INTERFACE ERROR MESSAGES (8601-
) ................................................................................ A-3
XX-XX
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XX-XX
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X-XX
)................................................................................ A-5
XX-XX
)............................................................. A-5
XX-XX
)................................................................ A-6
XX-XX
).......................................................... A-6
XX-XX
)......................................... A-7
XX-XX
) .............................................................. A-8
XX-XX
)...................................................................... A-8
XX-XX
)...................................................................... A-9
XX-XX
)........................................................... A-9
XX-XX
)................................................................................ A-10
XX
)................................................................... A-10
XX-XX
) ................................................. A-10
XX-XX
, 66XX-XX, 67XX-XX)............................ A-11
XX-XX
).................................... A-11
XX
APPENDIX B ASCII CHARACTER SET..................................................................................................
B.1 INT RODUCTION.......................................................................................................................B-1
APPENDIX C KEYBOARD.........................................................................................................................
C.1 INT RODUCTI ON.......................................................................................................................C-1
C.2 KEYSTROKE PROCESSING ....................................................................................................C-2
C.2.1 PS/2-TYPE KEYBOARD TRANSMISSIONS...................................................................C-3
C.2.2 USB-TYPE KEYBOARD TRANSMISSIONS...................................................................C-4
C.2.3 KEYBOARD LAYOUTS....................................................................................................C-5
C.2.4 KEYS...................................................................................................................................C-8
C.2.5 KEYBOARD COMMANDS.............................................................................................C-11
C.2.6 SCAN CODES...................................................................................................................C-11
C.3 CONNECTORS......................................................................................................................... C-16
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APPENDIX D COMPAQ/NVIDIA TNT2 PRO AGP GRAPHICS CARD..............................................
D.1 INTRODUCTION...................................................................................................................... D-1
D.2 FUNCTIONAL DESCRIPTION................................................................................................ D-2
D.3 DISPLAY MODES .................................................................................................................... D-3
D.4 SOFTWARE SUPPORT INFORMATION ............................................................................... D-4
D.5 POWER MANAGEMENT
AND CONSUMPTION ................................................................. D-4
D.6 CONNECTORS.......................................................................................................................... D-5
D.6.1 MONITOR CONNECTOR ................................................................................................ D-5
APPENDIX E COMPAQ/NVIDIA GEFORCE2 GTS AGP GRAPHICS CARD...................................
E.1 INTRODUCTION.......................................................................................................................E-1
E.2 FUNCTIONAL DESCRIPTION.................................................................................................E-2
E.3 DISPLAY MODES .....................................................................................................................E-3
E.4 SOFTWARE SUPPORT INFORMATION ................................................................................E-4
E.5 POWER MANAGEMENT AND CONSUMPTION..................................................................E-4
E.6 CONNECTORS...........................................................................................................................E-5
E.6.1 MONITOR CONNECTOR .................................................................................................E-5
E.6.2 VIDEO FEATURE CONNECTOR.....................................................................................E-6
APPENDIX F COMPAQ/LUCENT V.90 56K PCI MODEM ..................................................................
F.1 INTRODUCTION.......................................................................................................................F-1
F.2 FUNCTIONAL DESCRIPTION.................................................................................................F-2
F.3 OPERATING PARAMETERS ...................................................................................................F-3
F.3.1 UART TRANSFER RATES................................................................................................F-3
F.3.2 TRANSMISSION MODES.................................................................................................F-3
F.4 P OWER MANAGEMENT .........................................................................................................F-4
F.4.1 APM ENVIRONMENT......................................................................................................F-4
F.4.2 ACPI ENVIRONMENT......................................................................................................F-4
F.5 P ROGRAMMING.......................................................................................................................F-4
F.6 CONNECTOR.............................................................................................................................F-4
APPENDIX G COMPAQ/ELSA GLORIA II GRAPHICS CARD...........................................................
G.1 INTRODUCTION...................................................................................................................... G-1
G.2 FUNCTIONAL DESCRIPTION................................................................................................ G-2
G.3 DISPLAY MODES .................................................................................................................... G-3
G.4 SOFTWARE SUPPORT INFORMATION ............................................................................... G-4
G.5 POWER MANAGEMENT AND CONSUMPTION................................................................. G-4
G.6 CONNECTORS.......................................................................................................................... G-5
G.6.1 MONITOR CONNECTOR ................................................................................................ G-5
G.6.2 VIDEO FEATURE CONNECTOR.................................................................................... G-6
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APPENDIX H COMPAQ/MATROX MILLENNIUM G450 AGP GRAPHICS CARD........................
H.1 INTRODUCTION...................................................................................................................... H-1
H.2 FUNCTIONAL DESCRIPTION................................................................................................ H-2
H.3 DISPLAY MODES .................................................................................................................... H-3
H.4 SOFTWARE SUPPORT INFORMATION ............................................................................... H-4
H.5 POWER MANAGEMENT AND CONSUMPTION................................................................. H-4
H.6 CONNECTORS.......................................................................................................................... H-5
H.6.1 MONITOR CONNECTOR ................................................................................................ H-5
H.6.2 VIDEO FEATURE CONNECTOR.................................................................................... H-6
APPENDIX I COMPAQ/INTEL NETWORK INTERFACE CONTROLLER ADAPTERS................
I.1 INTRODUCTION........................................................................................................................I-1
I.2 FUNCTIONAL DESCRIPTION..................................................................................................I-2
I.2.1 AOL FUNCTION.............................................................................................................. .......I-3
I.2.2 WAKE UP FUNCTIONS.........................................................................................................I-3
I.2.3 IPSEC FUNCTION..................................................................................................................I-4
I.3 POWER MANAGEMENT SUPPORT........................................................................................I-5
I.3.1 APM ENVIRONMENT ...........................................................................................................I-5
I.3.2 ACPI ENVIRONMENT...........................................................................................................I-5
I.4 ADAPTER PROGRAMMING.................................................................................................... I-6
I.4.1 CONFIGURATION .................................................................................................................I-6
I.4.2 CONTROL...............................................................................................................................I-6
I.5 NETWORK CONNECTOR.........................................................................................................I-7
I.6 ADAPTER SPECIFICATIONS...................................................................................................I-7
APPENDIX J COMPAQ/NVIDIA QUADRO2 MXR AGP GRAPHICS CARD....................................
J.1 INTRODUCTION........................................................................................................................J-1
J.2 FUNCTIONAL DESCRIPTION..................................................................................................J-2
J.3 DISPLAY MODES ......................................................................................................................J-3
J.4 SOFTWARE SUPPORT INFORMATION .................................................................................J-4
J.5 POWER MANAGEMENT AND CONSUMPTION ...................................................................J-4
J.6 CONNECTORS............................................................................................................................J -5
J.6.1 MONITOR CONNECTOR ..................................................................................................J-5
APPENDIX K COMPAQ PCI 10/100 ETHERNET ADAPTER..............................................................
K.1 INTRODUCTION...................................................................................................................... K-1
K.2 FUNCTIONAL DESCRIPTION................................................................................................ K-2
K.2.1 AOL FUNCTION.................................................................................................................K-3
K.2.2 RSA FUNCTION..................................................................................................................K-4
K.2.3 WAKE UP FUNCTIONS .....................................................................................................K-4
K.3 POWER MANAGEMENT SUPPORT...................................................................................... K-5
K.3.1 APM ENVIRONMENT ..................................................................................................... K-5
K.3.2 ACPI ENVIRONMENT..................................................................................................... K-5
K.4 CONNECTORS.......................................................................................................................... K-6
K.4.1 NETWORK CONNECTOR............................................................................................... K-6
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K.4.2 AOL/SOS CONNECTOR .................................................................................................. K-6
K.4.3 SMBUS CONNECTOR ..................................................................................................... K-7
K.4.4 WOL CONNECTOR.......................................................................................................... K-7
K.5 ADAPTER SPECIFICATIONS................................................................................................. K-8
APPENDIX L COMPAQ/ADAPTEC SCSI HOST ADAPTER................................................................
L.1 INTRODUCTION.......................................................................................................................L-1
L.2 FUNCTIONAL DESCRIPTION.................................................................................................L-2
L.3 SCSI ADAPTER PROGRAMMING..........................................................................................L-3
L.3.1 SCSI ADAPTER CONFIGURATION................................................................................L-3
L.3.2 SCSI ADAPTER CONTROL..............................................................................................L-3
L.4 SPECIFICATIONS .....................................................................................................................L-3
L.5 SCSI CONNECTORS.................................................................................................................L-4
L.5.1 EXTERNAL 50-PIN ULTRA SCSI CONNECTOR...........................................................L-4
L.5.2 INTERNAL 50-PIN ULTRA SCSI CONNECTOR............................................................L-5
L.5.3 INT ERNAL 68-PIN ULTRA160 SCSI CONNECTOR......................................................L-6
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Compaq Deskpro EXS and Workstation 300 Personal Computers Featuring the Intel Pentium 4 Processor
First Edition –- December 2000
....................................................... 6-1
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Technical Reference Guide
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C–1. K C–2. PS/2 K C–3. U.S. E C–4. N C–5. U.S. E C–6. N C–7. 7-B C–8. 8-B C–9. PS/2 K C–10. USB K
D-1. C
EYSTROKE PROCESSING ELEMENTS
EYBOARD-TO-SYSTEM TRANSMISSION
NGLISH
ATIONAL
ATIONAL WINDOWS
OMPAQ
(102-KEY) K
NGLISH WINDOWS
UTTON EASY ACCESS KEYBOARD LAYOUT UTTON EASY ACCESS KEYBOARD LAYOUT
EYBOARD CABLE CONNECTOR (MALE
EYBOARD CABLE CONNECTOR (MALE
/NVIDIA TNT2 P D-2. NVIDIA TNT2 P D-3. VGA M
E-1. C E-2. NVIDIA GEF E-3. VGA M E-4. F
F-1. C F-2. C F-3. RJ-11 C
G-1. C G-2. ELSA GL G-3. VGA M G-4. F
ONITOR CONNECTOR
/NVIDIA GEF
OMPAQ
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ONITOR CONNECTOR
EATURE CONNECTOR
OMPAQ/LUCENT
OMPAQ/LUCENT
ONNECTOR
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OMPAQ
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ORIA
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, B
LOCK DIAGRAM
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IMING DIAGRAM
(101-KEY) K
EYBOARD KEY POSITIONS
EYBOARD KEY POSITIONS
(101W-KEY) K
(102W-KEY) K
EYBOARD KEY POSITIONS
EYBOARD KEY POSITIONS
.....................................................................C-7
.....................................................................C-7
)....................................................................C-16
) .................................................................C-16
AGP G
RO
RO GRAPHICS CARD BLOCK DIAGRAM
, (F
2 GTS AGP G
ORCE
2 GTS G
RAPHICS CARD BLOCK DIAGRAM
, (F
(26-P
IN HEADER
V.90 56K PCI M
V.90 56K PCI M
, (F
EMALE, AS VIEWED FROM REAR
II AGP G
ORIA
RAPHICS CARD BLOCK DIAGRAM
, (F
(26-P
IN HEADER
RAPHICS CARD
DB-15,
EMALE
EMALE
DB-15,
AS VIEWED FROM REAR
RAPHICS CARD
AS VIEWED FROM REAR
).................................................................................E-6
(PCA #152972) L
ODEM
ODEM BLOCK DIAGRAM
RAPHICS CARD
DB-15,
EMALE
AS VIEWED FROM REAR
) ................................................................................G-6
......................................................C-2
........................................C-3
..........................................................C-5
...............................................................C-5
.....................................C-6
..........................................C-6
(P/N 198998-B21) L
AYOUT
.............D-1
.........................................................D-2
)...............................D-5
(P/N 179642-001) L
AYOUT
......E-1
................................................E-2
). ..............................E-5
.....................................F-1
AYOUT
...................................................F-2
). ......................................................... F-4
(P/N 174565-001) L
AYOUT
...................G-1
..............................................................G-2
)...............................G-5
F F F F
F F F
F F F
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H-2. M
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H-3. VGA M
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H-4. F
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I-2. I
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I-3. E
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J-2. NVIDIA Q
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K-2. C
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K-3. E
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K-4. AOL/SOS C
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K-5. SMB
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K-6. WOL C
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OMPAQ/MATROX MILLENNIUM
ATROX MILLENNIUM
ONITOR CONNECTOR
EATURE CONNECTOR
PRO/100+
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PRP/100+ M
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THERNET
OMPAQ
OMPAQ OMPAQ
THERNET
TPE C
/NVIDIA Q
UADRO
ONITOR CONNECTOR
PCI 10/100 E PCI 10/100 E
TPE C
ONNECTOR
US CONNECTOR
ONNECTOR
G450 G
(26-P
PRO/100 S M
OR
ANAGEMENT ADAPTER
ONNECTOR
UADRO
2 MXR G
THERNET ADAPTER CARD LAYOUT THERNET ADAPTER
ONNECTOR
(7-
(4-
(3-
PIN HEADER
G450 AGP G
RAPHICS CARD BLOCK DIAGRAM
, (O
NE OF TWO FEMALE
IN HEADER
(RJ-45,
) ................................................................................H-6
ANAGEMENT ADAPTER CARD LAYOUT
VIEWED FROM CARD EDGE
2 MXR AGP G
RAPHICS CARD BLOCK DIAGRAM
, (F
PIN HEADER
PIN HEADER
DB-15,
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(RJ-45,
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)..................................................................................K-7
RAPHICS CARD LAYOUT
DB-15,
, B
LOCK DIAGRAM
RAPHICS CARD
AS VIEWED FROM REAR
, B
LOCK DIAGRAM
)..............................................................................K-6
).....................................................................................K-7
(PCA# 202901-001)H-1
...........................................H-2
AS VIEWED FROM REAR
...............................I-1
..................................................I-2
)..........................................I-7
(PCA# 221411-001) L
..................................................J-2
).................................J-5
(PCA# 402355-001) ...................K-1
................................................K-2
) .......................................K-6
Compaq Deskpro EXS and Workstation 300 Personal Computers Featuring the Intel Pentium 4 Processor
First Edition - December 2000
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XTERNAL ULTRA
L–4. I
NTERNAL
L–5. U
LTRA
OMPAQ/ADAPTEC OMPAQ/ADAPTEC ULTRA
50-P
160 SCSI C
29160N SCSI H
SCSI C
IN ULTRA
ONNECTOR
ONNECTOR
SCSI C
SCSI A
DAPTER CARD BLOCK DIAGRAM
ONNECTOR
(68-
PIN HEADER TYPE
OST ADAPTER CARD LAYOUT
(PCA# 157342-001).....L-1
....................................L-2
(50-
).......................................................................L-4
PIN
..........................................................................L-5
)............................................................L-6
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First Edition –- December 2000
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CRONYMS AND ABBREVIATIONS
TANDARD FEATURE DIFFERENCE MATRIX
HIPSET COMPARISON UPPORT COMPONENT FUNCTIONS TANDARD
NVIRONMENTAL SPECIFICATIONS LECTRICAL SPECIFICATIONS
HYSICAL SPECIFICATIONS
ISKETTE DRIVE SPECIFICATIONS
ARD DRIVE SPECIFICATIONS
/PCI B
OST
ASKABLE INTERRUPT PRIORITIES AND ASSIGNMENTS ASKABLE INTERRUPT CONTROL REGISTERS
EFAULT
LOCK GENERATION AND DISTRIBUTION
ONFIGURATION MEMORY YSTEM BOOT YSTEM OPERATIONAL STATUS
YSTEM
Technical Reference Guide
LIST OF TABLES
.......................................................................................... 1-3
............................................................................. 2-2
........................................................................................................... 2-11
........................................................................................ 2-11
AGP G
RAPHICS CARD COMPARISON
........................................................................................ 2-14
................................................................................................ 2-14
.................................................................................................... 2-15
......................................................................................... 2-15
RIVE SPECIFICATIONS
.................................................................................. 2-16
............................................................................................. 2-16
RIDGE CONFIGURATION REGISTERS
EVICE CONFIGURATION ACCESS DATA
US MASTERING DEVICES
RIDGE CONFIGURATION REGISTERS
US CONNECTOR PINOUT
RIDGE CONFIGURATION REGISTERS
US CONNECTOR PINOUT
DMA C
HANNEL ASSIGNMENTS AND REGISTER
................................................................................................ 4-6
................................................................................................. 4-9
.............................................................................................. 4-14
(CMOS) MAP........................................................................... 4-22
/ROM F
LASH STATUS
LED I
LED I
NDICATIONS
I/O MAP................................................................................................................ 4-35
EGISTER UTILIZATI ON (DESKTOP AND MINITOWER ONLY
ONTROL REGISTERS
EGISTER UTILIZATI ON (DESKTOP AND MINITOWER ONLY
........................................................................................ 4-37
................................................................... 2-13
(GMCH, F
UNCTION
0) ............................... 3-10
.......................................................................... 4-4
(ICH, F
(MCH, F
UNCTION
0)................................................ 4-8
UNCTION
1).................................... 4-13
........................................................ 4-16
....................................................................... 4-17
I/O P
................................... 4-19
ORTS
............................................................................ 4-20
NDICATIONS
...................................................... 4-33
.............................................................. 4-33
) .................... 4-36
) .................. 4-38
5–1. IDE PCI C
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ONFIGURATION REGISTERS
IDE B
US MASTER CONTROL REGISTERS
IN PRIMARY ISKETTE DRIVE CONTROLLER CONFIGURATION REGISTERS ISKETTE DRIVE INTERFACE CONTROL REGISTERS
34-P
IN DISKETTE DRIVE CONNECTOR PINOUT
DB-9 S
ERIAL CONNECTOR PINOUT ERIAL INTERFACE CONFIGURATION REGISTERS ERIAL INTERFACE CONTROL REGISTERS
ARALLEL INTERFACE CONFIGURATION REGISTERS
PARALLEL INTERFACE CONTROL REGISTERS
EYBOARD INTERFACE CONFIGURATION REGISTERS
OMMANDS TO THE
EYBOARD/POINTING DEVICE CONNECTOR PINOUT
NTERFACE CONFIGURATION REGISTERS
ONTROL REGISTERS
IDE C
ONNECTOR PINOUT
ARALLEL CONNECTOR PINOUT
EYBOARD COMMANDS
8042.......................................................................................... 5-20
................................................................................................. 5-24
.................................................................................... 5-2
................................................................................. 5-2
............................................................................ 5-3
.................................................. 5-5
................................................................ 5-5
........................................................................ 5-7
......................................................................................... 5-8
.................................................................... 5-9
............................................................................. 5-10
........................................................... 5-13
....................................................................... 5-14
.............................................................................. 5-15
...................................................................................... 5-17
.......................................................... 5-18
.......................................................... 5-21
.................................................................... 5-24
Compaq Deskpro EXS and Workstation 300 Personal Computers Featuring the Intel Pentium 4 Processor
First Edition - December 2000
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A–1. B A–2. P A–3. S A–4. M A–5. K A–6. P A–7. V A–8. D A–9. S A–10. S A–11. S A–12. H A–13. H A–14. V A–15. A A–16. DVD/CD-ROM D A–17. N A–18. SCSI I A–19. P
ONNECTOR PINOUT ABLE LENGTH DATA
UDIO CONTROLLER UDIO CODEC CONTROL REGISTERS
UDIO SUBSYSTEM SPECIFICATIONS
VENTS
EMOTE SYSTEM ALERT EVENTS
ETUP UTILITY FUNCTIONS
LIENT MANAGEMENT FUNCTIONS
UNCTIONS UNCTIONS
EEP/KEYBOARD OWER-ON SELF TEST YSTEM ERROR MESSAGES
EMORY ERROR MESSAGES
EYBOARD ERROR MESSAGES
RINTER ERROR MESSAGES
IDEO (GRAPHICS ISKETTE DRIVE ERROR MESSAGES
ERIAL INTERFACE ERROR MESSAGES
ERIAL INTERFACE ERROR MESSAGES YSTEM STATUS ERROR MESSAGES
ARD DRIVE ERROR MESSAGES ARD DRIVE ERROR MESSAGES IDEO (GRAPHICS UDIO ERROR MESSAGES
ETWORK INTERFACE ERROR MESSAGES
NTERFACE ERROR MESSAGES
OINTING DEVICE INTERFACE ERROR MESSAGES
.................................................................................................. 5-25
................................................................................................ 5-25
PCI C
ONFIGURATION REGISTERS
........................................... 5-31
....................................................................... 5-31
................................................................................... 5-32
...................................................................................................................... 5-33
....................................................................................... 5-36
................................................................................................................. 7-2
................................................................................................................. 7-5
...................................................................................................... 7-6
(INT15)......................................................................... 7-12
.......................................................................................................... 7-15
.......................................................................................................... 7-20
LED C
...............................................................................................A-1
ODES
(POST) M
ESSAGES
............................................................................A-2
....................................................................................................A-3
..................................................................................................A-4
..............................................................................................A-4
...................................................................................................A-5
) E
RROR MESSAGES
..................................................................................A-5
......................................................................................A-6
...................................................................................A-6
.................................................................................A-7
.....................................................................................A-8
..........................................................................................A-8
..........................................................................................A-9
) E
RROR MESSAGES
................................................................................A-9
..................................................................................................A-10
RIVE ERROR MESSAGES
........................................................................A-10
..........................................................................A-10
..................................................................................A-11
..............................................................A-11
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G–4. V
ABLE
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Compaq Deskpro EXS and Workstation 300 Personal Computers
EYBOARD-TO-SYSTEM COMMANDS EYBOARD SCAN CODES
RO GRAPHICS DISPLAY MODES
ONITOR POWER MANAGEMENT CONDITIONS
ONITOR CONNECTOR PINOUT
2 GTS G
ORCE
ONITOR POWER MANAGEMENT CONDITIONS
ONITOR CONNECTOR PINOUT
IDEO IN CONNECTOR PINOUT
PERATIONAL MODES
II G
ORIA
ONITOR POWER MANAGEMENT CONDITIONS
ONITOR CONNECTOR PINOUT
IDEO IN CONNECTOR PINOUT
.....................................................................................................C-12
RAPHICS DISPLAY MODES
...............................................................................................................F-3
RAPHICS DISPLAY MODES
...................................................................................C-11
.......................................................................D-4
...................................................................................D-5
.......................................................................E-4
...................................................................................E-5
...............................................................................................E-6
..........................................................................G-3
.......................................................................G-4
...................................................................................G-5
..............................................................................................G-6
Featuring the Intel Pentium 4 Processor
First Edition –- December 2000
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ONITOR POWER MANAGEMENT CONDITIONS
H-3. DB-15 M H–4. V
IDEO IN CONNECTOR PINOUT
G450 G
ONITOR CONNECTOR PINOUT
RAPHICS DISPLAY MODES
..............................................................................................H-6
Technical Reference Guide
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.......................................................................H-4
...................................................................................H-5
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K-1. A
L–1. SCSI H L–2. U L–3. E L–4. I L–5. U
ONTROLLER
ONTROL REGISTERS
DAPTER OPERATING SPECIFICATIONS
UADRO
ONITOR POWER MANAGEMENT CONDITIONS
ONITOR CONNECTOR PINOUT
DAPTER SPECIFICATIONS
OST ADAPTER CARD CONTROL REGISTER MAPPING
SCSI H
LTRA XTERNAL
NTERNAL
LTRA
50-P
50-P
160 SCSI C
PCI C
2 MXR G
OST ADAPTER CARD SPECIFICATIONS
IN ULTRA
IN ULTRA
ONNECTOR PINOUT
ONFIGURATION REGISTERS
...............................................................I-6
........................................................................................................I-6
.......................................................................................I-7
RAPHICS DISPLAY MODES
..............................................................J-3
.........................................................................J-4
.....................................................................................J-5
........................................................................................................K-8
....................................................L-3
...............................................................L-3
SCSI C
SCSI C
ONNECTOR PINOUT
ONNECTOR PINOUT
..............................................................L-4
...............................................................L-5
.....................................................................................L-6
Compaq Deskpro EXS and Workstation 300 Personal Computers Featuring the Intel Pentium 4 Processor
First Edition - December 2000
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Compaq Deskpro EXS and Workstation 300 Personal Computers Featuring the Intel Pentium 4 Processor
First Edition –- December 2000
Chapter 1 INTRODUCTION
Technical Reference Guide
1.
Chapter 1 INTRODUCTION
1.1 ABOUT THIS GUIDE
This guide provides technical information about Compaq Deskpro Personal Computers that feature the Intel Pentium 4 processor and the Intel 850 chipset. This document includes information regarding system design, function, and features that can be use d by programmers, engineers, technicians, and system administrators.
This guide and any applicable addendums are available online at the following location:
http://www.compaq.com/support/techpubs/technical_reference_guides/index.html
1.1.1 USING THIS GUIDE
The chapters of this guide primarily describe the hardware and firmware elements and primarily deal with the system board and the power supply assembly. The appendices contain general information about standard peripheral devices such as the keyboard.
1.1.2 ADDITIONAL INFORMATION S O URCES
For more information on chipset components mentioned in this guide refer to the indicated manufacturers’ documentation, which may be available at the following online sources:
Compaq Computer Corpo ration: http://www.compaq.comIntel Corporation: http://www.intel.comStandard Microsystems Corporation: http://www.smsc.com
1.2 MODEL NUMBERING CONVENTION
The model numbering convention for Compaq Deskpro units is as follows:
XXX/XNNN/NNX/N/NNNxxx
NIC/Modem: blank = none, n = NIC, m = modem Graphics: blank = integrated, a = AIMM, v = nVIDIA Removable storage: b = CD/CDRW, c = CD, d = DVD, r = CDRW, z = ZIP Memory (in MB) OS type (9 = Dual install Win95/98, 4 = Win NT 4.0, 6 = Dual install Win NT/2000) Chipset type (e = 850) Hard drive size (in GB) Processor speed (in MHz) Processor type: C = Celeron; P = Pentium Form factor: D = Desktop, M = Minitower Deskpro series: EX = EXS, WK = Workstation
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
1-1
First Edition – December 2000
Chapter 1 Introduction
1.3 NOTATIONAL CONVENTIONS
1.3.1 VALUES
Hexadecimal values are indicated by a numerical or alpha-numerical value followed by the letter “h.” Binary values are indicated by a value of ones and zeros followed by the letter “b.” Numerical values that have no succeeding letter can be assumed to be decimal.
1.3.2 RANGES
Ranges or limits for a parameter are shown using the following methods:
Example A: Bits <7..4> = bits 7, 6, 5, and 4. Example B: IRQ3-7, 9 = IRQ signals 3 thro ugh 7, and IRQ signal 9
1.3.3 SIGNAL LABELS
Signal names are indicated using abbreviations, acronyms, or, if possible, the full signal name in all capital letters. Signals that are meant to be active (asserted) low are indicated with a dash immediately following the name.
1.3.4 REGISTER NOTATION AND USAGE
This guide uses sta ndard Intel naming co nventions in discussing the microprocessor ’s (CPU) internal registers. Registers that are accessed through programmable I/O using an indexing scheme are indicated using the following format:
03C5.17h
Index port Data port
In the example above, register 03C5.17h is accessed by writing the index port value 17h to the index address (03C4h), followed by a write to or a read from port 03C5h.
1.3.5 BIT NOTATION
Bit values are labeled with bit <0> representing the least-significant bit (LSb) and bit <7> representing the most-significant bit (MSb) of a byte. Bytes, words, double words, and quad words are typically shown with most-significant portions on the left or top and the least-significant portions on the right or bottom respectively.
1-2
Compaq Deskpro EXS and Workstation 300 Personal Computers Featuring the Intel Pentium 4 Processor
First Edition – December 2000
1.4 COMMON ACRONYMS AND ABBREVIATIONS
Table 1-1 lists the acronyms and abbreviations used in this guide. Table 1–1. Acronyms and Abbreviations
Table 1-1.
Acronyms and Abbreviations
Acronym/Abbreviation Description
A ampere AC alternating current ACPI Advanced Configuration and Power Interfac e A/D analog-to-digital AGP Accelerated graphics port API applicat i on programming interface APIC Advanced Programmable I n t errupt Controller APM advanced power management AOL Alert-On-LAN™ ASIC application-specific integrated circuit AT 1) attention (modem commands) 2) 286-based PC arc hi tecture ATA AT attachment (IDE protocol) ATAPI AT attachment w/packet interface extensions AVI audio-video int erl eaved AVGA Advanced VGA AWG American Wire Gauge (specifi cation) BAT Basic assurance test BCD binary-coded decimal BIOS basic input/output system bis second/new revision BNC Bayonet Neill-Concelman (connector t ype) bps or b/s bits per second BSP Bootstrap processor BTO Built to order CAS column address strobe CD compact disk CD-ROM compact disk read-onl y memory CDS compact disk system CGA color graphics adapter Ch Channel, chapter cm centimeter CMC cache/memory controller CMOS complimentary metal-oxide semiconduct o r (configuration memory) Cntlr controller Cntrl control codec compressor/decompressor CPQ Compaq CPU central processing unit CRIMM Continuity (blank) RIMM CRT cathode ray tube CSM Compaq system management / Compaq server management DAC digital-to-analog converter DC direct current DCH DOS compatibility hole DDC Display Data Channel DF direct i on flag
Technical Reference Guide
Continued
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition – December 2000
1-3
Chapter 1 Introduction
Table 1-1. Acronyms and Abbreviations Continued
Acronym/Abbreviation Description
DIMM dual inline memory module DIN Deutche IndustriNorm (connector standard) DIP dual inline package DMA direct memory access DMI Desktop management i nterface dpi dots per i nch DRAM dynami c random access memory DRQ data request EDID extended display identification data EDO extended data out (RAM type) EEPROM elect ri cally eraseable PROM EGA enhanced graphics adapter EIA Elec tronic Industry Ass ociation EISA extended ISA EPP enhanced parallel port EIDE enhanced IDE ESCD Extended System Configuration Data (format) EV Environmental Variable (data) ExCA Exchangeable Card Architecture FIFO first in / first out FL flag (register) FM frequency modulation FPM fast page mode (RAM type) FPU Floating point unit (numeric or math coprocessor) FPS Frames per second ft Foot/feet GB gigabyte GMCH Graphics/memory controller hub GND ground GPIO general purpose I/ O GPOC general purpose open-coll ector GART Graphics address re-mapping t abl e GUI graphics user interface h hexadecimal HW hardware hex hexadecimal Hz Hertz (cycles-per-second) ICH I/O controller hub IDE integrated drive element IEEE Inst i t ute of Electrical and El ectronic Engineers IF interrupt flag I/F interface in inch INT interrupt I/O input/output IPL initial program loader IrDA InfraRed Data Assoc i ation IRQ interrupt request ISA indust ry standard architecture Kb / KB kilobits / kilobytes (x 1024 bits / x 1024 bytes) Kb/s kilobits per second kg kilogram KHz kilohertz kv kilovolt
Continued
1-4
Compaq Deskpro EXS and Workstation 300 Personal Computers Featuring the Intel Pentium 4 Processor
First Edition – December 2000
Technical Reference Guide
Table 1-1. Acronyms and Abbreviations Continued
Acronym/Abbreviation Description
lb pound LAN local area net work LCD liquid crystal displ a y LED light-emitting diode LIF low insertion force (socket) LPC Low pin count LSI large scale integration LSb / LSB least significant bi t / least signific ant byte LUN logical unit (SCSI) m Meter MCH Memory controller hub MMX multimedia extensions MPEG Motion Pic ture Experts Group ms millisecond MSb / MSB most significant bit / most significant byte mux multiplex MVA mot i on vi deo acceleration MVW motion video window
n
NIC network interface card/controller NiMH nickel-metal hydride NMI non-maskable interrupt NRZI Non-return-to-zero inverted ns nanosecond NT nested task flag NTSC National Televi sion Standards Commi t tee NVRAM non-volatile random access memory OS operating system PAL 1. programmable array logic 2. phase altering line PC Internet Device PCA Printed circuit assembl y PCI peripheral component interconnect PCM pulse code modulation PCMCIA Internet Device Memory Card International Associat i on PF parity flag PIN personal identification number PIO Programmed I/O POST power-on self tes t PROM programmable read-only memory PTR pointer RAM random access memory RAS row address st robe rcvr receiver RDRAM (Direct) Rambus DRAM RF resume flag RGB red/green/blue (monitor input) RH Relative humidity RIMM RDRAM inline memory module RMS root mean square ROM read-only memory RPM revolutions per minute RTC real time clock
variable parameter/value
Continued
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition – December 2000
1-5
Chapter 1 Introduction
Table 1-1. Acronyms and Abbreviations Continued
Acronym/Abbreviation Description
R/W Read/Write SCSI small comput er system interface SDRAM Synchronous Dynamic RA M SEC Single E dge-Connector SECAM sequential colour avec memoire (sequential color with memory) SF sign flag SGRAM Synchronous Graphics RAM SIMD Single instruction multipl e data SIMM single i n-l i ne memory module SIT system information table SMART Self Monitor Analysis Report Technology SMI system management interrupt SMM system management mode SMRAM system management RAM SPD serial presence detect SPDIF Sony/Philips Digit al I nt erface (IEC-958 specification) SPN Spare part number SPP standard parallel port SRAM static RAM SSE Streaming SIMD extensions STN super twist pneumatic SVGA super VGA SW software TAD telephone answering device TAFI Temperature-s ensing And Fan control Integrated ci rc ui t TAM telephone answering machine TCP tape carrier package TF trap flag TFT thin-film transistor TIA Telecommunications Inform at i on Administration TPE twisted pair ethernet TPI track per inch TTL transist or-t ransistor logic TV television TX transmit UART universal asynchronous receiver/transmitter UDMA Ultra DMA URL Uniform resource loc ator us / µs USB Universal Serial Bus UTP unshielded twisted pair Vvolt VESA Video Electronic Standards Association VGA video graphics adapter vib vibrato VLSI very large scale integration VRAM Video RAM Wwatt WOL Wake-On-LAN WRAM Windows RAM ZF zero flag ZIF zero insertion force (socket )
microsecond
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Compaq Deskpro EXS and Workstation 300 Personal Computers Featuring the Intel Pentium 4 Processor
First Edition – December 2000
Chapter 2 SYSTEM OVERVIEW
2. Chapter 2 SYSTEM OVERVIEW
2.1 INTRODUCTION
Compaq Deskpro Personal Computers (Figure 2-1) featuring the Intel Pentium 4 processor provide very high performance for advanced e-business and multimedia applications. This guide covers Compaq Deskpro EXS Minitower and the Compaq Deskpro Workstation 300 models that feature the Intel Pentium 4 processor and the Intel 850 chipset.
Technical Reference Guide
Compaq Deskpro EXS Minitower
Compaq Deskpro Workstation 300
Figure 2–1. Compaq Deskpro Personal Computers with Monitors
This chapter includes the following topics:
Features and options (2.2) page 2-2Mechanical design (2.3) page 2-4System architecture (2.4) page 2-8Specifications (2.5) page 2-13
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
2-1
Chapter 2 System Overview
2.2 FEATURES AND OPTIONS
This section describes the standard features and available options.
2.2.1 STANDARD FEATURES
The following standard features are included on all models:
Intel Pentium 4 processor in PPGA423 packageIntel 850 chipsetDual-channel Dire ct Rambus system memoryFive 33-MHz/32-bit PCI slotsOne AGP slotEmbedded Sound Blaster 128 PCI audio3.5 inch, 1.44-MB diskette drive48x Max CD-ROM driveIDE controllers with UATA/100 mode supportHard drive fault predictionOne parallel, two serial, and four USB portsAPM 1.2 power management supportPlug ’n Play compatible (with ESCD support)Intelligent Manageability supportEnergy Star compliantSecurity features including:
Flash ROM Boot Block
Diskette drive disable, boot disable, write protect
Power-on password
Administrator password
Serial/parallel port disablePS/2 Compaq Easy-Access keyboard w/Windows supportPS/2 Compaq Scroll Mouse
Table 2-1 shows the differences in standard features between the Deskpros: Table 2-1. Standard Feature Difference Matrix
Table 2-1.
Standard Feature Difference Matrix
Deskpro EXS Deskpro Workstation 300
Form Factor Minitower Convertible Minitower Standard Memory Type Installed Non-ECC ECC Communication devi ce 10/100 NIC & V.90 56K Modem 10/100 NIC only Mass Storage: Interface Type Drive Type Standard AGP Graphics Card NVIDIA GeForce2 GTS NVIDIA TNT2 Pro,
UATA100
20- or 40-MB
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Compaq Deskpro EXS and Workstation 300 Personal Computers Featuring the Intel Pentium 4 Processor
First Edition – December 2000
Ultra 160 SCSI / UATA100
18 GB / 20 GB
NVIDIA Quadro2 MXR,
ELSA Gloria II, or
Matrox Millennium G450
2.2.2 OPTIONS
The following items are available as options for all models and may be included in the standard configuration of some models:
System Memory: PC800 64-MB RIMM (non-ECC, ECC)
Hard drives/controllers: 20-, 40-GB UATA/100 hard drive
Removeable media drives:8x/4x/32x CD-RW drive
Technical Reference Guide
PC800 128-MB RIMM (non-ECC, ECC) PC800 256-MB RIMM (non-ECC, ECC)
Ultra 160 SCSI Controller 18-GB SCSI hard drive
10x/40x Max DVD-ROM drive LS-120 Super Disk drive PCI DXR DVD Decoder kit
Graphics Monitors: Compaq P700 17” CRT
Compaq P900 19” CRT Compaq P1100 21” CRT Compaq TFT5010 15” Flat Panel Compaq TFT8020 18” Flat Panel
Audio Accessories: PS115 Speakers
PS330 Speakers
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
2-3
Chapter 2 System Overview
2.3 MECHANICAL DESIGN
The following subsections describe the mechanical (physical) aspects of the covered Compaq Deskpro models.
CAUTION: Voltages are present within the system unit whenever the unit is plugged into a live AC outlet, regardless of the “Power On” condition. Always disconnect the
!
power cable from the power outlet and/or from the system unit before handling the system unit in any way. The following information is intended primarily for
identification purposes only. Before servicing these systems refer to the applicable Maintenance And Service Guide and/or Service Reference Guide.
2.3.1 CABINET LAYOUTS
2.3.1.1 Front Views
Figure 2-2 shows the front cabinet layouts of the controls and indicators.
5
4 8
1
2
Deskpro EXS
6 7 9
3
Item Description
1 Power button 2 Power LED 3 Hard drive act i vity LED 4 CD-ROM drive headphone jack 5 CD-ROM drive volum e control 6 CD-ROM drive act i vi ty LED 7 CD-ROM drive door open/cl ose button 8 1.44-MB diskette drive activit y LE D 9 1.44-MB diskette drive eject button
5
4 8
1
2
Deskpro Workstation 300
6 7 9
3
Figure 2–2. Front Cabinet Views
2-4
Compaq Deskpro EXS and Workstation 300 Personal Computers Featuring the Intel Pentium 4 Processor
First Edition – December 2000
2.3.1.2 Rear View
Figure 2-3 shows the rear cabinet layout of the controls and connectors.
10
Technical Reference Guide
1 2 3 4
6
8 9
5 7
11 12
13
14
Item Description
1 AC line In Connector (115V/230V) 2 Line voltage switch 3 Parallel I/F connector 4 PS/2 keyboard connector 5 PS/2 mouse connector 6 Serial port A connector 7 Serial port B connector 8 USB ports (4)
9 Microphone In audio jack 10 Headphone/ Li ne Out audio jack 11 Li ne I n audi o j ack 12 Ul tra SCSI connector (some Workstation models only) 13 Net work I / F connector 14 Graphi cs (RGB) monitor connect or
Figure 2–3. Rear Cabinet View
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
2-5
Chapter 2 System Overview
2.3.2 CHASSIS LAYOUT
For detailed information on servicing the chassis refer to the multimedia training CD-ROM and/or the maintenance and service guide for these systems.
Figure 2-4 shows the layout for the system in a minitower configuration. This chassis provides:
Three 5 ¼-inch drive bays and two 3 ½-inch drive baysEasy access to expansion slots and all socketed system board components.Space for either a µATX- or full ATX-type system board.
Power Supply
Chassis Fan/
Air Baffle
System Board
Back
PCI Slot 1 [1] PCI Slot 2 [1]
Graphics Card in AGP Slot
PCI Slot 3 PCI Slot 4 PCI Slot 5
NOTE:
Figure 2–4. Chassis Layout, Left Side View
Drive Bays
Front
Processor
Speaker
[1] May be populated with a V.90 56K modem in Deskpro EXS models. May be populated with an Ultra 160 SCSI adapter in sel ect Workst aton 300 models.
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Compaq Deskpro EXS and Workstation 300 Personal Computers Featuring the Intel Pentium 4 Processor
First Edition – December 2000
2.3.3 BOARD LAYOUT
These systems use an ATX-type system board. Figure 2-5 shows the location of sockets, connectors, headers, switches, jumpers, and LEDs.
27 26 25
24 23
Technical Reference Guide
2
1
3
1 7 8
5
4
6
9
10 11
12
13
15
22
Item Description Item Description
1 PCI expansion bus slot connectors 15 Power supply connector 2 AGP slot connector 16 Secondary IDE connector 3 Auxiliary audio input header 17 Power/LED connector [1] 4 Chassis f an header 18 Primary IDE connector 5 Line In, HP/Li ne Out, Mic In connectors 19 Power supply on / 5V Aux power LED 6 USB ports (4) 20 Disket te drive connector 7 Top: Serial port B ; Bottom: serial port A 21 CMOS clear button 8 Top: mouse connector, Bot.: Kybd conn. 22 Power button LED
9 Parallel port connector 23 Speaker connec tor 10 CD audio input header 24 Bat t ery 11 CPU power connector 25 3.3V aux power LED 12 Processor socket 26 AOL/SOS header 13 Channel B RIMM sockets 3, 4 27 Password clear jumper [2] 14 Channel A RIMM sockets 1, 2 -- --
NOTE:
[1] Connector for power button, Power/HD LEDs, and SCSI HD LEDs. [2] Jumper instal l ed, password enabled. Jumper removed, password cleared.
192021
18 171416
System Board
(PCA# 010821)
Figure 2–5. System Board Layout
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
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Chapter 2 System Overview
2.4 SYSTEM ARCHITECTURE
These systems feature architecture based on the Intel Pentium 4 processor and the Intel 850 chipset (Figure 2-6). These components are designed to compliment each other to provide very high desktop/minitower performance. Key technical highlights of this architecture include:
1.4 or 1.5-GHz Pentium 4 processorQuad-pumped Front Side Bus (FSB) for 400-MHz performanceDual-channel RDRAM controller supporting up to four PC800 RIMMsTwo IDE controllers supporting two UATA-100 hard drives eachSound Blaster 128 audio subsystemFive 33-MHz/32-bit PCI slotsAGP 4X slot (1.5-volt support only)One parallel portTwo serial portsFour USB portsPS/2 mouse and keyboard interfaces
The Pentium 4 processor represents Intel’s latest IA-32 microprocessor design and features a hyper-pipelined, rapid-execution engine for improved system responsiveness and higher execution throughput. Internet and multimedia performance is improved further with additional str e aming SIMD extensions (SSE2) designed to expedite video, speech, encryption, and photo processing tasks.
The 3.2 GB/s throughput of the FSB matches that of the dua l -channel RDRAM used for system memory, reducing latency and providing high, balanced performance. The 82850 Memory Controller Hub (MCH) includes an AGP 4X interface supporting a 1.5-VDC graphics card in the AGP slo t.
The 82801BA I/O Controller Hub (ICH2) and the LPC47B357 I/O Controller components provide most of the input/output functions listed previously. These systems also include an AGP 4X graphics card in the AGP slot and an Intel PRO/100+ Management Adapter (NIC) card in a PCI slot. Some models may also include a modem card and a SCSI host adapter installed in PCI slots.
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Compaq Deskpro EXS and Workstation 300 Personal Computers Featuring the Intel Pentium 4 Processor
First Edition – December 2000
Pentium 4
p
Processor
Technical Reference Guide
RGB
Graphics
Controller
Card
AGP Slot
UATA/100 Hard Drive
CD
Audio
Audio
Subsystem
Power
Supply
Beep Audio
AGP
4X I/F
Pri. IDE
I/F
Sec. IDE
I/F
33-MHz 32-Bit PCI Bus
PCI Slot 5
400- MHz FSB
850 Chipset
82850
MCH
Hub Link Bus
82801BA
ICH2
PCI Slot 4
RDRAM
Cntlr.
USB
I/F (4)
82802
FWH
Modem Card
PCI Slot 3
Channel A RDRAM Bus
Channel B RDRAM Bus
LPC Bus
V.90
56K
PCI
PC800
RIMM Pair(s)
PC800
RIMM Pair(s)
Serial I/F (2)
LPC47B357 I/O Controller
Keyboard/ Mouse I/F
Intel
PRO/100+
Mgmt.
Adapter Card
PCI Slot 2
Parallel
I/F
Diskette
I/F
SCSI
Hard Drive
Adaptec 29160N
SCSI
ter Card
Ada
PCI Slot 1
Some Deskpro Workstation 300 model s. Some Deskpro EXS models.
Figure 2–6. System Architecture, Block diagram
Compaq Deskpro EXS and Workstation 300 Personal Computers
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Featuring the Intel Pentium 4 Processor
First Edition - December 2000
Chapter 2 System Overview
2.4.1 PENTIUM 4 PROCESSOR
These systems feature the Intel Pentium 4 processor featuring Intel’s NetBurst Micro­Architecture. This processor is backward-compatible with software written for the Pentium III/II, Pentium MMX, Pentium Pro, Pentium, and x86 microprocessors.
Key features of the Pentium 4 processor include:
Hyper-Pipelined Technology for higher p erformanceRapid Execution Engine with increased throughput and reduced latencyQuad-pumped Front Side Bus (FSB) for balanced performance with RDRAMExecution Trace Cache for more efficient branch-handlingImproved dynamic execution for higher efficiencyAdditional Streaming SIMD Extensions (SSE2) for increased video, audio, and speech
processing
On-die (full speed) 256-KB ECC second-level cache
These systems employ a PGA423 zero-insertion-force (ZIF) socket designed for mounting a “Flip­Chip” (FC-PGA423) processor package (Figure 2-7).
Heat Sink
Retaining Clip
Heat Sink Retaining Clip
Heat Sink
FC-PGA423
Lock/Unlock
Handle
(Shown in unlock position)
Package
PGA423 Socket
Figure 2–7. Processor Assembly And Mounting
The PGA423 socket allows easy changing/upgrading of the processor. Raising the Lock/Unlock handle of the socket in the vertical position allows the processor package to be removed or inserted into the socket. Lowering the Lock/Unlock handle in the down (horizontal) position locks the processor package in place. The heat sink is placed on top of the processor and held in place by two retaining clips.
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Compaq Deskpro EXS and Workstation 300 Personal Computers Featuring the Intel Pentium 4 Processor
First Edition – December 2000
2.4.2 CHIPSET
The chipset consists of a Memory Controller Hub (MCH), an I/O Controller Hub (ICH), and a FirmWare Hub (FWH). Table 2-2 lists the integrated functions provided by the two types of chipsets used in these systems.
Table 2-2. Chipset Comparison
Chipset Component Function
850 82850 MCH AGP 4X interface
Technical Reference Guide
Table 2-2.
Chipset Comparison
Dual-channel RDRAM controller supporti ng up to 4 PC800 RIMMs 400-MHz FSB
82801BA ICH2 PCI bus I/F
LPC bus I/F SMBus I/F IDE I/F with UATA/100 support AC ’97 controller RTC/CMOS IRQ controller Power management logic USB I/F (4) 8259 and I/O APIC interrupt processing
82802 FWH Loaded with Compaq BIOS
2.4.3 SUPPORT COMPONENTS
Input/output functions not provided by the chipset are handled by other support components. Table 2-3 shows the functions provided by the support components.
Table 2-3. Support Component Functions
Support Component Functions
Component Name Function
LPC47B357 7 I/O Controller Keyboard and pointing device I/F
ES1373 PCI audio controller CS4297A Audio Codec Audio mixer
Table 2-3.
Diskette I/F Serial I/F (COM1and COM2) Parallel I/F (LPT1, LPT2, or LP T3) AGP, PCI reset generati on ISA serial IRQ converter Power button and LED control logic GPIO ports
Digital-to-analog converter Analog-to-digital converter Analog I/O
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
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Chapter 2 System Overview
2.4.4 SYSTEM MEMORY
These systems feature a dual-channel Direct Rambus (RDRAM) architecture. Capable of a peak data throughput of 3.2 GB / s ec., this high-performance memory design represents a new generation of memory subsystems that can keep pace with ever-increasing processor performance. These systems each provide a total of four RIMM sockets, all of which will be populated with either PC800 RDRAM memory modules (RIMMs) or continuity modules (CRIMMs). Up to two gigabytes of memory may be installed.
Compaq Deskpro EXS systems are shipped with non-ECC PC800 RIMMs. Compaq Deskpro Workstation 300 systems are shipped with ECC PC800 RIMMs. Both systems support ECC and non-ECC RIMMs.
2.4.5 MASS STORAGE
All models include a 3.5 inch 1.44-MB diskette drive installed as drive A. Most models also include a CD-ROM drive. The Deskpro EXS and some Deskpro Workstation 300 models will include a UATA100 (EIDE) hard drive while select Deskpro Workstation 300 models will include an Ultra 160 SCSI controller (PCI) card and SCSI hard drive. Standard hard drives feature Drive Protection System (DPS) support, which uses industry-standard function ATAPI-5 to check drive integrity. Standard drives also use SMART III technology that tests drive data during periods of drive inactivity for corruption.
2.4.6 SERIAL, PARALLEL INTERFACES
All models include two serial ports and a parallel port accessible at the rear of the chassis. Each serial port is RS-232-C/16550-compatible and supports standard baud rates up to 115,200 as well as high-speed baud rates of 230K and 460K, and uses a DB-9 connector. The parallel interface is Enhanced Parallel Port (EPP1.9) and Enhanced Capability Port (ECP) compatible, and supports bi-directional data transfers through a D B-25 connector.
2.4.7 UNIVERSAL SERIAL BUS INTERFACE
All models feature four Universal Serial Bus (USB) ports that provide a 12Mb/s interface for peripherals. The USB provide s hot plugging/unplugging (Plug ’n Play) functionality.
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Compaq Deskpro EXS and Workstation 300 Personal Computers Featuring the Intel Pentium 4 Processor
First Edition – December 2000
2.4.8 GRAPHICS SUBSYSTEM
Each of these systems provides an AGP slot that accommodates a Type 1 or Type 2 AGP graphics adapter (1.5-V only).
Table 2-4 lists the key features of the types of graphics adapters available as standard in these systems:
Table 2-4. Standard AGP Graphics Card Comparison
Standard AGP Graphics Card Comparison
NVIDIA
GeForce2 GTS
Std. Config. In EXS Wkstn. 300 Wkstn. 300 Wkstn. 300 Wkstn. 300 Recommended for: Bus Type AGP 4X AGP 2X/4X AGP 2X/4X AGP 2X/4X AGP 2X/4X Mem. Amount 32 MB 16 MB 32 MB 64 MB 32 MB Mem. Type SDRAM SGRAM SDRAM SDRAM DDR SDRAM DAC Speed 350 MHz 300 MHz 350 MHz 350 MHz Max. 2D Res. @ # of colors Software Compatibility
Special Features/ Accelerators
Aux. I/O VESA I/F VESA I/F VESA I/F VESA I/F VESA I/F Outputs 1 RGB 1 RGB 1 RGB, 1 DVI 1 RGB 2 RGB
NOTE:
Hi 2D,
Entry 3D
2048x1536
@ 16.7M
Quick Draw,
DCI/DirectX,
Direct Draw,
3D OGL,
MPEG 1/2
3ROP BitBLT,
Line Draw,
Color Expan.
Triangle Eng,
Anti-aliasing,
HDTV proc.,
FS Anti­aliasing,
32b color &
stencil,
Alpha planes
Table 2-4.
NVIDIA
TNT2 PRO
Hi 2D,
Entry 3D
1920x1200
@ 16.7M
Quick Draw, DCI/DirectX, Direct Draw,
Direct Show,
MPEG 1/2,
Indeo
Transparent
BLT,
Stretch BLT,
Polylines, Polygons,
Fills,
32b render,
24b Z-buffer, 8b
stencil,
Anisotropic
filtering,
128b TnT
Archit.
NVIDIA
Quadro2 MXR
Hi 2D,
Entry 3D
1920x1200
@ 16.7M Quick Draw, DCI/DirectX, Direct Draw,
Direct Show,
MPEG 1/2,
Indeo
Shading
rasterizer,
Digital vibrance
control,
32b render,
24b Z-buffer, 8b
stencil,
Anisotropic
filtering,
Twin View arch.
supporting
2-head Win. &
2-head clone,
Technical Reference Guide
ELSA
GLoria II
Hi 2D,
Mid 3D
2048x1536
@ 16.7M
Quick Draw,
DCI/DirectX,
Direct Draw,
ActiveX,
MPEG 1/2,
OpenGL
DVD support,
24b dbl-
buffered color
planes,
8b stencil,
24b Z-buffer,
stereo support,
Millennium
Multi-monitor
2048x768
Quick Draw, DCI/DirectX, Direct Draw,
MPEG 1/2,
OpenGL,
Direct 3D
3ROP BitBLT, Dual RAMDAC, Flat & Gouraud
shading,
Anisotropic
Perspective
Texture,
Specular highlighting, 32b z-buffer,
2-head zoom,
2-head clone,
2-head TV,
DVD max mode
Matrox
G450
Hi 2D
@ 65K
filtering,
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
2-13
Chapter 2 System Overview
2.4.9 AUDIO SUBSYSTEM
All models feature an embedded Sound Blaster 128 PCI audio system using the AC’97 ver. 2.1 specification-based design. The subsystem features a Creative Labs, Inc. ES1373 audio controller and a Cirrus Logic CS4297A audio codec. The output of the audio codec is applied to a 3-watt amplifier that drives the chassis’ internal speaker. Standard microphone and line input jacks are provided as well as a tri-purpose headphone/line/digital output jack that allows the use of headphones or a pair of powered speakers (optional). The output jack also provides a digital audio output signal using the Sony/Philips Digital Interface (SPDIF) format (officially known as IEC-
958).
2.5 SPECIFICATIONS
This section includes the environmental, electrical, and physical specifications for the Compaq Deskpro EXS and Workstation 300 Series Personal Computers. Where provided, metric statistics are given in parenthesis. All specifications subject to change without notice.
Table 2-5. Environmental Specifications
Table 2-5.
Environmental Specifications (Factory Configuration)
Parameter Operating Nonoperating
Ambient Air Temperature 50o to 95o F (10o to 35o C, max. rate
of change < 10°C/Hr) Shock (w/o damage) 5 Gs [1] 20 Gs [1] Vibration 0.000215 G2/Hz, 10-300 Hz 0.0005 G2/Hz, 10-500 Hz Humidity 10-90% Rh @ 28o C max.
wet bulb temperature Maximum Altitude 10,000 ft (3048 m) [2] 30,000 ft (9, 144 m) [2]
NOTE:
[1] Peak input accel erat i on duri ng an 11 ms half-sine shock pulse. [2] Maximum rate of change: 1500 ft/min.
-24o to 140o F (-30o to 60o C, max. rate of change < 20°C/Hr )
5-95% Rh @ 38.7o C max.
wet bulb temperature
Table 2-6. Electrical Specifications
Table 2-6.
Electrical Specifications
Parameter U.S. International
Input Line Voltage: Nominal: Maximum: Input Line Frequency Range: Nominal: Maximum: Power Supply: Maximum Continuous Power Maximum Line Current Draw
110 - 127 VAC
90 - 132 VAC
50 - 60 Hz 47 - 63 Hz
watts
A
200 - 240 VAC 180 - 264 VAC
50 - 60 Hz 47 - 63 Hz
watts
A
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Compaq Deskpro EXS and Workstation 300 Personal Computers Featuring the Intel Pentium 4 Processor
First Edition – December 2000
Technical Reference Guide
Table 2-7. Physical Specifications
Table 2-7.
Physical Specifications
Parameter Desktop Configuration Minitow er Confi guration
Height 6.60 in (16.76 cm) 17.65 in (44.83 cm) Width 17.65 in (44. 83 cm) 6.60 in (16.76 cm) Depth 17.11 in (43.46 cm) 17.11 in (43.46 cm) Weight (nom.) [1] 26 lb (11.8 kg) 26 lb (11.8 kg) Maximum Supported W e i ght [2] 100 N/A
NOTES:
[1] System weight may vary depending on installed drives/peripheral s. [2] Assumes reasonable article(s) such as a display monitor and/or another s ystem unit.
Table 2-8. Diskette Drive Specifications
Table 2-8.
Diskette Drive Specifications
(Compaq SP# 179161-001)
Parameter Measurement
Media Type 3.5 in 1.44 MB/720 KB diskette Height 1/3 bay (1 in) Bytes per Sector 512 Sectors per Track: High Density Low Density Tracks per Side: High Density Low Density Read/Write Heads 2 Average Access Time: Track-to-Track (high/low) Average (high/low) Settling Time Latency Average
18
9
80 80
3 ms/6 ms
94 ms/173ms
15 ms
100 ms
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
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Chapter 2 System Overview
Table 2-9. 48x CD-ROM Drive Specifications
48x CD-ROM Drive Specifications
Parameter Measurement
Interface Type IDE Transfer Rate: Max. Sustained Burst Media Type Mode 1,2, Mixed Mode, CD-DA,
Capacity: Mode 1, 12 cm Mode 2, 12 cm 8 cm Center Hole Diameter 15 mm Disc Diameter 8/12 cm Disc Thickness 1.2 mm Track Pitch 1.6 um Laser Beam Divergence Output Power Type Wave Length
Average Access Time: Random Full Stroke Audio Output Level 0.7 Vrms Cache Buffer 128 KB
Table 2-9.
(SP# 187217-B21)
4800 KB/s
16.6 MB/s
Photo CD, Cdi, CD-XA
550 MB 640 MB 180 MB
53.5 +/- 1.5 °
53.6 0.14 mW GaAs
790 +/- 25 nm
<100 ms <150 ms
Table 2-10. Hard Drive Specifications
Table 2-10.
Hard Drive Specifications
Parameter 18.0 GB 20.0 GB 40.0 GB
Drive Size 3.5” 3.5” 5.25” Interface Ultra 160 SCSI UATA/100 UATA/100 Drive Protection System Support? Yes Yes Yes Transfer Rate (max) 160 MB/s 100 MB/s 100 MB/s Typical Seek Time (w/sett l i ng) [ 1] Single Track Average Full Stroke Disk Format (logic al ): # of Cylinders # of Data Heads # of Sectors per Track Rotation Speed 10,000 RPM 7200 RPM 7200 RPM Drive Fault Prediction SMART III SMART III SMART III
NOTE:
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Compaq Deskpro EXS and Workstation 300 Personal Computers
Actual times may vary depending on specific dri ve installed. All EMEA units feat ure Qui et Dri ves. [1] Operates at 66 MB/s in t hese systems.
Featuring the Intel Pentium 4 Processor
1.7 ms
8.5 ms 15 ms
16383
16 63
2.0 ms
9.5 ms 21 ms
16383
16 63
1.0 ms
9.0 ms 20 ms
16383
16 63
First Edition – December 2000
Chapter 3 PROCESSOR/ MEMORY SUBSYSTEM
3. Chapter 3 PROCESSOR/MEMORY SUBSYSTEM
3.1 INTRODUCTION
This chapter describes the processor/memory subsystem of Compaq Deskpro Personal Computers featuring the Pentium 4 processor. These systems feature the Pentium 4 processor and the 850 chipset (Figure 3-1). The 82850 MCH component of the 850 chipset supports two Direct Rambus channels, each channel accommodating one or two RIMMs.
Pentium 4 Processor
Technical Reference Guide
400-MHz 64-Bit FSB
FSB I/F
AGP
I/F
Will be populated with optional RIMM or CRIMM
Covered in Chapter 6 Covered in Chapter 4
82850
MCH
Hub I/F
Cntl
Rambus
Cntlr.
Rambus Channel 1 /16
Rambus Channel 2 /16
Figure 3–1. Processor/Memory Subsystem Architecture
This chapter includes the following topics:
Pentium 4 processor [3.2] page 3-2Memory sub system [3.3] page 3-5Subsystem configuration {3.4] p age 3-8
XMM1
RIMM
In
Socket
System Memory
XMM2
RIMM
Socket
XMM3
RIMM
Socket
XMM4
RIMM
In
Socket
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Chapter 3 Processor/Memory Subsystem
3.2 PENTIUM 4 PROCESSOR
These systems each feature an Intel Pentium 4 processor in a FC-PGA423 package mounted with a passive heat sink in a PGA423 (W-type) zero-insertion force socket. The mounting socket allows the processor to be easily changed for servicing and/or upgrading.
3.2.1 PROCESSOR OVERVIEW
The 1.4-/1.5-GHz Intel Pentium 4 processor represents the latest generation of Intel’s IA32-class of processors. Featuring Intel’s NetBurst architecture, the Pentium 4 processor is designed for intensive multimedia and internet applications of today and the future while maintaining compatibility with software written for earlier (Pentium III, Pentium II, Pentium, Celeron, and x86) microprocessors. Key features of the Pentium 4 processor include:
Hyper-Pipelined Technology – The main processing loop has twice the depth (20 stages) of
the Pentium III allowing for increased processing frequencies.
Execution Trace Cache – A new feature supporting the branch prediction mechanism, the
trace cache stores translated sequences of branching micro-operations (µops) and is checked when suspected re-occurring branches are detected in the main processing loop. This feature allows instruction decoding to be removed from the main processing loop.
Rapid Execution Engine – Arithmetic Logic Units (ALUs) run at twice (2x) processing
frequency for higher throughput and reduced latency.
256-KB Advanced transfer L2 cache – Using 32-byte-wide interface at processing speed, the
L2 cache can provide 48 GB/s perrformance (3x over the Pentium III)
Advanced dynamic execution – Using a larger (4K) branch target buffer and improved
prediction algorithm, branch mis-predictions are reduced by an average of 33 % over the Pentium III.
Enhanced Floating Point Processor - With 128-bit integer processing and deeper pipelining
the Pentium 4’s FPU provides a 2x performance boost over the Pentium III.
Additional Streaming SIMD extensions (SSE2) – In addition to the SSE support provided by
previous Pentium processors, the Pentium 4 processor includes an additional 144 MMX instructions, fur t her enhancing:
Streaming video/audio processing
Photo/video editing
Speech recognition
3D processing
Encryption processing
Quad-pumped Front Side Bus (FSB) – The FSB uses a 100-MHz clock for qualifying the
buses’ control signals. However, address information is transferred using a 200-MHz strobe while data is transferred with a 400-MHz strobe, providing a maximum data transfer rate of
3.2 GB/s. This is a 3x boost over a Pentium III with a 133-MHz FSB. The 3.2 GB/s peak transfer rate of the FSB balances the 3.2 GB/s maximum transfer capability of the dual­channel Direct Rambus system memory.
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Figure 3-1 illustrates the internal architecture of the Pentium 4 processor.
Pentium 4 Process or
Technical Reference Guide
Branch
Prediction
Rapid Exe. Eng.
ALUs
ALU Speed: 2.8 GHz w/Pentium 4 @ 1. 4 GHz
Core Speed: 1.4 GHz w/Pentium 4 @ 1.4 GHz
FSB Speed: 400 MHz (Data transfer rate)
Execution
Trace Cache
CPU
Out-of-
Order Core
3.0 GHz w/Pentium 4 @ 1.5 GHz
1.5 GHz w/Pentium 4 @ 1.5 GHz
128-bit
Integer
FPU
FSB
I/F
L1
Data
Cache
256-KB
8-Way
L2
Adv.
Transfer
Cache
Figure 3–2. Pentium 4 Processor Internal Architecture
The Pentium 4 increases processing speed with higher clock speeds made possible with hyper­pipelined technology that can handle significantly more instructions at a time. Since branch mis­predicts would result in serious performance hits with such a long pipeline, the Pentium 4 features a branch prediction mechanism improved with the addition of an execution trace cache and a refined prediction algorithm. The execution trace cache can store 12k micro-ops (decoded instructions dealing with branching sequences) that are checked when re-occurring branches are processed. Code that is not executed (bypassed) is no longer stored in the L1 cache as was the case in the Pentium III.
The out-of-order core features Advanced Dynamic Execution, which provides a large window (126 instructions) for execution units to work with. A more accurate branch prediction algorithm, along with a larger (4-KB) branch target buffer that stores more details on branch history results in a 33% reduction in branch mis-predictions over the Pentium III.
The L1 data cache features a low-latency design for minimum response to cache hits. The 256-KB advanced transfer L2 cache features a 256-bit (32-byte) interface operating at processing speed. The L2 cache of the 1.5 GHz Pentium 4 can therefore provide a transfer rate of 48 GB/s.
The combined improvements of the Pentium 4’s CPU core the rapid execution engine’s ALUs to operate at twice the processing frequency to handle the steady stream of instructions.
The front side bus (FSB) of the Pentium 4 uses a 100-MHz clock but provides Quad-pumped data transfers. While the Pentium III could transfer 8 bytes of data on a 133-MHz clock cycle the Pentium 4 can transfer 32 bytes of data on a 100-MHz clock cycle for a throughput rate of 3.2 GB/s, balancing the performance of the dual-Rambus memory subsystem. Address information is transferred at a 200-MHz rate.
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Chapter 3 Processor/Memory Subsystem
The Pentium 4 processor is software-compatible with Celeron, Pentium II, Pentium MMX, Pentium, and x86 processors, but will require the latest versions of operating system software to take advantage of the Streaming SIMD extensions (SSE2).
3.2.2 PROCESSOR UPGRADING
All units use the PGA423 ZIF mounting socket and ship with the Pentium 4 processor in a Flip­Chip (FC-PGA423) package installed with a passive heat sink. The FC-PGA423 package consists of the processor die mounted “upside down” on a PC board. This arrangement allows the heat sink to come in direct contact with the processor die. The heat sink and attachment clip are specially designed provide maximum heat transfer from the processor component.
CAUTION: Attachment of the heat sink to the processor is critical on these systems. Improper attachment of the heat sink will likely result in a thermal condition.
!
Although the system is designed to detect thermal conditions and automatically shut down, such a condition could still result in damage to the processor component. Refer to the applicable Maintenance and Service Guide for processor installation instructions.
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3.3 MEMORY SUBSYSTEM
The 82850 MCH features Direct Rambus technology and supports two Rambus channels, each channel supporting up to two Rambus DRAM modules (RIMMs). Direct Rambus technology provides a significant improvement in performance over DRAM/SDRAM memory designs and allows the system memory to keep pace with increasing processor performance. Rambus technology implements RDRAM devices accessed over a channel specifically designed for high speed operations.
As shown in Figure 3-3, the conventional DRAM-based memory interface with a transfer rate of 66, 100, or 133 MHz increases bandwidth by widening the data bus. With the current top speed of 133 MHz, a 64-bit SDRAM interface achieves a maximum transfer rate of 1.0 GB/s.
Byte 0 Byte 1 Byte 2
SDRAM Memory
Controller
Byte 3 Byte 4 Byte 5 Byte 6
DIMM
RDRAM Memory
Controller
Technical Reference Guide
Byte 0
Byte 1
Byte 2
Byte 3
Ch 1
RIMM
Ch 2
RIMM
Byte 7
SDRAM Interface
64-bit Path
8 bytes @ 133 MHz = 1.0 GB/s
RDRAM Interface (Dual Channel)
32-bit Path
4 bytes @ 400 MHz = 3.2 GB/s (see text)
Figure 3–3. SDRAM/RDRAM Bandwidth Comparison
Although a Rambus channel handles only two bytes per tra nsfer, data is clocked on bot h t he rising and falling edges of the clock signal, allowing a 400-MHz clock to provide an effective speed of 800 MHz and resulting a transfer rate of 1.6 GB/s. Doubling the number of channels doubles the throughput. These systems feature dual-c hannel RDRAM architec ture that provi des a maximum transfer rate of 3.2 GB/s.
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Chapter 3 Processor/Memory Subsystem
3.3.1 RAMBUS ATTRIBUTES
To ensure signal quality during high-speed memory transfers, the Rambus interface design departs from previous memory interface designs in several key aspects (Figure 3-4). Rambus uses a daisy­chained signal distribution system that requires that all memory sockets be populated with either a RIMM or a continuity module (CRIMM) in order to maintain constant load impedance. Rambus Signaling Levels (RSL) uses a 1.4-volt reference with a 0. 8-volt swing between logic 0 at 1.8 V and logic 1 at 1.0 V.
On these systems RIMMs (or CRIMMs) must be installed in pairs (one module for each channel). A maximum of two gigabytes of memory may be installed using 512-MB RIMMs. These systems ship with PC800 (400-MHz) RIMMs but will also accept PC700 or PC600 RIMMs. A mix of ECC and non-ECC RIMMs may be installed, although all RIMMs must be ECC to realize ECC benefits.
RIMM
RIMM or CRIMM (Shown)
RIMM
MCH
Signal Name
ROW 2..0 3 O RSL 28 ohm s Row address COL 4..0 5 O RSL 28 ohms Col umn address DQA 8..0 9 I/O RSL 28 ohms Data byte A (w/parity or ECC bit) DQB 8..0 9 I/O RSL 28 ohms Data byte B (w/parity or ECC bit) CFM, CFMN 2 O RSL [2] 28 ohms 400-MHz Clock -f rom-master for writes CTM, CTMN 2 I RSL [2] 28 ohms 400-MHz Clock-to-master for reads Vref 1 -- 1.4 V -- Reference volt age for RSL signals SIO 1 I/O CMOS -- Serial I/F for initialization & pwr cntrl. SCK 1 O CMOS 56 ohms SIO clock ; 1 MHz for configuration,100
CMD 1 I/O CMOS 56 ohms Seri al I /F config. & power control Vdd -- 2.5 V -- Power for Rambus ci rcuitry
NOTES:
[1] Relative to the memory controller. [2] Differential pair with Ep-p swing of 400 to 600 mV.
Channel 1
No. of
Lines
Channel 2
RIMM Sock ets
Rambus Signal Attributes (Each Channel)
Input/
Output [1]
Signal
Level Impedance Function
Bus Termination
MHz for power management.
Figure 3–4. Rambus Channel Signal Distribution and Key Attributes
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3.3.2 RAMBUS CHANNEL TRANSACTIONS
Transactions on the Rambus Channel involve packets of control (row or column) bits and packets of data bits. Each packet consists of eight segments, with even segments transferred on falling clock edges and odd segments transferred on rising clock edges. A typical operation consists of the memory controller sending out a 24-bit row packet followed by a 40-bit column packet and then the 144-bit (128-bit for non-ECC) data packet being either written to or read from RDRAM (Figure 3-5).
Technical Reference Guide
Trc Tcd
0 1 2 3 4 5 6 7
Vref = 1.4
Clock
ROW 2..0
COL 4..0
DQA 8..0 DQB 8..0
NOTE:
Tn [1]
0 1 2 3 4 5 6 7
Row Packet Column Packet Data Packet
[1] Tn = 1.25 ns @ 400 MHz (PC800) = 1.42 ns @ 350 MHz (PC700) = 1.66 ns @ 300 MHz (PC600)
Figure 3–5. Rambus Transactio ns (Single Channel)
Logic 0 = 1.8 V
0 1 2 3 4 5 6 7
Logic 1 = 1.0 V
The clock signal is driven by the source device (i.e., by the memory controller during writes, by the RDRAM device during reads). The row (ROW) and column (COL) signal lines are driven only by the memory controller and assume the functions provided by the RAS/CAS signals of traditional memory buses. The ROW and COL signals are also used for power management and defining the type (read/write) of transaction. The data lines (DQAx/DQBx) are bi-directional, being driven by the controller during writes and by the RDRAM during reads. There is a specified delay period between related Row and Column packets (Trc, typically 7 clock cycles) and related column and data packets (Tcd, typically 8 to 12 clock cycles).
Note that while Figure 3-5 illustrates a single Rambus transaction, actual operation can involve pipelined transactions where back-to-back column packets are sent followed by back-to-back data packets. A row packet may be omitted if the row to be accessed is already open. Another important characteristic is that the ROW, COL, and DQA/DQB signal lines act as independent buses and simultaneous transfers of row, column, and data information can take place.
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3.3.3 RDRAM POWER MANAGEMENT
The Rambus architecture provides for power management of each RDRAM device on a RIMM. RDRAM power management control is compatible with but may also work independently of ACPI. Power management o f RDRAM is handled through control packets as well as the serial bus. Aside from complete “system off” state, an RDRAM may be placed in one of four basic power states:
ActiveStandbyNapPowerdown
These states are characterized by parameters such as power consumed, refresh method, and the time required to resume full (Active state) operation. The following table defines the RDRAM power states.
State
Powerdown 1 mW S el f Stopped
Nap 10 mW MCH On 90 ns Low power state. Can remain in this state for up
Standby 250 mW MCH On 20 ns Idle power state automatically entered after a
Active 500 mW MCH On -- Full power state. Available to receive control
NOTES:
[1] Per RDRAM device [2] Transition to Active state
Power
Consumed [1]
Refresh
Method
RDRAM
CLK
3.3.4 RDRAM CONFIGURATION/CONTROL
The Rambus architecture employs a CMOS-level serial bus (SIO, SCK, CMD) similar to that used on SDRAM-equipped systems. This bus is used for status and control of RDRAM configuration parameters as well as bringing RDRAM devices out of Powerdown and Nap states. The SIO signal is bi-directional and daisy-chai ned through all RDRAM devices, alternating from SIO0 to SI O1 between devices . The SCK and CMD signals are applied in parallel to all RDRAM devices. The SCK signal operates at 1 MHz during configuration and at 100 MHz when commands are issued to switch RDRAM devices from Powerdown or Nap states.
Exit
Latency [2]
12 µs
RDRAM Functionality
Lowest power state and condition entered after initialization. Can remain in thi s s tat e indef init ely. Brought out of Powerdown only by command over the SIO serial bus.
to 10 µs. Brought out of Nap only by com mand over the SIO serial bus.
transaction. Available to receive row packets. Transitions to Act ive or Nap state upon receipt of specific command on ROW bus .
packets and transm i t or receive data packets.
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Technical Reference Guide
(
)
The memory controller and RDRAM are configured by BIOS during POST. Refer to Chapter 8 for the configuration procedure performed by BIOS.
Figure 3-6 shows the system memory map.
Host,
PCI, AGP Area
Host, PCI,
ISA Area
DOS Compatibility
Area
FFFF FFFFh FFE0 0000h
FFDF FFFFh
FEC1 0000h
FEC0 FFFFh
FEC0 0000h
FEBF FFFFh
2000 0000h
1FFF FFFFh
0100 0000h
00FF FFFFh
0010 0000h
000F FFFFh
000F 0000h
000E FFFFh
000E 0000h
000D FFFFh
000C 0000h 000B FFFFh
000A 0000h 0009 FFFFh
0008 0000h
0007 FFFFh
High BIOS Area
(2 MB)
PCI Memory
(18 MB)
APIC Config. Space
(64 KB)
PCI Memory
Expansion (3060 MB)
Host/PCI Memory
Expansion
(496 MB)
Extended Memory
15 MB
System BIOS Area
(64 KB)
Extended BIOS
Area
Option ROM
(128 KB)
Graphics/SMRAM
RAM (128 KB)
Fixed Mem. Area
(128 KB)
4 GB
512 MB
16 MB
1 MB
640 KB
512 KB
Base Memory
(512 KB)
0000 0000h
NOTE: All locations in memory are cacheable. Base memory is always m apped to DRAM. The next 128 KB fixed memory area can, through t he MCH, be mapped to DRAM or to PCI space. Graphi cs RAM area is mapped to PCI or AGP loc ations.
Figure 3–6. System Memory Map
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Chapter 3 Processor/Memory Subsystem
3.4 SUBSYSTEM CONFIGURATION
The MCH component provides the configuration function for the processor/memory subsystem. Table 3-1 lists the configuration registers used for setting and checking such parameters as memory control and PCI bus operation. These registers reside in the PCI Configuration Space and accessed using the methods described in Chapter 4, section 4.2.
Table 3–1. Host/PCI Bridge Configuration Registers (GMCH, Funct i on 0)
Host/PCI Bridge Configuration Registers (MCH, Device 0)
PCI Config. Addr.
00, 01h Vender ID 8086h 6A, 6Bh DRAM Control Reg. 00h 02, 03h Device ID 1130h 6C..6Fh Memory Buffer Strength 55h 04, 05h Command 0006h 70h Multi-Trans action Timer 00h 06, 07h Status 71h CPU Latency Timer 10h 08h Revision ID -- 72h SMRAM Control 02h 0A..0Bh Class Code -- 90h Error Comm and 00h 0Dh Latency Timer 00h 91h Error Stat us Register 0 00h 0Eh Header Type 00h 92h Error S t atus Register 1 00h
10..13h Aperture Base Config. [2] 93h Reset Control 00h 50, 51h PAC Config. Reg. 00h A0..A3h AGP Capability Identifier N/A 53h Data Buffer Control 83h A4.. A7h AGP Status N/ A
55..56h DRAM Row Type 00h A8..ABh AGP Command 00h 57h DRAM Control 01h B0..B3h AGP Control 00h 58h DRAM Timing 00h B4h Aperture Size 0000h
59..5Fh PAM 0..6 Registers 00h B8..BBh Aperture Translation Table 0000h
60..67h DRAM Row Boundary 01h BCh Aperture I/F Timer 00h 68h Fixed DRAM Hole 00h BDh Low Priority Timer 00h
Register
Reset Value
Table 3-1.
PCI Config. Addr.
R egister
Reset
Value
NOTES:
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Chapter 4 SYSTEM SUPPORT
4. Chapter 4 SYSTEM SUPPORT
4.1 INTRODUCTION
This chapter covers subjects dealing with basic system architecture and covers the following topics:
PCI bus overview (4.2) page 4-2AGP bus overview (4.3) page 4-10System resources (4.4) page 4-15System clock distribution (4.5) page 4-20Real-time clock and configuration memory (4.6) page 4-20System management (4.7) page 4-31Register map and miscellaneous functions (4.8) page 4-35
This chapter covers functio ns provided by off-the-shelf chipsets and therefore d escribes only basi c aspects of these functions as well as information unique to the sytems covered in this guide. For detailed information on specific components, refer to the applicable manufacturer’s documentation.
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Chapter 4 System Support
4.2 PCI BUS OVERVIEW
NOTE: This section describes the PCI bus in general and highlights bus implementation in this particular system. For detailed information regarding PCI bus operation, refer to the PCI Local Bus Specification Revision 2.2.
This system implements a 32-bit Peripheral Component Interconnect (PCI) bus (spec. 2.2) operating at 33 MHz. The PCI bus handles a ddress/data transfers through the i dentification of devices and functions on the bus. A device is typically defined as a component or slot that resides on the PCI bus (although some compo nents suc h as the MCH and ICH are organized as multiple devices). A function is defined as the end source or target of the bus transaction. A device may contain one o r more functions.
In the standard configuration these systems use a hierarchy of three PCI buses (Figure 4-1). The PCI bus #0 is internal to the MCH/ICH chipset components and is not physically accessible. The AGP bus that services the AGP slot is designated as PCI bus #1. All PCI slots reside on PCI bus #2.
82850 MCH Component
Mem. Cnt lr.
Function
Hub Link I/F
PCI Bus #0
AGP
Bridge
Function
PCI Bus #1 (AGP Bus)
AGP Connector
Hub Link Bus
Hub Link I/F
PCI Bridge
Function
PCI Bus #2
Not used in these systems.
NIC
I/F
Function
ES1373
Controller
Audio
PCI Connector 1
82801BA ICH2 Component
PCI Bus #0
EIDE
Controller
Function
PCI Connector 2
PCI Connector 3
Figure 4-1. PCI Bus Devices a nd Functions
USB
I/F
Function
PCI Connector 4
PCI Connector 5
SMBus
Controller
Function
LPC
Bridge
Function
AC97 Audio
Function
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4.2.1 PCI BUS TRANSACTIONS
The PCI bus consists of a 32-bit path (AD31-00 lines) that uses a multiplexed scheme for handling both address and data transfers. A bus transaction consists of an address cycle and one or more data cycles, with each cycle requiring a clock (PCICLK) cycle. High performance is realized during burst modes in which a transaction with contiguous memory locations requires that only one address cycle be conducted and subsequent data cycles are completed using auto-incremented addressing. Four types of address cycles can take place on the PCI bus; I/O, memory, configuration, and special. Address decoding is distributed (left up to each device on the PCI bus).
4.2.1.1 I/O and Memory Cycles
For I/O and memory cycles, a standard 32-bit address decode (AD31..0) for byte-level addressing is handled by the appropriate PCI device. For memory addressing, PCI devices decode the AD31..2 lines for dword-level addressing and check the AD1,0 lines for burst (linear­incrementing) mode. In burst mode, subsequent data phases are conducted a dword at a time with addressing assumed to increment accordingly (four bytes at a time).
Technical Reference Guide
4.2.1.2 Configuration Cycles
Devices on the PCI bus must comply with PCI protocol that allows configuration of that device by software. In this system, configuration mechanism #1 (as described in the PCI Local Bus specification Rev. 2.1) is employed. This method uses two 32-bit registers for initiating a configuration cycle for accessing the configuration space of a PCI device. The configuration address register (CONFIG_ADDRESS) at 0CF8h holds a value that specifies the PCI bus, PCI device, and specific register to be accessed. The configuration data register (CONFIG_DATA) at 0CFCh contains the c onfiguration da t a.
PCI Configuration Address Register I/O Port 0CF8h, R/W, (32-bi t access only)
Bit Function Bit Function
31 Configuration Enable
0 = Disabled 1 = Enable
30..24 Reserved - read/write 0s
23..16 Bus Number. Selects PCI bus
15..11 PCI Device Number. Selects PCI device for access
10..8 Func tion Number. Selects function of selected PCI device.
7..2 Register Index. Specifies config. reg. 1,0 Configuration Cycle Type ID.
00 = Type 0 01 = Type 1
PCI Configuration Data Register I/O Port 0CFCh, R/W, (8-, 16-, 32-bit access)
31..0 Configurat i on Data.
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Two types of configuration cycles are used. A Type 0 (zero) cycle is targeted to a device on the PCI bus on which the cycle is running. A Type 1 cycle is targeted to a device on a downstream PCI bus as identified by bus number bits <23..16>. With three or more PCI buses, a PCI bridge may convert a Type 1 to a Type 0 if it’s destined for a device being serviced by that bridge or it may forward the Type 1 cycle unmodified if it is destined for a device being serviced by a downstream bridge. Figure 4-2 shows the configuration cycle format and how the loading of 0CF8h results in a Type 0 configuration cycle on the PCI bus. The Device Number (bits <15..11> determines which one of the AD31..11 lines is to be asserted high for the IDSEL signal, which acts as a “chip select” function for the PCI device to be configure d. The function number (CF8h, bits <10..8> ) is used to select a particular function within a PCI component.
Register 0CF8h
Results in:
AD31..0
(w/Type 0
Config. Cycle)
31 24 23 16 15 11 10 8
Reserved
IDSEL (only one signal line asserted)
Bus
Number
Device
Number
Function
Number
Function
Number
7 2 1 0 [1]
Register
Index
Register
Index
NOTES:
[1] Bits <1,0> : 00 = Type 0 Cycl e, 01 = Type 1 cycle Type 1 cycle only. Reserved on Type 0 cycle.
Figure 4-2. Configuration Cycle Table 4-1 shows the standard configuration access data for components and slots residing on a PCI
bus. Table 4-1. PCI Device Configuration Access Data
Table 4-1.
PCI Component Configuration Access Data
PCI Component Vendor/Device ID
82850 MCH: Memory Controller PCI/PCI (AGP) Bridge AGP slot [3] 1 0 (00h) 0 -­82801BA ICH2: PCI/PCI Bridge LPC Bridge EIDE Controller USB I/F #1 SMBus Controller USB I/F #2 AC97 Audio Controller [1] AC97 Modem Controller [1] Network Interface Controller [1] ES1373 Audio Controller 1274h/1373h 2 [2] 31 (1Fh) 0 AD22 PCI Connector 1 (PCI slot 1) [3] 2 [2] 4 (04h) 0 AD20 PCI Connector 2 (PCI slot 2) [3] 2 [2] 9 (09h) 0 AD25 PCI Connector 3 (PCI slot 3) [3] 2 [2] 10 (0Ah) 0 AD26 PCI Connector 3 (PCI slot 4) [3] 2 [2] 11 (0Bh) 0 AD27 PCI Connector 3 (PCI slot 5) [3] 2 [2] 13 (0Dh) 0 AD29
NOTES:
8086h/2530h 8086h/2532h
8086h/244Eh
8086h/2440h
8086h/244Bh
8086h/2442h 8086h/2443h 8086h/2444h 8086h/2445h 8086h/2446h 8086h/2449h
PCI
Bus # Device # Function #
0 0
0 0 0 0 0 0 0 0
2 [2]
0 (00h) 1 (01h)
30 (1Eh)
31 (1Fh) 31 (1Fh) 31 (1Fh) 31 (1Fh) 31 (1Fh) 31 (1Fh) 31 (1Fh)
8 (08h)
0 0
0 0 1 2 3 4 5 6 0
IDSEL
Wired to:
--
--
[1] Not implem ent ed on these systems. [2] Value in standard confi guration. Can change if an AGP card with an additional bridge is installed. [3] Card specific. Refer to appendices.
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Configuration
d
Space
Header
Technical Reference Guide
The register index (CF8h, bits <7..2>) identifies the 32-bit location within the configuration space of the PCI device to be accessed. All PCI devices can contain up to 256 bytes of configuration data (Figure 4-3), of which the first 64 bytes comprise the configuration space header.
Register
31 24 23 16 15 8 7 0
Device-Specific A rea
Int. LineInt. PinMin. GNTMin. Lat. Reserved Reserved
Expansion ROM Base Address
Subsystem Vendor IDSubsystem ID
Card Bus CIS Pointer
Base Address Registers
BIST Hdr. Type
Status
Device ID
Line SizeLat. Timer
Command
Vendor ID
Index
FCh
40h
3Ch
38h 34h 30h
2Ch
28h
10h
0Ch
08h 04h
00h
31 24 23 16 15 8 7 0
Device-Specific A rea
Bridge Control
Expansion ROM Base Address
Reserved
I/O Base Upper 16 BitsI/O Limit Upper 16 Bits
Prefetchable Limit Upper 32 Bits
Prefetchable Base Upper 32 Bits
Prefetch. Mem. Limit Prefetch. Mem . Base
Memory BaseMemory Limit
n
Base Address Registers
BIST Hdr. Type
Status
Device ID
Int. LineInt. Pin
I/O BaseI/O LimitSecondary Status
Pri. Bus #Sec. Bus #Sub. Bus #2
Line SizeLat. Timer
Command Vendor ID
Register Index
FCh
40h
3Ch
38h 34h 30h
2Ch 28h
24h 20h
1Ch
18h
10h 0Ch
08h 04h 00h
PCI Configuration Space Type 0
Data required by PCI protocol
Not required
PCI Configuration Space Type 1
Figure 4-3. PCI Configuration Space Mapping
Each PCI device is identified with a vendor ID (assigned to the vendor by the PCI Special Interest Group) and a device ID (assigned by the vendor). The device and vendor IDs for the devices on the system board are listed in Table 4-1.
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4.2.2 PCI BUS MASTER ARBITRATION
The PCI bus supports a bus master/target arbitration scheme. A bus master is a device that has been granted control of the bus for the purpose of initiating a transaction. A target is a device that is the recipient of a transaction. The Request (REQ), Grant (GNT), and FRAME signals are used by PCI bus masters for gaining access to the PCI bus. When a PCI device needs access to the PCI bus (and does not already own it), the PCI device asserts it’s REQn signal to the PCI bus arbiter (a function of the system controller component). If the bus is available, the arbiter asserts the GNTn signal to the requesting device, which then asserts FRAME and conducts the address phase of the transaction with a target. If the PCI device already owns the bus, a request is not needed and the device can simply assert FRAME and conduct the transaction. Table 4-2 shows the grant and request signals assignments for the devices on the PCI bus.
Table 4-2. PCI Bus Mastering D evices
Table 4-2.
PCI Bus Mastering Devices
REQ/GNT Line Device
REQ0/GNT0 PCI Connector Sl ot 1 REQ1/GNT1 PCI Connector Sl ot 2 REQ2/GNT2 PCI Connector Sl ot 3 REQ3/GNT3 PCI Connector Sl ot 4 REQ4/GNT4 PCI Connector Sl ot 5 REQ5/GNT5 ES1373 Audio Controller GREQ/GGNT AGP Slot
PCI bus arbitration is based on a round-robin scheme that complies with the fairness algorithm specified by the PCI specification. The bus parking policy allows for the current PCI bus owner (excepting the PCI/ISA bridge) to maintain ownership of the bus as long as no request is asserted by another agent. Note that most CPU-to-DRAM and AGP-to-DRAM accesses can occur concurrently with PCI traffic, therefore reducing the need for the Host/PCI bridge to compete for PCI bus ownership.
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4.2.3 OPTION ROM MAPPING
During POST, the PCI bus is scanned for devices that contain their own specific firmware in ROM. Such option ROM data, if detected, is loaded into system memory’s DOS compatibility area (refer to the system memory map shown in chapter 3).
4.2.4 PCI INTERRUPTS
Eight interrupt signals (INTA- thru INTH-) are available for use by PCI devices. These signals may be generated by on-board PCI devices or by devices installed in the PCI slots. For more information on interrupts including PCI interrupt mapping refer to the “System Resources” section
4.4.
4.2.5 PCI POWER MANAGEMENT SUPPORT
This system complies with the PCI Power Management Interface Specification (rev 1.0). The PCI Power Management Enable (PME-) signal is supported by the chipset and allows compliant PCI and AGP peripherals to initiate the power management routine.
Technical Reference Guide
4.2.6 PCI SUB-BUSSES
The chipset implements two data busses that are supplementary in operation to the PCI bus:
4.2.6.1 Hub Link Bus
The chipset implements a Hub Link bus between the MCH and the ICH. The Hub Link bus handles transactions at a 66-MHz rate using PCI-type protocol, and in fact operates as PCI bus #0. This bus is transparent to software and not accessible for expansion purposes.
4.2.6.2 LPC Bus
The 82801 ICH implements a Low Pin Count (LPC) bus for handling transactions to and from the 47B357 Super I/O Controller as well as the 82802 FWH. The LPC bus transfers data a nibble (4 bits) at a time at a 33-MHz rate. Generally transparent in operation, the LPC bus becomes a factor primarily during the configuration of DMA channel modes (see section 4.4.3 “DMA”).
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4.2.7 PCI CONFIGURATION
PCI bus operations require the configuration of certain parameters such as PCI IRQ routing, DMA channel configura tion, RTC cont rol, port decode ranges, and power management options. The s e parameters are handled by the LPC I/F bridge function (PCI function #0, device 31) of t he ICH component and configured through the PCI configuration space registers listed in Table 4-3. Configuration is provided by BIOS at power-up but re-configurable by software.
Table 4-3. LPC Bridge Configuration Registers (ICH, Function 0)
PCI Config. Addr. Register
00, 01h Vendor ID 8086h 8Ah Device 31 Error Status 00h 02, 03h Device ID 2410h 90, 91h PCI DMA Configuration 0000h 04, 05h Command 000Fh A0-CFh Power Management 06, 07h Status 0280h D0-D3h General Control 0’s 08h Revision ID 00h D4-D7h General Status F00h 0A-0Bh Class Code 0106h D8h RTC Configuration 00h 0Eh Header Type 80h E0h LPC COM Port Dec. Range 00h 40-43h ACPI Base Address 1 E1h LPC FDD & LPT Dec . Rge 00h 44h ACPI Control 00h E2h LPC Audio Dec. Range 80h 4E, 4Fh BIOS Control 0000h E3h FWH Decode Enable FFh 54h TCO Control 00h E4, E5h LPC I/F Dec ode Range 1 0000h 58-5Bh GPIO Base Address 1 E6, E7h LPC I/F Enables 0000h 5Ch GPIO Control 00h E8h FWH Select 00 60-63h INTA-D Rout i ng Cnt rl . 80h [1 ] EC, EDh LPC I/ F Decode Range 2 0000h 64h Serial IRQ Control 10h EE, EFh Reserved -­65-87h Reserved -- F0h Reserved -­88h Dev. 31 Error Config. 00h F2h Function Disable Register 00h
Table 4-3.
LPC Bridge Configuration Registers
(ICH, Function 0, Device 31)
PCI Reset Value
Config.
Addr. Register
Reset Value
NOTE:
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4.2.8 PCI CONNECTOR
Technical Reference Guide
B94
A94
A62
B62
B52
A52
B49
A49
B1
A1
Figure 4-4. PCI Bus Connector (32-Bit Type)
Table 4-4. PCI Bus Connector Pinout
Table 4-4.
PCI Bus Connector Pinout
Pin B Signal A Signal Pin B Signal A Signal Pin B Signal A Signal
01 -12 VDC TRS T- 32 AD17 AD16 63 Reserved GND 02 TCK +12 VDC 33 C/BE2- +3.3 VDC 64 GND C/BE7- 03 GND TMS 34 GND FRAME- 65 C/BE6- C/BE5- 04 TDO TDI 35 IRDY- GND 66 C/BE4- +5 VDC 05 +5 VDC +5 VDC 36 +3.3 VDC TRDY- 67 GND PAR64 06 +5 VDC INTA- 37 DEVSEL- GND 68 AD63 AD62 07 INTB- INTC- 38 GND STOP- 69 AD61 GND 08 INTD- +5 VDC 39 LOCK- +3.3 VDC 70 +5 VDC AD60 09 PRSNT1- Reserved 40 PERR- SDONE n 71 AD59 AD58 10 RSVD +5 VDC 41 +3.3 VDC SBO- 72 AD57 GND 11 PRSNT2- Reserved 42 SERR- GND 73 GND AD56 12 GND G ND 43 +3.3 VDC PAR 74 AD55 AD54 13 GND GND 44 C/BE1- AD15 75 AD53 +5 VDC 14 RSVD +3.3 AUX 45 AD14 +3.3 VDC 76 GND AD52 15 GND RST- 46 GND AD13 77 AD51 AD50 16 CLK +5 VDC 47 AD12 AD11 78 AD49 GND 17 GND GNT- 48 AD10 GND 79 +5 VDC AD48 18 REQ- GND 49 GND AD09 80 AD47 AD46 19 +5 VDC PME- 50 Key Key 81 AD45 GND 20 AD31 AD30 51 Key Key 82 GND AD44 21 AD29 +3.3 VDC 52 AD08 C/BE0- 83 AD43 AD42 22 GND AD28 53 AD07 +3.3 VDC 84 AD41 +5 VDC 23 AD27 AD26 54 +3.3 VDC AD06 85 GND AD40 24 AD25 GND 55 AD05 AD04 86 AD39 AD38 25 +3.3 VDC A D24 56 AD03 GND 87 AD37 GND 26 C/BE3- IDSEL 57 GND AD02 88 +5 VDC AD36 27 AD23 +3.3 VDC 58 AD01 AD00 89 AD35 AD34 28 GND AD22 59 +5 VDC +5 VDC 90 AD33 GND 29 AD21 AD20 60 ACK64- REQ64- 91 GND AD32 30 AD19 GND 61 +5 VDC +5 VDC 92 Reserved Res erved 31 +3.3 VDC AD18 62 +5 VDC +5 VDC 93 Reserved GND
-- -- -- -- -- -- 94 GND Reserved
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Chapter 4 System Support
4.3 AGP BUS OVERVIEW
NOTE: This section provides a brief description of AGP bus operation. For a detailed description of AGP bus operations as supported by these systems refer to the AGP Interface Specification Rev. 2.0 available at the following AGP forum web site:
http://www.agpforum.org/index.htm
The Accelerated Graphics Port (AGP) bus is specifically designed as an economical yet high­performance interface for graphics adapters, especially those designed for 3D operations. The AGP interface is designed to give graphics adapters dedicated pipelined access to system memory for the purpose of off-loading texturing, z-buffering, and alpha blend ing used in 3D graphics operations. By off-loading a large portion of 3D data to system memory the AGP graphics adapter only require s enough memory for frame b uffer (display image) refreshing.
4.3.1 BUS TRANSACTIONS
The operation of the AGP bus is based on the 66-MHz PCI specification but includes additional mechanisms to increase bandwidth. During the configuration phase the AGP bus acts in accordance with PCI protocol. Once graphics data handling operation is initiated, AGP-defined protocols take effect. The AGP graphics adapter acts generally as the AGP master, but can also behave as a “PCI” target during fast writes from the MCH.
Key differences between the AGP interface and the PCI interface are as follows: Address phase and associated data transfer phase are disconnected transactions. Addressing
and data transferring occur as contiguous actions on the PCI bus. On the AGP bus a request for data and the transfer of data may be separated by other operations.
Commands on the AGP bus specify system memory accesses only. Unlike the PCI bus,
commands involving I/O and configuration are not required or allowed. The system memory address space used in AGP operations is the same linear space used by PCI memory space commands, but is further specified by the graphics address re-mapping table (GART) of the north brid ge component.
Data transactions on the AGP bus involve eight bytes or multiples of eight bytes. The AGP
memory addressing protocol uses 8-byte boundaries as opposed to PCI’s 4-byte boundaries. If a transfer of less than eight bytes is needed, the remaining bytes are filled with arbitrary data that is discarded by the target.
Pipelined requests are defined by length or size on the AGP bus. The PCI bus defines transfer
lengths with the FRAME- signal.
There are two basic types of transactions on the AGP bus: data requests (addressing) and data transfers. These actions are separate from each other.
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4.3.1.1 Data Request
Requesting data is accomplished in one of two ways; either multiplexed addressing (using the AD lines for addressing/data) or demultiplexed (“sideband”) addressing (using the SBA lines for addressing only and the AD lines for data only). Even though there are only eight SBA li nes (as opposed to the 32 AD lines) sideband addressing maximizes efficiency and throughput by allowing the AD lines to be exclusively used for data transfers. Sideband addressing occurs at the same rate (1X, 2X, or 4X) as data transfers. The differences in rates will be discussed in the next section describing data transfers. Note also that sideband addressing is limited to 48 bits (address bits 48­63 are assumed zero). The MCH component supports both SBA and AD addressing , but the method and rate is selected by the AGP graphics adapter.
4.3.1.2 Data Transfers
Data transfers use the AD lines and occur as the result of data requests described previously. Each transaction resulting from a request involves at least eight bytes, requiring the 32 AD lines to handle at least two transfers per request. The 82850 MCH supports three transfer rates: 1X, 2X, and 4X. Regardless of the rate used, the speed of the bus clock is constant at 66 MHz. The following subsections describe how the use of additional strobe signals makes possible higher transfer rates.
Technical Reference Guide
NOTE: These systems support only 1.5-volt signaling on the AGP bus.
AGP 1X Transfers
During a AGP 1X transfer the 66-MHz CLK signal is used to qualify the control and data signals. Each 4-byte data transfer is synchronous with one CLK cycle so it takes two CLK cycles for a minimum 8-byte transfer (Figure 4-5 shows two 8-byte transfers). The GNT- and TRDY- signals retain their traditional PCI functions. The ST0..3 signals are used for priority encoding, with “000” for low priority and “001” indicating high priority.
T1 T2 T3 T4 T5 T6 T7
CLK
AD
GNT-
TRDY-
ST0..2
00x
D1A D2A D2BD1B
xxx
xxx
xxx
xxx
xxx
Figure 4-5. AGP 1X Data Transfer (Peak Transfer Rate: 266 MB/s)
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Chapter 4 System Support
AGP 2X Transfers
During AGP 2X transfers, clocking is basically the same as in 1X transfers except that the 66-MHz CLK signal is used to qualify only the control signals. The data bytes are latched by an additional strobe (AD_STBx) signal so that an 8-byte transfer occurs in one CLK cycle (Figure 4-6). The first four bytes (DnA) are latched by the receiving agent on the falling edge of AD_STBx and the second four bytes (DnB) are l atched on the ri sing edge of AD_STBx.
T1 T2 T3 T4 T5 T6 T7
CLK
AD
AD_STBx
GNT-
TRDY-
ST0..2
00x
D1B D2B D3B D4A D4B
D1A D2A D3A
xxx
xxx
xxx
xxx
xxx
Figure 4-6. AGP 2X Data Transfer (Peak Transfer Rate: 532 MB/s)
AGP 4X Transfers
The AGP 4X transfer rate allows sixteen bytes of data to be transferred in one clock cycle. As in 2X transfers the 66-MHz CLK signal is used only for qualifying control signals while strobe signals are used to latch each 4-byte transfer on the AD lines. As shown in Figure 4-7, 4-byte block DnA is latched by the falling edge of AD_STBx while DnB is latched by the falling edge of AD_STBx-.
T1 T2 T3
CLK
T4
AD
AD_STBx
AD_STBx-
ST0..2
D1A D2A D3AD1B D2B D3B D4A D4B
00xxxx xxx xxx
Figure 4-7. AGP 4X Data Transfer (Peak Transfer Rate: 1064 MB/s)
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4.3.2 AGP CONFIGURATION
AGP bus operations require the configuration of certain parameters involving system memory access by the AGP graphics adapter. The AGP bus interface is configured as a PCI device integrated within the north bridge (MCH, device 1) component. The AGP function is, from the PCI bus perspec tive, treated essentially as a PCI/PCI brid ge and configured through PCI configuration registers (Table 4-6). Configuration is accomplished by BIOS during POST.
NOTE: Configuration of the AGP bus interface involves functions 0 and 1 of the MCH. Function 0 registers (listed in Table 3-4) include functions that affect basic control (GART) of the AGP.
Table 4-5. PCI/AGP Bridge Configuration Regi sters (MCH, Function 1)
PCI/AGP Bridge Function Configuration Registers
PCI Config. Addr. Register
00, 01h Vendor ID 8086h 1Bh Sec. Master Latency Ti mer 00h 02, 03h Device ID 2532h 1Ch I/O Base A ddress F0h 04, 05h Command 0000h 1Dh I/O Limit Address 00h 06, 07h Status 0020h 1E, 1Fh Sec. PCI/PCI Status 02A0h 08h Revision ID 00h 20, 21h Memory Base Address FFF0h 0A, 0Bh Class Code 0406h 22, 23h Memory Limit Address 0000h 0Eh Header Type 01h 24, 25h Prefetch Mem. Base Addr. FFF0h 18h Primary Bus Number 00h 26, 27h Prefetch Mem. Limi t Addr. 0000h 19h Secondary Bus Number 00h 3Eh PCI / PCI Bridge Control 00h 1Ah S ubordi nate Bus Number 00h 3F-FFh Reserved 00h
Table 4-5.
(MCH, Function 1)
PCI Reset Value
Config.
Addr. Register
Technical Reference Guide
Reset Value
NOTE:
Assume unmark ed l ocations/gaps as reserved. Refer to Intel documentat i on for detailed register descriptions.
The AGP graphics adapter (actually its resident controller) is configured as a standard PCI device.
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Chapter 4 System Support
A
4.3.3 AGP CONNECTOR
B94
A94
B1
1
A41 A46
B41 B46
A66
Figure 4-8. 1.5-Volt AGP Bus Connector
Table 4-6. AGP Bus Connector Pinout
Table 4-6.
AGP Bus Connector Pinout
Pin A Signal B Signal Pin A Signal B Signal Pin A Signal B Signal
01 +12 VDC OVRCNT- 23 GND GND 45 KEY KEY 02 Type Det- 5.0 VDC 24 Reserved VDD3 Aux 46 T RDY- DEVSEL­03 Reserved 5.0 VDC 25 VDD3 VDD3 47 S T OP- VDDQ 04 USB- USB+ 26 PAD30 PAD31 48 PME- PERR­05 GND GND 27 PAD28 PAD29 49 GND GND 06 INTA- INTB- 28 VDD3 VDD3 50 PAR SERR­07 RESET CLK 29 PAD26 PAD27 51 PAD15 CBE1­08 GNT- REQ- 30 PAD24 PAD25 52 VDDQ VDDQ 09 VDD3 VDD3 31 GND GND 53 PAD13 PAD14 10 ST1 ST0 32 AD_STB1- AD_STB1 54 PAD11 PAD12 11 Reserved ST2 33 CBE3- PAD23 55 GND GND 12 PIPE- RBF- 34 VDDQ VDDQ 56 PAD09 PAD10 13 GND GND 35 PAD22 PAD21 57 CBE0- PAD08 14 WBF- Reserved 36 PAD20 PAD19 58 VDDQ VDDQ 15 SBA1 SBA0 37 GND GND 59 AD_STB0- AD_STB0 16 VDD3 VDD3 38 PAD18 PAD17 60 PAD06 PAD07 17 SBA3 SBA2 39 PAD16 CBE2- 61 GND GND 18 SB_STB- SB_STB 40 VDDQ VDDQ 62 PAD04 PAD05 19 GND GND 41 FRAME- IRDY- 63 PAD02 PAD03 20 SBA5 SBA4 42 KEY KEY 64 VDDQ VDDQ 21 SBA7 DBA6 43 KEY KEY 65 PAD00 PAD01 22 Reserved Reserved 44 KEY KEY 66 VREFGC VREFCG
NOTES:
NC = Not connected VDDQ = 1.5 VDC, as determined by system board grounding of Type Det- si gnal (pi n A 02).
B66
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4.4 SYSTEM RESOURCES
This section describes the availability and basic control of major subsystems, otherwise known as resource allocation or simply “system resources.” System resources are provided on a priority basis through hardware interrupts and DMA requests and grants.
4.4.1 INTERRUPTS
The microprocessor uses two types of hardware interrupts; maskable and nonmaskable. A maskable interrupt can be enabled or disabled within the microprocessor by the use of the STI and CLI instructions. A nonmaskable interrupt cannot be masked off within the microprocessor, although it may be inhibited by hardware or software means external to t he microprocessor.
4.4.1.1 Maskable Interrupts
The maskable interrupt is a hardware-generated signal used by peripheral functions within the system to get the attention of the microprocessor. Peripheral functions produce a unique INTA-H (PCI) or IRQ0-15 (ISA) signal that is routed to interrupt processing logic that asserts the interrupt (INTR-) input to the microprocessor. The microprocessor halts execution to determine the source of the interrupt and then services the peripheral as appropriate. Figure 4-9 shows the routing of PCI and ISA interrupts. Most I R Qs are routed t hrough the I/O cont roller, which contains a serializing function. A serialized interrupt stream is applied to the 82801 ICH.
Technical Reference Guide
I/O Controller
Interrupt
Serializer
Serial IRQ
82801
ICH2
Interrupt
Processing
INTR-
APIC Bus
SM Functions
I/O &
IDE
Hard Drives
PCI Peripherals
IRQ3..7,
9..12, 14,15
IRQ14,15
INTA-..D-
Figure 4-9. Maskable Interrupt Processing, Block Diagram
The 82801 ICH2 component can be configured (through the Setup utility) to handle interrupts in one of two modes of operation:
8259 modeAPIC mode
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8259 Mode
In 8259-Mode, interrupts IRQ0-IRQ15 are handled in the conventional (AT-system) method using logic that is the equivalent of two 8259 interrupt controllers. Table 4-7 lists the standard source configuration for maskable interrupts and their priorities in 8259 mode. If more than one interrupt is pending, the highest priority (lowest number) is processed first.
Table 4-7. Maskable Interrupt Priorities and Assignments
Priority Signal Label Source (Typical)
1 IRQ0 Interval timer 1, counter 0 2 IRQ1 Keyboard 3 I RQ8- Real-time c l ock 4 IRQ9 Microtower, game/MIDI port; desk top or minitower, unused. 5 IRQ10 Unused 6 IRQ11 Unused 7 IRQ12 Mouse 8 IRQ13 Coprocessor (mat h) 9 IRQ14 IDE primary I/F 10 IRQ15 IDE secondary I/F 11 IRQ3 Serial port (COM2) 12 IRQ4 Serial port (COM1) 13 IRQ5 Unused 14 IRQ6 Diskett e dri ve controller 15 IRQ7 Parallel port (LPT 1)
-- IRQ2 NOT AVAILABLE (Cascade from interrupt controller 2)
Table 4-7.
Maskable Interrupt Priorities and Assignments
APIC Mode
The Advanced Programmable Interrupt Controller (APIC) mode enhances interrupt-processing performance with the following advantages:
Eliminating the processor’s interrupt acknowledge cycle by using a separate APIC bus.Programmable interrupt priority.Additional interrupts (total of 24).
Eight PCI interrupts are available in APIC mode. The PCI interrupts are evenly distributed to minimize latency and are hard-wired as follows:
ICH2
IRQ Cntlr.
INTA- INTA- INTD- INTC- INTB- INTD- -- -- -- -­INTB- ------------ -- -- -­INTC- INTB- INTA- INTD- INTC- INTA- INTA- -- -- -­INTD- ----------INTB-INTD--- -­INTE- ------------ -- -- INTA­INTF- INTC- INTB- INTA- INTD- INTB- -- -- -- --
INTG- INTD- INTC- INTB- INTA- INTC- -- -- -- --
INTH- ------------ --INTH---
Wired
to
PCI
Slot 1
PCI
Slot 2
PCI
Slot 3
PCI
Slot 4
PCI
Slot 5
AGP
Slot
USB
Cntlr. #1
USB
Cntlr. #2
Audio
Cntlr.
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Technical Reference Guide
NOTE: The APIC mode is supported by Windows NT/2000 operating systems. Systems using the Windows 95 or 98 operating system will need to run in 8259 mode. The mode is selectable through the Setup utility (access with F10 key during boot sequence).
Maskable Interrupt proc essing is controlled and monitored through standar d AT-type I/O-mapped registers. These registers are listed in Table 4-8.
Table 4-8. Maskable Interrupt Control Registers
Table 4-8.
Maskable Interrupt Control Registers
I/O Port Register
020h Base Addres s, Int. Cntlr. 1 021h Initiali zat i on Command Word 2-4, Int. Cntlr. 1 0A0h Base Address, Int. Cntlr. 2 0A1h Initiali zat i on Command Word 2-4, Int. Cntlr. 2
The initialization and operation of the interrupt control registers follows standard AT-type protocol.
4.4.1.2 Non-Maskable Interrupts
Non-maskable interrupts cannot be masked (inhibited) within the microprocessor itself but may be maskable by software using logic external to the microprocessor. There are two non-maskable interrupt signals: the NMI- and the SMI-. These signals have service priority over all maskable interrupts, with the SMI- having top priority over all interrupts including the NMI-.
NMI- Generation
The Non-Maskable Interrupt (NMI-) signal can be generated by one of the following actions:
Parity errors detected on a PCI bus (activating SERR- or PERR-).Microprocessor internal error (activating IERRA or IERRB)
The SERR- and P ERR- signals are rout ed through the ICH c omponent, which in turn activa tes the NMI to the microprocessor.
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The NMI Status Register at I/O port 061h contains NMI source and status data as follows:
NMI Status Register 61h
Bit Function
7 NMI Status:
0 = No NMI from system board pari ty error. 1 = NMI requested, read only
6IOCHK- NMI:
0 = No NMI from IOCHK-
1 = IOCHK- is active (low), NMI requested, read only 5 Interval Timer 1, Counter 2 (Speaker) Status 4 Refresh Indicator (toggles with every ref resh) 3 IOCHK- NMI Enable/Disable:
0 = NMI from IOCHK- enabled
1 = NMI from IOCHK- disabled and c l eared (R/W) 2 System Board Parity Error (PERR/SERR) NMI Enable:
0 = Parity error NMI enabled
1 = Parity error NMI disabled and cleared (R/W) 1 Speaker Data (R/W) 0 Inteval Timer 1, Counter 2 Gate Signal (R/W)
0 = Counter 2 disabled
1 = Counter 2 enabled
Functions not related to NMI activity.
After the active NMI has been processed, status bits <7> or <6> are cleared by pulsing bits <2> or <3> respectively.
The NMI Enable Register (070h, <7>) is used to enable/disable the NMI signal. Writing 80h to this register masks generation of the NMI-. Note that the lower six bits of register at I/O port 70h affect RTC operation and should be considered when changing NMI- generation status.
SMI- Generation
The SMI- (System Management Interrupt) is typically used for power management functions. When power management is enabled, inactivity timers are monitored. When a timer times out, SMI- is asserted and invokes the microprocessor’s SMI handler. The SMI- handler works with the APM BIOS to service the SMI- according to the cause of the timeout.
Although the SMI- is primarily used for power managment the interrupt is also employed for t he QuickLock/QuickBlank functions as well.
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4.4.2 DIRECT MEMORY ACCESS
Direct Memory Access (DMA) is a method by which a device accesses system memory without involving the microprocesso r. Although the DMA method has been traditionally used to transfer blocks of data to or from an ISA I/O device, PCI devices may also use DMA operation as well. The DMA method reduces the amount of CPU interactions with memory, freeing the CPU for other proce ssing tasks.
NOTE: This section describes DMA in general. For detailed information regarding DMA operation, refer to the data manual for the Intel 82801BA I/O Controller Hub.
The 82801 ICH2 component includes the equivalent of two 8237 DMA controllers cascaded together to provide eight DMA channels, each (excepting channel 4) configurable to a specific device. Table 4-9 lists the default configuration of the DMA channels.
Table 4-9. Default DMA Channel Assignments And Register I/O Port s
DMA Channel Assignments And Register Ports
DMA Channel Function I/O Port
Controller 1 (byte transfers) 0 1 2 3 Controller 2 (word transfers) 4 5 6 7 Refresh 08Fh [see note]
NOTE: The DMA memory page register for the refresh channel must be programmed with 00h for proper operation.
Unused Audio subsystem Diskette drive Parallel port (ECP or EPP mode)
Cascade for controller 1 Unused Unused Unused
Technical Reference Guide
Table 4-9
Control registers 000h-00Eh Page register 087h Page register 083h Page register 081h Page register 082h Control registers 0C0h-0DEh n/a Page register 08Bh Page register 089h Page register 08Ah
All channels in DMA controller 1 operate at a higher priority than those in controller 2. Note that channel 4 is not available for use other than its cascading function for controller 1. The DMA controller 2 can transfer words only on an even address boundary. The DMA controller and page register define a 24-bit address that allows data transfers within the address space of the CPU.
In addition to device configuratio n, each channel can be configured (through PCI Configuration Registers) for one of two modes of operation:
LPC DMA Mode - Uses the LPC bus to communicate DMA channel control and is
implemented for d evices using DMA through the I/O controller such as the d iskette drive controller.
PC/PCI DMA Mode - Uses the REQ#/GNT# signals to communicate DMA channel control
and is used by PCI expansion devices.
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Chapter 4 System Support
CMOS
4.5 SYSTEM CLOCK DISTRIBUTION
These systems use an Intel CK-type clock generator and crystal for generating the clock signals required by the system board components. Table 4-10 lists the system board clock signals and how they are distributed.
Table 4-10. Clock Generatio n and Distribution
Table 4-10
Clock Generation and Distribution
Frequncy Source Destination
400 MHz MCH Processor, RI MM sockets 100 MHz CK MCH 66 MHz CK MCH, ICH2, AGP slot 48 MHz CK ICH2, I/O Cntlr. 33 MHz CK Processor, ICH2, PCI Slots
14.31818 MHz Crystal CK
Certain clock outputs are turned off during reduced power modes to conserve energy. Clock output control is handled through the SMBus interface by BIOS.
4.6 REAL-TIME CLOCK AND CONFIGURATION MEMORY
The Real-time clock (RTC) and configuration memory (also referred to as “CMOS”) functions are provided by the 82801 ICH component and is MC146818-compatible. As shown in the following figure, the 82801 ICH component provides 256 bytes of battery-backed RAM divided into two 128-byte configuration memory areas. The RTC uses the first 14 bytes (00-0Dh) of the standard memory area. All locations of the standard memory area (00-7Fh) can be directly accessed using conventional OUT and IN asse mbl y language instructions thr ough I/O ports 70h/71h, alt hough the suggested method is to use the INT15 AX=E823h BIOS call.
0Dh 0Ch 0Bh
0Ah
09h 08h 07h 06h 05h 04h 03h 02h 01h 00h
Register D Register C Register B Register A
Date of Month
Day of Week
Hours (Alarm)
Hours (Timer) Minutes (Alarm) Minutes (Timer)
Seconds (Alarm) Seconds (Timer)
Year
Month
82801
Extended Config.
Memory Area
(128 bytes)
Standard Config.
Memory Area
(114 bytes)
RTC Area (14 bytes)
FFh
80h 7Fh
0Eh 0Dh
00h
Figure 4-10. Configuration Memory Map
A lithium 3-VDC battery is used for maintaining the RTC and configuration memory while the system is powered down. The battery is located in a battery holder on the system board is replaced with a Renata CR2032 or equivalent 3-VDC lithium battery.
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4.6.1 CLEARING CMOS
The contents of configuration memory (including the Power-On Password) can be cleared by the following proc edures:
1. Turn off the unit.
2. Disconnect the AC power cord from the outlet and/or system unit.
3. Remove the chassis hood (cover) and insure that no LEDs on the system board are
illuminated.
4. Press and release the CMOS clear button on the system board.
5. Replace the chassis hood (cover).
6. Reconnect the AC power cord to the outlet and/or system unit.
7. Turn the unit on.
To clear only the Power-On Password refer to section 4.7.1.1.
Technical Reference Guide
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Chapter 4 System Support
4.6.2 CMOS ARCHIVE AND RESTORE
During the boot sequence the BIOS saves a copy of NVRAM (CMOS contents, password(s) and other system variables) in a portion of the flash ROM. Should the system become un-usable, the last good copy of NVRAM data can be restored with the Power Button Override function. This function is invoked with the following procedure:
1. With the unit powered down, press and release the power button.
2. Immediately after releasing the power button in step 1, press and hold the power button until
the unit powers down. This action will be recorded as a Power Button Override event.
With the next startup sequence the BIOS will detect the occurrence of the Power Button Override event and will load the backup copy of NVRAM from the ROM to the CMOS.
NOTE: The Power Button Override feature does not allow quick cycling of the system (turning on then off). If the power cord is disconnected during the POST routine, the splash screen image may become corrupted, requiring a re-flashing of the ROM (refer to chapter 8, BIOS ROM).
4.6.3 STANDARD CMOS LOCATIONS
Table 4-14 and the following paragraphs describe standard configuration memory locations 0Ah­3Fh. These locations are accessible using OUT/IN assembly language instructions using port 70/71h or BIOS function INT15, AX=E823h.
Table 4-11. Configuration Memory (CMOS) Map
Configuration Memory (CMOS) Map
Location Function Location Function
00-0Dh Real -t i me clock 24h S ys tem board ID 0Eh Diagnostic status 25h System architecture data 0Fh System reset c ode 26h Auxiliary peripheral configuration 10h Di skette drive type 27h Speed control external drive 11h Reserved 28h Expanded/base mem . size, IRQ12 12h Hard dri ve t ype 29h Miscellaneous configuration 13h S ecurity functions 2Ah Hard drive timeout 14h Equipment installed 2Bh System inactivity t i meout 15h Base memory size, low byte/KB 2Ch Monitor timeout, Num Lock Cntrl 16h Base memory size, hi gh byte/KB 2Dh Additional flags 17h E xtended memory, low byte/KB 2Eh-2Fh Checksum of locations 10h-2Dh 18h E xtended memory, high byte/KB 30h-31h Total extended memory tested 19h Hard dri ve 1, pri mary controller 32h Century 1Ah Hard drive 2, primary controller 33h Miscellaneous flags set by BIOS 1Bh Hard drive 1, secondary controller 34h Internat i onal l anguage 1Ch Hard drive 2, secondary c ontroller 35h APM status flags 1Dh Enhanced hard drive support 36h ECC POST test single bit 1Eh Reserved 37h-3Fh Power-on password 1Fh Power management functions 40-FFh Feature Control /Status
NOTES:
Assume unmark ed gaps are reserved.
Table 4-11.
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RTC Control Register A, Byte 0Ah
Bit Function
7 Update in Progress. Read only.
0 = Time update will not occur before 2444 us 1 = Time update will occur within 2444 us
6..4 Divider Chain Control. R/W. 00x = Oscillator disabled. 010 = Normal operation (time base frequency = 32.768 KHz). 11x = Divider chain reset.
3..0 Periodic Interrupt Control. R/W. Specifies the periodic i nterrupt interval. 0000 = none 1000 = 3.90625 ms 0001 = 3.90625 ms 1001 = 7.8125 ms 0010 = 7.8125 ms 1010 = 15. 625 ms 0011 = 122.070 us 1011 = 31.25 ms 0100 = 244.141 us 1100 = 62.50 ms 0101 = 488.281 us 1101 = 125 ms 0110 = 976.562 us 1110 = 250 ms 0111 = 1.953125 ms 1111 = 500 ms
RTC Control Register B, Byte 0Bh
Bit Function
7 Time Update Enable/disable
0 = Normal operation, 1 = Disable t i me updating for time set
6 Periodic Interrupt Enable/Dis abl e.
0 = Disable, 1 = Enable interval specified by Register A
5 Alarm Interrupt Enable/disable
0 = Disabled, 1 = Enabled
4 End-of-Update Interrupt Enable/Dis abl e
0 = Disabled, 1 = Enabled
3 Reserved (read 0) 2 Time/Date Format Selec t
0 = BCD format, 1 = Binary f ormat
1 Time Mode
0 = 12-hour mode, 1 = 24-hour mode
0 Automatic Daylight Savi ngs Time Enable/Disable
0 = Disable 1 = Enable (Advance 1 hour on 1 October).
st
Sunday in April, retreat 1 hour on las t Sunday in
Technical Reference Guide
RTC Status Register C, Byte 0Ch
Bit Function
7 If set, interrupt output signal active (read only) 6 If set, indicates periodi c interrupt flag 5 If set, indicates al arm interrupt 4 If set, indicates end-of -update interrupt
3..0 Reserved
RTC Status Register D, Byte 0Dh
Bit Function
7 RTC Power Status
0 = RTC has lost power 1 = RTC has not lost power
6..0 Reserved
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Chapter 4 System Support
Configuration Byte 0Eh, Diag nostic Status
Default Value = 00h
This byte contai ns diagnostic status d ata.
Configuration Byte 0Fh, System Reset Code
Default Value = 00h
This byte contains the system reset code.
Configuration Byte 10 h, Diskette Driv e Type
Bit Function
7..4 Primary (Drive A) Diskette Drive Type
3..0 Secondary (Drive B) Diskette Drive Type
Valid values for bits <7..4> and bits <3..0>:
0010 = 1.2-MB drive 0011 = 720-KB drive
0110 = 2.88-MB drive
(all other values reserved)
0000 = Not installed 0001 = 360-KB drive
0100 = 1.44-MB/1.25-MB drive
Configuration Byte 12h, Hard Drive Type
Bit Function
7..4 Primary Controller 1, Hard Drive 1 Type: 0000 = none 1000 = Type 8 0001 = Type 1 1001 = Type 9 0010 = Type 2 1010 = Type 10 0011 = Type 3 1011 = Type 11 0100 = Type 4 1100 = Type 12 0101 = Type 5 1101 = Type 13 0110 = Type 6 1110 = Type 14 0111 = Type 7 1111 = other (use bytes 19h)
3..0 Primary Controller 1, Hard Drive 2 Type: 0000 = none 1000 = Type 8 0001 = Type 1 1001 = Type 9 0010 = Type 2 1010 = Type 10 0011 = Type 3 1011 = Type 11 0100 = Type 4 1100 = Type 12 0101 = Type 5 1101 = Type 13 0110 = Type 6 1110 = Type 14 0111 = Type 7 1111 = other (use bytes 1Ah)
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Configuration Byte 13h, Security Functions
Default Value = 00h
Bit Function
7 Reserved 6 QuickBlank Enable Aft er S tandby:
0 = Disable 1 = Enable
5 Administrator Pass word:
0 = Not present 1 = Present
4 Reserved 3 Diskette Boot Enable:
0 = Enable 1 = Disable
2 QuickLock Enable:
0 = Disable 1 = Enable
1 Network Server Mode/Security Lock Override:
0 = Disable 1 = Enable
0 Password State (Set by BIOS at P ower-up)
0 = Not set 1 = Set
Technical Reference Guide
Configuration Byte 1 4h, Equipment Installed
Default Value (standard confi guration) = 03h
Bit Function
7,6 No. of Diskette Drives Instal l ed:
00 = 1 drive 10 = 3 drives 01 = 2 drives 11 = 4 drives
5..2 Reserved
1 Coprocessor Present
0 = Coprocessor not installed 1 = Coprocessor installed
0 Diskette Drives Present
0 = No diskette drives inst al l ed 1 = Diskette drive(s) inst al l ed
Configuration Bytes 15h and 16h, Base Memory Size
Default Value = 280h
Bytes 15h and 16h hold a 16-bit value that specifies the base memory size in 1-KB (1024) increments. Valid base memory sizes are 512 and 640 kilobytes .
Configuration Bytes 17h and 18h, Extended Memory Size
Bytes 17h and 18h hold a 16-bit value that specifies the extended memory size in 1-KB increments.
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Configuration Bytes 19 h- 1Ch, Hard Drive Types
Byte 19h contains the hard drive type for drive 1 of the primary controller if byte 12h bits <7..4> hold 1111b. Byte 1Ah contains the hard drive type for drive 2 of the primary controller if byte 12h bits <3..0> hold 1111b. Bytes1Bh and 1Ch contain the hard drive types for hard drives 1 and 2 of the secondary controller.
Configuration Byte 1Dh, Enhanced IDE Hard Drive Support
Default Value = F0h
Bit Function
7 EIDE - Drive C (83h) 6 EIDE - Drive D (82h) 5 EIDE - Drive E (81h) 4 EIDE - Drive F (80h)
3..0 Reserved
Values for bits <7..4> :
0 = Disable 1 = Enable for auto-configure
Configuration Byte 1Fh, Power Management Functions
Default Value = 00h
Bit Function
7..4 Reserved
3 Slow Processor Clock for Low Power Mode
0 = Processor runs at full speed 1 = Processor runs at slow speed
2 Reserved 1 Monitor Off Mode
0 = Turn monitor power off after 45 mi nutes in standby 1 = Leave monitor power on
0 Energy Saver Mode Indicator (Blinking LED)
0 = Disable 1 = Enable
Configuration Byte 24 h, Sy stem Board Identification
Default Value = 7Eh
Configuration memory location 24h holds the system board ID.
Configuration Byte 25h, System Architecture Data
Default Value = 0Bh
Bit Function
7..4 Reserved
3 Unmapping of ROM:
0 = Allowed 1 = Not allowed
2 Reserved
1,0 Diagnosti c Status Byte Address
00 = Memory locations 80C00000h-80C00004h 01 = I/O ports 878h-87Ch 11 = neither place
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Configuration Byte 26h, Auxiliary Peripheral Config uration
Default Value = 00h
Bit Function
7,6 I/O Delay Select
00 = 420 ns (default) 01 = 300 ns 10 = 2600 ns 11 = 540 ns
5 Alternative A20 Switching
0 = Disable port 92 mode 1 = Enable port 92 mode
4 Bi-directional Print Port Mode
0 = Disabled 1 = Enabled
3 Graphics Type
0 = Color 1 = Monochrome
2 Hard Drive Primary/Secondary Address Select:
0 = Primary 1 = Secondary
1 Diskette I/O Port
0 = Primary 1 = Secondary
0 Diskette I/O Port Enable
0 = Primary 1 = Secondary
Technical Reference Guide
Configuration Byte 27h, Speed Control/External Drive
Default Value = 00h
Bit Function
7 Boot Speed
0 = Max MHz 1 = Fast speed
6..0 Reserved
Configuration Byte 28 h, Expanded and Base Memory, IRQ12 Select
Default Value = 00h
Bit Function
7 IRQ12 Select
0 = Mouse 1 = Expansion bus
6,5 Base Memory Size:
00 = 640 KB 01 = 512 KB 10 = 256 KB 11 = Invalid
4..0 Internal Compaq Memory: 00000 = None 00001 = 512 KB 00010 = 1 MB 00011 = 1.5 MB . . 11111 = 15.5 MB
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Configuration Byte 29 h, Miscellaneous Configuration Dat a
Default Value = 00h
Bit Function
7..5 Reserved
4 Primary Hard Drive Enable (Non-PCI IDE Cont rol l ers)
0 = Disable 1 = Enable
3..0 Reserved
Configuration Byte 2Ah, Hard Drive Timeout
Default Value = 02h
Bit Function
7..5 Reserved
4..0 Hard Drive Timeout (index to SIT timeout record)
Configuration Byte 2Bh, System Inactivity Timeout
Default Value = 23h
Bit Function
7 Reserved
6,5 Power Conservation Boot
00 = Reserved 01 = PC on 10 = PC off 11 = Reserved
4..0 System Inactive Timeout. (Index to SIT sys t em timeout record) 00000 = Disabled
Configuration Byte 2Ch, ScreenSave and NUMLOCK Control
Default Value = 00h
Bit Function
7 Reserved 6 Numlock Control
0 = Numlock off at power on 1 = Numlock on at power on
5 Screen Blank Control:
0 = No screen blank 1 = Screen blank w/QuickLock
4..0 ScreenSave Timeout. (Index to SIT monitor timeout record) 000000 = Disabled
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Configuration Byte 2Dh, Additional Flags
Default Value = 00h
Bit Function
7..5 Reserved
4 Memory Test
0 = Test memory on power up only 1 = Test memory on warm boot
3 POST Error Handling (BIOS Defined)
0 = Display “Press F1 to Continue” on error 1 = Skip F1 message
2..0 Reserved
Configuration Byte 2Eh, 2Fh, Checksum
These bytes hold the checksum of bytes 10h to 2Dh.
Configuration Byte 30h, 31h, Total Extended Memory Tested
This location holds the amount of system memory that checked good during the POST.
Configuration Byte 32h, Cent ury
This location holds the Century value in a binary coded decimal (BCD) format.
Configuration Byte 33h, Miscellaneous Flags
Default Value = 80h
Bit Function
7 Memory Above 640 KB
0 = No, 1 = Yes
6 Reserved 5 Weitek Numeri c Coprocessor Present:
0 = Not installed, 1 = Inst all ed
4 Standard Numeric Coprocessor P resent:
0 = Not installed, 1 = Inst all ed
3..0 Reserved
Configuration Byte 34h, International Language Support
Default Value = 00h
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Configuration Byte 35h, AP M Status Flags
Default Value = 11h
Bit Function
7..6 Power Conservation State: 00 = Ready 01 = Standby 10 = Suspend 11 = Off
5,4 Reserved
3 32-bit Connection:
0 = Disconnected, 1 = Connected
2 16-bit Connection
0 = Disconnected, 1 = Connected
1 Real Mode Connection
0 = Disconnected, 1 = Connected
0 Power Management Enable:
0 = Disabled 1 = Enabled
Configuration Byte 36h, ECC P OST Test Single Bit Errors
Default Value = 01h
Bit Function
7 Row 7 Error Detect 6 Row 6 Error Detect 5 Row 5 Error Detect 4 Row 4 Error Detect 3 Row 3 Error Detect 2 Row 2 Error Detect 1 Row 1 Error Detect
0 Row 0 Error Detect 0 = No single bit error detected. 1 = Single bit error detected.
Configuration Byte 37h-3Fh, Power-On Password
These eight locations hold the power-on password.
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4.7 SYSTEM MANAGEMENT
This section describes functi ons having to do with secur ity, power management, temperature, and overall status. These functions are handled by hardware and firmware (BIOS) and generally configured through the Setup utility.
4.7.1 SECURITY FUNCTIONS
These systems include various features that provide different levels of security. Note that this subsection describes only the hardware functionality (including that supported by Setup) and does not describe security features that may be provided by the operating system and application software.
4.7.1.1 Power-On Password
These systems include a power-on password, which may be enabled or disabled (cleared) through a jumper on the system board. The jumper controls a GPIO input to the 82801 ICH that is checked during POST. The password is stored in configuration memory (CMOS) and if enabled and then forgotten by the user will require that either the password be cleared (preferable solution and described below) or the entire CMOS be cleared (refer to section 4.6).
Technical Reference Guide
To clear the password, use the following procedure:
1. Turn off the system and disconnect the AC power cord from the outlet and/or system unit.
2. Remove the cover (hood). Insure that all system board LEDs are off (not illuminated).
3. Locate the password header/jumper (labeled E49 on these systems) and remove the jumper
from pins 1 and 2 and place on (just) pin 2 (for safekeeping).
4. Replace the cover.
5. Re-connect the AC power cord to the AC outlet and/or system unit.
6. Turn on the system. The POST routine will clear and disable the password.
7. To re-enable the password feature, repeat steps 1-6, replacing the jumper on pins 1 and 2 of
header E49.
4.7.1.2 Setup Password
The Setup utility may be configured to be always changeable or changeable only by entering a password. The password is held on CMOS and, if forgotten, will require that CMOS be cleared (refer to section 4.6).
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4.7.1.3 Cable Lock Provision
These systems include a chassis cutout (on the rear panel) for the attachment of a cable lock mechanism.
4.7.1.4 I/O Interface Security
The serial, parallel, USB, and diskette interfaces may be disabled individually through the Setup utility to guard against unauthorized access to a system. In addition, the ability to write to or boot from a removable med ia drive (such as t he diskette dri ve) may be enabled through the Setup utility. The disabling of the serial, parallel, and diskette interfaces are a function of the LPC47B357 I/O controller. The USB ports are controlled through the 82801 ICH.
4.7.2 POWER MANAGEMENT
These systems provide baseline hardware support of ACPI- and APM-compliant firmware and software. Key power-consuming components (processor, chipset, I/O controller, and fan) can be placed into a reduced power mode either automatically or by user control. The system can then be brought bac k up (“wake-up”) by events defined by the ACP I specificati on. The ACPI wake-up events supported by this system are listed as follows:
ACPI Wake-Up Event S ystem Wakes From
Power Button Suspend or soft-off RTC Alarm Suspend or soft-off Wake On LAN (w/NIC) Suspend or soft-off PME Suspend or soft-off Serial Port Ring Suspend or soft-off USB Suspend only Keyboard Suspend only Mouse Suspend only
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4.7.3 SYSTEM STATUS
These systems provide a visual indication of system boot and ROM flash status through the keyboard LEDs as listed in table 4-12.
NOTE: The LED indications listed in Table 4-12 are valid only for PS/2-type keyboards. A USB keyboard will not provide LED status for the listed events, although audible (beep) indications will occur.
Table 4-12. System Boot/ROM Flash Status LED Indications
System Boot/ROM Flash Status LED Indications
Event
System memory failure [1] Blinking Off Off Graphics controller failure [2] Off Blinking Off System failure prior t o graphi cs cntlr. initiali zat i on [ 3] Off Off Blinking ROMPAQ diskette not present , faulty, or drive prob. On Off Off Password prompt Off On Off Invalid ROM detected - flash fai l e d Blinking [4] Blinking [4] Blinking [4] Keyboard locked in network mode B l i nking [5] Blinking [5] Blinking [5] Successful boot bl ock ROM flash On [ 6] On [6] On [6]
NOTES:
[1] Accompanied by 1 short, 2 long audio beeps [2] Accompanied by 1 l ong, 2 short audio beeps [3] Accompanied by 2 l ong, 1 short audio beeps [4] All LEDs will blink in sync twice, accompanied by 1 long and three short audio beeps [5] LEDs will blink in sequence (NUM Lock, then CA P s Lock, then Scroll Lock) [6] Accompanied by ri sing audio tone.
Table 4-12.
NUM Lock
LED
Technical Reference Guide
CAPs Lock
LED
Scroll Lock
LED
Table 4-13 lists the operation status codes provided by the power LED on the front of the chassis. Note that error or problem conditions are reported only by the power LED on the minitower.
Table 4-13. System Operational Status LED Indications
Table 4-13.
System Operational Status LED Indications
System Status
S0: System on (normal operation) Steady green Steady green S1: Suspend Blinks green @ 1 Hz Blinks green @ 1 Hz S3: Suspend to RAM Blinks green @ 1 Hz Bl i nks green @ 1 Hz S4: Suspend to disk Blinks green @ 0.5 Hz Blinks green @ 0.5 Hz S5: Soft off Off - clear Off - clear Processor not seated Off - c l ear Steady red CPU thermal shutdown Off - clear Blinks red @ 4 Hz ROM error Off - clear Blinks red @ 1 Hz Power supply crowbar activated Off - clear Blinks red @ .5 Hz System off Off - clear Off
Desktop
Power LED
Minitower
Power LED
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Chapter 4 System Support
4.7.4 TEMPERATURE SENSING AND COOLING
These systems feature a fan integrated into the power supply assembly. A separate chassis fan is also employed. Both fans are variable-speed type, and typically operate in tandem as long as the power supply is active (producing 12 VDC). The fans are off in S3 (Suspend-to-RAM) and S5 (Soft-Off) states.
NOTE: These systems are designed to provide optimum cooling with the cover in place. Operating a system with the cover removed may result in a thermal condition of system board components, including the processor.
Figure 4-11 shows the fan c ontrol schematic.
Chassis Fan
Header P8
(+)
P1
24 12
8
(-)
Fan Off
ICH2
SMBus
Processor
Sensing
ASIC
Fan Sense [1]
Fan CMD Fan Off-
Therm-
CH Fan CMD
On/Off
Control
82801
ICH2
4
4
3
3
2
2
Power Supply Assembly
Speed
Control
(+)
(-)
PS Fan CMD
On/Off
Control
PS Fan
(-)
(+)
NOTE:
[1] Will be +12 VDC if c hassis fan is connected and operat ing.
Figure 4-11. Fan Control Block Diagram
An ASIC monitors a thermal diode internal to the processor and provides a Fan CMD signal that the Speed Control logic of the power supply uses to var y the speed of the fans thr ough the negative power rail. The turning off of the fans as the result from the system being placed into a Sleep condition is initiated by the ASIC asserting the Fan Off- signal, which results in the On/Off Control logic shutting off the +12 volts to the fans.
Typical cooling conditions include the following:
1. Normal – Low fan speed.
2. Hot processor – ASIC directs Speed Control logic to increase speed of fan(s).
3. Hot power supply – Power supply increases speed of fan(s).
4. Sleep state – Fans turned off. Hot processor or power supply will result in starting fans.
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Technical Reference Guide
4.8 REGISTER MAP AND MISCELLANEOUS FUNCTIONS
This section contains the system I/O map and information on general-purpose functions of the ICH and I/O controller.
4.8.1 SYSTEM I/O MAP
Table 4-14 lists the fixed addresses of the input/output (I/O) ports. Table 4-14. System I/O Map
Table 4-14.
System I/O Map
I/O Port Function
0000..001Fh DMA Controller 1
0020..002Dh Interrupt Controll er 1 002E, 002Fh Index, Data Ports to LPC47B357 I/O Controller (primary)
0030..003Dh Interrupt Controll er
0040..0042h Timer 1 004E, 004Fh Index, Data Ports to LPC47B357 I/O Controller (secondary)
0050..0052h Timer / Counter
0060..0067h Microcontroller, NMI Controller (alternating addresses)
0070..0077h RTC Controller
0080..0091h DMA Controller 0092h Port A, Fast A20/Reset Generator
0093..009Fh DMA Controller 00A0..00B1h Interrupt Controller 2 00B2h, 00B3h APM Control/Status Ports 00B4..00BDh Interrupt Controller 00C0..00DFh DMA Controller 2 00F0h Coprocessor error register
0170..0177h IDE Controller 2 (active only if standard I/ O space is enabled for primary drive) 01F0..01F7h IDE Controller 1 (active only if standard I/O space is enabled for secondary drive)
0278..027Fh Parallel Port (LPT 2) 02E8..02EFh Serial Port (COM4) 02F8..02FFh Serial Port (COM2)
0370..0377h Diskette Drive Controller Secondary Address 0376h IDE Controller 2 (active only if standard I/O space is enabled for prim ary dri ve)
0378..037Fh Parallel Port (LPT 1) 03B0..03DFh Graphics Controller 03BC..03BEh Parallel Port (LPT3) 03E8..03EFh Serial Port (COM3) 03F0..03F5h Di skette Drive Controller Primary Addresses 03F6h IDE Controller 1 (act i ve onl y i f standard I/O space is enabled f or sec. drive) 03F8..03FFh Serial Port (COM1) 04D0, 04D1h Interrupt Controller
0678..067Fh Parallel Port (LPT 2)
0778..077Fh Parallel Port (LPT 1) 07BC..07BEh Parallel Port (LPT3) 0CF8h PCI Configuration Address (dword access onl y ) 0CF9h Reset Control Register 0CFCh PCI Configuration Data (byte, word, or dword acces s)
NOTE:
Assume unmark ed gaps are unused, reserved, or used by functions that employ variable I /O address mapping. Some ranges may include reserved addres ses.
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4.8.2 82801 ICH GENERAL PURPOSE FUNCTIONS
The 82801 ICH2 component includes a number of single and multi-purpose pins available as general-purpose input/output (GPIO) ports. The GPIO ports are configured (enabled/disabled) during POST by BIOS through the PCI configuratio n registers of the ICH ’s LPC I/F Bridge (82801, function 0). The GPIO ports are controlled through 64 bytes of I/O space that is mapped during POST.
Table 4-15 lists the utilization of the ICH’s GPIO ports in the desktop and minitower systems. Table 4-15. 82801 ICH GPIO Register Utilization (Desktop and Minitower only)
Table 4-15.
82801 ICH2 GPIO Register Utilization
GPIO Port # Function Direction
0PS LED I 1NIC REQ5 I 2IRQE- I 3IRQF- I 4 IRQG- I 5 IRQH- I 6HD LED I 7-- NC 8NC 12 TAFI ASIC Interrupt I 13 SMI I 18 -- NC 19 -- NC 20 -- NC 21 -- NC 22 -- NC 23 -- NC 24 NC 25 -- NC 26 NC 27 NC 28 Password Enable I
NOTE:
NC = not connected (not used).
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4.8.3 I/O CONTROLLER FUNCTIONS
The I/O controller (used in desktop and minitower systems) contains various functions such as the keyboard/mouse interfaces, diskette interface, serial interfaces, and parallel interface. While the control of these interfaces uses standard AT-type I/O addressing (as described in chapter 5) the configuration of these functions o ccurs through indexed ports using PnP protocol. In these systems, hardware strapping selects I/O addresses 02Eh/02Fh at reset as the Index/Data ports for accessing the logical devices within the I/O contoller. Table 4-16 lists the PnP control registers for the LPC47B357.
Table 4-16 LPC47B357 Control Registers
Table 4-16.
I/O Controller Control Registers
Index Function Reset Value
02h Configuration Cont rol 00h 03h Reserved 07h Logical Devic e (Interface) Select:
00h = Diskette Drive I/F 01h = Rsvd 02h = Rsvd 03h = Parallel I/F 04h = Serial I/F (UART 1) 05h = Serial I/F (UART 2) 06h = Rsvd 07h = Keyboard I/F 08h = Rsvd 09h = Rsvd 0Ah = Runtime Reg. (GPIO Confi g.)
0Bh = Rsvd 20h Super I/O ID Regi ster (SID) 56H 21h Revision -­22h Logical Devic e Power Control 00h 23h Logical Devic e P ower Management 00h 24h PLL / Oscillator Control 04h 25-2Fh Device specific [2] --
NOTES:
Refer to LPC47B357 data sheet for detailed register informat i on.
Technical Reference Guide
00h
The configuration registers are accessed through I/O registers 2Eh (index) and 2Fh (data) after the configuration phase has been activated by writing 55h once to I/O port 2Eh. The BIOS then initiates each logical device and then deactivates the configuration phase by writing AAh to 2Eh.
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Chapter 4 System Support
4.8.3.1 LPC47B357 GPIO Utilization
The LPC47B357 I/O Controller (used in desktop and minitower systems) provides 62 general­purpose pins that can be individually configured for specific purposes. These pins are configured through the Runtime registers (logical device 0Ah) during t he system’s configuration phas e of the boot sequence by the BIOS.
Table 4-17 lists the GPIO registers for the LPC47B357. Note that not all ports are listed as this table defines only the custom implementation of GPIO ports. Refer to SMC documentation for standard usage of unlisted GPIO ports.
Table 4-17. LPC47B357 GPIO Register Utilization (Desktop and Minitower only)
LPC47B357 GPIO Port Utilization
GPIO Function Direction GPIO Function Direction
10 Board rev 1 I 42 ICH SCI O 11 Board rev 0 I 43 -- NC 12 -- NC 44 Hood Lock NC 13 PME- I 45 Hood Unlock NC 14 WOL NC 46 ICH SMI- O 15 System I D 4 [ 1] I 60 PCI Slot Reset O 16 Processor Fan sense I 61 AGP S l ot Reset O 17 -- NC 62 PWR Button In I 20 Pri. IDE 80-pin Cable Detect I 63 SLP S3 I 21 Sec. IDE 80-pin Cabl e Detect I 64 SLP S5 I 22 -- NC 65 CPU Changed/Removed O 23 System I D 2 [ 1] I 66 PWR Button Out O 24 BIOS fail for AOL O 67 PS On O 25 System I D 3 [ 1] I 70 Remote Off I 26 Processor Present I 71 System ID 0 [1] NC 27 -- NC 72 System ID 1 [1] NC 30 PS LED Color Grn O 73 -- NC 31 PS LED Blink O 74 -- NC 32 Thermal Trip I 75 -- NC 33 2 MB Media ID I 76 -- NC 34 FWH Write Protect O 85 Pwr SEL O 35 FWH Reset O 86 S3 3.3 VDC On O 36 Diskette Mot or B O -- -- -­37 Diskette Select B O -- -- --
NOTE:
NC = Not connected (not used). [1] System ID (I D4..0) value for these systems = 00111.
Table 4-17.
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Technical Reference Guide
4.8.3.2 LPC47B357 I/O Controller Miscellaneous Functions
The desktop and minitower systems utilize the following specialized functions built into the LPC 47B357 I/O Controller:
Power/Hard drive LED control – The I/O controller provides color and blink control for the
front panel LEDs used for indicating system events as listed below:
System Status Power LED HD LED
S0: System on (normal operation) St eady green Green w/HD activity S1: Suspend Blinks green @ 1 Hz Off S3: Suspend to RAM B l i nks green @ 1 Hz Off S4: Suspend to disk Blinks green @ 0.5 Hz Off S5: Soft off Off - clear Off Backplane board not seated St eady red Steady red Processor not seated Steady red Off CPU thermal shutdown Blinks red @ 4 Hz Off ROM error Blinks red @ 1 Hz Off Power supply crowbar activated Blinks red @ 0.5 Hz Off System off Off Off
I/O security – The parallel, serial, and diskette interfaces may be disabled individually by
software and the LPC47B357’s disabling register locked. If the disabling register is locked, a system reset through a cold boot is required to gain access to the disabling (Device Disable) register.
Processor present/speed detection – One of the battery-back general-purpose inputs (GPI26)
of the LPC47B357 detects if the processor has been removed. The occurrence of this event is passed to the ICH that will, during the next boot sequence, initiate the speed selection routine for the processor. The speed selection function replaces the manual DIP switch configuration procedure required on previous systems.
Legacy/ACPI power button mode control – The LPC47B357 receives the pulse signal from
the system’s power button and produces the PS On signal according to the mode (legacy or ACPI) selected. Refer to chapter 7 for more information regarding power management.
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Chapter 4 System Support
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Chapter 5 INPUT/OUTPUT INTERFACES
5. Chapter 5 INPUT/OUTPUT INTERFACES
5.1 INTRODUCTION
This chapter describes the standard (i.e., system board) interfaces that provide input and output (I/O) porting of data and specifically discusses interfaces that are controlled through I/O-mapped registers. The following I/O interfaces are covered in this chapter:
Enhanced IDE interface (5.2) page 5-1Diskette drive interface (5.3) page 5-4Serial interfaces (5.4) page 5-8Parallel interface (5.5) page 5-11Keyboard/pointing device interface (5.6) page 5-16Universal serial bus interface (5.7) page 5-22Audio subsystem (5.8) page 5-26Network support (5.9) page 5-33
Technical Reference Guide
5.2 ENHANCED IDE INTERFACE
The enhanced IDE (EIDE) interface consists of primary and secondary controllers integrated into the 82801 ICH2 component of the chipset. Two 40-pin IDE connectors (one for each controller) are included on the system board. Each controller can be configured independently for the following modes of operation:
Programmed I/O ( PIO) mode – CPU controls drive transactions through standard I/O mapped
registers of the IDE drive.
8237 DMA mode – CPU offloads drive transactions using DMA protocol with transfer rates
up to 16 MB/s.
Ultra ATA/100 mode – Preferred bus mastering source-synchronous protocol providing
transfer rates of 100 MB/s.
NOTE: These systems include 80-conductor data cables required for UATA/66 and /100 modes.
5.2.1 IDE PROGRAMMING
The IDE interface is configured as a PCI device during POST and controlled through I/O-mapped registers at runtime.
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Hard drives types not found in the ROM’s parameter table are automatically configured as to (soft)type by DOS as follows:
Primary controller: drive 0, type 65; drive 1, type 66 Secondary controller: drive 0, type 68; drive 1, type 15
Non-DOS (non-Windows) operating systems may require using Setup (F10) for drive configuration.
5.2.1.1 IDE Configuration Registers
The IDE controller is configured as a PCI device with bus mastering capability. The PCI configuration registers for the IDE controller function (PCI device #31, function #1) are listed in Table 5-1. Table 5–1. IDE PCI Configur ation Registers
EIDE PCI Configuration Registers (82801, Device 31/Function 1)
PCI Conf. Addr. Register
00-01h Vender ID 8086h 0F..1Fh Reserved 0’s 02-03h Device ID 244Bh 20-23h BMIDE Base Address 1 04-05h PCI Command 0000h 2C, 2Dh Subsystem Vender ID 0000h 06-07h PCI Stat us 0280h 2E, 2Fh Subs ystem ID 0000h 08h Revision ID 00h 30..3Fh Reserved 0’s 09h Programming 80h 40-43h P ri ./Sec. IDE Timi ng 0’s 0Ah S ub-Cl ass 01h 44h Slave IDE Timi ng 00h 0Bh B ase Class Code 01h 48h Sync. DMA Control 00h 0Dh Master Latency Tim er 00h 4A -4B h S ync . DMA Timing 0000h 0Eh Header Type 00h 54h EIDE I/O Config.Register 00h
NOTE:
Assume unmark ed gaps are reserved and/or not used.
Table 5-1.
Reset Value
PCI Conf. Addr. Register
Reset Value
5.2.1.2 IDE Bus Master Control Registers
The IDE interface can perform PCI bus master operations using the registers listed in Table 5-2. These registers occupy 16 bytes of variable I/O space set by software and indicated by PCI configuration register 20h in the previous table. Table 5–2. IDE Bus Master Control Registers
Table 5-2.
IDE Bus Master Control Registers
I/O Addr. Offset
00h 1 Bus Master IDE Command (Primary) 00h 02h 1 Bus Master IDE Status (Primary) 00h 04h 4 Bus Master IDE Descriptor Pointer (Pri.) 0000 0000h 08h 1 Bus Master IDE Command (Sec ondary) 00h 0Ah 2 Bus Master IDE Status (Secondary) 00h 0Ch 4 Bus Master IDE Descriptor Point er (Sec.) 0000 0000h
NOTE:
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Size
(Bytes) Register
Unspecified gaps are reserved, will return indeterminat e data, and should not be written to.
Default
Value
First Edition – December 2000
5.2.2 IDE CONNECTOR
This system uses a standard 40-pin connector for the primary IDE device and connects (via a cable) to the hard drive installed in the right side drive bay. Note that some signals are re-defined for UATA/33 and UATA/66 modes, which require a special 80-conductor cable (supplied) designed to reduce cross-tal k. Device power is supplied through a separate connector.
Figure 5-1. 40-Pin Primary IDE Connector (on system board).
Table 5–3. 40-Pin Primar y IDE Connector Pinout
Pin Signal Description Pin Signal Description
1 RESE T - Reset 21 DRQ DMA Request 2 GND Ground 22 GND Ground 3 DD7 Data Bit <7> 23 IOW- I/O Write [1] 4 DD8 Dat a B i t <8> 24 GND Ground 5 DD6 Dat a B i t <6> 25 IOR- I/O Read [2] 6 DD9 Dat a B i t <9> 26 GND Ground 7 DD5 Dat a B i t <5> 27 IORDY I/O Channel Ready [ 3] 8 DD10 Data Bit <10> 28 CSE L Cable Sel ect 9 DD4 Dat a B i t <4> 29 DAK- DMA Acknowledge 10 DD11 Data Bit <11> 30 GND Ground 11 DD3 Data Bit <3> 31 IRQn Interrupt Request [4] 12 DD12 Data Bit <12> 32 IO16- 16-bit I/O 13 DD2 Data Bit <2> 33 DA1 Address 1 14 DD13 Data Bit <13> 34 DSKPDIAG Pass Diagnostics 15 DD1 Data Bit <1> 35 DA0 Address 0 16 DD14 Data Bit <14> 36 DA2 Address 2 17 DD0 Data Bit <0> 37 CS0- Chip Select 18 DD15 Data Bit <15> 38 CS1- Chip Sel ect 19 GND Ground 39 HDACTIVE- Drive Active (f ront panel LED) [5] 20 -- Key 40 GND Ground
NOTES:
[1] On UATA/33 and higher modes, re-defined as STOP. [2] On UATA/33 and higher mode reads , re-defined as DMARDY-. On UATA/33 and higher mode writes, re-defi ned as STROBE. [3] On UATA/33 and higher mode reads , re-defined as STROBE-. On UATA/33 and higher mode writes, re-def i ned as DMARDY-. [4] Primary connector wired to IRQ14, secondary connector wired to I RQ15. [5] Pin 39 is used for s pi ndl e sync and drive activity (becom es SPSYNC/DACT-) when synchronous drives are connected.
Technical Reference Guide
Table 5-3.
40-Pin Primary IDE Connector Pinout
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5.3 DISKETTE DRIVE INTERFACE
The diskette drive interface supports up to two diskette drives, each of which use a common cable connected to a standard 34-pin diskette drive connector. All models come standard with a 3.5-inch
1.44-MB diskette drive installed as drive A. The drive designation is determined by which connector is used on the diskette drive cable. The drive attached to the end connector is drive A while the drive attached to the second (next to the end) connector) is drive B.
On all models, the diskette drive interface function is integrated into the LPC47B357 super I/O component. The internal logic of the I/O controller is software-compatible with standard 82077­type logic. The diskette drive controller has three operational phases in the following order:
Command phase - The controller receives the command from the system.Execution phase - The controller carries out the command.Results phase - Status and results data is read back from the controller to the system.
The Command phase consists of several bytes written in series from the CPU to the data register (3F5h/375h). The first byte identifies the command and the remaining bytes define the parameters of the command. The Main Status register (3F4h/374h) provides data flow control for the diskette drive controller and must be polled between each byte transfer during the Command phase.
The Execution phase starts as soon as the last byte of the Command phase is received. An Execution phase may involve the transfer of data to and from the diskette drive, a mechnical control function of the drive, or an operation that remains internal to the diskette drive controller. Data transfers (writes or reads) with the diskette drive controller are by DMA, using the DRQ2 and DACK2- signals for control.
The Results phase consists of the CPU reading a series of status bytes (from the data register (3F5h/375h)) that indicate the results of the command. Note that some commands do not have a Result phase, in which case the Execution phase can be followed by a Command phase.
During periods of inactivity, the diskette drive controller is in a non-operation mode known as the Idle phase.
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5.3.1 DISKETTE DRIVE PROGRAMMING
Programming the diskette drive interface consists of configuration, which occurs typically during POST, and control, which occurs at runtime.
5.3.1.1 Diskette Drive Interface Configuration
The diskette drive controller must be configured for a specific address and also must be enabled before it can be used. Address selection and enabling of the diskette drive interface are affected by firmware through the PnP configuration registers of the 47B357 I/O controller during POST.
The configuration registers are accessed through I/O registers 2Eh (index) and 2Fh (data) after the configuration phase has been activated by writing 55h to I/O port 2Eh. The diskette drive I/F is initiated by firmware selecting logical device 0 of the 47B357 using the following sequence:
1. Write 07h to I/O register 2Eh.
2. Write 00h to I/O register 2Fh (this selects the diskette drive I/F).
3. Write 30h to I/O register 2Eh.
4. Write 01h to I/O register 2Fh (this activates the interface).
Technical Reference Guide
Writing AAh to 2Eh deactivates the configuration phase. The diskette drive I/F configuration registers are listed in the following table:
Table 5–4. Diskette Drive Controller Configuration Registers
Table 5-4.
Diskette Drive Interface Configuration Registers
Index
Address Function R/W
30h Activate R/W 01h
60-61h Base Address R/W 03F0h
70h Interrupt Select R/W 06h 74h DMA Channel Select R/W 02h F0h DD Mode R/W 02h F1h DD Option R/W 00h F2h DD Type R/W FFh F4h DD 0 R/W 00h F5h DD 1 R/W 00h
For detailed configuration register information refer to the SMSC data sheet for the LPC47B357 I/O component.
5.3.1.2 Diskette Drive Interface Control
The BIOS function INT 13 provides basic control of the diskette drive interface. The diskette drive interface can be controlled by software through the LPC47B357’s I/O-mapped registers listed in Table 5-5. The diskette drive controller of the LPC47B357 operates in the PC/AT mode in these systems. Table 5–5. Diskette Drive Interface Control Registers
Reset Value
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Diskette Drive Interface Control Registers
Pri.
Addr.
3F0h 370h Status Register A:
3F1h 371h Status Register B:
3F2h 372h Digital Output Register (DOR):
3F3h 373h Tape Drive Register (available for compatibility) R/W 3F4h 374h Main Status Register (MSR):
3F5h 375h Data Register: 3F6h 376h Reserved --
3F7h 377h Digital Input Register (DIR):
NOTE: The most recently written data rate value to either DRSR or CCR will be in effect.
Sec.
Addr. Register R/W
<7> Interrupt pending <6> Reserved (always 1) <5> STEP pin status (ac tive high) <4> TRK 0 status (active high) <3> HDSEL status (0 = side 0, 1 = s i de 1) <2> INDEX status (active high) <1> WR PRTK stat us (0 = di sk is write protected) <0> Direction (0 = outward, 1 = inward)
<7,6> Reserved (always 1’s) <5> DOR bit 0 status <4> Write data toggle <3> Read data toggle <2> WGATE st atus (active high) <1,0> MTR 2, 1 ON- status (acti ve high)
<7,6> Reserved <5,4> Motor 1, 0 enable (active high) <3> DMA enable (active high) <2> Reset (active low) <1,0> Drive select (00 = Drive 1, 01 = Drive 2, 10 = Reserved, 11 = Tape drive)
<7> Request for master (hos t can transfer data) (active high) <6> Transfer direction (0 – write, 1 = read) <5> non-DMA execution (active high) <4> Command busy (active hi gh) <3,2> Reserved <1,0> Drive 1, 2 busy (active high) Data Rate Select Register (DRSR): <7> Software reset (active high) <6> Low power mode enable (active high) <5> Reserved (0) <4..2> Precompensati on select (default = 000) <1,0> Data rate select (00 = 500 Kb/s, 01 = 300 Kb/s, 10 = 250 Kb/s, 11 = 2/ 1 Mb/s)
<7..0> Data
<7> DSK CHG status (records opposite value of pin) <6..0> Reserved (0’s) Configuration Control Register (CCR): <7..2> Reserved <1,0> Data rate select (00 = 500 Kb/s, 01 = 300 Kb/s, 10 = 250 Kb/s, 11 = 2/ 1 Mb/s)
Table 5-5.
R
R
R/W
R
W
R/W
R
W
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