Compal LA-B412P Schematics

A

B

C

D

E

1

ZFWAA

Dione 10FU/10FUT

2

LA-B412P REV 0.2 Schematic

2

3

Intel Processor (Ivy Bridge) + PCH (Panther Point)

3

2014-01-02 Rev 0.2

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

LAB412P

141Wednesday, January 22, 2014

E

of

4

0.2

A

B

C

D

E

RTC CKT.

DC/DC Interface CKT.

1

Power Circuit DC/DC

page ??

GCLK

SLG3NB244VTR

2

3

Sub Boards

LS-B301P LED/B

LS-B302P Power Button/B

page 16

page 32

page 26

page 31

LVDS & eDP Conn.

CRT Conn.

page 14

HDMI Conn.

page 15

RJ45 Conn.

page 13

RTL8106E & 8111G

PCIe port 1

USB Left

USB20 port 2

page 27

To sub-board (JLAN)

SPI ROM (8MB)

page 16

eDP 1.1 2x

2.7GT/s

PCIe Gen1 1x

1.5V 5GT/s

USB20 1x

5V 480MHz

KB9012

page 30

Intel CPU Ivy Bridge 17W

BGA-1023

31mm*24mm

page 5,6,7,8,9,10

FDI X8

2.7GT/s

DMI X4

5GT/s

Intel PCH Panther Point

FCBGA-989

25mm*25mm

page 16,17,18,19,20,21,22,23,24

LPC BUS

3.3V 33 MHz

TPM

NPCT650

page 26

Memory BUS(DDR3L)

Dual Channel

1.35V DDR3L 1600 MT/s

USB30 1x

5V 5GT/s

USB20 2x

5V 480MHz

USB20 2x

5V 480MHz

PCIe Gen1 1x

1.5V 5GT/s

USB20 1x

5V 480MHz

PCIe Gen1 1x

1.5V 5GT/s

SATA Gen3 1x

5V 6GHz(600MB/s)

SATA Gen2 1x

5V 3GHz(300MB/s)

HD Audio

3.3V 24MHz

HDA Codec

ALC233-VB2

page 29

204pin DDR3-SO-DIMM X2

BANK 0, 1, 2

USB Right 3.0*1+2.0*1

USB20 port 0,1 USB30 port 1

Int. Camera

USB port 11

page 13

NGFF Slot 1 - WLAN & BT

PCIe port 2 & USB port 9

Card Reader

PCIe port 4

page 31

page 28

Touch Screen

USB port 8

To sub-board (JCARD)

SATA HDD

SATA port 0

SATA ODD

SATA port 2

page 25

page 11,12

page 13

page 25

www.schematic-x.blogspot.com

1

2

3

LS-B303P LAN+USB/B Audio Combo Jack

4

LS-B304P CardReader/TP/LID B

page 27

page 31

A

Touch Pad+LID/B

page 31 page 31

To sub-board (JCARD)

SPK Conn

LED/B

Int.KBD

page 31

page 29

To sub-board (JLED)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

JCOM (Combo Jack)

D

page 27

To sub-board (JLAN)

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Block Diagram

LAB412P

E

4

0.2

of

241Wednesday, January 22, 2014

of

241Wednesday, January 22, 2014

of

241Wednesday, January 22, 2014

5

3V5V_EN

B+

D

C

SY8208CQNC

SUSP#

TPS22966DPUR

3V5V_EN_3

Ipeak=5A, Imax=3.5A, Iocp min=6A

SY8206BQNC

SUSP#

TPS22966DPUR

4

Ipeak8A, Imax=5.6A, Iocp min=9A

PCH_PWR_EN#

P-CHANNEL

AO-3413

USB_EN#0

SY6288D20AAC

USB_EN#2

SY6288D20AAC

ODD_EN

TPS22967DSGR

+5VS

AP2151DWG

WOWL_EN

TPS22967DSGR

PCH_PWR_EN#

P-CHANNEL

AO-3413

For ZPODD

For ISCT/WOWL

DESIGN CURRENT 2A

DESIGN CURRENT 6A

DESIGN CURRENT 1A

DESIGN CURRENT 0.1A

DESIGN CURRENT 6A

+5VALW

+5VALW_PCH

+USB_VCCB

+USB_VCCC

+5VS

+5VS_ODD

+HDMI_5V_OUT

+3VL

+3VALW

+3V_WLAN

+3VALW_PCH

+3V_LAN

+3VS

3

2

1

D

C

+3V_WLAN

LCD_ENVDD

SUSP#

B

SY8032ABC

SY6288C20AAC

+1.5V_EN

DESIGN CURRENT 2A

APL5930KAI

VR_ON

ISL95833HRTZ

SUSP#

SY8208DQNC

SYSON

RT8207MZQW

A

Ipeak=10A, Imax=7A, Iocp min=12A

VCCP_PWRGOOD

G978F11U

Ipeak=9A, Imax=6.3A, Iocp min=11A

0.675VR_ON

SUSP

N-CHANNEL

AO4354

DESIGN CURRENT 45A

DESIGN CURRENT 6A

DESIGN CURRENT 1.5A

DESIGN CURRENT 5A

+LCD_VDD

+1.8VS

+1.5VS

+CPU_CORE

+GFX_CORE

+1.05VS_VCCP

+VCCSA

+1.05VS_PCH

+1.35V

+0.675VS

+1.35V_CPU

B

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Power Tree

LAB412P

1

of

341Wednesday, January 22, 2014

of

341Wednesday, January 22, 2014

of

341Wednesday, January 22, 2014

0.2

Voltage Rails

1

State

power plane

A

( O MEANS ON X MEANS OFF )

+RTCVCC

B+

+LCD_INV

+3VL

+5VALW

+3VALW

B

C

D

E

BTO Option Table

+1.35V

+5VS

+3VS

+1.8VS

+1.5VS

+1.35V_CPU

+0.675VS

+CPU_CORE

+GFX_CORE

+VCCSA

+1.05VS_VCCP

+3V_WLAN

+LCD_VDD

Function

description

explain

BTO

Function

description

explain

BTO

Ivy Bridge

i3-3217U

CPUR1@

LVDS-eDP

LVDS eDP

LVDS@ IEDP@

PCHCPU

Panther Point

HM76

HM76R1@

Camera

CAM_EMI@

ISPD

HDMI LOGO

HDMI45@

CRT

w/ CRT w/o CRT

CRT@ CRT@EMI@ NOCRT@

EMI/ESD/RF part

EMI@ @EMI@ ESD@ @ESD@ @RF@

Red Word: always un-mount

ISCT

w/

ISCT@

w/o

NOISCT@

1

S0

S1

S3

2

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

PCH SM Bus Address

Power

+3VS

+3VS Touch Pad

3

EC SM Bus1 Address

+3VL

O

X

O

XX

X

XX

OO

X

Device

DDR SO-DIMM 0

DDR SO-DIMM 1

O

X

HEX

O

X

Address

1010 0000 bA0 H

1010 0100 bA4 H

O

EC SM Bus2 Address

Device Address Address

HEX HEX

16 H

0001 0110 bSmart Battery

12 HSmart Charger 0001 0010 b+3VL

PowerPower

+3VS

Device

96 H

1001 0110 bPCH

Function

description

explain

BTO

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

G3 LOW LOWLOW

SIGNAL

ZPODD

w/

ZPODD@

w/o

NONZP@

SLP_S3# SLP_S4# SLP_S5#

HIGH HIGHHIGH

LOW

HIGH

LOW LOW

LOW LOWLOW

TPM

NPCT650

TPM@

HIGH

Touch Screen

w/ TOUCH

TOUCH_EMI@

2

3

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Notes List

LAB412P

441Wednesday, January 22, 2014

E

of

4

0.2

1

2

+3VALW_PCH

A

@

PM_DRAM_PWRGD_R

1

2

CC621000P_0402_50V7K

ESD@

1

2

CC63180P_0402_50V8J

@ESD@

1

2

CC20100P_0402_50V8J

by ESD requestion and place near CPU

+1.05VS_VCCP

1

2

RC44 62_0402_5%

1

2

RC45 10K_0402_5%

2

H_PROCHOT#

H_PWRGOOD

@

1

CC701000P_0402_50V7K

@

1

CC671000P_0402_50V7K

@

1

CC661000P_0402_50V7K

Please place near UC1

DRAMPWROK

1

2

RC11 200_0402_5%

10K_0402_5%

+3VS

DRAMPWROK<18>

DRAMPWROK

1

2

RC13

2

H_PWRGOOD

H_THERMTRIP#

H_PECI

H_PM_SYNC

BUF_CPU_RST#

+3VALW_PCH

UC3

5

74AHC1G09GW_TSSOP5

P

B

4

O

A

G

3

PM_SYS_PWRGD_BUF

B

H_SNB_IVB#<21>

H_PECI<30>

H_PROCHOT#<30>

H_THERMTRIP#<21>

H_PM_SYNC<18>

H_PWRGOOD<21>

PM_SYS_PWRGD_BUF

+1.35V_CPU

1

RC14

200_0402_5%

2

T1 PAD @

T2 PAD @

RC170 130_0402_5%

RC159

1

H_THERMTRIP#

1

BUF_CPU_RST#

TP_SKTOCC#

H_CATERR#

H_PECI

H_PROCHOT#_R

2

56_0402_5%

H_PM_SYNC

H_PWRGOOD

PM_DRAM_PWRGD_R

2

UC1B

F49

PROC_SELECT#

C57

PROC_DETECT#

C49

CATERR#

A48

PECI

C45

PROCHOT#

D45

THERMTRIP#

C48

PM_SYNC

B46

UNCOREPWRGOOD

BE45

SM_DRAMPWROK

D44

RESET#

IVY-BRIDGE_BGA1 023

CPUR1@

C

100 MHz

J3

BCLK

MISC THERMAL PWR MANAGEMENT

DPLL_REF_CLK

DPLL_REF_CLK#

CLOCKS

SM_DRAMRST#

SM_RCOMP[0]

SM_RCOMP[1]

SM_RCOMP[2]

DDR3

MISC

DDR3

MISC

JTAG & BPM

BCLK#

PRDY#

PREQ#

TCK

TMS

TRST#

TDO

DBR#

BPM#[0]

BPM#[1]

BPM#[2]

BPM#[3]

BPM#[4]

BPM#[5]

BPM#[6]

BPM#[7]

TDI

H2

120 MHz

CLK_CPU_EDP

AG3

CLK_CPU_EDP#

AG1

H_DRAMRST#

AT30

SM_RCOMP_0

BF44

SM_RCOMP_1

BE43

SM_RCOMP_2

BG43

N53

N55

XDP_TCK

L56

XDP_TMS

L55

XDP_TRST#

J58

XDP_TDI

M60

XDP_TDO

L59

K58

G58

E55

E59

G55

G59

H60

J59

J61

D

CLK_CPU_DMI <17>

CLK_CPU_DMI# <17>

CLK_CPU_EDP <17>

CLK_CPU_EDP# <17>

H_DRAMRST# <7>

1

2

RC56 140_0402_1%

RC59 25.5_0402_1%

RC61 200_0402_1%

1

2

1

2

T3 PAD@

T4 PAD@

1

T6 PAD@

T7 PAD@

2

RC55 51_0402_5%

Close to CPU side

E

Stuff RC158&RC157 if do not support eDP

+1.05VS_VCCP

LVDS@

CLK_CPU_EDP#

CLK_CPU_EDP

H_DRAMRST#

LVDS@

1

LVDS@

@ESD@

2

RC157 1K_0402_5%

RC158 1K_0402_5%

CC34 180P_0402_50V8J

by ESD requestion and place near CPU

DDR3 Compensation Signals Layout Note:Place these resistors near Processor

1

2

3

FAN Control Circuit

+5VS

Buffered Reset to CPU

+3VS

PLT_RST# <20,25,26,27,30,31>

UC2

PLT_RST#

4

UC2

1

OE#

IN

GND

VCC

OUT

2

3

74AHC1G125GW_SOT353-5

A

5

BUFO_CPU_RST#

4

+1.05VS_VCCP

1

RC38

75_0402_5%

2

43_0402_1%

1

RC35

BUF_CPU_RST#

2

DFAN1 from EC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

1A

2013/12/17 2014/12/17

+5VS_FAN

1

2

@

R1 0_0603_5%

+FAN2

DFAN1<30>

10mil

1

2

Main source SA00005CA00 2nd source SA00005JO00

Compal Secret Data

Deciphered Date

U1

1

EN

2

VIN

3

VOUT

4

VSET

NCT3942S_SOP 8P

C3

10U_0603_6.3V6M

C1

10U_0603_6.3V6M

8

GND

7

GND

6

GND

5

GND

D

+FAN2

@

1

2

C2

1000P_0402_50V7K

2

1

JFAN

@

1

2

3

4

GND

5

GND

CVILU_CI4403M1HRT-NH

R2 10K_0402_5%

1

2

1

C4

0.01U_0402_25V7K

@

2

+3VS

FAN_SPEED1 <30>

FAN_SPEED1 to EC

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Ivy Bridge_JTAG/XDP/FAN

LAB412P

E

4

0.2

of

541Wednesday, January 22, 2014

of

541Wednesday, January 22, 2014

of

541Wednesday, January 22, 2014

A

B

C

D

E

+1.05VS_VCCP

RC1

24.9_0402_1%

UC1A

1

2

+1.05VS_VCCP

eDP_COMP signals should be shorted near balls and routed with typical impedance <25m ohm

3

+1.05VS_VCCP

2

1

H_EDP_HPD#

1

D

IEDP@

RC9

2

G

S

3

2

1

CPU_EDP_HPD<13>

100K_0402_5%

4

DMI_PTX_CRX_N0<18>

DMI_PTX_CRX_N1<18>

DMI_PTX_CRX_N2<18>

DMI_PTX_CRX_N3<18>

DMI_PTX_CRX_P0<18>

DMI_PTX_CRX_P1<18>

DMI_PTX_CRX_P2<18>

DMI_PTX_CRX_P3<18>

DMI_CTX_PRX_N0<18>

DMI_CTX_PRX_N1<18>

DMI_CTX_PRX_N2<18>

DMI_CTX_PRX_N3<18>

DMI_CTX_PRX_P0<18>

DMI_CTX_PRX_P1<18>

DMI_CTX_PRX_P2<18>

DMI_CTX_PRX_P3<18>

FDI_CTX_PRX_N0<18>

FDI_CTX_PRX_N1<18>

FDI_CTX_PRX_N2<18>

FDI_CTX_PRX_N3<18>

FDI_CTX_PRX_N4<18>

FDI_CTX_PRX_N5<18>

FDI_CTX_PRX_N6<18>

FDI_CTX_PRX_N7<18>

FDI_CTX_PRX_P0<18>

FDI_CTX_PRX_P1<18>

FDI_CTX_PRX_P2<18>

FDI_CTX_PRX_P3<18>

FDI_CTX_PRX_P4<18>

FDI_CTX_PRX_P5<18>

FDI_CTX_PRX_P6<18>

FDI_CTX_PRX_P7<18>

FDI_FSYNC0<18>

FDI_FSYNC1<18>

FDI_INT<18>

FDI_LSYNC0<18>

FDI_LSYNC1<18>

1

RC2 24.9_0402_1%

H_EDP_AUXN<13>

H_EDP_AUXP<13>

H_EDP_TXN0<13>

H_EDP_TXN1<13>

H_EDP_TXP0<13>

H_EDP_TXP1<13>

RC10

1K_0402_5%

2N7002_SOT23-3

QC1

IEDP@

2

EDP_COMP

H_EDP_HPD#

M2

DMI_RX#[0]

P6

DMI_RX#[1]

P1

DMI_RX#[2]

P10

DMI_RX#[3]

N3

DMI_RX[0]

P7

DMI_RX[1]

P3

DMI_RX[2]

P11

DMI_RX[3]

K1

DMI_TX#[0]

M8

DMI_TX#[1]

N4

DMI_TX#[2]

R2

DMI_TX#[3]

K3

DMI_TX[0]

M7

DMI_TX[1]

P4

DMI_TX[2]

T3

DMI_TX[3]

U7

FDI0_TX#[0]

W11

FDI0_TX#[1]

W1

FDI0_TX#[2]

AA6

FDI0_TX#[3]

W6

FDI1_TX#[0]

V4

FDI1_TX#[1]

Y2

FDI1_TX#[2]

AC9

FDI1_TX#[3]

U6

FDI0_TX[0]

W10

FDI0_TX[1]

W3

FDI0_TX[2]

AA7

FDI0_TX[3]

W7

FDI1_TX[0]

T4

FDI1_TX[1]

AA3

FDI1_TX[2]

AC8

FDI1_TX[3]

AA11

FDI0_FSYNC

AC12

FDI1_FSYNC

U11

FDI_INT

AA10

FDI0_LSYNC

AG8

FDI1_LSYNC

AF3

eDP_COM PIO

AD2

eDP_ICO MPO

AG11

eDP_HP D#

AG4

eDP_AU X#

AF4

eDP_AU X

AC3

eDP_TX #[0]

AC4

eDP_TX #[1]

AE11

eDP_TX #[2]

AE7

eDP_TX #[3]

AC1

eDP_TX [0]

AA4

eDP_TX [1]

AE10

eDP_TX [2]

AE6

eDP_TX [3]

IVY-BRIDGE_BGA1 023

CPUR1@

DMI Intel(R) FDI

eDP

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0]

PEG_RX#[1]

PEG_RX#[2]

PEG_RX#[3]

PEG_RX#[4]

PEG_RX#[5]

PEG_RX#[6]

PEG_RX#[7]

PEG_RX#[8]

PEG_RX#[9]

PEG_RX#[10]

PEG_RX#[11]

PEG_RX#[12]

PEG_RX#[13]

PEG_RX#[14]

PEG_RX#[15]

PEG_RX[0]

PEG_RX[1]

PEG_RX[2]

PEG_RX[3]

PEG_RX[4]

PEG_RX[5]

PEG_RX[6]

PEG_RX[7]

PEG_RX[8]

PEG_RX[9]

PEG_RX[10]

PEG_RX[11]

PEG_RX[12]

PEG_RX[13]

PEG_RX[14]

PEG_RX[15]

PEG_TX#[0]

PEG_TX#[1]

PEG_TX#[2]

PEG_TX#[3]

PEG_TX#[4]

PEG_TX#[5]

PEG_TX#[6]

PEG_TX#[7]

PEG_TX#[8]

PEG_TX#[9]

PEG_TX#[10]

PEG_TX#[11]

PEG_TX#[12]

PEG_TX#[13]

PEG_TX#[14]

PCI EXPRESS -- GRAPHICS

PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]

PEG_TX[10]

PEG_TX[11]

PEG_TX[12]

PEG_TX[13]

PEG_TX[14]

PEG_TX[15]

PEG_COMP

G3

G1

G4

H22

J21

B22

D21

A19

D17

B14

D13

A11

B10

G8

A8

B6

H8

E5

K7

K22

K19

C21

D19

C19

D16

C13

D12

C11

C9

F8

C8

C5

H6

F6

K6

G22

C23

D23

F21

H19

C17

K15

F17

F14

A15

J14

H13

M10

F10

D9

J4

F22

A23

D24

E21

G19

B18

K17

G17

E14

C15

K13

G13

K10

G10

D8

K4

24.9_0402_1%

PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical

1

impedance = 43 m ohm (4 mils) PEG_ICOMPO signals should be routed with max length = 500 mils

2

- typical impedance = 14.5 m ohm (12 mils)

1

2

3

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Ivy Bridge_DMI/PEG/FDI

LAB412P

E

641Wednesday, January 22, 2014

0.2

of

A

DDR_A_D[0..63]<11>

UC1C

DDR_A_D0

DDR_A_D1

DDR_A_D2

DDR_A_D3

DDR_A_D4

DDR_A_D5

DDR_A_D6

1

2

DDR_A_BS0<11>

DDR_A_BS1<11>

3

DDR_A_BS2<11>

DDR_A_CAS#<11>

DDR_A_RAS#<11>

DDR_A_WE#<11>

DDR_A_D7

DDR_A_D8

DDR_A_D9

DDR_A_D10

DDR_A_D11

DDR_A_D12

DDR_A_D13

DDR_A_D14

DDR_A_D15

DDR_A_D16

DDR_A_D17

DDR_A_D18

DDR_A_D19

DDR_A_D20

DDR_A_D21

DDR_A_D22

DDR_A_D23

DDR_A_D24

DDR_A_D25

DDR_A_D26

DDR_A_D27

DDR_A_D28

DDR_A_D29

DDR_A_D30

DDR_A_D31

DDR_A_D32

DDR_A_D33

DDR_A_D34

DDR_A_D35

DDR_A_D36

DDR_A_D37

DDR_A_D38

DDR_A_D39

DDR_A_D40

DDR_A_D41

DDR_A_D42

DDR_A_D43

DDR_A_D44

DDR_A_D45

DDR_A_D46

DDR_A_D47

DDR_A_D48

DDR_A_D49

DDR_A_D50

DDR_A_D51

DDR_A_D52

DDR_A_D53

DDR_A_D54

DDR_A_D55

DDR_A_D56

DDR_A_D57

DDR_A_D58

DDR_A_D59

DDR_A_D60

DDR_A_D61

DDR_A_D62

DDR_A_D63

DDR_A_BS0

DDR_A_BS1

DDR_A_BS2

DDR_A_CAS#

DDR_A_RAS#

DDR_A_WE#

AG6

SA_DQ[0]

AJ6

SA_DQ[1]

AP11

SA_DQ[2]

AL6

SA_DQ[3]

AJ10

SA_DQ[4]

AJ8

SA_DQ[5]

AL8

SA_DQ[6]

AL7

SA_DQ[7]

AR11

SA_DQ[8]

AP6

SA_DQ[9]

AU6

SA_DQ[10]

AV9

SA_DQ[11]

AR6

SA_DQ[12]

AP8

SA_DQ[13]

AT13

SA_DQ[14]

AU13

SA_DQ[15]

BC7

SA_DQ[16]

BB7

SA_DQ[17]

BA13

SA_DQ[18]

BB11

SA_DQ[19]

BA7

SA_DQ[20]

BA9

SA_DQ[21]

BB9

SA_DQ[22]

AY13

SA_DQ[23]

AV14

SA_DQ[24]

AR14

SA_DQ[25]

AY17

SA_DQ[26]

AR19

SA_DQ[27]

BA14

SA_DQ[28]

AU14

SA_DQ[29]

BB14

SA_DQ[30]

BB17

SA_DQ[31]

BA45

SA_DQ[32]

AR43

SA_DQ[33]

AW48

SA_DQ[34]

BC48

SA_DQ[35]

BC45

SA_DQ[36]

AR45

SA_DQ[37]

AT48

SA_DQ[38]

AY48

SA_DQ[39]

BA49

SA_DQ[40]

AV49

SA_DQ[41]

BB51

SA_DQ[42]

AY53

SA_DQ[43]

BB49

SA_DQ[44]

AU49

SA_DQ[45]

BA53

SA_DQ[46]

BB55

SA_DQ[47]

BA55

SA_DQ[48]

AV56

SA_DQ[49]

AP50

SA_DQ[50]

AP53

SA_DQ[51]

AV54

SA_DQ[52]

AT54

SA_DQ[53]

AP56

SA_DQ[54]

AP52

SA_DQ[55]

AN57

SA_DQ[56]

AN53

SA_DQ[57]

AG56

SA_DQ[58]

AG53

SA_DQ[59]

AN55

SA_DQ[60]

AN52

SA_DQ[61]

AG55

SA_DQ[62]

AK56

SA_DQ[63]

BD37

SA_BS[0]

BF36

SA_BS[1]

BA28

SA_BS[2]

BE39

SA_CAS#

BD39

SA_RAS#

AT41

SA_WE#

IVY-BRIDGE_BGA1 023

CPUR1@

DDR SYSTEM MEMORY A

B

SA_CK[0]

SA_CK#[0]

SA_CKE[0]

SA_CK[1]

SA_CK#[1]

SA_CKE[1]

SA_CS#[0]

SA_CS#[1]

SA_ODT[0]

SA_ODT[1]

SA_DQS#[0]

SA_DQS#[1]

SA_DQS#[2]

SA_DQS#[3]

SA_DQS#[4]

SA_DQS#[5]

SA_DQS#[6]

SA_DQS#[7]

SA_DQS[0]

SA_DQS[1]

SA_DQS[2]

SA_DQS[3]

SA_DQS[4]

SA_DQS[5]

SA_DQS[6]

SA_DQS[7]

SA_MA[0]

SA_MA[1]

SA_MA[2]

SA_MA[3]

SA_MA[4]

SA_MA[5]

SA_MA[6]

SA_MA[7]

SA_MA[8]

SA_MA[9]

SA_MA[10]

SA_MA[11]

SA_MA[12]

SA_MA[13]

SA_MA[14]

SA_MA[15]

DDRA_CLK0

AU36

DDRA_CLK0#

AV36

AY26

DDRA_CLK1

AT40

DDRA_CLK1#

AU40

DDRA_CKE1

BB26

DDRA_SCS0#

BB40

DDRA_SCS1#

BC41

DDRA_ODT0

AY40

DDRA_ODT1

BA41

DDR_A_DQS#0

AL11

DDR_A_DQS#1

AR8

DDR_A_DQS#2

AV11

DDR_A_DQS#3

AT17

DDR_A_DQS#4

AV45

DDR_A_DQS#5

AY51

DDR_A_DQS#6

AT55

DDR_A_DQS#7

AK55

DDR_A_DQS0

AJ11

DDR_A_DQS1

AR10

DDR_A_DQS2

AY11

DDR_A_DQS3

AU17

DDR_A_DQS4

AW45

DDR_A_DQS5

AV51

DDR_A_DQS6

AT56

DDR_A_DQS7

AK54

BG35

BB34

BE35

BD35

AT34

AU34

BB32

AT32

AY32

AV32

BE37

BA30

BC30

AW41

DDR_A_MA14

DDR_A_MA15

AY28

AU26

DDRA_CKE0

DDR_A_MA0

DDR_A_MA1

DDR_A_MA2

DDR_A_MA3

DDR_A_MA4

DDR_A_MA5

DDR_A_MA6

DDR_A_MA7

DDR_A_MA8

DDR_A_MA9

DDR_A_MA10

DDR_A_MA11

DDR_A_MA12

DDR_A_MA13

DDR_B_D[0..63]<12>

DDRA_CLK0 <11>

DDRA_CLK0# <11>

DDRA_CKE0 <11>

DDRA_CLK1 <11>

DDRA_CLK1# <11>

DDRA_CKE1 <11>

DDRA_SCS0# <11>

DDRA_SCS1# <11>

DDRA_ODT0 <11>

DDRA_ODT1 <11>

DDR_A_DQS#[0..7] <11>

DDR_A_DQS[0..7] <11>

DDR_A_MA[0..15] <11>

C

UC1D

DDR_B_D0

DDR_B_D1

DDR_B_D2

DDR_B_D3

DDR_B_D4

DDR_B_D5

DDR_B_D6

DDR_B_D7

DDR_B_D8

DDR_B_D9

DDR_B_D10

DDR_B_D11

DDR_B_D12

DDR_B_D13

DDR_B_D14

DDR_B_D15

DDR_B_D16

DDR_B_D17

DDR_B_D18

DDR_B_D19

DDR_B_D20

DDR_B_D21

DDR_B_D22

DDR_B_D23

DDR_B_D24

DDR_B_D25

DDR_B_D26

DDR_B_D27

DDR_B_D28

DDR_B_D29

DDR_B_D30

DDR_B_D31

DDR_B_D32

DDR_B_D33

DDR_B_D34

DDR_B_D35

DDR_B_D36

DDR_B_D37

DDR_B_D38

DDR_B_D39

DDR_B_D40

DDR_B_D41

DDR_B_D42

DDR_B_D43

DDR_B_D44

DDR_B_D45

DDR_B_D46

DDR_B_D47

DDR_B_D48

DDR_B_D49

DDR_B_D50

DDR_B_D51

DDR_B_D52

DDR_B_D53

DDR_B_D54

DDR_B_D55

DDR_B_D56

DDR_B_D57

DDR_B_D58

DDR_B_D59

DDR_B_D60

DDR_B_D61

DDR_B_D62

DDR_B_D63

DDR_B_BS0<12>

DDR_B_BS1<12>

DDR_B_BS2<12>

DDR_B_CAS#<12>

DDR_B_RAS#<12>

DDR_B_WE#<12>

DDR_B_BS0

DDR_B_BS1

DDR_B_BS2

DDR_B_CAS#

DDR_B_RAS#

DDR_B_WE#

AL4

SB_DQ[0]

AL1

SB_DQ[1]

AN3

SB_DQ[2]

AR4

SB_DQ[3]

AK4

SB_DQ[4]

AK3

SB_DQ[5]

AN4

SB_DQ[6]

AR1

SB_DQ[7]

AU4

SB_DQ[8]

AT2

SB_DQ[9]

AV4

SB_DQ[10]

BA4

SB_DQ[11]

AU3

SB_DQ[12]

AR3

SB_DQ[13]

AY2

SB_DQ[14]

BA3

SB_DQ[15]

BE9

SB_DQ[16]

BD9

SB_DQ[17]

BD13

SB_DQ[18]

BF12

SB_DQ[19]

BF8

SB_DQ[20]

BD10

SB_DQ[21]

BD14

SB_DQ[22]

BE13

SB_DQ[23]

BF16

SB_DQ[24]

BE17

SB_DQ[25]

BE18

SB_DQ[26]

BE21

SB_DQ[27]

BE14

SB_DQ[28]

BG14

SB_DQ[29]

BG18

SB_DQ[30]

BF19

SB_DQ[31]

BD50

SB_DQ[32]

BF48

SB_DQ[33]

BD53

SB_DQ[34]

BF52

SB_DQ[35]

BD49

SB_DQ[36]

BE49

SB_DQ[37]

BD54

SB_DQ[38]

BE53

SB_DQ[39]

BF56

SB_DQ[40]

BE57

SB_DQ[41]

BC59

SB_DQ[42]

AY60

SB_DQ[43]

BE54

SB_DQ[44]

BG54

SB_DQ[45]

BA58

SB_DQ[46]

AW59

SB_DQ[47]

AW58

SB_DQ[48]

AU58

SB_DQ[49]

AN61

SB_DQ[50]

AN59

SB_DQ[51]

AU59

SB_DQ[52]

AU61

SB_DQ[53]

AN58

SB_DQ[54]

AR58

SB_DQ[55]

AK58

SB_DQ[56]

AL58

SB_DQ[57]

AG58

SB_DQ[58]

AG59

SB_DQ[59]

AM60

SB_DQ[60]

AL59

SB_DQ[61]

AF61

SB_DQ[62]

AH60

SB_DQ[63]

BG39

SB_BS[0]

BD42

SB_BS[1]

AT22

SB_BS[2]

AV43

SB_CAS#

BF40

SB_RAS#

BD45

SB_WE#

IVY-BRIDGE_BGA1 023

CPUR1@

D

DDRB_CLK0

BA34

SB_CK[0]

SB_CK#[0]

SB_CKE[0]

SB_CK[1]

SB_CK#[1]

SB_CKE[1]

SB_CS#[0]

SB_CS#[1]

SB_ODT[0]

SB_ODT[1]

SB_DQS#[0]

SB_DQS#[1]

SB_DQS#[2]

SB_DQS#[3]

SB_DQS#[4]

SB_DQS#[5]

SB_DQS#[6]

SB_DQS#[7]

SB_DQS[0]

SB_DQS[1]

SB_DQS[2]

SB_DQS[3]

SB_DQS[4]

SB_DQS[5]

SB_DQS[6]

SB_DQS[7]

DDR SYSTEM MEMORY B

SB_MA[0]

SB_MA[1]

SB_MA[2]

SB_MA[3]

SB_MA[4]

SB_MA[5]

SB_MA[6]

SB_MA[7]

SB_MA[8]

SB_MA[9]

SB_MA[10]

SB_MA[11]

SB_MA[12]

SB_MA[13]

SB_MA[14]

SB_MA[15]

DDRB_CLK0#

AY34

DDRB_CKE0

AR22

DDRB_CLK1

BA36

DDRB_CLK1#

BB36

DDRB_CKE1

BF27

DDRB_SCS0#

BE41

DDRB_SCS1#

BE47

DDRB_ODT0

AT43

DDRB_ODT1

BG47

DDR_B_DQS#0

AL3

DDR_B_DQS#1

AV3

DDR_B_DQS#2

BG11

DDR_B_DQS#3

BD17

DDR_B_DQS#4

BG51

DDR_B_DQS#5

BA59

DDR_B_DQS#6

AT60

DDR_B_DQS#7

AK59

DDR_B_DQS0

AM2

DDR_B_DQS1

AV1

DDR_B_DQS2

BE11

DDR_B_DQS3

BD18

DDR_B_DQS4

BE51

DDR_B_DQS5

BA61

DDR_B_DQS6

AR59

DDR_B_DQS7

AK61

DDR_B_MA0

DDR_B_MA1

BF32

DDR_B_MA2

BE33

DDR_B_MA3

BD33

DDR_B_MA4

AU30

DDR_B_MA5

BD30

DDR_B_MA6

AV30

DDR_B_MA7

BG30

DDR_B_MA8

BD29

DDR_B_MA9

BE30

DDR_B_MA10

BE28

DDR_B_MA11

BD43

DDR_B_MA12

AT28

DDR_B_MA13

AV28

DDR_B_MA14

BD46

DDR_B_MA15

AT26

AU22

DDRB_CLK0 <12>

DDRB_CLK0# <12>

DDRB_CKE0 <12>

DDRB_CLK1 <12>

DDRB_CLK1# <12>

DDRB_CKE1 <12>

DDRB_SCS0# <12>

DDRB_SCS1# <12>

DDRB_ODT0 <12>

DDRB_ODT1 <12>

DDR_B_DQS#[0..7] <12>

DDR_B_DQS[0..7] <12>

DDR_B_MA[0..15] <12>

E

1

2

3

+1.35V

1

RC76

1K_0402_5%

D

S

D

S

1

3

G

2

1

CC37

0.047U_0402_25V7K

2

DDR3_DRAMRST#_R

QC3

BSS138_NL_SOT23-3

1

RC73 0_0402_5%

A

H_DRAMRST#

4.99K_0402_1%

DRAMRST_CNTRL

2

RC78

2

1

H_DRAMRST#<5>

4

DRAMRST_CNTRL_PCH<17,9>

2

RC77

1K_0402_5%

1

2

B

SM_DRAMRST# <11,12>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Ivy Bridge_DDR3

LAB412P

E

741Wednesday, January 22, 2014

of

4

0.2

A

B

C

D

E

+CPU_CORE

1

2

3

4

A

UC1F

A26

VCC[1]

A29

VCC[2]

A31

VCC[3]

A34

VCC[4]

A35

VCC[5]

A38

VCC[6]

A39

VCC[7]

A42

VCC[8]

C26

VCC[9]

C27

VCC[10]

C32

VCC[11]

C34

VCC[12]

C37

VCC[13]

C39

VCC[14]

C42

VCC[15]

D27

VCC[16]

D32

VCC[17]

D34

VCC[18]

D37

VCC[19]

D39

VCC[20]

D42

VCC[21]

E26

VCC[22]

E28

VCC[23]

E32

VCC[24]

E34

VCC[25]

E37

VCC[26]

E38

VCC[27]

F25

VCC[28]

F26

VCC[29]

F28

VCC[30]

F32

VCC[31]

F34

VCC[32]

F37

VCC[33]

F38

VCC[34]

F42

VCC[35]

G42

VCC[36]

H25

VCC[37]

H26

VCC[38]

H28

VCC[39]

H29

VCC[40]

H32

VCC[41]

H34

VCC[42]

H35

VCC[43]

H37

VCC[44]

H38

VCC[45]

H40

VCC[46]

J25

VCC[47]

J26

VCC[48]

J28

VCC[49]

J29

VCC[50]

J32

VCC[51]

J34

VCC[52]

J35

VCC[53]

J37

VCC[54]

J38

VCC[55]

J40

VCC[56]

J42

VCC[57]

K26

VCC[58]

K27

VCC[59]

K29

VCC[60]

K32

VCC[61]

K34

VCC[62]

K35

VCC[63]

K37

VCC[64]

K39

VCC[66]

K42

VCC[67]

L25

VCC[68]

L28

VCC[69]

L33

VCC[70]

L36

VCC[71]

L40

VCC[72]

N26

VCC[73]

N30

VCC[74]

N34

VCC[75]

N38

VCC[76]

IVY-BRIDGE_BGA1 023

CPUR1@

POWER

CORE SUPPLY

8.5A33A

PEG IO AND DDR IO

VCCIO_SEL

RAILS

VIDALERT#

VCC_SENSE

VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID QUIET

B

VCCIO[1]

VCCIO[3]

VCCIO[4]

VCCIO[5]

VCCIO[6]

VCCIO[7]

VCCIO[8]

VCCIO[9]

VCCIO[10]

VCCIO[11]

VCCIO[12]

VCCIO[13]

VCCIO[14]

VCCIO[15]

VCCIO[16]

VCCIO[17]

VCCIO[18]

VCCIO[19]

VCCIO[20]

VCCIO[21]

VCCIO[22]

VCCIO[23]

VCCIO[24]

VCCIO[25]

VCCIO[26]

VCCIO[27]

VCCIO[28]

VCCIO[29]

VCCIO[30]

VCCIO[31]

VCCIO[32]

VCCIO[33]

VCCIO[34]

VCCIO[35]

VCCIO[36]

VCCIO[37]

VCCIO[38]

VCCIO[39]

VCCIO[40]

VCCIO[41]

VCCIO[42]

VCCIO[43]

VCCIO[44]

VCCIO[45]

VCCIO[46]

VCCIO[47]

VCCIO[48]

VCCIO[49]

VCCIO50

VCCIO51

1mA

VCCPQE[1]

VCCPQE[2]

VIDSCLK

VIDSOUT

+1.05VS_VCCP

AF46

AG48

AG50

AG51

AJ17

AJ21

AJ25

AJ43

AJ47

AK50

AK51

AL14

AL15

AL16

AL20

AL22

AL26

AL45

AL48

AM16

AM17

AM21

AM43

AM47

AN20

AN42

AN45

AN48

AA14

AA15

AB17

AB20

AC13

AD16

AD18

AD21

AE14

AE15

AF16

AF18

AF20

AG15

AG16

AG17

AG20

AG21

AJ14

AJ15

+1.05VS_VCCP

W16

W17

BC22

+1.05VS_VCCP

AM25

AN22

H_CPU_SVIDALRT#

A44

B43

C44

F43

G43

AN16

AN17

For DDR

For PEG

1

CC71

1U_0402_6.3V6K

2

1

RC98

10_0402_1%

2

1

RC96

10_0402_1%

Close to CPU

2

+1.05VS_VCCP

1

CC17

2

ESD@

100P_0402_50V8J

1

CC19

CC18

2

ESD@

100P_0402_50V8J

by ESD requestion and place near CPU

+1.05VS_VCCP

1

RC91

130_0402_5%

2

RC90 43_0402_1%

+CPU_CORE

VCCIO_SENSE <38>

+1.05VS_VCCP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

RC90 43_0402_1%

2

RC93

100_0402_1%

1

RC97

100_0402_1%

2

Close to CPU

C

+1.05VS_VCCP

1

RC89

75_0402_5%

1

2013/12/17 2014/12/17

2

VCCSENSE <40>

VSSSENSE <40>

VR_SVID_ALRT# <40>

VR_SVID_CLK <40>

VR_SVID_DAT <40>

Pull high resistor on VR side

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Ivy Bridge_POWER-1

LAB412P

841Wednesday, January 22, 2014

E

841Wednesday, January 22, 2014

of

1

2

3

4

0.2

A

B

C

D

E

1

2

VCC_AXG_SENSE<40>

VSS_AXG_SENSE<40>

3

4

VCCPLL Decoupling: 1X 330U (6m ohm), 1X 10U, 2x1U

1

+VCCSA

CC44

1

@

2

@

10U_0603_6.3V6M

Place TOP IN BGA

CC42

2

1

10U_0603_6.3V6M

47U_0805_6.3V6M

Place BOT OUT BGA

CC77

1

2

1U_0402_6.3V6K

+1.8VS

RC119 0_0805_5%

+VCCSA Decoupling: 2X 47U (MLCC), 3X 10U, 5X 1U

A

CC59

CC41

2

1

CC76

1

2

+GFX_CORE

1

2

10U_0603_6.3V6M

1U_0402_6.3V6K

CC75

1

RC105

100_0402_1%

Close to CPU

2

RC106

1

100_0402_1%

+1.8VS_VCCPLL

CC60

1

2

1U_0402_6.3V6K

CC40

CC43

1

2

@

2

1

10U_0603_6.3V6M

CC74

1

2

1U_0402_6.3V6K

47U_0805_6.3V6M

1U_0402_6.3V6K

+GFX_CORE

2

CC73

1

2

1U_0402_6.3V6K

UC1G

29A

AA46

VAXG[1]

AB47

VAXG[2]

AB50

VAXG[3]

AB51

VAXG[4]

AB52

VAXG[5]

AB53

VAXG[6]

AB55

VAXG[7]

AB56

VAXG[8]

AB58

VAXG[9]

AB59

VAXG[10]

AC61

VAXG[11]

AD47

VAXG[12]

AD48

VAXG[13]

AD50

VAXG[14]

AD51

VAXG[15]

AD52

VAXG[16]

AD53

VAXG[17]

AD55

VAXG[18]

AD56

VAXG[19]

AD58

VAXG[20]

AD59

VAXG[21]

AE46

VAXG[22]

N45

VAXG[23]

P47

VAXG[24]

P48

VAXG[25]

P50

VAXG[26]

P51

VAXG[27]

P52

VAXG[28]

P53

VAXG[29]

P55

VAXG[30]

P56

VAXG[31]

P61

VAXG[32]

T48

VAXG[33]

T58

VAXG[34]

T59

VAXG[35]

T61

VAXG[36]

U46

VAXG[37]

V47

VAXG[38]

V48

VAXG[39]

V50

VAXG[40]

V51

VAXG[41]

V52

VAXG[42]

V53

VAXG[43]

V55

VAXG[44]

V56

VAXG[45]

V58

VAXG[46]

V59

VAXG[47]

W50

VAXG[48]

W51

VAXG[49]

W52

VAXG[50]

W53

VAXG[51]

W55

VAXG[52]

W56

VAXG[53]

W61

VAXG[54]

Y48

VAXG[55]

Y61

VAXG[56]

F45

VAXG_SENSE

G45

VSSAXG_SENSE

1.2A

BB3

VCCPLL[1]

BC1

VCCPLL[2]

BC4

VCCPLL[3]

6A

L17

VCCSA[1]

L21

VCCSA[2]

N16

VCCSA[3]

N20

VCCSA[4]

N22

VCCSA[5]

P17

VCCSA[6]

P20

VCCSA[7]

R16

VCCSA[8]

R18

VCCSA[9]

R21

VCCSA[10]

U15

VCCSA[11]

V16

VCCSA[12]

V17

VCCSA[13]

V18

VCCSA[14]

V21

VCCSA[15]

W20

VCCSA[16]

IVY-BRIDGE_BGA1 023

CPUR1@

POWER

VREF

DDR3 - 1.5V RAILS

GRAPHICS

SENSE

LINES

SENSE

LINES

1.8V RAIL

SA RAIL

VCCSA VID

B

SM_VREF

SA_DIMM_VREFDQ

SB_DIMM_VREFDQ

5A

VDDQ[1]

VDDQ[2]

VDDQ[3]

VDDQ[4]

VDDQ[5]

VDDQ[6]

VDDQ[7]

VDDQ[8]

VDDQ[9]

VDDQ[10]

VDDQ[11]

VDDQ[12]

VDDQ[13]

VDDQ[14]

VDDQ[15]

VDDQ[16]

VDDQ[17]

VDDQ[18]

VDDQ[19]

VDDQ[20]

VDDQ[21]

VDDQ[22]

VDDQ[23]

VDDQ[24]

VDDQ[25]

VDDQ[26]

1mA

VCCDQ[1]

VCCDQ[2]

QUIET RAILS

VDDQ_SENSE

VSS_SENSE_VDDQ

SENSE LINES

VCCSA_SENSE

VCCSA_VID[0]

VCCSA_VID[1]

lines

+V_SM_VREF should have 20 mil trace width

AY43

BE7

BG7

AJ28

AJ33

AJ36

AJ40

AL30

AL34

AL38

AL42

AM33

AM36

AM40

AN30

AN34

AN38

AR26

AR28

AR30

AR32

AR34

AR36

AR40

AV41

AW26

BA40

BB28

BG33

AM28

AN26

BC43

BA43

U10

D48

D49

+V_SM_VREF

+VREF_DQA_M3

+VREF_DQB_M3

+1.35V_CPU

1

CC72

1U_0402_6.3V6K

2

H_VCCSA_VID0

H_VCCSA_VID1

Power IC intergrate PD

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

Place TOP IN BGA

CC57

CC51

2

1

10U_0603_6.3V6M

CC81

CC82

1

2

1U_0402_6.3V6K

H_VCCSA_VID0 <38>

H_VCCSA_VID1 <38>

C

+1.35V_CPU

RC120 1K_0402_0.5%

1

2

1

CC65

RC109 1K_0402_0.5%

1

2

0.1U_0402_10V7K

CC52

CC55

2

1

10U_0603_6.3V6M

2

+1.35V_CPU

CC56

CC54

2

1

10U_0603_6.3V6M

CC50

CC53

1

@

2

10U_0603_6.3V6M

47U_0805_6.3V6M

Place BOT OUT BGA

CC80

CC79

1

2

1U_0402_6.3V6K

CC78

1

2

1U_0402_6.3V6K

VCCSA_VID0

0

1

CC87

1

2

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

VCCSA_VID1

CC85

1

2

0

1

0

1U_0402_6.3V6K

CC86

CC87

11

2

RC203

470_0805_5%

1

3

QC5B

SUSP

2N7002DW-T/R7_SOT363-6

2013/12/17 2014/12/17

5

4

Compal Secret Data

Deciphered Date

Intel DDR Vref M3

BSS138_NL_SOT23-3

S

+VREF_DQA_M3

+VREF_DQB_M3

+1.35V_CPU Decoupling: 2X 47U(MLCC), 6X 10U, 8X 1U

+VCCSA

0.90 V

0.80 V

0.725 V

0.675 V

Id=23A,Rdson=5mohm@10V

+1.35V_CPU

QC4 AO4354_SOIC-8

1

2

D

3

CC69

0.1U_0402_25V6

1

CC68

10U_0603_6.3V6M@

2

3

G

2

3

S

BSS138_NL_SOT23-3

For Sandy Bridge

8

7

6

5

4

RUN_ON_CPU1.5VS3

1

RC205

820K_0402_5%

2

Title

Size Document Number Rev

Custom

Date: Sheet

QC7

D

1

2

1

D

QC8

+1.35V_CPU

+1.35V

RC204

1

220K_0402_5%

6

QC5A

SUSP

2

2N7002DW-T/R7_SOT363-6

1

Compal Electronics, Inc.

Ivy Bridge_POWER-2

LAB412P

+VREF_DQA

DRAMRST_CNTRL_PCH <17,7>

+VREF_DQB

1

2

CC46 0.1U_0402_10V7K@

1

2

CC47 0.1U_0402_10V7K@

1

2

CC48 0.1U_0402_10V7K@

1

2

CC45 0.1U_0402_10V7K@

B+

2

SUSP <32>

E

1

2

3

+1.35V

4

0.2

of

941Wednesday, January 22, 2014

of

941Wednesday, January 22, 2014

of

941Wednesday, January 22, 2014

UC1H

www.vinaﬁx.com

UC1H

A13

VSS[1]

A17

VSS[2]

A21

VSS[3]

A25

VSS[4]

A28

VSS[5]

A33

VSS[6]

A37

VSS[7]

A40

VSS[8]

A45

VSS[9]

A49

1

2

3

4

VSS[10]

A53

VSS[11]

A9

VSS[12]

AA1

VSS[13]

AA13

VSS[14]

AA50

VSS[15]

AA51

VSS[16]

AA52

VSS[17]

AA53

VSS[18]

AA55

VSS[19]

AA56

VSS[20]

AA8

VSS[21]

AB16

VSS[22]

AB18

VSS[23]

AB21

VSS[24]

AB48

VSS[25]

AB61

VSS[26]

AC10

VSS[27]

AC14

VSS[28]

AC46

VSS[29]

AC6

VSS[30]

AD17

VSS[31]

AD20

VSS[32]

AD4

VSS[33]

AD61

VSS[34]

AE13

VSS[35]

AE8

VSS[36]

AF1

VSS[37]

AF17

VSS[38]

AF21

VSS[39]

AF47

VSS[40]

AF48

VSS[41]

AF50

VSS[42]

AF51

VSS[43]

AF52

VSS[44]

AF53

VSS[45]

AF55

VSS[46]

AF56

VSS[47]

AF58

VSS[48]

AF59

VSS[49]

AG10

VSS[50]

AG14

VSS[51]

AG18

VSS[52]

AG47

VSS[53]

AG52

VSS[54]

AG61

VSS[55]

AG7

VSS[56]

AH4

VSS[57]

AH58

VSS[58]

AJ13

VSS[59]

AJ16

VSS[60]

AJ20

VSS[61]

AJ22

VSS[62]

AJ26

VSS[63]

AJ30

VSS[64]

AJ34

VSS[65]

AJ38

VSS[66]

AJ42

VSS[67]

AJ45

VSS[68]

AJ48

VSS[69]

AJ7

VSS[70]

AK1

VSS[71]

AK52

VSS[72]

AL10

VSS[73]

AL13

VSS[74]

AL17

VSS[75]

AL21

VSS[76]

AL25

VSS[77]

AL28

VSS[78]

AL33

VSS[79]

AL36

VSS[80]

AL40

VSS[81]

AL43

VSS[82]

AL47

VSS[83]

AL61

VSS[84]

AM13

VSS[85]

AM20

VSS[86]

AM22

VSS[87]

AM26

VSS[88]

AM30

VSS[89]

AM34

VSS[90]

IVY-BRIDGE_BGA1 023

CPUR1@

A

VSS

VSS[91]

VSS[92]

VSS[93]

VSS[94]

VSS[95]

VSS[96]

VSS[97]

VSS[98]

VSS[99]

VSS[100]

VSS[101]

VSS[102]

VSS[103]

VSS[104]

VSS[105]

VSS[106]

VSS[107]

VSS[108]

VSS[109]

VSS[110]

VSS[111]

VSS[112]

VSS[113]

VSS[114]

VSS[115]

VSS[116]

VSS[117]

VSS[118]

VSS[119]

VSS[120]

VSS[121]

VSS[122]

VSS[123]

VSS[124]

VSS[125]

VSS[126]

VSS[127]

VSS[128]

VSS[129]

VSS[130]

VSS[131]

VSS[132]

VSS[133]

VSS[134]

VSS[135]

VSS[136]

VSS[137]

VSS[138]

VSS[139]

VSS[140]

VSS[141]

VSS[142]

VSS[143]

VSS[144]

VSS[145]

VSS[146]

VSS[147]

VSS[148]

VSS[149]

VSS[150]

VSS[151]

VSS[152]

VSS[153]

VSS[154]

VSS[155]

VSS[156]

VSS[157]

VSS[158]

VSS[159]

VSS[160]

VSS[161]

VSS[162]

VSS[163]

VSS[164]

VSS[165]

VSS[166]

VSS[167]

VSS[168]

VSS[169]

VSS[170]

VSS[171]

VSS[172]

VSS[173]

VSS[174]

VSS[175]

VSS[176]

VSS[177]

VSS[178]

VSS[179]

VSS[180]

AM38

AM4

AM42

AM45

AM48

AM58

AN1

AN21

AN25

AN28

AN33

AN36

AN40

AN43

AN47

AN50

AN54

AP10

AP51

AP55

AP7

AR13

AR17

AR21

AR41

AR48

AR61

AR7

AT14

AT19

AT36

AT4

AT45

AT52

AT58

AU1

AU11

AU28

AU32

AU51

AU7

AV17

AV21

AV22

AV34

AV40

AV48

AV55

AW13

AW43

AW61

AW7

AY14

AY19

AY30

AY36

AY4

AY41

AY45

AY49

AY55

AY58

AY9

BA1

BA11

BA17

BA21

BA26

BA32

BA48

BA51

BB53

BC13

BC5

BC57

BD12

BD16

BD19

BD23

BD27

BD32

BD36

BD40

BD44

BD48

BD52

BD56

BD8

BE5

BG13

BG17

BG21

BG24

BG28

BG37

BG41

BG45

BG49

BG53

BG9

C29

C35

C40

D10

D14

D18

D22

D26

D29

D35

D4

D40

D43

D46

D50

D54

D58

D6

E25

E29

E3

E35

E40

F13

F15

F19

F29

F35

F40

F55

G51

G6

G61

H10

H14

H17

H21

H4

H53

H58

J1

J49

J55

K11

K21

K51

K8

L16

L20

L22

L26

L30

L34

L38

L43

L48

L61

M11

M15

B

UC1I

VSS[181]

VSS[182]

VSS[183]

VSS[184]

VSS[185]

VSS[186]

VSS[187]

VSS[188]

VSS[189]

VSS[190]

VSS[191]

VSS[192]

VSS[193]

VSS[194]

VSS[195]

VSS[196]

VSS[197]

VSS[198]

VSS[199]

VSS[200]

VSS[201]

VSS[202]

VSS[203]

VSS[204]

VSS[205]

VSS[206]

VSS[207]

VSS[208]

VSS[209]

VSS[210]

VSS[211]

VSS[212]

VSS[213]

VSS[214]

VSS[215]

VSS[216]

VSS[217]

VSS[218]

VSS[219]

VSS[220]

VSS[221]

VSS[222]

VSS[223]

VSS[224]

VSS[225]

VSS[226]

VSS[227]

VSS[228]

VSS[229]

VSS[230]

VSS[231]

VSS[232]

VSS[233]

VSS[234]

VSS[235]

VSS[236]

VSS[237]

VSS[238]

VSS[239]

VSS[240]

VSS[241]

VSS[242]

VSS[243]

VSS[244]

VSS[245]

VSS[246]

VSS[247]

VSS[248]

VSS[249]

IVY-BRIDGE_BGA1 023

CPUR1@

VSS

VSS[250]

VSS[251]

VSS[252]

VSS[253]

VSS[254]

VSS[255]

VSS[256]

VSS[257]

VSS[258]

VSS[259]

VSS[260]

VSS[261]

VSS[262]

VSS[263]

VSS[264]

VSS[265]

VSS[266]

VSS[267]

VSS[268]

VSS[269]

VSS[270]

VSS[271]

VSS[272]

VSS[273]

VSS[274]

VSS[275]

VSS[276]

VSS[277]

VSS[278]

VSS[279]

VSS[280]

VSS[281]

VSS[282]

VSS[283]

VSS[284]

VSS[285]

VSS[286]

VSS[287]

VSS[288]

VSS[289]

VSS[290]

VSS[291]

VSS[292]

VSS[293]

VSS[294]

VSS[295]

VSS[296]

VSS[297]

VSS[298]

VSS[299]

VSS[300]

VSS[301]

VSS_NCTF_1

VSS_NCTF_2

VSS_NCTF_3

VSS_NCTF_4

VSS_NCTF_5

VSS_NCTF_6

VSS_NCTF_7

VSS_NCTF_8

VSS_NCTF_9

VSS_NCTF_10

VSS_NCTF_11

NCTF

VSS_NCTF_12

VSS_NCTF_13

VSS_NCTF_14

M4

M58

M6

N1

N17

N21

N25

N28

N33

N36

N40

N43

N47

N48

N51

N52

N56

N61

P14

P16

P18

P21

P58

P59

P9

R17

R20

R4

R46

T1

T47

T50

T51

T52

T53

T55

T56

U13

U8

V20

V61

W13

W15

W18

W21

W46

W8

Y4

Y47

Y58

Y59

G48

A5

A57

BC61

BD3

BD59

BE4

BE58

BG5

BG57

C3

C58

D59

E1

E61

C

UC1E

CFG0

B50

CFG[0]

T87PAD@

CFG2

CFG4

CFG5

CFG6

CFG7

C51

CFG[1]

B54

CFG[2]

D53

CFG[3]

A51

CFG[4]

C53

CFG[5]

C55

CFG[6]

H49

CFG[7]

A55

CFG[8]

H51

CFG[9]

K49

CFG[10]

K53

CFG[11]

F53

CFG[12]

G53

CFG[13]

L51

CFG[14]

F51

CFG[15]

D52

CFG[16]

L53

CFG[17]

H43

VCC_VAL_SENSE

K43

VSS_VAL_SENSE

H45

VAXG_VAL_SENSE

K45

VSSAXG_VAL_SENSE

F48

VCC_DIE_SENSE

H48

RSVD6

K48

RSVD7

BA19

RSVD8

AV19

RSVD9

AT21

RSVD10

BB21

RSVD11

BB19

RSVD12

AY21

RSVD13

BA22

RSVD14

AY22

RSVD15

AU19

RSVD16

AU21

RSVD17

BD21

RSVD18

BD22

RSVD19

BD25

RSVD20

BD26

RSVD21

BG22

RSVD22

BE22

RSVD23

BG26

RSVD24

BE26

RSVD25

BF23

RSVD26

BE24

RSVD27

IVY-BRIDGE_BGA1 023

CPUR1@

BCLK_ITP#

These pins are for solder joint

RESERVED

reliability and non-critical to function. For BGA only.

DC_TEST_A4

DC_TEST_C4

DC_TEST_D3

DC_TEST_D1

DC_TEST_A58

DC_TEST_A59

DC_TEST_C59

DC_TEST_A61

DC_TEST_C61

DC_TEST_D61

DC_TEST_BD61

DC_TEST_BE61

DC_TEST_BE59

DC_TEST_BG61

DC_TEST_BG59

DC_TEST_BG58

DC_TEST_BG4

DC_TEST_BG3

DC_TEST_BE3

DC_TEST_BG1

DC_TEST_BE1

DC_TEST_BD1

T89 PAD@

BCLK_ITP

RSVD30

RSVD31

RSVD32

RSVD33

RSVD34

RSVD35

RSVD36

RSVD37

RSVD38

RSVD39

RSVD40

RSVD41

RSVD42

RSVD43

RSVD44

RSVD45

D

N59

N58

N42

L42

L45

L47

M13

M14

U14

W14

P13

AT49

K24

AH2

AG13

AM14

AM15

N50

A4

C4

DC_TEST_C4_D3

D3

D1

A58

A59

DC_TEST_A59_C59

C59

A61

DC_TEST_A61_C61

C61

D61

BD61

BE61

DC_TEST_BE61_BE59

BE59

BG61

DC_TEST_BG61_BG59

BG59

BG58

BG4

BG3

DC_TEST_BG3_BE3

BE3

BG1

DC_TEST_BG1_BE1

BE1

BD1

E

CFG Straps for Processor

(CFG[17:0] internal pull high 5~15K to VCCIO)

CFG2

1

RC79

1K_0402_1%

@

2

PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane # definition

*

CFG2

matches socket pin map definition

0:Lane Reversed

CFG4

1

RC82

1K_0402_1%

IEDP@

2

Embedded Display Port Presence Strap

1 : Disabled; No Physical Display Port attached to Embedded Display Port

*

CFG4

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

CFG7

1

RC85

1K_0402_1%

@

2

1

2

PEG DEFER TRAINING

CFG7

*

3

1: (Default) PEG Train immediately following xxRESETB de assertion

0: PEG Wait for BIOS for training

CFG6

CFG5

RC83

1K_0402_1%

@

1

RC84

1

1K_0402_1%

@

2

PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2 disabled

*

CFG[6:5]

10: x8, x8 - Device 1 function 1 enabled; function 2 disabled

01: Reserved - (Device 1 function 1 disabled; function 2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

4

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Ivy Bridge_GND/RSVD/CFG

LAB412P

10 41Wednesday, January 22, 2014

E

10 41Wednesday, January 22, 2014

of

0.2

5

4

3

2

1

+1.35V

JDDR3L

+VREF_DQA

1

CD1

0.1U_0402_10V7K

2

D

Close to JDDRL.1

+3VS

DDRA_CKE0<7>

DDR_A_BS2<7>

DDRA_CLK0<7>

DDRA_CLK0#<7>

DDR_A_BS0<7>

DDR_A_WE#<7>

DDR_A_CAS#<7>

DDRA_SCS1#<7>

0.1U_0402_10V7K

C

B

A

DDR_A_D0

DDR_A_D1

DDR_A_D2

DDR_A_D3

DDR_A_D8

DDR_A_D9

DDR_A_DQS#1

DDR_A_DQS1

DDR_A_D10

DDR_A_D11

DDR_A_D16

DDR_A_D17

DDR_A_DQS#2

DDR_A_DQS2

DDR_A_D18

DDR_A_D19

DDR_A_D24

DDR_A_D25

DDR_A_D26

DDR_A_D27

DDR_A_MA12

DDR_A_MA9

DDR_A_MA8

DDR_A_MA5

DDR_A_MA3

DDR_A_MA1

DDR_A_MA10

DDR_A_MA13

DDR_A_D32

DDR_A_D33

DDR_A_DQS#4

DDR_A_DQS4

DDR_A_D34

DDR_A_D35

DDR_A_D40

DDR_A_D41

DDR_A_D42

DDR_A_D43

DDR_A_D48

DDR_A_D49

DDR_A_DQS#6

DDR_A_DQS6

DDR_A_D50

DDR_A_D51

DDR_A_D56

DDR_A_D57

DDR_A_D58

DDR_A_D59

1

CD26

2

SPD setting (SA0, SA1) PU/PD by Channel A/B

->Channel A 00

->Channel B 01

+0.675VS

5

1

VREF_DQ

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1

29

DQS1

31

VSS11

33

DQ10

35

DQ11

37

VSS13

39

DQ16

41

DQ17

43

VSS15

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25

61

VSS22

63

DM3

65

VSS23

67

DQ26

69

DQ27

71

VSS25

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4406-0102

@

DQS#0

VSS10

RESET#

VSS12

VSS14

VSS16

VSS17

VSS19

VSS21

DQS#3

VSS24

VSS26

VDD10

VDD12

VDD14

VDD16

VDD18

VREF_CA

VSS28

VSS30

VSS31

VSS33

VSS35

DQS#5

VSS38

VSS40

VSS42

VSS43

VSS45

VSS47

DQS#7

VSS50

VSS52

EVENT#

VSS1

DQ4

DQ5

VSS3

DQS0

VSS6

DQ6

DQ7

VSS8

DQ12

DQ13

DM1

DQ14

DQ15

DQ20

DQ21

DM2

DQ22

DQ23

DQ28

DQ29

DQS3

DQ30

DQ31

CKE1

VDD2

VDD4

VDD6

VDD8

CK1#

RAS#

ODT0

ODT1

NC2

DQ36

DQ37

DM4

DQ38

DQ39

DQ44

DQ45

DQS5

DQ46

DQ47

DQ52

DQ53

DM6

DQ54

DQ55

DQ60

DQ61

DQS7

DQ62

DQ63

VTT2

CK1

BA1

SDA

A15

A14

A11

S0#

SCL

+1.35V

2

DDR_A_D4

4

DDR_A_D5

6

8

DDR_A_DQS#0

10

DDR_A_DQS0

12

14

DDR_A_D6

16

DDR_A_D7

18

20

DDR_A_D12

22

DDR_A_D13

24

26

28

30

32

DDR_A_D14

34

DDR_A_D15

36

38

DDR_A_D20

40

DDR_A_D21

42

44

46

48

DDR_A_D22

50

DDR_A_D23

52

54

DDR_A_D28

56

DDR_A_D29

58

60

DDR_A_DQS#3

62

DDR_A_DQS3

64

66

DDR_A_D30

68

DDR_A_D31

70

72

74

76

DDR_A_MA15

78

DDR_A_MA14

80

82

DDR_A_MA11

84

DDR_A_MA7

86

A7

88

DDR_A_MA6

90

A6

A4

A2

A0

G2

DDR_A_MA4

92

94

DDR_A_MA2

96

DDR_A_MA0

98

100

102

104

106

108

110

112

114

116

118

120

122

124

+VREF_CAA

126

128

DDR_A_D36

130

DDR_A_D37

132

134

136

138

DDR_A_D38

140

DDR_A_D39

142

144

DDR_A_D44

146

DDR_A_D45

148

150

DDR_A_DQS#5

152

DDR_A_DQS5

154

DDR_A_D46

156

158

DDR_A_D47

160

DDR_A_D52

162

DDR_A_D53

164

166

168

170

DDR_A_D54

172

DDR_A_D55

174

176

DDR_A_D60

178

DDR_A_D61

180

182

DDR_A_DQS#7

184

DDR_A_DQS7

186

188

DDR_A_D62

190

DDR_A_D63

192

194

196

198

200

202

+0.675VS

204

206

4

DDR3 SO-DIMM A Standard Type

SM_DRAMRST# <12,7>

DDRA_CKE1 <7>

DDRA_CLK1 <7>

DDRA_CLK1# <7>

DDR_A_BS1 <7>

DDR_A_RAS# <7>

DDRA_SCS0# <7>

DDRA_ODT0 <7>

DDRA_ODT1 <7>

1

CD16

0.1U_0402_10V7K

2

close to JDDRL.126

PM_SMBDATA <12,17,31>

PM_SMBCLK <12,17,31>

DDR_A_DQS[0..7] <7>

DDR_A_DQS#[0..7] <7>

DDR_A_D[0..63] <7>

DDR_A_MA[0..15] <7>

+1.35V

1

RD1

1K_0402_1%

+VREF_DQA

+1.35V

1

RD6

1K_0402_1%

2

1

RD7

1K_0402_1%

2

Layout Note: Place near JDDRL

+1.35V

1

2

CD8 10U_0603_6.3V6M

1

2

CD9 10U_0603_6.3V6M

1

2

CD10 10U_0603_6.3V6M

1

2

CD11 10U_0603_6.3V6M

1

2

CD12 10U_0603_6.3V6M

1

2

CD13 10U_0603_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

2

1

RD2

1K_0402_1%

2

Layout Note: Place these 4 Caps near Command and Control si gnals of DIMMA

+1.35V

1

2

CD20 0.1U_0402_10V7K

1

2

CD17 0.1U_0402_10V7K

1

2

CD18 0.1U_0402_10V7K

1

2

CD19 0.1U_0402_10V7K

2

Date: Sheet

Layout Note: Place near JDDRL1.203 and 204

+0.675VS

1

2

CD24 1U_0402_6.3V6K

1

2

CD21 1U_0402_6.3V6K

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Compal Electronics, Inc.

DDRIII-SODIMM0

LAB412P

1

11 41Wednesday, January 22, 2014

of

D

C

B

A

0.2

A

B

C

D

E

VSS

DQ4

DQ5

VSS

DQ6

DQ7

VSS

DM1

VSS

DQ21

VSS

DM2

VSS

DQ22

DQ23

VSS

DQ28

DQ29

VSS

DQS3

VSS

DQ30

DQ31

VSS

CKE1

VDD

CK1#

VDD

RAS#

VDD

ODT0

VDD

ODT1

VDD

VSS

DQ36

DQ37

VSS

DM4

VSS

DQ38

DQ39

VSS

DQ44

DQ45

VSS

DQS5

DQ46

DQ47

DQ52

DQ53

DM6

DQ54

DQ55

DQ60

DQ61

DQS7

DQ62

DQ63

SDA

GND2

A15

A14

A11

CK1

BA1

S0#

VSS

SCL

VTT

+1.35V

2

DDR_B_D4

4

DDR_B_D5

6

8

DDR_B_DQS#0

10

DDR_B_DQS0

12

14

DDR_B_D6

16

DDR_B_D7

18

20

DDR_B_D12

22

DDR_B_D13

24

26

28

30

32

DDR_B_D14

34

DDR_B_D15

36

38

DDR_B_D20

40

DDR_B_D21

42

44

46

48

DDR_B_D22

50

DDR_B_D23

52

54

DDR_B_D28

56

DDR_B_D29

58

60

DDR_B_DQS#3

62

DDR_B_DQS3

64

66

DDR_B_D30

68

DDR_B_D31

70

72

74

76

DDR_B_MA15

78

DDR_B_MA14

80

82

DDR_B_MA11

84

DDR_B_MA7

86

A7

88

DDR_B_MA6

90

A6

A4

A2

A0

NC

DDR_B_MA4

92

94

DDR_B_MA2

96

DDR_B_MA0

98

100

102

104

106

108

110

112

114

116

118

120

122

124

+VREF_CAB

126

128

DDR_B_D36

130

DDR_B_D37

132

134

136

DDR_B_D38

138

140

DDR_B_D39

142

DDR_B_D44

144

DDR_B_D45

146

148

DDR_B_DQS#5

150

DDR_B_DQS5

152

154

DDR_B_D46

156

DDR_B_D47

158

160

DDR_B_D52

162

DDR_B_D53

164

166

168

170

DDR_B_D54

172

DDR_B_D55

174

176

DDR_B_D60

178

DDR_B_D61

180

182

DDR_B_DQS#7

184

DDR_B_DQS7

186

188

DDR_B_D62

190

DDR_B_D63

192

194

196

198

200

202

+0.675VS

204

206

208

B

DDR3 SO-DIMM B Reverse Type

SM_DRAMRST# <11,7>

DDRB_CKE1 <7>

DDRB_CLK1 <7>

DDRB_CLK1# <7>

DDR_B_BS1 <7>

DDR_B_RAS# <7>

DDRB_SCS0# <7>

DDRB_ODT0 <7>

DDRB_ODT1 <7>

CD47

0.1U_0402_10V7K

1

2

Close to JDDRH.126

PM_SMBDATA <11,17,31>

PM_SMBCLK <11,17,31>

DDR_B_DQS#[0..7] <7>

DDR_B_DQS[0..7] <7>

DDR_B_D[0..63] <7>

DDR_B_MA[0..15] <7>

+1.35V

1

RD10

1K_0402_1%

+VREF_DQB

+1.35V

1

RD12

1K_0402_1%

2

1

RD13

1K_0402_1%

2

Layout Note: Place near JDDRH

+1.35V

1

CD31 47U_0805_6.3V6M

1

CD41 10U_0603_6.3V6M

1

CD36 10U_0603_6.3V6M

1

CD37 10U_0603_6.3V6M

1

CD38 10U_0603_6.3V6M

1

CD39 10U_0603_6.3V6M

1

CD40 10U_0603_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

2013/12/17 2014/12/17

2

1

2

Compal Secret Data

RD11

1K_0402_1%

Layout Note: Place these 4 Caps near Command and Control si gnals of DIMMB

+1.35V

1

CD33 0.1U_0402_10V7K

CD29 0.1U_0402_10V7K

CD30 0.1U_0402_10V7K

1

CD32 0.1U_0402_10V7K

Deciphered Date

D

2

1

2

1

2

Date: Sheet

Layout Note: Place near JDDRH.203 and 204

+0.675VS

1

2

CD45 1U_0402_6.3V6K

1

2

CD42 1U_0402_6.3V6K

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Compal Electronics, Inc.

DDRIII-SODIMM1

LAB412P

E

12 41Wednesday, January 22, 2014

of

1

2

3

4

0.2

+1.35V

JDDR3H

+VREF_DQB

1

Close to JDDRH.1

+3VS

DDRB_CKE0<7>

DDR_B_BS2<7>

DDRB_CLK0<7>

DDRB_CLK0#<7>

DDR_B_BS0<7>

DDR_B_WE#<7>

DDR_B_CAS#<7>

DDRB_SCS1#<7>

1

CD49

2

0.1U_0402_10V7K

2

3

4

DDR_B_D0

DDR_B_D1

CD27

1

DDR_B_D2

DDR_B_D3

0.1U_0402_10V7K

DDR_B_D8

2

DDR_B_D9

DDR_B_DQS#1

DDR_B_DQS1

DDR_B_D10

DDR_B_D11

DDR_B_D16

DDR_B_D17

DDR_B_DQS#2

DDR_B_DQS2

DDR_B_D18

DDR_B_D19

DDR_B_D24

DDR_B_D25

DDR_B_D26

DDR_B_D27

DDR_B_MA12

DDR_B_MA9

DDR_B_MA8

DDR_B_MA5

DDR_B_MA3

DDR_B_MA1

DDR_B_MA10

DDR_B_MA13

DDR_B_D32

DDR_B_D33

DDR_B_DQS#4

DDR_B_DQS4

DDR_B_D34

DDR_B_D35

DDR_B_D40

DDR_B_D41

DDR_B_D42

DDR_B_D43

DDR_B_D48

DDR_B_D49

DDR_B_DQS#6

DDR_B_DQS6

DDR_B_D50

DDR_B_D51

DDR_B_D56

DDR_B_D57

DDR_B_D58

DDR_B_D59

1

2

RD15 10K_0402_5%

SPD setting (SA0, SA1) PU/PD by Channel A/B

->Channel A 00

->Channel B 01

A

+0.675VS

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

LCN_DAN06-K4406-0103

@

DQS0#

DQS0

DQ12

DQ13

RESET#

DQ14

DQ15

DQ20

DQS3#

VREF_CA

DQS5#

DQS7#

EVENT#

BOSS2

For eDP Panel

H_EDP_AUXP<6>

H_EDP_AUXN<6>

1

H_EDP_TXP0<6>

H_EDP_TXN0<6>

H_EDP_TXP1<6>

H_EDP_TXN1<6>

For LVDS 1ch Panel

LCD_TXOUT0+<19>

LCD_TXOUT0-<19>

LCD_TXOUT1+<19>

LCD_TXOUT1-<19>

LCD_TXOUT2+<19>

LCD_TXOUT2-<19>

LCD_TXCLK+<19>

2

3

BKOFF#_R

4

LCD_TXCLK-<19>

LCD_EDID_CLK<19>

LCD_EDID_DATA<19>

Reserve for eDP panel potential issue

IEDP@

R7 0_0402_5%

1

RB751V-40 SOD-323

1

R8

10K_0402_5%

2

A

C890 0.1U_0402_10V7K

C891 0.1U_0402_10V7K

C912 0.1U_0402_10V7K

C913 0.1U_0402_10V7K

C914 0.1U_0402_10V7K

C915 0.1U_0402_10V7K

1

2

D4

LVDS@

D4

LVDS@

2

IEDP@

1

2

IEDP@

1

2

IEDP@

1

2

IEDP@

1

2

IEDP@

1

2

IEDP@

1

2

1

LVDS@

R262 0_0402_5%

1

LVDS@

R263 0_0402_5%

1

LVDS@

R265 0_0402_5%

1

LVDS@

R264 0_0402_5%

1

LVDS@

R300 0_0402_5%

1

LVDS@

R299 0_0402_5%

+3VS

IEDP@

5

U3

IN1

VCC

4

OUT

IN2

GND

3

1

R10 0_0402_5%

LVDS@

LVDS_EDID_CLK

LVDS_EDID_DATA

LVDS_TXOUT0+

LVDS_TXOUT0-

LVDS_TXOUT1+

LVDS_TXOUT1-

LVDS_TXOUT0+

2

LVDS_TXOUT0-

2

LVDS_TXOUT1+

2

LVDS_TXOUT1-

2

LCD_TXOUT2+

LCD_TXOUT2-

LCD_TXCLK+

LCD_TXCLK-

LVDS_EDID_CLK

2

LVDS_EDID_DATA

2

1

BKOFF#

2

MC74VHC1G08DFT2G_SC70-5

2

B

Camera

+3VS

From PCH

EC_ENBKL <19,30>

BKOFF# <30>

From EC

Camera

USB20_P11<20>

USB20_N11<20>

Touch Screen

USB20_N8<20>

USB20_P8<20>

20mils

1

2

@

R11 0_0603_5%

C

L1CAM_EMI@

USB20_P11_R

3

2

DLW21HN900HQ2L_4P

@TOUCH_EMI@

1

R3 0_0402_5%

L2 TOUCH_EMI@

2

3

DLW21HN900HQ2L_4P

1

R4 0_0402_5%

@TOUCH_EMI@

4

USB20_N11_R

1

2

USB20_N8_R

1

USB20_P8_R

4

2

Reserve for EMI request

LVDS colay eDP cable

JLVDS

@

JLVDS

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

E-T_3753K-F30N-07R

@

1

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

+5VS_LVDS_TOUCH

USB20_N8_R

USB20_P8_R

BKOFF#

+3VS_LVDS_CAM

USB20_P11_R

USB20_N11_R

LVDS_TXOUT0+

LVDS_TXOUT0-

LVDS_TXOUT1+

LVDS_TXOUT1-

LCD_TXOUT2+

LCD_TXOUT2-

LCD_TXCLK+

LCD_TXCLK-

pin1,3,5,6,7,8 Camera function with single or dual MIC pin2,4,9,10-30 For LVDS or EDP panel

Touch Screen

+5VS

20mils

2

R12 0_0603_5%

pin1-4 Touch function for panel

LVDS_EDID_CLK

LVDS_EDID_DATA

Irush=1.5A

+LCD_INV

1

2

3

4

5

6

7

8

ACES_50208-00601-P01

LCD POWER CIRCUIT

+LCD_VDD

1

C54.7U_0603_6.3V6K

2

LED_PWM

BKOFF#_R

+3VS

Irush=1.5A

+LCD_VDD

Irush=1.5A

+LCD_INV

60mils

L3

2

FBMA-L11-201209-221LMA30T_0805

EMI@

JTOUCH

1

2

3

4

5

6

GND

@

1

@

R6 0_0805_5%

@

INT_MIC_C LK <29>

INT_MIC_D ATA <29>

CPU_EDP_HPD <6>

60mils

1

D

I rush=2A

W=80mils

U2

+LCD_VDD_R

2

U2

1

OUT

GND

OC

IN

EN

2

3

SY6288C20AAC_SOT23-5

SA000079400

5

LCD_ENVDD_R

4

R5

1

2

1

2

100K_0402_5%

E

+3VS

1

2

R15

0_0402_5%

C11

@

Need to check vol tage level if change R15 resistance

0.1U_0402_10V7K

LCD_ENVDD <19>

1

Camera & MIC

D1 @ESD@

USB20_P11_R

+3VS

INT_MIC_D ATA

LED_PWM

B+

R9

47K_0402_5%

D1 @ESD@

4

5

6

SC300001400

1

D3 RB751V-40 SOD-323

1

2

4

Vbus

6

2

USB20_N11_R

3

2

GND

INT_MIC_C LK

1

close to LVDS conn.

PCH_PWM <19>

From PCH

2

3

Touch Panel

D5

@ESD@

D5

+5VS

USB20_P8_R

@ESD@

6

I/O4

5

VDD

4

I/O3

AZC099-04S.R7G_SOT23-6

USB20_N8_R

3

I/O2

2

GND

BKOFF#

1

I/O1

close to JTOUCH

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

LVDS

LAB412P

E

13 41Wednesday, January 22, 2014

0.2

of

Compal LA-B412P Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual