Compal LA-B412P Schematics

A

B

C

D

E

1

ZFWAA

Dione 10FU/10FUT

2

LA-B412P REV 0.2 Schematic

2

3

Intel Processor (Ivy Bridge) + PCH (Panther Point)

3

2014-01-02 Rev 0.2

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

LAB412P

141Wednesday, January 22, 2014

E

of

4

0.2

A

B

C

D

E

RTC CKT.

DC/DC Interface CKT.

1

Power Circuit DC/DC

page ??

GCLK

SLG3NB244VTR

2

3

Sub Boards

LS-B301P LED/B

LS-B302P Power Button/B

page 16

page 32

page 26

page 31

LVDS & eDP Conn.

CRT Conn.

page 14

HDMI Conn.

page 15

RJ45 Conn.

page 13

RTL8106E & 8111G

PCIe port 1

USB Left

USB20 port 2

page 27

To sub-board (JLAN)

SPI ROM (8MB)

page 16

eDP 1.1 2x

2.7GT/s

PCIe Gen1 1x

1.5V 5GT/s

USB20 1x

5V 480MHz

KB9012

page 30

Intel CPU Ivy Bridge 17W

BGA-1023

31mm*24mm

page 5,6,7,8,9,10

FDI X8

2.7GT/s

DMI X4

5GT/s

Intel PCH Panther Point

FCBGA-989

25mm*25mm

page 16,17,18,19,20,21,22,23,24

LPC BUS

3.3V 33 MHz

TPM

NPCT650

page 26

Memory BUS(DDR3L)

Dual Channel

1.35V DDR3L 1600 MT/s

USB30 1x

5V 5GT/s

USB20 2x

5V 480MHz

USB20 2x

5V 480MHz

PCIe Gen1 1x

1.5V 5GT/s

USB20 1x

5V 480MHz

PCIe Gen1 1x

1.5V 5GT/s

SATA Gen3 1x

5V 6GHz(600MB/s)

SATA Gen2 1x

5V 3GHz(300MB/s)

HD Audio

3.3V 24MHz

HDA Codec

ALC233-VB2

page 29

204pin DDR3-SO-DIMM X2

BANK 0, 1, 2

USB Right 3.0*1+2.0*1

USB20 port 0,1 USB30 port 1

Int. Camera

USB port 11

page 13

NGFF Slot 1 - WLAN & BT

PCIe port 2 & USB port 9

Card Reader

PCIe port 4

page 31

page 28

Touch Screen

USB port 8

To sub-board (JCARD)

SATA HDD

SATA port 0

SATA ODD

SATA port 2

page 25

page 11,12

page 13

page 25

www.schematic-x.blogspot.com

1

2

3

LS-B303P LAN+USB/B Audio Combo Jack

4

LS-B304P CardReader/TP/LID B

page 27

page 31

A

Touch Pad+LID/B

page 31 page 31

To sub-board (JCARD)

SPK Conn

LED/B

Int.KBD

page 31

page 29

To sub-board (JLED)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

JCOM (Combo Jack)

D

page 27

To sub-board (JLAN)

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Block Diagram

LAB412P

E

4

0.2

of

241Wednesday, January 22, 2014

of

241Wednesday, January 22, 2014

of

241Wednesday, January 22, 2014

5

3V5V_EN

B+

D

C

SY8208CQNC

SUSP#

TPS22966DPUR

3V5V_EN_3

Ipeak=5A, Imax=3.5A, Iocp min=6A

SY8206BQNC

SUSP#

TPS22966DPUR

4

Ipeak8A, Imax=5.6A, Iocp min=9A

PCH_PWR_EN#

P-CHANNEL

AO-3413

USB_EN#0

SY6288D20AAC

USB_EN#2

SY6288D20AAC

ODD_EN

TPS22967DSGR

+5VS

AP2151DWG

WOWL_EN

TPS22967DSGR

PCH_PWR_EN#

P-CHANNEL

AO-3413

For ZPODD

For ISCT/WOWL

DESIGN CURRENT 2A

DESIGN CURRENT 6A

DESIGN CURRENT 1A

DESIGN CURRENT 0.1A

DESIGN CURRENT 6A

+5VALW

+5VALW_PCH

+USB_VCCB

+USB_VCCC

+5VS

+5VS_ODD

+HDMI_5V_OUT

+3VL

+3VALW

+3V_WLAN

+3VALW_PCH

+3V_LAN

+3VS

3

2

1

D

C

+3V_WLAN

LCD_ENVDD

SUSP#

B

SY8032ABC

SY6288C20AAC

+1.5V_EN

DESIGN CURRENT 2A

APL5930KAI

VR_ON

ISL95833HRTZ

SUSP#

SY8208DQNC

SYSON

RT8207MZQW

A

Ipeak=10A, Imax=7A, Iocp min=12A

VCCP_PWRGOOD

G978F11U

Ipeak=9A, Imax=6.3A, Iocp min=11A

0.675VR_ON

SUSP

N-CHANNEL

AO4354

DESIGN CURRENT 45A

DESIGN CURRENT 6A

DESIGN CURRENT 1.5A

DESIGN CURRENT 5A

+LCD_VDD

+1.8VS

+1.5VS

+CPU_CORE

+GFX_CORE

+1.05VS_VCCP

+VCCSA

+1.05VS_PCH

+1.35V

+0.675VS

+1.35V_CPU

B

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Power Tree

LAB412P

1

of

341Wednesday, January 22, 2014

of

341Wednesday, January 22, 2014

of

341Wednesday, January 22, 2014

0.2

Voltage Rails

1

State

power plane

A

( O MEANS ON X MEANS OFF )

+RTCVCC

B+

+LCD_INV

+3VL

+5VALW

+3VALW

B

C

D

E

BTO Option Table

+1.35V

+5VS

+3VS

+1.8VS

+1.5VS

+1.35V_CPU

+0.675VS

+CPU_CORE

+GFX_CORE

+VCCSA

+1.05VS_VCCP

+3V_WLAN

+LCD_VDD

Function

description

explain

BTO

Function

description

explain

BTO

Ivy Bridge

i3-3217U

CPUR1@

LVDS-eDP

LVDS eDP

LVDS@ IEDP@

PCHCPU

Panther Point

HM76

HM76R1@

Camera

CAM_EMI@

ISPD

HDMI LOGO

HDMI45@

CRT

w/ CRT w/o CRT

CRT@ CRT@EMI@ NOCRT@

EMI/ESD/RF part

EMI@ @EMI@ ESD@ @ESD@ @RF@

Red Word: always un-mount

ISCT

w/

ISCT@

w/o

NOISCT@

1

S0

S1

S3

2

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

PCH SM Bus Address

Power

+3VS

+3VS Touch Pad

3

EC SM Bus1 Address

+3VL

O

X

O

XX

X

XX

OO

X

Device

DDR SO-DIMM 0

DDR SO-DIMM 1

O

X

HEX

O

X

Address

1010 0000 bA0 H

1010 0100 bA4 H

O

EC SM Bus2 Address

Device Address Address

HEX HEX

16 H

0001 0110 bSmart Battery

12 HSmart Charger 0001 0010 b+3VL

PowerPower

+3VS

Device

96 H

1001 0110 bPCH

Function

description

explain

BTO

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

G3 LOW LOWLOW

SIGNAL

ZPODD

w/

ZPODD@

w/o

NONZP@

SLP_S3# SLP_S4# SLP_S5#

HIGH HIGHHIGH

LOW

HIGH

LOW LOW

LOW LOWLOW

TPM

NPCT650

TPM@

HIGH

Touch Screen

w/ TOUCH

TOUCH_EMI@

2

3

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Notes List

LAB412P

441Wednesday, January 22, 2014

E

of

4

0.2

1

2

+3VALW_PCH

A

@

PM_DRAM_PWRGD_R

1

2

CC621000P_0402_50V7K

ESD@

1

2

CC63180P_0402_50V8J

@ESD@

1

2

CC20100P_0402_50V8J

by ESD requestion and place near CPU

+1.05VS_VCCP

1

2

RC44 62_0402_5%

1

2

RC45 10K_0402_5%

2

H_PROCHOT#

H_PWRGOOD

@

1

CC701000P_0402_50V7K

@

1

CC671000P_0402_50V7K

@

1

CC661000P_0402_50V7K

Please place near UC1

DRAMPWROK

1

2

RC11 200_0402_5%

10K_0402_5%

+3VS

DRAMPWROK<18>

DRAMPWROK

1

2

RC13

2

H_PWRGOOD

H_THERMTRIP#

H_PECI

H_PM_SYNC

BUF_CPU_RST#

+3VALW_PCH

UC3

5

74AHC1G09GW_TSSOP5

P

B

4

O

A

G

3

PM_SYS_PWRGD_BUF

B

H_SNB_IVB#<21>

H_PECI<30>

H_PROCHOT#<30>

H_THERMTRIP#<21>

H_PM_SYNC<18>

H_PWRGOOD<21>

PM_SYS_PWRGD_BUF

+1.35V_CPU

1

RC14

200_0402_5%

2

T1 PAD @

T2 PAD @

RC170 130_0402_5%

RC159

1

H_THERMTRIP#

1

BUF_CPU_RST#

TP_SKTOCC#

H_CATERR#

H_PECI

H_PROCHOT#_R

2

56_0402_5%

H_PM_SYNC

H_PWRGOOD

PM_DRAM_PWRGD_R

2

UC1B

F49

PROC_SELECT#

C57

PROC_DETECT#

C49

CATERR#

A48

PECI

C45

PROCHOT#

D45

THERMTRIP#

C48

PM_SYNC

B46

UNCOREPWRGOOD

BE45

SM_DRAMPWROK

D44

RESET#

IVY-BRIDGE_BGA1 023

CPUR1@

C

100 MHz

J3

BCLK

MISC THERMAL PWR MANAGEMENT

DPLL_REF_CLK

DPLL_REF_CLK#

CLOCKS

SM_DRAMRST#

SM_RCOMP[0]

SM_RCOMP[1]

SM_RCOMP[2]

DDR3

MISC

DDR3

MISC

JTAG & BPM

BCLK#

PRDY#

PREQ#

TCK

TMS

TRST#

TDO

DBR#

BPM#[0]

BPM#[1]

BPM#[2]

BPM#[3]

BPM#[4]

BPM#[5]

BPM#[6]

BPM#[7]

TDI

H2

120 MHz

CLK_CPU_EDP

AG3

CLK_CPU_EDP#

AG1

H_DRAMRST#

AT30

SM_RCOMP_0

BF44

SM_RCOMP_1

BE43

SM_RCOMP_2

BG43

N53

N55

XDP_TCK

L56

XDP_TMS

L55

XDP_TRST#

J58

XDP_TDI

M60

XDP_TDO

L59

K58

G58

E55

E59

G55

G59

H60

J59

J61

D

CLK_CPU_DMI <17>

CLK_CPU_DMI# <17>

CLK_CPU_EDP <17>

CLK_CPU_EDP# <17>

H_DRAMRST# <7>

1

2

RC56 140_0402_1%

RC59 25.5_0402_1%

RC61 200_0402_1%

1

2

1

2

T3 PAD@

T4 PAD@

1

T6 PAD@

T7 PAD@

2

RC55 51_0402_5%

Close to CPU side

E

Stuff RC158&RC157 if do not support eDP

+1.05VS_VCCP

LVDS@

CLK_CPU_EDP#

CLK_CPU_EDP

H_DRAMRST#

LVDS@

1

LVDS@

@ESD@

2

RC157 1K_0402_5%

RC158 1K_0402_5%

CC34 180P_0402_50V8J

by ESD requestion and place near CPU

DDR3 Compensation Signals Layout Note:Place these resistors near Processor

1

2

3

FAN Control Circuit

+5VS

Buffered Reset to CPU

+3VS

PLT_RST# <20,25,26,27,30,31>

UC2

PLT_RST#

4

UC2

1

OE#

IN

GND

VCC

OUT

2

3

74AHC1G125GW_SOT353-5

A

5

BUFO_CPU_RST#

4

+1.05VS_VCCP

1

RC38

75_0402_5%

2

43_0402_1%

1

RC35

BUF_CPU_RST#

2

DFAN1 from EC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

1A

2013/12/17 2014/12/17

+5VS_FAN

1

2

@

R1 0_0603_5%

+FAN2

DFAN1<30>

10mil

1

2

Main source SA00005CA00 2nd source SA00005JO00

Compal Secret Data

Deciphered Date

U1

1

EN

2

VIN

3

VOUT

4

VSET

NCT3942S_SOP 8P

C3

10U_0603_6.3V6M

C1

10U_0603_6.3V6M

8

GND

7

GND

6

GND

5

GND

D

+FAN2

@

1

2

C2

1000P_0402_50V7K

2

1

JFAN

@

1

2

3

4

GND

5

GND

CVILU_CI4403M1HRT-NH

R2 10K_0402_5%

1

2

1

C4

0.01U_0402_25V7K

@

2

+3VS

FAN_SPEED1 <30>

FAN_SPEED1 to EC

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Ivy Bridge_JTAG/XDP/FAN

LAB412P

E

4

0.2

of

541Wednesday, January 22, 2014

of

541Wednesday, January 22, 2014

of

541Wednesday, January 22, 2014

A

B

C

D

E

+1.05VS_VCCP

RC1

24.9_0402_1%

UC1A

1

2

+1.05VS_VCCP

eDP_COMP signals should be shorted near balls and routed with typical impedance <25m ohm

3

+1.05VS_VCCP

2

1

H_EDP_HPD#

1

D

IEDP@

RC9

2

G

S

3

2

1

CPU_EDP_HPD<13>

100K_0402_5%

4

DMI_PTX_CRX_N0<18>

DMI_PTX_CRX_N1<18>

DMI_PTX_CRX_N2<18>

DMI_PTX_CRX_N3<18>

DMI_PTX_CRX_P0<18>

DMI_PTX_CRX_P1<18>

DMI_PTX_CRX_P2<18>

DMI_PTX_CRX_P3<18>

DMI_CTX_PRX_N0<18>

DMI_CTX_PRX_N1<18>

DMI_CTX_PRX_N2<18>

DMI_CTX_PRX_N3<18>

DMI_CTX_PRX_P0<18>

DMI_CTX_PRX_P1<18>

DMI_CTX_PRX_P2<18>

DMI_CTX_PRX_P3<18>

FDI_CTX_PRX_N0<18>

FDI_CTX_PRX_N1<18>

FDI_CTX_PRX_N2<18>

FDI_CTX_PRX_N3<18>

FDI_CTX_PRX_N4<18>

FDI_CTX_PRX_N5<18>

FDI_CTX_PRX_N6<18>

FDI_CTX_PRX_N7<18>

FDI_CTX_PRX_P0<18>

FDI_CTX_PRX_P1<18>

FDI_CTX_PRX_P2<18>

FDI_CTX_PRX_P3<18>

FDI_CTX_PRX_P4<18>

FDI_CTX_PRX_P5<18>

FDI_CTX_PRX_P6<18>

FDI_CTX_PRX_P7<18>

FDI_FSYNC0<18>

FDI_FSYNC1<18>

FDI_INT<18>

FDI_LSYNC0<18>

FDI_LSYNC1<18>

1

RC2 24.9_0402_1%

H_EDP_AUXN<13>

H_EDP_AUXP<13>

H_EDP_TXN0<13>

H_EDP_TXN1<13>

H_EDP_TXP0<13>

H_EDP_TXP1<13>

RC10

1K_0402_5%

2N7002_SOT23-3

QC1

IEDP@

2

EDP_COMP

H_EDP_HPD#

M2

DMI_RX#[0]

P6

DMI_RX#[1]

P1

DMI_RX#[2]

P10

DMI_RX#[3]

N3

DMI_RX[0]

P7

DMI_RX[1]

P3

DMI_RX[2]

P11

DMI_RX[3]

K1

DMI_TX#[0]

M8

DMI_TX#[1]

N4

DMI_TX#[2]

R2

DMI_TX#[3]

K3

DMI_TX[0]

M7

DMI_TX[1]

P4

DMI_TX[2]

T3

DMI_TX[3]

U7

FDI0_TX#[0]

W11

FDI0_TX#[1]

W1

FDI0_TX#[2]

AA6

FDI0_TX#[3]

W6

FDI1_TX#[0]

V4

FDI1_TX#[1]

Y2

FDI1_TX#[2]

AC9

FDI1_TX#[3]

U6

FDI0_TX[0]

W10

FDI0_TX[1]

W3

FDI0_TX[2]

AA7

FDI0_TX[3]

W7

FDI1_TX[0]

T4

FDI1_TX[1]

AA3

FDI1_TX[2]

AC8

FDI1_TX[3]

AA11

FDI0_FSYNC

AC12

FDI1_FSYNC

U11

FDI_INT

AA10

FDI0_LSYNC

AG8

FDI1_LSYNC

AF3

eDP_COM PIO

AD2

eDP_ICO MPO

AG11

eDP_HP D#

AG4

eDP_AU X#

AF4

eDP_AU X

AC3

eDP_TX #[0]

AC4

eDP_TX #[1]

AE11

eDP_TX #[2]

AE7

eDP_TX #[3]

AC1

eDP_TX [0]

AA4

eDP_TX [1]

AE10

eDP_TX [2]

AE6

eDP_TX [3]

IVY-BRIDGE_BGA1 023

CPUR1@

DMI Intel(R) FDI

eDP

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0]

PEG_RX#[1]

PEG_RX#[2]

PEG_RX#[3]

PEG_RX#[4]

PEG_RX#[5]

PEG_RX#[6]

PEG_RX#[7]

PEG_RX#[8]

PEG_RX#[9]

PEG_RX#[10]

PEG_RX#[11]

PEG_RX#[12]

PEG_RX#[13]

PEG_RX#[14]

PEG_RX#[15]

PEG_RX[0]

PEG_RX[1]

PEG_RX[2]

PEG_RX[3]

PEG_RX[4]

PEG_RX[5]

PEG_RX[6]

PEG_RX[7]

PEG_RX[8]

PEG_RX[9]

PEG_RX[10]

PEG_RX[11]

PEG_RX[12]

PEG_RX[13]

PEG_RX[14]

PEG_RX[15]

PEG_TX#[0]

PEG_TX#[1]

PEG_TX#[2]

PEG_TX#[3]

PEG_TX#[4]

PEG_TX#[5]

PEG_TX#[6]

PEG_TX#[7]

PEG_TX#[8]

PEG_TX#[9]

PEG_TX#[10]

PEG_TX#[11]

PEG_TX#[12]

PEG_TX#[13]

PEG_TX#[14]

PCI EXPRESS -- GRAPHICS

PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]

PEG_TX[10]

PEG_TX[11]

PEG_TX[12]

PEG_TX[13]

PEG_TX[14]

PEG_TX[15]

PEG_COMP

G3

G1

G4

H22

J21

B22

D21

A19

D17

B14

D13

A11

B10

G8

A8

B6

H8

E5

K7

K22

K19

C21

D19

C19

D16

C13

D12

C11

C9

F8

C8

C5

H6

F6

K6

G22

C23

D23

F21

H19

C17

K15

F17

F14

A15

J14

H13

M10

F10

D9

J4

F22

A23

D24

E21

G19

B18

K17

G17

E14

C15

K13

G13

K10

G10

D8

K4

24.9_0402_1%

PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical

1

impedance = 43 m ohm (4 mils) PEG_ICOMPO signals should be routed with max length = 500 mils

2

- typical impedance = 14.5 m ohm (12 mils)

1

2

3

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Ivy Bridge_DMI/PEG/FDI

LAB412P

E

641Wednesday, January 22, 2014

0.2

of

A

DDR_A_D[0..63]<11>

UC1C

DDR_A_D0

DDR_A_D1

DDR_A_D2

DDR_A_D3

DDR_A_D4

DDR_A_D5

DDR_A_D6

1

2

DDR_A_BS0<11>

DDR_A_BS1<11>

3

DDR_A_BS2<11>

DDR_A_CAS#<11>

DDR_A_RAS#<11>

DDR_A_WE#<11>

DDR_A_D7

DDR_A_D8

DDR_A_D9

DDR_A_D10

DDR_A_D11

DDR_A_D12

DDR_A_D13

DDR_A_D14

DDR_A_D15

DDR_A_D16

DDR_A_D17

DDR_A_D18

DDR_A_D19

DDR_A_D20

DDR_A_D21

DDR_A_D22

DDR_A_D23

DDR_A_D24

DDR_A_D25

DDR_A_D26

DDR_A_D27

DDR_A_D28

DDR_A_D29

DDR_A_D30

DDR_A_D31

DDR_A_D32

DDR_A_D33

DDR_A_D34

DDR_A_D35

DDR_A_D36

DDR_A_D37

DDR_A_D38

DDR_A_D39

DDR_A_D40

DDR_A_D41

DDR_A_D42

DDR_A_D43

DDR_A_D44

DDR_A_D45

DDR_A_D46

DDR_A_D47

DDR_A_D48

DDR_A_D49

DDR_A_D50

DDR_A_D51

DDR_A_D52

DDR_A_D53

DDR_A_D54

DDR_A_D55

DDR_A_D56

DDR_A_D57

DDR_A_D58

DDR_A_D59

DDR_A_D60

DDR_A_D61

DDR_A_D62

DDR_A_D63

DDR_A_BS0

DDR_A_BS1

DDR_A_BS2

DDR_A_CAS#

DDR_A_RAS#

DDR_A_WE#

AG6

SA_DQ[0]

AJ6

SA_DQ[1]

AP11

SA_DQ[2]

AL6

SA_DQ[3]

AJ10

SA_DQ[4]

AJ8

SA_DQ[5]

AL8

SA_DQ[6]

AL7

SA_DQ[7]

AR11

SA_DQ[8]

AP6

SA_DQ[9]

AU6

SA_DQ[10]

AV9

SA_DQ[11]

AR6

SA_DQ[12]

AP8

SA_DQ[13]

AT13

SA_DQ[14]

AU13

SA_DQ[15]

BC7

SA_DQ[16]

BB7

SA_DQ[17]

BA13

SA_DQ[18]

BB11

SA_DQ[19]

BA7

SA_DQ[20]

BA9

SA_DQ[21]

BB9

SA_DQ[22]

AY13

SA_DQ[23]

AV14

SA_DQ[24]

AR14

SA_DQ[25]

AY17

SA_DQ[26]

AR19

SA_DQ[27]

BA14

SA_DQ[28]

AU14

SA_DQ[29]

BB14

SA_DQ[30]

BB17

SA_DQ[31]

BA45

SA_DQ[32]

AR43

SA_DQ[33]

AW48

SA_DQ[34]

BC48

SA_DQ[35]

BC45

SA_DQ[36]

AR45

SA_DQ[37]

AT48

SA_DQ[38]

AY48

SA_DQ[39]

BA49

SA_DQ[40]

AV49

SA_DQ[41]

BB51

SA_DQ[42]

AY53

SA_DQ[43]

BB49

SA_DQ[44]

AU49

SA_DQ[45]

BA53

SA_DQ[46]

BB55

SA_DQ[47]

BA55

SA_DQ[48]

AV56

SA_DQ[49]

AP50

SA_DQ[50]

AP53

SA_DQ[51]

AV54

SA_DQ[52]

AT54

SA_DQ[53]

AP56

SA_DQ[54]

AP52

SA_DQ[55]

AN57

SA_DQ[56]

AN53

SA_DQ[57]

AG56

SA_DQ[58]

AG53

SA_DQ[59]

AN55

SA_DQ[60]

AN52

SA_DQ[61]

AG55

SA_DQ[62]

AK56

SA_DQ[63]

BD37

SA_BS[0]

BF36

SA_BS[1]

BA28

SA_BS[2]

BE39

SA_CAS#

BD39

SA_RAS#

AT41

SA_WE#

IVY-BRIDGE_BGA1 023

CPUR1@

DDR SYSTEM MEMORY A

B

SA_CK[0]

SA_CK#[0]

SA_CKE[0]

SA_CK[1]

SA_CK#[1]

SA_CKE[1]

SA_CS#[0]

SA_CS#[1]

SA_ODT[0]

SA_ODT[1]

SA_DQS#[0]

SA_DQS#[1]

SA_DQS#[2]

SA_DQS#[3]

SA_DQS#[4]

SA_DQS#[5]

SA_DQS#[6]

SA_DQS#[7]

SA_DQS[0]

SA_DQS[1]

SA_DQS[2]

SA_DQS[3]

SA_DQS[4]

SA_DQS[5]

SA_DQS[6]

SA_DQS[7]

SA_MA[0]

SA_MA[1]

SA_MA[2]

SA_MA[3]

SA_MA[4]

SA_MA[5]

SA_MA[6]

SA_MA[7]

SA_MA[8]

SA_MA[9]

SA_MA[10]

SA_MA[11]

SA_MA[12]

SA_MA[13]

SA_MA[14]

SA_MA[15]

DDRA_CLK0

AU36

DDRA_CLK0#

AV36

AY26

DDRA_CLK1

AT40

DDRA_CLK1#

AU40

DDRA_CKE1

BB26

DDRA_SCS0#

BB40

DDRA_SCS1#

BC41

DDRA_ODT0

AY40

DDRA_ODT1

BA41

DDR_A_DQS#0

AL11

DDR_A_DQS#1

AR8

DDR_A_DQS#2

AV11

DDR_A_DQS#3

AT17

DDR_A_DQS#4

AV45

DDR_A_DQS#5

AY51

DDR_A_DQS#6

AT55

DDR_A_DQS#7

AK55

DDR_A_DQS0

AJ11

DDR_A_DQS1

AR10

DDR_A_DQS2

AY11

DDR_A_DQS3

AU17

DDR_A_DQS4

AW45

DDR_A_DQS5

AV51

DDR_A_DQS6

AT56

DDR_A_DQS7

AK54

BG35

BB34

BE35

BD35

AT34

AU34

BB32

AT32

AY32

AV32

BE37

BA30

BC30

AW41

DDR_A_MA14

DDR_A_MA15

AY28

AU26

DDRA_CKE0

DDR_A_MA0

DDR_A_MA1

DDR_A_MA2

DDR_A_MA3

DDR_A_MA4

DDR_A_MA5

DDR_A_MA6

DDR_A_MA7

DDR_A_MA8

DDR_A_MA9

DDR_A_MA10

DDR_A_MA11

DDR_A_MA12

DDR_A_MA13

DDR_B_D[0..63]<12>

DDRA_CLK0 <11>

DDRA_CLK0# <11>

DDRA_CKE0 <11>

DDRA_CLK1 <11>

DDRA_CLK1# <11>

DDRA_CKE1 <11>

DDRA_SCS0# <11>

DDRA_SCS1# <11>

DDRA_ODT0 <11>

DDRA_ODT1 <11>

DDR_A_DQS#[0..7] <11>

DDR_A_DQS[0..7] <11>

DDR_A_MA[0..15] <11>

C

UC1D

DDR_B_D0

DDR_B_D1

DDR_B_D2

DDR_B_D3

DDR_B_D4

DDR_B_D5

DDR_B_D6

DDR_B_D7

DDR_B_D8

DDR_B_D9

DDR_B_D10

DDR_B_D11

DDR_B_D12

DDR_B_D13

DDR_B_D14

DDR_B_D15

DDR_B_D16

DDR_B_D17

DDR_B_D18

DDR_B_D19

DDR_B_D20

DDR_B_D21

DDR_B_D22

DDR_B_D23

DDR_B_D24

DDR_B_D25

DDR_B_D26

DDR_B_D27

DDR_B_D28

DDR_B_D29

DDR_B_D30

DDR_B_D31

DDR_B_D32

DDR_B_D33

DDR_B_D34

DDR_B_D35

DDR_B_D36

DDR_B_D37

DDR_B_D38

DDR_B_D39

DDR_B_D40

DDR_B_D41

DDR_B_D42

DDR_B_D43

DDR_B_D44

DDR_B_D45

DDR_B_D46

DDR_B_D47

DDR_B_D48

DDR_B_D49

DDR_B_D50

DDR_B_D51

DDR_B_D52

DDR_B_D53

DDR_B_D54

DDR_B_D55

DDR_B_D56

DDR_B_D57

DDR_B_D58

DDR_B_D59

DDR_B_D60

DDR_B_D61

DDR_B_D62

DDR_B_D63

DDR_B_BS0<12>

DDR_B_BS1<12>

DDR_B_BS2<12>

DDR_B_CAS#<12>

DDR_B_RAS#<12>

DDR_B_WE#<12>

DDR_B_BS0

DDR_B_BS1

DDR_B_BS2

DDR_B_CAS#

DDR_B_RAS#

DDR_B_WE#

AL4

SB_DQ[0]

AL1

SB_DQ[1]

AN3

SB_DQ[2]

AR4

SB_DQ[3]

AK4

SB_DQ[4]

AK3

SB_DQ[5]

AN4

SB_DQ[6]

AR1

SB_DQ[7]

AU4

SB_DQ[8]

AT2

SB_DQ[9]

AV4

SB_DQ[10]

BA4

SB_DQ[11]

AU3

SB_DQ[12]

AR3

SB_DQ[13]

AY2

SB_DQ[14]

BA3

SB_DQ[15]

BE9

SB_DQ[16]

BD9

SB_DQ[17]

BD13

SB_DQ[18]

BF12

SB_DQ[19]

BF8

SB_DQ[20]

BD10

SB_DQ[21]

BD14

SB_DQ[22]

BE13

SB_DQ[23]

BF16

SB_DQ[24]

BE17

SB_DQ[25]

BE18

SB_DQ[26]

BE21

SB_DQ[27]

BE14

SB_DQ[28]

BG14

SB_DQ[29]

BG18

SB_DQ[30]

BF19

SB_DQ[31]

BD50

SB_DQ[32]

BF48

SB_DQ[33]

BD53

SB_DQ[34]

BF52

SB_DQ[35]

BD49

SB_DQ[36]

BE49

SB_DQ[37]

BD54

SB_DQ[38]

BE53

SB_DQ[39]

BF56

SB_DQ[40]

BE57

SB_DQ[41]

BC59

SB_DQ[42]

AY60

SB_DQ[43]

BE54

SB_DQ[44]

BG54

SB_DQ[45]

BA58

SB_DQ[46]

AW59

SB_DQ[47]

AW58

SB_DQ[48]

AU58

SB_DQ[49]

AN61

SB_DQ[50]

AN59

SB_DQ[51]

AU59

SB_DQ[52]

AU61

SB_DQ[53]

AN58

SB_DQ[54]

AR58

SB_DQ[55]

AK58

SB_DQ[56]

AL58

SB_DQ[57]

AG58

SB_DQ[58]

AG59

SB_DQ[59]

AM60

SB_DQ[60]

AL59

SB_DQ[61]

AF61

SB_DQ[62]

AH60

SB_DQ[63]

BG39

SB_BS[0]

BD42

SB_BS[1]

AT22

SB_BS[2]

AV43

SB_CAS#

BF40

SB_RAS#

BD45

SB_WE#

IVY-BRIDGE_BGA1 023

CPUR1@

D

DDRB_CLK0

BA34

SB_CK[0]

SB_CK#[0]

SB_CKE[0]

SB_CK[1]

SB_CK#[1]

SB_CKE[1]

SB_CS#[0]

SB_CS#[1]

SB_ODT[0]

SB_ODT[1]

SB_DQS#[0]

SB_DQS#[1]

SB_DQS#[2]

SB_DQS#[3]

SB_DQS#[4]

SB_DQS#[5]

SB_DQS#[6]

SB_DQS#[7]

SB_DQS[0]

SB_DQS[1]

SB_DQS[2]

SB_DQS[3]

SB_DQS[4]

SB_DQS[5]

SB_DQS[6]

SB_DQS[7]

DDR SYSTEM MEMORY B

SB_MA[0]

SB_MA[1]

SB_MA[2]

SB_MA[3]

SB_MA[4]

SB_MA[5]

SB_MA[6]

SB_MA[7]

SB_MA[8]

SB_MA[9]

SB_MA[10]

SB_MA[11]

SB_MA[12]

SB_MA[13]

SB_MA[14]

SB_MA[15]

DDRB_CLK0#

AY34

DDRB_CKE0

AR22

DDRB_CLK1

BA36

DDRB_CLK1#

BB36

DDRB_CKE1

BF27

DDRB_SCS0#

BE41

DDRB_SCS1#

BE47

DDRB_ODT0

AT43

DDRB_ODT1

BG47

DDR_B_DQS#0

AL3

DDR_B_DQS#1

AV3

DDR_B_DQS#2

BG11

DDR_B_DQS#3

BD17

DDR_B_DQS#4

BG51

DDR_B_DQS#5

BA59

DDR_B_DQS#6

AT60

DDR_B_DQS#7

AK59

DDR_B_DQS0

AM2

DDR_B_DQS1

AV1

DDR_B_DQS2

BE11

DDR_B_DQS3

BD18

DDR_B_DQS4

BE51

DDR_B_DQS5

BA61

DDR_B_DQS6

AR59

DDR_B_DQS7

AK61

DDR_B_MA0

DDR_B_MA1

BF32

DDR_B_MA2

BE33

DDR_B_MA3

BD33

DDR_B_MA4

AU30

DDR_B_MA5

BD30

DDR_B_MA6

AV30

DDR_B_MA7

BG30

DDR_B_MA8

BD29

DDR_B_MA9

BE30

DDR_B_MA10

BE28

DDR_B_MA11

BD43

DDR_B_MA12

AT28

DDR_B_MA13

AV28

DDR_B_MA14

BD46

DDR_B_MA15

AT26

AU22

DDRB_CLK0 <12>

DDRB_CLK0# <12>

DDRB_CKE0 <12>

DDRB_CLK1 <12>

DDRB_CLK1# <12>

DDRB_CKE1 <12>

DDRB_SCS0# <12>

DDRB_SCS1# <12>

DDRB_ODT0 <12>

DDRB_ODT1 <12>

DDR_B_DQS#[0..7] <12>

DDR_B_DQS[0..7] <12>

DDR_B_MA[0..15] <12>

E

1

2

3

+1.35V

1

RC76

1K_0402_5%

D

S

D

S

1

3

G

2

1

CC37

0.047U_0402_25V7K

2

DDR3_DRAMRST#_R

QC3

BSS138_NL_SOT23-3

1

RC73 0_0402_5%

A

H_DRAMRST#

4.99K_0402_1%

DRAMRST_CNTRL

2

RC78

2

1

H_DRAMRST#<5>

4

DRAMRST_CNTRL_PCH<17,9>

2

RC77

1K_0402_5%

1

2

B

SM_DRAMRST# <11,12>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Ivy Bridge_DDR3

LAB412P

E

741Wednesday, January 22, 2014

of

4

0.2

A

B

C

D

E

+CPU_CORE

1

2

3

4

A

UC1F

A26

VCC[1]

A29

VCC[2]

A31

VCC[3]

A34

VCC[4]

A35

VCC[5]

A38

VCC[6]

A39

VCC[7]

A42

VCC[8]

C26

VCC[9]

C27

VCC[10]

C32

VCC[11]

C34

VCC[12]

C37

VCC[13]

C39

VCC[14]

C42

VCC[15]

D27

VCC[16]

D32

VCC[17]

D34

VCC[18]

D37

VCC[19]

D39

VCC[20]

D42

VCC[21]

E26

VCC[22]

E28

VCC[23]

E32

VCC[24]

E34

VCC[25]

E37

VCC[26]

E38

VCC[27]

F25

VCC[28]

F26

VCC[29]

F28

VCC[30]

F32

VCC[31]

F34

VCC[32]

F37

VCC[33]

F38

VCC[34]

F42

VCC[35]

G42

VCC[36]

H25

VCC[37]

H26

VCC[38]

H28

VCC[39]

H29

VCC[40]

H32

VCC[41]

H34

VCC[42]

H35

VCC[43]

H37

VCC[44]

H38

VCC[45]

H40

VCC[46]

J25

VCC[47]

J26

VCC[48]

J28

VCC[49]

J29

VCC[50]

J32

VCC[51]

J34

VCC[52]

J35

VCC[53]

J37

VCC[54]

J38

VCC[55]

J40

VCC[56]

J42

VCC[57]

K26

VCC[58]

K27

VCC[59]

K29

VCC[60]

K32

VCC[61]

K34

VCC[62]

K35

VCC[63]

K37

VCC[64]

K39

VCC[66]

K42

VCC[67]

L25

VCC[68]

L28

VCC[69]

L33

VCC[70]

L36

VCC[71]

L40

VCC[72]

N26

VCC[73]

N30

VCC[74]

N34

VCC[75]

N38

VCC[76]

IVY-BRIDGE_BGA1 023

CPUR1@

POWER

CORE SUPPLY

8.5A33A

PEG IO AND DDR IO

VCCIO_SEL

RAILS

VIDALERT#

VCC_SENSE

VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID QUIET

B

VCCIO[1]

VCCIO[3]

VCCIO[4]

VCCIO[5]

VCCIO[6]

VCCIO[7]

VCCIO[8]

VCCIO[9]

VCCIO[10]

VCCIO[11]

VCCIO[12]

VCCIO[13]

VCCIO[14]

VCCIO[15]

VCCIO[16]

VCCIO[17]

VCCIO[18]

VCCIO[19]

VCCIO[20]

VCCIO[21]

VCCIO[22]

VCCIO[23]

VCCIO[24]

VCCIO[25]

VCCIO[26]

VCCIO[27]

VCCIO[28]

VCCIO[29]

VCCIO[30]

VCCIO[31]

VCCIO[32]

VCCIO[33]

VCCIO[34]

VCCIO[35]

VCCIO[36]

VCCIO[37]

VCCIO[38]

VCCIO[39]

VCCIO[40]

VCCIO[41]

VCCIO[42]

VCCIO[43]

VCCIO[44]

VCCIO[45]

VCCIO[46]

VCCIO[47]

VCCIO[48]

VCCIO[49]

VCCIO50

VCCIO51

1mA

VCCPQE[1]

VCCPQE[2]

VIDSCLK

VIDSOUT

+1.05VS_VCCP

AF46

AG48

AG50

AG51

AJ17

AJ21

AJ25

AJ43

AJ47

AK50

AK51

AL14

AL15

AL16

AL20

AL22

AL26

AL45

AL48

AM16

AM17

AM21

AM43

AM47

AN20

AN42

AN45

AN48

AA14

AA15

AB17

AB20

AC13

AD16

AD18

AD21

AE14

AE15

AF16

AF18

AF20

AG15

AG16

AG17

AG20

AG21

AJ14

AJ15

+1.05VS_VCCP

W16

W17

BC22

+1.05VS_VCCP

AM25

AN22

H_CPU_SVIDALRT#

A44

B43

C44

F43

G43

AN16

AN17

For DDR

For PEG

1

CC71

1U_0402_6.3V6K

2

1

RC98

10_0402_1%

2

1

RC96

10_0402_1%

Close to CPU

2

+1.05VS_VCCP

1

CC17

2

ESD@

100P_0402_50V8J

1

CC19

CC18

2

ESD@

100P_0402_50V8J

by ESD requestion and place near CPU

+1.05VS_VCCP

1

RC91

130_0402_5%

2

RC90 43_0402_1%

+CPU_CORE

VCCIO_SENSE <38>

+1.05VS_VCCP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

RC90 43_0402_1%

2

RC93

100_0402_1%

1

RC97

100_0402_1%

2

Close to CPU

C

+1.05VS_VCCP

1

RC89

75_0402_5%

1

2013/12/17 2014/12/17

2

VCCSENSE <40>

VSSSENSE <40>

VR_SVID_ALRT# <40>

VR_SVID_CLK <40>

VR_SVID_DAT <40>

Pull high resistor on VR side

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Ivy Bridge_POWER-1

LAB412P

841Wednesday, January 22, 2014

E

841Wednesday, January 22, 2014

of

1

2

3

4

0.2

A

B

C

D

E

1

2

VCC_AXG_SENSE<40>

VSS_AXG_SENSE<40>

3

4

VCCPLL Decoupling: 1X 330U (6m ohm), 1X 10U, 2x1U

1

+VCCSA

CC44

1

@

2

@

10U_0603_6.3V6M

Place TOP IN BGA

CC42

2

1

10U_0603_6.3V6M

47U_0805_6.3V6M

Place BOT OUT BGA

CC77

1

2

1U_0402_6.3V6K

+1.8VS

RC119 0_0805_5%

+VCCSA Decoupling: 2X 47U (MLCC), 3X 10U, 5X 1U

A

CC59

CC41

2

1

CC76

1

2

+GFX_CORE

1

2

10U_0603_6.3V6M

1U_0402_6.3V6K

CC75

1

RC105

100_0402_1%

Close to CPU

2

RC106

1

100_0402_1%

+1.8VS_VCCPLL

CC60

1

2

1U_0402_6.3V6K

CC40

CC43

1

2

@

2

1

10U_0603_6.3V6M

CC74

1

2

1U_0402_6.3V6K

47U_0805_6.3V6M

1U_0402_6.3V6K

+GFX_CORE

2

CC73

1

2

1U_0402_6.3V6K

UC1G

29A

AA46

VAXG[1]

AB47

VAXG[2]

AB50

VAXG[3]

AB51

VAXG[4]

AB52

VAXG[5]

AB53

VAXG[6]

AB55

VAXG[7]

AB56

VAXG[8]

AB58

VAXG[9]

AB59

VAXG[10]

AC61

VAXG[11]

AD47

VAXG[12]

AD48

VAXG[13]

AD50

VAXG[14]

AD51

VAXG[15]

AD52

VAXG[16]

AD53

VAXG[17]

AD55

VAXG[18]

AD56

VAXG[19]

AD58

VAXG[20]

AD59

VAXG[21]

AE46

VAXG[22]

N45

VAXG[23]

P47

VAXG[24]

P48

VAXG[25]

P50

VAXG[26]

P51

VAXG[27]

P52

VAXG[28]

P53

VAXG[29]

P55

VAXG[30]

P56

VAXG[31]

P61

VAXG[32]

T48

VAXG[33]

T58

VAXG[34]

T59

VAXG[35]

T61

VAXG[36]

U46

VAXG[37]

V47

VAXG[38]

V48

VAXG[39]

V50

VAXG[40]

V51

VAXG[41]

V52

VAXG[42]

V53

VAXG[43]

V55

VAXG[44]

V56

VAXG[45]

V58

VAXG[46]

V59

VAXG[47]

W50

VAXG[48]

W51

VAXG[49]

W52

VAXG[50]

W53

VAXG[51]

W55

VAXG[52]

W56

VAXG[53]

W61

VAXG[54]

Y48

VAXG[55]

Y61

VAXG[56]

F45

VAXG_SENSE

G45

VSSAXG_SENSE

1.2A

BB3

VCCPLL[1]

BC1

VCCPLL[2]

BC4

VCCPLL[3]

6A

L17

VCCSA[1]

L21

VCCSA[2]

N16

VCCSA[3]

N20

VCCSA[4]

N22

VCCSA[5]

P17

VCCSA[6]

P20

VCCSA[7]

R16

VCCSA[8]

R18

VCCSA[9]

R21

VCCSA[10]

U15

VCCSA[11]

V16

VCCSA[12]

V17

VCCSA[13]

V18

VCCSA[14]

V21

VCCSA[15]

W20

VCCSA[16]

IVY-BRIDGE_BGA1 023

CPUR1@

POWER

VREF

DDR3 - 1.5V RAILS

GRAPHICS

SENSE

LINES

SENSE

LINES

1.8V RAIL

SA RAIL

VCCSA VID

B

SM_VREF

SA_DIMM_VREFDQ

SB_DIMM_VREFDQ

5A

VDDQ[1]

VDDQ[2]

VDDQ[3]

VDDQ[4]

VDDQ[5]

VDDQ[6]

VDDQ[7]

VDDQ[8]

VDDQ[9]

VDDQ[10]

VDDQ[11]

VDDQ[12]

VDDQ[13]

VDDQ[14]

VDDQ[15]

VDDQ[16]

VDDQ[17]

VDDQ[18]

VDDQ[19]

VDDQ[20]

VDDQ[21]

VDDQ[22]

VDDQ[23]

VDDQ[24]

VDDQ[25]

VDDQ[26]

1mA

VCCDQ[1]

VCCDQ[2]

QUIET RAILS

VDDQ_SENSE

VSS_SENSE_VDDQ

SENSE LINES

VCCSA_SENSE

VCCSA_VID[0]

VCCSA_VID[1]

lines

+V_SM_VREF should have 20 mil trace width

AY43

BE7

BG7

AJ28

AJ33

AJ36

AJ40

AL30

AL34

AL38

AL42

AM33

AM36

AM40

AN30

AN34

AN38

AR26

AR28

AR30

AR32

AR34

AR36

AR40

AV41

AW26

BA40

BB28

BG33

AM28

AN26

BC43

BA43

U10

D48

D49

+V_SM_VREF

+VREF_DQA_M3

+VREF_DQB_M3

+1.35V_CPU

1

CC72

1U_0402_6.3V6K

2

H_VCCSA_VID0

H_VCCSA_VID1

Power IC intergrate PD

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

Place TOP IN BGA

CC57

CC51

2

1

10U_0603_6.3V6M

CC81

CC82

1

2

1U_0402_6.3V6K

H_VCCSA_VID0 <38>

H_VCCSA_VID1 <38>

C

+1.35V_CPU

RC120 1K_0402_0.5%

1

2

1

CC65

RC109 1K_0402_0.5%

1

2

0.1U_0402_10V7K

CC52

CC55

2

1

10U_0603_6.3V6M

2

+1.35V_CPU

CC56

CC54

2

1

10U_0603_6.3V6M

CC50

CC53

1

@

2

10U_0603_6.3V6M

47U_0805_6.3V6M

Place BOT OUT BGA

CC80

CC79

1

2

1U_0402_6.3V6K

CC78

1

2

1U_0402_6.3V6K

VCCSA_VID0

0

1

CC87

1

2

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

VCCSA_VID1

CC85

1

2

0

1

0

1U_0402_6.3V6K

CC86

CC87

11

2

RC203

470_0805_5%

1

3

QC5B

SUSP

2N7002DW-T/R7_SOT363-6

2013/12/17 2014/12/17

5

4

Compal Secret Data

Deciphered Date

Intel DDR Vref M3

BSS138_NL_SOT23-3

S

+VREF_DQA_M3

+VREF_DQB_M3

+1.35V_CPU Decoupling: 2X 47U(MLCC), 6X 10U, 8X 1U

+VCCSA

0.90 V

0.80 V

0.725 V

0.675 V

Id=23A,Rdson=5mohm@10V

+1.35V_CPU

QC4 AO4354_SOIC-8

1

2

D

3

CC69

0.1U_0402_25V6

1

CC68

10U_0603_6.3V6M@

2

3

G

2

3

S

BSS138_NL_SOT23-3

For Sandy Bridge

8

7

6

5

4

RUN_ON_CPU1.5VS3

1

RC205

820K_0402_5%

2

Title

Size Document Number Rev

Custom

Date: Sheet

QC7

D

1

2

1

D

QC8

+1.35V_CPU

+1.35V

RC204

1

220K_0402_5%

6

QC5A

SUSP

2

2N7002DW-T/R7_SOT363-6

1

Compal Electronics, Inc.

Ivy Bridge_POWER-2

LAB412P

+VREF_DQA

DRAMRST_CNTRL_PCH <17,7>

+VREF_DQB

1

2

CC46 0.1U_0402_10V7K@

1

2

CC47 0.1U_0402_10V7K@

1

2

CC48 0.1U_0402_10V7K@

1

2

CC45 0.1U_0402_10V7K@

B+

2

SUSP <32>

E

1

2

3

+1.35V

4

0.2

of

941Wednesday, January 22, 2014

of

941Wednesday, January 22, 2014

of

941Wednesday, January 22, 2014

UC1H

www.vinaﬁx.com

UC1H

A13

VSS[1]

A17

VSS[2]

A21

VSS[3]

A25

VSS[4]

A28

VSS[5]

A33

VSS[6]

A37

VSS[7]

A40

VSS[8]

A45

VSS[9]

A49

1

2

3

4

VSS[10]

A53

VSS[11]

A9

VSS[12]

AA1

VSS[13]

AA13

VSS[14]

AA50

VSS[15]

AA51

VSS[16]

AA52

VSS[17]

AA53

VSS[18]

AA55

VSS[19]

AA56

VSS[20]

AA8

VSS[21]

AB16

VSS[22]

AB18

VSS[23]

AB21

VSS[24]

AB48

VSS[25]

AB61

VSS[26]

AC10

VSS[27]

AC14

VSS[28]

AC46

VSS[29]

AC6

VSS[30]

AD17

VSS[31]

AD20

VSS[32]

AD4

VSS[33]

AD61

VSS[34]

AE13

VSS[35]

AE8

VSS[36]

AF1

VSS[37]

AF17

VSS[38]

AF21

VSS[39]

AF47

VSS[40]

AF48

VSS[41]

AF50

VSS[42]

AF51

VSS[43]

AF52

VSS[44]

AF53

VSS[45]

AF55

VSS[46]

AF56

VSS[47]

AF58

VSS[48]

AF59

VSS[49]

AG10

VSS[50]

AG14

VSS[51]

AG18

VSS[52]

AG47

VSS[53]

AG52

VSS[54]

AG61

VSS[55]

AG7

VSS[56]

AH4

VSS[57]

AH58

VSS[58]

AJ13

VSS[59]

AJ16

VSS[60]

AJ20

VSS[61]

AJ22

VSS[62]

AJ26

VSS[63]

AJ30

VSS[64]

AJ34

VSS[65]

AJ38

VSS[66]

AJ42

VSS[67]

AJ45

VSS[68]

AJ48

VSS[69]

AJ7

VSS[70]

AK1

VSS[71]

AK52

VSS[72]

AL10

VSS[73]

AL13

VSS[74]

AL17

VSS[75]

AL21

VSS[76]

AL25

VSS[77]

AL28

VSS[78]

AL33

VSS[79]

AL36

VSS[80]

AL40

VSS[81]

AL43

VSS[82]

AL47

VSS[83]

AL61

VSS[84]

AM13

VSS[85]

AM20

VSS[86]

AM22

VSS[87]

AM26

VSS[88]

AM30

VSS[89]

AM34

VSS[90]

IVY-BRIDGE_BGA1 023

CPUR1@

A

VSS

VSS[91]

VSS[92]

VSS[93]

VSS[94]

VSS[95]

VSS[96]

VSS[97]

VSS[98]

VSS[99]

VSS[100]

VSS[101]

VSS[102]

VSS[103]

VSS[104]

VSS[105]

VSS[106]

VSS[107]

VSS[108]

VSS[109]

VSS[110]

VSS[111]

VSS[112]

VSS[113]

VSS[114]

VSS[115]

VSS[116]

VSS[117]

VSS[118]

VSS[119]

VSS[120]

VSS[121]

VSS[122]

VSS[123]

VSS[124]

VSS[125]

VSS[126]

VSS[127]

VSS[128]

VSS[129]

VSS[130]

VSS[131]

VSS[132]

VSS[133]

VSS[134]

VSS[135]

VSS[136]

VSS[137]

VSS[138]

VSS[139]

VSS[140]

VSS[141]

VSS[142]

VSS[143]

VSS[144]

VSS[145]

VSS[146]

VSS[147]

VSS[148]

VSS[149]

VSS[150]

VSS[151]

VSS[152]

VSS[153]

VSS[154]

VSS[155]

VSS[156]

VSS[157]

VSS[158]

VSS[159]

VSS[160]

VSS[161]

VSS[162]

VSS[163]

VSS[164]

VSS[165]

VSS[166]

VSS[167]

VSS[168]

VSS[169]

VSS[170]

VSS[171]

VSS[172]

VSS[173]

VSS[174]

VSS[175]

VSS[176]

VSS[177]

VSS[178]

VSS[179]

VSS[180]

AM38

AM4

AM42

AM45

AM48

AM58

AN1

AN21

AN25

AN28

AN33

AN36

AN40

AN43

AN47

AN50

AN54

AP10

AP51

AP55

AP7

AR13

AR17

AR21

AR41

AR48

AR61

AR7

AT14

AT19

AT36

AT4

AT45

AT52

AT58

AU1

AU11

AU28

AU32

AU51

AU7

AV17

AV21

AV22

AV34

AV40

AV48

AV55

AW13

AW43

AW61

AW7

AY14

AY19

AY30

AY36

AY4

AY41

AY45

AY49

AY55

AY58

AY9

BA1

BA11

BA17

BA21

BA26

BA32

BA48

BA51

BB53

BC13

BC5

BC57

BD12

BD16

BD19

BD23

BD27

BD32

BD36

BD40

BD44

BD48

BD52

BD56

BD8

BE5

BG13

BG17

BG21

BG24

BG28

BG37

BG41

BG45

BG49

BG53

BG9

C29

C35

C40

D10

D14

D18

D22

D26

D29

D35

D4

D40

D43

D46

D50

D54

D58

D6

E25

E29

E3

E35

E40

F13

F15

F19

F29

F35

F40

F55

G51

G6

G61

H10

H14

H17

H21

H4

H53

H58

J1

J49

J55

K11

K21

K51

K8

L16

L20

L22

L26

L30

L34

L38

L43

L48

L61

M11

M15

B

UC1I

VSS[181]

VSS[182]

VSS[183]

VSS[184]

VSS[185]

VSS[186]

VSS[187]

VSS[188]

VSS[189]

VSS[190]

VSS[191]

VSS[192]

VSS[193]

VSS[194]

VSS[195]

VSS[196]

VSS[197]

VSS[198]

VSS[199]

VSS[200]

VSS[201]

VSS[202]

VSS[203]

VSS[204]

VSS[205]

VSS[206]

VSS[207]

VSS[208]

VSS[209]

VSS[210]

VSS[211]

VSS[212]

VSS[213]

VSS[214]

VSS[215]

VSS[216]

VSS[217]

VSS[218]

VSS[219]

VSS[220]

VSS[221]

VSS[222]

VSS[223]

VSS[224]

VSS[225]

VSS[226]

VSS[227]

VSS[228]

VSS[229]

VSS[230]

VSS[231]

VSS[232]

VSS[233]

VSS[234]

VSS[235]

VSS[236]

VSS[237]

VSS[238]

VSS[239]

VSS[240]

VSS[241]

VSS[242]

VSS[243]

VSS[244]

VSS[245]

VSS[246]

VSS[247]

VSS[248]

VSS[249]

IVY-BRIDGE_BGA1 023

CPUR1@

VSS

VSS[250]

VSS[251]

VSS[252]

VSS[253]

VSS[254]

VSS[255]

VSS[256]

VSS[257]

VSS[258]

VSS[259]

VSS[260]

VSS[261]

VSS[262]

VSS[263]

VSS[264]

VSS[265]

VSS[266]

VSS[267]

VSS[268]

VSS[269]

VSS[270]

VSS[271]

VSS[272]

VSS[273]

VSS[274]

VSS[275]

VSS[276]

VSS[277]

VSS[278]

VSS[279]

VSS[280]

VSS[281]

VSS[282]

VSS[283]

VSS[284]

VSS[285]

VSS[286]

VSS[287]

VSS[288]

VSS[289]

VSS[290]

VSS[291]

VSS[292]

VSS[293]

VSS[294]

VSS[295]

VSS[296]

VSS[297]

VSS[298]

VSS[299]

VSS[300]

VSS[301]

VSS_NCTF_1

VSS_NCTF_2

VSS_NCTF_3

VSS_NCTF_4

VSS_NCTF_5

VSS_NCTF_6

VSS_NCTF_7

VSS_NCTF_8

VSS_NCTF_9

VSS_NCTF_10

VSS_NCTF_11

NCTF

VSS_NCTF_12

VSS_NCTF_13

VSS_NCTF_14

M4

M58

M6

N1

N17

N21

N25

N28

N33

N36

N40

N43

N47

N48

N51

N52

N56

N61

P14

P16

P18

P21

P58

P59

P9

R17

R20

R4

R46

T1

T47

T50

T51

T52

T53

T55

T56

U13

U8

V20

V61

W13

W15

W18

W21

W46

W8

Y4

Y47

Y58

Y59

G48

A5

A57

BC61

BD3

BD59

BE4

BE58

BG5

BG57

C3

C58

D59

E1

E61

C

UC1E

CFG0

B50

CFG[0]

T87PAD@

CFG2

CFG4

CFG5

CFG6

CFG7

C51

CFG[1]

B54

CFG[2]

D53

CFG[3]

A51

CFG[4]

C53

CFG[5]

C55

CFG[6]

H49

CFG[7]

A55

CFG[8]

H51

CFG[9]

K49

CFG[10]

K53

CFG[11]

F53

CFG[12]

G53

CFG[13]

L51

CFG[14]

F51

CFG[15]

D52

CFG[16]

L53

CFG[17]

H43

VCC_VAL_SENSE

K43

VSS_VAL_SENSE

H45

VAXG_VAL_SENSE

K45

VSSAXG_VAL_SENSE

F48

VCC_DIE_SENSE

H48

RSVD6

K48

RSVD7

BA19

RSVD8

AV19

RSVD9

AT21

RSVD10

BB21

RSVD11

BB19

RSVD12

AY21

RSVD13

BA22

RSVD14

AY22

RSVD15

AU19

RSVD16

AU21

RSVD17

BD21

RSVD18

BD22

RSVD19

BD25

RSVD20

BD26

RSVD21

BG22

RSVD22

BE22

RSVD23

BG26

RSVD24

BE26

RSVD25

BF23

RSVD26

BE24

RSVD27

IVY-BRIDGE_BGA1 023

CPUR1@

BCLK_ITP#

These pins are for solder joint

RESERVED

reliability and non-critical to function. For BGA only.

DC_TEST_A4

DC_TEST_C4

DC_TEST_D3

DC_TEST_D1

DC_TEST_A58

DC_TEST_A59

DC_TEST_C59

DC_TEST_A61

DC_TEST_C61

DC_TEST_D61

DC_TEST_BD61

DC_TEST_BE61

DC_TEST_BE59

DC_TEST_BG61

DC_TEST_BG59

DC_TEST_BG58

DC_TEST_BG4

DC_TEST_BG3

DC_TEST_BE3

DC_TEST_BG1

DC_TEST_BE1

DC_TEST_BD1

T89 PAD@

BCLK_ITP

RSVD30

RSVD31

RSVD32

RSVD33

RSVD34

RSVD35

RSVD36

RSVD37

RSVD38

RSVD39

RSVD40

RSVD41

RSVD42

RSVD43

RSVD44

RSVD45

D

N59

N58

N42

L42

L45

L47

M13

M14

U14

W14

P13

AT49

K24

AH2

AG13

AM14

AM15

N50

A4

C4

DC_TEST_C4_D3

D3

D1

A58

A59

DC_TEST_A59_C59

C59

A61

DC_TEST_A61_C61

C61

D61

BD61

BE61

DC_TEST_BE61_BE59

BE59

BG61

DC_TEST_BG61_BG59

BG59

BG58

BG4

BG3

DC_TEST_BG3_BE3

BE3

BG1

DC_TEST_BG1_BE1

BE1

BD1

E

CFG Straps for Processor

(CFG[17:0] internal pull high 5~15K to VCCIO)

CFG2

1

RC79

1K_0402_1%

@

2

PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane # definition

*

CFG2

matches socket pin map definition

0:Lane Reversed

CFG4

1

RC82

1K_0402_1%

IEDP@

2

Embedded Display Port Presence Strap

1 : Disabled; No Physical Display Port attached to Embedded Display Port

*

CFG4

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

CFG7

1

RC85

1K_0402_1%

@

2

1

2

PEG DEFER TRAINING

CFG7

*

3

1: (Default) PEG Train immediately following xxRESETB de assertion

0: PEG Wait for BIOS for training

CFG6

CFG5

RC83

1K_0402_1%

@

1

RC84

1

1K_0402_1%

@

2

PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2 disabled

*

CFG[6:5]

10: x8, x8 - Device 1 function 1 enabled; function 2 disabled

01: Reserved - (Device 1 function 1 disabled; function 2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

4

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Ivy Bridge_GND/RSVD/CFG

LAB412P

10 41Wednesday, January 22, 2014

E

10 41Wednesday, January 22, 2014

of

0.2

5

4

3

2

1

+1.35V

JDDR3L

+VREF_DQA

1

CD1

0.1U_0402_10V7K

2

D

Close to JDDRL.1

+3VS

DDRA_CKE0<7>

DDR_A_BS2<7>

DDRA_CLK0<7>

DDRA_CLK0#<7>

DDR_A_BS0<7>

DDR_A_WE#<7>

DDR_A_CAS#<7>

DDRA_SCS1#<7>

0.1U_0402_10V7K

C

B

A

DDR_A_D0

DDR_A_D1

DDR_A_D2

DDR_A_D3

DDR_A_D8

DDR_A_D9

DDR_A_DQS#1

DDR_A_DQS1

DDR_A_D10

DDR_A_D11

DDR_A_D16

DDR_A_D17

DDR_A_DQS#2

DDR_A_DQS2

DDR_A_D18

DDR_A_D19

DDR_A_D24

DDR_A_D25

DDR_A_D26

DDR_A_D27

DDR_A_MA12

DDR_A_MA9

DDR_A_MA8

DDR_A_MA5

DDR_A_MA3

DDR_A_MA1

DDR_A_MA10

DDR_A_MA13

DDR_A_D32

DDR_A_D33

DDR_A_DQS#4

DDR_A_DQS4

DDR_A_D34

DDR_A_D35

DDR_A_D40

DDR_A_D41

DDR_A_D42

DDR_A_D43

DDR_A_D48

DDR_A_D49

DDR_A_DQS#6

DDR_A_DQS6

DDR_A_D50

DDR_A_D51

DDR_A_D56

DDR_A_D57

DDR_A_D58

DDR_A_D59

1

CD26

2

SPD setting (SA0, SA1) PU/PD by Channel A/B

->Channel A 00

->Channel B 01

+0.675VS

5

1

VREF_DQ

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1

29

DQS1

31

VSS11

33

DQ10

35

DQ11

37

VSS13

39

DQ16

41

DQ17

43

VSS15

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25

61

VSS22

63

DM3

65

VSS23

67

DQ26

69

DQ27

71

VSS25

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4406-0102

@

DQS#0

VSS10

RESET#

VSS12

VSS14

VSS16

VSS17

VSS19

VSS21

DQS#3

VSS24

VSS26

VDD10

VDD12

VDD14

VDD16

VDD18

VREF_CA

VSS28

VSS30

VSS31

VSS33

VSS35

DQS#5

VSS38

VSS40

VSS42

VSS43

VSS45

VSS47

DQS#7

VSS50

VSS52

EVENT#

VSS1

DQ4

DQ5

VSS3

DQS0

VSS6

DQ6

DQ7

VSS8

DQ12

DQ13

DM1

DQ14

DQ15

DQ20

DQ21

DM2

DQ22

DQ23

DQ28

DQ29

DQS3

DQ30

DQ31

CKE1

VDD2

VDD4

VDD6

VDD8

CK1#

RAS#

ODT0

ODT1

NC2

DQ36

DQ37

DM4

DQ38

DQ39

DQ44

DQ45

DQS5

DQ46

DQ47

DQ52

DQ53

DM6

DQ54

DQ55

DQ60

DQ61

DQS7

DQ62

DQ63

VTT2

CK1

BA1

SDA

A15

A14

A11

S0#

SCL

+1.35V

2

DDR_A_D4

4

DDR_A_D5

6

8

DDR_A_DQS#0

10

DDR_A_DQS0

12

14

DDR_A_D6

16

DDR_A_D7

18

20

DDR_A_D12

22

DDR_A_D13

24

26

28

30

32

DDR_A_D14

34

DDR_A_D15

36

38

DDR_A_D20

40

DDR_A_D21

42

44

46

48

DDR_A_D22

50

DDR_A_D23

52

54

DDR_A_D28

56

DDR_A_D29

58

60

DDR_A_DQS#3

62

DDR_A_DQS3

64

66

DDR_A_D30

68

DDR_A_D31

70

72

74

76

DDR_A_MA15

78

DDR_A_MA14

80

82

DDR_A_MA11

84

DDR_A_MA7

86

A7

88

DDR_A_MA6

90

A6

A4

A2

A0

G2

DDR_A_MA4

92

94

DDR_A_MA2

96

DDR_A_MA0

98

100

102

104

106

108

110

112

114

116

118

120

122

124

+VREF_CAA

126

128

DDR_A_D36

130

DDR_A_D37

132

134

136

138

DDR_A_D38

140

DDR_A_D39

142

144

DDR_A_D44

146

DDR_A_D45

148

150

DDR_A_DQS#5

152

DDR_A_DQS5

154

DDR_A_D46

156

158

DDR_A_D47

160

DDR_A_D52

162

DDR_A_D53

164

166

168

170

DDR_A_D54

172

DDR_A_D55

174

176

DDR_A_D60

178

DDR_A_D61

180

182

DDR_A_DQS#7

184

DDR_A_DQS7

186

188

DDR_A_D62

190

DDR_A_D63

192

194

196

198

200

202

+0.675VS

204

206

4

DDR3 SO-DIMM A Standard Type

SM_DRAMRST# <12,7>

DDRA_CKE1 <7>

DDRA_CLK1 <7>

DDRA_CLK1# <7>

DDR_A_BS1 <7>

DDR_A_RAS# <7>

DDRA_SCS0# <7>

DDRA_ODT0 <7>

DDRA_ODT1 <7>

1

CD16

0.1U_0402_10V7K

2

close to JDDRL.126

PM_SMBDATA <12,17,31>

PM_SMBCLK <12,17,31>

DDR_A_DQS[0..7] <7>

DDR_A_DQS#[0..7] <7>

DDR_A_D[0..63] <7>

DDR_A_MA[0..15] <7>

+1.35V

1

RD1

1K_0402_1%

+VREF_DQA

+1.35V

1

RD6

1K_0402_1%

2

1

RD7

1K_0402_1%

2

Layout Note: Place near JDDRL

+1.35V

1

2

CD8 10U_0603_6.3V6M

1

2

CD9 10U_0603_6.3V6M

1

2

CD10 10U_0603_6.3V6M

1

2

CD11 10U_0603_6.3V6M

1

2

CD12 10U_0603_6.3V6M

1

2

CD13 10U_0603_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

2

1

RD2

1K_0402_1%

2

Layout Note: Place these 4 Caps near Command and Control si gnals of DIMMA

+1.35V

1

2

CD20 0.1U_0402_10V7K

1

2

CD17 0.1U_0402_10V7K

1

2

CD18 0.1U_0402_10V7K

1

2

CD19 0.1U_0402_10V7K

2

Date: Sheet

Layout Note: Place near JDDRL1.203 and 204

+0.675VS

1

2

CD24 1U_0402_6.3V6K

1

2

CD21 1U_0402_6.3V6K

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Compal Electronics, Inc.

DDRIII-SODIMM0

LAB412P

1

11 41Wednesday, January 22, 2014

of

D

C

B

A

0.2

A

B

C

D

E

VSS

DQ4

DQ5

VSS

DQ6

DQ7

VSS

DM1

VSS

DQ21

VSS

DM2

VSS

DQ22

DQ23

VSS

DQ28

DQ29

VSS

DQS3

VSS

DQ30

DQ31

VSS

CKE1

VDD

CK1#

VDD

RAS#

VDD

ODT0

VDD

ODT1

VDD

VSS

DQ36

DQ37

VSS

DM4

VSS

DQ38

DQ39

VSS

DQ44

DQ45

VSS

DQS5

DQ46

DQ47

DQ52

DQ53

DM6

DQ54

DQ55

DQ60

DQ61

DQS7

DQ62

DQ63

SDA

GND2

A15

A14

A11

CK1

BA1

S0#

VSS

SCL

VTT

+1.35V

2

DDR_B_D4

4

DDR_B_D5

6

8

DDR_B_DQS#0

10

DDR_B_DQS0

12

14

DDR_B_D6

16

DDR_B_D7

18

20

DDR_B_D12

22

DDR_B_D13

24

26

28

30

32

DDR_B_D14

34

DDR_B_D15

36

38

DDR_B_D20

40

DDR_B_D21

42

44

46

48

DDR_B_D22

50

DDR_B_D23

52

54

DDR_B_D28

56

DDR_B_D29

58

60

DDR_B_DQS#3

62

DDR_B_DQS3

64

66

DDR_B_D30

68

DDR_B_D31

70

72

74

76

DDR_B_MA15

78

DDR_B_MA14

80

82

DDR_B_MA11

84

DDR_B_MA7

86

A7

88

DDR_B_MA6

90

A6

A4

A2

A0

NC

DDR_B_MA4

92

94

DDR_B_MA2

96

DDR_B_MA0

98

100

102

104

106

108

110

112

114

116

118

120

122

124

+VREF_CAB

126

128

DDR_B_D36

130

DDR_B_D37

132

134

136

DDR_B_D38

138

140

DDR_B_D39

142

DDR_B_D44

144

DDR_B_D45

146

148

DDR_B_DQS#5

150

DDR_B_DQS5

152

154

DDR_B_D46

156

DDR_B_D47

158

160

DDR_B_D52

162

DDR_B_D53

164

166

168

170

DDR_B_D54

172

DDR_B_D55

174

176

DDR_B_D60

178

DDR_B_D61

180

182

DDR_B_DQS#7

184

DDR_B_DQS7

186

188

DDR_B_D62

190

DDR_B_D63

192

194

196

198

200

202

+0.675VS

204

206

208

B

DDR3 SO-DIMM B Reverse Type

SM_DRAMRST# <11,7>

DDRB_CKE1 <7>

DDRB_CLK1 <7>

DDRB_CLK1# <7>

DDR_B_BS1 <7>

DDR_B_RAS# <7>

DDRB_SCS0# <7>

DDRB_ODT0 <7>

DDRB_ODT1 <7>

CD47

0.1U_0402_10V7K

1

2

Close to JDDRH.126

PM_SMBDATA <11,17,31>

PM_SMBCLK <11,17,31>

DDR_B_DQS#[0..7] <7>

DDR_B_DQS[0..7] <7>

DDR_B_D[0..63] <7>

DDR_B_MA[0..15] <7>

+1.35V

1

RD10

1K_0402_1%

+VREF_DQB

+1.35V

1

RD12

1K_0402_1%

2

1

RD13

1K_0402_1%

2

Layout Note: Place near JDDRH

+1.35V

1

CD31 47U_0805_6.3V6M

1

CD41 10U_0603_6.3V6M

1

CD36 10U_0603_6.3V6M

1

CD37 10U_0603_6.3V6M

1

CD38 10U_0603_6.3V6M

1

CD39 10U_0603_6.3V6M

1

CD40 10U_0603_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

2013/12/17 2014/12/17

2

1

2

Compal Secret Data

RD11

1K_0402_1%

Layout Note: Place these 4 Caps near Command and Control si gnals of DIMMB

+1.35V

1

CD33 0.1U_0402_10V7K

CD29 0.1U_0402_10V7K

CD30 0.1U_0402_10V7K

1

CD32 0.1U_0402_10V7K

Deciphered Date

D

2

1

2

1

2

Date: Sheet

Layout Note: Place near JDDRH.203 and 204

+0.675VS

1

2

CD45 1U_0402_6.3V6K

1

2

CD42 1U_0402_6.3V6K

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Compal Electronics, Inc.

DDRIII-SODIMM1

LAB412P

E

12 41Wednesday, January 22, 2014

of

1

2

3

4

0.2

+1.35V

JDDR3H

+VREF_DQB

1

Close to JDDRH.1

+3VS

DDRB_CKE0<7>

DDR_B_BS2<7>

DDRB_CLK0<7>

DDRB_CLK0#<7>

DDR_B_BS0<7>

DDR_B_WE#<7>

DDR_B_CAS#<7>

DDRB_SCS1#<7>

1

CD49

2

0.1U_0402_10V7K

2

3

4

DDR_B_D0

DDR_B_D1

CD27

1

DDR_B_D2

DDR_B_D3

0.1U_0402_10V7K

DDR_B_D8

2

DDR_B_D9

DDR_B_DQS#1

DDR_B_DQS1

DDR_B_D10

DDR_B_D11

DDR_B_D16

DDR_B_D17

DDR_B_DQS#2

DDR_B_DQS2

DDR_B_D18

DDR_B_D19

DDR_B_D24

DDR_B_D25

DDR_B_D26

DDR_B_D27

DDR_B_MA12

DDR_B_MA9

DDR_B_MA8

DDR_B_MA5

DDR_B_MA3

DDR_B_MA1

DDR_B_MA10

DDR_B_MA13

DDR_B_D32

DDR_B_D33

DDR_B_DQS#4

DDR_B_DQS4

DDR_B_D34

DDR_B_D35

DDR_B_D40

DDR_B_D41

DDR_B_D42

DDR_B_D43

DDR_B_D48

DDR_B_D49

DDR_B_DQS#6

DDR_B_DQS6

DDR_B_D50

DDR_B_D51

DDR_B_D56

DDR_B_D57

DDR_B_D58

DDR_B_D59

1

2

RD15 10K_0402_5%

SPD setting (SA0, SA1) PU/PD by Channel A/B

->Channel A 00

->Channel B 01

A

+0.675VS

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

LCN_DAN06-K4406-0103

@

DQS0#

DQS0

DQ12

DQ13

RESET#

DQ14

DQ15

DQ20

DQS3#

VREF_CA

DQS5#

DQS7#

EVENT#

BOSS2

For eDP Panel

H_EDP_AUXP<6>

H_EDP_AUXN<6>

1

H_EDP_TXP0<6>

H_EDP_TXN0<6>

H_EDP_TXP1<6>

H_EDP_TXN1<6>

For LVDS 1ch Panel

LCD_TXOUT0+<19>

LCD_TXOUT0-<19>

LCD_TXOUT1+<19>

LCD_TXOUT1-<19>

LCD_TXOUT2+<19>

LCD_TXOUT2-<19>

LCD_TXCLK+<19>

2

3

BKOFF#_R

4

LCD_TXCLK-<19>

LCD_EDID_CLK<19>

LCD_EDID_DATA<19>

Reserve for eDP panel potential issue

IEDP@

R7 0_0402_5%

1

RB751V-40 SOD-323

1

R8

10K_0402_5%

2

A

C890 0.1U_0402_10V7K

C891 0.1U_0402_10V7K

C912 0.1U_0402_10V7K

C913 0.1U_0402_10V7K

C914 0.1U_0402_10V7K

C915 0.1U_0402_10V7K

1

2

D4

LVDS@

D4

LVDS@

2

IEDP@

1

2

IEDP@

1

2

IEDP@

1

2

IEDP@

1

2

IEDP@

1

2

IEDP@

1

2

1

LVDS@

R262 0_0402_5%

1

LVDS@

R263 0_0402_5%

1

LVDS@

R265 0_0402_5%

1

LVDS@

R264 0_0402_5%

1

LVDS@

R300 0_0402_5%

1

LVDS@

R299 0_0402_5%

+3VS

IEDP@

5

U3

IN1

VCC

4

OUT

IN2

GND

3

1

R10 0_0402_5%

LVDS@

LVDS_EDID_CLK

LVDS_EDID_DATA

LVDS_TXOUT0+

LVDS_TXOUT0-

LVDS_TXOUT1+

LVDS_TXOUT1-

LVDS_TXOUT0+

2

LVDS_TXOUT0-

2

LVDS_TXOUT1+

2

LVDS_TXOUT1-

2

LCD_TXOUT2+

LCD_TXOUT2-

LCD_TXCLK+

LCD_TXCLK-

LVDS_EDID_CLK

2

LVDS_EDID_DATA

2

1

BKOFF#

2

MC74VHC1G08DFT2G_SC70-5

2

B

Camera

+3VS

From PCH

EC_ENBKL <19,30>

BKOFF# <30>

From EC

Camera

USB20_P11<20>

USB20_N11<20>

Touch Screen

USB20_N8<20>

USB20_P8<20>

20mils

1

2

@

R11 0_0603_5%

C

L1CAM_EMI@

USB20_P11_R

3

2

DLW21HN900HQ2L_4P

@TOUCH_EMI@

1

R3 0_0402_5%

L2 TOUCH_EMI@

2

3

DLW21HN900HQ2L_4P

1

R4 0_0402_5%

@TOUCH_EMI@

4

USB20_N11_R

1

2

USB20_N8_R

1

USB20_P8_R

4

2

Reserve for EMI request

LVDS colay eDP cable

JLVDS

@

JLVDS

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

E-T_3753K-F30N-07R

@

1

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

+5VS_LVDS_TOUCH

USB20_N8_R

USB20_P8_R

BKOFF#

+3VS_LVDS_CAM

USB20_P11_R

USB20_N11_R

LVDS_TXOUT0+

LVDS_TXOUT0-

LVDS_TXOUT1+

LVDS_TXOUT1-

LCD_TXOUT2+

LCD_TXOUT2-

LCD_TXCLK+

LCD_TXCLK-

pin1,3,5,6,7,8 Camera function with single or dual MIC pin2,4,9,10-30 For LVDS or EDP panel

Touch Screen

+5VS

20mils

2

R12 0_0603_5%

pin1-4 Touch function for panel

LVDS_EDID_CLK

LVDS_EDID_DATA

Irush=1.5A

+LCD_INV

1

2

3

4

5

6

7

8

ACES_50208-00601-P01

LCD POWER CIRCUIT

+LCD_VDD

1

C54.7U_0603_6.3V6K

2

LED_PWM

BKOFF#_R

+3VS

Irush=1.5A

+LCD_VDD

Irush=1.5A

+LCD_INV

60mils

L3

2

FBMA-L11-201209-221LMA30T_0805

EMI@

JTOUCH

1

2

3

4

5

6

GND

@

1

@

R6 0_0805_5%

@

INT_MIC_C LK <29>

INT_MIC_D ATA <29>

CPU_EDP_HPD <6>

60mils

1

D

I rush=2A

W=80mils

U2

+LCD_VDD_R

2

U2

1

OUT

GND

OC

IN

EN

2

3

SY6288C20AAC_SOT23-5

SA000079400

5

LCD_ENVDD_R

4

R5

1

2

1

2

100K_0402_5%

E

+3VS

1

2

R15

0_0402_5%

C11

@

Need to check vol tage level if change R15 resistance

0.1U_0402_10V7K

LCD_ENVDD <19>

1

Camera & MIC

D1 @ESD@

USB20_P11_R

+3VS

INT_MIC_D ATA

LED_PWM

B+

R9

47K_0402_5%

D1 @ESD@

4

5

6

SC300001400

1

D3 RB751V-40 SOD-323

1

2

4

Vbus

6

2

USB20_N11_R

3

2

GND

INT_MIC_C LK

1

close to LVDS conn.

PCH_PWM <19>

From PCH

2

3

Touch Panel

D5

@ESD@

D5

+5VS

USB20_P8_R

@ESD@

6

I/O4

5

VDD

4

I/O3

AZC099-04S.R7G_SOT23-6

USB20_N8_R

3

I/O2

2

GND

BKOFF#

1

I/O1

close to JTOUCH

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

LVDS

LAB412P

E

13 41Wednesday, January 22, 2014

0.2

of

A

B

C

D

E

CRT CONNECTOR

1

2.2P_0402_50V8C

VIDEO1

VIDEO2

VIDEO3

BYP

CRT_R_L

CRT_G_L

CRT_B_L

8

C15 0.22U_0402_16V7K

3

4

5

9

12

14

16

CRT@

1

VSYNC_R

HSYNC_R

2

CRT_R_L

CRT_G_L

CRT_B_L

USE HDMI POWER

R153

4.7K_0402_5%

CRT@

R62

CRT@

1

2

22_0402_5%

R63

22_0402_5%

CRT@

1

2

22_0402_5%

+HDMI_5V_OUT

2

R159

4.7K_0402_5%

CRT@

1

VSYNC

HSYNC

CRT_DDC_DAT

CRT_DDC_CLK

CRT_R_L

CRT_DDC_DAT

CRT_G_L

HSYNC

CRT_B_L

VSYNC

CRT_DDC_CLK

T65 PAD

T66 PAD

JCRT

6

11

1

7

12

2

8

16

G

13

17

G

3

9

14

4

10

15

5

J-L_TNBNRACZZ013015

@

2

3

1

2.2P_0402_50V8C

CRT@EMI@

CRT@

C241

2

1

2

2.2P_0402_50V8C

1

2

7

10

11

13

15

6

CRT@

1

C243

C242

2

2.2P_0402_50V8C

U49

VCC_SYNC

VCC_VIDEO

VCC_DDC

DDC_IN1

DDC_IN2

SYNC_IN1

SYNC_IN2

GND

TPD7S019-15DBQR_SSOP16

CRT@

1

2

DDC_OUT1

DDC_OUT2

SYNC_OUT1

SYNC_OUT2

L4 NBQ100505T-800Y_0402

UMA_CRT_R<19>

UMA_CRT_G<19>

UMA_CRT_B<19>

2

3

CRT@

+HDMI_5V_OUT

CRT@

R138

1

2

@

C250

0.1U_0402_10V7K

1

R140

R139

1

150_0402_1%

2

CRT@

1

150_0402_1%

2

UMA_CRT_VSYNC<19>

UMA_CRT_HSYNC<19>

UMA_CRT_DATA<19>

UMA_CRT_CLK<19>

CRT@

1

C238

2

+HDMI_5V_OUT

L4 NBQ100505T-800Y_0402

L6 NBQ100505T-800Y_0402

L5 NBQ100505T-800Y_0402

CRT@

1

C240

C239

2.2P_0402_50V8C

+3VS

2

2.2P_0402_50V8C

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

CRT

LAB412P

E

14 41Wednesday, January 22, 2014

of

4

0.2

A

B

C

D

E

RPY1

G

2

3

S

1

UMA_HDMI_CLK

8

UMA_HDMI_DATA

7

HDMI_SCLK

6

HDMI_SDATA

5

+3VS

G

2

3

S

BSS138 1N SOT23-3

1

D

QY2

2

BSS138 1N SOT23-3

1

D

QY1

HDMI_SCLK

HDMI_SDATA

HDMI_TXC-

HDMI_TXC+

HDMI_TXD0-

HDMI_TXD0+

HDMI_TXD1-

HDMI_TXD1+

LY1

EMI@

LY1

EMI@

4

1

DLW21HN900HQ2L_4P

LY2

EMI@

LY2

EMI@

4

1

DLW21HN900HQ2L_4P

LY3

EMI@

LY3

EMI@

4

1

DLW21HN900HQ2L_4P

L

LL

L

HH

H

XZ

+HDMI_5V_OUT

HDMI_HPD_U

1

5

UY1

P

2

OE#

A

Y

G

74AHCT1G125GW_SOT353-5

3

HDMI_HPD

3

2

3

2

3

2

HDMI_HPD

4

RY1

1

1K_0402_5%

2

RY3

2.2K_0402_5%

2

1

RY2

100K_0402_5%

+3VS

HDMI_HPD <19,21>

HDMI_HPD_C

2

CY4

0.1U_0402_10V7K

1

+3VS

+HDMI_5V_OUT

1

2

3

4

2.2K_0804_8P4R_5%

UMA_HDMI_CLK<19>

UMA_HDMI_DATA<19>

2

UMA_HDMI_CLK-<19>

UMA_HDMI_CLK+<19>

UMA_HDMI_TX0-<19>

UMA_HDMI_TX0+<19>

3

UMA_HDMI_TX1-<19>

UMA_HDMI_TX1+<19>

UMA_HDMI_CLK

UMA_HDMI_DATA

CY2 0.1U_0402_10V7K

CY1 0.1U_0402_10V7K

CY5 0.1U_0402_10V7K

CY3 0.1U_0402_10V7K

CY7 0.1U_0402_10V7K

CY6 0.1U_0402_10V7K

HDMI POWER CIRCUIT

VIN = 5V, IOUT = 0.5A , RDS(ON) TYP=95m ; MAX=115m Current Limit: TYP=0.8A ; MAX=1A

+HDMI_5V_OUT

CY18

0.1U_0402_10V7K

1

2

UY2

1

IN

OUT

2

GND

3

EN

FLG

AP2151DWG-7_SOT25-5

SA00006H000

5

4

+5VS

HDMI Connector

JHDMI

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

ACON_HMR2U-AK120C

@

GND

20

21

22

23

+HDMI_5V_OUT

HDMI_HPD_C

HDMI_SDATA

HDMI_SCLK

HDMI_R_CK-

HDMI_R_CK+

HDMI_R_D0-

HDMI_R_D0+

HDMI_R_D1-

HDMI_R_D1+

HDMI_R_D2-

HDMI_R_D2+

1

2

3

RPY1

OE# A Y

680 +-5% 8P4R

+5VS

680 +-5% 8P4R

5

6

7

8

RPY3

680 +-5% 8P4R

5

6

7

8

RPY4

4

3

2

1

4

3

2

1

QY4

2

G

D

1

D

S

3

2N7002KW_SOT323-3

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

HDMI Conn.

LAB412P

E

15 41Wednesday, January 22, 2014

of

4

0.2

HDMI_R_D0-

HDMI_R_D0+

LY4

EMI@

LY4

UMA_HDMI_TX2-<19>

UMA_HDMI_TX2+<19>

HDMI Royalty

4

HDMI W/O Logo: RO0000001HM HDMI W/Logo: RO0000002HM HDMI W/Logo + HDCP: RO0000003HM

please manually load this virtual material to 45@ BOM

A

RO0000003HM

HDMI W/Logo + HDCP

1

HDMI45@

2

CY9 0.1U_0402_10V7K

CY8 0.1U_0402_10V7K

ZZZ

HDMI_TXD2-

HDMI_TXD2+

B

EMI@

4

1

DLW21HN900HQ2L_4P

3

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

2013/12/17 2014/12/17

HDMI_R_CK-

HDMI_R_CK+

HDMI_R_D1-

HDMI_R_D1+

HDMI_R_D2-

HDMI_R_D2+

Compal Secret Data

Deciphered Date

5

CMOS Setting, near DDR Door

RH23

+RTCVCC

D

RH23

20K_0402_5%

iME Setting.

RH24

20K_0402_5%

Integrated S US 1.05V VRM Enabl e

PCH_INTVRMEN

+RTCVCC

1

RH12

C

B

1

RH33

+3VS

@

1

RH36 1K_0402_5%

AZ_BITCLK_HD<29>

AZ_SYNC_HD<29>

AZ_RST_HD#<29>

AZ_SDOUT_HD<29>

HDA_SDO

ME debug mode, this signal has a weak internal pull down Low = Disable (default)

*

High = Enable (flash descriptor security overide)

HDA_SYNC

This signal has a weak internal pull down

*

H=>On Die PLL is supplied by 1.5V L=>On Die PLL is supplied by 1.8V Need to pull high for Chief River Mobile platform

AZ_SYNC_R

1M_0402_5%

PCH_RTCRST#

1

2

PCH_SRTCRST#

1

2

High - Enable Internal VRs (must be always pulled high)

SM_INTRUDER#

2

1M_0402_5%

330K_0402_5%

PCH_INTVRMEN

2

AZ_BITCLK_HD

2

1

PCH_SPKR

+5VS

G

3

S

BSS138_NL_SOT23-3

2

RH56

CH4

1U_0402_6.3V6K

CH5

1U_0402_6.3V6K

RPH2

1

2

3

4

33_8P4R_5%

+3VALW_PCH

2

QH1

1

D

JCMOS @

1

2

1

2

JME @

1

2

1

2

PCH_SPKR High = Enabled "No Reboot Mode"

*

Low = Disabled (Default)

AZ_BITCLK

8

AZ_SYNC_R

7

AZ_RST#

6

AZ_SDOUT

5

2

RH55

1K_0402_5%

1

AZ_SYNC

RTC schematic for non-chargeable/main battery

A

CH8

0.1U_0402_10V7K

+RTCVCC

1

2

+RTC_R

2

RH4 1K_0402_5%

5

1

DH7 RB751V-40 SOD-323

1

DH8 RB751V-40 SOD-323

1

2

+RTCBATT_R

2

@

Placement near to YH1

+3VL

RH1 1K_0402_5%@

SUYIN_060003HA002G202ZL

1

2

JRTC

@

4

32.768KHZ_12.5P_9H03200031

Change Net name due to this function is high active

PWRME_CTRL<30>

+RTCBATT

1

+

-

2

4

1

2

CH2 15P_0402_50V8J

2

YH1

1

2

CH3 15P_0402_50V8J

PCH_SPKR<29>

AZ_SDIN0_HD<29>

1

RH25 0_0402_5%

SPI ROM for BIOS & ME & Win8 (8MByte)

PCH_SPIDO

1

@

RH68

0_0402_5%

3

UH1A

@

1

RH2

2

10M_0402_5%

2

T70 PAD

T67 PAD

T68 PAD

T69 PAD

PCH_SPICS0#

PCH_SPI0_DO

2

+3VALW_PCH

PCH_RTCX1

PCH_RTCX2

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

AZ_BITCLK

AZ_SYNC

PCH_SPKR

AZ_RST#

AZ_SDIN0_HD

AZ_SDOUT

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_SPICLK

PCH_SPICS0#

PCH_SPIDI

PCH_SPIDO

A20

C20

D20

G22

K22

C17

N34

L34

T10

K34

E34

G34

C34

A34

A36

C36

N32

J3

H7

K5

H1

T3

Y14

T1

V4

U3

PANTHER-POINT_FCBGA989

HM76R1@

UH3

1

/CS

2

DO(IO1)

3

/WP(IO2)

4

GND

W25Q64FVSSIQ_SO8

INT.PH 20K

RTCX1

INT.PH 20K INT.PH 20K

RTCX2

INT.PH 20K

RTCRST#

SRTCRST#

INTRUDER #

INTVRMEN

HDA_BCLK

INT.PD 20K

HDA_SYNC

INT.PD 20K

SPKR

HDA_RST#

INT.PD 20K

HDA_SDIN0

INT.PD 20K

HDA_SDIN1

INT.PD 20K

HDA_SDIN2

INT.PD 20K

HDA_SDIN3

INT.PD 20K

HDA_SDO

HDA_DOCK_EN# / GPIO33

HDA_DOCK_RST# / GPIO13

INT.PD 20K

JTAG_TCK

INT.PH 20K

JTAG_TMS

INT.PH 20K

JTAG_TDI

JTAG_TDO

SPI_CLK

SPI_CS0#

SPI_CS1#

SPI_MOSI

SPI_MISO

VCC

/HOLD(IO3)

CLK

DI(IO0)

INT.PD 20K

INT.PH 20K

+3VALW_PCH

8

7

PCH_SPI0_CLK

6

PCH_SPI0_DI

5

JTAG

INT.PH 20K INT.PH 20K

RTC

IHDA

SPI

INT.PH 20K

Please place UH3 close to UH1 PCH, Please place RH66, RH67, RH68 near UH3

LPC

FWH4 / LFRAME#

LDRQ1# / GPIO23

SATA 6G

SATA

SATA3RCOMPO

SATA0GP / GPIO21

SATA1GP / GPIO19

RH66 0_0402_5%

RH67 0_0402_5%

2

FWH0 / LAD0

FWH1 / LAD1

FWH2 / LAD2

FWH3 / LAD3

LDRQ0#

SERIRQ

SATA0RXN

SATA0RXP

SATA0TXN

SATA0TXP

SATA1RXN

SATA1RXP

SATA1TXN

SATA1TXP

SATA2RXN

SATA2RXP

SATA2TXN

SATA2TXP

SATA3RXN

SATA3RXP

SATA3TXN

SATA3TXP

SATA4RXN

SATA4RXP

SATA4TXN

SATA4TXP

SATA5RXN

SATA5RXP

SATA5TXN

SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3COMPI

SATA3RBIAS

SATALED#

1

2

@

1

2

@

8MB ROM P/N: SA000039A30

LPC_AD0

C38

LPC_AD1

A38

LPC_AD2

B37

LPC_AD3

C37

LPC_FRAME#

D36

E36

K36

SERIRQ

V5

SATA_PRX_C_DTX_N0

AM3

SATA_PRX_C_DTX_P0

AM1

SATA_PTX_DRX_N0

AP7

SATA_PTX_DRX_P0

AP5

AM10

AM8

AP11

AP10

SATA_PRX_C_DTX_N2

AD7

SATA_PRX_C_DTX_P2

AD5

SATA_PTX_DRX_N2

AH5

SATA_PTX_DRX_P2

AH4

AB8

AB10

AF3

AF1

Y7

Y5

AD3

AD1

Y3

Y1

AB3

AB1

Y11

SATAICOMP

Y10

AB12

SATA3_COMP

AB13

RBIAS_SATA3

AH1

SATA_LED#

P3

PCH_GPIO21

V14

PCH_GPIO19

P1

PCH_SPICLK

PCH_SPIDI

RH43 37.4_0402_1%

RH48 49.9_0402_1%

RH41 750_0402_1%

SA00006MK00

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

2

1

LPC_AD0 <26,30>

LPC_AD1 <26,30>

LPC_AD2 <26,30>

LPC_AD3 <26,30>

LPC_FRAME# <26,30>

SERIRQ <26,30>

SATA_PRX_C_DTX_N0 <25>

SATA_PRX_C_DTX_P0 <25>

SATA_PTX_DRX_N0 <25>

SATA_PTX_DRX_P0 <25>

SATA_PRX_C_DTX_N2 <25>

SATA_PRX_C_DTX_P2 <25>

SATA_PTX_DRX_N2 <25>

SATA_PTX_DRX_P2 <25>

1

2

+1.05VS_PCH

1

2

+1.05VS_PCH

1

2

PCH_GPIO19 <20>

BOOT BIOS Strap Bit 0

EC_SDIO<30>

EC_CS0#<30>

EC_SCK<30>

EC_SDI<30>

HDD

ODD

SERIRQ

SATA_LED#

PCH_GPIO19

PCH_GPIO21

RPH9

1

2

3

4

33_8P4R_5%

8

7

6

5

RPH1

1

2

3

4

10K_0804_8P4R_5%

PCH_SPI0_DO

PCH_SPICS0#

PCH_SPI0_CLK

PCH_SPI0_DI

For fix code Please place RPH9 near UH3

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

PCH_HDA/JTAG/SATA/SPI/LPC

LAB412P

1

16 41Wednesday, January 22, 2014

D

+3VS

8

7

6

5

C

B

A

0.2

of

LAN

WLAN

D

Card Reader

+3VS

C

+3VALW_PCH

B

+3VALW_PCH

A

5

PCIE_PRX_C_LANTX_N1<27>

PCIE_PRX_C_LANTX_P1<27>

PCIE_PTX_C_LANRX_N1<27>

PCIE_PTX_C_LANRX_P1<27>

PCIE_PRX_WLANTX_N 2<25>

PCIE_PRX_WLANTX_P2<25>

PCIE_PTX_C_WLANR X_N2<25>

PCIE_PTX_C_WLANR X_P2<25>

PCIE_PRX_C_CRTX_N4<31>

PCIE_PRX_C_CRTX_P4<31>

PCIE_PTX_C_CRRX_N4<31>

PCIE_PTX_C_CRRX_P4<31>

RPH14

1

8

2

7

3

6

4

5

10K_0804_8P4R_5%

RH105 10K_0402_5%

1

2

RPH6

1

8

2

7

3

6

4

5

10K_0804_8P4R_5%

LVDS@

1

RH119 10K_0402_5%

RH276 10K_0402_5%

2

1

2

IEDP@

LVDS_SEL

Channel

HL

Single (Default)

5

CH13 0.1U_0402_10V7K

CH11 0.1U_0402_10V7K

CH14 0.1U_0402_10V7K

CH17 0.1U_0402_10V7K

CH15 0.1U_0402_10V7K

CH12 0.1U_0402_10V7K

Intel Spec: PCIECLK_RQ0# is suspend well, but we pull high to +3V S for LAN en/disable func tion

CLKREQ_LAN#

CLKREQ_WLAN#

PCH_GPIO67

CLK_14M_PCH

LAN

WLAN

CLKREQ_CR#

Card Reader

PCH_GPIO28

PASSWORD_CLEAR#

PCH_SMBALERT#

LAN_EN

PANEL_SEL

Dual

1

2

1

2

1

2

1

2

1

2

1

2

CLK_LAN#<27>

CLK_LAN<27>

CLKREQ_LAN#<27>

CLK_WLAN#<25>

CLK_WLAN<25>

CLKREQ_WLAN#<25>

CLK_CR#<31>

CLK_CR<31>

CLKREQ_CR#<31>

PCH_GPIO28 <21>

Note: place in DDR area

PASSWORD_CLEAR#

1

JPW

@

2

LVDS_SEL<20>

PANEL_SEL

Channel LVDS

PCIE_PRX_C_LANTX_N1

PCIE_PRX_C_LANTX_P1

PCIE_PTX_LANRX_N1

PCIE_PTX_LANRX_P1

PCIE_PRX_WLANTX_N 2

PCIE_PRX_WLANTX_P2

PCIE_PTX_WLANRX_N 2

PCIE_PTX_WLANRX_P2

PCIE_PRX_C_CRTX_N4

PCIE_PRX_C_CRTX_P4

PCIE_PTX_CRRX_N4

PCIE_PTX_CRRX_P4

CLK_LAN#

CLK_LAN

CLKREQ_LAN#

CLK_WLAN#

CLK_WLAN

CLKREQ_WLAN#

CLK_CR#

CLK_CR

CLKREQ_CR#

LVDS_SEL

PANEL_SEL

HL

4

BG34

BJ34

AV32

AU32

BE34

BF34

BB32

AY32

BG36

BJ36

AV34

AU34

BF36

BE36

AY34

BB34

BG37

BH37

AY36

BB36

BJ38

BG38

AU36

AV36

BG40

BJ40

AY40

BB40

BE38

BC38

AW38

AY38

Y40

Y39

AB49

AB47

AA48

AA47

V10

Y37

Y36

Y43

Y45

L12

V45

V46

L14

AB42

AB40

V40

V42

T13

V38

V37

K12

AK14

AK13

4

UH1B

PERN1

PERP1

PETN1

PETP1

PERN2

PERP2

PETN2

PETP2

PERN3

PERP3

PETN3

PETP3

PERN4

PERP4

PETN4

PETP4

PERN5

PERP5

PETN5

PETP5

PERN6

PERP6

PETN6

PETP6

PERN7

PERP7

PETN7

PETP7

PERN8

PERP8

PETN8

PETP8

CLKOUT_PCIE0N

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GPIO73

CLKOUT_PCIE1N

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GPIO18

CLKOUT_PCIE2N

CLKOUT_PCIE2P

PCIECLKRQ2# / GPIO20

CLKOUT_PCIE3N

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

CLKOUT_PCIE4N

CLKOUT_PCIE4P

PCIECLKRQ4# / GPIO26

CLKOUT_PCIE5N

CLKOUT_PCIE5P

PCIECLKRQ5# / GPIO44

CLKOUT_PEG_B_N

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

CLKOUT_PCIE6N

CLKOUT_PCIE6P

PCIECLKRQ6# / GPIO45

CLKOUT_PCIE7N

CLKOUT_PCIE7P

PCIECLKRQ7# / GPIO46

CLKOUT_ITPXDP_N

CLKOUT_ITPXDP_P

PANTHER-POINT_FCBGA989HM76R1@

EDP

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

Link

PEG_A_CLKRQ# / GPIO47

CLOCKS

INT. PH 20K

CLKIN_PCILOOPBACK

INT. PD 20K

CLKOUTFLEX0 / GPIO64

INT. PH 20K

INT. PD 20K

CLKOUTFLEX1 / GPIO65

INT. PD 20K

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

PCH_GPIO67 (DGPU_PRSNT#)

PCH_GPIO67

M/B SKU UMA

3

PCH_SMBALERT#

E12

PCH_SMBCLK

H14

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK / GPIO58

SML1DATA / GPIO75

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_PEG_A_N

CLKOUT_PEG_A_P

CLKOUT_DMI_N

CLKOUT_DMI_P

CLKOUT_DP_N

CLKOUT_DP_P

CLKIN_DMI_N

CLKIN_DMI_P

CLKIN_GND1_N

CLKIN_GND1_P

CLKIN_DOT_96N

CLKIN_DOT_96P

CLKIN_SATA_N

CLKIN_SATA_P

REFCLK14IN

XTAL25_ IN

XTAL25_ OUT

XCLK_RC OMP

PCH_SMBDATA

C9

DRAMRST_CNTRL_PCH

A12

PCH_SMLCLK0

C8

PCH_SMLDATA0

G12

LAN_EN

C13

PCH_SMLCLK1

E14

PCH_SMLDATA1

M16

M7

Control Link only for support Intel IAMT.

T11

P10

PCH_GPIO47

M10

AB37

AB38

AV22

AU22

AM12

AM13

PCH_CLK_DMI#

BF18

PCH_CLK_DMI

BE18

CLKIN_GND1#

BJ30

CLKIN_GND1

BG30

CLK_DOT#

G24

CLK_DOT

E24

CLK_SATA#

AK7

CLK_SATA

AK5

CLK_14M_PCH

K45

CLK_PCILOOP

H45

PCH_X1

PCH_X2

V47

V49

XCLK_RCOMP

Y47

CLK_FLEX0

K43

CLK_FLEX1

F47

CLK_FLEX2

H47

PCH_GPIO67

K49

DRAMRST_CNTRL_PCH <7,9>

LAN_EN <27>

CLK_CPU_DMI# <5>

CLK_CPU_DMI <5>

CLK_CPU_EDP# <5>

CLK_CPU_EDP <5>

CLK_PCILOOP <20>

1

2

RH115 90.9_0402_1%

T72 PAD

T74 PAD

T73 PAD

From Clock Gen.

+1.05VS_VCCDIFFCLKN

HL

DIS/OPT

Security Classification

Issued Dat e

THIS SHEET OF ENG INEERING DRAWING I S THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY O R DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Compal common design SW request to add DGPU_Present on this GPIO67

Compal Secret Data

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

2

+3VALW_PCH

120 MHz for eDP

2

RPH5

PCH_SMBDATA

4

5

PCH_SMBCLK

3

6

PCH_SMLDATA1

2

7

PCH_SMLCLK1

1

8

2.2K_0804_8P4R_5%

27P_0402_50V8J

DRAMRST_CNTRL_PCH

PCH_SMLCLK0

PCH_SMLDATA0

PCH_GPIO47

PCH_CLK_DMI

PCH_CLK_DMI#

CLKIN_GND1#

CLKIN_GND1

CLK_DOT#

CLK_DOT

CLK_SATA

CLK_SATA#

CLK_PCILOOP

CH26

1

RH102 4.7 K_0402_5%

5

QH3B

3

2

2N7002DW-T/R7_SOT363-6

QH3A

6

1

2N7002DW-T/R7_SOT363-6

5

QH4B

3

2

QH4A

6

PCH_X1

1

2

Title

Size Document Nu mber Rev

Custom

Date: Sheet

2N7002DW-T/R7_SOT363-6

1

2N7002DW-T/R7_SOT363-6

RH76 1K_0402_5%

1

RH73 2.2K_0402_5%

RH77 2.2K_0402_5%

RH106 10K_0402_5%

1

RPH3

1

2

3

4

10K_0804_8P4R_5%

RPH4

1

2

3

4

10K_0804_8P4R_5%

@EMI@

1

2

RH70 10_0402_5%

2

RH117 1M_0402_5%

YH2

25MHZ_20PF_7V25000016

1

GND

2

Compal Electronics, Inc.

PCH_PCI-E/SMBUS/CLK

LAB412P

RH103 4.7 K_0402_5%

4

+3VS

4

2

1

2

1

2

8

7

6

5

8

7

6

5

@EMI@

1

2

CH9 10P_0402_50 V8J

1

PCH_X2

3

4

1

PM_SMBDATA <11,12,31>

PM_SMBCLK <11,12,31 >

EC_SMB_DA2 <30>

EC_SMB_CK2 <30>

+3VALW_PCH

1

CH27

27P_0402_50V8J

2

of

17 41Wednesday, January 22, 2014

of

17 41Wednesday, January 22, 2014

of

17 41Wednesday, January 22, 2014

+3VS

D

C

B

A

0.2

5

+3VALW_PCH

RPH7

1

D

C

SUSACK#_R

Stuff R137 if EC does not want to involve in the handshake mechanism for the DeepSX state entry and exit

B

2

3

4

10K_0804_8P4R_5%

RPH17

1

2

3

4

10K_0804_8P4R_5%

PM_PWROK

2

CC26

100P_0402_50V8J

@ESD@

1

8

7

6

5

8

7

6

5

2

@

RH282 0_0402_5%

PCH_SUSPWRDN#_R

RI#

PCH_LOW_BAT#

EC_SWI#

PM_PWROK

PCH_GPIO32

PCH_GPIO37

PCH_RSMRST#

2

1

PCH_SUSPWRDN#_R

1

PCH_GPIO37 <21>

XDP_DBRESET#

CC27

100P_0402_50V8J

@ESD@

4

DMI_CTX_PRX_N0<6>

DMI_CTX_PRX_N1<6>

DMI_CTX_PRX_N2<6>

DMI_CTX_PRX_N3<6>

DMI_CTX_PRX_P0<6>

DMI_CTX_PRX_P1<6>

DMI_CTX_PRX_P2<6>

DMI_CTX_PRX_P3<6>

DMI_PTX_CRX_N0<6>

DMI_PTX_CRX_N1<6>

DMI_PTX_CRX_N2<6>

DMI_PTX_CRX_N3<6>

DMI_PTX_CRX_P0<6>

DMI_PTX_CRX_P1<6>

DMI_PTX_CRX_P2<6>

DMI_PTX_CRX_P3<6>

1

+1.05VS_PCH

Reserve this signal to EC by SW demand 2011/10/18a

SUSACK#<30>

+3VS

VGATE<30,40>

DRAMPWROK<5>

PCH_RSMRST#<30>

PCH_SUSPWRDN#<30>

PBTN_OUT#<30>

1

+3VALW_PCH

ACIN<30,35>

Reserve this signal to EC by SW demand 2011/10/18a

2

RH161 330K_0402_5%

DH2

1

RB751V-40 SOD-323

2

RH126 49.9_0402_1%

1

2

RH127 750_0402_1%

1

@

RH133 0_0402_5%

1

RH47 1K_0402_5%

2

PM_PWROK<30>

1

2

@

RH132 0_0402_5%

2

DMI_COMP

RBIAS_CPY

SUSACK#_R

2

XDP_DBRESET#

PM_PWROK

PCH_RSMRST#

PCH_SUSPWRDN#_R

PCH_ACIN

PCH_LOW_BAT#

RI#

UH1C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

INT.PH 20K

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

H20

E10

A10

INT.PH 20K

PWRBTN#

ACPRESENT / GPIO31

BATLOW# / GPIO72

RI#

PANTHER-POINT_FCBGA989

HM76R1@

3

BJ14

FDI_RXN0

AY14

FDI_RXN1

BE14

FDI_RXN2

BH13

FDI_RXN3

BC12

FDI_RXN4

BJ12

FDI_RXN5

BG10

FDI_RXN6

BG9

FDI_RXN7

BG14

FDI_RXP0

BB14

FDI_RXP1

BF14

FDI_RXP2

BG13

FDI_RXP3

BE12

FDI_RXP4

BG12

FDI_RXP5

BJ10

FDI_RXP6

DMI

FDI

DMI

FDI

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Management

INT.PD 20K

INT.PH 20K

SLP_LAN# / GPIO29

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

BH9

AV12

AW16

BC10

AV14

BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

DSWVREN

PCH_DPWROK

EC_SWI#

PCH_GPIO32

SUS_STAT#

PM_SLP_A#

PM_SLP_SUS#

FDI_CTX_PRX_N0 <6>

FDI_CTX_PRX_N1 <6>

FDI_CTX_PRX_N2 <6>

FDI_CTX_PRX_N3 <6>

FDI_CTX_PRX_N4 <6>

FDI_CTX_PRX_N5 <6>

FDI_CTX_PRX_N6 <6>

FDI_CTX_PRX_N7 <6>

FDI_CTX_PRX_P0 <6>

FDI_CTX_PRX_P1 <6>

FDI_CTX_PRX_P2 <6>

FDI_CTX_PRX_P3 <6>

FDI_CTX_PRX_P4 <6>

FDI_CTX_PRX_P5 <6>

FDI_CTX_PRX_P6 <6>

FDI_CTX_PRX_P7 <6>

FDI_INT <6>

FDI_FSYNC0 <6>

FDI_FSYNC1 <6>

FDI_LSYNC0 <6>

FDI_LSYNC1 <6>

EC_SWI# <27,30>

T76 PAD

32.768 KHz

CLK_NGFF <25>

PM_SLP_S5# <30>

PM_SLP_S4# <30>

PM_SLP_S3# <30>

T77 PAD

T78 PAD

H_PM_SYNC <5>

2

PCH_DPWROK

1

RH128 0_0402_5%

1

2

@

D

PCH_RSMRST#

Not support DeepSX state

+RTCVCC

DSWVREN

RH150 330K_0402_5%

1

2

DSWVREN must be always pulled high to +RTCVCC

DSWVREN - Internal Deep Sleep 1.05V regulator H Enable

*

L Disable

Follow EC check list demand, but don't implement CLKRUN# this fuction

C

B

DH5

PM_PWROK

POK<30,36>

A

5

4

DH5

2

RB751V-40 SOD-323

DH6

1

RB751V-40 SOD-323

1

2

PCH_RSMRST#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

PCH_DMI/FDI/PM

LAB412P

1

18 41Wednesday, January 22, 2014

of

A

0.2

5

CRT@

2

CRT@

8

7

6

5

2

LCTL_CLK

LCTL_DATA

LCD_EDID_CLK

LCD_EDID_DATA

1

2

EC_ENBKL

UMA_CRT_DATA

UMA_CRT_CLK

UMA_CRT_B

UMA_CRT_G

UMA_CRT_R

LCD_EDID_CLK<13>

LCD_EDID_DATA<13>

UMA_CRT_CLK<14>

UMA_CRT_DATA<14>

UMA_CRT_HSYNC<14>

UMA_CRT_VSYNC<14>

1

RH125 100K_0402_5%

D

C

B

+3VS

1

2

3

4

1

RH154 150_0402_1%

RH156 150_0402_1%

1

RH152 150_0402_1%

RPH8

2.2K_0804_8P4R_5%

2

RH142 2.2K_0402_5%

2

RH144 2.2K_0402_5%

1

4

EC_ENBKL<13,30>

LCD_ENVDD<13>

PCH_PWM<13>

1

2

RH143 2.37K_0402_1%

LCD_TXCLK-<13>

LCD_TXCLK+<13>

LCD_TXOUT0-<13>

LCD_TXOUT1-<13>

LCD_TXOUT2-<13>

LCD_TXOUT0+<13>

LCD_TXOUT1+<13>

LCD_TXOUT2+<13>

UMA_CRT_B<14>

UMA_CRT_G<14>

UMA_CRT_R<14>

2

RH138 1K_0402_0.5%

RH138

1K_0402_5%

NOCRT@

EC_ENBKL

LCD_ENVDD

PCH_PWM

LCD_EDID_CLK

LCD_EDID_DATA

LCTL_CLK

LCTL_DATA

LVDS_IBG

UMA_CRT_B

UMA_CRT_G

UMA_CRT_R

UMA_CRT_CLK

UMA_CRT_DATA

CRT@

1

CRT_IREF

UH1D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

INT.PD 20K

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

PANTHER-POINT_FCBGA989

HM76R1@

3

SDVO_INTN

SDVO_INTP

DDPB_HPD

DDPB_0N

DDPB_0P

DDPB_1N

DDPB_1P

DDPB_2N

DDPB_2P

DDPB_3N

DDPB_3P

DDPC_HPD

DDPC_0N

DDPC_0P

DDPC_1N

DDPC_1P

DDPC_2N

DDPC_2P

DDPC_3N

DDPC_3P

DDPD_HPD

DDPD_0N

DDPD_0P

DDPD_1N

DDPD_1P

DDPD_2N

DDPD_2P

DDPD_3N

DDPD_3P

AP43

AP45

AM42

AM40

AP39

AP40

P38

M39

AT49

AT47

AT40

AV42

AV40

AV45

AV46

AU48

AU47

AV47

AV49

P46

P42

AP47

AP49

AT38

AY47

AY49

AY43

AY45

BA47

BA48

BB47

BB49

M43

M36

AT45

AT43

BH41

BB43

BB45

BF44

BE44

BF42

BE42

BJ42

BG42

INT.PD 50 INT.PD 50

LVDS

CRT

SDVO_TVCLKINN

INT.PD 50 INT.PD 50

SDVO_TVCLKINP

SDVO_STALLN

SDVO_STALLP

INT.PD 50 INT.PD 50

SDVO_CTRLCLK

SDVO_CTRLDATA

INT.PD 20K

DDPB_AUXN

DDPB_AUXP

DDPC_CTRLCLK

DDPC_CTRLDATA

INT.PD 20K

DDPC_AUXN

DDPC_AUXP

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

INT.PD 20K

DDPD_AUXN

DDPD_AUXP

UMA_HDMI_CLK <15>

UMA_HDMI_DATA <15>

HDMI_HPD

2

RH141 100K_0402_5%

2

RH255 100K_0402_5%

HDMI_HPD <15,21>

UMA_HDMI_TX2- <15>

UMA_HDMI_TX2+ <15>

UMA_HDMI_TX1- <15>

UMA_HDMI_TX1+ <15>

UMA_HDMI_TX0- <15>

UMA_HDMI_TX0+ <15>

UMA_HDMI_CLK- <15>

UMA_HDMI_CLK+ <15>

1

2

HDMI

1

D

C

B

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PCH_CRT/LVDS/HDMI

LAB412P

1

of

19 41Wednesday, January 22, 2014

of

19 41Wednesday, January 22, 2014

of

19 41Wednesday, January 22, 2014

A

0.2

5

D

+3VS

C

100K_0402_5%

B

1

CH115

2

RH173

CLK_PCI_EC

@RF@

22P_0402_50V8J

RPH12

1

8

2

7

3

6

4

5

8.2K_0804_8P4R_5%

RPH13

1

8

2

7

3

6

4

5

8.2K_0804_8P4R_5%

RPH18

1

8

2

7

3

6

4

5

8.2K_0804_8P4R_5%

PLT_RST#

2

1

PCH_GPIO52

PCH_GPIO2

PCI_PIRQA#

PCI_PIRQB#

PCI_PIRQC#

CLK_PCI_EC<30>

CLK_PCILOOP<17>

CLK_PCI_TPM_R<26>

PCH_GPIO51

ODD_DA#

PCI_PIRQD#

PCH_GPIO4

PCH_GPIO5

PCH_GPIO50

USB-Right Front (USB3.0 port)

U3RXDN1<28>

U3RXDP1<28>

U3TXDN1<28>

U3TXDP1<28>

PCH_GPIO54<21>

ODD_DA#<25>

PLT_RST#<25,26,27,30,31,5>

CLK_PCI_EC

T81 PAD

1

EMI@

1

@

T80 PAD

TPM@

U3RXDN1

U3RXDP1

U3TXDN1

U3TXDP1

RH16722_0402_5%

2

RH1660_0402_5%

RH1680_0402_5%

4

PCI_PIRQA#

PCI_PIRQB#

PCI_PIRQC#

PCI_PIRQD#

PCH_GPIO50

PCH_GPIO52

PCH_GPIO54

PCH_GPIO51

PCH_GPIO2

ODD_DA#

PCH_GPIO4

PCH_GPIO5

PCI_PME#

PLT_RST#

CLK_EC_R

CLK_PCH

CLK_PCI_DDR

CLK_PCI_TPM

UH1E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

USB3Rn1

BC30

USB3Rn2

BE32

USB3Rn3

BJ32

USB3Rn4

BC28

USB3Rp1

BE30

USB3Rp2

BF32

USB3Rp3

BG32

USB3Rp4

AV26

USB3Tn1

BB26

USB3Tn2

AU28

USB3Tn3

AY30

USB3Tn4

AU26

USB3Tp1

AY26

USB3Tp2

AV28

USB3Tp3

AW30

USB3Tp4

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

INT.PU 20K

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

PANTHER-POINT_FCBGA989

HM76R1@

RSVD

PCI

INT.PU 20K INT.PU 20K INT.PU 20K

INT.PD 20K INT.PD 20K INT.PD 20K INT.PD 20K INT.PD 20K

INT.PD 20K

EHCI 1

EHCI 2

USB

RSVD1

RSVD2

RSVD3

RSVD4

RSVD5

RSVD6

RSVD7

RSVD8

RSVD9

RSVD10

RSVD11

RSVD12

RSVD13

RSVD14

RSVD15

RSVD16

RSVD17

RSVD18

RSVD19

RSVD20

RSVD21

RSVD22

RSVD23

RSVD24

RSVD25

RSVD26

RSVD27

RSVD28

RSVD29

USBP0N

USBP0P

USBP1N

USBP1P

USBP2N

USBP2P

USBP3N

USBP3P

USBP4N

USBP4P

USBP5N

USBP5P

USBP6N

USBP6P

USBP7N

USBP7P

USBP8N

USBP8P

USBP9N

USBP9P

USBP10N

USBP10P

USBP11N

USBP11P

USBP12N

USBP12P

USBP13N

USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59

OC1# / GPIO40

OC2# / GPIO41

OC3# / GPIO42

OC4# / GPIO43

OC5# / GPIO9

OC6# / GPIO10

OC7# / GPIO14

3

AY7

AV7

AU3

BG4

AT10

BC8

AU2

AT4

AT3

AT1

AY3

AT5

AV3

AV1

BB1

BA3

BB5

BB3

BB7

BE8

BD4

BF6

NV_ALE

AV5

AV10

AT8

AY5

BA2

AT12

BF3

USB20_N0

C24

A24

C25

B25

C26

A26

K28

H28

E28

D28

C28

A28

C29

B29

N28

M28

L30

K30

G30

E30

C30

A30

L32

K32

G32

E32

C32

A32

C33

B33

A14

K20

B17

C16

L16

A16

D14

C14

USB20_P0

USB20_N1

USB20_P1

USB20_N2

USB20_P2

USB20_N8

USB20_P8

USB20_N9

USB20_P9

USB20_N11

USB20_P11

USBBIAS

PCH_GPIO59

PCH_GPIO40

PCH_GPIO41

USB_OC#3

USB_OC#4

USB_OC#5_7

USB20_N0 <28>

USB20_P0 <28>

USB20_N1 <28>

USB20_P1 <28>

USB20_N2 <27>

USB20_P2 <27>

USB20_N8 <13>

USB20_P8 <13>

USB20_N9 <25>

USB20_P9 <25>

USB20_N11 <13>

USB20_P11 <13>

RH165 22.6_0402_1%

Within 500 mils

USB-Right Front

USB-Right Rear

USB-Left

Touch Screen

WiMax/BT

Int. Camera

1

2

1

D

Intel Anti-Theft Techonlogy

High=Endabled

NV_ALE

Low=Disable(floating)

NV_ALE

PCH_GPIO40

PCH_GPIO41

LVDS_SEL<17>

EC_SMI#<21,30>

LVDS_SEL

USB_OC#5_7

EC_SMI#

PCH_GPIO59

USB_OC#3

USB_OC#4

1

@

RH164 1K_0402_5%

RPH11

1

2

3

4

10K_0804_8P4R_5%

RPH10

1

2

3

4

10K_0804_8P4R_5%

2

8

7

6

5

8

7

6

5

*

+1.8VS

C

+3VALW_PCH

B

Boot BIOS Strap

ESD@

1

2

A

2

5

ODD_DA#

2

CH105180P_0402_50V8J

PCH_GPIO51

1

RH2931K_0402_5% @

PCH_GPIO19

1

RH2941K_0402_5% @

PCH_GPIO19 <16>

PCH_GPIO51

4

PCH_GPIO19 Boot BIOS Loact ion

0 0 1

0 1

Reserved

0

11

LPC

PCI

SPI

*

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

A16 Swap Override Strap

WL_OFF#

3

Low= A16 swap ove rride Enable High= A16 swap over ride Disable

*

Compal Secret Data

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

PCH_PCI/USB/NAND

LAB412P

1

20 41Wednesday, January 22, 2014

of

A

0.2

5

4

3

2

1

8

7

6

5

1

RH187

2.2K_0402_5%

+3VS

H_SNB_IVB# <5>

D

C

B

RPH16

UH1F

HDMI_HPD<15,19>

D

+3VALW_PCH

EC_LID_OUT#_R

1

+3VS

C

B

2

RH204 1K_0402_5%

1

RH178 200K_0402_5%

+3VS

RPH15

1

2

3

4

10K_0804_8P4R_5%

2

RH200 10K_0402_5%

2

RH199 10K_0402_5%

ODD_DETEC T#

2

PCH_GPIO34

8

PCH_GPIO16

7

EC_SCI#

6

PCH_GPIO49

5

PCH_GPIO17

1

PCH_GPIO27

1

@

Follow Compal ORB and Intel Check list 460603 V1.5

EC_SCI#<30>

EC_SMI#<20,30>

EC_LID_OUT#_R<30>

PCH_GPIO28<17>

ODD_DETEC T#<25>

PCH_GPIO37<18>

HDMI_HPD

EC_SCI#

EC_LID_OUT#_R

PCH_GPIO16

PCH_GPIO17

PCH_GPIO27

PCH_GPIO34

ODD_DETEC T#

PCH_GPIO38

PCH_GPIO49

GPIO28 (pull high on P.17)

On-Die PLL Voltage Regulator H: Enable

*

L: Disable

T7

BMBUSY# / GPIO0

A42

H36

E38

C10

C4

G2

U2

D40

T5

E8

E16

P8

K1

K4

V8

M5

N2

M3

V13

V3

D6

A4

A44

A45

A46

A5

A6

B3

B47

BD1

BD49

BE1

BE49

BF1

BF49

PANTHER-POINT_FCBGA989

INT.PH 20K

TACH1 / GPIO1

INT.PH 20K

TACH2 / GPIO6

INT.PH 20K

TACH3 / GPIO7

INT.PH 20K

GPIO8

LAN_PHY_PWR_CTRL / GPIO12

INT.PD 20K

GPIO15

SATA4GP / GPIO16

INT.PH 20K

TACH0 / GPIO17

SCLOCK / GPIO22

GPIO24

INT.PH 20K

GPIO27

INT.PH 20K

GPIO28

STP_PCI# / GPIO34

GPIO35

SATA2GP / GPIO36

SATA3GP / GPIO37

SLOAD / GPIO38

SDATAOUT0 / GPIO39

SDATAOUT1 / GPIO48

SATA5GP / GPIO49 / TEMP_ALERT#

GPIO57

VSS_NCTF_1

VSS_NCTF_2

VSS_NCTF_3

VSS_NCTF_4

VSS_NCTF_5

VSS_NCTF_6

VSS_NCTF_7

VSS_NCTF_8

VSS_NCTF_9

VSS_NCTF_10

VSS_NCTF_11

VSS_NCTF_12

VSS_NCTF_13

VSS_NCTF_14

HM76R1@

INT.PD 20K

INT.PH 20K

INT.PD 350

GPIO

INT.PH 20K

INT.PD 20K

CPU/MISC

NCTF

TACH4 / GPIO68

TACH5 / GPIO69

TACH6 / GPIO70

TACH7 / GPIO71

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

INIT3_3V#

DF_TVS

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

NC_1

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

VSS_NCTF_23

VSS_NCTF_24

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_29

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_32

C40

B41

C41

A40

P4

AU16

P5

AY11

AY10

T14

AY1

AH8

AK11

AH10

AK10

P37

BG2

BG48

BH3

BH47

BJ4

BJ44

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

F1

F49

ODD_EN

ZP_DETECT#

TOUCH_DETECT

GATEA20

KB_RST#

PCH_THRMTRIP#

NV_CLE

ODD_EN <32>

GATEA20 <30>

KB_RST# <30>

1

2

RH191 390_0402_5%

This signal has weak internal pull-up, can't be pulled low

H_PWRGOOD <5>

H_THERMTRIP# <5>

PCH_GPIO54<20>

GATEA20

KB_RST#

PCH_GPIO38

PCH_GPIO54

ODD_EN

ZP_DETECT#

TOUCH_DETECT

H_THERMTRIP#

100P_0402_50V8J

DMI & FDI Termination Voltage

Set to VCC when HIGH

NV_CLE

Set to VSS when LOW

NV_CLE

2

RH189 1K_0402_5%

RPH16

1

2

3

4

10K_0804_8P4R_5%

2

RH205 10K_0402_5%

NONZP@

2

RH182 10K_0402_5%

ZPODD@

2

RH181 10K_0402_5%

2

RH184 10K_0402_5%

2

CC21

1

@ESD@

+1.8VS

1

2

1

OPTIMUS_EN#

GPIO8

Integrated Clock Chip Enable (Removed) H: Disable L: Enable

*

OPTIMUS_EN#

SKU NonOPT

HL

Optimus

A

Integrated clock enable functionality is achieved by soft-strap The current default is clock enable

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PCH_CPU/GPIO

LAB412P

1

21 41Wednesday, January 22, 2014

of

A

0.2

5

+1.05VS_VCCP

D

C

10U_0603_6.3V6M

B

PJ4

@

1

2

1

2

JUMP_43X79

CH32

10U_0603_6.3V6M

This pin can be left as NC if On-Die VR is enabled (Default)

+1.05VS_PCH

1

CH45

CH43

2

1U_0402_6.3V6K

This pin can be left as NC if On-Die VR is enabled (Default)

1

CH33

2

1U_0402_6.3V6K

1

CH46

2

+3VS

1U_0402_6.3V6K

1

CH31

2

1

CH47

2

1U_0402_6.3V6K

1

CH34

2

1U_0402_6.3V6K

+1.05VS_PCH

1

CH44

1U_0402_6.3V6K

2

1

CH50

0.1U_0402_10V7K

2

+1.05VS_PCH

+VCCP_VCCDMI

+1.05VS_PCH

1

2

1

2

+VCCAFDI_VRM

4

UH1G

1730mA

AA23

VCCCORE[1]

AC23

VCCCORE[2]

AD21

VCCCORE[3]

AD23

VCCCORE[4]

AF21

VCCCORE[5]

AF23

VCCCORE[6]

AG21

VCCCORE[7]

AG23

VCCCORE[8]

AG24

VCCCORE[9]

AG26

VCCCORE[10]

AG27

VCCCORE[11]

AG29

VCCCORE[12]

AJ23

VCCCORE[13]

AJ26

VCCCORE[14]

AJ27

VCCCORE[15]

AJ29

VCCCORE[16]

AJ31

VCCCORE[17]

AN19

VCCIO[28]

BJ22

T82PAD

T83PAD

VCCAPLLEXP

AN16

VCCIO[15]

AN17

VCCIO[16]

AN21

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29

VCC3_3[3]

AP16

VCCVRM[2]

BG6

VccAFDIPLL

AP17

VCCIO[27]

AU20

VCCDMI[2]

PANTHER-POINT_FCBGA989

HM76R1@

3799mA

POWER

VCC CORE

VCCIO

FDI

63mA

VCCADAC

VSSADAC

CRTLVDS

1mA

VCCALVDS

VSSALVDS

VCCTX_LVDS[1]

VCCTX_LVDS[2]

40mA

VCCTX_LVDS[3]

VCCTX_LVDS[4]

VCC3_3[6]

VCC3_3[7]

HVCMOS

VCCVRM[3]

VCCDMI[1]

DMI

75mA

VCCCLKDMI

VCCDFTERM

VCCDFTERM[1]

VCCDFTERM[2]

2mA

VCCDFTERM[3]

VCCDFTERM[4]

DFT / SPI

10mA

VCCSPI

U48

U47

AK36

AK37

AM37

AM38

AP36

AP37

V33

V34

AT16

AT20

AB36

AG16

AG17

AJ16

AJ17

V1

3

+VCCA_DAC

0.01U_0402_25V7K

+VCCA_LVDS

+VCCTX_LVDS

CH38

0.01U_0402_25V7K

+VCCAFDI_VRM

+VCCP_VCCDMI

+1.05VS_VCC_DMI

CH35

0.01U_0402_25V7K

1

CH42

0.1U_0402_10V7K

2

+VCCP_VCCDMI

1

CH49

1U_0402_6.3V6K

2

1

CH51

0.1U_0402_10V7K

2

+3VALW_PCH

1

CH53

1U_0402_6.3V6K

2

0.1U_0402_10V7K

1

CH36

2

1

@

RH208 0_0402_5%

CH39

+3VS

+VCCAFDI_VRM

RH214 0_0402_5%

1

2

@

+1.8VS

1

CH37

10U_0603_6.3V6M

2

1

CH40

22U_0603_6.3V6M

2

+1.05VS_PCH

RH309

+VCCA_DAC_R

1

2

1_0603_1%

+3VS

LH2

2

PBY160808T-181Y-N 0603

RH221 0_0402_5%

1

@

RH213 0_0402_5%

1

CH48

1U_0402_6.3V6K

2

1

+1.5VS

2

@

2

LH1

1

2

PBY160808T-181Y-N 0603

+1.8VS

+1.05VS_VCCP

2

+3VS

PCH Power Rail Table Refer to PCH EDS V2.2

Voltage Rail

V_PROC_IO

V5REF

V5REF_Sus

Vcc3_3

VccADAC

VccADPLLA

VccADPLLB

VccCore

VccDMI

Voltage

1.05

3.3

1.05

1.1

S0 Iccmax Current (A)

0.002

5

0.001

0.178

0.063

0.075

1.73

0.047

1.05VccIO 3.799

1.05VccASW 0.803

3.3VccSPI 0.01

3.3VccDSW3_3 0.001

1.8 0.002VccDFTERM

3.3VccRTC N/A

3.3VccSus3_3

3.3VccSusHDA

0.119

0.01

VccVRM 1.5 0.147

1.05VccCLKDMI

0.075

VccSSC 1.05 0.095

VccDIFFCLKN 1.05 0.05

VccALVDS 3.3

0.001

1.8VccTX_LVDS 0.04

1

D

C

B

+3VALW to +3VALW_PCH

+3VALW

1

2

RH5 0_0805_5%

Id=3A,Rds=130mohm/-2.5V

QH2

AO3413_SOT23

@

D

S

D

S

1

3

G

A

PCH_PWR_EN#<23,32>

PCH_PWR_EN#

5

2

RH3 47K_0402_5%@

1

G

2

1

CH1120.01U_0402_25V7K

CH1110.1U_0402_25V6

@

2

+3VALW_PCH

1

CH1130.1U_0402_10V7K

@

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PCH_POWER-1

LAB412P

1

22 41Wednesday, January 22, 2014

of

A

0.2

D

C

B

+1.05VS_PCH

A

+3VS

1

10UH_LB2012T100MR_20%

+1.05VS_PCH

RH247 0_0402_5%

1

LH5

@

5

2

1

PBY160808T-181Y-N 0603

1

PBY160808T-181Y-N 0603

+1.05VS_VCCDIFFCLKN

2

1

CH81

1U_0402_6.3V6K

2

5

+3VS_VCC_CLKF33

1

CH73

10U_0603_6.3V6M

2

LH7

LH8

1

2

+1.05VS_VCCADPLLB

2

1

CH94

CH93

1U_0402_6.3V6K

2

10U_0603_6.3V6M

Place CH79 near pin AF17

+1.05VS_VCCDIFFCLKN

Place CH86, CH87, CH88 near pin BJ8

CH74

1U_0402_6.3V6K

+1.05VS_VCCADPLLA

1

2

10U_0603_6.3V6M

+1.05VS_VCCP

4.7U_0603_6.3V6K

CH95

+3VALW_PCH

1U_0402_6.3V6K

1

2

+1.05VS_PCH

1U_0402_6.3V6K

+1.05VS_PCH

1U_0402_6.3V6K

0.1U_0402_10V7K

1

CH86

2

+1.05VS_PCH

CH67

1

CH96

1U_0402_6.3V6K

2

CH78

0.1U_0402_10V7K

CH79

1

CH84

2

1

CH88

CH87

0.1U_0402_10V7K

2

4

This pin can be left as NC if On-Die VR is enabled (Default)

1

CH55

0.1U_0402_10V7K

2

+1.05VS_PCH

CH64

22U_0603_6.3V6M

1U_0402_6.3V6K

1

CH68

2

1

CH78

2

1

2

1

2

1

2

4

1

CH65

22U_0603_6.3V6M

2

1

CH69

1U_0402_6.3V6K

2

+VCCRTCEXT

+VCCAFDI_VRM

+1.05VS_VCCADPLLA

+1.05VS_VCCADPLLB

+1.05VS_VCCDIFFCLKN

+VCCSST

0.1U_0402_10V7K

CH85

+RTCVCC

+3VS_VCC_CLKF33

1

2

1

2

0.1U_0402_10V7K

CH90

3

2

+5VALW

1

+5VALW_PCH

Id=3A,Rds=130mohm/-2.5V

QH6

AO3413_SOT23

D

S

D

UH1J

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3[5]

BH23

VCCAPLLDMI2

AL29

VCCIO[14]

AL24

DCPSUS[3]

AA19

VCCASW[1]

AA21

VCCASW[2]

AA24

VCCASW[3]

AA26

VCCASW[4]

AA27

VCCASW[5]

AA29

VCCASW[6]

AA31

VCCASW[7]

AC26

VCCASW[8]

AC27

VCCASW[9]

AC29

VCCASW[10]

AC31

VCCASW[11]

AD29

VCCASW[12]

AD31

VCCASW[13]

W21

VCCASW[14]

W23

VCCASW[15]

W24

VCCASW[16]

W26

VCCASW[17]

W29

VCCASW[18]

W31

VCCASW[19]

W33

VCCASW[20]

N16

DCPRTC

Y49

VCCVRM[4]

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO[7]

AF33

VCCDIFFCLKN[1]

AF34

VCCDIFFCLKN[2]

AG34

VCCDIFFCLKN[3]

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS[1]

V19

DCPSUS[2]

BJ8

V_PROC_IO

A22

1

2

VCCRTC

PANTHER-POINT_FCBGA989

POWER

1mA

VCCSUS3_3[7]

119mA

VCCSUS3_3[8]

VCCSUS3_3[9]

VCCSUS3_3[10]

VCCSUS3_3[6]

803mA

75mA 75mA

95mA

2mA

6uA@G3

HM76R1@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

1mA

VCCSUS3_3[1]

1mA

VCCSUS3_3[2]

VCCSUS3_3[3]

VCCSUS3_3[4]

VCCSUS3_3[5]

Clock and Miscellaneous

PCI/GPIO/LPC

VCCAPLLSATA

SATA USB

50mA

VCCASW[22]

VCCASW[23]

MISC

CPURTC

VCCASW[21]

10mA

VCCSUSHDA

HDA

3

N26

VCCIO[29]

P26

VCCIO[30]

P28

VCCIO[31]

T27

VCCIO[32]

T29

VCCIO[33]

T23

T24

V23

V24

P24

T26

VCCIO[34]

V5REF_SUS

DCPSUS[4]

V5REF

VCC3_3[1]

VCC3_3[8]

VCC3_3[4]

VCC3_3[2]

VCCIO[5]

VCCIO[12]

VCCIO[13]

VCCIO[6]

VCCVRM[1]

VCCIO[2]

VCCIO[3]

VCCIO[4]

2013/12/17 2014/12/17

M26

AN23

AN24

P34

N20

N22

P20

P22

AA16

W16

T34

AJ2

AF13

AH13

AH14

AF14

AK1

AF11

AC16

AC17

AD17

T21

V21

T19

P32

+PCH_V5REF_SUS

+PCH_V5REF_RUN

+VCCAFDI_VRM

+1.05VS_PCH

1

CH56

1U_0402_6.3V6K

2

+3VALW_PCH

1

CH60

0.1U_0402_10V7K

2

1

2

+1.05VS_PCH

+3VALW_PCH

1

2

CH66 0.1U_0402_10V7K

+3VALW_PCH

1

CH70

1U_0402_6.3V6K

2

+3VS

1

2

CH75

0.1U_0402_10V7K

1

2

Compal Secret Data

+3VS

1

CH76

0.1U_0402_10V7K

2

This pin can be left as NC if On-Die VR is enabled (Default)

+VCCAFDI_VRM

+1.05VS_PCH

+3VALW_PCH

CH92

0.1U_0402_10V7K

Deciphered Date

PCH_PWR_EN#<22,32>

+3VALW_PCH

Change RH232, RH237 to 10 ohm by follow Compal ORB abd Intel CRB

CH61

0.1U_0402_10V7K

+3VS

1

CH72

0.1U_0402_10V7K

2

+1.05VS_PCH

1

CH77

1U_0402_6.3V6K

2

Place CH77 near pin AF13, AH13, AH14, AF14

+1.05VS_PCH

1

CH82

1U_0402_6.3V6K

2

Place CH82 near pin AC16, AC17, AD17

2

RH328

1

2

47K_0402_5%

10_0402_5%

Title

Size Document Number Rev

Custom

Date: Sheet

S

1

3

G

1

2

+5VALW_PCH

RH232

2

CH80

0.1U_0402_10V7K

+3VALW_PCH

1

2

DH3

RB751V-40 SOD-323

2

1

+PCH_V5REF_SUS

1

CH63

0.1U_0402_10V7K

2

+5VS

+3VS

CH63 & CH71 are different by Intel CRB.

2

1

DH4

RH237

Compal Electronics, Inc.

LAB412P

DH4

RB751V-40 SOD-323

1

+PCH_V5REF_RUN

2

1

CH71

1U_0402_6.3V6K

2

PCH_POWER-2

1

CH59

2

0.1U_0402_10V7K

of

23 41Wednesday, January 22, 2014

of

23 41Wednesday, January 22, 2014

of

23 41Wednesday, January 22, 2014

D

C

B

A

0.2

5

UH1H

H5

VSS[0]

AA17

VSS[1]

AA2

D

C

B

A

VSS[2]

AA3

VSS[3]

AA33

VSS[4]

AA34

VSS[5]

AB11

VSS[6]

AB14

VSS[7]

AB39

VSS[8]

AB4

VSS[9]

AB43

VSS[10]

AB5

VSS[11]

AB7

VSS[12]

AC19

VSS[13]

AC2

VSS[14]

AC21

VSS[15]

AC24

VSS[16]

AC33

VSS[17]

AC34

VSS[18]

AC48

VSS[19]

AD10

VSS[20]

AD11

VSS[21]

AD12

VSS[22]

AD13

VSS[23]

AD19

VSS[24]

AD24

VSS[25]

AD26

VSS[26]

AD27

VSS[27]

AD33

VSS[28]

AD34

VSS[29]

AD36

VSS[30]

AD37

VSS[31]

AD38

VSS[32]

AD39

VSS[33]

AD4

VSS[34]

AD40

VSS[35]

AD42

VSS[36]

AD43

VSS[37]

AD45

VSS[38]

AD46

VSS[39]

AD8

VSS[40]

AE2

VSS[41]

AE3

VSS[42]

AF10

VSS[43]

AF12

VSS[44]

AD14

VSS[45]

AD16

VSS[46]

AF16

VSS[47]

AF19

VSS[48]

AF24

VSS[49]

AF26

VSS[50]

AF27

VSS[51]

AF29

VSS[52]

AF31

VSS[53]

AF38

VSS[54]

AF4

VSS[55]

AF42

VSS[56]

AF46

VSS[57]

AF5

VSS[58]

AF7

VSS[59]

AF8

VSS[60]

AG19

VSS[61]

AG2

VSS[62]

AG31

VSS[63]

AG48

VSS[64]

AH11

VSS[65]

AH3

VSS[66]

AH36

VSS[67]

AH39

VSS[68]

AH40

VSS[69]

AH42

VSS[70]

AH46

VSS[71]

AH7

VSS[72]

AJ19

VSS[73]

AJ21

VSS[74]

AJ24

VSS[75]

AJ33

VSS[76]

AJ34

VSS[77]

AK12

VSS[78]

AK3

VSS[79]

PANTHER-POINT_FCBGA989

HM76R1@

4

AK38

VSS[80]

AK4

VSS[81]

AK42

VSS[82]

AK46

VSS[83]

AK8

VSS[84]

AL16

VSS[85]

AL17

VSS[86]

AL19

VSS[87]

AL2

VSS[88]

AL21

VSS[89]

AL23

VSS[90]

AL26

VSS[91]

AL27

VSS[92]

AL31

VSS[93]

AL33

VSS[94]

AL34

VSS[95]

AL48

VSS[96]

AM11

VSS[97]

AM14

VSS[98]

AM36

VSS[99]

AM39

VSS[100]

AM43

VSS[101]

AM45

VSS[102]

AM46

VSS[103]

AM7

VSS[104]

AN2

VSS[105]

AN29

VSS[106]

AN3

VSS[107]

AN31

VSS[108]

AP12

VSS[109]

AP19

VSS[110]

AP28

VSS[111]

AP30

VSS[112]

AP32

VSS[113]

AP38

VSS[114]

AP4

VSS[115]

AP42

VSS[116]

AP46

VSS[117]

AP8

VSS[118]

AR2

VSS[119]

AR48

VSS[120]

AT11

VSS[121]

AT13

VSS[122]

AT18

VSS[123]

AT22

VSS[124]

AT26

VSS[125]

AT28

VSS[126]

AT30

VSS[127]

AT32

VSS[128]

AT34

VSS[129]

AT39

VSS[130]

AT42

VSS[131]

AT46

VSS[132]

AT7

VSS[133]

AU24

VSS[134]

AU30

VSS[135]

AV16

VSS[136]

AV20

VSS[137]

AV24

VSS[138]

AV30

VSS[139]

AV38

VSS[140]

AV4

VSS[141]

AV43

VSS[142]

AV8

VSS[143]

AW14

VSS[144]

AW18

VSS[145]

AW2

VSS[146]

AW22

VSS[147]

AW26

VSS[148]

AW28

VSS[149]

AW32

VSS[150]

AW34

VSS[151]

AW36

VSS[152]

AW40

VSS[153]

AW48

VSS[154]

AV11

VSS[155]

AY12

VSS[156]

AY22

VSS[157]

AY28

VSS[158]

3

UH1I

AY4

VSS[159]

AY42

VSS[160]

AY46

VSS[161]

AY8

VSS[162]

B11

VSS[163]

B15

VSS[164]

B19

VSS[165]

B23

VSS[166]

B27

VSS[167]

B31

VSS[168]

B35

VSS[169]

B39

VSS[170]

B7

VSS[171]

F45

VSS[172]

BB12

VSS[173]

BB16

VSS[174]

BB20

VSS[175]

BB22

VSS[176]

BB24

VSS[177]

BB28

VSS[178]

BB30

VSS[179]

BB38

VSS[180]

BB4

VSS[181]

BB46

VSS[182]

BC14

VSS[183]

BC18

VSS[184]

BC2

VSS[185]

BC22

VSS[186]

BC26

VSS[187]

BC32

VSS[188]

BC34

VSS[189]

BC36

VSS[190]

BC40

VSS[191]

BC42

VSS[192]

BC48

VSS[193]

BD46

VSS[194]

BD5

VSS[195]

BE22

VSS[196]

BE26

VSS[197]

BE40

VSS[198]

BF10

VSS[199]

BF12

VSS[200]

BF16

VSS[201]

BF20

VSS[202]

BF22

VSS[203]

BF24

VSS[204]

BF26

VSS[205]

BF28

VSS[206]

BD3

VSS[207]

BF30

VSS[208]

BF38

VSS[209]

BF40

VSS[210]

BF8

VSS[211]

BG17

VSS[212]

BG21

VSS[213]

BG33

VSS[214]

BG44

VSS[215]

BG8

VSS[216]

BH11

VSS[217]

BH15

VSS[218]

BH17

VSS[219]

BH19

VSS[220]

H10

BH27

VSS[221]

VSS[222]

BH31

VSS[223]

BH33

VSS[224]

BH35

VSS[225]

BH39

VSS[226]

BH43

VSS[227]

BH7

VSS[228]

D3

VSS[229]

D12

VSS[230]

D16

VSS[231]

D18

VSS[232]

D22

VSS[233]

D24

VSS[234]

D26

VSS[235]

D30

VSS[236]

D32

VSS[237]

D34

VSS[238]

D38

VSS[239]

D42

VSS[240]

D8

VSS[241]

E18

VSS[242]

E26

VSS[243]

G18

VSS[244]

G20

VSS[245]

G26

VSS[246]

G28

VSS[247]

G36

VSS[248]

G48

VSS[249]

H12

VSS[250]

H18

VSS[251]

H22

VSS[252]

H24

VSS[253]

H26

VSS[254]

H30

VSS[255]

H32

VSS[256]

H34

VSS[257]

F3

VSS[258]

PANTHER-POINT_FCBGA989

HM76R1@

2

VSS[259]

VSS[260]

VSS[261]

VSS[262]

VSS[263]

VSS[264]

VSS[265]

VSS[266]

VSS[267]

VSS[268]

VSS[269]

VSS[270]

VSS[271]

VSS[272]

VSS[273]

VSS[274]

VSS[275]

VSS[276]

VSS[277]

VSS[278]

VSS[279]

VSS[280]

VSS[281]

VSS[282]

VSS[283]

VSS[284]

VSS[285]

VSS[286]

VSS[287]

VSS[288]

VSS[289]

VSS[290]

VSS[291]

VSS[292]

VSS[293]

VSS[294]

VSS[295]

VSS[296]

VSS[297]

VSS[298]

VSS[299]

VSS[300]

VSS[301]

VSS[302]

VSS[303]

VSS[304]

VSS[305]

VSS[306]

VSS[307]

VSS[308]

VSS[309]

VSS[310]

VSS[311]

VSS[312]

VSS[313]

VSS[314]

VSS[315]

VSS[316]

VSS[317]

VSS[318]

VSS[319]

VSS[320]

VSS[321]

VSS[322]

VSS[323]

VSS[324]

VSS[325]

VSS[328]

VSS[329]

VSS[330]

VSS[331]

VSS[333]

VSS[334]

VSS[335]

VSS[337]

VSS[338]

VSS[340]

VSS[342]

VSS[343]

VSS[344]

VSS[345]

VSS[346]

VSS[347]

VSS[348]

VSS[349]

VSS[350]

VSS[351]

VSS[352]

K7

L18

L2

L20

L26

L28

L36

L48

M12

P16

M18

M22

M24

M30

M32

M34

M38

M4

M42

M46

M8

N18

P30

P11

P18

T33

P40

P43

P47

P7

R2

R48

T12

T31

T37

T4

W34

T46

T47

T8

V11

V17

V26

V27

V29

V31

H46

K18

K26

K39

K46

N47

V36

V39

V43

V7

W17

W19

W2

W27

W48

Y12

Y38

Y4

Y42

Y46

Y8

BG29

N24

AJ3

AD47

B43

BE10

BG41

G14

H16

T36

BG22

BG24

C22

AP13

M14

AP3

AP1

BE16

BC16

BG28

BJ28

1

D

C

B

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PCH_GND

LAB412P

24 41Wednesday, January 22, 2014

1

0.2

of

A

B

C

D

E

SATA HDD Conn. SATA ODD Conn

JHDD

@

JHDD

@

1

GND

RX+

RX-

GND

1

24

23

2

GND

SANTA_191503-1

TX+

3.3V

TX-

5V

Rsv

12V

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

SATA_PTX_C_DRX_P0

SATA_PTX_C_DRX_N0

SATA_PRX_DTX_N0

SATA_PRX_DTX_P0

NGFF-Slot1-E-Key-WLAN

3

WL_OFF#<30>

BT_ON<30>

PLT_RST#<20,26,27,30,31,5>

CLK_NGFF<18>

E51_RXD<30>

E51_TXD<30>

Debug card using

CLink is only for Intel AMT

pin 8-15 Removed for key A

Close to JHDD

1

C369 0.01U_0402_25V7K

1

C367 0.01U_0402_25V7K

1

C368 0.01U_0402_25V7K

1

C370 0.01U_0402_25V7K

+3VS

+5VS

Close to JHDD Close to JODD

1.2A

1

C356

10U_0603_6.3V6M

2

+3V_WLAN

2

1

C357

0.1U_0402_10V7K

2

JWLAN

68

GND1

66

3.3VAUX_74

64

3.3VAUX_72

62

RSVD_70

60

RSVD_68

58

RSVD_66

56

RSVD_64

54

I2C_IRQ

52

I2C_CLK

50

I2C_DAT

48

W_DISABLE1#

46

W_DISABLE2#

44

PERST0#

42

SUSCLK(32KHz)

40

COEX1

38

COEX2

36

COEX3

34

CLink_CLK

32

CLink_DATA

30

CLink_RST

28

UART_CTS

26

UART_RTS

24

UART_RX

22

UART_TX

20

UART_WAKE

18

GND_18

16

LED2#

14

PCM_IN

12

PCM_OUT

10

PCM_SYNC

8

PCM_CLK

6

LED1#

4

3.3VAUX_4

2

3.3VAUX_2

SATA_PTX_DRX_P0 <16>

SATA_PTX_DRX_N0 <16>

SATA_PRX_C_DTX_N0 <16>

SATA_PRX_C_DTX_P0 <16>

1

C358

0.1U_0402_10V7K

2

@

GND2

GND_75

RSVD_73

RSVD_71

GND_69

RSVD/PCIE_TX_N1

RSVD/PCIE_TX_P1

GND_63

RSVD/PCIE_RX_N1

RSVD/PCIE_RX_P1

GND_57

PEWAKE0#

CLKREQ0#

GND_51

REFCLK_N0

REFCLK_P0

GND_45

PER_TX_N0

PER_TX_P0

GND_39

PET_RX_N0

PET_RX_P0

GND_33

SDIO_RST

SDIO_WAKE

SDIO_DAT3

SDIO_DAT2

SDIO_DAT1

SDIO_DAT0

SDIO_CMD

SDIO_CLK

GND_7

USB_D-

USB_D+

GND_1

BELLW_80152-3221

@JODD

1

GND

A+

A-

GND

B-

B+

GND

DP

+5V

14

15

+3V_WLAN

0.1U_0402_10V7K

1

CM6

69

67

65

63

61

59

57

55

53

51

49

47

45

43

41

39

37

35

33

31

29

27

25

23

21

19

17

15

13

11

9

7

5

3

1

0.1U_0402_10V7K

Close to JWLAN

1

CM7

CM8

2

4.7U_0603_6.3V6K

WLAN_WAKE# <30>

CLKREQ_WLAN# <17>

CLK_WLAN# <17>

CLK_WLAN <17>

PCIE_PRX_WLANTX_N2 <17>

PCIE_PRX_WLANTX_P2 <17>

PCIE_PTX_C_WLANRX_N2 <17>

PCIE_PTX_C_WLANRX_P2 <17>

USB20_N9 <20>

USB20_P9 <20>

GND

SANTA_201902-1

1

2

WiMax/ BT

MD

2

3

4

5

6

7

8

9

10

11

12

13

WLAN/ WiFi

SATA_PTX_C_DRX_P2

SATA_PTX_C_DRX_N2

SATA_PRX_DTX_N2

SATA_PRX_DTX_P2

+5VS_ODD

Close to JODD

1

2

C378 0.01U_0402_25V7K

1

2

C377 0.01U_0402_25V7K

1

2

C376 0.01U_0402_25V7K

1

2

C375 0.01U_0402_25V7K

ODD_DETEC T# <21>

ODD_DA# <20 >

+5VS_ODD

1

C352

10U_0603_6.3V6M

2

1

C372

0.1U_0402_10V7K

2

SATA_PTX_DRX_P2 <16>

SATA_PTX_DRX_N2 <16>

SATA_PRX_C_DTX_N2 <16>

SATA_PRX_C_DTX_P2 <16>

1

C373

0.1U_0402_10V7K

2

Power Consumpt ion

Peak 1800 mA Read (CD) 1 100 mA Read (DVD) 9 50 mA Write 1300 mA Standby 20mA

1

2

3

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

HDD/ODD/NGFF

LAB412P

E

of

25 41Wednesday, January 22, 2014

of

25 41Wednesday, January 22, 2014

of

25 41Wednesday, January 22, 2014

4

0.2

A

B

C

D

E

TPM

+3VALW

1

CT6

CT5

2

10U_0603_6.3V6M

1

TPM@

CT2

2

0.1U_0402_10V7K

Close to Pin24

Close to Pin5

TPM@

0.1U_0402_10V7K

1

TPM@

CT3

2

0.1U_0402_10V7K

1

CT4

2

0.1U_0402_10V7K

1

Close to Pin10

2

1

TPM@

+3VS

TPM@

1

2

TPM@

CT1

2

10U_0603_6.3V6M

For EMI

RT2

22_0402_5% @EMI@

CT7

2

CT7

10P_0402_50V8J

BADD ADDRESS

0

* Floating

CLK_PCI_TPM_R

1

2

1

@EMI@

2

EEh - EFh

7Eh - 7Fh

TPM@

VSB

VDD1

VDD2

TEST

NC0

VDD3

VSS3

NC1

NC2

NC3

VSS0

VSS1

VSS2

TPM@

5

19

24

8

3

10

11

12

13

14

4

18

25

+3VALW

+3VS

UT1

1

GPIO0/XOR_OUT

2

GPIO1

@

1

2

RT1 10K_0402_5%

LPC_AD0<16,30>

LPC_AD1<16,30>

LPC_AD2<16,30>

LPC_AD3<16,30>

CLK_PCI_TPM_R<20>

LPC_FRAME#<16,30>

PLT_RST#<20,25,27,30,31,5>

SERIRQ<16,30>

CLK_PCI_TPM_R

6

GPIO2/GPX

9

GPIO3/BADD

15

GPIO4/CLKRUN #

26

LAD0

23

LAD1

20

LAD2

17

LAD3

28

LPCPD#

21

LCLK

22

LFRAME#

16

LRESET#

27

SERIRQ

7

PP

NPCT650AA0WX_TSSOP28

Close to Pin19

3

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

TPM/GCLK

Size Document Number Rev

Date: Sheet

D

Date: Sheet

TPM/GCLK

LAB412P

Wednesday, January 22, 2014

of

26 41

of

26 41

of

E

26 41

3

4

0.2

A

B

C

D

E

1

2

3

LAN/USB Small board Conn

JLAN

@

JLAN

@

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

27

28

E-T_6905-E26N-01R

25

G1

26

G2

For LAN function

1

2

RL24 10K_0402_5%

+3VS

LAN_EN<17>

CLKREQ_LAN#<17>

2N7002KW_SOT323-3

LANCLK_REQ#

2

G

1

D

QL53

ISOLATE#

LANCLK_REQ#

3

S

+USB_VCCC

PCIE_PRX_C_LANTX_P1 <17>

PCIE_PRX_C_LANTX_N1 <17>

PCIE_PTX_C_LANRX_P1 <17>

PCIE_PTX_C_LANRX_N1 <17>

EC_SWI# <18,30>

PLT_RST# <20,25,26,30,31,5>

+3V_LAN

PL <29>

PR <29>

EXT_MIC_L <29>

NBA_PLUG# <29>

+3V_LAN

+3VS

1

2

USB20_N2_R

USB20_P2_R

CLK_LAN_R

CLK_LAN#_R

1K_0402_5%

RL8

@

ISOLATE#

RL9

15K_0402_5%

+3V_LAN > 40 mil

PJ77

@

PJ77

@

1

2

JUMP_43X39

1

RL433 0_0402_5%@

WOL_EN#

2

LR9 EMI@

1

4

DLW21HN900HQ2L_4P

RL1 0_0402_5%@EMI@

1

4

DLW21HN900HQ2L_4P

+3VALW_PCH

2

Sx Enable Wake up

LOW

2

3

1

2

@EMI@

Sx Disable Wake up

2

3

2

LL1 EMI@

1

RL2 0_0402_5%

HIGH

WOL_EN# <30>

USB20_N2 <20>

USB20_P2 <20>

CLK_LAN <17>

CLK_LAN# <17>

Left USB 2.0 x 1

Current Limit 2A

+5VALW

5

USB_EN#2<30>

+5VALW

1

CR2

@

2

LAN WOL LAN_EN ISOLATEB S0 Sx S0 Sx

--------------------------------------------- 0 0 0 0 1 1 0 1 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 0*

* S3: after SUSP# assert low over 100ms S4/S5: after SYSON assert low over 100ms

+3V_LAN rising time (10%~90%) need > 1ms and <100ms.

4

SY6288D20AAC_SOT23-5

SA00007AO00

Un-mount due to near +5VALW source

10U_0603_6.3V6M

Check Output Caps are on sub-board or not.

W=80mils

UR3

OUT

IN

GND

EN

OCB

+USB_VCCC

1

2

3

+3VALW_PCH

1

2

RR1

10K_0402_5%

USB_OC#2 <30>

1

2

3

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

C

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

LUSB20/LAN conn.

LAB412P

E

of

27 41Wednesday, January 22, 2014

of

27 41Wednesday, January 22, 2014

of

27 41Wednesday, January 22, 2014

4

0.2

5

4

3

2

1

D

Right USB power switch

D

Current Limit 2A

+5VALW

C

USB_EN#0<30>

W=80mils

UR1

OUT

5

IN

GND

4

EN

OCB

SY6288D20AAC_SOT23-5

SA00007AO00

+USB_VCCB

1

2

3

+3VALW_PCH

1

2

RR2

10K_0402_5%

USB_OC#0 <30>

CLOSE to UR1

+USB_VCCB

+5VALW

1

CR1

2

10U_0603_6.3V6M

1

2

CR3

0.1U_0402_10V7K

W=80mils

1

CR10

2

22U_0805_6.3V6M

1

CR11

2

1

CR12

2

22U_0805_6.3V6M

C

Right front USB 3.0 Conn.Right rear USB2.0 Conn.

LR1

EMI@

LR1

EMI@

4

LR7 EMI@

USB20_P1<20>

USB20_N1<20>

1

4

DLW21HN900HQ2L_4P

2

3

USB20_P1_R

2

USB20_N1_R

3

U3RXDP1<20>

U3RXDN1<20>

4

1

DLW21HN900HQ2L_4P

U3RXDP1_L

3

U3RXDN1_L

2

USB20_N0<20>

USB20_P0<20>

LR8 EMI@

4

1

DLW21HN900HQ2L_4P

USB20_N0_R

3

USB20_P0_R

2

LR2

EMI@

LR2

B

JUSBR

@

JUSBR

@

+USB_VCCB

A

USB20_N1_R

USB20_P1_R

5

1

VBUS

2

D-

3

D+

4

SHIELD

5

GND

6

GND

7

GND

8

GND

SANTA_360131-1

4

U3TXDP1<20>

U3TXDN1<20>

1

CR4 0.1U_0402_10V7K

1

CR5 0.1U_0402_10V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

U3TXDP1_C

2

U3TXDN1_C

2

U3TXDP1_C_L

U3TXDN1_C_L

U3RXDP1_L

U3RXDN1_L

2013/12/17 2014/12/17

3

EMI@

4

1

DLW21HN900HQ2L_4P

1

2

4

5

3

L05ESDL5V0NA-4_SLP2510P8-10-9

3

2

DR1

@ESD@

1

2

4

3

8

10

9

7

65

Compal Secret Data

Deciphered Date

U3TXDP1_C_L

U3TXDN1_C_L

U3TXDP1_C_L

9

U3TXDN1_C_L

8

U3RXDP1_L

7

U3RXDN1_L

6

2

+USB_VCCB

W=80mils

U3TXDP1_C_L

U3TXDN1_C_L

USB20_N0_R

USB20_P0_R

U3RXDP1_L

U3RXDN1_L

JUSBF

@

JUSBF

@

9

SSTX+

1

VBUS

8

SSTX-

2

D-

7

GND

3

D+

6

SSRX+

4

GND

5

SSRX-

OCTEK_USB -09EAEB

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

RUSB20/30

GND

LAB412P

10

11

12

13

of

28 41Wednesday, January 22, 2014

of

28 41Wednesday, January 22, 2014

of

1

28 41Wednesday, January 22, 2014

B

A

0.2

1

2

0.1U_0402_10V7K

1

2

RA17 100K_0402_5%

1

2

CA18 4.7U_0402_6.3V6M

close to pin, 10mil

AC_VREF

2

1

@

CA21

1

2

A

PR_R

PR_L

close to pin, 10mil close to pin3

Reserve for solve pop noise

EC_MUTE_INT<30>

LDO1-CAP

CA22

2.2U_0402_6.3V6M

RA3 4.7K_0402_5%

1

2

1

2

RA5 4.7K_0402_5%

RA7

PR_L

PR_R

1

CA6 1U_0402_6.3V6K

CA9 1U_0402_6.3V6K

1

CA7 4.7U_0402_6.3V6M

CA12 4.7U_0402_6.3V6M

2

RA4 47_0402_1%

2

1

2

1

2

RA12

2

1

@

0_0402_5%

1

47_0402_1%

1

AGND

+MIC2_VREFO

+MIC1-VREFO-R

+MIC1-VREFO-L

AC_VREF

HPOUT_L

HPOUT_R

CBN

CBP

CPVEE

LDO1-CAP

LDO2-CAP

LDO3-CAP

SPKL-

SPKL+

SPKR-

SPKR+

EC_MUTE_INT_R

DGND

UA1

16

MONO- OUT

29

MIC2-VREFO

30

MIC1-VREFO-R

31

MIC1-VREFO-L

15

JDREF

28

VREF

32

HPOUT-L(PORT-I-L)

33

HPOUT-R(PORT-I-R)

35

CBN

37

CBP

34

CPVEE

27

LDO1-CAP

39

LDO2-CAP

7

LDO3-CAP

43

SPK-OUT-L-

42

SPK-OUT-L+

44

SPK-OUT-R-

45

SPK-OUT-R+

48

SPDIF-OUT/GPIO2

4

DVSS

25

AVSS1

38

AVSS2

49

Thermal Pad

ALC233-VB2 MQFN 48P

B

DVDD

DVDD-IO

AVDD1

AVDD2

PVDD1

PVDD2

CPVDD

GPIO0/DMIC-DATA

GPIO1/DMIC-CLK

SDATA-IN

SDATA-OUT

BCLK

SYNC

PCBEEP

Sense A

Sense B

MIC1-L (PORT -B-L )

MIC1-R (PORT -B-R )

MIC2-L(PORT-F-L)

MIC2-R(PORT-F-R)

LINE1-L(PORT-C-L)

LINE1-R(PORT-C-R)

LINE2-L(PORT-E-L)

LINE2-R(PORT-E-R)

RESETB

C

60 mil 20 mil

+DVDD

1

+DVDD

9

+AVDD1

26

+AVDD2

40

+PVDD

41

+PVDD

46

+DVDD

36

2

3

8

5

6

10

12

13

14

19

20

17

18

22

21

24

23

11

47

PDB

For EMI reserve

INT_MIC_CLK_R

AZ_SDIN0_HD_R

AZ_BITCLK_HD

MONO_IN

SENSE_A

CPVREF

MIC2_R_C_R

LINE1-L

LINE1-R

2

1

RA8

CAM_EMI@

RA8

CAM_EMI@

SBY100505T-301Y-N

1

2

22_0402_5%

RA9

CA14 4.7U_0402_6.3V6M

1

2

1

2

CA16 2.2U_0402_6.3V6M

1

2

CA17 2.2U_0402_6.3V6M

EC_MUTE# <30>

RA19

4.7K_0402_5%

@

Reserve for solve noise issue

Internal AMP

EC_MUTE#

Hight

Enable

LOW

Disable

INT_MIC_DATA <13>

AZ_SDIN0_HD <16>

AZ_SDOUT_HD <16>

AZ_BITCLK_HD <16>

AZ_SYNC_HD <16>

RA15 1K_0402_5%

LINE1-L_C

LINE1-R_C

RA16 1K_0402_5%

2

CA19

0.01U_0402_25V7K

1

@ESD@

RA13 0_0402_5%

1

2

@

1

2

1

2

AZ_RST_HD# <16>

EMI@

CA8

220P_0402_50V7K

EXT_MIC

PR_L

PR_R

INT_MIC_CLK <13>

0.1U_0402_10V7K

close to pin41

0.1U_0402_10V7K

close to pin46

20 mil

For EMI reserve close to codec

AZ_BITCLK_HD

+PVDD

1

CA3

2

CA5

+AVDD2

1

CA11

1U_0402_6.3V6K

2

20 mil

CPVREF

2

RA23

10_0402_5% EMI@

D

1

2

1

@

RA11 0_0603_5%

1

@

RA18 0_0402_5%

1

10P_0402_50V8J EMI@

1

@

RA1 0_0603_5%

2

CA4

1

10U_0603_6.3V6M

2

+3VALW

2

1

CA20

+1.5VS

2

+5VS

close to pin26

1U_0402_6.3V6K

close to pin1

0.1U_0402_10V7K

+DVDD

1

CA10

2

0.1U_0402_10V7K

+AVDD1

CA1

E

1

2

1

CA15

2

1

@

RA20 0_0603_5%

1

@

RA21 0_0603_5%

1

@

RA22 0_0603_5%

1

RA24 0_0603_5%

1

RA25 0_0603_5%

1

@

RA2 0_0603_5%

CA2

1U_0402_6.3V6K

1

RA10 0_0603_5%

1

CA13

4.7U_0402_6.3V6M

2

close to pin36

2

+5VS

2

@

+3VS

1

2

Combo Jack

RA26 2.2K_0402_5%

1

+MIC2_VREFO

EXT_MIC

3

+3VS

NBA_PLUG#<27>

2

place close to chip

1

RA29 100K_0402_5%

1

RA30 200K_0402_1%

for Combo Jack normal Open

(ALC233VB supported IPhone headset/ Headphone/ MIC in)

4

A

Change material to SM01000GK00

LA2

2

EMI@

1

2

SBY100505T-470Y-N_2P

SENSE_A

For EMI protection use SM01000GK00

LA1

PR_R

EXT_MIC_L <27>

1

2

CA24

100P_0402_50V8J

PR_L

LA1

1

2

0_0402_5%@

LA3

1

2

0_0402_5%@

@EMI@

CA26

1

CA27

2

@EMI@

2

100P_0402_50V8J

PR <27>

PL <27>

Beep sound

PCI Beep

PCH_SPKR<16>

RA27

1

47K_0402_5%

RA28

4.7K_0402_5%

MONO_IN

CA23

1

2

@

1

2

0.1U_0402_10V7K

CA25

100P_0402_50V8J

For better sound by customer request

3

SPK Conn.

For EMI reserve close to codec

SPKL+

SPKL-

SPKR+

SPKR-

B

1

2

@

RA32 0_0603_5%

1

2

@

RA33 0_0603_5%

CA28

1000P_0402_50V7K

@EMI@

1

2

@

RA34 0_0603_5%

1

2

@

RA35 0_0603_5%

@EMI@

1000P_0402_50V7K

CA30

1

2

1

2

1

CA29

1000P_0402_50V7K

2

@EMI@

1

@EMI@

CA31

1000P_0402_50V7K

2

SPK_L1

SPK_L2

SPK_R1

SPK_R2

DA8 ESD@

1

MESC5V02BD03_SOT23-3

1

MESC5V02BD03_SOT23-3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONI CS, INC.

C

3

2

SPK_L1

SPK_L2

SPK_R1

SPK_R2

DA9 ESD@

3

2

Compal Secr et Data

2013/12/17 2014/12/17

Compal Secr et Data

1

2

3

4

CVILU_CI4404M1HRT-LF

Deciphered Date

D

JSPK

@

1

2

6

3

GND

5

4

GND

Speaker 4 ohm: 40mil Speaker 8 ohm: 20mil

EXT_MIC

EXT_MIC_L

RA13

LA2 CA24

close to small board connector

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet

Compal Electronics, Inc.

HDA-ALC233VB

LAB412P

E

LAB412P

29 41Wednesday, January 22, 2014

of

4

0.2

A

B

C

D

E

For RF

CLK_PCI_EC

1

RB3

22_0402_5% @RF@

2

1

CB11

@RF@

CB11

10P_0402_50V8J

1

10P_0402_50V8J

+3VL

2

+3VL

+3VS

3

@RF@

2

ESD@

2

RPB1

1

2

3

4

2.2K_8P4R_5%

RB27

100K_0402_5%

1

RB12

4.7K_0402_5%

1

2

PLT_RST#

8

7

6

5

1

CB13 10 0P_0402_50V8J

RB2

47K_0402_5%

1

CB12 0.1U_ 0402_10V7K

EC_RST#

EC_SMB_CK1

EC_SMB_DA1

EC_SMB_CK2

EC_SMB_DA2

E51_TXD

EC_MUTE_INT

KSI[0..7]<31>

KSO[0..17]<31>

0.1U_0402_10V7K

KB_RST#<21>

LPC_FRAME#<16,26>

CLK_PCI_EC<20>

WOWL_EN<32>

KSI[0..7]

KSO[0..17]

EC_SMB_CK1<34,35>

EC_SMB_DA1<34,35>

EC_SMB_CK2<17>

EC_SMB_DA2<17>

PM_SLP_S3#<18>

PM_SLP_S5#<18>

USB_OC#2<27>

USB_EN#2<27>

FAN_SPEED1<5>

PM_PWROK<18>

NUM_LED#<31>

EC_MUTE_INT<29>

0.1U_0402_10V7K

1

CB1

2

GATEA20<21>

SERIRQ<16,26>

LPC_AD3<16,26>

LPC_AD2<16,26>

LPC_AD1<16,26>

LPC_AD0<16,26>

PLT_RST#<20,25,26,27,31,5>

EC_SCI#<21>

EC_SMI#<20,21>

WL_OFF#<25>

E51_TXD<25>

E51_RXD<25>

BT_ON<25>

POK<18,36>

1

CB2

2

0.1U_0402_10V7K

CLK_PCI_EC

PLT_RST#

EC_RST#

KSI0

KSI1

KSI2

KSI3

KSI4

KSI5

KSI6

KSI7

KSO0

KSO1

KSO2

KSO3

KSO4

KSO5

KSO6

KSO7

KSO8

KSO9

KSO10

KSO11

KSO12

KSO13

KSO14

KSO15

KSO16

KSO17

EC_SMB_CK1

EC_SMB_DA1

EC_SMB_CK2

EC_SMB_DA2

E51_TXD

EC_MUTE_INT

0.1U_0402_10V7K

1

@

CB4

2

+3VL

1

CB5

@

CB5

@

2

UB1

1

GATEA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ

4

LPC_FRAME#

5

LPC_AD3

7

LPC_AD2

8

LPC_AD1

10

LPC_AD0

12

CLK_PCI_EC

13

PCIRST#/GPIO05

37

EC_RST#

20

EC_SCII#/GPIO0E

38

GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

EC_SMB_CK1/GPIO44

78

EC_SMB_DA1/GPIO45

79

EC_SMB_CK2/GPIO46

80

EC_SMB_DA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

GPIO0A

17

GPIO0B

18

GPIO0C

19

GPIO0D

25

EC_INVT_PWM/GPIO11

28

FAN_SPEED1/GPIO14

29

EC_PME#/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

PCH_PWROK/GPIO18

34

SUSP_LED#/GPIO19

36

NUM_LED#/GPIO1A

122

XCLKI/G PIO5D

123

XCLKO/G PIO5E

LPC & MISC

Int. K/B

Matrix

9

22

33

EC_VDD/VCC

PWM Output

DA Output

PS2 Interface

SPI Device Interface

SM Bus

GPIO

GND/GND

11

24

+3VL

CB3

0.1U_0402_10V7K

1

67

96

111

125

EC_VDD0

EC_VDD/VCC

EC_VDD/AVCC

BATT_TEMP/GPIO38

AD Input

CPU1.5V_S3_GATE/GPXIOA00

VCIN0_PH/GPXIOD00

SPI Flash ROM

PECI_KB930/GPIO41

BATT_CHG_LED#/GPIO52

GPIO

BATT_LOW_LED#/GPIO55

PM_SLP_S4#/GPIO59

EC_RSMRST#/GPXIOA03

EC_LID_OUT#/GPXIOA04

PROCHOT_IN/GPXIOA05

H_PROCHOT#_EC/GPXIOA06

VCOUT0_PH/GPXIOA07

GPO

PBTN_OUT#/GPXIOA09

PCH_APWROK/GPXIOA10

SA_PGOOD/GPXIOA11

GPI

PECI_KB9012/GPXIOD07

GND/GND

AGND/AGND

GND/GND

GND0

KB9012QF-A4_L QFP128_14X14

69

94

113

KB9012QF-A4_L QFP128_14X14

35

2

GPIO0F

BEEP#/GPIO10

GPIO12

ACOFF/GPIO13

GPIO39

ADP_I/GPIO3A

GPIO3B

GPIO42

IMON/GPIO43

DAC_BRIG/GPIO3C

EN_DFAN1/GPIO3D

IREF/GPIO3E

CHGVADJ/GPIO3F

EC_MUTE#/GPIO4A

USB_EN#/GPIO4B

CAP_INT#/GPIO4C

EAPD/GPIO4D

TP_CLK/GPIO4E

TP_DATA/GPIO4F

WOL_EN/GPXIOA01

ME_EN/GPXIO A02

SPIDI/GPIO5B

SPIDO/GPIO5C

SPICLK/GPIO58

SPICS#/GPIO5A

ENBKL/GPIO40

FSTCHG/GPIO50

CAPS_LED#/GPIO53

PWR_LED#/GPIO54

SYSON/GPIO56

VR_ON/GPIO57

BKOFF#/GPXIOA08

AC_IN/GPXIOD01

EC_ON/GPXIOD02

ON/OFF/GPXIOD03

LID_SW#/GPXIOD04

SUSP#/GPXIOD05

GPXIOD06

V18R

21

23

TRANS_PRSNT

26

27

BATT_PRES

63

64

65

66

75

76

DFAN1

68

70

71

72

83

84

85

86

TP_CLK

87

TP_DATA

88

97

98

99

109

119

120

126

128

WLAN_WAKE#

73

74

89

90

91

92

93

SYSON

95

VR_ON

121

127

EC_LID_OUT#

100

101

102

H_PROCHOT#_EC

103

VCOUT0_PH_L

104

105

106

107

108

ACIN_D

110

ON/OFFBTN#

112

LID_SW#

114

SUSP#

115

116

EC_PECI

117

118

+EC_V18R

124

1

CB15

4.7U_0603_6.3V6K

2

WL_BT_LED# <31>

USB_EN#0 <28>

BATT_PRES <34>

USB_OC#0 <28>

ADP_I <34,35 >

ADP_V <35>

EC_ENBKL < 13,19>

DFAN1 <5>

PCH_SUSPWRDN# <18>

SUSACK# <1 8>

EC_MUTE# <29>

PM_SLP_S4# <18>

EC_SWI# <18,27>

TP_CLK <31>

TP_DATA <31>

VGATE <18,40 >

PWRME_CTRL <16>

VCIN0_PH <34>

EC_SDIO <16>

EC_SDI <16>

EC_SCK <16>

EC_CS0# <16 >

WLAN_WAKE# <25>

WOL_EN# <27>

BATT_FULL_LED# <31>

CAPS_LED# <31>

PWR_SUSP_LED# <31>

BATT_CHG_LOW_L ED# <3 1>

SYSON <3 7>

VR_ON <40>

PCH_RSMRST# <18>

PROCHOT_IN <3 4>

BKOFF# <13>

PBTN_OUT# <18>

PCH_PWR_EN <32,36>

SA_PGOOD <38 >

EC_ON <36>

ON/OFFBTN# <31>

LID_SW# <31>

SUSP# <32,38,39>

Reserve this signal to EC by SW demand

VCIN0_PH connect to power portion

RB4 0_0402_ 5%

PROCHOT_IN connect to power portion

RB19 43_0402_5%

@

1

VR_HOT#<40>

H_PROCHOT#_EC

2

EC_LID_OUT#_R <21>

H_PECI <5>

@

1

RB1 0_0402_5%

2

1

2

G

3

BATT_PRES

ACIN_D

TRANS_PRSNT

Reserve TRANS_PRSNT for panel timing tuning

TP_CLK

TP_DATA

LID_SW#

WLAN_WAKE#

H_PROCHOT#_EC

Close to EC

SYSON

SUSP#

VR_ON

VCOUT0_PH_L

VCOUT0_PH connect to power portion

ACIN_D

Close to EC

D

QB1

2N7002K_SOT23-3

S

1

CB8

47P_0402_50V8J

2

@

1

2

CB9 100P_0402_50V8J

1

2

CB10 10 0P_0402_50V8J

@

1

2

RB22 10K_0402 _5%

1

2

RB8 4.7K_0402_5 %

1

2

RB9 4.7K_0402_5 %

1

2

RB35 47K_0402 _5%

1

2

RB7 10K_0402_5 %

1

2

@

RB6 10K_0402_5 %

1

2

CB16 1 00P_0402_50V8J

@ESD@

1

RB10 4.7 K_0402_5%

1

RB21 10K_0 402_5%

1

2

RB23 10K_040 2_5%

@

1

RB34 0_0402 _5%

RB5 0_040 2_5%

2

@

1

2

@ESD@

1

2

CB14 18 0P_0402_50V8J

H_PROCHOT# <5>

+3VS

+3VL

+3VS

2

VS_ON <36>

ACIN <18, 35>

SUSP#

1

2

3

ON/OFFBTN#

Voltage Comparator Pins FOR 9012 A4

4

A

VCIN0 pin109 VCIN1 pin102

VCOUT0 pin104

VCOUT1 pin103

>1.2V <1.2V

HIGH (default)

HIGH

LOW

LOW (default)

B

Security Classification

Issued Dat e

THIS SHEET OF ENG INEERING DRAWING I S THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY O R DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Nu mber Rev

Date: Sheet

Compal Electronics, Inc.

LPC-EC-KB9012/9022

Wednesday, January 22, 201 4

DFAN1

2

CC24

100P_0402_50V8J

@ESD@

1

LAB412P

E

2

CC23

100P_0402_50V8J

@ESD@

1

of

30 41

of

30 41

of

30 41

4

0.2

5

4

3

2

1

Power Button

D

C

KEYBOARD CONN.

+3VS

R483 300_0402_5%

B

+3VS

KSI[0..7]

KSO[0..17]

TJG-533-V-T/R_6P

3

4

NUM_LED#<30>

CAPS_LED#<30>

2

R480 300_0402_5%

KSI[0..7] <30>

KSO[0..17] <30>

+3VL

2

R469

100K_0402_5%

1

2

SW2

5

6

ON/OFFBTN#

1

R442

0_0805_5%

@

2

Reserved for DQA test Close to JDDRH & JPWR

ON/OFFBTN# <30>

PBTN/B to M/B

NOTICE: ON/OFFBTN# must have pull-high resistor on motherboard

JPWR

1

2

ON/OFFBTN#

3

5

3

G1

4

6

4

G2

E-T_6916K-Q04N-03R

@

+5VALW

PWR_SUSP_LED# <30>

Card Reader + TP + Lid SW

JKB

1

2

1

2

+3VS_CAP

KSI1

KSI6

KSI5

KSI0

KSI4

KSI3

KSI2

KSI7

KSO15

KSO12

KSO11

KSO10

KSO9

KSO8

KSO13

KSO7

KSO6

KSO14

KSO5

KSO3

KSO4

KSO0

KSO1

KSO2

KSO17

KSO16

+3VS_NUM

1

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

GND1

36

GND2

CVILU_CF17341U0R0-NH

@

JCARD

+3VS

+3VL

PLT_RST#<20,25,26,27,30,5>

CLKREQ_CR#<17>

1

2

@EMI@

R13 0_0402_5%

3

L7 EMI@

CLK_CR<17>

CLK_CR#<17>

L7 EMI@

3

2

DLW21HN900HQ2L_4P

1

R14 0_0402_5%

@EMI@

4

1

2

PCIE_PTX_C_CRRX_P4<17>

PCIE_PTX_C_CRRX_N4<17>

PCIE_PRX_C_CRTX_P4<17>

PCIE_PRX_C_CRTX_N4<17>

4

CLK_CR_R

CLK_CR#_R

1

LID_SW#<30>

TP_DATA<30>

TP_CLK<30>

PM_SMBDATA<11,12,17>

PM_SMBCLK<11,12,17>

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

GND

22

GND

ACES_50578-0200N-001

@

LED Small board to Conn

JLED

1

2

3

4

7

5

G1

8

6

G2

E-T_6916K-Q06N-00L

@

1

2

3

4

5

6

+5VALW

BATT_FULL_LED# <30>

BATT_CHG_LOW_LED# <30>

WL_BT_LED# <30>

Screw Hole

CPU

H2

H1

H2

H_4P2

@

1

H_4P6x4P2

@

H3

H_4P6

@

1

PTH NPTH

H6

H4

H_3P0

@

1

H8

H_3P0

@

1

H6

H5

H_3P0

@

1

H9

H_3P0

@

1

H7

H_3P0

@

1

H_3P0

@

1

H10

H_3P0

@

1

PCB Fedical Mark PAD

FD3

FD2

FD1

@

1

FD4

@

1

H15

1

H_4P2x3P2N

@

D

C

B

ISPD

ZZZ

DA600152000

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2013/12/17 2014/12/17

Compal Secret Data

Deciphered Date

DA600152000

PCB LA-B412P

2

Title

Sub conn./ISPD/KB/Screw

Size Document Number Rev

Date: Sheet

LAB412P

Wednesday, January 22, 2014

of

31 41

of

31 41

of

1

31 41

A

0.2

A

B

C

D

E

+5VALW TO +5VS +3VALW TO +3VS Load switch

1

1U_0402_6.3V6K

C537

+3VALW

@

VIN 5V and 3.3V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm

U4

1

VOUT1

VIN1

2

VOUT1

1

2

+5VALW

@

+5VALW

1

C542

1U_0402_6.3V6K

2

SUSP#

VIN1

3

4

5

6

7

Slew Rate (us/V) = 0.32*CT + 13.7

CT1

ON1

GND

VBIAS

ON2

CT2

VIN2

VOUT2

VIN2

VOUT2

GPAD

APE8990GN3B DFN 14P

+3VS

PJ3

@

+3VS_LS

14

13

12

11

10

9

8

15

C540 330P_0402_50V7K

1

C538 180P_0402_50V8J

+5VS_LS

2

1

2

1

PAD-OPEN 4x4m

PJ5

@

PAD-OPEN 4x4m

2

@

+5VS

1

2

1

C539

0.1U_0402_10V7K

@

2

C541

@

0.1U_0402_10V7K

1

+5VS TO +5VS_ODD

2

+3VALW TO +3V_WLAN

3

1U_0402_6.3V6K

C543

+5VS

@

1

2

for ISCT

RM3

10K_0402_5% NOISCT@

WOWL_EN<30>

4

WOWL_EN

RM2

10K_0402_5% ISCT@

for EC detect ISCT H -> NOISCT L -> ISCT

ODD_EN<21>

+3VALW

1

2

1

2

VIN 0.8V-5.5V (VBIAS=5V),IMAX=4A,Rds=22mohm

U7

ZPODD@

U7

ZPODD@

7

VOUT

8

VOUT

6

CT

5

GND

9

GND

VIN 0.8V-5.5V (VBIAS=5V),IMAX=4A,Rds=22mohm

U8

1

VIN

2

WOWL_EN

+5VALW

VIN

3

ON

4

VBIAS

TPS22967DSGR_SON8_2X2

SA000070S00

+5VS

1U_0402_6.3V6K

1

VIN

2

VIN

3

ON

4

VBIAS

TPS22967DSGR_SON8_2X2

SA000070S00

+3VALW

C546

1

@

2

Need mount R440 if system don't support ZPODD

+5VS_ODD_LS

Slew Rate (us/V) = 0.39*CT + 13.4

ISCT@

VOUT

CT

GND

+5VS

R440 0_0805_5%

R441 0_0805_5%

1

ZPODD@

C545

270P_0402_50V7K

2

7

8

6

5

9

NONZP@

1

ZPODD@

1

Slew Rate (us/V) = 0.39*CT + 13.4

2

+5VS_ODD

2

1

C544

0.1U_0402_10V7K

@

2

Need mount RM5 if system don't support ISCT

+3V_WLAN_LS

+3VS

RM7 0_0805_5%

1

ISCT@

2

NOISCT@

1

2

RM5 0_0805_5%

ISCT@

1

2

C548

270P_0402_50V7K

+3V_WLAN

1

2

C547

0.1U_0402_10V7K

@

+1.8VS

2

R470

470_0805_5%

1

D

Q190

SUSP

2

G

2

G

S

+5VALW

Q5527

3

G

2

R5545

10K_0402_5%

1

PCH_PWR_EN#

1

D

2N7002KW_SOT323-3

S

3

2N7002KW_SOT323-3

PCH_PWR_EN<30,36>

+0.675VS

2

R421

22_0805_5%

1

D

Q189

2

G

S

2N7002KW_SOT323-3

S

2N7002KW_SOT323-3

3

PCH_PWR_EN# <22,23>

+1.05VS_VCCP

SUSP

2

G

2N7002KW_SOT323-3

SUSP<9>

SUSP#<30,38,39>

2

R468

470_0805_5%

1

D

Q60

S

3

+5VALW

2

R422

100K_0402_5%

SUSP#

1

6

2

1

Q6A

2N7002KDWH_SOT363-6

SUSP

2

3

For S3 CPU Power Saving

VCCP_PWRGOOD<38>

1

2

R158 220K_0402_5%

SUSP

0.675VR_EN

3

5

4

Q6B

2N7002KDWH_SOT363-6

0.675VR_EN <37>

4

Security Cla ssification

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2013/12/17 2014/12/17

Compal Sec ret Data

Deciphered Date

Title

Size Document Number Rev

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

DC-DC INTERFACE

LAB412P

Wednesday, January 22, 2014

E

32 41

0.2

of

32 41

of

32 41

of

Function Field :

D

Support 37.1 RTC 38.2 EMI Part 47.1

5

4

3

2

1

Mark Green frame that means this part is not belong to layout module part .

D

PC3

VIN

1

EMI@

1000P_0603_50V7K

2

PC4

C

B

@

PJP1

ACES_50299-00401-001

C

B

DC_IN

1

2

3

4

PF1

5A_32V_0466005.NRHF

2

1

DC_IN_S1

1

EMI@

1000P_0603_50V7K

2

PC1

FBMA-L11-201209-121LMA50T_0805

1

EMI@

100P_0603_50V8

2

PL1

EMI@

PL1

EMI@

FBMA-L11-201209-121LMA50T_0805

1

2

1

2

PL2

EMI@

PL2

EMI@

PC2

1

EMI@

100P_0603_50V8

2

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/11/26 2014/11/26

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

A3

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

DCIN / RTC Battery

LAB412P

33 41Wednesday, January 22, 2014

1

of

A

0.2

Function Field :

Support 37.1 OTP 39.7

D

EMI Part 47.1

5

4

3

2

1

Mark Green frame that means this part is not belong to layout module part .

D

SUYIN_200045MR009G171ZR

C

B

OTP

+3VL

VMB

FBMA-L11-201209-121LMA50T_0805

1

PC5

EMI@

PC5

EMI@

1000P_0402_50V7K

2

PF2

@

PJP2

1

2

3

4

5

6

7

10

GND

11

GND

8

9

BATT_S1

BATT_P5

EC_SMDA

EC_SMCA

PR5

100_0402_1%

+RTC_R

1

PD1

L30ESD24VC3-2_SOT23-3

2

1

2

3

1

PR4

100_0402_1%

2

1

PR3

1K_0402_1%

2

PF2

10A_24V_F1206HB10V024TM

1

PR1

1K_0402_1%

2

PD2

2

3

1

PR2

L30ESD24VC3-2_SOT23-3

6.49K_0402_1%

1

2

BATT_PRES <30>

EC_SMB_DA1 <30,35>

EC_SMB_CK1 <30,35>

EMI@

1

EMI@

PL3

PL4

2

1

PC6

EMI@

PC6

EMI@

0.01U_0402_25V7K

2

BATT+

ADP_I<30,35>

1

PR6

1K_0402_1%

PR8

0_0402_5%

PROCHOT_IN<30>

1

1K_0402_1%

2

1

2

PR7

20K_0402_1%

VCIN0_PH<30>

RecoveryInitial

45W

0.55V 0.43V

UMA

CPU OTP

Initial

90 C 70 C

Recovery

PR9

12.1K_0402_1%

PR10

0_0402_5%

1

PC7

@

PC7

@

0.1U_0402_10V7K

2

+3VL

2

1

2

1

PH1

2

100K_0402_1%_TSM0B104F4251RZ

C

B

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/11/26 2014/11/26

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

A3

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Battery Conn / OTP

LAB412P

1

of

34 41Wednesday, January 22, 2014

of

34 41Wednesday, January 22, 2014

of

34 41Wednesday, January 22, 2014

A

0.2

5

4

3

2

1

Module model information

BQ24735A_V1.mdd

BQ24735A_V2.mdd

D

C

B

A

VIN

5

1

PCB10

2

PRB12

1

2

1M_0402_5%

PQB03

AON6414AL_DFN8-5

4

2200P_0402_50V7K

BQ24725A_ACDRV_1

1

D

2

G

1

2

3

G

PRB11

1

3M_0402_5%

P1

1

2

PRB10@

0_0402_5%

PQB05

2N7002KW_SOT323-3

S

3

SI7716ADN-T1-GE3_POWERPAK8-5

1

2

3

1

2

PCB11

0.1U_0402_25V6

1

PRB16

PRB15

2

4.12K_0603_1%

Vin Dectector

Min. Typ Max. L-->H 17.16V 17.63V 18.12V H-->L 16.76V 17.22V 17.70V

VILIM = 20*ILIM*Rsr ILIM = 3.3*100/(100+107)/20/0.02 = 3.986 A

PQB04

4

Mark Green frame that means this part is not belong to layout module part .

Function Field :

Regulator 40.1 Support 40.2 EMI Part 47.1

P2

5

PCB13

0.1U_0402_25V6

+3VL

ACIN<18,30>

1

PRB17 100K_0402_1%

VIN

1

2

PRB50

0.01_1206_1%

1

2

1

2

PCB14

0.1U_0402_25V6

BQ24725A_ACP

BQ24725A_CMSRC

BQ24725A_ACDRV

2

PRB18

422K_0402_1%

1

PCB16

2

2200P_0402_50V7K

4

3

BQ24725A_ACN

2

PRB19

1

2

1U_0603_25V6K

1

66.5K_0402_1%

2

B+

1UH_NRS4018T1R0NDGJ_3.2A_30%

VIN

VF = 0.5V

2

3

1

PCB15

0.1U_0402_25V6

PRB26

10_1206_1%

2

PCB22

BQ24725A_VCC

1

2

BQ24725A_LX

20

PUB00

21

PAD

VCC

1

ACN

2

ACP

3

CMSRC

4

ACDRV

5

ACOK

ACDET

6

BQ24725A_ACDET

BQ24725A_IOUT

1

PCB17

2

100P_0402_50V8J

Close EC chip

PLB01

EMI@

PLB01

EMI@

1

PDB01

BAS40CW_SOT323-3

PCB01

0.047U_0402_25V7K

1

2

1

PRB25

2

2.2_0603_5%

DH_CHG

BQ24725A_BST

17

18

19

BTST

HIDRV

PHASE

IOUT

SDA

8

@

0_0402_5%

1

PRB20

SCL

9

7

2

1

PCB25

2

VF = 0.37V

1

PDB02

RB751V-40_SOD323-2

2

DH_CHG

1

BQ24725A_REGN

PCB21

1U_0603_25V6K

16

REGN

15

LODRV

14

GND

13

SRP

12

SRN

11

BATDRV

BQ24735RGRR_QFN20_3P5X3P5

ILIM

10

BQ24725A_ILIM

1

PRB22

2

100K_0402_1%

2

1

PCB18

@

PCB18

@

100P_0402_50V8J

2

CHG_B+

1

PCB26

2

10U_0805_25V6K

PRB28

0_0402_5%

1

2

DL_CHG

PRB24

10_0603_1%

SRP

1

PRB23

6.8_0603_1%

SRN

1

BQ24725A_BATDRV

1

PRB21

590K_0402_1%

PCB19

0.01U_0402_25V7K

EC_SMB_CK1 <30,34>

EC_SMB_DA1 <30,34>

ADP_I <30,34>

2

+5VALW

2

PCB23

2200P_0402_25V7K

@EMI@

2

CSOP1

CSON1

1

PCB24

2

0.1U_0402_25V6

@EMI@

5

4

2

3

5

4

2

3

1

2

PCB20

0.1U_0603_16V7K

BQ24725A_BATDRV

PQB01

AON7408L

1

BQ24725A_LX

PQB02

1

AON7406L

PLB03

4.7UH_PCMB063T-1R0MS_12A_20%

1

PRB02@EMI@

2

4.7_1206_5%

1

2

PCB02@EMI@

680P_0402_50V7K

PRB13

309K_0402_1%

PRB14

47K_0402_1%

For A51 ADP_V function

PQB07

SI7716ADN-T1-GE3_POWERPAK8-5

5

BQ24725A_BATDRV_1

1

2

PRB27

4.12K_0603_1%

PRB51

0.01_1206_1%

CHG

1

2

CSOP1

1

PCB28

2

0.1U_0402_25V6

VIN

1

2

1

2

1

2

1

2

3

4

3

CSON1

1

PCB29

2

0.1U_0402_25V6

PCB12

@

PCB12

@

0.1U_0402_10V7K

D

1

PCB27

2

0.01U_0402_50V7K

C

BATT+

1

PCB05

PCB06

2

10U_0805_25V6K

ADP_V <30>

PCB06

10U_0805_25V6K

B

A

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2013/11/26 2014/11/26

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PWR-CHARGER

LAB412P

1

of

35 41Wednesday, January 22, 2014

of

35 41Wednesday, January 22, 2014

of

35 41Wednesday, January 22, 2014

0.2

5

4

3

2

1

Module model information

SY8206B_V2.mdd

Function Field :

Regulator 35.1

D

Support 35.2 EMI Part 47.1

B+

EMI@

HCB2012KF-121T50_0805

1

C

Module model information

SY8208C_V2.mdd

B+

PL351

EMI@

PL351

EMI@

HCB2012KF-121T50_0805

1

B

2

3.3V LDO 150mA~300mA

PL301

2

1

2

PC313

0.1U_0402_25V6

@EMI@

POK<18,30>

+3VL

5V_VIN

3V_VIN

1

2

PC314

2200P_0402_50V7K

EMI@

PR310

100K_0402_1%

1

Mark Green frame that means this part is not belong to layout module part .

2

1

2

3V5V_EN_3

PC312

@

0.047U_0402_16V4Z

ENLDO_3V5V

0_0402_5%

1

2

PR312

1

PC305

2

22U_0603_6.3V6M

2

PR303

PU300

7

EN2

8

IN

1

2

PC311

9

10U_0805_25V6K

2

GND

2

PG

SY8206BQNC_QFN10_3X3

OUT

EN1

LDO

1

3

FB

6

BS

10

LX

4

5

EC_ON<30>

VS_ON<30>

BST_3V

3V5V_EN_3

3V_FB

1

PR301

0_0603_5%

1

PC309

4.7U_0603_6.3V6M

2

0.1U_0603_25V7K

+3VLP

PR306

2.2K_0402_5%

1

PR307

@

PR307

@

1

0_0402_5%

1

2

1

PC301

2

PR308

1M_0402_1%

PC303

0.01U_0402_25V7K

1

2

LX_3V

2.2UH_PCMB063T-1R0MS_12A_20%

1

PR302

2

@EMI@

3V_SN

1

PC302

2

@EMI@

3V5V_EN

1

PC304

2

4.7U_0402_6.3V6M

PR303

1K_0402_5%

1

2

PL303

1

4.7_1206_5%

680P_0603_50V7K

Place to 3V EN1 pin

@

PR311

0_0402_5%

1

2

+3VALWP

1

PC306

PC307

2

22U_0603_6.3V6M

+3VALWP

+3VLP

PCH_PWR_EN <30,32>

PR304

499K_0402_1%

1

PR305

2

1M_0402_1%

+3VALWP

Ipeak : 5A Imax : 3.5A Iocp : 6A FSW : 750KHz

PJ303

@

PJ303

@

1

2

1

2

JUMP_43X118

PJ302

@

PJ302

@

2

1

2

1

JUMP_43X39

D

2

B+

C

+3VALW

+3VL

B

PU350

VCC_3V

1

2

PC365

4.7U_0603_6.3V6M

8

IN

EN1

EN2

BS

9

5

2

LX

GND

OUT

VCC

LDO

PG

SY8208CQNC_QFN10_3X3

1

PC363

2

0.1U_0402_25V6

@EMI@

A

5

1

PC364

2

2200P_0402_50V7K

EMI@

1

PC361

2

PC362

2

10U_0805_25V6K

@

10U_0805_25V6K

3V5V_EN

1

5V_FB

3

BST_5V

6

10

4

7

4

1

PR351

0_0603_5%

1

PC359

2

4.7U_0603_6.3V6M

2

1

PC351

0.1U_0603_25V7K

LX_5V

PC353

6800P_0402_25V7K

1

2

2.2UH_PCMB063T-1R0MS_12A_20%

1

PR352

2

@EMI@

5V_SN

1

2

PC352

@EMI@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

2

1

4.7_1206_5%

680P_0603_50V7K

PR353

1K_0402_5%

1

PL353

3

2

1

PC355

2

22U_0603_6.3V6M

2013/11/26 2014/11/26

1

PC358

PC357

2

22U_0603_6.3V6M

Deciphered Date

PC358

22U_0603_6.3V6M

PC356

22U_0603_6.3V6M

Compal Secret Data

+

2

@

PC360

150U_D2_6.3V_Y

+5VALWP

2

+5VALWP

Ipeak : 8A Imax : 5.6A Iocp : 9A FSW : 750KHz

+5VALWP

Size Document Number Rev

Custom

Date: Sheet

PJ352

@

PJ352

@

1

2

1

2

JUMP_43X118

Title

Compal Electronics, Inc.

+3VALW/+5VALW

+5VALW

LAB412P

1

A

0.2

of

36 41Wednesday, January 22, 2014

of

36 41Wednesday, January 22, 2014

of

36 41Wednesday, January 22, 2014

5

4

3

2

1

Module model information

RT8207M_V1.mdd For Single layer RT8207M_V2.mdd For Dual layer

Function Field :

D

Regulator 35.3 Support 35.4 EMI Part 47.1

PLW01

EMI@

PLW01

EMI@

HCB2012KF-121T50_0805

B+

1

+1.35VP

Ipeak : 9A Imax : 6.3A Iocp : 11A

C

FSW : 550KHz

+1.35VP

1

B

1

2

+1.35VP

1

PCW62

2

PCW63

2

PCW61

22U_0603_6.3V6M

2

1

PCW17

2

0.1U_0402_25V6

@EMI@

PLW03

1UH_VMPI0703AR-1R0M-Z01_11A_20%

1

PCW18

2

EMI@

2200P_0402_50V7K

2

PRW02

@EMI@

PRW02

@EMI@

4.7_1206_5%

PCW02

@EMI@

PCW02

@EMI@

680P_0402_50V7K

+1.35V

PCW64

@

22U_0603_6.3V6M

PJW02

1

PCW66

2

PCW65

2

22U_0603_6.3V6M

2

1

2

1

JUMP_43X118

1

PCW15

2

10U_0805_25V6K

AON7408L_DFN8-5

1

2

1

SI7716ADN

2

1

PCW67

2

@

22U_0603_6.3V6M

+1.35V

1.35V_B+

PCW16

10U_0805_25V6K

PQW01

PQW02

PCW68

@

Mark Green frame that means this part is not belong to layout module part .

D

PRW01

0_0603_5%

2

13.7K_0402_1%

1

VDD_1.35V

1

2

0_0603_5%

1

PRW03

PCW14

1U_0603_10V6K

1

BST_1.35V

1

PCW01

5

4

1

2

3

5

4

1

2

3

0.1U_0603_25V7K

2

+5VALW

PCW01

PRW14

5.1_0603_5%

1

PCW13

1U_0603_10V6K

SYSON<30>

22U_0603_6.3V6M

0.675VR_EN<32>

2

DL_1.35V

CS_1.35V

2

+5VALW

1.35V_B+

BOOT_1.35V

DH_1.35V

SW_1.35V

15

LGATE

14

PGND

13

CS

12

VDDP

11

VDD

PRW12

430K_0402_5%

1

PRW04

@

PRW04

@

0_0402_5%

1

0.1U_0402_10V7K

16

18

17

BOOT

PHASE

UGATE

PUW00

RT8207MZQW_WQFN20_3X3

S5

PGOOD

TON

8

9

10

TON_1.35V

2

PCW12

@

PCW12

@

PRW05

@

PRW05

@

0_0402_5%

EN_1.35V

1

2

1

20

19

VTT

VLDOIN

VTTGND

VTTSNS

VTTREF

FB

S3

6

7

FB_1.35V

EN_0.675VSP

1

PCW11

@

PCW11

@

0.1U_0402_10V7K

2

PAD

GND

VDDQ

21

1

2

3

4

5

VTTREF_1.35V

8.06K_0402_1%

1

PRW11

10K_0402_1%

2

1

+1.35VP

PRW10

+1.35V

1

2

1

PCW06

2

10U_0603_6.3V6M

1

2

+1.35VP

+0.675VSP

PCW07

10U_0603_6.3V6M

PCW10

0.033U_0402_16V7K

C

B

PJW04

@

PJW04

+0.675VSP

A

5

@

1

JUMP_43X39

2

+0.675VS

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2013/11/26

Compal Secret Data

Deciphered Date

2

2014/11/26

Compal Electronics, Inc.

Title

Size Document Number Rev

Wednesday, January 22, 2014

Date: Sheet

DDR / VTT

LAB412P

1

of

37 41

of

37 41

of

37 41

0.2Custom

5

4

3

2

1

Module model information

SY8033_V1.mdd

Function Field :

D

+1.05V Regulator 35.5 +1.05V Support 35.6 +1.0V Regulator 35.27 +1.0V Support 35.28 EMI Part 47.1

EMI@

HCB2012KF-121T50_0805

C

B+

HCB2012KF-121T50_0805

1

PLH01

VCCP_PWRGOOD<32>

2

+3VS

Mark Green frame that means this part is not belong to layout module part .

EN pin don't floating If have pull down resistor at HW side, pls delete PR2

PUH00

B+_1.05V

1

PCH15

PCH14

2

EMI@

2200P_0402_50V7K

2

PCH13

PCH12

0.1U_0402_25V6

@

10U_0805_25V6K

@EMI@

1

PRH11

10K_0402_5%

The current limit is set to 6A, 8A or 12A when this pin is pull low, floating or pull high

VCCP_PWRGOOD

2

ILMT_1.05V

PUH00

8

IN

EN

9

3

2

BS

LX

GND

FB

BYP

ILMT

PG

LDO

SY8208DQNC_QFN10_3X3

1

PRH03

0_0402_5%

2

1

PRH04

@

PRH04

@

0_0402_5%

2

1

6

10

4

7

5

@

BST_1.05V

LX_1.05V

LDO_3V

PRH05

0_0402_5%

1

PCH11

@

PCH11

2

@

0.22U_0402_10V6K

@EMI@

PRH01

0_0603_5%

1

PRH06

1M_0402_1%

0.1U_0603_25V7K

2

PCH01

1

+3VALW

1

PCH17

2

4.7U_0603_6.3V6K

1

Pin 7 BYP is for CS. Common NB can delete +3VALW and PC15

PCH16

2

4.7U_0603_6.3V6K

2

1UH_PCMB063T-1R0MS_12A_20%

PRH02

4.7_1206_5%

1

SUSP# <30,32,39>

@EMI@

SNB_1.05V

2

PLH03

PCH02

680P_0603_50V7K

1

2

1

PRH12

2

1

PRH13

20K_0402_1%

2

15K_0402_1%

+1.05VS_VCCPP

D

Ipeak : 10A Imax : 7A Iocp : 12A FSW : 800KHz

+1.05VS_VCCPP

1

PCH18

2

330P_0402_50V7K

1

PHR14

2

1K_0402_1%

1

2

PCH06

PCH05

47U_0805_6.3V6M

1

2

PCH08

PCH07

22U_0805_6.3VAM

+1.05VS_VCCP

+VCCSA

2

0_0402_5%

PRA5

C

1

@

PJH02

@

PJH02

@

1

JUMP_43X118

PR611

@

1

0.001_1206_1%

VCCIO_SENSE <8>

2

PR611

2

+1.05VS_VCCPP

47U_0805_6.3V6M

VID [0] VID[1] VCCSA Vout 0 0 0.9V

B

0 1 0.85V 1 0 0.775V

B

1 1 0.75V

PJA02

@

PJA02

22U_0603_6.3V6M

@

1

JUMP_43X118

1

PCA04

2

22U_0603_6.3V6M

2

+VCCSA

+VCCSAP

0.9V

1

PCA06

PCA05

2

22U_0603_6.3V6M

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

+1.0VALW / +1.8VALW

LAB412P

1

A

0.2

of

38 41Wednesday, January 22, 2014

of

38 41Wednesday, January 22, 2014

of

38 41Wednesday, January 22, 2014

output voltage adjustable network

+VCCSAP

+3VS

1

PJA01

@

PJA01

@

1

+1.05VS_VCCP

PRA01

2

100K_0402_5%

SA_PGOOD<30>

A

5

1

JUMP_43X118

VCCP_PWRGOOD

1

PCA01

2

22U_0603_6.3V6M

+5VALW

1

2

0_0402_5%

PRA04

@

PRA04

@

4

1

2

1

2

1U_0402_6.3V6K

@

PCA07

PCA08

PUA00

9

PCA02

GND

5

22U_0603_6.3V6M

VIN

6

VPP

7

POK

8

VEN/MODE

G978F11U_S O8

1

2

1U_0603_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

4

Vo

3

Vo

D1

D0

PRA02

@

PRA02

@

2

1

0_0402_5%

1

PRA03

@

PRA03

@

0_0402_5%

3

H_VCCSA_VID1

2

H_VCCSA_VID0

2

2013/11/26 2014/11/26

H_VCCSA_VID1 <9>

H_VCCSA_VID0 <9>

Compal Secret Data

Deciphered Date

1

PCA03

2

5

4

3

2

1

Module model information

SY8033_V1.mdd

Function Field :

D

+1.8V Regulator 35.15 +1.8V Support 35.16 +1.5V Regulator 35.31 +1.5V Support 35.32 EMI Part 47.1

C

B

SUSP#<30,32,38>

SUSP#

1

PRM04

100K_0402_5%

1

PRM05

@

PRM05

@

47K_0402_5%

PR1804

0_0402_5%

1M_0402_1%

2

+3VALW

+1.8VALWP_ON

2

1

PR1805

2

@

JUMP_43X79

4.7U_0603_6.3VAK

+1.5V_EN

1

2

Mark Green frame that means this part is not belong to layout module part .

PC1811

22U_0603_6.3V6M

1

2

PJ1801

@

PJ1801

@

JUMP_43X79

1

2

+1.8VS

1

PJM01

2

PCM11

1

2

PCM12

0.1U_0402_16V7K

2

1

2

PC1813

@

0.1U_0402_16V7K

+5VALW

1

2

SY8032ABC_SOT23-6

4

IN

5

PG

6

FB

1

PCM13

1U_0402_6.3V6K

2

PUM00

APL5930KAI-TRG_SO8

6

VCNTL

5

VIN

9

VIN

8

EN

7

POK

PU1800

GND

1

GND

VOUT

PL1803

1UH_PH041H-1R0MS_3.8A_20%

LX_1.8VALWP

3

LX

2

1

EN

3

4

+1.5V_FB

2

FB

1UH_PH041H-1R0MS_3.8A_20%

1

PR1802

@EMI@

PR1802

@EMI@

4.7_0603_5%

2

1

@EMI@

680P_0402_50V7K

2

FB_1.8VALWP

PC1802

1

PRM11

1.54K_0402_1%

2

1

PRM12

1.74K_0402_1%

2

20K_0402_1%

10K_0402_1%

2

PR1811

PR1812

1

2

1

2

1

2

PCM14

0.01U_0402_25V7K

1

2

PC1812

68P_0402_50V8J

1

PCM05

22U_0603_6.3V6M

2

1

2

PC1805

+1.5VSP

D

+1.8VSP

Ipeak :1A Imax : 0.7A Iocp : 2.5A FSW : 1MHz

+1.8VSP

PJ1803

@

PJ1803

@

1

2

PC1806

22U_0603_6.3V6M

+1.8VSP

1

2

JUMP_43X79

2

+1.8VS

C

+1.5VSP

Ipeak : 0.5A Imax : 0.35A Iocp : 5.7A

PJM02

@

PJM02

+1.5VSP

@

1

JUMP_43X79

2

+1.5VS

B

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

3

2013/11/26 2014/11/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

+1.05VS / +1.5VS

LAB412P

39 41Wednesday, January 22, 2014

1

39 41Wednesday, January 22, 2014

of

A

0.2

A

B

C

D

E

Module model information

ISL95833_V1A.mdd

ISL95833_V1B.mdd

1

Design Note This circuit is for ULV 1+1 17W. CPU: IccMax=33A, TDC=16A(TDP NOM) Loadline: -2.9 m V/A Output Cap. follow Intel PDDG 330uF/9m*3, 22uF_0805*12, 2.2uF_0402*16 GFX(GT2): IccMax=33A, TDC=21.5A Loadline: -3.9 m V/A Output Cap. follow Intel PDDG 330uF/9m*2, 22uF_0805*6, 10uF_0603*6 , 1uF_0402*11

2

VR_ON<30>

VR_SVID _CLK<8>

VR_SVID _ALRT#<8>

VR_SVID _DAT<8>

For VR_HOT#, already pull high at power side.

VR_HOT#<30>

PCZ05

@

PCZ05

@

47P_0402_50V8J

+1.05VS_VCCP

PR18 and PR30

27.4K ohm for 100 degree

3

Layout Note SVID routing

1. Alert# signal must be routed between the Clock and Date lines to reduce the cross talk between them. Signal order arrangement: mobile order is Clock-Alert-Date.

4

2. SVID spacing requirement is 18mils(0.475mm).

3. Maximum total microstrip routing length of each SVID signal must not exceed 6000mils(152.4mm).

4. The SVID bus must be ground reference, It cannot be referenced to input (Vbat or 12V) power plans as they can couple noise into the SVID bus as power states change.

5. Avoid routing under noisy circuit, e.g. switch node , Gate driver, B+, Vin, high speed signal.

6. When SVID signal changes Layer, GND return path may be changed also. We need add GND via for GND reference.

61.9K ohm for 110 degree

470P_0402_50V7K

A

1

PRZ04

@

PRZ04

@

0_0402_5%

1

2

PCZ12

1

2

PCZ13

470P_0402_50V7K

1

2

1.91K_0402_1%

1

PRZ26

PRG16

3.83K_0402_1%

1

2

Close CPU L/S MOS

PRZ19

2K_0402_1%

1

PRZ22

499_0402_1%

Close GFX choke

PHZ04

10K_0402_1%_ERTJ0EG103FA

VSUMG-

1

2

1

PCG11

2

PRG12

11K_0402_1%

.1U_0402_16V7K

VSUMG+

Close GFX L/S MOS

NTCG_1

2

1

PRZ10

499_0402_1%

2

1

PCZ11

@

PCZ11

@

0.1U_0402_16V7K

2

1

137K_0402_1%

11K_0402_1%

PRG11

2

2.61K_0402_1%

After module layout change to ISL95833B(SA000057V10)

PRG15

61.9K_0402_1%

1

2

PHZ01

1

2

470K +-5% ERTJ0EV474J 0402

1

PRZ12

PRZ11

130_0402_1%

54.9_0402_1%

2

1

2

PRZ20

42.2K_0402_1%

1

PCZ14

120P_0402_50V8

1

2

PCZ17

1000P_0402_50V7K

2

1

PRZ27

VCCSENS E<8>

VSSSENSE<8>

1

2

PHZ02

2

+5VS

1

NTC_1

2

1

PRZ16

470K +-5% ERTJ0EV474J 0402

2

330P_0402_50V7K

0.01UF_0402_25V7K

B

1

PCG12

2

0.1U_0402_25V6K

NTCG

SVID_CLK

SVID_ALERT#

SVID_DATA

NTC

PRZ09

@

PRZ09

@

1

0_0402_5%

PRZ13

61.9K_0402_1%

3.83K_0402_1%

@

1

PCZ20

1

PCZ21

6800P_0402_25V7K

1

PRZ05

2K_0402_1%

2

1

PCG14

2

0.022U_0402_25V7K

2

PCG07

2

PRG07

422_0402_1%

1

PUZ00

1

NTCG

2

VR_ON

3

SCLK

4

ALERT#

5

SDA

6

VR_HOT#

7

NTC

8

ISEN2

33

VCC_AXG _SENSE<9>

VSS_AXG_ SENSE<9>

2

29

30

31

32

FBG

PAD

RTNG

ISUMPG

ISUMNG

ISL95833HRTZ-T_TQFN32_4X4

ISEN1

ISUMP

ISUMN

RTN

9

10

11

12

1

PCG05

@

PCG05

@

1000P_0402_50V7K

+3VS

1000P_0402_50V7K

0.01UF_0402_25V7K

PCG08

120P_0402_50V8

1

2

PCG10

1000P_0402_50V8J

1

2

1

2

BOOTA_GFX

UGA_GFX

PHASEA_G FX

LGA_GFX

1

2

1

PRG08

137K_0402_1%

1

PRG13

2

13.3K_0402_1%

1

2

PRG14 1.91K_0402_1%

PCG06

PCG09

470P_0402_50V7K

1

2

499_0402_1%

1

PRG09

2.55K_0402_1%

PRG10

2K_0402_1%

PCG13

330P_0402_50V7K

PRG06

2

1

2

MDV1525 Vds=30V Rds(on)=11.5~14m ohm@Vgs=4.5V

2

UGA_GFX

+5VS

25

26

27

28

1

VDD source use +5VS and PGOOD source use +3VS

PRZ07

1_0603_5%

PRZ06

2

1

2

1

PHZ03

10K_0402_1%_ERTJ0EG103FA

2

1

2

Issued Date

Please confirm power on and down sequence, make sure VGATE after CPU_CORE on.

2

1

PCZ04

2

1U_0603_10V6K

MDV1525 Vds=30V Rds(on)=11.5~14m ohm@Vgs=4.5V

UG1_CPU

PHASE1_ CPU

BOOT_CPU

LG1_CPU

VSUM+

MDU1511 Vds=30V Rds(on)=2.7~3.3m ohm@Vgs=4.5V

PRZ21

2.61K_0402_1%

Close CPU choke

VSUM-

PCZ19

.1U_0402_16V7K

PCZ03

PRZ08 1. 91K_04 02_1%@

LG1_CPU

PHASE1_ CPU

UG1_CPU

BOOT_CPU

+3VS

1

PCZ16

2

1

@

0_0603_5%

2

1U_0603_10V6K

2

1

VGATE <18,30>

1

2

0.1U_0402_25V6K

PRZ25 11K_0402_1%

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET I NFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONI CS, INC.

BOOTG

COMPG

UGATEG

PGOODG

FB

COMP

13

14

1

PRZ23

2K_0402_1%

2

1

PCZ18

2

6800P_0402_25V7K

Cn = L/((Rntcnet*Rsum)/(Rntcnet+Rsum))*DCR) If Cn is correctly selected, when the load current has a square change, the output voltage also has a square response.

15

PGOOD

16

PHASEG

LGATEG

LGATE1

PHASE1

UGATE1

BOOT1

1

2

VCCP

VDD

PWM2

1

PRZ24

422_0402_1%

24

23

22

21

20

19

18

17

2

PRZ141.91K_0402_1%

1

PCZ15

2

0.022U_0402_25V7K

C

Layout Note Reduce Acoustic Noise

1. The AL bulk capacitor of B+ should be very close to CPU_CORE MOSFET.

2. Input ceramic caps must place on symmetry same location on top side and bottom side.

5

PRG03

0_0603_5%

UGA_GFX-1

1

2

MDV1525URH_PDFN33-8-5

PHASEA_G FX

0.1U_0603_25V7K

BOOTA_GFX

1

PRG01

2.2_0603_5%

LGA_GFX

PQG02

MDU1511RH_POWERDFN56-8-5

MDU1511 Vds=30V Rds(on)=2.7~3.3m ohm@Vgs=4.5V

PRZ15

0_0603_5%

UG1_CPU-1

1

2

PQZ01

MDV1525URH_PDFN33-8-5

2.2_0603_5%

PCZ01

1

PRZ01

1

2

0.1U_0603_25V7K

PQZ02

MDU1511RH_POWERDFN56-8-5

2013/11/26 2014/11/26

4

PQG01

PCG01

1

2

4

2

4

Compal Secre t Data

Deciphered Date

D

1

2

3

5

1

2

3

+CPU_B+

5

1

2

3

5

1

2

3

+CPU_B+

1

PCG04

PCG03

2

10U_0805_25V6K

OCP setting=39.9~44.99A

0.22uH DCR= 0.97+-5% m ohm, Idc~Isat= 25~34A

PLG02

0.22UH_FDUE0640J-H-R22M-P3_25A_20%

1

4

3

1

PRG02

@EMI@

PRG02

@EMI@

4.7_1206_5%

2

1

PCG02

@EMI@

PCG02

@EMI@

680P_0402_50V7K

2

1

2

1

PCZ07

PCZ10

2

PCZ06

2

10U_0805_25V6K

1

2

1

2

VSUM+

VSUM-

PRZ02

4.7_1206_5%

@EMI@

PCZ02

680P_0402_50V7K

@EMI@

0.22uH DCR= 0.97+-5% m ohm, Idc~Isat= 25~34A

2

1

3.65K_0402_1%

PRG04

2

VSUMG+

1

PCZ10

2

0.1U_0402_25V6

@EMI@

0.22UH_FDUE0640J-H-R22M-P3_25A_20%

1

2

Title

Size Document Number Rev

Date: Sheet

VSUMG-

PLZ01

FBMA-L11-201209-121LMA50T_0805

1

PLZ05

FBMA-L11-201209-121LMA50T_0805

1

+

Height 6 mm

PCZ09

2

PCZ08

100U_25V_M

OCP setting=39.9~44.99A

EMI@

2200P_0402_50V7K

PLZ02

0.22UH_FDUE0640J-H-R22M-P3_25A_20%

1

4

3

2

3.65K_0402_1%

PRZ17

Compal Electronics, Inc.

CPU/GFX_CORE

LAB412P

E

1

2

1_0402_5%

PRG05

2

1

1_0402_5%

PRZ18

2

+GFX_CORE

B+

+CPU_CORE

1

2

3

4

0.2

of

40 41Wednesday, January 22, 2014

of

40 41Wednesday, January 22, 2014

of

40 41Wednesday, January 22, 2014

D

CPU_Core output CAP (Including MLCC) 36.4

+CPU_CORE

1

PC600

2.2U_0402_6.3V6M

2

1

PC611

2.2U_0402_6.3V6M

2

1

PC634

2.2U_0402_6.3V6M

2

5

1

PC601

2.2U_0402_6.3V6M

2

1

PC612

2.2U_0402_6.3V6M

2

1

PC635

2.2U_0402_6.3V6M

2

1

PC607

2.2U_0402_6.3V6M

2

1

PC613

2.2U_0402_6.3V6M

2

1

PC636

2.2U_0402_6.3V6M

2

1

PC610

2.2U_0402_6.3V6M

2

1

PC614

2.2U_0402_6.3V6M

2

1

PC637

2.2U_0402_6.3V6M

2

4

1

PC608

2.2U_0402_6.3V6M

2

1

PC615

2.2U_0402_6.3V6M

2

1

PC638

2.2U_0402_6.3V6M

2

1

PC639

2.2U_0402_6.3V6M

2

+GFX_CORE

1

PC602

2

22U_0603_6.3V6M

1

2

PC616

10U_0603_6.3V6M

3

2

1

GFX output CAP (Including MLCC) 36.5

1

PC604

PC603

2

22U_0603_6.3V6M

1

PC617

PC618

2

10U_0603_6.3V6M

PC606

PC605

2

22U_0603_6.3V6M

PC609

2

22U_0603_6.3V6M

VCCP output Cap (Including MLCC) 36.6

D

+1.05VS_VCCP

1

PC619

PC620

PC621

2

10U_0603_6.3V6M

PC621

2

10U_0603_6.3V6M

1

PC622

2

10U_0603_6.3V6M

1

PC625

PC623

PC625

PC624

2

22U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6M

10U_0603_6.3V6M

1

PC626

2

22U_0603_6.3V6M

1

PC627

2

22U_0603_6.3V6M

1

PC629

PC630

PC628

PC630

2

22U_0603_6.3V6M

1

PC631

2

22U_0603_6.3V6M

1

PC632

PC633

2

22U_0603_6.3V6M

PC633

2

22U_0603_6.3V6M

C

B

+CPU_CORE

1

PC659

22U_0603_6.3V6M

2

1

PC679

22U_0603_6.3V6M

2

1

PC686

22U_0603_6.3V6M

2

1

PC660

22U_0603_6.3V6M

2

1

PC680

22U_0603_6.3V6M

2

1

PC687

22U_0603_6.3V6M

2

+CPU_CORE

1

+

PC692

330U_D2_2V_Y

2

1

PC681

22U_0603_6.3V6M

2

1

PC688

22U_0603_6.3V6M

2

1

+

PC693

330U_D2_2V_Y

2

1

PC682

22U_0603_6.3V6M

2

1

PC689

22U_0603_6.3V6M

2

1

PC683

22U_0603_6.3V6M

2

1

PC690

22U_0603_6.3V6M

2

1

PC684

22U_0603_6.3V6M

2

1

PC691

22U_0603_6.3V6M

2

1

PC640

2

1

PC661

2

1

+

PC685560U_D2_2VM_R4.5M

2

1

PC641

2

1U_0402_6.3V6K

1

PC662

2

1U_0402_6.3V6K

1

PC643

PC642

2

1U_0402_6.3V6K

1

PC663

2

1U_0402_6.3V6K

1

PC644

PC645

2

1U_0402_6.3V6K

PC664

1U_0402_6.3V6K

PC645

2

1U_0402_6.3V6K

1

PC665

2

1U_0402_6.3V6K

1

PC646

2

1U_0402_6.3V6K

2

1U_0402_6.3V6K

1

PC666

2

1U_0402_6.3V6K

Chief River ULV 330uF*9m 22uF 10uF

CPU

GFX_CORE

2 14

66

1

PC647

PC648

2

1U_0402_6.3V6K

1

PC668

2

PC667

2

1U_0402_6.3V6K

1

PC650

2

PC649

1U_0402_6.3V6K

1

2

PC670

PC669

2

1U_0402_6.3V6K

1

PC651

2

PC652

2

1U_0402_6.3V6K

1

PC671

2

PC672

2

1U_0402_6.3V6K

2.2uF 1uF

1

PC653

PC654

2

1U_0402_6.3V6K

1

PC673

PC674

2

1U_0402_6.3V6K

470uF 560uF

1

PC655

2

1U_0402_6.3V6K

1

PC675

2

1U_0402_6.3V6K

1

PC658

PC656

1U_0402_6.3V6K

PC676

PC658

PC657

2

1U_0402_6.3V6K

1

PC678

2

PC677

2

1U_0402_6.3V6K

C

B

16

11

1

1.05V_VCCP

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/11/26 2014/11/26

3

9

Compal Secret Data

Deciphered Date

3

2

26

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PWR - PROCESSOR DECOUPLING

LAB412P

1

of

41 41Wednesday, January 22, 2014

of

41 41Wednesday, January 22, 2014

of

41 41Wednesday, January 22, 2014

A

0.2

Compal LA-B412P Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual