COMPAL LA-B131P Schematics

A

B

C

D

E

Compal Confidential

MODEL NAME :
PCB NO :

1 1

BOM P/N :

2 2

ZIVY1

LA-B131P

SKU1_4519RY38L05 (I5-4200U 1.6GHZ - Hynix 2G)
SKU2_4519RY38L05 (I5-4200U 1.6GHZ - Micro 2G)
SKU3_4519RY38L08 (I7-4500U 1.8GHZ - Hynix 4G) FAI
SKU3_4519RY38L08 (I7-4510U 1.8GHZ - Hynix 4G) main SMT
SKU4_4519RY38L07 (I2-4200U 1.6GHZ - Micro 4G)
SKU5_4519RY38L05 (I5-4200U 1.6GHZ - Samsung 2G)
SKU6_4519RY38L07 (I5-4200U 1.6GHZ - Samsung 4G)

Compal Confidential

Lamborghini Y40 M/B Schematics Document

Intel Haswell / Broadwell ULT Processor + AMD Venus XTX

3 3

2014-03-03

REV:1.0

4 4

w w w . c h i n a f i x . c o m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2014/03/03 2015/03/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA-B131P

E

of

1 52Tuesday, March 04, 2014

1.0

A

Compal confidential

File Name :ZIVY1

B

C

D

E

AMD Venus XTX (M2)

VRAM 256X16, 128X16

1 1

DDR3 x 8

page 17~24

EDP Conn.

page 25

PCIE x4

eDP x1
2 Lane

Memory BUS

1.35V DDR3L 1600

SATA 3.0

Intel Haswell / Broadwell

ULT Processor

HDMI Conn.

page 28

2 2

LAN( 10/100/1GbE)

RJ45 Conn

Int. Speaker Conn.

page 27

page 26

Realtek RTL8111GUL-CG

page 26

AUDIO CODEC

Realtek ALC283

Combo jack & S/PDIF

page 27

HDMI x 4 lanes

port 3

PCIe 2.0 5GT/s

HD Audio

DDI x1

PCIE x1

Audio/B

3 3

SYS BIOS ROM 8M

WINBOND W25Q64FVSSIQ

page 7

SPI

1168pin BGA

page 04~14

USB 3.0

USB 2.0x8

PCIE x1

PCIE x1

USB 3.0
conn x2

page 32 page 25

WLAN+BT

(NGFF E type)

page 29

204pin DDR3L-SO-DIMM X2

page 15~16

SATA3.0 HDD (SSD)

page 29

USB Charger

TPS2544

page 32

USB 2.0
conn x1

port 3 (Right)port 1, 2 (Left)

CMOS
Camera

Audio/B

Touch Panel

Card Reader

RTS5249-GR

Card Reader
Conn.

page 25

LPC BUS

CLK=24MHz

Sub-board

Power Board

LED Board

4 4

AUDIO Board

w w w . c h i n a f i x . c o m

Audio/B

Card Reader Board

A

B

Lid SW

TCS20DLR

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

KBC

NUVOTON
NPCE288N

PS/2

page 30

Int.KBDTouch Pad

page 31 page 31

2014/03/03 2015/03/03

C

Thermal Sensor

EMC1403-2-AIZL-TR

Compal Secret Data

Deciphered Date

page 31

D

Card Reader/B

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Block Diagram

LA-B131P

E

of

2 52Tuesday, March 04, 2014

1.0

1

2

3

4

5

Voltage Rails

STATE

power
plane

+5VALW

A A

State

S0

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

B B

B+

O

O

O

X

X

+1.35V

+3VALW

O

O

O

X

X X X

+5VS

+3VS

+1.5VS

+1.05VS

+CPU_CORE

+0.675VS

+VGA_CORE

+MEM_GFX

+3VGA

+1.8VGA

+VGA_PCIE

O

X X

X

OO

X

X

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

BOM Structure Table

BTO Item BOM Structure

Unpop

CPU OPTION CPU1@ ~ CPU4@

VRAM Option

DS3

ODS3

N
L

AN RTL8111GUS
EMI PART EMI@
ESD PART
Crystal
Green CLK
SATA Repeater TI@ / Parade @
EC 902 2@ / 9012@
Connector CONN@

SIGNAL

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

ON

ON

ON

ON

ON

ONONON ON

ON

OFF

OFF

HIGH HIGH HIGH HIGH

LOW

LOW

LOW

HIGH

LOWLOWLOW

LOW LOW LOW LOW

@
@CONN@ / @DIS@
@EMI@ / @ESD@

DIS@AMD Venus XTX
V2G@ / V4G@
HYN2@ / HYN4@
SAM2@ / SAM4@
MIC2@ / MIC4@

BDW@ / HSW@Platform
DS3@
NODS3@
SWR@ / LDO@

ESD@
NOGCLK@
GCLK@

HIGHHIGHHIGH

HIGH

HIGH

ON

LOW

OFF

OFF

OFF

OFF

OFF

OFF

ZZZ

V2G@

H5TC2G63FFR-11C

U21

HYN2@

U16

HYN2@

PCB part

2G
X7654038L01

HYN2@

ZZZ

@

DA8000ZQ010

PCB 14P LA-B131P REV1 M/B 4

CPU part (R1)

U9

HSW

I5-4200U_1.6G

SA00006SMC0

BDW

HYN2@

RV6

U20

ZZZ

DAZ14P00100

PCB ZIVY1 LA-B131P LS-B131P/B132/B133 02

CPU3@

U9

R3

CPU1@

R1

I5-4210U_1.7GHZ

SA00007LO10

VRAM * 8 (R1)

H5TC4G63AFR-11C

HYN2@

U14

ZZZ

HYN4@U15

U9

R3

I7-4500U_1.8G

SA00006SLA0

V4G@

SVT

U9

CPU2@

CPU4@

R1

I7-4510U_2GHZ

SA00007M700

SVT

4G
X7654038L04

RV6

U16

HYN4@

U18

HYN4@

U20

HYN4@

HYN4@

EC SM Bus1 address

Device

Smart Battery

Address

0001 0010

PCH SM Bus address

Device Address

DDR_JDIMM1

DDR_JDIMM2

TP module

C C

SMBUS Control Table

SMB_EC_CK1
SMB_EC_DA1

SMBCLK
SMBDATA

SML0CLK
SML0DATA

SML1CLK
SML1DATA

USB2.0

Port 0

D D

Flexible I/O Cap able Ports

HSIO Port

USB 3.0

PCIe

SATA

1010 000x A0h

1010 010x A4h

SOURCEECBATT SODIMM

PCH

PCH

PCH

Left USB3.0 Right USB2.0 Touch Panel BT (NGFF)Left USB3.0

1

1

USB3.0_12USB3.0_2

VGA

X

V

X

X
X

XXX

X

V

1

EC SM Bus2 address

Device

Thermal Sensor

EC-KB9022

X

X

X

V

X

V

432 8765 1211109 1413

CardReader LAN GPU_Venus GPU_VenusGPU_VenusGPU_Venus

Address

1001 101xb

TP

Smart Charge

X

V

X
X

321 64

4321 5-L0

WLAN

Thermal Sensor

Camera

X

X

X

V

5

7

V

X
X
X

w w w . c h i n a f i x . c o m

5-L35-L25-L1

3 2 1

2

6-L36-L26-L16-L0

0

HDD(SSD)

H5TC2G63FFR-11C

U19

HYN2@

H5TC2G63FFR-11C

SA00006H410

Hynix_X7654038L01

U21

MIC2@

MT41J128M16JT-093G:K

MT41J128M16JT-093G:K

U20

SA000067510

MT41J128M16JT-093G:K

MIC2@

MT41J128M16JT-093G:K

Micron_X7654038L02

U15

SAM2@

K4W2G1646Q-BC1A

U20

SAM2@

K4W2G1646Q-BC1A

SA000068U50

Samsung_X7654038L03

3

HYN2@

MIC2@

MIC2@

SAM2@

SAM2@

Compal Secret Data

4

10K_0402_5%

RV8

HYN2@

10K_0402_5%

RV10

HYN2@

10K_0402_5%

RV6

MIC2@

10K_0402_5%

RV8

MIC2@

10K_0402_5%

RV9

MIC2@

10K_0402_5%

RV6

SAM2@

10K_0402_5%

RV7

SAM2@

10K_0402_5%

RV10

SAM2@

10K_0402_5%

Deciphered Date

H5TC2G63FFR-11C

H5TC2G63FFR-11C

U18

U16

K4W2G1646Q-BC1A

K4W2G1646Q-BC1A

H5TC2G63FFR-11C

U17

HYN2@

H5TC2G63FFR-11C

U14

MIC2@

MT41J128M16JT-093G:K

U15

MIC2@

MT41J128M16JT-093G:K

U21

SAM2@

K4W2G1646Q-BC1A

U19

SAM2@

K4W2G1646Q-BC1A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

H5TC2G63FFR-11C

U14

U17

U16

U18

HYN2@

H5TC2G63FFR-11C

U19

MIC2@

MT41J128M16JT-093G:K

MIC2@

U17

MT41J128M16JT-093G:K

SAM2@

U14

K4W2G1646Q-BC1A

U18

SAM2@

K4W2G1646Q-BC1A

2014/03/03 2015/03/03

H5TC4G63AFR-11C

U15

HYN4@

H5TC4G63AFR-11C

SA00006E830

Hynix_X7654038L04

U20

MIC4@

MT41J256M16HA-093G

U21

MIC4@

MT41J256M16HA-093G

SA000077K10

Micron_X7654038L05

U21

SAM4@

K4W4G1646D-BC1A

U20

SAM4@

K4W4G1646D-BC1A

SA000076P10

Samsung_X7654038L06

H5TC4G63AFR-11C

H5TC4G63AFR-11C

U14

MT41J256M16HA-093G

U15

MT41J256M16HA-093G

U14

K4W4G1646D-BC1A

U17

K4W4G1646D-BC1A

H5TC4G63AFR-11C

U17

HYN4@

H5TC4G63AFR-11C

MIC4@

U17

MT41J256M16HA-093G

MIC4@

U16

MT41J256M16HA-093G

U16

SAM4@

K4W4G1646D-BC1A

SAM4@

U15

K4W4G1646D-BC1A

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

U19

MIC4@

MIC4@

SAM4@

SAM4@

H5TC4G63AFR-11C

U21

HYN4@

H5TC4G63AFR-11C

U18

MT41J256M16HA-093G

U19

MT41J256M16HA-093G

U19

K4W4G1646D-BC1A

U18

K4W4G1646D-BC1A

Notes List

LA-B131P

5

MIC4@

MIC4@

SAM4@

SAM4@

HYN4@

10K_0402_5%

RV7

10K_0402_5%

RV9

10K_0402_5%

RV5

10K_0402_5%

RV8

10K_0402_5%

RV10

10K_0402_5%

RV5

10K_0402_5%

RV8

10K_0402_5%

RV9

10K_0402_5%

of

3 52Tuesday, March 04, 2014

HYN4@

HYN4@

MIC4@

MIC4@

MIC4@

SAM4@

SAM4@

SAM4@

1.0

5

D D

4

U9A

HASWELL_MCP_E

3

2

1

C54

DDI1_TXN0

C55

DDI1_TXP0

B58

DDI1_TXN1

C58

DDI1_TXP1

B55

DDI1_TXN2

A55

DDI1_TXP2

A57

DDI1_TXN3

B57

C51
C50
C53
B54
C49
B50
A53
B53

D61
K61
N62

K63

C61

DDI1_TXP3

DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3

U9B

PROC_DETECT
CATERR
PECI

PROCHOT

PROCPWRGD

T1 @

R4
56_0402_5%

1 2

CPU_DP2_N0
CPU_DP2_P0
CPU_DP2_N1
CPU_DP2_P1
CPU_DP2_N2
CPU_DP2_P2
CPU_DP2_N3
CPU_DP2_P3

T2 @

H_PROCHOT#_R

H_CPUPWRGD

C1 0.1U_0402_16V7K

HDMI_TX2-_CK28
HDMI_TX2+_CK28
HDMI_TX1-_CK28

HDMI

C C

HDMI_TX1+_CK28
HDMI_TX0-_CK28
HDMI_TX0+_CK28
HDMI_CLK-_CK28
HDMI_CLK+_CK28

H_PECI30

+1.05VS

H_PROCHOT#30

1 2

C2 0.1U_0402_16V7K

1 2

C3 0.1U_0402_16V7K

1 2

C4 0.1U_0402_16V7K

1 2

C5 0.1U_0402_16V7K

1 2

C6 0.1U_0402_16V7K

1 2

C7 0.1U_0402_16V7K

1 2

C8 0.1U_0402_16V7K

1 2

R3

1 2

62_0402_5%

R5 10K_0402_5%

1 2

DDI EDP

1 OF 19

HASWELL_MCP_E

MISC

JTAG

THERMAL

PWR

EDP_RCOMP

EDP_DISP_UTIL

DDR3 Compensation Signals

B B

DDR3 Compensation Signals:
20mils to comp signals
25mils to non-comp signals
500mil for Max trace length

R6 200_0402_1%

1 2

R7 120_0402_1%

1 2

R8 100_0402_1%

1 2

DDR_PG_CTRL15

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
DIMM_DRAMRST#
DDR_PG_CTRL

AU60
AV60
AU61
AV15
AV61

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_DRAMRST
SM_PG_CNTL1

DDR3

2 OF 19

EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1

EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3

EDP_AUXN
EDP_AUXP

Rev1p2

PROC_TCK

PROC_TMS

PROC_TRST

PROC_TDI

PROC_TDO

PRDY
PREQ

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7

Rev1p2

C45
B46
A47
B47

C47
C46
A49
B49

A45
B45

EDP_COMP

D20

CPU_INV_PWM

A43

EDP_COMP:
Trace width=20 mils,Spacing=25mil,Max length=100mils

J62
K62
E60
E61
E59
F63
F62

J60
H60
H61
H62
K59
H63
K60
J61

EDP_TXN0 25
EDP_TXP0 25
EDP_TXN1 25
EDP_TXP1 25

EDP_AUXN 25
EDP_AUXP 25

R1 24.9_0402_1%

1 2

XDP_TCK
XDP_TMS
XDP_TRST#
XDP_TDI
XDP_TDO

@

eDP

T20

T3@
T4@
T5@
T6@
T7@

+VCCIOA_OUT

+1.35V

12

R9
470_0402_5%

ESD@

H_CPUPWRGD

1

C9
100P_0402_50V8J

2

DIMM_DRAMRST#

1

C338

ESD@

100P_0402_50V8J

A A

2

DIMM_DRAMRST# 15,16

w w w . c h i n a f i x . c o m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2014/03/03 2015/03/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

BDW ULT(1/11) DDI,MSIC,XDP

LA-B131P

1

of

4 52Tuesday, March 04, 2014

1.0

5

D D

U9C

DDR_A_D0

AH63
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57

AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54

AL55
AK55
AR54
AN54
AY58

AW58

AY56

AW56

AV58
AU58
AV56
AU56
AY54

AW54

AY52

AW52

AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22

C C

B B

DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

HASWELL_MCP_E

3 OF 19

DDR CHANNEL A

4

SA_CLK#0

SA_CLK0

SA_CLK#1

SA_CLK1

SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3

SA_CS#0
SA_CS#1

SA_ODT0

SA_RAS

SA_WE

SA_CAS

SA_BA0
SA_BA1
SA_BA2

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8

SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15

SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7

SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7

SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1

AU37
AV37
AW36
AY36

AU43
AW43
AY42
AY43

AP33
AR32

AP32

AY34
AW34
AU34

AU35
AV35
AY41

AU36
AY37
AR38
AP36
AU39
AR36
AV40
AW39
AY39
AU40
AP35
AW41
AU41
AR35
AV42
AU42

AJ61
AN62
AM58
AM55
AV57
AV53
AL43
AL48

AJ62
AN61
AN58
AN55
AW57
AW53
AL42
AL49

AP49
AR51
AP51

DDRA_ODT0

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

SA_CLK_DDR#0 15
SA_CLK_DDR0 15
SA_CLK_DDR#1 15
SA_CLK_DDR1 15

DDRA_CKE0_DIMM 15
DDRA_CKE1_DIMM 15

DDRA_CS0_DIMM# 15
DDRA_CS1_DIMM# 15

T9@

DDR_A_RAS# 15

DDR_A_WE# 15

DDR_A_CAS# 15

DDR_A_BS0 15
DDR_A_BS1 15
DDR_A_BS2 15

SM_DIMM_VREFCA 15
SA_DIMM_A_VREFDQ 15
SA_DIMM_B_VREFDQ 16

3

U9D

DDR_B_D0

AY31

AW31

AY29

AW29

AV31

AU31

AV29

AU29

AY27

AW27

AY25

AW25

AV27

AU27

AV25
AU25
AM29

AK29

AL28

AK28
AR29
AN29
AR28

AP28
AN26
AR26
AR25

AP25

AK26
AM26

AK25

AL25

AY23
AW23

AY21
AW21

AV23
AU23

AV21
AU21

AY19
AW19

AY17
AW17

AV19
AU19

AV17
AU17
AR21
AR22

AL21
AM22
AN22

AP21

AK21

AK22
AN20
AR20

AK18

AL18

AK20
AM20
AR18

AP18

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

2

HASWELL_MCP_E

DDR CHANNEL B

4 OF 19

SB_CK#0

SB_CK0

SB_CK#1

SB_CK1

SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3

SB_CS#0
SB_CS#1

SB_ODT0

SB_RAS

SB_WE

SB_CAS

SB_BA0
SB_BA1
SB_BA2

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8

SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15

SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7

SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7

AM38
AN38
AK38
AL38

AY49
AU50
AW49
AV50

AM32
AK32

AL32

AM35
AK35
AM33

AL35
AM36
AU49

AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46

AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18

AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18

DDRB_ODT0

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

1

SA_CLK_DDR#2 16
SA_CLK_DDR2 16
SA_CLK_DDR#3 16
SA_CLK_DDR3 16

DDRB_CKE2_DIMM 16
DDRB_CKE3_DIMM 16

DDRB_CS2_DIMM# 16
DDRB_CS3_DIMM# 16

T8@

DDR_B_RAS# 16

DDR_B_WE# 16

DDR_B_CAS# 16

DDR_B_BS0 16
DDR_B_BS1 16
DDR_B_BS2 16

Rev1p2

DDR_B_D[0..63]16

DDR_A_D[0..63]15

DDR_A_MA[0..15]15

DDR_A_DQS#[0..7]15

A A

DDR_A_DQS[0..7]15

DDR_B_MA[0..15]16

DDR_B_DQS#[0..7]16

DDR_B_DQS[0..7]16

Rev1p2

w w w . c h i n a f i x . c o m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2014/03/03 2015/03/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

BDW ULT(2/11) DDRIII

LA-B131P

1

5 52Tuesday, March 04, 2014

1.0

of

5

4

3

2

1

GCLK (RG3 close to Y1.1)

RG3

CPU_RTCX1_GCLK34

NOGCLK@

1 2

R10 10M_0402_5%

Y1

D D

C C

1 2

32.768KHZ 12.5PF 9H03200031

NOGCLK@

1

C12

NOGCLK@

15P_0402_50V8J

2

PCH_INTVRMEN

INTVRMEN (+1.05V A)

H：Integrated VRM e nable

*

L：Integrated VRM d isable

RTC CONN place to PWR side

1 2

1

C13

NOGCLK@

15P_0402_50V8J

2

R14 330K_0402_5%

1 2

R15 330K_0402_5%@

1 2

0_0402_5%

PCH_RTCX1

PCH_RTCX2

RTC Battery

W=20mils W=20mils

+RTCVCC

R17 0_0402_5%

C14
1U_0402_6.3V6K

1 2

1

2

+RTCBATT

SIV

SVT

+RTCVCC

PCH_RTCX1

+RTCVCC

R11 20K_04 02_1%

R12 20K_04 02_1%

1U_0603_10V6K

1 2
1 2

C10

1U_0603_10V6K

+RTCVCC

1

C11

Clear ME (TOP)

JME2
SHORT PADS

1 2

2

@

1

Clear CMOS (BOT)

JME1
SHORT PADS

1 2

2

@

CMOS

R13 1M_0402_5%

SVT

HDA_SDIN027

1 2

T10@

T11@
T12@
T13@

T14@
T91@

PCH_RTCX1
PCH_RTCX2
SM_INTRUDER#
PCH_INTVRMEN
PCH_SRTCRST#
PCH_RTCRST#

HDA_BIT_CLK
HDA_SYNC
HDA_RST#
HDA_SDIN0

HDA_SDOUT

PCH_JTAG_RST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

PCH_TCK_JTAGX
PCH_RSVD

U9E

AW5

RTCX1

AY5

RTCX2

AU6

INTRUDER

AV7

INTVRMEN

AV6

SRTCRST

AU7

RTCRST

AW8

HDA_BCLK/I2S0_SCLK

AV11

HDA_SYNC/I2S0_SFRM

AU8

HDA_RST/I2S_MCLK

AY10

HDA_SDI0/I2S0_RXD

AU12

HDA_SDI1/I2S1_RXD

AU11

HDA_SDO/I2S0_TXD

AW10

HDA_DOCK_EN/I2S1_TXD

AV10

HDA_DOCK_RST/I2S1_SFRM

AY8

I2S1_SCLK

AU62

PCH_TRST

AE62

PCH_TCK

AD61

PCH_TDI

AE61

PCH_TDO

AD62

PCH_TMS

AL11

RSVD

AC4

RSVD

AE63

JTAGX

AV2

RSVD

HASWELL_MCP_E

RTC

5 OF 19

JTAG

SATA_IREF

RSVD
RSVD

SATALED

Rev1p2

J5
H5
B15
A15

J8
H8
A17
B17

J6
H6
B14
C15

F5
E5
C17
D17

V1
U1
V6
AC1

A12
L11
K10
C12
U3

PCH_GPIO34
PCH_GPIO35
PCH_GPIO36
PCH_GPIO37

SATA_RCOMP
PCH_SATALED#

SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3

SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2

SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1

SATA_TN2/PETN6_L1

SATAAUDIO

SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0

SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0

SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37

SATA_RCOMP

SATA_PRX_DTX_N0 29
SATA_PRX_DTX_P0 29
SATA_PTX_DRX_N0 29
SATA_PTX_DRX_P0 29

PCH_GPIO35 9
PCH_GPIO36 9
PCH_GPIO37 9

within 500 mils

R16 3.01K_0402_1%

1 2

PCH_SATALED# 9,33

HDD(SSD)

+1.05VS_ASATA3PLL

+3V_PCH

B B

R18 1K_0402_5%@

1 2

HDA_SDOUT

ME debug mode,th is signal has a weak internal PD
Low = Disabled ( Default)

*

High = Enabled [ Flash Descriptor Security Overide ]

1 2

R20 51_0402_5%@

A A

HDA_SDOUT

PCH_JTAG_TCK

RP1

EMI@

HDA_SDOUT_AUDIO27

HDA_SYNC_AUDIO27
HDA_RST_AUDIO#27

HDA_BITCLK_AUDIO27

C15

@EMI@

68P_0402_50V8J

ME_EN30

1 8
2 7
3 6
4 5

33_0804_8P4R_5%

1

2

R21 0_0402_5%

1 2

SIV

HDA_SDOUT
HDA_SYNC
HDA_RST#
HDA_BIT_CLK

+3VS

R19 10K_0402_5%

1 2

PCH_GPIO34

w w w . c h i n a f i x . c o m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2014/03/03 2015/03/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

BDW ULT(3/11)RTC,SATA,JTAG

LA-B131P

1

of

6 52Tuesday, March 04, 2014

1.0

5

PCH_GPIO189

CLK_PCIE_CR#33

Card Reader

D D

LAN

WLAN(NGFF)

dGPU

+3VS

12

R154
10K_0402_5%

GPUCLK_REQ#

R1443
10K_0402_5%

C C

B B

To SPI 8MByte ROM From PCH

A A

1 2

From EC
(For share ROM)

@

SPI ROM ( 8MByte )

CLK_PCIE_CR33
CRCLK_REQ#9,33

CLK_PCIE_LAN#26
CLK_PCIE_LAN26
LANCLK_REQ#9,26

CLK_PCIE_WLAN#29
CLK_PCIE_WLAN29
WLANCLK_REQ#9,29

CLK_PCIE_VGA#17
CLK_PCIE_VGA17

GPUCLK_REQ#18

PCH_GPIO239

+3V_PCH

PCH_SPI_HOLD#_R
PCH_SPI_CLK_R
PCH_SPI_SI_R
PCH_SPI_SO_R

PCH_SPI_CS0#_R

EC_SPI_CS0#30
EC_SPI_CLK30
EC_SPI_MOSI30
EC_SPI_MISO30

22P_0402_50V8J

PCH_SPI_CS0#_R

PCH_SPI_WP#_R

5

PCH_GPIO23

R36 1K_0402_1%

1 2

R37 1K_0402_1%

1 2

R42 33_0402_5%

1 2

RP30

1 8
2 7
3 6
4 5

33_0804_8P4R_5%

EMI@

R38

1 2

RP12

1 8
2 7
3 6
4 5

12

@EMI@

C19

1
2
3
4

33_0804_8P4R_5%

EMI@

U10

@

/CS
DO(IO1)

/HOLD(IO3)
/WP(IO2)
GND

W25Q64FVSSIQ_SO8

LPC_AD030
LPC_AD130
LPC_AD230
LPC_AD330

LPC_FRAME#30

22P_0402_50V8J

0_0402_5%

VCC

CLK

DI(IO0)

8
7
6
5

@EMI@

C325

SVT

+3V_PCH

+3V_ROM
PCH_SPI_HOLD#_RPCH_SPI_SO_R
PCH_SPI_CLK_R
PCH_SPI_SI_R

4

HASWELL_MCP_E

CLOCK

SIGNALS

6 OF 19

HASWELL_MCP_E

LPC

SMBUS

SPI C-LINK

7 OF 19

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#

PCH_SPI_CLK
PCH_SPI_CS0#

12

PCH_SPI_SI
PCH_SPI_SO
PCH_SPI_WP#
PCH_SPI_HOLD#

PCH_SPI_WP#PCH_SPI_WP#_R

PCH_SPI_HOLD#
PCH_SPI_CLK
PCH_SPI_SI
PCH_SPI_SO

PCH_SPI_CS0#

PCH_SPI_CS0#_R
PCH_SPI_CLK_R
PCH_SPI_SI_R
PCH_SPI_SO_R

U9F

C43

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

U2

PCIECLKRQ0/GPIO18

B41

CLKOUT_PCIE_N1

A41

CLKOUT_PCIE_P1

Y5

PCIECLKRQ1/GPIO19

C41

CLKOUT_PCIE_N2

B42

CLKOUT_PCIE_P2

AD1

PCIECLKRQ2/GPIO20

B38

CLKOUT_PCIE_N3

C37

CLKOUT_PCIE_P3

N1

PCIECLKRQ3/GPIO21

A39

CLKOUT_PCIE_N4

B39

CLKOUT_PCIE_P4

U5

PCIECLKRQ4/GPIO22

B37

CLKOUT_PCIE_N5

A37

CLKOUT_PCIE_P5

T2

PCIECLKRQ5/GPIO23

U9G

AU14

LAD0

AW12

LAD1

AY12

LAD2

AW11

LAD3

AV12

LFRAME

AA3

SPI_CLK

Y7

SPI_CS0

Y4

SPI_CS1

AC2

SPI_CS2

AA2

SPI_MOSI

AA4

SPI_MISO

Y6

SPI_IO2

AF1

SPI_IO3

To SPI 8MByte ROM

SDV for HSW SDV for BDW

U10

HSW@

w w w . c h i n a f i x . c o m

4

@

C20 0.1U_0402_16V7 K

1 2

SIV

W25Q64FVSSIQ_SO8

3

XTAL24_IN

A25

XTAL24_IN

XTAL24_OUT

DIFFCLK_BIASREF

TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8

CLKOUT_LPC_0
CLKOUT_LPC_1

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

SMBALERT/GPIO11

SMBCLK

SMBDATA

SML0ALERT/GPIO60

SML0CLK

SML1ALERT/PCHHOT/GPIO73

SML0DATA

SML1CLK/GPIO75

SML1DATA/GPIO74

CL_CLK

CL_DATA

CL_RST

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

XTAL24_OUT

B25

K21

RSVD

M21

RSVD

XCLK_BIASREF

C26

C35
C34
AK8
AL8

CLKOUT_LPC0

AN15
AP15

CLK_BCLK_ITP#

B35

CLK_BCLK_ITP

A35

Rev1p2

AN2
AP2
AH1
AL2
AN1
AK1
AU4
AU3
AH3

AF2
AD2
AF4

Rev1p2

2014/03/03 2015/03/03

GCLK (RG9 close to Y2.1)

CPU_XTAL24_IN_GCLK34

RP31 10K_8P4R_5%

R28 22_0402_5%EMI@

SMBCLK
SMBDATA
PCH_GPIO60
SML0CLK
SML0DATA
PCH_GPIO73
SML1CLK
SML1DATA

T17@
T18@
T19@

Compal Secret Data

R23 3.01K_0402_1%

1 2

3
4
1
2

12

T15@
T16@

PCH_GPIO11 9

PCH_GPIO60 9

PCH_GPIO73 9

Deciphered Date

8
7
6
5

2

RG9

1 2

+1.05VS_AXCK_LCPLL

1

2

2

0_0402_5%

SIV

C18

@EMI@

68P_0402_50V8J

SMBus :DIMMA,DIMMB,TP

FootPrint :DMN66D0LDW-7_SOT363-6

SMBDATA

SMBCLK

SMBDATA PCH_SMB_DATA

SMBCLK

ML1 Bus :EC,Thermal Sensor

S

FootPrint :DMN66D0LDW-7_SOT363-6

SML1CLK

SML1DATA

PCH_SMB_DATA
PCH_SMB_CLK
EC_SMB_DA2
EC_SMB_CK2

SML1CLK
SML1DATA
SMBCLK
SMBDATA

SML0CLK
SML0DATA

XTAL24_IN

SVT

15P_0402_50V8J

+3VS

2

@

6 1

ME2N7002D1KW-G 2N SOT363-6
Q1A

@

3 4

Q1B ME2N7002D1KW-G 2N SOT363-6

1 2

R34

1 2

R35

ME2N7002D1KW-G 2N SOT363-6
Q2A

Q2B ME2N7002D1KW-G 2N SOT363-6

SML1CLK

SML1DATA

RP32

1 8
2 7
3 6
4 5

2.2K_0804_8P4R_5%

RP4

1 8
2 7
3 6
4 5

2.2K_0804_8P4R_5%

R41 2.2K_0402_5%

1 2

R43 2.2K_0402_5%

1 2

Custom

Date: Sheet

1

XTAL24_IN

NOGCLK@

12

R221M_0402_5%

Y2

24MHZ_12PF_7V24000020

1

1

GND

1

NOGCLK@

C16

NOGCLK@

2

5

0_0402_5%

PCH_SMB_CLK

0_0402_5%

+3VS

2

@

6 1

5

@

3 4

1 2

R39

R40

@

Title

Size Document Number Rev

0_0402_5%

1 2

0_0402_5%

Compal Electronics, Inc.

BDW ULT(4/11)CLK,SPI,SMBUS

GND

2

4

CK_LPC_KBC 30

SIT

EC_SMB_CK2

EC_SMB_DA2

+3VS

SIV

+3V_PCH

LA-B131P

1

XTAL24_OUT

3

3

1

C17
15P_0402_50V8J

NOGCLK@

2

PCH_SMB_DATA 15,16,31

PCH_SMB_CLK 15,16,31

EC_SMB_CK2 30,31

EC_SMB_DA2 30,31

SIT

of

7 52Tuesday, March 04, 2014

1.0

5

D D

+3VALW

12

R50
200K_0402_5%

AC_PRESENT30

SYS_PWROK EC_RSMRST#

C C

1

C339

ESD@

100P_0402_50V8J

2

+3V_PCH

R211 10K_0402_5%

1 2

1

C340

ESD@

100P_0402_50V8J

2

SUSWARN#_R

AC_PRESENT

4

Note: SUSACK# and SUSWARN# can be tied together if
EC does not want to involve in the handshake mechanism
for the Deep Sleep state entry and exit

CAN be NC ,if not support Deep Sx

SUSWARN#_R

R210 0_0402_5%@

1 2

DS3

R47 0_0402_5%DS3@

SUSACK#30
SYS_RESET#9
SYS_PWROK30
PCH_PWROK30

EC_RSMRST#30
SUSWARN#30
PBTN_OUT#30

PCH_GPIO729

PCH_GPIO299

ESD

1 2

0_0402_5%

1 2

R46

C21 100P_0402_50V8 J

12

ESD@

DS3

R209 0_0402_5%DS3@

1 2

INVPWM25
ENBKL25,30
PCH_ENVDD25

DGPU_PWROK9,45

DGPU_PWR_EN9,19,30,41,42

DGPU_HOLD_RST#17

WLBT_OFF#9,29

PCH_GPIO559
PCH_GPIO529
PCH_GPIO549

PCH_GPIO519
PCH_GPIO539

SIT

R51

PCH_GPIO55
PCH_GPIO52
PCH_GPIO54

PCH_GPIO53

T25 @

SIT

0_0402_5%

1 2

SYS_RESET#
SYS_PWROK
PCH_PWROK
APWROK_R

CPU_PLT_RST#

EC_RSMRST#
SUSWARN#_R
PBTN_OUT#
AC_PRESENT
PCH_GPIO72

PCH_GPIO29

EDP_BKCTL

T28 @

3

U9H

AK2

SUSACK

AC3

SYS_RESET

AG2

SYS_PWROK

AY7

PCH_PWROK

AB5

APWROK

AG7

PLTRST

AW6

RSMRST

AV4

SUSWARN/SUSPW RDNACK/GPIO30

AL7

PWRBTN

AJ8

ACPRESENT/GPIO31

AN4

BATLOW/GPIO72

AF3

SLP_S0

AM5

SLP_WLAN/GPIO29

U9I

B8

EDP_BKLCTL

A9

EDP_BKLEN

C6

EDP_VDDEN

U6

PIRQA/GPIO77

P4

PIRQB/GPIO78

N4

PIRQC/GPIO79

N2

PIRQD/GPIO80

AD4

PME

U7

GPIO55

L1

GPIO52

L3

GPIO54

R5

GPIO51

L4

GPIO53

HASWELL_MCP_E

SYSTEM POWER MANAGEMENT

HASWELL_MCP_E

eDP SIDEBAND

GPIO

DPWROK: Tired to ghter with RSMRS T#
that do not supp ort Deep Sx

DSWVRMEN

DPWROK

WAKE

CLKRUN/GPIO32

SUS_STAT/GPIO61

SUSCLK/GPIO62

SLP_S5/GPIO63

SLP_S4
SLP_S3

SLP_A
SLP_SUS
SLP_LAN

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPB_AUXN

DDPC_AUXN

DDPB_AUXP
DDPC_AUXP

DDPB_HPD
DDPC_HPD

EDP_HPD

Rev1p2

8 OF 19

DISPLAY

2

AW7
AV5
AJ5

V5
AG4
AE6
AP5

AJ6
AT4
AL5
AP4
AJ7

DDI1_CTRL_CK

B9
C9

DDI2_CTRL_CK

D9

DDI2_CTRL_DATA

D11

C5
B6
B5
A6

C8
A8
D6

DSWODVRENSUSACK#_R
DPWROK

PCH_GPIO32

SUSCLK
PM_SLP_S5#

PM_SLP_S4#
PM_SLP_S3#
PM_SLP_A#

DSWODVREN - On Die DSW VR Enable
(*) H：：：：Enable(DEFAULT)
( ) L：：：：Disable

R44 330K_0402_5%

1 2

R45 330K_0402_5%@

1 2

DS3

R212 0_0402_5%DS3@

1 2

R48 0_0402_5%NODS3@

1 2

R49 10K_0402_5%

PCH_PCIE_WAKE#

1 2

T21

@

T22

@

T24@

T27@

DDI2_CTRL_CK 28

DDI2_CTRL_DATA 28

T99@

DDI2_HDMI_HPD 9,28
EDP_HPD 25

T23

@

DS3

DDI1_CTRL_CK

DDI1_CTRL_DATADDI1_CTRL_DATA

1

+RTCVCC

EC_RSMRST#

PCH_PCIE_WAKE# 9,29

PCH_GPIO32 9

SUSCLK 29
PM_SLP_S5# 30

PM_SLP_S4# 30
PM_SLP_S3# 30

SLP_SUS# 30

R58 2.2K_0402_5%@

1 2

R52 2.2K_0402_5%@

1 2

DDPB_CTRLDATA: Port B Detected
DDPC_CTRLDATA: Port C Detected

1: Port B or C is detected

*

0: Port B or C is not detected
(Have internal PD)

DPWROK_EC 30

+3VS

9 OF 19

B B

SIT

0_0402_5%

R53

1 2

V0.2

CPU_PLT_RST#

MC74VHC1G08DFT2G_SC70-5

A A

+3VS

SVT

5

U11

@

2

P

B

4

Y

1

A

12

G

3

R54

100K_0402_5%

Rev1p2

PLT_RST# 17,26,29,30,33

w w w . c h i n a f i x . c o m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2014/03/03 2015/03/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

BDW ULT(5/11) PM,GPIO,DDI

LA-B131P

1

of

8 52Tuesday, March 04, 2014

1.0

5

+3VS

1 8
2 7
3 6
4 5

D D

C C

B B

A A

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 2

R276 10K_0402_5%

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 2

R170 1K_0402_5%

PCH_GPIO50
SERIRQ
PCH_GPIO17

RP5 10K_8P4R_5%

PCH_GPIO83
PCH_GPIO2

RP6 10K_8P4R_5%

PCH_GPIO65
PCH_GPIO64
PCH_GPIO1
PCH_GPIO3

RP7 10K_8P4R_5%

KB_RST#

RP8 10K_8P4R_5%

PCH_GPIO33

RP9 10K_8P4R_5%

PCH_GPIO48
PCH_GPIO71

RP2 10K_8P4R_5%

PCH_GPIO87
PCH_GPIO94
PCH_GPIO69

RP23 10K _8P4R_5%

PCH_GPIO38

RP26 10K _8P4R_5%

PCH_GPIO0
EC_SCI#
PCH_GPIO68
PCH_GPIO67

RP24 10K _8P4R_5%

PCH_GPIO4
PCH_GPIO5
PCH_GPIO6
PCH_GPIO7

RP25 2.2K_0 804_8P4R_5%

PCH_GPIO49
PCH_GPIO16

RP13 10K _8P4R_5%

PCH_GPIO89
PCH_GPIO85
PCH_GPIO92

RP28 10K _8P4R_5%

PCH_GPIO84
PCH_GPIO90
PCH_GPIO93
PCH_GPIO91

RP29 10K _8P4R_5%

HDA_SPKR

@

5

PCH_GPIO18 7

PCH_GPIO51 8
WLBT_OFF# 8,29

PCH_GPIO36 6
CRCLK_REQ# 7,33

LANCLK_REQ# 7,26

PCH_GPIO53 8
PCH_GPIO52 8
WLANCLK_REQ# 7,29

DGPU_PWR_EN 8,19,30,41,42

PCH_SATALED# 6,33
PCH_GPIO35 6

DGPU_PWROK 8,45

PCH_GPIO55 8
PCH_GPIO32 8
PCH_GPIO54 8

SYS_RESET# 8
PCH_GPIO37 6

SIT

PCH_GPIO23 7

SIV

SIT

+3V_PCH

SIV

4

1 8
2 7
3 6
4 5

RP14 10K _8P4R_5%

1 8
2 7
3 6
4 5

RP16 10K _8P4R_5%

1 8
2 7
3 6
4 5

RP18 10K _8P4R_5%

1 8
2 7
3 6
4 5

RP11 10K _8P4R_5%

1 8
2 7
3 6
4 5

RP15 10K _8P4R_5%

1 8
2 7
3 6
4 5

RP17 10K _8P4R_5%

PCH_GPIO58
PCH_GPIO10

PCH_GPIO13

PCH_GPIO8
PCH_GPIO12

PCH_GPIO26

PCH_GPIO57

PCH_GPIO24
PCH_GPIO46

PCH_GPIO14

PCH_GPIO59
PCH_GPIO44

PCH_GPIO47
PCH_GPIO28
PCH_GPIO45
PCH_GPIO56

DDI2_HDMI_HPD8,28

SIV

EC_SCI#30

HDA_SPKR27

PCH_GPIO60 7

PCH_GPIO11 7

USB_OC1# 10,32

PCH_GPIO72 8
PCH_GPIO43 10

PCH_GPIO42 10

USB_OC0# 10,32
PCH_GPIO73 7

PCH_GPIO8
PCH_GPIO12
PCH_GPIO15
PCH_GPIO16
PCH_GPIO17
PCH_GPIO24
PCH_GPIO27
PCH_GPIO28
PCH_GPIO26

PCH_GPIO56
PCH_GPIO57
PCH_GPIO58
PCH_GPIO59
PCH_GPIO44
PCH_GPIO47
PCH_GPIO48
PCH_GPIO49
PCH_GPIO50
PCH_GPIO71
PCH_GPIO13
PCH_GPIO14
PCH_GPIO25
PCH_GPIO45
PCH_GPIO46

PCH_GPIO10
PCH_GPIO33

PCH_GPIO38
EC_SCI#
HDA_SPKR

SIT

SIT

+3VALW

3

1 8
2 7
3 6
4 5

U9J

P1

BMBUSY/GPIO76

AU2

GPIO8

AM7

LAN_PHY_PWR_CTRL/GPIO12

AD6

GPIO15

Y1

GPIO16

T3

GPIO17

AD5

GPIO24

AN5

GPIO27

AD7

GPIO28

AN3

GPIO26

AG6

GPIO56

AP1

GPIO57

AL4

GPIO58

AT5

GPIO59

AK4

GPIO44

AB6

GPIO47

U4

GPIO48

Y3

GPIO49

P3

GPIO50

Y2

HSIOPC/GPIO71

AT3

GPIO13

AH4

GPIO14

AM4

GPIO25

AG5

GPIO45

AG3

GPIO46

AM3

GPIO9

AM2

GPIO10

P2

DEVSLP0/GPIO33

C4

SDIO_POWER_EN/GPIO70

L2

DEVSLP1/GPIO38

N5

DEVSLP2/GPIO39

V2

SPKR/GPIO81

PCH_GPIO25
PCH_GPIO27

RP27 10K_8P4R_5%

HASWELL_MCP_E

GPIO

10 OF 19

PCH_GPIO29 8
PCH_PCIE_WAKE# 8,29

+3VS

2

THERMTRIP

RCIN/GPIO82

CPU/
MISC

LPIO

Platform
BDW => R200 stuff (BDW@)
HSW => R202 stuff (HSW@)

BDW@

1 2

R200 10K_0402_5%

HSW@

1 2

R202 10K_0402_5%

SERIRQ

PCH_OPI_RCOMP

GSPI0_CS/GPIO83

GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86

GSPI1_CS/GPIO87

GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89

GSPI_MOSI/GPIO90
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART0_RTS/GPIO93
UART0_CTS/GPIO94

UART1_RXD/GPIO0

UART1_TXD/GPIO1
UART1_RST/GPIO2
UART1_CTS/GPIO3

I2C0_SDA/GPIO4

I2C0_SCL/GPIO5

I2C1_SDA/GPIO6

I2C1_SCL/GPIO7

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69

PCH_GPIO88

RSVD
RSVD

Rev1p2

D60
V4
T4
AW15
AF20
AB21

R6
L6
N6
L8
R7
L5
N7
K2
J1
K3
J2
G1
K4
G2
J3
J4
F2
F3
G4
F1
E3
F4
D3
E4
C3
E2

+1.05VS

12

R56

1K_0402_1%

H_THERMTRIP#

PCH_OPIRCOMP

PCH_GPIO83
PCH_GPIO84
PCH_GPIO85
PCH_GPIO86

PCH_GPIO88
PCH_GPIO89
PCH_GPIO90
PCH_GPIO91
PCH_GPIO92
PCH_GPIO93
PCH_GPIO94
PCH_GPIO0
PCH_GPIO1
PCH_GPIO2
PCH_GPIO3
PCH_GPIO4
PCH_GPIO5
PCH_GPIO6
PCH_GPIO7
PCH_GPIO64
PCH_GPIO65
PCH_GPIO66
PCH_GPIO67
PCH_GPIO68
PCH_GPIO69

1 2

R57

49.9_0402_1%

SIT

PCH_GPIO87 25

GPIO87 : Touch / Non-Touch

1: Non-Touch

*

0: Touch

H_THERMTRIP#

PCH_GPIO86

R60 1K_0402_1%@
R61 1K_0402_1%

KB_RST# 30

SERIRQ 30

SDV

ESD@

C22 100P_0402_50V8J

1 2

1 2
1 2

GSPI0_MOSI / GPIO86 : Boot BIOS Strap

1: LPC BUS

0: SPI BUS

*

PCH_GPIO66

(Have internal PD)

R205

1 2

SDIO_D0 / GPIO66 : Top-Block Swap Override

1: DISABLED

*

0: ENABLED

+3V_PCH

(Have internal PD)

R69

@

1 2

1K_0402_1%

GPIO15 : TLS Confidentiality

1: Intel ME TLS with confidentiality

0: Intel ME TLS with no confidentiality

*

(Have internal PD)

1

+3VS

+3VS

150K_0402_1%

PCH_GPIO15

w w w . c h i n a f i x . c o m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2014/03/03 2015/03/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

BDW ULT(6/11) GPIO,LPIO

LA-B131P

1

of

9 52Tuesday, March 04, 2014

1.0

5

4

3

2

1

PCIe

HASWELL_MCP_E

11 OF 19

AN8

USB2N0

AM8

USB2P0

AR7

USB2N1

AT7

USB2P1

AR8

USB2N2

AP8

USB2P2

AR10

USB2N3

AT10

USB2P3

AM15

USB2N4

AL15

USB2P4

AM13

USB2N5

AN13

USB2P5

AP11

USB2N6

AN11

USB2P6

AR13

USB2N7

AP13

USB2P7

G20

USB3RN1

H20

USB

USB3RP1

USB3TN1
USB3TP1

USB3RN2
USB3RP2

USB3TN2
USB3TP2

USBRBIAS
USBRBIAS

RSVD
RSVD

OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43

Rev1p2

C33
B34

E18
F18

B33
A33

AJ10
AJ11
AN10
AM10

AL3
AT1
AH2
AV3

USBRBIAS

R71 22.6_0402_1%

1 2

T92@
T93@

USB20_N0 32
USB20_P0 32

USB20_N1 32
USB20_P1 32

USB20_N2 32
USB20_P2 32

USB20_N4 25
USB20_P4 25

USB20_N5 25
USB20_P5 25

USB20_N6 29
USB20_P6 29

USB3_RX1_N 32
USB3_RX1_P 32

USB3_TX1_N 32
USB3_TX1_P 32

USB3_RX2_N 32
USB3_RX2_P 32

USB3_TX2_N 32
USB3_TX2_P 32

CAD note:
Route single-end 50-ohms and max 450-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15 mils

USB_OC0# 9,32
USB_OC1# 9,32
PCH_GPIO42 9
PCH_GPIO43 9

Left USB2/3 IO (MB)

Left USB2/3 IO (MB)

Right USB2.0 (IO/B)

Touch Panel

Camera

BT (NGFF)

USB2/3 IO (MB)

USB2/3 IO (MB)

D D

PCIE_CRX_GTX_N017
PCIE_CRX_GTX_P017

PCIE_CTX_GRX_N017
PCIE_CTX_GRX_P017

PCIE_CRX_GTX_N117
PCIE_CRX_GTX_P117

dGPU

LAN

C C

WLAN(NGFF)

Card Reader

PCIE_CTX_GRX_N117
PCIE_CTX_GRX_P117

PCIE_CRX_GTX_N217
PCIE_CRX_GTX_P217

PCIE_CTX_GRX_N217
PCIE_CTX_GRX_P217

PCIE_CRX_GTX_N317
PCIE_CRX_GTX_P317

PCIE_CTX_GRX_N317
PCIE_CTX_GRX_P317

PCIE_PRX_DTX_N326
PCIE_PRX_DTX_P326

PCIE_PTX_C_DRX_N326
PCIE_PTX_C_DRX_P326

PCIE_PRX_DTX_N429

PCIE_PRX_DTX_P429

PCIE_PTX_C_DRX_N429
PCIE_PTX_C_DRX_P429

PCIE_PRX_DTX_N233
PCIE_PRX_DTX_P233

PCIE_PTX_C_DRX_N233
PCIE_PTX_C_DRX_P233

+1.05VS_AUSB3PLL

C23 0.22U_0402_10V6K

1 2

C24 0.22U_0402_10V6K

1 2

C25 0.22U_0402_10V6K

1 2

C26 0.22U_0402_10V6K

1 2

C27 0.22U_0402_10V6K

1 2

C28 0.22U_0402_10V6K

1 2

C29 0.22U_0402_10V6K

1 2

C30 0.22U_0402_10V6K

1 2

C31 0.1U_0402_16V7K

1 2

C32 0.1U_0402_16V7K

1 2

C33 0.1U_0402_16V7K

1 2

C34 0.1U_0402_16V7K

1 2

C35 0.1U_0402_16V7K

1 2

C36 0.1U_0402_16V7K

1 2

R72 3.01K_0402_1%

1 2

PCIE_PTX_DRX_N5_L0
PCIE_PTX_DRX_P5_L0

PCIE_PTX_DRX_N5_L1
PCIE_PTX_DRX_P5_L1

PCIE_PTX_DRX_N5_L2
PCIE_PTX_DRX_P5_L2

PCIE_PTX_DRX_N5_L3
PCIE_PTX_DRX_P5_L3

PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P3

PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4

PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2

PCIE_RCOMP

F10

PERN5_L0

E10

PERP5_L0

C23

PETN5_L0

C22

PETP5_L0

F8

PERN5_L1

E8

PERP5_L1

B23

PETN5_L1

A23

PETP5_L1

H10

PERN5_L2

G10

PERP5_L2

B21

PETN5_L2

C21

PETP5_L2

E6

PERN5_L3

F6

PERP5_L3

B22

PETN5_L3

A21

PETP5_L3

G11

PERN3

F11

PERP3

C29

PETN3

B30

PETP3

F13

PERN4

G13

PERP4

B29

PETN4

A29

PETP4

G17

PERN1/USB3RN3

F17

PERP1/USB3RP3

C30

PETN1/USB3TN3

C31

PETP1/USB3TP3

F15

PERN2/USB3RN4

G15

PERP2/USB3RP4

B31

PETN2/USB3TN4

A31

PETP2/USB3TP4

E15

RSVD

E13

RSVD

A27

PCIE_RCOMP

B27

PCIE_IREF

U9K

B B

USB2.0

Port 0

Left USB3.0 Ri ght USB2.0 Touch Panel BT (NGFF)Left USB3.0

321 64

5 7

Camera

Flexible I/O Capable Ports

HSIO Port

USB 3.0

PCIe

A A

SATA

1

1

USB3.0_12USB3.0_2

432 8765 1211109 1413

CardReader

4321 5-L0

WLANLAN GPU_Venus GPU_VenusGPU_VenusGPU_Venus

5-L35- L25-L1

3 2 1

6-L36- L26- L16-L0

0

HDD(SSD)

w w w . c h i n a f i x . c o m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2014/03/03 2015/03/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

BDW ULT(7/11) PCIE,USB

LA-B131P

1

10 52Tuesday, March 04, 2014

1.0

of

5

D D

VCCST_PWRGD30

C C

VCCST_PWRGD

SVID ALERT

+1.05VS

12

VR_SVID_ALRT#46

Place the PU
resistors close to C PU

R74
75_0402_5%

R75
43_0402_1%

12

H_CPU_SVIDALRT#

SVID DATA

+1.05VS

Place the PU
resistors close to C PU

12

R77

B B

VR_SVID_DAT46

SIT

1 2

R79

0_0402_5%

+CPU_CORE

110_0402_5%

H_CPU_SVIDDATA

R77:
CRB r0.7 changed from 130 Ohms to
110 Ohms

+1.05VS

12

4

R73
10K_0402_5%

+1.05VS

@

@

R76
150_0402_1%

1 2

R78
10K_0402_5%

1 2

connect to PWR

R76: CPU_PWR_DEBUG
CRB mount
Check list ,XDP use only

CPU_PWR_DEBU G

VR_SVID_CLK46

VR_ON46

VGATE46

RF

C38

@

68P_0402_50V8J

3

+VCCIOA_OUT

VR_SVID_CLK

1

2

+1.35V

1

2

SIV

+1.35V

+CPU_CORE

T29

@

R151 10K_0402_5%

+CPU_CORE

1 2

+1.05VS

VCCSENSE

+VCCIO_OUT_R

H_CPU_SVIDALRT#
VR_SVID_CLK
H_CPU_SVIDDATA
VCCST_PWRGD

CPU_PWR_DEBU G

T30 @

T31 @
T32 @
T33 @
T34 @
T35 @
T36 @
T37 @
T38 @
T39 @
T40 @
T41 @
T42 @
T43 @

VDDQ DECOUPLING

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

@

C42

C41

1

2

CRB:
+1.35V : 470UF/2V/7343 *2 (Un-mount)
10UF/6.3V/0603 * 6

2.2UF/6.3V/0402 * 4

C49

C43

1

2

10U_0603_6.3V6M

1

1

1

C50

2

2

2

2

U9L

L59

RSVD

J58

RSVD

AH26

VDDQ

AJ31

VDDQ

AJ33

VDDQ

AJ37

VDDQ

AN33

VDDQ

AP43

VDDQ

AR48

VDDQ

AY35

VDDQ

AY40

VDDQ

AY44

VDDQ

AY50

VDDQ

F59

VCC

N58

RSVD

AC58

RSVD

E63

VCC_SENSE

AB23

RSVD

A59

VCCIO_OUT

E20

VCCIOA_OUT

AD23

RSVD

AA23

RSVD

AE59

RSVD

L62

VIDALERT

N63

VIDSCLK

L63

VIDSOUT

B59

VCCST_PWRGD

F60

VR_EN

C59

VR_READY

D63

VSS

H59

PWR_DEBUG

P62

VSS

P60

RSVD_TP

P61

RSVD_TP

N59

RSVD_TP

N61

RSVD_TP

T59

RSVD

AD60

RSVD

AD59

RSVD

AA59

RSVD

AE60

RSVD

AC59

RSVD

AG58

RSVD

U59

RSVD

V59

RSVD

AC22

VCCST

AE22

VCCST

AE23

VCCST

AB57

VCC

AD57

VCC

AG57

VCC

C24

VCC

C28

VCC

C32

VCC

10U_0603_6.3V6M

10U_0603_6.3V6M

C44

10U_0603_6.3V6M

1

2

@

1

C51

C45

2

SIV

HASWELL_MCP_E

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

12 OF 19

HSW ULT POWER

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

2

C52

C46

2

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

Rev1p2

C36
C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
U57
W57

1

+CPU_CORE

12

R80
100_0402_1%

CAD Note: PU resistor should be close to CPU

CAD Note: PD resistor should be close to CPU

w w w . c h i n a f i x . c o m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2014/03/03 2015/03/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

BDW ULT(8/11) Power

LA-B131P

1

of

11 52Tuesday, March 04, 2014

1.0

12

R81
100_0402_1%

VCCSENSE

VSSSENSE

VCCSENSE46

A A

VSSSENSE13,46

5

5

D D

4

3

2

1

Check Power Source

+1.05VS +1.05VS_AUSB3PLL

L1

1 2

2.2UH_LQM2MPN2R2NG0L_30%

+1.05VS_ASATA3PLL

L2

1 2

2.2UH_LQM2MPN2R2NG0L_30%

+1.05VS_APLLOPI

C C

B B

A A

L3

1 2

2.2UH_LQM2MPN2R2NG0L_30%

L4

1 2

2.2UH_LQM2MPN2R2NG0L_30%

L5

1 2

2.2UH_LQM2MPN2R2NG0L_30%

+1.05VS

+1.05VS

+3V_PCH

+3V_PCH

C57 1U_0402_6.3V6K@

C80 1U_0402_6.3V6K
C82 1U_0402_6.3V6K

C84 22U_0603_6.3V6M

C85 22U_0603_6.3V6M

+3VS

C86 1U_0402_6.3V6K

+1.05VS

C87 1U_0402_6.3V6K

+1.05VS

C88 1U_0402_6.3V6K

+3VALW

C83 0.47U_0402_16V4Z

5

+1.05VS_AXCK_DCB

+1.05VS_AXCK_LCPLL

Close to N8

1 2

Close to K9,M9

1 2
1 2

Close to AC9/AA9/AE20/AE21

1 2

Close to V8

1 2

Close to J17

1 2

Close to R21

1 2

Close to AH14

V1.0

1 2

C58 1U_0402_6.3V6K
C59 22U_0805_6.3V6M
C37 47U_0805_6.3V6M@

C60 1U_0402_6.3V6K
C62 47U_0805_6.3V6M@
C138 22U_0805_6.3V6M

C65 1U_0402_6.3V6K
C66 22U_0805_6.3V6M@
C333 47U_0805_6.3V6M@

C68 1U_0402_6.3V6K
C70 47U_0805_6.3V6M@
C334 22U_0805_6.3V6M

C73 1U_0402_6.3V6K
C75 22U_0805_6.3V6M
C335 47U_0805_6.3V6M@

12

@

1 2
1 2
1 2

1 2
1 2
1 2

1 2
1 2
1 2

1 2
1 2
1 2

1 2
1 2
1 2

+PCH_VCCDSW

+3V_PCH

C72
1U_0402_6.3V6K

1 2

18mA

Share ROM

+1.05VS

658mA

+1.05VS

+RTCVCC

C79

1U_0402_6.3V6K

1

2

SIT

SIT

+1.05VS_AUSB3PLL

+1.05VS_ASATA3PLL

+1.05VS_APLLOPI

SIT
SIV

SIT

+3VALW

SIT

+1.05VS_AXCK_DCB

+1.05VS_AXCK_LCPLL

+1.05VS

+1.05VS

T44 @

+3VALW

T45 @

+3V_PCH

+3VS

+1.05VS
+1.05VS

+3V_PCH

AA21

W21

AH14

AH13

AC9

AH10

M20

AE20
AE21

L10

M9
N8

B18
B11

Y20

J13

AA9

W9

J18
K19
A20

J17
R21
T21
K18

V21

K9

VCCHSIO
VCCHSIO
VCCHSIO
VCC1_05

P9

VCC1_05
VCCUSB3PLL
VCCSATA3PLL

RSVD
VCCAPLL
VCCAPLL

DCPSUS3

VCCHDA

DCPSUS2

VCCSUS3_3
VCCSUS3_3
VCCDSW3_3

V8

VCC3_3
VCC3_3

VCCCLK
VCCCLK
VCCACLKPLL
VCCCLK
VCCCLK
VCCCLK
RSVD
RSVD
RSVD
VCCSUS3_3
VCCSUS3_3

mPHY

OPI

USB3

AXALIA/HDA

VRM/USB2/AZALIA

GPIO/LCC

LPT LP POWER

HASWELL_MCP_E

13 OF 19

RTC

SPI

CORE

THERMAL SENSOR

SDIO/PLSS

SUS OSCILLATOR

USB2

VCCSUS3_3

VCCRTC
DCPRTC

VCCSPI

VCCASW
VCCASW

VCC1_05
VCC1_05
VCC1_05
VCC1_05

VCC1_05
DCPSUSBYP
DCPSUSBYP

VCCASW

VCCASW

VCCASW

DCPSUS1
DCPSUS1

VCCTS1_5

VCC3_3
VCC3_3

VCCSDIO
VCCSDIO

DCPSUS4

RSVD
VCC1_05
VCC1_05

Rev1p2

C61 1U_0402_6.3V6K

AH11
AG10
AE7

+VCCRTCEXT

Y8

AG14
AG13

J11
H11
H15
AE8
AF22
AG19
AG20
AE9
AF9
AG8
AD10
AD8

J15
K14
K16

U8
T9

AB8

AC20
AG16
AG17

C64 0.1U_0 402_16V7K

C67 10U_0603_6.3V6M
C69 1U_0402_6.3V6K
C71 1U_0402_6.3V6K

+PCH_VCCDSW

C74 22U_0603_6.3V6M@
C76 1U_0402_6.3V6K

T46 @
T47 @

C77 0.1U_0 402_16V7K

1 2

C78 1U_0402_6.3V6K

1 2

T48 @

+1.05VS

C81 1U_0402_6.3V6K

1 2

1 2

1 2

1 2
1 2
1 2

1 2
1 2

+RTCVCC

C63 0.1U_0 402_16V7K

1 2

@

+1.05VS

+3V_PCH

+1.5VS
+3VS

+3VS

U9M

w w w . c h i n a f i x . c o m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2014/03/03 2015/03/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

BDW ULT(9/11) Power

LA-B131P

1

1.0

of

12 52Tuesday, March 04, 2014

5

D D

4

3

2

1

HASWELL_MCP_E

U9N

A11

VSS

A14

VSS

A18

VSS

A24

VSS

A28

VSS

A32

VSS

A36

VSS

A40

VSS

A44

VSS

A48

VSS

A52

VSS

A56

VSS

AA1

VSS

AA58

VSS

AB10

VSS

AB20

VSS

AB22

VSS

AB7

C C

B B

AC61
AD21

AD3
AD63
AE10

AE5
AE58
AF11
AF12
AF14
AF15
AF17
AF18

AG1
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57

AJ13
AJ14
AJ23
AJ25
AJ27
AJ29

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

14 OF 19

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

Rev1p2

AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20

AP22
AP23
AP26
AP29

AP3
AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49

AR5
AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63

AU1
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U9O

HASWELL_MCP_E

15 OF 19

Rev1p2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AV59
AV8
AW16
AW24
AW33
AW35
AW37
AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31

U9P

D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49

D50
D51
D53
D54
D55
D57
D59
D62

E11
E17
F20
F26
F30
F34
F38
F42
F46
F50
F54
F58
F61
G18
G22

H13

HASWELL_MCP_E

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

D5

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

D8

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

G3

VSS

G5

VSS

G6

VSS

G8

VSS
VSS

16 OF 19

VSS_SENSE

Rev1p2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS

VSS

H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63

V58
AH46
V23
E62
AH16

VSSSENSE 11,46

A A

w w w . c h i n a f i x . c o m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2014/03/03 2015/03/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

BDW ULT(10/11) GND

LA-B131P

1

1.0

of

13 52Tuesday, March 04, 2014

1

12

12

HASWELL_MCP_E

18 OF 19

R82
1K_0402_1%

@

R83
1K_0402_1%

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

Rev1p2

N23
R23
T23
U10

AL1
AM11
AP7
AU10
AU15
AW14
AY14

U9Q

DC_TEST_AY2_AW2
DC_TEST_AY3_AW3

T49 @

DC_TEST_AY61_AW61
DC_TEST_AY62_AW62

T51 @

DC_TEST_A3_B3
DC_TEST_A61_B61
DC_TEST_B62_B63

DC_TEST_C1_C2

T55 @
T56 @
T57 @
T58 @
T59 @
T60 @
T61 @
T62 @
T63 @
T64 @

A A

T65 @
T66 @
T67 @
T68 @
T69 @
T70 @

T71 @
T72 @
T73 @
T74 @

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

CFG16
CFG18
CFG17
CFG19

CFG_RCOMP

TD_IREF

AY2

DAISY_CHAIN_NCTF_AY2

AY3

DAISY_CHAIN_NCTF_AY3

AY60

DAISY_CHAIN_NCTF_AY60

AY61

DAISY_CHAIN_NCTF_AY61

AY62

DAISY_CHAIN_NCTF_AY62

B2

DAISY_CHAIN_NCTF_B2

B3

DAISY_CHAIN_NCTF_B3

B61

DAISY_CHAIN_NCTF_B61

B62

DAISY_CHAIN_NCTF_B62

B63

DAISY_CHAIN_NCTF_B63

C1

DAISY_CHAIN_NCTF_C1

C2

DAISY_CHAIN_NCTF_C2

U9S

AC60

CFG0

AC62

CFG1

AC63

CFG2

AA63

CFG3

AA60

CFG4

Y62

CFG5

Y61

CFG6

Y60

CFG7

V62

CFG8

V61

CFG9

V60

CFG10

U60

CFG11

T63

CFG12

T62

CFG13

T61

CFG14

T60

CFG15

AA62

CFG16

U63

CFG18

AA61

CFG17

U62

CFG19

V63

CFG_RCOMP

A5

RSVD

E1

RSVD

D1

RSVD

J20

RSVD

H18

RSVD

B12

TD_IREF

HASWELL_MCP_E

17 OF 19

HASWELL_MCP_E

RESERVED

19 OF 19

DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4

DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_A62

DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
DAISY_CHAIN_NCTF_AW2
DAISY_CHAIN_NCTF_AW3

DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63

Rev1p2

PROC_OPI_RCOMP

RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP

RSVD

RSVD_TP
RSVD_TP

RSVD_TP

RSVD

RSVD
RSVD

RSVD
RSVD

VSS
VSS

RSVD
RSVD

Rev1p2

A3
A4

A60
A61
A62
AV1
AW1

DC_TEST_AY2_AW2

AW2

DC_TEST_AY3_AW3

AW3

DC_TEST_AY61_AW61

AW61

DC_TEST_AY62_AW62

AW62
AW63

AV63
AU63

C63
C62
B43

A51
B51

L60

N60

W23
Y22
AY15

AV62
D58

P22
N21

P20
R20

DC_TEST_A3_B3

DC_TEST_A61_B61

OPI_COMP

T50@

V1.0

T52@
T53@

T54@

U9R

AT2

RSVD

AU44

RSVD

AV44

RSVD

D15

RSVD

F22

RSVD

H22

RSVD

J21

RSVD

CFG Straps for Processor

CFG3

Physical Debug Enable (DFX Privacy)

1: DISABLED

CFG3

0: ENABLED; SET DFX ENABLED BIT
IN DEBUG INTERFACE MSR

CFG4

R84 49.9_0402_1%

R85 49.9_0402_1%

R86 8.2K_0402_5%

12

12

12

CFG_RCOMP

OPI_COMP

TD_IREF

Display Port Presence Strap

1 : Disabled; No Physical Display Port

CFG4

attached to Embedded Display Port

0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

w w w . c h i n a f i x . c o m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2014/03/03 2015/03/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

BDW ULT(11/11) RSVD

LA-B131P

of

14 52Tuesday, March 04, 2014

1.0

A

SA_DIMM_A_VREFDQ5

1 1

+1.35V

C93

1U_0402_6.3V6K

1

@

2

SIV

+1.35V

C98

1U_0402_6.3V6K

2 2

3 3

1

@

2

SIV

+1.35V

C102

10U_0603_6.3V6M

1

2

+1.35V

C109

10U_0603_6.3V6M

1

2

Layout Note:
Place near JDIMMA
Everage by each side

C89

0.022U_0402_16V7K

12

@

12

@

SIT

C94

1U_0402_6.3V6K

C96

1U_0402_6.3V6K

1

1

@

@

2

2

C100

1U_0402_6.3V6K

C99

1U_0402_6.3V6K

1

1

2

1

2

1

2

@

@

2

C104

10U_0603_6.3V6M

C103

10U_0603_6.3V6M

1

1

2

2

C110

10U_0603_6.3V6M

C111

10U_0603_6.3V6M

1

1

+

@

@

2

2

CRB1.0 10uF *8 /1uF *8

+0.675VS

C115

1U_0402_6.3V6K

C113

10U_0603_6.3V6M

1

1

@

2

2

4 4

SIV

Layout Note:
Place near JDIMM1.203,204

C116

1U_0402_6.3V6K

C114

1U_0402_6.3V6K

1

@

@

2

1

1

2

2

+1.35V

12

R88

1 2

0_0402_5%

R90

24.9_0402_1%

10U_0603_6.3V6M

C112

12

C95

1U_0402_6.3V6K

1

2

C101

1U_0402_6.3V6K

1

2

C105

100U_B2_6.3VM_R45M

+3VS

+0.675VS

C117

1U_0402_6.3V6K

CRB1.0 0.1uF *1 /2.2uF *1

R87

1.8K_0402_1%

C90

2.2U_0402_6.3V6M

@

R89

1.8K_0402_1%

CRB1.0 0.1uF *1 /2.2uF *1

2.2uF (reserved)

DDRA_CKE0_DIMM5

DDR_A_BS25

SA_CLK_DDR05
SA_CLK_DDR#05

DDR_A_BS05

DDR_A_WE#5
DDR_A_CAS#5

DDRA_CS1_DIMM#5

C118

0.1U_0402_16V7K

1

2

0.1U_0402_16V7K

1

1

2

2

C119

2.2U_0402_6.3V6M

1

@

2

SIV

C91

DDRA_CKE0_DIMM

DDR_A_BS2

DDRA_CS1_DIMM#

+V_DDR_REFA

DDR_A_D13
DDR_A_D8

DDR_A_D14
DDR_A_D10

DDR_A_D29
DDR_A_D28

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D31

DDR_A_D44
DDR_A_D41

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D43
DDR_A_D47

DDR_A_D51
DDR_A_D50

DDR_A_D49
DDR_A_D48

SA_CLK_DDR0
SA_CLK_DDR#0

DDR_A_D0
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D6

DDR_A_D21
DDR_A_D20

DDR_A_D17
DDR_A_D16

DDR_A_D36
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D38

DDR_A_D62
DDR_A_D58

DDR_A_D60
DDR_A_D61

CRB1.0 10uF *1 /1uF *4

A

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13

DDR_A_SA0

DDR_A_SA1

B

JDIMM1

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

LCN_DAN06-K4406-0103

VSS
DQ4
DQ5
VSS

DQS0#

DQS0

VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

RESET#

VSS
DQ14
DQ15

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

CKE1

VDD

VDD

VDD

VDD

VDD

CK1#

VDD

RAS#

VDD

ODT0

VDD
ODT1

VDD

VREF_CA

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

EVENT#

SDA

GND2

BOSS2

+1.35V+1.35V

2

DDR_A_D9

4

DDR_A_D12

6
8

DDR_A_DQS#1

10

DDR_A_DQS1

12
14

DDR_A_D15

16

DDR_A_D11

18
20

DDR_A_D25

22

DDR_A_D24

24
26
28

DIMM_DRAMRST#

30
32

DDR_A_D27

34

DDR_A_D26

36
38

DDR_A_D45

40

DDR_A_D40

42
44
46
48

DDR_A_D42

50

DDR_A_D46

52
54

DDR_A_D52

56

DDR_A_D53

58
60

DDR_A_DQS#6

62

DDR_A_DQS6

64
66

DDR_A_D54

68

DDR_A_D55

70
72

DDRA_CKE1_DIMM

74
76

DDR_A_MA15

78

A15
A14

A11

A7

A6
A4

A2
A0

CK1

BA1

S0#

NC

SCL
VTT

80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206
208

DDR_A_MA14

DDR_A_MA11
DDR_A_MA7

DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

SA_CLK_DDR1
SA_CLK_DDR#1

DDR_A_BS1
DDR_A_RAS#

DDRA_CS0_DIMM#
SA_ODT0

SA_ODT1

DDR_A_D5
DDR_A_D4

DDR_A_D3
DDR_A_D7

DDR_A_D18
DDR_A_D19

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D22
DDR_A_D23

DDR_A_D37
DDR_A_D32

DDR_A_D35
DDR_A_D39

DDR_A_D63
DDR_A_D59

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D56
DDR_A_D57

PCH_SMB_DATA

PCH_SMB_CLK

+0.675VS

C

All VREF traces should
have 10 mil trace width

DIMM_DRAMRST# 4,16

C92 0 .1U_0402_16V7K

1 2

@

DDRA_CKE1_DIMM 5

SA_CLK_DDR1 5
SA_CLK_DDR#1 5

DDR_A_BS1 5
DDR_A_RAS# 5

DDRA_CS0_DIMM# 5

+VREF_CA

2.2U_0402_6.3V6M

C108

0.1U_0402_16V7K

C106

1

1

@

2

2

CRB1.0 0.1uF *1 /2.2uF *1

2.2uF (reserved)

PCH_SMB_DATA 7,16,31
PCH_SMB_CLK 7,16 ,31

DDR_A_D[0..63] 5

DDR_A_MA[0..15] 5

DDR_A_DQS#[0..7] 5

DDR_A_DQS[0..7] 5

+1.35V

12

R97

1.8K_0402_1%

R98

1 2

0_0402_5%

12

R99

1.8K_0402_1%

DDR_PG_CTRL4

C107

0.022U_0402_16V7K

Address : 00

R101 0_0402_5%

R102 0_0402_5%

12

@

12

@

R100

24.9_0402_1%

1 2

1 2

D

SIV

U13

NC1VCC

2

A

3

GND

74AUP1G07GW_TSSOP5

SM_DIMM_VREFCA 5

SIT

SIV

0.1U_0402_16V7K

C97

DDR_A_SA0

DDR_A_SA1

E

+1.35V

+5VALW

1

@

2

5

4

Y

+5VS

R91220K_0402_5%

R92220K_0402_5%

12

12

V0.2

@

+1.35V

Q3

13

D

LBSS138LT1G_SOT-23-3

2

G

S

M_A_B_DIMM_ODT

DDR_VTT_PG_CTRL 40

SA_ODT216
SA_ODT316

1 2

R93 66.5_0402_1%

1 2

R94 66.5_0402_1%

1 2

R95 66.5_0402_1%

1 2

R96 66.5_0402_1%

SA_ODT2
SA_ODT3

SA_ODT0

SA_ODT1

SA_ODT2

SA_ODT3

CHANNEL A /TYPE :Reverse / H:4mm

w w w . c h i n a f i x . c o m

PN:SP07000LT00

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2014/03/03 2015/03/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

DDR3L_DIMMA

LA-B131P

E

1.0

of

15 52Tuesday, March 04, 2014

A

SA_DIMM_B_VREFDQ5

1 1

+1.35V

C124

1U_0402_6.3V6K

1

@

2

SIV

+1.35V

C128

1U_0402_6.3V6K

2 2

3 3

1

@

2

SIV

+1.35V

C132

10U_0603_6.3V6M

1

2

+1.35V

C139

10U_0603_6.3V6M

1

2

Layout Note:
Place near JDIMMB
Everage by each side

C120

0.022U_0402_16V7K

12

@

12

@

SIT

C127

1U_0402_6.3V6K

C126

1U_0402_6.3V6K

1

1

@

2

1

2

1

2

1

2

@

2

C131

1U_0402_6.3V6K

C129

1U_0402_6.3V6K

1

@

@

2

C133

10U_0603_6.3V6M

C134

10U_0603_6.3V6M

1

1

2

2

C140

10U_0603_6.3V6M

C141

10U_0603_6.3V6M

1

1

+

@

@

2

2

CRB1.0 10uF *8 /1uF *8

+0.675VS

C146

C143

10U_0603_6.3V6M

C144

1U_0402_6.3V6K

1

1

@

@

2

4 4

2

SIV

Layout Note:
Place near JDIMMB.203,204

1U_0402_6.3V6K

C147

1U_0402_6.3V6K

1

1

@

2

1

2

2

+1.35V

12

R104

1 2

0_0402_5%

R106

24.9_0402_1%

10U_0603_6.3V6M

C142

12

C125

1U_0402_6.3V6K

1

2

C130

1U_0402_6.3V6K

1

2

C135

100U_B2_6.3VM_R45M

+0.675VS

C145

1U_0402_6.3V6K

CRB1.0 0.1uF *1 /2.2uF *1

R103

1.8K_0402_1%

C121

2.2U_0402_6.3V6M

@

R105

1.8K_0402_1%

CRB1.0 0.1uF *1 /2.2uF *1

2.2uF (reserved)

DDRB_CKE2_DIMM5

DDR_B_BS25

SA_CLK_DDR25
SA_CLK_DDR#25

DDR_B_BS05

DDR_B_WE#5
DDR_B_CAS#5

DDRB_CS3_DIMM#5

C148

0.1U_0402_16V7K

1

2

0.1U_0402_16V7K

1

1

2

2

C149

2.2U_0402_6.3V6M

1

@

2

C122

DDRB_CKE2_DIMM

DDR_B_BS2

DDRB_CS3_DIMM#

+V_DDR_REFB

DDR_B_D8
DDR_B_D14

DDR_B_D10
DDR_B_D11

DDR_B_D28
DDR_B_D29

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D26
DDR_B_D27

DDR_B_D40
DDR_B_D41

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D46
DDR_B_D42

DDR_B_D56
DDR_B_D57

DDR_B_D59
DDR_B_D58

DDR_B_D4
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D3
DDR_B_D7

DDR_B_D21
DDR_B_D20

DDR_B_D22
DDR_B_D23

DDR_B_D36
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D35
DDR_B_D39

DDR_B_D52
DDR_B_D49

DDR_B_D48
DDR_B_D53

CRB1.0 10uF *1 /1uF *4

A

B

JDIMM2

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

SA_CLK_DDR2
SA_CLK_DDR#2

DDR_B_MA10
DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

DDR_B_MA13

DDR_B_SA0

DDR_B_SA1 PCH_SMB_CLK

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

LCN_DAN06-K4406-0103

DQS0#

RESET#

DQS3#

VREF_CA

DQS5#

DQS7#

EVENT#

BOSS2

VSS

DQ4

DQ5

VSS

DQS0

VSS

DQ6

DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS
DQ14
DQ15

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3

VSS
DQ30
DQ31

VSS

CKE1

VDD

VDD

VDD

VDD

VDD

CK1#

VDD

RAS#

VDD

ODT0

VDD
ODT1

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7

VSS
DQ62
DQ63

VSS

SDA

GND2

+1.35V+1.35V

2

DDR_B_D12

4

DDR_B_D9

6
8

DDR_B_DQS#1

10

DDR_B_DQS1

12
14

DDR_B_D13

16

DDR_B_D15

18
20

DDR_B_D25

22

DDR_B_D24

24
26
28

DIMM_DRAMRST#

30
32

DDR_B_D30

34

DDR_B_D31

36
38

DDR_B_D45

40

DDR_B_D44

42
44
46
48

DDR_B_D47

50

DDR_B_D43

52
54

DDR_B_D61

56

DDR_B_D60

58
60

DDR_B_DQS#7

62

DDR_B_DQS7

64
66

DDR_B_D63

68

DDR_B_D62

70
72

DDRB_CKE3_DIMM

74
76

DDR_B_MA15

78

A15
A14

A11

A7

A6
A4

A2
A0

CK1

BA1

S0#

NC

SCL
VTT

80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206
208

DDR_B_MA14

DDR_B_MA11
DDR_B_MA7

DDR_B_MA6
DDR_B_MA4

DDR_B_MA2
DDR_B_MA0

SA_CLK_DDR3
SA_CLK_DDR#3

DDR_B_BS1
DDR_B_RAS#

DDRB_CS2_DIMM#
SA_ODT2

SA_ODT3

DDR_B_D5
DDR_B_D0

DDR_B_D2
DDR_B_D6

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D19
DDR_B_D18

DDR_B_D37
DDR_B_D32

DDR_B_D34
DDR_B_D38

DDR_B_D51
DDR_B_D55

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D54
DDR_B_D50

PCH_SMB_DATA

+0.675VS

C

All VREF traces should
have 10 mil trace width

DIMM_DRAMRST# 4,15

C123 0.1U_ 0402_16V7K

1 2

@

DDRB_CKE3_DIMM 5

SA_CLK_DDR3 5
SA_CLK_DDR#3 5

DDR_B_BS1 5
DDR_B_RAS# 5

DDRB_CS2_DIMM# 5
SA_ODT2 15

SA_ODT3 15

+VREF_CA

2.2U_0402_6.3V6M
C136

1

@

2

CRB1.0 0.1uF *1 /2.2uF *1

2.2uF (reserved)

+3VS

PCH_SMB_DATA 7,15,31+3VS
PCH_SMB_CLK 7,15 ,31

DDR_B_D[0..63] 5

DDR_B_MA[0..15] 5

DDR_B_DQS#[0..7] 5

DDR_B_DQS[0..7] 5

C137

0.1U_0402_16V7K

1

2

Address : 01

R111 0_0402_5%

1 2

R112 0_0402_5%

1 2

D

DDR_B_SA0

SIV

DDR_B_SA1

E

CHANNEL B /TYPE :Reverse / H:4mm

w w w . c h i n a f i x . c o m

PN:SP07000LT00

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2014/03/03 2015/03/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

DDR3L_DIMMB

LA-B131P

E

of

16 52Tuesday, March 04, 2014

1.0

5

4

3

2

1

GFX PCIE LANE REVERSAL

D D

PCIE_CTX_GRX_P010
PCIE_CTX_GRX_N010

PCIE_CTX_GRX_P110
PCIE_CTX_GRX_N110

PCIE_CTX_GRX_P210
PCIE_CTX_GRX_N210

PCIE_CTX_GRX_P310
PCIE_CTX_GRX_N310

C C

B B

CLK_PCIE_VGA7
CLK_PCIE_VGA#7

PCIE_CTX_GRX_P0
PCIE_CTX_GRX_N0

PCIE_CTX_GRX_P1
PCIE_CTX_GRX_N1

PCIE_CTX_GRX_P2
PCIE_CTX_GRX_N2

PCIE_CTX_GRX_P3
PCIE_CTX_GRX_N3

CLK_PCIE_VGA
CLK_PCIE_VGA#

DIS@

1 2

RV2 1K_0402_5%

GPU_RST#

12

DIS@

RV4
100K_0402_5%

UV1A

AA38

PCIE_RX0P

Y37

PCIE_RX0N

Y35

PCIE_RX1P

W36

PCIE_RX1N

W38

PCIE_RX2P

V37

PCIE_RX2N

V35

PCIE_RX3P

U36

PCIE_RX3N

U38

PCIE_RX4P

T37

PCIE_RX4N

T35

PCIE_RX5P

R36

PCIE_RX5N

R38

PCIE_RX6P

P37

PCIE_RX6N

P35

PCIE_RX7P

N36

PCIE_RX7N

N38

PCIE_RX8P

M37

PCIE_RX8N

M35

PCIE_RX9P

L36

PCIE_RX9N

L38

PCIE_RX10P

K37

PCIE_RX10N

K35

PCIE_RX11P

J36

PCIE_RX11N

J38

PCIE_RX12P

H37

PCIE_RX12N

H35

PCIE_RX13P

G36

PCIE_RX13N

G38

PCIE_RX14P

F37

PCIE_RX14N

F35

PCIE_RX15P

E37

PCIE_RX15N

CLOCK

AB35

PCIE_REFCLKP

AA36

PCIE_REFCLKN

AH16

PWRGOOD

AA30

PERSTB

216-0833000-A11-THAME S-XT-M2_FCBGA962~D

THAMES XT M2

DIS@

PCIE_TX0P

PCIE_TX0N

PCIE_TX1P

PCIE_TX1N

PCIE_TX2P

PCIE_TX2N

PCIE_TX3P

PCIE_TX3N

PCIE_TX4P

PCI EXPRESS INTERFACE

PCIE_TX4N

PCIE_TX5P

PCIE_TX5N

PCIE_TX6P

PCIE_TX6N

PCIE_TX7P

PCIE_TX7N

PCIE_TX8P

PCIE_TX8N

PCIE_TX9P

PCIE_TX9N

PCIE_TX10P

PCIE_TX10N

PCIE_TX11P

PCIE_TX11N

PCIE_TX12P

PCIE_TX12N

PCIE_TX13P

PCIE_TX13N

PCIE_TX14P

PCIE_TX14N

PCIE_TX15P

PCIE_TX15N

CALIBRATION

PCIE_CALRP

PCIE_CALRN

PCIE_CRX_C_GTX_N0

Y32

PCIE_CRX_C_GTX_P1

W33

PCIE_CRX_C_GTX_N1 PCIE_CRX_GTX_N1

W32

PCIE_CRX_C_GTX_P2

U33

PCIE_CRX_C_GTX_N2

U32

PCIE_CRX_C_GTX_P3

U30

PCIE_CRX_C_GTX_N3 PCIE_CRX_GTX_N3

U29

T33
T32

T30
T29

P33
P32

P30
P29

N33
N32

N30
N29

L33
L32

L30
L29

K33
K32

J33
J32

K30
K29

H33
H32

DIS@

RV1

1.69K_0402_1%

Y30

Y29

1 2

1 2

DIS@

RV3
1K_0402_1%

Thames
RV198, 1.27K_0402_1% pull-down
RV203, 2K_0402_1% pull-up
PWR need to Modify +VGA_PCIE

+VGA_PCIE

+VGA_PCIE

PCIE_CRX_C_GTX_P0

Y33

CV10.22U_0402_10V6K DIS@

12

CV20.22U_0402_10V6K DIS@

12

CV30.22U_0402_10V6K DIS@

12

CV40.22U_0402_10V6K DIS@

12

CV80.22U_0402_10V6K DIS@

12

CV50.22U_0402_10V6K DIS@

12

CV60.22U_0402_10V6K DIS@

12

CV70.22U_0402_10V6K DIS@

12

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0

PCIE_CRX_GTX_P1

PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P3

PCIE_CRX_GTX_P0 10
PCIE_CRX_GTX_N0 10

PCIE_CRX_GTX_P1 10
PCIE_CRX_GTX_N1 10

PCIE_CRX_GTX_P2 10
PCIE_CRX_GTX_N2 10

PCIE_CRX_GTX_P3 10
PCIE_CRX_GTX_N3 10

DGPU_HOLD_RST#8

PLT_RST#8,26,29,30,33

LVDS Interface

UV1G

LVDS CONTROL

LVTMDP

216-0833000-A11-THAME S-XT-M2_FCBGA962~D

DIS@

+3VGS

5

1

IN1

2

IN2

3

VARY_BL

DIGON

TXCLK_UP_DPF3P
TXCLK_UN_DPF3N

TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N

TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N

TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N

TXOUT_U3P
TXOUT_U3N

TXCLK_LP_DPE3P
TXCLK_LN_DPE3N

TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N

TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N

TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N

TXOUT_L3P

TXOUT_L3N

Place CV326 Close to UV13

@DIS@

2

CV9

0.1U_0402_25V6K

1

VCC

OUT

GND

GPU_RST#

4

UV2
MC74VHC1G08DFT2G_S C70-5

DIS@

AK27
AJ27

AK35
AL36

AJ38
AK37

AH35
AJ36

AG38
AH37

AF35
AG36

AP34
AR34

AW37
AU35

AR37
AU39

AP35
AR35

AN36
AP37

SIV

A A

w w w . c h i n a f i x . c o m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

2014/03/03 2015/03/03

3

Compal Secret Data

Deciphered Date

Title

Size D ocument Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Venus XTX(1/8) PCIE/PWRseq

LA-B131P

1

of

17 52Tuesday, March 04, 2014

1.0

5

4

3

2

1

CONFIGURATION STRAPS

+1.8VGS

RV5 10K_0402_5%@

1 2

RV6 10K_0402_5%@

1 2

RV7 10K_0402_5%@

1 2

RV8 10K_0402_5%@

1 2

RV9 10K_0402_5%@

1 2

RV10 10 K_040 2_5%@

1 2

D D

C C

B B

Vendor VRAM_ID0 VRAM_ID1 VRAM_ID2

H5TC2G63FFR-11C

128MX16bits
DDR3

128MX16bits
DDR3

128MX16bits
DDR3

256MX16bits
DDR3

256MX16bits
DDR3

256MX16bits
DDR3

Hynix 2Gb
SA00006H410

MT41J128M16JT-093G:K

Micron 2Gb
SA000067510

K4W2G1646Q-BC1A

Samsung 2Gb
SA000068U50

H5TC4G63AFR-11C

Hynix 4Gb
SA00006E830

MT41J256M16HA-093G

Micron 4Gb
SA000077K10

K4W4G1646D-BC1A

Samsung 4Gb
SA000076P10

+3VGS

+1.8VGS

BLM15BD 121SN1D _0402

+VGA_PC IE

BLM15BD 121SN1D _0402

STRAPS

LV3

DIS@

12

(125mA)

LV4

DIS@

12

RV6 RV10

RV6 RV8

RV6 RV7

RV5

RV5 RV8

1 2

1 2

@DIS@
1 8
2 7
3 6
4 5

RP19

10K_8P 4R_5%

1 2
1 2
1 2
1 2

@DIS@
1 8
2 7
3 6
4 5

RP20

10K_8P 4R_5%

(75mA)

1

CV20

2

DIS@

10U_0603_6.3V6M

0.95V@Venus

1

CV23

2

DIS@

10U_0603_6.3V6M

0 0

0 1

0 1

1 0

RV134.7K_0402_5% DIS@

RV1610K_0402 _5% @DIS@

RV1910K_0402 _5% @DI S@
RV2210K_0402 _5% @DIS@
RV2410K_0402 _5% @DIS@
RV251K_0402_5% @ DIS@

GPIO24 _TRSTB
GPIO25 _TDI
GPIO27 _TMS
GPIO26 _TCK

1

CV21

2

1U_0402_6.3V6K

DIS@

1

CV24

2

1U_0402_6.3V6K

DIS@

GCLK (RV187 close to YV1.1)

GPU_XTA LIN_GCL K34

A A

5

GPU_XTA LIN_GCL K

RESERVE FOR GREEN CLOCK

SUN internal VGA Thermal Sensor
Address 0x714

CV30

10P_04 02_50V 8J

NOGCLK@

1 2

RV187 0_0402 _5%

3

12

RV8

00

RV7RV6

RV8

01

THM_ALER T#

SIV

GPU_GPI O0

GPU_GPI O2

SIV

GPU_GPI O1
GPU_GPI O8
GPU_GPI O9

GPU_GPI O11
GPU_GPI O14
GPU_GPI O13
AC_BAT T

SVT

+DPLL_P VDD

1

CV22

2

DIS@

0.1U_0402_16V7K

+DPLL_V DDC

1

CV25

2

DIS@

0.1U_0402_16V7K

XTALIN

SVT

RV37

NOGCLK@

1M_0402 _5%

YV1

NOGCLK@

27MHZ_10 PF_7V2 70000 50

3

GND

GND

2

4

GPUCLK_ REQ#7

VRAM_ID 0

VRAM_ID 1

VRAM_ID 2

0

RV9

1

RV10

0

RV9

1

RV10

0

RV9

1

+3VGS

12

RV35
10K_04 02_5%

@DIS@

TS_FDO

12

RV36
10K_04 02_5%

DIS@

Add 12/6 for MLPS

(5mA)

+1.8VGS

BLM15BD 121SN1D _0402

XTALINXTAL OUT

1

1

12

CV31

10P_04 02_50V 8J

NOGCLK@

+3VGS

2

G

1 3

D

S

QV2

@DIS@

2N7002K _SOT23 -3

4

THM_ALER T#31

RV18 10K_0402_5 %@DIS@

connect to PWR

+1.8VGS

DIS@

RV31 499_04 02_1%

DIS@

RV33 249_04 02_1%

DIS@

CV19 0.1U_0402_16 V7K

XTALIN
Voltage Swing: 1.8 V

DIS@

LV5

1 2

+3VGS

AC_BAT T30,37

GPU_VID 545

GPU_VID 445

GPU_VID 345
GPU_VID 245

1 2

GPU_VID 145

0.60 V level, Please
VREFG Divider ans
cap close to ASIC

12

12

12

1 2

RV44

SIT

REMOTE2 +31
REMOTE2 -3 1

(1.8V@20mA TSVDD)

12

@DIS@

RV40

2.2K_04 02_5%

GPUCLK_ REQ#_R

T96
T97

T95
T94

T80
T98

T81

0_0402 _5%

1

CV26

2

DIS@

10U_0603_6.3V6M

GPUCLK_ REQ#_R

VRAM_ID 0
VRAM_ID 1
VRAM_ID 2

GPU_GPI O0
GPU_GPI O1
GPU_GPI O2

AC_BAT T

GPU_GPI O8
GPU_GPI O9
GPU_VID 5
GPU_GPI O11
GPU_VID 4
GPU_GPI O13
GPU_GPI O14
GPU_VID 3
GPU_VID2
THM_ALER T#

GPU_VID 1

GPIO24 _TRSTB
GPIO25 _TDI
GPIO26 _TCK
GPIO27 _TMS

+VREFG_ GPU

+DPLL_P VDD

DPLL_P VSS

+DPLL_V DDC

TS_FDO

+TSVDD

1

CV28

2
DIS@

1U_0402_6.3V6K

20mil

20mil

20mil

XTALIN
XTALOUT

1

CV29

2

DIS@

10mil

0.1U_0402_16V7K

UV1B

MUTI GFX

AR8

DVPCNTL_MVP_0

AU8

DVPCNTL_MVP_1

AP8

DVPCNTL_0

AW8

DVPCNTL_1

AR3

DVPCNTL_2

AR1

DVPCLK

AU1

DVPDATA_0

AU3

DVPDATA_1

AW3

DVPDATA_2

AP6

DVPDATA_3

AW5

DVPDATA_4

AU5

DVPDATA_5

AR6

DVPDATA_6

AW6

DVPDATA_7

AU6

DVPDATA_8

AT7

DVPDATA_9

AV7

DVPDATA_10

AN7

DVPDATA_11

AV9

DVPDATA_12

AT9

DVPDATA_13

AR10

DVPDATA_14

AW10

DVPDATA_15

AU10

DVPDATA_16

AP10

DVPDATA_17

AV11

DVPDATA_18

AT11

DVPDATA_19

AR12

DVPDATA_20

AW12

DVPDATA_21

AU12

DVPDATA_22

AP12

DVPDATA_23

AJ21

SWAPLOCKA

AK21

SWAPLOCKB

I2C

AK26

SCL

AJ26

SDA

GENERAL PURPOSE I/O

AH20

GPIO_0

AH18

GPIO_1

AN16

GPIO_2

AH23

GPIO_3_SMBDATA

AJ23

GPIO_4_SMBCLK

AH17

GPIO_5_AC_BATT

AJ17

GPIO_6

AK17

GPIO_7_BLON

AJ13

GPIO_8_ROMSO

AH15

GPIO_9_ROMSI

AJ16

GPIO_10_ROMSCK

AK16

GPIO_11

AL16

GPIO_12

AM16

GPIO_13

AM14

GPIO_14_HPD2

AM13

GPIO_15_PWRCNTL_0

AK14

GPIO_16

AG30

GPIO_17_THERMAL_INT

AN14

GPIO_18_HPD3

AM17

GPIO_19_CTF

AL13

GPIO_20_PWRCNTL_1

AJ14

GPIO_21_BB_EN

AK13

GPIO_22_ROMCSB

AN13

GPIO_23_CLKREQB

AM23

JTAG_TRSTB

AN23

JTAG_TDI

AK23

JTAG_TCK

AL24

JTAG_TMS

AM24

JTAG_TDO

AJ19

GENERICA

AK19

GENERICB

AJ20

GENERICC

AK20

GENERICD

AJ24

GENERICE_HPD4

AH26

GENERICF_HPD5

AH24

GENERICG_HPD6

AK24

AH13

AM32
AN32

AN31

AV33
AU34

AW34

AW35

AF29
AG29

AK32

AL31

AJ32
AJ33

V2SYNC/GENLK_VSYNC

HPD1

VREFG

DPLL_PVDD
DPLL_PVSS

PLL/CLOCK

DPLL_VDDC

XTALIN
XTALOUT

XO_IN

XO_IN2

DPLUS

THERMAL

DMINUS

TS_FDO

TS_A/NC

TSVDD
TSVSS

216-083 3000-A1 1-THAMES-X T-M2_FC BGA962 ~D

DIS@

TXCAP_DPA3P
TXCAM_DPA3N

TX0P_DPA2P
TX0M_DPA2N

DPA

TX1P_DPA1P
TX1M_DPA1N

TX2P_DPA0P
TX2M_DPA0N

TXCBP_DPB3P
TXCBM_DPB3N

TX3P_DPB2P
TX3M_DPB2N

DPB

TX4P_DPB1P
TX4M_DPB1N

TX5P_DPB0P
TX5M_DPB0N

TXCCP_DPC3P
TXCCM_DPC3N

TX0P_DPC2P
TX0M_DPC2N

DPC

TX1P_DPC1P
TX1M_DPC1N

TX2P_DPC0P
TX2M_DPC0N

TXCDP_DPD3P
TXCDM_DPD3N

TX3P_DPD2P
TX3M_DPD2N

DPD

TX4P_DPD1P
TX4M_DPD1N

TX5P_DPD0P
TX5M_DPD0N

DAC1

COMP/NC

DAC2

H2SYNC/GENLK_CLK

VDD2DI/NC

VSS2DI/NC

A2VDD/NC

A2VDDQ/NC

A2VSSQ/TSVSSQ

R2SET/NC

DDC/AUX

DDC1CLK

DDC1DATA

DDC2CLK

DDC2DATA

DDCCLK_AUX3P

DDCDATA_AUX3N

DDCCLK_AUX4P

DDCDATA_AUX4N

DDCCLK_AUX5P

DDCDATA_AUX5N

DDC6CLK

DDC6DATA

DDCCLK_AUX7P

DDCDATA_AUX7N

AU24
AV23

AT25
AR24

AU26
AV25

AT27
AR26

AR30
AT29

AV31
AU30

AR32
AT31

AT33
AU32

AU14
AV13

AT15
AR14

AU16
AV15

AT17
AR16

AU20
AT19

AT21
AR20

AU22
AV21

AT23
AR22

For DGPU output display Debug
(For Venus ASIC)

AD39

R

AD37

RB

AE36

G

AD35

GB

AF37

B

AE38

BB

AC36

HSYNC

AC38

VSYNC

DIS@

RV15 499_0402_1 %

AB34

RSET

10mil

+AVDD

AD34

AVDD

AE34

AVSSQ

10mil

+VDD1DI

(1.8V@100mA VDD1DI)

AC33

VDD1DI

AC34

VSS1DI

AC30

R2/NC

AC31

R2B/NC

AD30

G2/NC

PS_1

AD31

G2B/NC

AF30

B2/NC

AF31

B2B/NC

AC32

C/NC

AD32

Y/NC

AF32

AD29
AC29

PS_2

AG31
AG32

AG33

PS_3

AD33

AF33

AA29

AM26
AN26

AM27

AUX1P

AL27

AUX1N

AM19
AL19

AN20

AUX2P

AM20

AUX2N

AL30
AM30

AL29
AM29

AN21
AM21

For DGPU output display Debug

AJ30

(For Venus ASIC)

AJ31

AK30
AK29

4.7K_04 02_5%

QV1B

DMN66D0L DW-7_S OT363 -6

T75

T76

T77

T78
T79

1

CV15

2

DIS@

10U_0603_6.3V6M

+DPLL_P VDD

DPLL_P VSS

T82
T83

0_0402 _5%

T84
T85

100mA

1 2

DIS@

LV2
BLM15BD 121SN1D _0402

1 2

RV12

0_0402 _5%

@DIS@

+1.8VGS

VCIN1_A C_IN30,38

1 2

(1.8V@65mA AVDD)

1

1

CV14

CV13

2

2

DIS@

DIS@

1U_0402_6.3V6K

0.1U_0402_16V7K

RV26

1 2

0_0402 _5%@D IS@

RV27

1 2

0_0402 _5%@D IS@

SIT

1 2

RV32

NC_TSVSSQ should be tied to GND

3

RV34

@DIS@

2

+3VGS

12

@DIS@

DMN66D0L DW-7_S OT363 -6

PACIN#

61

D

G

S

1

CV11

2

DIS@

1U_0402_6.3V6K

0.1U_0402_16V7K

1

CV12

2
DIS@

10K_04 02_5%

QV1A

@DIS@

1

CV10

2
DIS@

10U_0603_6.3V6M

RV11

65mA

+3VGS

RV85 PU

12

chg to @

@DIS@

AC_BAT T

34

D

G

5

S

+1.8VGS

1 2

DIS@

LV1
BLM15BD 121SN1D _0402

PS0_[1] = 1
PS0_[2] = 0 For a 256-MB aperture size, PS_0[3:1] is set to 001
PS0_[3] = 0
PS0_[4] = 1 Must be 1 at reset.
PS0_[5] = 1 Audio-capable display outputs. 111 = No usable endpoints.

PS1_[1] = 1 PCIe GEN3 is supported = 1
PS1_[2] = 0 Must be 0 at reset.
PS1_[3] = 0 Must be 0 at reset.
PS1_[4] = 1 Full Tx output swing = 1
PS1_[5] = 1 Tx deemphasis enabled = 1

PS2_[1] = 0 Reserved
PS2_[2] = 0 Reserved
PS2_[3] = 0 Disable the external BIOS ROM device = 1
PS2_[4] = 1 The device will not be recognized as the system’s VGA controller = 1
PS2_[5] = 1 Reserved

PS3_[1] = 0 Reserved
PS3_[2] = 0 Reserved
PS3_[3] = 0 Reserved
PS3_[4] = 1 Audio-capable display outputs. 111 = No usable endpoints.
PS3_[5] = 1 Audio-capable display outputs. 111 = No usable endpoints.

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE
GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

STRAPS

RSVD

RSVD

RSVD

BIOS_R OM_EN

ROMIDCF G(2:0)

VIP_DE VICE_S TRAP_ ENA V2SYNC IGNORE V IP DEVI CE STR APS

RSVD

RSVD

AMD RESERVED CONFIGURAT ION STRAPS

ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL
RESISTOR. IF THESE GPIOS ARE USED, THEY MUST KEEP "LOW" AND
NOT CONFLICT DURING RESET

GPIO21

H2SYNC GENERIC C

TX_PWRS_ENB GPIO0

+1.8VGS

PS_1

1

CV16

2

@DIS@

0.68U_0402_10V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2014/03/03 2015/03/03

DESCRI PTION OF DEFAUL T SETTI NGSPIN

GPIO0 PCIE FULL TX O UTPUT SW INGTX_PWRS_ENB

GPIO1TX_DEEMPH_ EN PCIE TR ANSMITTE R DE-EMPHA SIS

Advertises PCIE speed

GPIO2

when compliance test

RESERVED

GPIO8

GPIO9 VGA E NABLEDBIF_VG A DIS

RESERVED

GPIO21

GPIO_2 2_ROMCS B

ENABLE EXTERNAL BIOS ROM

GPIO[13 :11]

SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT

H2SYNC

GENERIC C

AUD[1] AUD[0]

HSYNCAUD[1]

0 0 No audio function
0 1 Audio for DisplayPort and HDMI if dongle is detected

VSYNCAUD[0]

1 0 Audio for DisplayPort only
1 1 Audio for both DisplayPort and HDMI

GPIO2

GPIO8

Transmitter Power Saving Enable
0: 50% Tx output swing for mobile mode
1: full Tx output swin g (Default setting for Desktop)

PCI Express Transmitter De-emphasis Enable

GPIO1TX_DEEMPH_EN

0: Tx de-emphasis diabled for mobile mode
1: Tx de-emphasis enabled (Defailt setti ng for desktop)

12

RV23

8.45K_0 402_1%

DIS@

12

RV28
2K_040 2_1%

DIS@

+1.8VGS +1.8VGS

PS_2

1

CV17

2

@DIS@

0.68U_0402_10V

VENUS MLPs
PS_3 used default

Compal Secret Dat a

Deciphered Date

12

RV20
10K_04 02_1%

@DIS@

12

RV29

4.75K_0 402_1%

DIS@

RECOMMENDE D SETT INGS
0= DO NOT I NSTALL R ESIST OR
1 = INSTAL L 10K RE SISTO R
X = DESIG N DEPENDA NT
NA = NOT APPL ICABL E

0: 50% swing
1: Full swing

0: disable
1: enable

0: 2.5GT/s
1: 5GT/s

0: disable
1: enable

12

PS_3

12

1

CV18

2

@DIS@

0.68U_0402_10V

RECOMMENDED
SETTINGS

X

X

0

0

0

0

X

XXX

0

0

0

11

RV21

8.45K_0 402_1%

@DIS@

RV30

4.75K_0 402_1%

DIS@

Compal Electronics, Inc.

Title

Venus XTX(2/8) Main Gen

Size Docume nt Number Rev

D

Date: Sheet of

LA-B131P

1

18 52Tuesday, March 04 , 2014

w w w . c h i n a f i x . c o m

1.0

5

4

3

2

1

PX_MODE=1 for Normal Operation
PX_MODE=0 for BACO mode to shut down power rails expcept VDDR3,PCIE_VDDC and 1.8V rail

Note:

PX4.0 +VGA_CORE,VDDCI,+1.5VGS ON
PX4.0 +3VGS, +1.0VGS,+1.8VGS OFF
PX5.0 +3VGS,+VGA_CORE,VDDCI,+1.5VGV,+1.0VGS,+1.8VGS OFF

D D

Switch circuits in BACO desingns for Thames/Seymour only
55mA@1.0V, in BACO mode

+3VS TO +3VGS

+3VS +3VGS

JP2

@DIS@

2 1

2MM

D

S

C C

+5VALW

DIS@

RV47

20K_0402_5%

DGPU_PW R_EN8,9,30,41,42

SVT

2

ME2N7002D1KW -G 2N SOT363-6

61

1 2

DIS@

Q17A

DIS@

RV48

1K_0402_5%

13

QV5

DIS@

G

ME2301DC-G_SOT23- 3

2

SIV

1

DIS@

CV36

0.1U_0603_25V7K

2

DIS@

1

CV34
10U_0603_6.3V6M

2

DIS@

1

CV35
1U_0603_10V6K

2

2

G

12

R829
10_0805_1%

@DIS@

13

D

Q7
2N7002K_SOT23-3

@DIS@

S

SVT

SIT

+VGA_PCIE +BIF_VDDC

60mil

RV45
0_0805_5%

1 2

SIT

1

CV33

22U_0805_6.3V6MDIS@

2

+1.5VS to +MEM_GFX

+1.5VS

B B

Power seguence of Venus XTX

+3VGS

+VGA_PCIE (0.95V)

+1.8VGS

+MEM_GFX (1.5V)

+VGA_CORE

<20ms

>100ms

R830

33_0603_5%

DIS@

SIT

SVT

8
7
6
5

AO4354_SO8

12

GPU_RST#

A A

Q139

+MEM_GFX

DIS@

1

S

D

2

S

D

3

S

D

4

G

D

DIS@

C900

GPU_PW R_EN30,45

VRAM_1.5VS_GATE

1

2

0.01U_0402_25V7K

12

R827
820K_0402_5%@DIS@

ME2N7002D1KW -G 2N SOT363-6

R826
200K_0402_5%

1 2

61

Q15A

2

DIS@

ME2N7002D1KW -G 2N SOT363-6

SVT

DIS@

1.5V_PW R_EN#

3

DIS@

Q17B

5

4

B+

R825
470_0805_5%

DIS@

1 2

3

Q15B
ME2N7002D1KW -G 2N SOT363-6

5

DIS@

4

1 2

R828100K_0402_5%

DIS@

SVT

+5VALW

+MEM_GFX

DIS@

1

+

C342
150U_B2_6.3VM_R35M

2

w w w . c h i n a f i x . c o m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

2014/03/03 2015/03/03

3

Compal Secret Data

Deciphered Date

Title

Size D ocument Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Venus XTX(3/8) DC/DC POWER

LA-B131P

1

of

19 52Tuesday, March 04, 2014

1.0

5

D D

+1.8VGS

RV46

SIT

1 2

RV50

SIT

1 2

RV55

SIT

0_0402_5%

(220mA)

0_0402_5%

+1.8VGS

(220mA)

1.0V@220mA DPCD_VDD10)

0.95V@Venus

1

CV46

2

@DIS@

10U_0603_6.3V6M

+1.8VGS

1.0V@240mA DPEF_VDD10)

0.95V@Venus

CV52

@DIS@

12

DIS@

RV58

8.45K_0402_1%

12

DIS@

RV60
2K_0402_1%

+VGA_PCIE

C C

+VGA_PCIE

B B

A A

(30mA)

1 2

CV47

@DIS@

(330mA)

SIT

10U_0603_6.3V6M

1.8V@300mA DPCD_VDD18)

0_0402_5%

+DPCD_VDD10

1

CV48

2

@DIS@

1U_0402_6.3V6K

1 2

RV52

+DPEF_VDD10

1

CV53

2

@DIS@

1U_0402_6.3V6K

0_0402_5%

1

CV41

CV40

@DIS@

@DIS@

2

10U_0603_6.3V6M

+DPCD_VDD10

1

2

0.1U_0402_16V7K

1.8V@300mA DPEF_VDD18)

1

CV49

DIS@

2

10U_0603_6.3V6M

+DPEF_VDD10

1

1

CV54

2

2

@DIS@

0.1U_0402_16V7K

PS_0

1

@DIS@

CV55

0.68U_0402_10V

2

Thames/Seymour Only

Do not install for Heathrow/Mars Pro

PS_0 Should be tied to GND on Thames/Seymour

+DPCD_VDD18

1

1

CV42

@DIS@

2

2

1U_0402_6.3V6K

0.1U_0402_16V7K

+DPCD_VDD18

+DPCD_VDD10

+DPEF_VDD18

1

1

CV50

CV51

DIS@

DIS@

2

2

1U_0402_6.3V6K

0.1U_0402_16V7K

+DPEF_VDD18

+DPEF_VDD10

PS_0

DIS@

RV59
150_0402_1%

20mil

+DPCD_VDD18

+DPCD_VDD10

20mil

20mil

20mil

RV53150_0402_1% DIS@

12

+DPEF_VDD18

20mil

+DPEF_VDD10

20mil

20mil

20mil

4

UV1H

DP C/D POWER

AP20

DPCD/DPC_VDD 18#1

AP21

DPCD/DPC_VDD 18#2

AP13

DPCD/DPC_VDD 10#1

AT13

DPCD/DPC_VDD 10#2

AN17

DP/DPC_VSSR#1

AP16

DP/DPC_VSSR#2

AP17

DP/DPC_VSSR#3

AW14

DP/DPC_VSSR#4

AW16

DP/DPC_VSSR#5

AP22

DPCD/DPD_VDD 18#1

AP23

DPCD/DPD_VDD 18#2

AP14

DPCD/DPD_VDD 10#1

AP15

DPCD/DPD_VDD 10#2

AN19

DP/DPD_VSSR#1

AP18

DP/DPD_VSSR#2

AP19

DP/DPD_VSSR#3

AW20

DP/DPD_VSSR#4

AW22

DP/DPD_VSSR#5

AW18

DPCD_CALR

DP E/F POWER

AH34

DPEF/DPE_VDD18# 1

AJ34

DPEF/DPE_VDD18# 2

AL33

DPEF/DPE_VDD10# 1

AM33

DPEF/DPE_VDD10# 2

AN34

DP/DPE_VSSR#1

AP39

DP/DPE_VSSR#2

AR39

DP/DPE_VSSR#3

AU37

DP/DPE_VSSR#4

AF34

DPEF/DPF_VDD18# 1

AG34

DPEF/DPF_VDD18# 2

AK33

DPEF/DPF_VDD10# 1

AK34

DPEF/DPF_VDD10# 2

AF39

DP/DPF_VSSR#1

AH39

DP/DPF_VSSR#2

AK39

DP/DPF_VSSR#3

AL34

DP/DPF_VSSR#4

AM34

DP/DPF_VSSR#5

AM39

DPEF_CALR

12

216-0833000-A11-THAMES-XT-M2_FCBGA962~D

DIS@

DP A/B POWER

DPAB/DPA_VDD18#1
DPAB/DPA_VDD18#2

DPAB/DPA_VDD10#1
DPAB/DPA_VDD10#2

DP/DPA_VSSR#1
DP/DPA_VSSR#2
DP/DPA_VSSR#3
DP/DPA_VSSR#4
DP/DPA_VSSR#5

DPAB/DPB_VDD18#1
DPAB/DPB_VDD18#2

DPAB/DPB_VDD10#1
DPAB/DPB_VDD10#2

DP/DPB_VSSR#1
DP/DPB_VSSR#2
DP/DPB_VSSR#3
DP/DPB_VSSR#4
DP/DPB_VSSR#5

DPAB_CALR

DP PLL POWER

DPAB_VDD18/DPA_PVDD

DP_VSSR/DPA_PVSS

DPAB_VDD18/DPB_P VDD

DP_VSSR/DPB_PVSS

DPCD_VDD18/D PC_PVDD

DP_VSSR/DPC_PVSS

DPCD_VDD18/D PD_PVDD

DP_VSSR/DPD_PVSS

DPEF_VDD18/DPE_ PVDD

DP_VSSR/DPE_PVSS

DPEF_VDD18/DPF_ PVDD

DP_VSSR/DPF_PVSS

1.8V@300mA DPAB_VDD18)

+DPAB_VDD18

CV37

20mil

130mA

DIS@

AN24
AP24

0.1U_0402_16V7K

(1.0V@220mA DPAB_VDD10)

20mil

110mA

0.95V@Venus

+DPAB_VDD10

AP31
AP32

CV43

AN27
AP27
AP28

DIS@

AW24

0.1U_0402_16V7K

AW26

+DPAB_VDD18

20mil

130mA

AP25
AP26

+DPAB_VDD10

20mil

110mA

AN33
AP33

AN29
AP29
AP30
AW30
AW32

AW28

1 2

+DPAB_VDD18

20mA

10mil

AU28
AV27

+DPAB_VDD18

20mA

10mil

AV29
AR28

+DPCD_VDD18

20mA

10mil

AU18
AV17

+DPCD_VDD18

20mA

10mil

AV19
AR18

+DPEF_VDD18

20mA

10mil

AM37
AN38

+DPEF_VDD18

20mA

10mil

AL38
AM35

1

CV38

2

DIS@

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

DIS@

RV54
150_0402_1%

3

(30mA)

1

CV39

2

DIS@

10U_0603_6.3V6M

1

CV44

DIS@

2

10U_0603_6.3V6M

+DPAB_VDD18

1

2

(330mA)

1

CV45

DIS@

2

1 2

RV57

+DPAB_VDD10

RV51

0_0402_5%

1 2

0_0402_5%

SIT

+1.8VGS

SIT

+VGA_PCIE

2

UV1F

AB39

PCIE_VSS#1

E39

PCIE_VSS#2

F34

PCIE_VSS#3

F39

PCIE_VSS#4

G33

PCIE_VSS#5

G34

PCIE_VSS#6

H31

PCIE_VSS#7

H34

PCIE_VSS#8

H39

PCIE_VSS#9

J31

PCIE_VSS#10

J34

PCIE_VSS#11

K31

PCIE_VSS#12

K34

PCIE_VSS#13

K39

PCIE_VSS#14

L31

PCIE_VSS#15

L34

PCIE_VSS#16

M34

PCIE_VSS#17

M39

PCIE_VSS#18

N31

PCIE_VSS#19

N34

PCIE_VSS#20

P31

PCIE_VSS#21

P34

PCIE_VSS#22

P39

PCIE_VSS#23

R34

PCIE_VSS#24

T31

PCIE_VSS#25

T34

PCIE_VSS#26

T39

PCIE_VSS#27

U31

PCIE_VSS#28

U34

PCIE_VSS#29

V34

PCIE_VSS#30

V39

PCIE_VSS#31

W31

PCIE_VSS#32

W34

PCIE_VSS#33

Y34

PCIE_VSS#34

Y39

PCIE_VSS#35

F15
F17
F19
F21
F23
F25
F27
F29
F31
F33

F7

F9
G2
G6
H9

J2

J27

J6

J8

K14

K7

L11
L17

L2

L22
L24

L6

M17
M22
M24
N16
N18

N2

N21
N23
N26

N6

R15
R17

R2

R20
R22
R24
R27

R6

T11
T13
T16
T18
T21
T23
T26
U15
U17

U2

U20
U22
U24
U27

U6

V11
V16
V18
V21
V23
V26

W2

W6
Y15
Y17
Y20
Y22
Y24
Y27
U13
V13

GND

GND#100
GND#101
GND#102
GND#103
GND#104
GND#105
GND#106
GND#107
GND#108
GND#109
GND#110
GND#111
GND#112
GND#113
GND#114
GND#115
GND#116
GND#117
GND#118
GND#119
GND#120
GND#121
GND#122
GND#123
GND#124
GND#125
GND#126
GND#127
GND#128
GND#129
GND#130
GND#131
GND#132
GND#133
GND#134
GND#135
GND#136
GND#137
GND#138
GND#139
GND#140
GND#141
GND#142
GND#143
GND#144
GND#145
GND#146
GND#147
GND#148
GND#149
GND#150
GND#151
GND#153
GND#154
GND#155
GND#156
GND#157
GND#158
GND#159
GND#160
GND#161
GND#163
GND#164
GND#165
GND#166
GND#167
GND#168
GND#169
GND#170
GND#171
GND#172
GND#173
GND#174
GND#175
GND#152
GND#162

216-0833000-A11-THAMES-XT-M2_FCBGA962~D

DIS@

GND#1
GND#2
GND#3
GND#4
GND#5
GND#6
GND#7
GND#8

GND#9
GND#10
GND#11
GND#12
GND#13
GND#14
GND#15
GND#16
GND#17
GND#18
GND#19
GND#20
GND#21
GND#22
GND#23
GND#24
GND#25
GND#26
GND#27
GND#28
GND#29
GND#30
GND#31
GND#32
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55
GND#56
GND#57
GND#58
GND#59
GND#60

GND/PX_EN#61

GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84
GND#85
GND#86
GND#87
GND#88
GND#89
GND#90
GND#91
GND#92
GND#93
GND#94
GND#95
GND#96
GND#97
GND#98

VSS_MECH#1
VSS_MECH#2
VSS_MECH#3

A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20
AG22
AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20
AL21
AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13

A39
AW1
AW39

12

@DIS@

RV56

4.7K_0402_5%

T86 PAD
T87 PAD
T88 PAD

1

w w w . c h i n a f i x . c o m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/03/03 2015/03/03

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Venus XTX(4/8)DPX Power/GND

Size Document Number Rev

Custom

Date: Sheet of

LA-B131P

1

20 52Tuesday, March 04, 2014

1.0

5

4

3

2

1

(440mA)

(1.8V@504mA PCIE_VDDR)

+PCIE_VDDR

1

1

1

CV58

CV56

CV57

2

2

D D

C C

B B

+1.8VGS

(100mA)

+VGA_PCIE

CHILISIN PBY100505T-300Y-N 0402

SVT

+MEM_GFX

220U_B2_2.5VM_R35

CV70

1

+

@DIS@

2

+1.8VGS +VDDC_CT

+3VGS

(60mA)

1

1

CV94

CV93

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

10U_0603_6.3V6M

(50mA)

LV11

DIS@

1 2

BLM15BD121SN1D_0402

0.95V@Venus

LV13

DIS@

1 2

connect to PWR

A A

For GDDR3 MVDDQ = 1.5V

(1.7)A

1

1

1

CV61

CV71

CV72

2

2

2

DIS@

DIS@

DIS@

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

(50mA)

LV8

DIS@

1 2

BLM15BD121SN1D_0402

1

1

CV95

CV96

2

2

1U_0402_6.3V6K

DIS@

DIS@

+1.8VGS

(150mA)

+1.8VGS

(M97, Broadway and Madison: 1.8V@150mA MPV18)

LV10

1 2

CHILISIN PBY100505T-300Y-N 0402

(1.8V@75mA SPV18)

1

1

1

CV104

CV106

CV105

2

2

2

1U_0402_6.3V6K

DIS@

DIS@

DIS@

0.1U_0402_16V7K

10U_0603_6.3V6M

(120mA SPV10)

1

1

1

CV108

CV109

CV107

2

2

2

1U_0402_6.3V6K

DIS@

DIS@

DIS@

0.1U_0402_16V7K

10U_0603_6.3V6M

VDDC_SEN45

VDDC_RTN45

1

1

1

1

CV74

CV73

CV75

CV62

2

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

DIS@

+MEM_GFX

1

CV83

2

DIS@

0.1U_0402_16V7K

DIS@

1

CV84

2

DIS@

0.1U_0402_16V7K

10U_0603_6.3V6M

(1.8V@110mA VDD_CT)

1

1

1

1

CV89

CV91

CV90

CV88

2

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

DIS@

DIS@

10U_0603_6.3V6M

DIS@

LV9

1 2

BLM15BD121SN1D_0402

1U_0402_6.3V6K

SVT

DIS@

1

CV101

2

1U_0402_6.3V6K

DIS@

10U_0603_6.3V6M

VDDC_SEN

VDDC_RTN

1

1

1

CV77

CV63

CV76

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

DIS@

1

1

1

CV65

CV85

CV86

2

2

2

DIS@

DIS@

DIS@

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

1

CV92

2

DIS@

0.1U_0402_16V7K

1

1

CV97

CV98

2

2

DIS@

DIS@

0.1U_0402_16V7K

1

1

CV103

CV102

2

2

DIS@

DIS@

0.1U_0402_16V7K

+MPV18

10mil
20mil

+VGA_CORE

12

RV64
10_0402_1%

DIS@

12

RV65

10_0402_1%DIS@

UV1E

MEM I/O

AC7

VDDR1#1

AD11

VDDR1#2

AF7

VDDR1#3

AG10

VDDR1#4

AJ7

VDDR1#5

AK8

VDDR1#6

AL9

VDDR1#7

G11

VDDR1#8

G14

VDDR1#9

G17

VDDR1#10

G20

VDDR1#11

G23

VDDR1#12

G26

VDDR1#13

G29

VDDR1#14

H10

VDDR1#15

J7

VDDR1#16

J9

VDDR1#17

K11

VDDR1#18

K13

VDDR1#19

K8

VDDR1#20

L12

VDDR1#21

L16

VDDR1#22

L21

VDDR1#23

L23

VDDR1#24

L26

VDDR1#25

L7

VDDR1#26

M11

VDDR1#27

N11

VDDR1#28

P7

VDDR1#29

R11

VDDR1#30

U11

VDDR1#31

U7

VDDR1#32

Y11

VDDR1#33

Y7

VDDR1#34

LEVEL

20mil

TRANSLATION

AF26

VDD_CT#1

AF27

VDD_CT#2

AG26

VDD_CT#3

AG27

VDD_CT#4

10mil

20mil

+VDDR4

20mil

+SPV18

+SPV10

I/O

AF23

VDDR3#1

AF24

VDDR3#2

AG23

VDDR3#3

AG24

VDDR3#4

AF13

VDDR4#4

AF15

VDDR4#5

AG13

VDDR4#7

AG15

VDDR4#8

AD12

VDDR4#1

AF11

VDDR4#2

AF12

VDDR4#3

AG11

VDDR4#6

M20

NC_VDDRHA

M21

NC_VSSRHA

V12

NC_VDDRHB

U12

NC_VSSRHB

PLL

H7

MPV18#1

H8

MPV18#2

AM10

SPV18

AN9

SPV10

AN10

SPVSS

VOLTAGE
SENESE

10mil

AF28

FB_VDDC

10mil

AG28

FB_VDDCI

AH29

FB_GND

216-0833000-A11-THAMES-XT-M2_FCBGA962~D

DIS@

PCIE

PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8

PCIE_VDDR/PCIE_PVDD

PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8

PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12

VDDC#1

CORE

VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8

VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15

POWER

VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23
VDDC#24
VDDC#25
VDDC#26
VDDC#27
VDDC#28
VDDC#29
VDDC#30
VDDC#31
VDDC#32

VDDC/BIF_VDDC#33

VDDC#34
VDDC#35
VDDC#36
VDDC#37
VDDC#38
VDDC#39
VDDC#40
VDDC#41

VDDC/BIF_VDDC#42

VDDC#43
VDDC#44
VDDC#45
VDDC#46
VDDC#47
VDDC#48
VDDC#49
VDDC#50
VDDC#51
VDDC#52
VDDC#53
VDDC#54
VDDC#55
VDDC#56
VDDC#57
VDDC#58

VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8

VDDCI#9
VDDCI#10
VDDCI#11
VDDCI#12
VDDCI#13
VDDCI#14
VDDCI#15

ISOLATED

VDDCI#16

CORE I/O

VDDCI#17
VDDCI#18
VDDCI#19
VDDCI#20
VDDCI#21
VDDCI#22

40mil

AA31
AA32
AA33
AA34
V28
W29
W30
Y31

+PCIE_PVDD

AB37

G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28

AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AG21
AH22
AH27
AH28
M26
N24
N27
R18
R21
R23
R26
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28

(GDDR3/DDR3 1.12V@4A VDDCI)

(GDDR5 1.12V@16A VDDCI)

AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13

VDDCI and VDDC should have seperate regulators with a merge option on PCB
For Madison, Park, Capilano, Robson, Seymour and Whistler, VDDCI and VDDC can share one common regulator

0.1U_0402_16V7K

0.1U_0402_16V7K

@DIS@

@DIS@

1 2

RV61 0_0402_5%

@DIS@

1 2

RV62 0_0402_5%

+VGA_CORE

(20.5A)

1

CV87
330U_D2_2.5V_R6M

2

ESD@

+BIF_VDDC

1

CV99

2

1U_0402_6.3V6K

DIS@

1

1

CV110

CV111

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

2

1U_0402_6.3V6K

@DIS@

@DIS@

+PCIE_VDDR

1

CV78

2

1U_0402_6.3V6K

DIS@

ESD solution

55mA

1

CV100

2

1U_0402_6.3V6K

DIS@

1

1

CV113

CV112

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

1

1

1

CV60

CV59

CV66

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

@DIS@

@DIS@

@DIS@

+BIF_VDDC

1

1

1

CV80

CV79

CV81

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

DIS@

For non-BACO designs, connect BIF_VDDC to VDDC.
For BACO designs - see BACO reference schematics

1

1

CV114

CV115

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

+1.8VGS

LV6

@DIS@

1 2

BLM15PD121SN1D_0402

SIV

40mA

1

CV67

2

DIS@

0.1U_0402_16V7K

+VGA_PCIE

1

1

CV64

CV82

2

2

1U_0402_6.3V6K

DIS@

DIS@

10U_0603_6.3V6M

1

1

1

CV117

CV116

CV118

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

DIS@

+1.8VGS

LV7

DIS@

1 2

BLM15PD121SN1D_0402

1

1

CV69

CV68

2

2

1U_0402_6.3V6K

DIS@

DIS@

10U_0603_6.3V6M

(SUN)

(VENUS)

(PCIe 2.0 => +0.95V@1920mA PCIE_VDDC)

(PCIe 3.0 => +0.95V@2.5A PCIE_VDDC)

+VGA_CORE

4A

1

1

1

CV120

CV119

CV121

2

2

2

1U_0402_6.3V6K

DIS@

DIS@

DIS@

10U_0603_6.3V6M

10U_0603_6.3V6M

(SUN)(VENUS)

SIV

(PCIe 2.0 => 1.8V@50mA PCIE_PVDD)

(PCIe 3.0 => 1.8V@80mA PCIE_PVDD)

w w w . c h i n a f i x . c o m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/03/03 2015/03/03

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Venus XTX(5/8) Power

LA-B131P

1

21 52Tuesday, March 04, 2014

1.0

5

4

3

2

1

M_DA[63..0]23

M_MAA[14..0]23

M_DQMA[7..0]23

M_DQSA[7..0]23

M_DQSA#[7..0]23

D D

C C

B B

M_DA[63..0]

M_MAA[14..0]

M_DQMA[7..0]

M_DQSA[7..0]

M_DQSA#[7..0]

RV67 DIS@ 120_0402_1%

1 2

M_DA0
M_DA1
M_DA2
M_DA3
M_DA4
M_DA5
M_DA6
M_DA7
M_DA8
M_DA9
M_DA10
M_DA11
M_DA12
M_DA13
M_DA14
M_DA15
M_DA16
M_DA17
M_DA18
M_DA19
M_DA20
M_DA21
M_DA22
M_DA23
M_DA24
M_DA25
M_DA26
M_DA27
M_DA28
M_DA29
M_DA30
M_DA31
M_DA32
M_DA33
M_DA34
M_DA35
M_DA36
M_DA37
M_DA38
M_DA39
M_DA40
M_DA41
M_DA42
M_DA43
M_DA44
M_DA45
M_DA46
M_DA47
M_DA48
M_DA49
M_DA50
M_DA51
M_DA52
M_DA53
M_DA54
M_DA55
M_DA56
M_DA57
M_DA58
M_DA59
M_DA60
M_DA61
M_DA62
M_DA63

+VDD_MEM15_REFDA
+VDD_MEM15_REFSA

UV1C

DDR2
GDDR3/GDDR5
DDR3

C37

DQA0_0/DQA_0

C35

DQA0_1/DQA_1

A35

DQA0_2/DQA_2

E34

DQA0_3/DQA_3

G32

DQA0_4/DQA_4

D33

DQA0_5/DQA_5

F32

DQA0_6/DQA_6

E32

DQA0_7/DQA_7

D31

DQA0_8/DQA_8

F30

DQA0_9/DQA_9

C30

DQA0_10/DQA_10

A30

DQA0_11/DQA_11

F28

DQA0_12/DQA_12

C28

DQA0_13/DQA_13

A28

DQA0_14/DQA_14

E28

DQA0_15/DQA_15

D27

DQA0_16/DQA_16

F26

DQA0_17/DQA_17

C26

DQA0_18/DQA_18

A26

DQA0_19/DQA_19

F24

DQA0_20/DQA_20

C24

DQA0_21/DQA_21

A24

DQA0_22/DQA_22

E24

DQA0_23/DQA_23

C22

DQA0_24/DQA_24

A22

DQA0_25/DQA_25

F22

DQA0_26/DQA_26

D21

DQA0_27/DQA_27

A20

DQA0_28/DQA_28

F20

DQA0_29/DQA_29

D19

DQA0_30/DQA_30

E18

DQA0_31/DQA_31

C18

DQA1_0/DQA_32

A18

DQA1_1/DQA_33

F18

DQA1_2/DQA_34

D17

DQA1_3/DQA_35

A16

DQA1_4/DQA_36

F16

DQA1_5/DQA_37

D15

DQA1_6/DQA_38

E14

DQA1_7/DQA_39

F14

DQA1_8/DQA_40

D13

DQA1_9/DQA_41

F12

DQA1_10/DQA_42

A12

DQA1_11/DQA_43

D11

DQA1_12/DQA_44

F10

DQA1_13/DQA_45

A10

DQA1_14/DQA_46

C10

DQA1_15/DQA_47

G13

DQA1_16/DQA_48

H13

DQA1_17/DQA_49

J13

DQA1_18/DQA_50

H11

DQA1_19/DQA_51

G10

DQA1_20/DQA_52

G8

DQA1_21/DQA_53

K9

DQA1_22/DQA_54

K10

DQA1_23/DQA_55

G9

DQA1_24/DQA_56

A8

DQA1_25/DQA_57

C8

DQA1_26/DQA_58

E8

DQA1_27/DQA_59

A6

DQA1_28/DQA_60

C6

DQA1_29/DQA_61

E6

DQA1_30/DQA_62

A5

DQA1_31/DQA_63

L18

MVREFDA

L20

MVREFSA

L27

MEM_CALRN0

N12

MEM_CALRN1

AG12

MEM_CALRN2

M12

MEM_CALRP1

M27

MEM_CALRP0

AH12

MEM_CALRP2

216-0833000-A11-THAMES-XT-M2_FCBGA962~D

DIS@

MEMORY INTERFACE A

EDCA0_0/QSA_0/RDQS A_0
EDCA0_1/QSA_1/RDQS A_1
EDCA0_2/QSA_2/RDQS A_2
EDCA0_3/QSA_3/RDQS A_3
EDCA1_0/QSA_4/RDQS A_4
EDCA1_1/QSA_5/RDQS A_5
EDCA1_2/QSA_6/RDQS A_6
EDCA1_3/QSA_7/RDQS A_7

DDBIA0_0/QSA_0B/WD QSA_0
DDBIA0_1/QSA_1B/WD QSA_1
DDBIA0_2/QSA_2B/WD QSA_2
DDBIA0_3/QSA_3B/WD QSA_3
DDBIA1_0/QSA_4B/WD QSA_4
DDBIA1_1/QSA_5B/WD QSA_5
DDBIA1_2/QSA_6B/WD QSA_6
DDBIA1_3/QSA_7B/WD QSA_7

DDR2
GDDR5/GDDR3
DDR3

MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA1_0/MAA_8

MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12

MAA1_5/MAA_13_BA2
MAA1_6/MAA_14_BA0

MAA1_7/MAA_A15_BA1

WCKA0_0/DQM A_0

WCKA0B_0/DQ MA_1

WCKA0_1/DQM A_2

WCKA0B_1/DQ MA_3

WCKA1_0/DQM A_4

WCKA1B_0/DQ MA_5

WCKA1_1/DQM A_6

WCKA1B_1/DQ MA_7

GDDR5/DDR2/GDDR3

ADBIA0/ODTA0
ADBIA1/ODTA1

CLKA0B

CLKA1B

RASA0B
RASA1B

CASA0B
CASA1B

CSA0B_0
CSA0B_1

CSA1B_0
CSA1B_1

WEA0B
WEA1B

MAA0_8
MAA1_8

GDDR5

M_MAA0

G24

M_MAA1

J23

M_MAA2

H24

M_MAA3

J24

M_MAA4

H26

M_MAA5

J26

M_MAA6

H21

M_MAA7

G21

M_MAA8

H19

M_MAA9

H20

M_MAA10

L13

M_MAA11

G16

M_MAA12

J16

M_A_BA2

H16

M_A_BA0

J17

M_A_BA1

H17

M_DQMA0

A32

M_DQMA1

C32

M_DQMA2

D23

M_DQMA3

E22

M_DQMA4

C14

M_DQMA5

A14

M_DQMA6

E10

M_DQMA7

D9

M_DQSA0

C34

M_DQSA1

D29

M_DQSA2

D25

M_DQSA3

E20

M_DQSA4

E16

M_DQSA5

E12

M_DQSA6

J10

M_DQSA7

D7

M_DQSA#0

A34

M_DQSA#1

E30

M_DQSA#2

E26

M_DQSA#3

C20

M_DQSA#4

C16

M_DQSA#5

C12

M_DQSA#6

J11

M_DQSA#7

F8

J21
G19

H27

CLKA0

G27

J14

CLKA1

H14

K23
K19

K20
K17

K24
K27

M13
K16

K21

CKEA0

J20

CKEA1

K26
L15

M_MAA13

H23

M_MAA14

J19

This basic topology should be used for DRAM_RST for DDR3/GDDR5.These
Capacitors and Resistor values are an example only. The Series R and
|| Cap values will depend on the DRAM load and will have to be
calculated for different Memory ,DRAM Load and board to pass Reset
Signal Spec.
Place all these components very close to GPU (Within
25mm) and keep all component close to each Other (within
5mm) except Rser2

M_A_BA2 23
M_A_BA0 23
M_A_BA1 23

VRAM_ODTA0 23
VRAM_ODTA1 23

M_CLKA0 23
M_CLKA#0 23

M_CLKA1 23
M_CLKA#1 23

M_RASA#0 23
M_RASA#1 23

M_CASA#0 23
M_CASA#1 23

M_CSA0#_0 23

M_CSA1#_0 23

M_CKEA0 23
M_CKEA1 23

M_WEA#0 23
M_WEA#1 23

M_DB[63..0]24

M_MAB[14..0]24

M_DQMB[7..0]24

M_DQSB[7..0]24

M_DQSB#[7..0]24

M_DB[63..0]

M_MAB[14..0]

M_DQMB[7..0]

M_DQSB[7..0]

M_DQSB#[7..0]

RV66

1 2

1K_0402_5%

0.1U_0402_16V7K

M_DB0
M_DB1
M_DB2
M_DB3
M_DB4
M_DB5
M_DB6
M_DB7
M_DB8
M_DB9
M_DB10
M_DB11
M_DB12
M_DB13
M_DB14
M_DB15
M_DB16
M_DB17
M_DB18
M_DB19
M_DB20
M_DB21
M_DB22
M_DB23
M_DB24
M_DB25
M_DB26
M_DB27
M_DB28
M_DB29
M_DB30
M_DB31
M_DB32
M_DB33
M_DB34
M_DB35
M_DB36
M_DB37
M_DB38
M_DB39
M_DB40
M_DB41
M_DB42
M_DB43
M_DB44
M_DB45
M_DB46
M_DB47
M_DB48
M_DB49
M_DB50
M_DB51
M_DB52
M_DB53
M_DB54
M_DB55
M_DB56
M_DB57
M_DB58
M_DB59
M_DB60
M_DB61
M_DB62
M_DB63

+VDD_MEM15_REFDB
+VDD_MEM15_REFSB

DIS@

CV126

RV68

51.1_0402_1%

@DIS@

@DIS@

TESTEN

12

12

UV1D

DDR2
GDDR3/GDDR5
DDR3

C5

DQB0_0/DQB_0

C3

DQB0_1/DQB_1

E3

DQB0_2/DQB_2

E1

DQB0_3/DQB_3

F1

DQB0_4/DQB_4

F3

DQB0_5/DQB_5

F5

DQB0_6/DQB_6

G4

DQB0_7/DQB_7

H5

DQB0_8/DQB_8

H6

DQB0_9/DQB_9

J4

DQB0_10/DQB_1 0

K6

DQB0_11/DQB_1 1

K5

DQB0_12/DQB_1 2

L4

DQB0_13/DQB_1 3

M6

DQB0_14/DQB_1 4

M1

DQB0_15/DQB_1 5

M3

DQB0_16/DQB_1 6

M5

DQB0_17/DQB_1 7

N4

DQB0_18/DQB_1 8

P6

DQB0_19/DQB_1 9

P5

DQB0_20/DQB_2 0

R4

DQB0_21/DQB_2 1

T6

DQB0_22/DQB_2 2

T1

DQB0_23/DQB_2 3

U4

DQB0_24/DQB_2 4

V6

DQB0_25/DQB_2 5

V1

DQB0_26/DQB_2 6

V3

DQB0_27/DQB_2 7

Y6

DQB0_28/DQB_2 8

Y1

DQB0_29/DQB_2 9

Y3

DQB0_30/DQB_3 0

Y5

DQB0_31/DQB_3 1

AA4

DQB1_0/DQB_32

AB6

DQB1_1/DQB_33

AB1

DQB1_2/DQB_34

AB3

DQB1_3/DQB_35

AD6

DQB1_4/DQB_36

AD1

DQB1_5/DQB_37

AD3

DQB1_6/DQB_38

AD5

DQB1_7/DQB_39

AF1

DQB1_8/DQB_40

AF3

DQB1_9/DQB_41

AF6

DQB1_10/DQB_4 2

AG4

DQB1_11/DQB_4 3

AH5

DQB1_12/DQB_4 4

AH6

DQB1_13/DQB_4 5

AJ4

DQB1_14/DQB_4 6

AK3

DQB1_15/DQB_4 7

AF8

DQB1_16/DQB_4 8

AF9

DQB1_17/DQB_4 9

AG8

DQB1_18/DQB_5 0

AG7

DQB1_19/DQB_5 1

AK9

DQB1_20/DQB_5 2

AL7

DQB1_21/DQB_5 3

AM8

DQB1_22/DQB_5 4

AM7

DQB1_23/DQB_5 5

AK1

DQB1_24/DQB_5 6

AL4

DQB1_25/DQB_5 7

AM6

DQB1_26/DQB_5 8

AM1

DQB1_27/DQB_5 9

AN4

DQB1_28/DQB_6 0

AP3

DQB1_29/DQB_6 1

AP1

DQB1_30/DQB_6 2

AP5

DQB1_31/DQB_6 3

Y12

MVREFDB

AA12

MVREFSB

AD28

TESTEN

AK10

CLKTESTA

AL10

CLKTESTB

216-0833000-A11-THAMES-XT-M2_FCBGA962~D

DIS@

12

@DIS@

CV127

0.1U_0402_16V7K

12

@DIS@

RV69

51.1_0402_1%

route 50ohms single-ended/100ohms diff
and keep short
Debug only, for clock observation, if not needed, DNI
5mil 5mil

DDR2
GDDR5/GDDR3
DDR3

MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8

MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12

WCKB0_0 /DQMB_0

WCKB0B_0 /DQMB_1

WCKB0_1 /DQMB_2

WCKB0B_1 /DQMB_3

WCKB1_0 /DQMB_4

WCKB1B_0 /DQMB_5

WCKB1_1 /DQMB_6

WCKB1B_1 /DQMB_7

GDDR5/DDR2/GDDR3

EDCB0_0/QSB_0 /RDQSB_0

MEMORY INTERFACE B

EDCB0_1/QSB_1 /RDQSB_1
EDCB0_2/QSB_2 /RDQSB_2
EDCB0_3/QSB_3 /RDQSB_3
EDCB1_0/QSB_4 /RDQSB_4
EDCB1_1/QSB_5 /RDQSB_5
EDCB1_2/QSB_6 /RDQSB_6
EDCB1_3/QSB_7 /RDQSB_7

DDBIB0_0/QSB_0B/W DQSB_0
DDBIB0_1/QSB_1B/W DQSB_1
DDBIB0_2/QSB_2B/W DQSB_2
DDBIB0_3/QSB_3B/W DQSB_3
DDBIB1_0/QSB_4B/W DQSB_4
DDBIB1_1/QSB_5B/W DQSB_5
DDBIB1_2/QSB_6B/W DQSB_6
DDBIB1_3/QSB_7B/W DQSB_7

ADBIB0/ODTB0
ADBIB1/ODTB1

MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1

CLKB0

CLKB0B

CLKB1

CLKB1B

RASB0B
RASB1B

CASB0B
CASB1B

CSB0B_0
CSB0B_1

CSB1B_0
CSB1B_1

CKEB0
CKEB1

WEB0B
WEB1B

MAB0_8
MAB1_8

DRAM_RST

GDDR5

P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9

H3
H1
T3
T5
AE4
AF5
AK6
AK5

F6
K3
P3
V5
AB5
AH1
AJ9
AM5

G7
K1
P1
W4
AC4
AH3
AJ8
AM3

T7
W7

L9
L8

AD8
AD7

T10
Y10

W10
AA10

P10
L10

AD10
AC10

U10
AA11

N10
AB11

T8
W8

AH11

DRAM_RST#_R

M_MAB0
M_MAB1
M_MAB2
M_MAB3
M_MAB4
M_MAB5
M_MAB6
M_MAB7
M_MAB8
M_MAB9
M_MAB10
M_MAB11
M_MAB12

M_DQMB0
M_DQMB1
M_DQMB2
M_DQMB3
M_DQMB4
M_DQMB5
M_DQMB6
M_DQMB7

M_DQSB0
M_DQSB1
M_DQSB2
M_DQSB3
M_DQSB4
M_DQSB5
M_DQSB6
M_DQSB7

M_DQSB#0
M_DQSB#1
M_DQSB#2
M_DQSB#3
M_DQSB#4
M_DQSB#5
M_DQSB#6
M_DQSB#7

M_MAB13
M_MAB14

M_B_BA2
M_B_BA0
M_B_BA1

M_B_BA2 24
M_B_BA0 24
M_B_BA1 24

VRAM_ODTB0 24
VRAM_ODTB1 24

M_CLKB0 24
M_CLKB#0 24

M_CLKB1 24
M_CLKB#1 24

M_RASB#0 24
M_RASB#1 24

M_CASB#0 24
M_CASB#1 24

M_CSB0#_0 24

M_CSB1#_0 24

M_CKEB0 24
M_CKEB1 24

M_WEB#0 24
M_WEB#1 24

+MEM_GFX

12

RV70

4.7K_0402_5%

@DIS@

+MEM_GFX +MEM_GFX

12

RV75

40.2_0402_1%

A A

DIS@

RV80

100_0402_1%

DIS@

12

5

+VDD_MEM15_REFDA

1

CV131
1U_0402_6.3V6K

DIS@

2

RV76

40.2_0402_1%

DIS@

RV81

100_0402_1%

DIS@

12

12

+VDD_MEM15_REFSA

1

CV132

1U_0402_6.3V6K

DIS@

2

w w w . c h i n a f i x . c o m

DRAM_RST#23,24

4

RV73

1 2

51.1_0402_1%

DIS@

DIS@

CV128

120P_0402_50V9

12

1 2

10_0402_1%

3

RV74

DIS@

DRAM_RST#_R

DIS@

RV77

4.99K_0402_1%

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/03/03 2015/03/03

+MEM_GFX +MEM_GFX

12

RV71

40.2_0402_1%

DIS@

+VDD_MEM15_REFDB

1

12

RV78

100_0402_1%

DIS@

CV129
1U_0402_6.3V6K

DIS@

2

Compal Secret Data

Deciphered Date

2

RV72

40.2_0402_1%

DIS@

RV79

100_0402_1%

DIS@

12

+VDD_MEM15_REFSB

1

12

CV130
1U_0402_6.3V6K

DIS@

2

Compal Electronics, Inc.

Title

Venus XTX(6/8)MEM Interface

Size Document Number Rev

Custom

Date: Sheet

LA-B131P

1

1.0

of

22 52Tuesday, March 04, 2014

5

4

3

2

1

M_DA[63..0]22

M_MAA[14..0]22

M_DQMA[7..0]22

M_DQSA[7..0]22

M_DQSA#[7..0]22

D D

C C

B B

A A

M_CLKA0

M_CLKA#0

M_CLKA1

M_CLKA#1

ref Mars_M2 recommand

VRAM P/N :

Hynix : SA00003YO40 (S IC D3 128M16 H5TQ2G63BFR-11C 96P C38A! )

Samsung : SA000047Q30 (S IC D3 128M16 K4W2G1646C-HC11 96P C38A!)

update VRAM PN

M_DA[63..0]

M_MAA[14..0]

M_DQMA[7..0]

M_DQSA[7..0]

M_DQSA#[7..0]

DIS@

1 2

R117 40.2_0402_1%

DIS@

1 2

R118 40.2_0402_1%

DIS@

1 2

R126 40.2_0402_1%

DIS@

1 2

R128 40.2_0402_1%

5

M_A_BA022
M_A_BA122
M_A_BA222

M_CLKA022
M_CLKA#022

VRAM_ODTA022

M_CSA0#_022
M_RASA#022
M_CASA#022
M_WEA#022

DRAM_RST#22,24

243_0402_1%

1

C150

0.01U_0402_16V7K

DIS@

2

1

C155

0.01U_0402_16V7K

DIS@

2

R113

DIS@

VREFC_A56
VREFD_Q56

M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_MAA12
M_MAA13
M_MAA14

M_A_BA0
M_A_BA1
M_A_BA2

M_CLKA0
M_CLKA#0
M_CKEA0

VRAM_ODTA0
M_CSA0#_0
M_RASA#0
M_CASA#0
M_WEA#0

M_DQSA2
M_DQSA0

M_DQMA2
M_DQMA0

M_DQSA#2
M_DQSA#0

DRAM_RST#

12

U14

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

SDRAM DDR3

K4W2G1646E-BC1A

@

U15

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

SDRAM DDR3

K4W2G1646E-BC1A

@

VREFC_A56

0.1U_0402_16V7K

1

C151

2

DIS@

+MEM_GFX

10U_0603_6.3V6M

C156

DIS@

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

R119

4.99K_0402_1%

DIS@

R123

4.99K_0402_1%

DIS@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

M_DA20

E3

M_DA21

F7

M_DA19

F2

M_DA18

F8

M_DA22

H3

M_DA17

H8

M_DA23

G2

M_DA16

H7

M_DA1

D7

M_DA7

C3

M_DA0

C8

M_DA6

C2

M_DA3

A7

M_DA4

A2

M_DA2

B8

M_DA5

A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

+MEM_GFX

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

12

VREFD_Q56

12

0.1U_0402_16V7K

1

C154

2

DIS@

R114

243_0402_1%

DIS@

4.99K_0402_1%

4.99K_0402_1%

DIS@

VREFD_Q56
VREFC_A56

M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_MAA12
M_MAA13
M_MAA14

M_DQSA3
M_DQSA1

M_DQMA3
M_DQMA1

M_DQSA#3
M_DQSA#1

DRAM_RST#

12

+MEM_GFX+MEM_GFX

R120

DIS@

R127

M_A_BA0
M_A_BA1
M_A_BA2

M_CLKA0
M_CLKA#0
M_CKEA0

VRAM_ODTA0
M_CSA0#_0
M_RASA#0
M_CASA#0
M_WEA#0

12

12

w w w . c h i n a f i x . c o m

Place across each VDDIO-GND plane seam

4

M_DA27

E3

DQL0

M_DA24

F7

DQL1

M_DA31

F2

DQL2

M_DA25

F8

DQL3

M_DA26

H3

DQL4

M_DA28

H8

DQL5

M_DA29

G2

DQL6

M_DA30

H7

DQL7

M_DA15

D7

DQU0

M_DA10

C3

DQU1

M_DA12

C8

DQU2

M_DA11

C2

DQU3

M_DA14

A7

DQU4

M_DA9

A2

DQU5

M_DA13

B8

DQU6

M_DA8

A3

DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

1

C157

DIS@

2

10U_0603_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

+MEM_GFX

+MEM_GFX

10U_0603_6.3V6M

1

C158

DIS@

2

3

VRAM_ODTA122

M_CSA1#_022
M_RASA#122
M_CASA#122
M_WEA#122

10U_0603_6.3V6M

1

1

C159

DIS@

2

10U_0603_6.3V6M

C160

DIS@

2

1

C161

DIS@

2

10U_0603_6.3V6M

2014/03/03 2015/03/03

M_CLKA122
M_CLKA#122
M_CKEA122M_CKEA022

R115

243_0402_1%

DIS@

DIS@

4.99K_0402_1%

4.99K_0402_1%

1

2

Compal Secret Data

VREFC_A78
VREFD_Q78

M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_MAA12
M_MAA13 M_DA44
M_MAA14

M_A_BA0
M_A_BA1
M_A_BA2

M_CLKA1
M_CLKA#1
M_CKEA1

VRAM_ODTA1
M_CSA1#_0
M_RASA#1
M_CASA#1
M_WEA#1

M_DQSA4
M_DQSA5

M_DQMA4
M_DQMA5

M_DQSA#4
M_DQSA#5

DRAM_RST#

12

R121

R124

DIS@

+MEM_GFX

1U_0402_6.3V6K

Deciphered Date

M8
H1

N3

P7
P3

N2

P8

P2
R8
R2

T8
R3

L7
R7
N7

T3

T7
M7

M2
N8
M3

J7
K7
K9

K1
L2

J3
K3
L3

F3

C7

E7

D3

G3

B7

T2

L8

J1
L1

J9
L9

+MEM_GFX

12

12

1U_0402_6.3V6K

DIS@

DIS@

C163

C162

1

1

2

2

1U_0402_6.3V6K

U16

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

BA0
BA1
BA2

CK
CK
CKE/CKE0

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET

ZQ/ZQ0

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

96-BALL

SDRAM DDR3

K4W2G1646E-BC1A

@

VREFC_A78

0.1U_0402_16V7K

1

C152

4.99K_0402_1%

2

DIS@

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

C164

C165

1

1

1

2

2

2

1U_0402_6.3V6K

2

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DIS@

C166

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

+MEM_GFX

12

12

R125

DIS@

DIS@

C167

1

2

1U_0402_6.3V6K

M_DA37

E3

M_DA38

F7

M_DA34

F2

M_DA35

F8

M_DA33

H3

M_DA32

H8

M_DA39

G2

M_DA36

H7

M_DA40

D7

M_DA47

C3

M_DA43

C8

M_DA41

C2

M_DA46

A7

M_DA45

A2
B8

M_DA42

A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

R122

DIS@

4.99K_0402_1%

1

C153

2

DIS@

1U_0402_6.3V6K

DIS@

DIS@

C169

C168

1

1

2

2

1U_0402_6.3V6K

VREFD_Q78
VREFC_A78

M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_MAA12
M_MAA13

+MEM_GFX+MEM_GFX

+MEM_GFX

243_0402_1%

VREFD_Q78

0.1U_0402_16V7K

1U_0402_6.3V6K

DIS@

C170

1

2

M_MAA14

M_A_BA0
M_A_BA1
M_A_BA2

M_CLKA1
M_CLKA#1
M_CKEA1

VRAM_ODTA1
M_CSA1#_0
M_RASA#1
M_CASA#1
M_WEA#1

M_DQSA6
M_DQSA7

M_DQMA6
M_DQMA7

M_DQSA#6
M_DQSA#7

DRAM_RST#

12

R116

DIS@

+MEM_GFX

1U_0402_6.3V6K

DIS@

1

C171

1

2

2

1U_0402_6.3V6K

Title

Size Document Number Rev

Custom

Date: Sheet

DIS@

C172

U17

M8
H1

N3
P7
P3
N2
P8
P2
R8
R2

T8

R3

L7
R7
N7

T3

T7
M7

M2
N8
M3

J7
K7
K9

K1

L2

J3
K3

L3

F3

C7

E7
D3

G3
B7

T2

L8

J1
L1
J9
L9

K4W2G1646E-BC1A

@

1U_0402_6.3V6K

DIS@

DIS@

C173

1

1

2

2

1U_0402_6.3V6K

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

BA0
BA1
BA2

CK
CK
CKE/CKE0

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET

ZQ/ZQ0

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

96-BALL
SDRAM DDR3

DIS@

C174

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

C176

C175

1

2

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

DIS@

1

2

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1
B9
D1
D8
E2
E8
F9
G1
G9

1U_0402_6.3V6K

DIS@

C178

C177

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

M_DA55
M_DA52
M_DA50
M_DA54
M_DA48
M_DA53
M_DA49
M_DA51

M_DA61
M_DA59
M_DA63
M_DA56
M_DA60
M_DA57
M_DA62
M_DA58

1U_0402_6.3V6K

DIS@

C179

1

1

2

2

DIS@

Compal Electronics, Inc.

Venus XTX(7/8) DDR3 VRAM_A

LA-B131P

1

of

23 52Tuesday, March 04, 2014

+MEM_GFX

+MEM_GFX

DIS@

C180

1

2

C181

1.0

5

M_DB[63..0]22

M_MAB[14..0]22

M_DQMB[7..0]22

M_DQSB[7..0]22

M_DQSB#[7..0]22

D D

C C

M_DB[63..0]

M_MAB[14..0]

M_DQMB[7..0]

M_DQSB[7..0]

M_DQSB#[7..0]

VRAM_ODTB022

M_B_BA022
M_B_BA122
M_B_BA222

M_CLKB022
M_CLKB#022
M_CKEB022

M_CSB0#_02 2
M_RASB#022
M_CASB#022
M_WEB#022

DRAM_RST#22,23

243_0402_1%

VREFC_A12
VREFD_Q12

M_MAB0
M_MAB1
M_MAB2
M_MAB3
M_MAB4
M_MAB5
M_MAB6
M_MAB7
M_MAB8
M_MAB9
M_MAB10
M_MAB11
M_MAB12
M_MAB13
M_MAB14 M_MAB14 M_MAB14 M_MAB14

M_B_BA0
M_B_BA1
M_B_BA2

M_CLKB0
M_CLKB#0
M_CKEB0

VRAM_ODTB0
M_CSB0#_0
M_RASB#0
M_CASB#0
M_WEB#0

M_DQSB2
M_DQSB0

M_DQMB2
M_DQMB0

M_DQSB#2
M_DQSB#0

DRAM_RST#

12

R129

DIS@

U18

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

SDRAM DDR3

K4W2G1646E-BC1A

@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

4

M_DB18

E3

M_DB19

F7

M_DB20

F2

M_DB16

F8

M_DB21

H3

M_DB17

H8

M_DB22

G2

M_DB23

H7

M_DB2

D7

M_DB7

C3

M_DB1

C8

M_DB6

C2

M_DB3

A7

M_DB5

A2

M_DB0

B8

M_DB4

A3

+MEM_GFX

B2
D9
G7
K2
K8
N1
N9
R1
R9

+MEM_GFX

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

R130

243_0402_1%

DIS@

VREFD_Q12
VREFC_A12

M_MAB0
M_MAB1
M_MAB2
M_MAB3
M_MAB4
M_MAB5
M_MAB6
M_MAB7
M_MAB8
M_MAB9
M_MAB10
M_MAB11
M_MAB12
M_MAB13

M_B_BA0
M_B_BA1
M_B_BA2

M_CLKB0
M_CLKB#0
M_CKEB0

VRAM_ODTB0

M_CSB0#_0
M_RASB#0
M_CASB#0
M_WEB#0

M_DQSB3
M_DQSB1

M_DQMB3
M_DQMB1

M_DQSB#3
M_DQSB#1

DRAM_RST#

12

U19

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

SDRAM DDR3

K4W2G1646E-BC1A

@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

3

M_B_BA0
M_B_BA1
M_B_BA2

M_CLKB1
M_CLKB#1
M_CKEB1

U20

M8
H1

N3

P7
P3

N2

P8

P2
R8
R2

T8
R3

L7
R7
N7

T3

T7
M7

M2
N8
M3

J7
K7
K9

K1
L2

J3
K3
L3

F3

C7

E7

D3

G3

B7

T2

L8

J1
L1

J9
L9

K4W2G1646E-BC1A

@

M_DB25

E3

M_DB27

F7

M_DB28

F2

M_DB26

F8

M_DB30

H3

M_DB29

H8

M_DB31

G2

M_DB24

H7

M_DB15

D7

M_DB8

C3

M_DB14

C8

M_DB10

C2

M_DB12

A7

M_DB9

A2

M_DB13

B8

M_DB11

A3

+MEM_GFX

B2
D9
G7
K2
K8
N1
N9
R1
R9

+MEM_GFX

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

VRAM_ODTB122

M_CSB1#_022
M_RASB#122
M_CASB#122
M_WEB#122

M_CLKB122
M_CLKB#122
M_CKEB122

R131

243_0402_1%

DIS@

VREFC_A34
VREFD_Q34

M_MAB0
M_MAB1
M_MAB2
M_MAB3
M_MAB4
M_MAB5
M_MAB6
M_MAB7
M_MAB8
M_MAB9
M_MAB10
M_MAB11
M_MAB12
M_MAB13

VRAM_ODTB1
M_CSB1#_0
M_RASB#1
M_CASB#1
M_WEB#1

M_DQSB4
M_DQSB5

M_DQMB4
M_DQMB5

M_DQSB#4
M_DQSB#5

DRAM_RST# DRAM_RST#

12

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

BA0
BA1
BA2

CK
CK
CKE/CKE0

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET

ZQ/ZQ0

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

96-BALL
SDRAM DDR3

2

U21

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

K4W2G1646E-BC1A

@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

M_DB37

E3

M_DB39

F7

M_DB34

F2

M_DB33

F8

M_DB32

H3

M_DB36

H8

M_DB35

G2

M_DB38

H7

M_DB45

D7

M_DB40

C3

M_DB47

C8

M_DB42

C2

M_DB44

A7

M_DB41

A2

M_DB46

B8

M_DB43

A3

+MEM_GFX

B2
D9
G7
K2
K8
N1
N9
R1
R9

+MEM_GFX

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

R132

243_0402_1%

DIS@

VREFD_Q34
VREFC_A34

M_MAB0
M_MAB1
M_MAB2
M_MAB3
M_MAB4
M_MAB5
M_MAB6
M_MAB7
M_MAB8
M_MAB9
M_MAB10
M_MAB11
M_MAB12
M_MAB13

M_B_BA0
M_B_BA1
M_B_BA2

M_CLKB1
M_CLKB#1
M_CKEB1

VRAM_ODTB1
M_CSB1#_0
M_RASB#1
M_CASB#1
M_WEB#1

M_DQSB6
M_DQSB7

M_DQMB6
M_DQMB7

M_DQSB#6
M_DQSB#7

12

96-BALL
SDRAM DDR3

1

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

M_DB53

E3

M_DB51

F7

M_DB54

F2

M_DB50

F8

M_DB52

H3

M_DB49

H8

M_DB55

G2

M_DB48

H7

M_DB57

D7

M_DB62

C3

M_DB56

C8

M_DB61

C2

M_DB59

A7

M_DB63

A2

M_DB58

B8

M_DB60

A3

+MEM_GFX

B2
D9
G7
K2
K8
N1
N9
R1
R9

+MEM_GFX

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

B B

A A

M_CLKB0

M_CLKB#0

M_CLKB1

M_CLKB#1

ref 139-02 recommand
add off page

Park SCL recommand
pu 60.4 ohm to 1.5VGS

0619 update

VRAM P/N :

Hynix : SA00003YO40 (S IC D3 128M16 H5TQ2G63BFR-11C 96P C38A! )

Samsung : SA000047Q30 (S IC D3 128M16 K4W2G1646C-HC11 96P C38A!)

update VRAM PN

DIS@

1 2

R133 40.2_0402_1%

DIS@

1 2

R137 40.2_0402_1%

DIS@

1 2

R143 40.2_0402_1%

DIS@

1 2

R144 40.2_0402_1%

5

1

C182

0.01U_0402_16V7K

DIS@

2

1

C187

0.01U_0402_16V7K

DIS@

2

+MEM_GFX +MEM_GFX

DIS@

R138

DIS@

R140

12

12

+MEM_GFX

VREFC_A12

0.1U_0402_16V7K

1

C184

2

DIS@

+MEM_GFX

10U_0603_6.3V6M

1

C188

DIS@

2

10U_0603_6.3V6M

1

C190

C189

DIS@

DIS@

2

10U_0603_6.3V6M

1

2

10U_0603_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

10U_0603_6.3V6M

1

1

C192

DIS@

2

10U_0603_6.3V6M

C193

DIS@

2

C191

DIS@

2014/03/03 2015/03/03

1U_0402_6.3V6K

DIS@

DIS@

1

2

C194

1

1

2

2

1U_0402_6.3V6K

Compal Secret Data

Deciphered Date

C195

1U_0402_6.3V6K

12

R134

4.99K_0402_1%

DIS@

R139

4.99K_0402_1%

DIS@

12

VREFD_Q12

0.1U_0402_16V7K

1

C183

2

DIS@

4.99K_0402_1%

4.99K_0402_1%

w w w . c h i n a f i x . c o m

Place across each VDDIO-GND plane seam

4

+MEM_GFX +MEM_GFX

12

R135

DIS@

4.99K_0402_1%

VREFC_A34 VREFD_Q34

12

1U_0402_6.3V6K

DIS@

DIS@

C199

C198

1

1

2

2

1U_0402_6.3V6K

1

C185

2
DIS@

1U_0402_6.3V6K

DIS@

1

2

R141

DIS@

4.99K_0402_1%

1U_0402_6.3V6K

DIS@

DIS@

C197

C196

1

1

2

2

1U_0402_6.3V6K

2

0.1U_0402_16V7K

4.99K_0402_1%

1U_0402_6.3V6K

DIS@

C200

C201

1

1

2

2

1U_0402_6.3V6K

12

R136

DIS@

4.99K_0402_1%

0.1U_0402_16V7K

12

R142

DIS@

DIS@

DIS@

C202

1

2

Custom

Date: Sheet

1

C186

2
DIS@

+MEM_GFX

C203

1U_0402_6.3V6K

Title

Size Document Number Rev

DIS@

1U_0402_6.3V6K

DIS@

C204

C205

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

C207

C206

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

DIS@

C209

C208

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@

C210

1

2

1U_0402_6.3V6K

Compal Electronics, Inc.

Venus XTX(8/8) DDR3 VRAM_B

LA-B131P

1

24 52Tuesday, March 04, 2014

1U_0402_6.3V6K

DIS@

C211

1

1

2

2

of

DIS@

DIS@

C212

C213

1

2

1.0

5

4

3

2

1

LCD POWER CIRCUIT

+LCDVDD

C215

4.7U_0603_6.3V6K

1

C1153

@

10U_0603_6.3V6M

2

R146

C220

4

+LCDVDD

1 2

1

@EMI@

2

1

C216

0.1U_0402_16V7K

2

DMIC_CLK

DMIC_DATA

12

CA12

220P_0402_50V7K

@EMI@

CA12 close to JE DP1

ENBKL

1 8

DISPOFF#

2 7

PCH_ENVDD

3 6

EDP_HPD

4 5

RP10 100K_8P4R_5%

From PCH

From EC

eDP(FHD) + TOUCH + Camera

JEDP1

+3VS

+LCDVDD

TS_DISABLE#30

SDV

PCH_GPIO879

DMIC_CLK27
DMIC_DATA27

+3VS

C223 0.1U_0402_16V7K

EDP_AUXP4
EDP_AUXN4

EDP_TXN04
EDP_TXP04

EDP_TXN14
EDP_TXP14

EDP_HPD8

INVPWM8

JP5

@

JUMP_43X39

5

P

Y

G

3

0_0402_5%

112

SVT

2

4

B+

SIT

+3VS

@

U33

2

B

1

A

1 2

R213

SIT

2014/03/03 2015/03/03

1 2

C224 0.1U_0402_16V7K

1 2

C218 0.1U_0402_16V7K

1 2

C219 0.1U_0402_16V7K

1 2

C221 0.1U_0402_16V7K

1 2

C222 0.1U_0402_16V7K

1 2

1 2

0_0805_5%

SVT

DISPOFF#

Compal Secret Data

Deciphered Date

R2

0.1U_0402_25V6K

2

W=80mils

@

USB20_N4_L
USB20_P4_L

USB20_N5_L
USB20_P5_L

EDP_CONN_AUXP
EDP_CONN_AUXN

EDP_CONN_TXN0
EDP_CONN_TXP0

EDP_CONN_TXN1
EDP_CONN_TXP1

DISPOFF#

INVPWR_B+

2

2

C225

1

1

1090mA

@

0.1U_0402_25V6K

C226

Touch Screen

Camera
DMIC

SIV

ENBKL8,30

BKOFF#30

eDP(FHD)

SIT

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+3VS_CMOS

MC74VHC1G08DFT2G_SC70-5

Issued Date

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

35

35

36
37
38
39
40

Title

eDP LCD / Camera / Touch

Size Document Number Rev

Custom

Date: Sheet

41

36

G1

42

37

G2

43

38

G3

44

39

G4

45

40

G5

ACES_50398-04041-001

CONN@

Compal Electronics, Inc.

LA-B131P

1

of

25 52Tuesday, March 04, 2014

1.0

+3VS

D D

0.1U_0402_16V7K

SIV

1

C214

@

2

0_0402_5%

1500P_0402_50V7K

W=80mils

R145

@

1 2

C217

+3VS_SS

C217 Resevre for APL3512A

2A

1

2

U22

5

IN

4

SS

APL3512ABI-TRG_SOT23-5

PCH_ENVDD8

OUT

GND

1

2

3

EN

W=80mils

2

A

1

2

R145 Resevre for G5243AT11U

@EMI@

R258 0_0402_5%

USB20_N410

USB20_P410

R255 0_0402_5%

C C

R254 0_0402_5%

USB20_N510

USB20_P510

R244 0_0402_5%

SVT

CMOS Camera

B B

CMOS_ON#30

A A

+3VS

R1458 150K_0402_5%

R148 0_0603_5%

1 2

Q70
ME2301DC-G_SOT23-3

S

G

2

1

C1155

0.1U_0402_16V7K

2

USB20_N4

2

3

D3

@ESD@

1

L30ESDL5V0C3-2 C/A SOT-23

5

12

L24

@EMI@

2

2

3

3

DLW21HN900HQ2L_4P

12

@EMI@

@EMI@

12

L23

EMI@

2

2

3

3

DLW21HN900HQ2L_4P

12

@EMI@

@

D

13

1

1

4

4

1

4

1

C1152

0.1U_0402_16V7K

2

SIT

1

4

W=20milsW=20mils

R1456 0_0603_5%

1 2

USB20_P5_LUSB20_P4

USB20_N5_L

2

3

D4

@ESD@
1

L30ESDL5V0C3-2 C/A SOT-23

USB20_N4_L

USB20_P4_L

USB20_N5_L

USB20_P5_L

+3VS_CMOS

SVT

33_0402_5% @EMI@

w w w . c h i n a f i x . c o m

22P_0402_50V8J

1

+3_LAN Rising time (10%~90%) >1mS and <100mS

+3VALW

W=60mils

A A

J2

112

JUMP_43X39

@

2

+3V_LAN

370mA

GCLK (RG6 close to Y3.1)

0_0402_5%

XTLO

XTLI

SVT

XTLI

2

GND

4

GND

1 2

RG6

1

Y3

1

25MHZ_12PF_7V25000012

NOGCLK@

3

3

LAN_XTLI_GCLK34

C239
15P_0402_50V8J

1 2

NOGCLK@

B B

C242
15P_0402_50V8J

1 2

NOGCLK@

2

RTL8111GS L7

SWR mode

C230

C298

C232

C237

O O X O

+3V_LAN

SWR@

12

C298

4.7U_0603_6.3V6K

These caps close to U23 : Pin 23

LANCLK_REQ#7,9
PCIE_PTX_C_DRX_P310
PCIE_PTX_C_DRX_N310
CLK_PCIE_LAN7
CLK_PCIE_LAN#7

R147 C229

X

2

C237

SWR@

0.1U_0402_16V7K

1

MDI0+
MDI0­+LAN_VDD10
MDI1+
MDI1­MDI2+
MDI2­+LAN_VDD10
MDI3+
MDI3­+3V_LAN

3

C230

RTL8111G L7

C232

C298
C237

LDO mode

LDO@

R147 0_0603_5%

1 2

+LAN_REGOUT

W=60mils

0.1U_0402_16V7K

1

LDO@

C229

2

( Should be place within 200 mils )
These components close to U23 : Pin 24

1 2

2.2UH +-5% NLC252018T-2R2J-N

LDO mode SWR mode

U23

1

MDIP0

2

MDIN0

3

AVDD10

4

MDIP1

5

MDIN1

6

MDIP2

7

MDIN2

8

AVDD10

9

MDIP3

10

MDIN3

11

AVDD33

12

CLKREQB

13

HSIP

14

HSIN

15

REFCLK_P

16

REFCLK_N

R147 C229

O O X X X

L7

SWR@

SWR@

C230

4.7U_0603_6.3V6K

HSOP

HSON

PERSTB

ISOLATEB

LANWAKEB

DVDD10
VDDREG
REGOUT

LED2

LED1/GPIO

LED0
CKXTAL1
CKXTAL2

AVDD10

RSET

AVDD33

GND

4

Layout Notice : Place as close
chip as possible.

+LAN_VDD10

W=60mils

1

12

SWR@

C232

2

C231

@

0.1U_0402_16V7K

1 2

C234

1U_0402_6.3V6K

C233

0.1U_0402_16V7K

1

1

@

2

2

C236

0.1U_0402_16V7K

C235

0.1U_0402_16V7K

0.1U_0402_16V7K

1

1

2

2

+3V_LAN

@

@

C322

4.7U_0603_6.3V6K

12

C238

C227

4.7U_0603_6.3V6K

C228

0.1U_0402_16V7K

0.1U_0402_16V7K

1

12

12

2

close to pin 22

These components close to U23 : Pin 3,8,22,30
1uF reserved on Pin 22

T89

T90

These caps close to U11

C240 0.1U_0402_16V7K

1 2

C241 0.1U_0402_16V7K

1 2

LED1_GPIO

R152

1 2

2.49K_0402_1%

PCIE_PRX_DTX_N3

@

1 2

RL17 10K_0402_5%

reserved GPIO pin

PCIE_PRX_C_DTX_P3 PCIE_PRX_DTX_P3

17

PCIE_PRX_C_DTX_N3

18
19

ISOLATEB ISOLATEB

20
21

+LAN_VDD10

22

+3V_LAN

23

+LAN_REGOUT

24
25

1
26
27

1

XTLO

28

XTLI

29

+LAN_VDD10

30

LAN_RSET

31

+3V_LAN

32
33

These caps close to U23 : Pin 11,32
DVDD33

PCIE_PRX_DTX_P3 10
PCIE_PRX_DTX_N3 10
PLT_RST# 8,17,29,30,33

+3V_LAN

PCIE_LAN_WAKE# 29,30

5

+3VS

1 2

12

R149

1K_0402_5%

R153
15K_0402_5%

RTL8111GUL-CG QFN 32P

SA00006ML10

D5

C C

MDI0+

MDI0-

C292

1 2

0.01U_0402_16V7K

D D

MDI1+

MDI1-

MDI2+

MDI2-

MDI3+

MDI3-

TS1

1

TCT1

2

TD1+

3

TD1-

4

TCT2

5

TD2

6

TD2-

7

TCT3

8

TD3+

9

TD3-

10

TCT4

11

TD4+

TD4-12MX4-

NS892407 1G

SP050006800

MCT1

MX1+

MX1-

MCT2

MX2+

MX2-

MCT3

MX3+

MX3-

MCT4

MX4+

24

MDO0+

23

MDO0-

22

21

MDO1+

20

MDO1-

19

18

MDO2+

17

MDO2-

16

15

MDO3+

14

MDO3-

13

SIV

MCTTCT

R168

1 2

75_0805_5%

EMI@

1 2

C290

10P_0603_50V8-J

12

DL2
BS4200N-C-LV_SMB-F2

EMI@ S

CV00001D00

CHASSIS1_GND

MDI1-

MDI1+

Place Close to TS1

MDI0-

MDI0+

Place Close to TS1

SIV (EMI suggest ion)

EMI@

1

10

1

10

2

9

2

9

3

8

3

8

4

7

4

7

6

556

GND

RCLAMP3304N.TCT_SLP2626P10-10

11

D6

EMI@

1

10

1

10

2

9

2

9

3

8

3

8

4

7

4

7

6

556

GND

RCLAMP3304N.TCT_SLP2626P10-10

11

MDI3+

MDI3-

MDI2+

MDI2-

MDO0+

MDO1+

MDO2+

MDO3+

MDO0-

MDO2-

MDO1-

MDO3-

JRJ1

1

PR1+

2

PR1-

3

PR2+

4

PR3+

5

PR3-

6

PR2-

7

PR4+

8

PR4-

SANTA_130460-3

DC231112261

CONN@

GND

GND

GND

GND

12

11

10

9

CHASSIS1_GND

w w w . c h i n a f i x . c o m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2014/03/03 2015/03/03

Compal Secret Data

Deciphered Date

4

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

LAN_RTL8111G-CG

LA-B131P

5

26 52Tuesday, March 04, 2014

of

1.0

5

4

3

2

1

R159 0_0402_5%

+1.5VS

R157

1 2

0_0805_5%

SVT

1U_0402_6.3V6K

C344

1

0.01U_0402_16V7K

@

2

2

C248

1

+3VS

D D

600ohms @100MHz 2A
P/N: SM01000EE00

+5VS

C C

wide 40MIL

EXT_MIC_RING233

SIV (EMI suggest ion)

DMIC_DATA25
DMIC_CLK25

12

12

C254

CA13

EMI@

@EMI@

220P_0402_50V7K

220P_0402_50V7K

SIV (EMI suggest ion)

RA13, CA13 close to UA1

B B

RA7 pop on ALC283, NC on ALC23 3

EXT_MIC_SLEEVE33

RA13 0_0402_5%

1 2
1 2

L8 SB Y100505T-301Y-NEMI@

EC_MUTE#30

HDA_RST_AUDIO#6

JACK_SENSE#

RA4 close to chip

+3VS

+3VLP

EMI@

SIT

RA4 39.2K_0402_1%

1 2

U1

@

1

VIN

VOUT

3

SHDN

4

BP

1

C343

2

@

GND

APE8800A-15Y5P_SOT23-5

Place near Pin25

1

1

C249

C250

2

2

0.1U_0402_16V7K

4.7U_0603_6.3V6K

RA2 0_0402_5%

CA2 2.2U_0402_6.3V6M

CA6 4.7U_0603_6.3V6K

R163 100K_0402_5%

0.1U_0402_16V7K

EXT_MIC_RING2
EXT_MIC_SLEEVE

DMIC_DATA_R
DMIC_CLK_R

1 2

HDA_RST_AUDIO# HDA_SDIN0_R

PC_BEEP

1 2

12

1 2

@

CA8 4.7U_0603_6.3V6K

12

SVT

RA7 0_0402_5%

1 2

5

2

+3VDD_CODEC

PDB

33_0603_5%

12

R249

R250

+5VS_PVDD

+IOVDD_CODEC

UA1

22

LINE1-L(PORT-C-L)

21

LINE1-R(PORT-C-R)

24

LINE2-L(PORT-E-L)

23

LINE2-R(PORT-E-R)

17

MIC2-L(PORT-F-L) /RING2

18

MIC2-R(PORT-F-R) /SLEEVE

31

LINE1-VREFO-L

30

LINE1-VREFO-R

2

GPIO0/DMIC-DATA

3

GPIO1/DMIC-CLK

47

PDB

11

RESETB

12

PCBEEP

13

SENSE A

14

SENSE B

37

CBP

35

CBN

36

CPVDD

20

CPVREF

19

MIC-CAP

4

DVSS

49

Thermal PAD

ALC283-CG_MQFN48_6X6

1U_0603_10V6K

33_0603_5%

12

C253

1

2

1

9

41

DVDD

PVDD1

DVDD-IO

ALC283-CG

SVT

26

46

AVDD1

PVDD2

+3VS+1.5VS_AVDD2

R155 0_0603_5%

1 2

SVT

Place near Pin1 Place near Pin9

1

12

C245

C246

2

1U_0402_6.3V6K

0.1U_0402_16V7K

+5VDDA_CODEC

Place near Pin26

+1.5VS_AVDD2

40

AVDD2

SPK-OUT-L-

SPK-OUT-L+

SPK-OUT-R+

SPK-OUT-R-

HPOUT-L(PORT-I-L)

HPOUT-R(PORT-I-R)

SYNC

BCLK

SDATA-OUT

SDATA-IN

SPDIF-OUT/GPIO2

MONO-OUT

MIC2-VREFO

LDO3-CAP
LDO2-CAP
LDO1-CAP

VREF

JDREF

CPVEE

AVSS1
AVSS2

SVT

Place near Pin40

43
42

45
44

32
33

HDA_SYNC_AUDIO

10

HDA_BITCLK_AUDIO

6

HDA_SDOUT_AUDIO

5
8

48

16

29

LDO3

7

LDO2

39
27

LDO1

28

JDREF

15

CPVEE

34

25
38

1

C251

2

0.1U_0402_16V7K

SPK_L­SPK_L+

SPK_R+
SPK_R-

HP_OUTL
HP_OUTR

RA3 33_0402_5%

RA12

EMI@

CHILISIN SBY100505T-301Y-N 0402

SIT (EMI suggest ion)

CA3 4.7U_0603_6.3V6K

12

CA4 4.7U_0603_6.3V6K

12

CA5 4.7U_0603_6.3V6K

12

RA5

1 2

CA7 1U_0402_6.3V6K

1 2

1 2

RA6

close to chip

1

CA9

2.2U_0402_6.3V6M

2

1

C247

@

2

1

C252

2

4.7U_0603_6.3V6K

1 2

1 2

100K_0402_5%

20K_0402_1%

0.1U_0402_16V7K

R158 0_0603_5%

1 2

HP_OUTL 33
HP_OUTR 33

HDA_SYNC_AUDIO 6
HDA_BITCLK_AUDIO 6

R156 0_0603_5%

1 2

SVT

SPK_R+
SPK_R­SPK_L+
SPK_L-

+3VDD_CODEC+3VDD_CODEC +IOVDD_CODEC

SIV

+5VS

HDA_SDOUT_AUDIO 6

HDA_SDIN0 6

SPDIF_OUT 33

MIC2-VREFO 33

wide 40MIL

R164 0_0603_5%

1 2

R165 0_0603_5%

1 2

R166 0_0603_5%

1 2

R167 0_0603_5%

1 2

SIT (EMI suggest ion)

PLUG_IN#33

SIT (EMI suggest ion)

R196 0_0402_5%

1 2

R197 0_0402_5%

1 2

R198 0_0402_5%

1 2

R173 0_0402_5%

1 2

GNDAGND

A A

@EMI@

1 2

R171 27_0402_5%

1

@EMI@

C263

2

33P_0402_50V8J

EMI

HDA_BITCLK_AUDIO

PC Beep

EC Beep

PCH Beep

BEEP#30

HDA_SPKR9

1 2

C260 0.1U_0402_16V7K

PC_BEEP1 PC_BEEP

1 2

C262 0.1U_0402_16V7K

1 2

1K_0402_5%

12

@

R174
10K_0402_5%

R172

C261

1 2

0.1U_0402_16V7K

JACK_PLUG Delay circutis

+3VS +3VS

12

@

RA11
100K_0402_5%

@

PLUG_IN#

DMN66D0LDW-7_SOT363-6

10U_0603_6.3V6M

PLUG_IN#

QA5B

1 2

@

RA8
10K_0402_5%

1

@

CA11

2

RA10 0_0402_5%

1 2

1

2

Reserve for cancel Delay circutis

HDA_RST_AUDIO#

SPK_R+_CONN
SPK_R-_CONN
SPK_L+_CONN
SPK_L-_CONN

3

EMI@

SPK_R+_CONN

SPK_R-_CONN

2

@EMI@

D8

PACDN042Y3R_SOT23-3

1

1

1

C257

C256

2

2

EMI@

1000P_0402_50V7K

Reserve for ESD request.

1000P_0402_50V7K

C258

EMI@

1 2

R162
10K_0402_5%

1

2

EMI@

1000P_0402_50V7K

SPK_L-_CONN

SPK_L+_CONN

2

3

PACDN042Y3R_SOT23-3

1

12

RA9
100K_0402_5%

61

D

G

2

S

@

CA10
10U_0603_6.3V6M

SIT

R161

100K_0402_5%

1U_0402_6.3V6K

1

C259

2

1000P_0402_50V7K

@EMI@

D7

@

+3VS

@

C255

JACK_SENSE#

12

5

1

@

2

1
2
3
4

5
6

34

D

G

QA5A

5

S

DMN66D0LDW-7_SOT363-6

+3VLP

V0.2

100K_0402_5%

12

R160

2

34

Q4B

ME2N7002D1KW-G 2N SOT363-6

JSPK1

1
2
3
4

G1
G2

ACES_50281-0040N-001

CONN@

JACK_SENSE#

@

EXT_MIC_SLEEVE

61

GNDA

ME2N7002D1KW-G 2N SOT363-6

Q4A

w w w . c h i n a f i x . c o m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2014/03/03 2015/03/03

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

ALC283 CODEC

LA-B131P

1

of

27 52Tuesday, March 04, 2014

1.0

5

4

3

2

1

+5VS

UH1

1

D D

R175

1M_0402_5%

DDI2_HDMI_HPD8,9

+5VS_HDMI

+3VS

C C

DDI2_CTRL_CK8

DDI2_CTRL_DATA8

B B

A A

5

4

Q6B

ME2N7002D1KW-G 2N SOT363-6

HDMI_CLK+_CK

HDMI_CLK-_CK

HDMI_TX0+_CK

HDMI_TX0-_CK HDMI_TX0-_CONN

HDMI_TX1+_CK

HDMI_TX1-_CK

HDMI_TX2+_CK

HDMI_TX2-_CK

5

RHP1

2.2K_0804_8P4R_5%

1 8
2 7
3 6
4 5

Q6A

2

ME2N7002D1KW-G 2N SOT363-6

HDMICLK_R

61

3

HDMIDAT_R

L9

3

3

2

2

DLW21HN900HQ2L_4P

L10

3

3

2

2

DLW21HN900HQ2L_4P

L11

3

3

2

2

DLW21HN900HQ2L_4P

L12

3

3

2

2

DLW21HN900HQ2L_4P

HDMICLK_R
HDMIDAT_R
DDI2_CTRL_CK
DDI2_CTRL_DATA

EMI@

EMI@

EMI@

EMI@

+3VS

2

1 2

4

1

4

1

4

1

4

1

Q5A

ME2N7002D1KW-G 2N SOT363-6

4

1

C323

2.2PU_50V C NPO 0402

1

@EMI@

2

4

1

C327

2.2PU_50V C NPO 0402

1

@EMI@

2

4

1

C329

2.2PU_50V C NPO 0402

1

@EMI@

2

4

1

C331

2.2PU_50V C NPO 0402

1

@EMI@

2

1

EMI@

C265
1000P_0402_50V7K

2

61

SVT

R176
100K_0402_5%

HDMI_CLK+_CONN

HDMI_CLK-_CONN

C326

2.2PU_50V C NPO 0402

1

@EMI@

2

C323,C326 close to L9

HDMI_TX0+_CONN

C328

2.2PU_50V C NPO 0402

1

@EMI@

2

C327,C328 close to L10

HDMI_TX1+_CONN

HDMI_TX1-_CONN

C330

2.2PU_50V C NPO 0402

1

@EMI@

2

C329,C330 close to L11

HDMI_TX2+_CONN

HDMI_TX2-_CONN

w w w . c h i n a f i x . c o m

C332

2.2PU_50V C NPO 0402

1

C331,C332 close to L12

@EMI@

2

SVT (EMI suggestion)

4

12

HDMI_CLK-_CK4

HDMI_CLK+_CK4
HDMI_TX0-_CK4

HDMI_TX0+_CK4
HDMI_TX1-_CK4

HDMI_TX1+_CK4
HDMI_TX2-_CK4

HDMI_TX2+_CK4

HDMI_TX2+_CONN

HDMI_TX2-_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_CLK+_CONN

HDMI_CLK-_CONN

+5VS_HDMI

+5VALW

HDMI_DET

ESD

HDMI_CLK-_CK

HDMI_CLK+_CK
HDMI_TX0-_CK

HDMI_TX0+_CK
HDMI_TX1-_CK

HDMI_TX1+_CK
HDMI_TX2-_CK

HDMI_TX2+_CK

Close to HDMI connector

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

R177 0_0402_5%@

1 2

R178 0_0402_5%@

1 2

R179 0_0402_5%@

1 2

R180 0_0402_5%@

1 2

R181 0_0402_5%@

1 2

R182 0_0402_5%@

1 2

R183 0_0402_5%@

1 2

R184 0_0402_5%@

1 2

D9

@ESD@

1

2

4

5

3

TVWDF1004AD0_DFN 9

D10

@ESD@

1

2

4

5

3

TVWDF1004AD0_DFN 9

D11

6

I/O4

5

VDD

4

I/O3

YSUSB2.0-5_SOT23-6

Main: SC300001400
2nd: SC300001G00

@ESD@

I/O2

GND

I/O1

HDMI_TX2+_CONN

9

HDMI_TX2-_CONN

8

HDMI_TX0+_CONN

7

HDMI_TX0-_CONN

6

HDMI_TX1+_CONN

9

HDMI_TX1-_CONN

8

HDMI_CLK+_CONN

7

HDMI_CLK-_CONN

6

3

2

1

2014/03/03 2015/03/03

IN

AP2330W-7_SC59-3

HDMI_CLK-_CONN

HDMI_CLK+_CONN
HDMI_TX0-_CONN

HDMI_TX0+_CONN
HDMI_TX1-_CONN

HDMI_TX1+_CONN
HDMI_TX2-_CONN

HDMI_TX2+_CONN

Main: SC300002800
2nd: SC300001Y00

HDMICLK_R

HDMIDAT_R

Compal Secret Data

Deciphered Date

OUT

GND

HDMI_DET

+5VS_HDMI

HDMIDAT_R
HDMICLK_R

3

1

2

C264

0.1U_0402_16V7K

2

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

SINGA_2HE1638-012212F_19P-T

CONN@

SD309470080
S ROW RES 1/16W 470 +-5% 8P4R 0804

HDMI_CLK-_CONN
HDMI_CLK+_CONN
HDMI_TX1-_CONN
HDMI_TX1+_CONN

HDMI_TX0-_CONN
HDMI_TX0+_CONN
HDMI_TX2-_CONN
HDMI_TX2+_CONN

2

+5VS_HDMI

20

GND

21

GND

22

GND

23

GND

SIV

470 +-5% 8P4R

45
36
27
18

RP21

470 +-5% 8P4R

45
36
27
18

RP22

SVT

Title

Size Document Number Rev

Custom

Date: Sheet

3

+3VS

Q5B

5

ME2N7002D1KW-G 2N SOT363-6

4

Compal Electronics, Inc.

HDMI_CONN

LA-B131P

1

SVT

1.0

of

28 52Tuesday, March 04, 2014

A

B

C

D

E

F

G

H

SATA HDD (SSD) CONN.

+3VS

U25

SATA_PTX_DRX_P06
SATA_PTX_DRX_N06

SATA_PRX_DTX_P06

1 1

SATA_PRX_DTX_N06

SATA_PTX_DRX_P0

SATA_PTX_DRX_N0 SATA_PTX_DRX_N0_R

SATA_PRX_DTX_P0

1 2
1 2

1 2
1 2

+3VS

SATA_PTX_DRX_P0_R

C2670.01U_0402_16V7K
C2660.01U_0402_16V7K

SATA_PRX_DTX_P0_R

C2700.01U_0402_16V7K

SATA_PRX_DTX_N0_RSATA_PRX_DTX_N0

C2720.01U_0402_16V7K

SATA1_A_PRE1
SATA1_B_PRE1

SATA1_TEST

Add EQ pin

U25

TI@

SN75LVCP601RTJR_TQFN20_4X4

SIT

SATA1_B_PRE1

SATA1_A_PRE1

SATA1_A_PRE0

2 2

SATA1_B_PRE0

DEW1_TI

DEW2_TI

R186 0_0402_5%TI@

1 2

R189 0_0402_5%@

1 2

R190 0_0402_5%@

1 2

R192 0_0402_5%@

1 2

R194 0_0402_5%@

1 2

R201 0_0402_5%@

1 2

R204 0_0402_5%@

1 2

U25

Parade@

PS8520CTQFN20GTR2-A_TQFN20_4X4

SATA1_TESTSATA1_TEST

SATA1_B_PRE1

SATA1_A_PRE1

SATA1_A_PRE0

SATA1_B_PRE0

DEW1_TI

DEW2_TI

R187 0_0402_5%@

1 2

R188 4.7K_0402_5%@

1 2

R191 4.7K_0402_5%@

1 2

R193 4.7K_0402_5%TI@

1 2

R195 4.7K_0402_5%@

1 2

R214 4.7K_0402_5%@

1 2

R272 4.7K_0402_5%@

1 2

+3VS

SIT

SIT

@

7

EN

1

A_INp

2

A_INn

5

B_OUTp

4

B_OUTn

19

A_PRE1

17

B_PRE1

18

TEST

3

GND

13

GND

21

EPAD

PS8520CTQFN20GTR2-A_TQFN20_4X4

+3VS

VDD
VDD

A_PRE0
B_PRE0

A_OUTp
A_OUTn

B_INp
B_INn

Place caps.
near U25

12

10
20

6

NC

16

NC

9
8

15
14

11
12

C275

1U_0402_6.3V6K

SATA1_A_PRE0
SATA1_B_PRE0

SATA_PTX_C_DRX_P0_R
SATA_PTX_C_DRX_N0_R

SATA_PRX_C_DTX_P0_R
SATA_PRX_C_DTX_N0_R

0.01U_0402_16V7K

C276

0.1U_0402_16V7K

1

1

2

2

C277

DEW2_TI
DEW1_TI

JHDD1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND

12

GND

ACES_50208-01001-001

CONN@

+5VS_HDD

SATA_PTX_C_DRX_P0_CSATA_PTX_C_DRX_P0_R
SATA_PTX_C_DRX_N0_C

SATA_PRX_C_DTX_N0_CSATA_PRX_C_DTX_N0_R
SATA_PRX_C_DTX_P0_C

1

C281
10U_0603_6.3V6M

2

C268 0.01U_0402_16V7K

SIT

+5VS_HDD

1

EMI@

C278
1000P_0402_50V7K

2

SATA_PTX_C_DRX_N0_R

SATA_PRX_C_DTX_P0_R

R185 0_0805_5%

+5VS

1

C279

0.1U_0402_16V7K

2

1 2

C269 0.01U_0402_16V7K

1 2

C271 0.01U_0402_16V7K

1 2

C273 0.01U_0402_16V7K

1 2

1 2

12

@

C280
1U_0402_6.3V6K

SVT

NGFF for WLAN+BT

+3VS +3VS_WLAN

JP3

@

2

112

JUMP_43X39

For Power consumption
Measurement

1

C282

4.7U_0603_6.3V6K

2

1

C283

0.1U_0402_16V7K

2

3.3VAUX

3.3VAUX
LED1#

PCM_IN

LED2#

GND

COEX3
COEX2
COEX1

SUSCLK

I2C_CLK

ALERT

3.3VAUX

3.3VAUX

MTG76

2
4
6
8
10
12
14
16
18
20
22

24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66

68

+3VS_WLAN

R218 0_0402_5%

1 2

R257 0_0402_5%

R169

1 2

100K_0402_5%

SUSCLK_R

BT_DISABLE_R

D

1 2

R222 0_0402_5%

1 2

R199 0_0402_5%

1 2

R226 0_0402_5%

1 2

Note: The real behavior of BT_DISABLE are
BT_DISABLE=LOW, BT=OFF
BT_DISABLE=HIGH, BT=ON

SIV

EC_TX 30
EC_RX 30

SUSCLK 8
PLT_RST# 8,17,26,30,33

WLBT_OFF# 8,9

EC_WL_OFF# 30

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

E

2014/03/03 2015/03/03

Compal Secret Data

Deciphered Date

F

Title

Size Document Number Rev

Custom

Date: Sheet

G

Compal Electronics, Inc.

HDD/NGFF(WLAN+BT)

LA-B131P

of

29 52Tuesday, March 04, 2014

H

1.0

3 3

BT

WLAN

4 4

USB20_P610

USB20_N610

PCIE_PTX_C_DRX_P410
PCIE_PTX_C_DRX_N410

PCIE_PRX_DTX_P410
PCIE_PRX_DTX_N410

CLK_PCIE_WLAN7

CLK_PCIE_WLAN#7

WLANCLK_REQ#7,9

PCH_PCIE_WAKE#8,9

PCIE_LAN_WAKE#26,30

A

SIV

R217 0_0402_5%

1 2

R216 0_0402_5%@

1 2

R275 0_0402_5%@

1 2

SIT

B

WLANCLK_REQ#_R
WAKE#_R

JWLAN1

1

GND

3

USB_D+

5

USB_D-

7

GND

9

SIDO_CLK

11

SDIO_CMD

13

SDO_DAT0

15

SDO_DAT1

17

SDO_DAT2

19

SDO_DAT3

21

SDIO_WAKE#

23

SDIO_RESET#

25

GND

27

PETP0

29

PETN0

31

GND

33

PERP0

35

PERN0

37

GND

39

REFCLKP0

41

REFCLKN0

43

GND

45

CLKEQ0#

47

PEWAKE0#

49

GND

51

RSRVD/PETP1

53

RSRVD/PETN1

55

GND

57

RSRVD/PERP1

59

RSRVD/PERN1

61

GND

63

RESERVED

65

RESERVED

67

GND

w w w . c h i n a f i x . c o m

69

MTG77

LCN_DAN05-67306-0102

CONN@

SP070013F00

C

PCM_CLK

PCM_SYNC

PCM_OUT

UART_WAKE#

UART_RX

UART_TX
UART_CTS
UART_RTS
RESERVED
RESERVED
RESERVED

PERST0#
W_DISABLE2#
W_DISABLE1#

I2C_DATA

RESERVED
RESERVED
RESERVED
RESERVED

+3VALW_EC

+3VALW_EC

SIV

L13

BLM15BD601SN1D_2P_0402

1 2

0.1U_0402_16V7K

1 2

BLM15BD601SN1D_2P_0402

L14

EMI

C243 22P_0402_50V8J

1 2

R269 47K_0402_5%

0.1U_0402_16V7K

KSO[0..15]31

KSI[0..7]31

+3VALW_EC

1 2

1 2

+3VALW

1 2

R261 10K_0402_5%

1

C288

2

ECAGND

@EMI@

R29 10_0402_1%

12

C337

KSO[0..15]

KSI[0..7]

R263

2.2K_0402_5%

R264

2.2K_0402_5%

PCH_PWROK8

Share ROM

PCIE_LAN_WAKE#

SIT

1

2

ECAGND

@EMI@

2

1

EC_SMB_CK1

EC_SMB_DA1

DS3

SUSWARN#8

SLP_SUS#8

R207

1 2

10K_0402_5%

+EC_VCCA

C289

EMI@

1000P_0402_50V7K

12

PLT_RST#8,17,26,29,33

ECAGND 37

12

ESD

+3VLP

C284

0.1U_0402_16V7K

1

2

USB_CHG_CTL332

LPC_FRAME#7

CK_LPC_KBC7

EC_SCI#9

ADP_ID_CLOSE36

ESD@

C295
22P_0402_50V8J

EC_SMB_CK137,38
EC_SMB_DA137,38
EC_SMB_CK27,31
EC_SMB_DA27,31

PM_SLP_S3#8

USB_CHG_CTL132

3V/5VALW_PG39

USB_CHG_EN32
AC_PRESENT8

EC_FAN_PWM233

FAN_SPEED133
FAN_SPEED233

TP_LOCK_LED#33

PBTN_OUT#8

PCIE_LAN_WAKE#26,29

PM_SLP_S4#8

PM_SLP_S5#8

KB_RST#9

LPC_AD37
LPC_AD27
LPC_AD17
LPC_AD07

SERIRQ9

EC_TX29
EC_RX29

NOVO#33

+3VALW

C285

0.1U_0402_16V7K

1

2

9

22

33

EC_VDD/VCC

EC_VDD/VCC

PWM Output

DA Output

PS2 Interface

SPI Device Interface

SM Bus

GPIO

GND/GND

11

24

SIT

PM_SLP_S4#_R

SIT

1

C291

EMI@

100P_0402_50V8J

2

+EC_VCCA

111

96

125

67

EC_VDD0

EC_VDD/VCC

EC_VDD/VCC

EC_VDD/VCC

EC_VDD/AVCC

BATT_TEMP/GPIO38

AD Input

CPU1.5V_S3_GATE/GPXIOA00

WOL_EN/GPXIOA01
HDA_SDO/GPXIOA02
VCIN0_PH/GPXIOD00

SPI Flash ROM

PECI_KB930/GPIO41

BATT_CHG_LED#/GPIO52

CAPS_LED#/GPIO53

GPIO

BATT_LOW_LED#/GPIO55

PM_SLP_S4#/GPIO59

EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05

H_PROCHOT#_EC/GPXIOA06

VCOUT0_PH/GPXIOA07

GPO

PBTN_OUT#/GPXIOA09

PCH_APWROK/GPXIOA10

SA_PGOOD/GPXIOA11

GPI

LID_SW#/GPXIOD04

PECI_KB9012/GPXIOD07

GND/GND

GND/GND

AGND/AGND

GND/GND

GND0

35

69

94

113

ECAGND

GPIO0F

BEEP#/GPIO10

GPIO12

ACOFF/GPIO13

GPIO39

ADP_I/GPIO3A

GPIO3B
GPIO42

IMON/GPIO43

DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D

IREF/GPIO3E

CHGVADJ/GPIO3F

EC_MUTE#/GPIO4A

USB_EN#/GPIO4B

CAP_INT#/GPIO4C

EAPD/GPIO4D

TP_CLK/GPIO4E

TP_DATA/GPIO4F

SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58

SPICS#/GPIO5A

ENBKL/GPIO40

FSTCHG/GPIO50

PWR_LED#/GPIO54

SYSON/GPIO56
VR_ON/GPIO57

BKOFF#/GPXIOA08

AC_IN/GPXIOD01

EC_ON/GPXIOD02

ON/OFF/GPXIOD03

SUSP#/GPXIOD05

GPXIOD06

V18R

U26

21
23
26
27

63
64
65
66
75
76

68
70
71
72

83
84
85
86
87
88

97
98
99
109

119
120
126
128

73
74
89
90
91
92
93
95
121
127

100
101
102
103
104
105
106
107
108

110
112
114
115
116
117
118

124

VR_TT#_R

TP_CLK
TP_DATA

AC_BATT_R

PM_SLP_S4#_REC_SMB_DA2

SVT

NUVOTON_VTT
PECI

+V18R

1

2

4.7U_0603_6.3V6K

+5VALW

KB9012/Nuvoton : +V18R
KB9022 : +3VALW_EC

+3VS

VCCST_PWRGD 11
BEEP# 27
EC_FAN_PWM1 33
AC_OFF 38

VCIN1_BATT_TEMP 37

VCIN1_BATT_DROP 37
ADP_I 37,38

ADP_ID 36

ENBKL 8,25

GPU_PWR_EN 19,45

DGPU_PWR_EN 8,9,19,41,42

EC_WL_OFF# 29

EC_MUTE#

EC_MUTE# 27
USB1_EN# 32

CMOS_ON# 25

TP_CLK 31

TP_DATA 31

TS_DISABLE# 25

ME_EN 6

VCIN0_PH1 37

EC_SPI_MISO 7
EC_SPI_MOSI 7
EC_SPI_CLK 7
EC_SPI_CS0# 7

USB_CHG_CTL2 32
SYS_PWROK 8

USB2_EN# 32
BATT_CHG_LED# 33
CAPS_LED# 31
PWR_LED# 33
BATT_LOW_LED# 33

SYSON 35,40

EC_RSMRST# 8
USB_CHG_STATUS# 32
VCIN1_ADP_PROCHOT 37
VCOUT1_PROCHOT# 37
VCOUT0_MAIN_PWR_ON 39

BKOFF# 25

+1.05VS_PGOOD 43

VCIN1_AC_IN 18,38
EC_ON 39

ON/OFF# 33

LID_SW# 33

SUSP# 35,40,43,44

1 2

R208 43_0402_1%

R265 0_0402_5%

1 2

9012@

C294

9022@

FAN_SPEED1

1 8

FAN_SPEED2

2 7

USB1_EN#

3 6

USB_CHG_EN

4 5

RP33 10K_8P4R_5%

USB2_EN#

1 2

R277 10K_0402_5%

R271 10K_0402_5%@

1 2

R274

R273

+3VALW_EC

SIT

DS3

1 2

1 2

DS3

DS3

SIV

SUSACK# 8

+3VALW

0_0402_5%

SIV

0_0402_5%

SIV

DPWROK_EC 8

PCH_PWR_EN 35

H_PECI 4

VR_TT# 45

AC_BATT 18,37

VR_HOT#46

LID_SW#

NUVOTON_VTT

ESD

SYSON

@ESD@

VCOUT1_PROCHOT#

R267

1 2

100K_0402_5%

R268

C296

1

2

0.1U_0402_16V7K

SIT

R260 0_0402_5%

1 2

R223 0_0402_5%

1 2

VCOUT1_PROCHOT#

2N7002K_SOT23-3

+3VALW

@

SIT

1 2

SIV

R1567 4.7K_0402_5%@

TP_CLK

TP_DATA

VCIN1_BATT_TEMP

VCIN1_AC_IN

0_0402_5%

1 2

R1568 4.7K_0402_5%

1 2

R1569 4.7K_0402_5%@

1 2

R1570 4.7K_0402_5%

1 2

C341 100P_0402_50V8J

C336 100P_0402_50V8J

1 2

13

D

2

G

Q13

S

9012@

+1.05VS

1 2

1 2

R203 4.7K_0402_5%@

1

@

C297
47P_0402_50V8J

2

+5VS+5VS

+3VS +3VS

H_PROCHOT# 4

C286

1000P_0402_50V7K

1

EMI@

2

1

GATEA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ

4

LPC_FRAME#

5

LPC_AD3

7

LPC_AD2

8

LPC_AD1

10

LPC_AD0

12

CLK_PCI_EC

13

PCIRST#/GPIO05

37

EC_RST#

20

EC_SCII#/GPIO0E

38

GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

EC_SMB_CK1/GPIO44

78

EC_SMB_DA1/GPIO45

79

EC_SMB_CK2/GPIO46

80

EC_SMB_DA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

GPIO0A

17

GPIO0B

18

GPIO0C

19

GPIO0D

25

EC_INVT_PWM/GPIO11

28

FAN_SPEED1/GPIO14

29

EC_PME#/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

PCH_PWROK/GPIO18

34

SUSP_LED#/GPIO19

36

NUM_LED#/GPIO1A

122

XCLKI/GPIO5D

123

XCLKO/GPIO5E

SA000079Y00

+3VS

5

P

B

Y

A

G

3

+3VALW_EC

C287

1000P_0402_50V7K

1

EMI@

2

LPC & MISC

Int. K/B
Matrix

4

SVT

SIT

R224 0_0603_5%@

1 2

R225 0_0603_5%

1 2

SVT

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

EC_RST#

EC_SCI#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2

NPCE288NA0DX LQFP 128P KBC

R270 0_0402_5%

1 2

@

U27

2

1

w w w . c h i n a f i x . c o m

MC74VHC1G08DFT2G_SC70-5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

2014/03/03 2015/03/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

C

Date: Sheet

Compal Electronics, Inc.

BIOS & EC I/O Port

LA-B131P

of

30 52Tuesday, March 04, 2014

1.0

Thermal Sensor

5

4

3

2

1

Close U28

2200P_0402_50V7K

D D

C301

2200P_0402_50V7K

KB CONN. TP CONN.

C C

KSI[0..7]

KSO[0..15]

CAPS_LED#30

B B

REMOTE1+

1

C299

2

REMOTE1-

REMOTE2+

1

@

2

REMOTE2-

KSI[0..7] 30

KSO[0..15] 30

SIT

R230 649_0402_1%

+5VS

MESC5V02BD03 3P C/A SOT23

1 2

@ESD@

+3VS

2

@

C300

0.1U_0402_16V7K

SIT

2

3

D13

1

KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6

KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

+5VS_CAPLED

CAPS_LED#

1

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

27
28

SMSC thermal sensor
Close to thermal pipe

REMOTE1+

REMOTE1-

REMOTE2+

REMOTE2-

Address 1001_101xb

JKB1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

GND
GND

ACES_50504-0260N-001

CONN@

U28

1

VDD

2

DP1

3

DN1

4

DP2

5

DN2

EMC1403-2-AIZL-TR_MSOP10

P/N:SA000029210

F75303M P/N:SA0 00046C00

SMCLK

SMDATA

ALERT#

THERM#

GND

10

9

8

7

6

+3VS

12

EC_SMB_CK2

EC_SMB_DA2

THM_ALERT#_R

R227
10K_0402_5%

@

R243

1 2

SIV

0_0402_5%

EC_SMB_CK2 7,30

EC_SMB_DA2 7,30

THM_ALERT# 18

TP_CLK30
TP_DATA30

C304

@EMI@

100P_0402_50V8J

REMOTE1+33

REMOTE1-33

REMOTE2+18

REMOTE2-18

REMOTE1+

REMOTE1-

C302

@

100P_0402_50V8J

REMOTE1,2+/-:
Trace width/space:10/10 mil
Trace length:<8"

1

1

C305

@EMI@

100P_0402_50V8J

2

2

3

1

1

2

B

2

E

+3VS

@

PCH_SMB_CLK7,15,16
PCH_SMB_DATA7,15,16

2

D12

@ESD@

PJSOT24C 3P C/A SOT-23

To PWR/B

Close to GPU

C

3 1

Q9

@

MMST3904-7-F_SOT323-3

C303

0.1U_0402_16V7K

SIT

R228 0_0402_5%

1 2

R229 0_0402_5%

1 2

SIT

PCH_SMBCLK_TP

PCH_SMBDATA_TP

@EMI@

SIT

TP_CLK
TP_DATA

C306

100P_0402_50V8J

1

2

JTP1

6
5
4
3
2
1

ACES_51524-0060N-001

SP010014M10

CONN@

1

C307

@EMI@

2

100P_0402_50V8J

8

6

G2

7

5

G1
4
3
2
1

Screw

H6

H15

H7

H12
HOLEA

H_3P7

H10
HOLEA

H_3P7

H14
HOLEA

1

1

H_3P7

H11
HOLEA

1

1

H_3P7

FD4

FD3

1

1

CHASSIS1_GND

H_3P3

LAN

w w w . c h i n a f i x . c o m

Zero point

HOLEA

CPU

GPU

A A

1

H_3P7

H9
HOLEA

1

H_3P7

FD2

FD1

1

1

5

H2
HOLEA

1

H5
HOLEA

1

H_1P5N

H4
HOLEA

1

H_3P1N

H3
HOLEA

H_3P3

H8
HOLEA

1

H_1P5N

1

Board side

NGFF

Fan

4

H13
HOLEA

1

H_2P5

H17
HOLEA

1

H_3P3

H21
HOLEA

1

H_1P3X1P8N

HOLEA

1

H_2P5

3

H19

H20

HOLEA

HOLEA

1

1

H_2P5

H_4P1X3P1N

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

H18

H16
HOLEA

1

H_2P5

HOLEA

HOLEA

1

1

H_2P5

H_3P0

2014/03/03 2015/03/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

KB/TP/Thermal Sensor

LA-B131P

1

of

31 52Tuesday, March 04, 2014

1.0

A

USB3.0 <Port1>

@EMI@

@EMI@

+USB3_VC CA

W=80mils

8

OUT

7

OUT

6

OUT

USB_OC0 #

5

12

EMI@

1

443

12

12

EMI@

443

1

12

12

EMI@

443

1

12

USB_OC0 # 9,1 0

CON-USBP0+

1

CON-USBP0-

U3RXDN1

U3RXDP1

1

U3TXDN1

U3TXDP1

1

U3TXDP1

U3TXDN1

U3RXDP1

U3RXDN1

D16

1

2

4

5

3

TVWDF 1004AD 0_DFN9

@ESD@

SIV (EMI suggestion)

USB20_P 0

USB20_N0

SIT

1
2
3

R231 0 _0402 _5%@EMI @

R233 0_0402_5%@EMI@

2A

U29

GND
IN
IN
EN#4OC#

AP2301 MPG-13 MSO P 8P

L15

2

2

3

DLW21 HN900HQ2L _4P

R235 0 _0402 _5%@EMI @

L17

3

2

2

DLW21 HN900HQ2L _4P

R237 0 _0402 _5%

R239 0 _0402 _5%@EMI @

L19

3

2

2

DLW21 HN900HQ2L _4P

R241 0 _0402 _5%

+5VALW

1

2

C310

C311

@

2.2U_060 3_10V6 K

2

1

USB1_EN#30

USB20_P 010

USB20_N010

U3TXDN1_ R

12

C316 0.1U_0402_ 16V7K

U3TXDP1 _R

12

C318 0.1U_0402 _16V7 K

USB3_TX 1_N10

USB3_TX 1_P10

USB3_RX 1_N10

USB3_RX 1_P10

0.1U_040 2_16V7 K

1 1

2 2

U3TXDP1

9

U3TXDN1

8

U3RXDP1

7

U3RXDN1

6

B

+USB3_VC CA

220U 6.3V M B2 H1.9

470P_0402_50V7K

1

C1312

C309

12

+

2

CON-USBP1+

CON-USBP1-

SIV (EMI suggestion)

C

D21

@EMI@

1

1

10

2

2

9

3

3

8

4

4

7

556

GND

RCLAMP3 304N.TCT _SLP2 626P10 -10

11

D

E

USB3.0 <Port2>

10

CON-USBP0-

9
8

CON-USBP0+

7
6

0.1U_040 2_16V7 K

+5VALW

2

1

C315

@

C314

2.2U_060 3_10V6 K

1

2

USB2_EN#30

SIT

2A

U30

1

GND

2

IN

3

IN
EN#4OC#

AP2301 MPG-13 MSO P 8P

+USB3_VC CB

W=80mils

8

OUT

7

OUT

6

OUT

USB_OC0 #

5

+USB3_VC CB

220U 6.3V M B2 H1.9

470P_0402_50V7K

1

C1311

C313

12

+

2

Pseudo Cap(C345, C346) to protect L16

R232 0_0402_5%@EMI@

12

L16

EMI@

+USB3_VC CA

CON-USBP0­CON-USBP0+

U3RXDN1
U3RXDP1

U3TXDN1
U3TXDP1

JUSB1

1

VBUS

2

D-

3

D+

4

GND

5

STDA_SSRX-

6

STDA_SSRX+

7

GND

8

STDA_SSTX-

9

STDA_SSTX+

10

GND

11

GND

12

GND

13

GND

SINGA_2 UB4039-2 00011 F

CONN@

USB20_P 1

USB20_N1

2

3

DLW21 HN900HQ2L _4P

R234 0_0402_5%@EMI@

3

2

3

2

2

12

L18

2

@EMI@

L20

2

@EMI@

USB20_P 110

USB20_N11 0

C345

0.1U_040 2_16V7 K

SVT

C346

12

0.1U_040 2_16V7 K

12

USB3_RX 2_N10

USB3_RX 2_P10

USB3_TX 2_N10

USB3_TX 2_P10

U3TXDN2_ R

12

C317 0.1U_0402_1 6V7K

U3TXDP2 _R

12

C319 0.1U_0402_ 16V7K

CON-USBP1+

1

1

CON-USBP1-

443

0_0402 _5%@E MI@

12

EMI@

EMI@

12

12

12

443

1

1

0_0402 _5%

0_0402 _5%@E MI@

443

1

1

0_0402 _5%

U3RXDN2

U3RXDP2

U3TXDN2

U3TXDP2

R236

D17

U3RXDN2 U3 RXDN2

1

2

4

5

3

TVWDF 1004AD 0_DFN9

@ESD@

SIV (EMI suggestion)

9

8

U3TXDN2U3T XDN2

7

U3TXDP2U3 TXDP2

6

U3RXDP2 U3RXDP2

DLW21 HN900HQ2L _4P

R238

R240

DLW21 HN900HQ2L _4P

R242

+USB3_VC CB

CON-USBP1­CON-USBP1+

U3RXDN2
U3RXDP2

U3TXDN2
U3TXDP2

JUSB2

1

VBUS

2

D-

3

D+

4

GND

5

STDA_SSRX-

6

STDA_SSRX+

7

GND

8

STDA_SSTX-

9

STDA_SSTX+

10

GND

11

GND

12

GND

13

GND

SINGA_2 UB4039-2 00011 F

CONN@

USB2.0 + Charger

+USB2_VC CA

470P_0402_50V7K

47U_0805_6.3V6M

C467

1

12

C468

USB20_N2 10
USB20_P 2 10

2
@

R245 0_0402_5%@EMI@

12

L21

EMI@

CON_USB2 0_P2_L

CON_USB2 0_N2_L

B

2

3

DLW21 HN900HQ2L _4P

R248 0_0402_5%@EMI@

2

12

CON_USB2 0_P2

1

1

CON_USB2 0_N2

443

CON_USB2 0_P2 33

CON_USB2 0_N2 33

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

Compal Secret Dat a

2014/03/03 2015/03/03

Deciphered Date

Compal Electronics, Inc.

Title

Size Docume nt Number Rev

D

Date: Sheet of

USB2.0/3.0

LA-B131P

E

32 52Tuesday, March 04 , 2014

3 3

+5VALW

C320 0.1U_0402_1 6V7K

12

12

C321 4.7U_0402_6 .3V6M

@

USB_CHG_ STATUS#30

USB_OC1 #9,10

4 4

R259 0_0402_5 %@

USB_CHG_ EN30
USB_CHG_ CTL130
USB_CHG_ CTL230
USB_CHG_ CTL330

12

A

U32

1

IN

9

STATUS#

13

FAULT#

4

ILIM_SEL

5

EN

6

CTL1

7

CTL2

8

CTL3

TPS254 4RTER_ QFN16_ 3X3

DM_OUT

DP_OUT
ILIM_LO

ILIM_HI

OUT
DP_IN
DM_IN

GND
T-PAD

+USB2_VC CA

12

CON_USB2 0_P2_L

10

CON_USB2 0_N2_L

11

USB20_N2

2

USB20_P 2

3

R246 2.2M_0402_ 1%@

15

R247 20K_0402 _1%

16
14
17

12
12

w w w . c h i n a f i x . c o m

1.0

Power Board CONN.

+3VLP

ON/OFFBTN#

J3

1 2

SHORT PADS

J4

1 2

SHORT PADS

R251
100K_0402_5%

1 2

R253

1 2

0_0402_5%

J3: TOP
J4: BOT

NOVO#30

3

1

SIV

+3VLP

R266
100K_0402_5%

1 2

SIT

PWR_LED#30

REMOTE1+31
REMOTE1-31

NOVO#
ON/OFFBTN#

2

D20

ESD@

PJSOT24C 3P C/A SOT-23

ON/OFF#

@

+3VALW

ON/OFFBTN#

PWR_LED#

ON/OFF# 30

+5VALW

JPWR1

8

8

7

10

7

G2

6

9

6

G1

5

5

4

4

3

3

2

2

1

1

ACES_51522-00801-001

CONN@

EXT_MIC_SLEEVE

EXT_MIC_RING2

2

3

@ESD@

SCA00001A00

D19

1

AZ5125-02_SOT23-3

I/O Board CONN.

PLT_RST#8,17,26,29,30

CRCLK_REQ#7,9
PCIE_PTX_C_DRX_P210
PCIE_PTX_C_DRX_N210

PCIE_PRX_DTX_P210
PCIE_PRX_DTX_N210

HP_OUTL27
HP_OUTR27
EXT_MIC_SLEEVE27

EXT_MIC_RING227

LID_SW#30

MIC2-VREFO27

+USB2_VCCA

40 mils
40 mils

R321 2.2K_0402_5%

1 2

R322 2.2K_0402_5%

1 2

CS1

0.1U_0402_16V7K

1 2

@EMI@

JIO1

313132

292930
272728
252526
232324
212122
191920
171718
151516
131314
111112
9910

7

7

5

5

3

3

1

1

ACES_50255-03001-001

CONN@

32

30
28
26
24
22
20
18
16
14
12
10
8

8

6

6

4

4

2

2

CON_USB20_P2 32
CON_USB20_N2 32

+3VS

+5VS

+3VALW

CLK_PCIE_CR 7

CLK_PCIE_CR# 7

PLUG_IN# 27

SPDIF_OUT 27

EMC

SPDIF_OUT

1

C244
22P_0402_50V8J

2

@EMI@

12

R30
33_0402_5%

@EMI@

SIV (EMI suggestion)

LED Board CONN.

BATT_LOW_LED#30
BATT_CHG_LED#30
PCH_SATALED#6,9
TP_LOCK_LED#30

+3VS

PWR_LED#
BATT_LOW_LED#
BATT_CHG_LED#
PCH_SATALED#
TP_LOCK_LED#

+3VLP

JLED1

8

8

7

7

G2

6

6

G1

5

5

4

4

3

3

2

2

1

1

ACES_51522-00801-001

CONN@

FAN1 Conn

10
9

+5VS

SVT

R256 0_0603_5%

1 2

2

C324
10U_0603_6.3V6M

1

FAN_SPEED130

EC_FAN_PWM130

FAN_SPEED230

EC_FAN_PWM230

+5VS_FAN

JFAN1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

GND

10

GND

ACES_50278-00801-001

CONN@

FAN1 FAN2

FAN_SPEED1
EC_FAN_PWM1

FAN_SPEED2
EC_FAN_PWM2

w w w . c h i n a f i x . c o m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

2014/03/03 2015/03/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

C

Date: Sheet

Compal Electronics, Inc.

FAN/PWR/LED/IO Board

LA-B131P

33 52Tuesday, March 04, 2014

of

1.0

5

D D

4

+CHGRTC_R

12

RG1

330_0402_5%

GCLK@

3

2

1

C C

+3VLP

0.1U_0402_16V7K

B B

CG4

GCLK@

1

2

0.1U_0402_16V7K

+3VALW

CG10

GCLK@

1

2

0.1U_0402_16V7K

+1.8VGS

GCLK@

15P_0402_50V8J

1

CG1

2

CL28

GCLK@

+3V_LAN

CG3

0.1U_0402_16V7K

GCLK@

4

1

25MHZ_10PF_7V25000014

1

2

22U_0805_6.3V6M

YG1

NC

OSC

GCLK@

CG5

GCLK@

1

2

0.1U_0402_16V7K

OSC

NC

+1.05VS

3

2

1

2

CG2

GCLK@

CLK_X1

CLK_X2

1

CL29
12P_0402_50V8J

GCLK@

2

1

2

UG1

10

VRTC

15

V3.3A

2

VDD

11

VIOE_27M

8

VIO_25M

3

VIOE_24M

CLK_X2

16

X2

CLK_X1

1

X1

SLG3NB3374VTR_TQFN16_2X3

GCLK@

SA00006RD00

SIV

GND1

4

32.768kHz

GND2

GND3

7

13

VOUT

27M

25M

24M

GND4

17

RTC_VOUTGCLK_VRTC

14

CPU_RTCX1_GCLK_R

9

GPU_XTALIN_GCLK_R

12

LAN_XTLI_GCLK_R

6

CPU_XTAL24_IN_GCLK_R

5

510_0402_5%

GCLK@

SVT

1

CG11

2.2U_0402_6.3V6M

GCLK@

2

RG4 0_0402_5%GCLK@

1 2

SVT

RG5 0_0402_5%GCLK@

1 2

RG7 33_0402_5%GCLK@

1 2

RG8 0_0402_5%GCLK@

1 2

1

CG9
15P_0402_50V8J

12

RG2

1

2

2

1

CG8
15P_0402_50V8J

@EMI@

2

CG7
15P_0402_50V8J

@EMI@

@EMI@

SIV

CPU_RTCX1_GCLK 6

GPU_XTALIN_GCLK 18

LAN_XTLI_GCLK 26

CPU_XTAL24_IN_GCLK 7

CPU_32.768KHz

GPU_27MHz for GPU

LAN_25MHz

CPU_24MHz

A A

w w w . c h i n a f i x . c o m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

2014/03/03 2015/03/03

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

GCLK

LA-B131P

1

52Tuesday, March 04, 2014

34

1.0

A

B

C

D

E

+5VALW TO +5VS
+3VALW TO +3VS

1 1

1 2

0.1U_0402_16V7K
C2306

1

2

SUSP

12

SIV

+5VALW

0_0402_5%

C2305

1

2

+5VALW

@

2

G

@

10U_0603_6.3V6M

@

12

13

D

S

SUSP#30,40,43,4 4

2 2

3 3

R630

10mil

+3VALW

C2318

C2316

1

2

1

2

SUSP#

R622

10K_0402_5%

10U_0603_6.3V6M

@

@

0.1U_0402_16V7K

+5VALW

EN_3VS_5VS

+5VL

+3VALW

R620
100K_0402_5%

Q45
SSM3K7002BFU_SC70-3

U2301

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

APE8990GN3B_DFN_14P

SVT

VOUT1
VOUT1

GND

VOUT2
VOUT2

GPAD

14
13

C2322

1 2

12

CT1

11

C2309

1 2

10

CT2

9
8

15

Need to check power sequence

+0.675VS

12

R627

13

D

Q47

2

G

S

@

@

SSM3K7002BFU_SC70-3

470_0402_5%

SUSP

5VS

220P_0402_50V7K

V0.2

470P_0402_50V7K

3VS

2

2

470_0402_5%

SUSP

J510

JUMP_43X79@

J511

JUMP_43X79@

2

R628

G

112

112

+1.05VS

12

@

13

D

Q48

@

S

SSM3K7002BFU_SC70-3

+5VS

@

+3VS

@

C2308

C2307

C2324

0.1U_0402_16V7K

10U_0805_10V4Z

1

1

2

2

10U_0603_6.3V6M

C2323

0.1U_0402_16V7K

1

1

2

2

DS3

+5VALW

PCH_PWR_EN30

+3VALW to +3V_PCH

+3VALW

1

C293

4.7U_0603_6.3V6K

DS3@

R221

1 2

47K_0402_5%

2

G

2

PCH_PWR_EN#

13

D

DS3@

Q19
2N7002K_SOT23-3

S

DS3@

NODS3@

R219

12

0_0603_5%

3 1

DS3@

Q16

ME2301DC-G_SOT23-3

2

1

DS3@

C312

0.1U_0402_16V7K

2

+3V_PCH

DS3@

4.7U_0603_6.3V6K

1U_0603_10V6K

1

C308

12

@

R220

2

470_0603_5%

13

D

PCH_PWR_EN#

2

G

@

S

Q18
2N7002K_SOT23-3

1

2

@

C274

+5VALW

12

R619

@

SYSON#

SYSON30,40

4 4

10K_0402_5%

A

R621

12

@

100K_0402_5%

61

Q44A

@

2

ME2N7002D1KW-G 2N SOT363-6

SYSON#

+1.35V

12

R629

470_0402_5%

w w w . c h i n a f i x . c o m

@

3

Q44B

@

ME2N7002D1KW-G 2N SOT363-6

5

4

B

SVT

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2014/03/03 2015/03/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

DC/DC Interface

LA-B131P

E

35 52Tuesday, March 04, 2014

1.0

of

5

JDCIN1

ACES_50299-00501-003_5P

@CONN@

S

P02000YD00

D D

90W adaptor

APDIN

1

1

2

2

3

3

4

4

5

5

PF101

FUSE 0501010.WR 10A 32V

SP040005R00

APDIN1

21

+3VALW

12

PC101

1000P_0402_50V7K

EMI@

PR101

@

0_0402_5%

1 2

1 2

PR102

750_0402_1%

PR103

100K_0402_5%

1 2

VIN

PR104

100K_0402_5%

+CHGRTC

PR105

1K_0603_5%

PD101

S SCH DIO BAS40CW SOT-323

C C

+RTCBATT

2

1

3

PR106

1K_0603_5%

1 2

1 2

+CHGRTC_R

4

EMI@

PL101

FBMA-L11-201209-121LMA50T_0805

1 2

5A*2

12

EMI@

PL102

FBMA-L11-201209-121LMA50T_0805

1 2

SM01000BY00

PC102

100P_0402_50V8J

EMI@

PQ101A

2N7002KDW-2N_SOT363-6

6 1

2

34

12

PQ101B

2N7002KDW-2N_SOT363-6

+3VLP

JBATT1

@CONN@

1

1

2

2

3

GND

4

GND

ACES_50271-0020N-001

SP02000RO00

3

2

1

VIN

12

12

PC104

PC103

100P_0402_50V8J

1000P_0402_50V7K

EMI@

EMI@

ADP_ID 30

12

PC106

680P_0603_50V7K

ADP_ID_CLOSE 30

A/D

12

PC105

0.1U_0402_16V7K

5

RTC Battery

B B

A A

GC02001DR00
BATT CR2032 3V 210MAH MB 5 W/C
30MM

w w w . c h i n a f i x . c o m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2014/03/03 2015/03/03

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PWR DCIN / RTC Battery

Size Document Number Rev

Custom

BE_BDW

2

Date: Sheet

1

36 52Tuesday, March 04, 2014

1.0

of

5

@CONN@

JBATT2

GND
GND

D D

SUYIN_125017GA007G101ZL

LTCX005GY00

2S2P / 48W

VMB2

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8
9

EC_SMDA

EC_SMCA

12

PR201

PF201

FUSE 0501015.WR 15A 32V

SP040006F00

12

100_0402_1%

PR211

100_0402_1%

1 2

PR212

6.49K_0402_1%

1 2

PR214
10K_0402_5%

21

4

PL202

EMI@

FBMA-L11-201209-121LMA50T_0805

1 2

VMB

+3VLP

PL201

EMI@

FBMA-L11-201209-121LMA50T_0805

1 2

SM01000BY00

5A*2

12

PC201

EMI@

1000P_0402_50V7K

EC_SMB_CK1 30,38

EC_SMB_DA1 30,38

VCIN1_BATT_TEMP 30

BATT+

12

PC202

0.01U_0402_25V7K

A/D

EMI@

3

2

1

PH201 under CPU botten side :
CPU thermal protection at 93 +-3 degree C

AC_BATT18,30VCOUT1_PROCHOT#30

C C

PC204

0.01U_0402_25V7K

VCIN1_BATT_DROP

+2.48V

12

PR232

14.7K_0402_1%

PR231

10K_0402_1%

B B

A A

1 2

+5VS

12

3

2

PR225

1 2

200_0603_5%

470P_0402_50V7K

+5VS

8

P

+

1

O

-

G

PU202A
AS393MTR-E1 SO 8P OP

4

2N7002KDW-2N_SOT363-6

+2.48V

PC209

12

PR220
47K_0402_1%

1 2

+5VS

1 2

61

2

34

PQ201B

5

2N7002KW_SOT323-3

PR223

10K_0402_1%

1 2

3

Cathode

PR219

10K_0402_1%

PQ201A
2N7002KDW-2N_SOT363-6

+5VS

PR218

10K_0402_1%

1 2

13

D

PQ205

S

PR224

10K_0402_1%

1 2

2

REF

PU201
APL431LBAC-TRL_SOT23-3

SA00001MU00

Anode

1

2N7002KDW-2N_SOT363-6

12

PC203

0.022U_0402_16V7K

12

PR202

1.5M_0402_5%

2

G

PQ202A

12

PD204

1N4148WS-7-F_SOD323-2

1 2

61

2

PR227

15K_0402_1%

PR229

10K_0402_1%

PR228
0_0402_5%

+2.48V

12

1 2

PR230
0_0402_5%

1 2

34

PQ202B
2N7002KDW-2N_SOT363-6

5

VCIN1_BATT_DROP

AS393MTR-E1 SO 8P OP

PU202B

PR226

665K_0402_1%

1 2

8

5

P

+

6

-

G

4

+5VS

7

O

Recovery at 56 +-3 degree C

VCIN1_ADP_PROCHOT30

12

PR222

34

47K_0402_1%

PQ215B

5

2N7002KDW-2N_SOT363-6

61

2N7002KDW-2N_SOT363-6

PQ215A

2

VCOUT1_PROCHOT#

0.1U_0402_25V6

ADP_I30,38

12

PR216

PR217

@

10K_0402_1%

1 2

5.1K_0402_1%

PR221
100K_0402_1%

1 2

VCIN0_PH130

+EC_VCCA

12

PR215

16.5K_0402_1%

12

PH201
100K_0402_1%_TSM0B104F4251RZ

SL200002H00

ECAGND 30

B+

12

PR14

56.2K_0402_1%

VCIN1_BATT_DROP 30

PC9

@

12

PR15

1 2

10K_0402_1%

w w w . c h i n a f i x . c o m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

3

2014/03/03 2015/03/03

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PWR-BATTERY CONN/OTP

Size Document Number Rev

Custom

BE_BDW

2

Date: Sheet

1

37 52Tuesday, March 04, 2014

1.0

of

5

AO4435L Vds=-30V
Rds_on=27~36mohm@Vgs=-5V
ID = 8A (Ta=70C)

VIN

D D

C C

AC_OFF

B B

A A

12

PR301

V1

61

2N7002KDW -2N_SOT363-6

2

1 2

10K_0402_1%

DTA144EUA_SC70-3

47K_0402_5%

13

2

PQ307A

PACIN

PQ311

DTC115EUA_SC70-3

ACOFF-1

PR315

PQ301

SB00000DJ10

AO4435L 1P SO8

8
7

5

PQ304

2

1 3

PQ305

DTC115EUA_SC70-3

PACIN_2

PR311

47K_0402_1%

1 2

2

4

13

AO4435L Vds=-30V
Rds_on=7.4~9.5mohm@Vgs=-6V
ID = 14A (Ta=70C)

P2

1
2
36

12

12

PC301

0.1U_0603_25V7K

P2-1

12

PR308

150K_0402_1%

P2-2

34

5

PR303

200K_0402_1%

PQ307B2N7002KDW-2N_SOT363-6

1
2
3 6

20K_0402_1%

1 2

PQ302

SB000012B00

AO4455 1P SO8

4

5600P_0402_25V7K

PR312

PC312

1 2

0.01u_0402_25V7K

EC_SMB_DA130,37

EC_SMB_CK130,37

8
7

5

1 2

PC302

VIN PACIN

12

PR309

124K_0402_1%

PR328

+3VLP

4

12

249K_0402_1%

P3

ADP_I30,37

PR317

121K_0402_1%

1 2

Power Rating = 1W
VACP~VACN spec < 80.64mV

SD00000K820

PR302

0.01_1206_1%

1

2

6

12

ACDET

7

IOUT

8

SDA

BQ24737RGRR_VQFN20_ 3P5X3P5

9

SCL

10

12

ILIM

PR320

100K_0402_1%

PR323

@

10K_0402_5%

+3VALW

PC313

1 2

100P_0603_50V8

PC316

0.01U_0402_25V7K

MOSFET: 3x3 DFN
H

/S Rds(on): 22mohm(Typ), 34mohm(Max)

Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C

L/S Rds(on): 9.8mohm(Typ), 15.8mohm(Max)
Idsm: 12A@Ta=25C, 10.5A@Ta=70C

B+

4

3

ACP

PC308

0.1U_0402_25V6

1 2

ACPRN#

3

4

5

ACOK

CMPIN

CMPOUT

PU301

SA00004RZ00

SRN12BM

SRP

12
13

11

12

PR321

PR322

6.8_0603_5%

12

PC321

1 2

0.1U_0402_25V6

12

PC323

0.1U_0402_25V6

ACN

10_0603_5%

0.1U_0402_25V6

1 2

PC310

1 2

0.1U_0402_25V6

1

2

ACP

ACN

PHASE

HIDRV

REGN

LODRV

GND

15

14

3

12

@EMI@

10U_0805_25V6K

PC309

TP

VCC

BTST

PL301

EMI@

1UH +-20% PH041H -1R0MS 3.8A

1 2

SH00000YG00

3.8x3.8xH1.8

PC303

DCR: 20~25mohm
Idc / Isat: 3.8A

BQ24737VCC

BST_CHG

PD301

RB751V-40_SOD323-2

PC319
1U_0603_16V7

PR310

10_1206_5%

DH_CHG

12

DL_CHG

21

20

19

18

17

16

12

12

PC322

@

0.1U_0402_25V6

2

Need EC write ChargeOption() bit[8]=0
to disable iFault_Hi function.

CHG_B+

12

PC304

charge current: 6.6A
discharge current: 8A
Hybrid: BATT limit 6.5A

P2

12

PC314

1 2

1U_0603_25V6K

LX_CHG

PR318

2.2_0603_5%

1 2

BQ24737VDD

0.047U_0603_16V7K

ACPRN#

12

PC305

10U_0805_25V6K

PR313

0_0402_5%

1 2

PC315

1 2

PR324

47K_0402_1%

DTC115EUA_SC70-3

12

12

PC307

PC306

0.1U_0402_25V6

10U_0805_25V6K

EMI@

12

PQ314

2

2200P_0402_50V7K

EMI@

4

4

BQ24737VDD

12

13

PQ303

AO4455 1P SO8

1
2
3 6

ACOFF-1

21

PD302

1SS355_UMD2-2

4

1SS355_UMD2-2

PD303

SD00000K820

0.01_1206_1%

1

2

SRP

DISCHG_G

200K_0402_1%

1 2

12

PR305
47K_0402_1%

DISCHG_G-1

PQ306

13

DTC115EUA_SC70-3

2

SB00000H800
5

SB000010U00
5

PR325
10K_0402_1%

7x7xH3

CR: 18~22mohm

D
Idc: 6.5A
Isat: 9.5A

PQ310

AON7408L 1N DFN

123

4.7UH +-20% PC MB104T-4R7MS 8.5A

6251_SN

PQ312

AON7752 1N DFN

123

10K_0402_1%

1 2

PACIN

12

12K_0402_1%

PR304

SH00000Q900

PL302

1 2

12

PR319

EMI@

4.7_1206_5%

12

PC320

EMI@

680P_0603_50V7K

PR326

PR327

For disable pre-charge circuit

SB000012B00

8
7

5

12

21

12

PC311

0.1U_0603_25V7K

PR314

SRN

1

VIN

PR306
200K_0402_1%

PQ309
2N7002KW_S OT323-3

13

D

S

4

3

12

PC317

10U_0805_25V6K

VCIN1_AC_IN 18,30

2

G

PC318

10U_0805_25V6K

PACIN_2

12

@

PC324

10U_0805_25V6K

BATT+

12

w w w . c h i n a f i x . c o m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

3

Compal Secret Data

Deciphered Date

2015/03/032014/03/03

2

Title

Size D ocument Number Rev

Date: Sheet

Compal Electronics, Inc.

Charger_BQ24737

BE_BDW

1

1.0

of

38 52Tuesday, March 04, 2014

A

1 1

B+

PL401

EMI@

HCB2012KF-121T50_0805

1 2

SM01000C000

5A

3V_VIN

12

12

12

PC405

PC401

2200P_0402_50V7K

0.1U_0402_25V6

@EMI@

@EMI@

PC407

PC406

@

10U_0805_25V6K

10U_0805_25V6K

3V/5VALW_PG30

2 2

EC_ON30

VCOUT0_MAIN_PWR_ON30

B+

PL403

EMI@

HCB2012KF-121T50_0805

1 2

SM01000C000

5A

3 3

PC416

5V_VIN

12

12

PC419

PC418

10U_0805_25V6K

10U_0805_25V6K

2200P_0402_50V7K

@EMI@

12

2.2K_0402_5%

1 2

1 2

0_0402_5%

12

PC420

0.1U_0402_25V6

@EMI@

@

PR407

PR408

12

PR410

5V_VCC

12

PC421

4.7U_0603_6.3V6M

+3VLP

3V5V_EN

12

PC414

1M_0402_1%

@

4.7U_0402_6.3V6M

PU402

8

IN

9

GND

5

VCC

2

PG

SY8208CQNC_QFN10_3X3

SA000061N00

B

PU401

7

IN

8

12

9

12

PR415

100K_0402_1%

EN1

IN

EN2

BS

LX

OUT

GND

PG2LDO

SY8208BQNC_QFN10_3X3

SA000061M00

3.3V LDO 150mA~300mA

EN1 and EN2 dont't floating

EN1

EN2

BS

LX

OUT

LDO

5V_FB

3

BST_5V

6

10

4

7

1 2

+5VL

12

PC426

4.7U_0603_6.3V6M

3V5V_EN

1

5V LDO 150mA~300mA

1

3

6

10

4

5

PR413

0_0603_5%

BST_3V

3V5V_EN

3V_FB

PR405

1 2

0_0603_5%

+3VLP

12

PC412

4.7U_0603_6.3V6M

PC417

0.1U_0603_25V7K

1 2

LX_5V

0.01U_0402_25V7K

PC404

1 2

0.1U_0603_25V7K

LX_3V

PC415

6800P_0402_25V7K

PR414

@EMI@

PC427

@EMI@

1K_0402_5%

1 2

1 2

1.5UH_PCMB053T-1R5MS_6A_20%

12

SH00000SC00

5x5xH3
DCR: 20~25mohm
Idc: 6A

4.7_1206_5%

Isat: 10A

5V_SN

12

680P_0603_50V7K

C

PC403

1 2

1.5UH_PCMB053T-1R5MS_6A_20%

12

PR406

@EMI@

3V_SN

12

PC413

@EMI@

PR412

1 2

PL404

PR403

1K_0402_5%

1 2

PL402

1 2

SH00000SC00

5x5xH3
DCR: 20~25mohm
Idc: 6A

4.7_1206_5%

Isat: 10A

680P_0603_50V7K

ENLDO_3V5V

12

D

PR401
499K_0402_1%

1 2

12

PR404

150K_0402_1%

12

22U_0603_6.3V6M

PC411

+3VALWP

TDC=4A
Iocp : 6A

22U_0603_6.3V6M

PC408

22U_0603_6.3V6M

22U_0603_6.3V6M

PC410

PC409

12

12

B+

E

FSW : 750KHz

PJ401

@

+3VALWP +3VALW

12

22U_0603_6.3V6M

PC429

+5VALWP

TDC=6A
Iocp : 9A

22U_0603_6.3V6M

22U_0603_6.3V6M

PC423

PC422

12

12

22U_0603_6.3V6M

22U_0603_6.3V6M

PC424

12

12

22U_0603_6.3V6M

PC425

PC428

12

112

JUMP_43X118

2

FSW : 750KHz

PJ402

@

112

JUMP_43X118

2

+5VALW+5VALWP

4 4

w w w . c h i n a f i x . c o m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2014/03/03 2015/03/03

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

+3VALW/+5VALW

Size Document Number Rev

Custom

D

Date: Sheet

BE_BDW

39 52Tuesday, March 04, 2014

E

1.0

of

5

D D

PL501

EMI@

HCB2012 KF-121T50_080 5

B+

C C

1 2

7x7xH3
DCR: 6.7~7.4mohm
Idc: 12A
Isat: 15A

1UH +-20% PCMB063T-1R0MS 12A

12

+1.35VP

TDC : 7A
Iocp : 10.7A
FSW : 300KHz

B B

Mode Level +0.675VSP VTTREF_1.35V
S5 L off off
S3 L off on
S0 H on on

Note: S3 - sleep ; S5 - power off

A A

1

PC510

+

2

SGA20331E10

330U 2V D2 LESR9M EEFSX H1.9

ESR: 9mohm

12

PC501

0.1U_0402_25V6

@EMI@

PL502

1 2

SH00000 YE00

@EMI@

@EMI@

680P_04 02_50V7K

1.35V_B+

PC502

@EMI@

4.7_1206 _5%

4

12

12

PC504

PC503

2200P_0402_50V7K

PR503

PC513

MOSFET: 3x3 DFN
H/S Rds(on): 22mohm(Typ), 34mohm(Max)
Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C

L/S Rds(on): 8.2mohm(Typ), 14.5mohm(Max)
Idsm: 12A@Ta=25C, 15A@Ta=70C

10U_0805_25V6K

10U_0805_25V6K

5

PQ501AON7408L-3x3

4

SB00000H800

123

12

5

PQ502

12

SB000010U00

AON7752 1N DFN3X3EP

4

123

12

0.1U_060 3_25V7K

+5VALW

PC505

PR504

5.1_0603 _5%

1 2

PC512

1U_0603 _10V6K

3

BST_1.35 V

12.4K_04 02_1%

VDD_1.35 V

12

+5VALW

+3VALW

DDR_VTT_PG_CTRL15

2.2_0603 _5%

1 2

PR502

1 2

1U_0603 _10V6K

1 2

5.1_0603 _5%

SYSON30,35

PR501

DL_1.35V

15

14

CS_1.35V

1 2

887K_04 02_1%

13

12

11

1 2

PC508

1 2

PR513

PR505 1 00K_0402_5%

1.35V_B+

SUSP#30,35,43,44

BOOT_1.3 5V

DH_1.35V

SW_1 .35V

16

PHASE

LGATE

PGND

CS

RT8207M ZQW_W QFN20_3X3

VDDP

VDD

PGOOD

10

PR507

PR509

@

1 2

0_0402_ 5%

PC514

@

0.1U_040 2_10V7K

PR511

1_0402_ 1%

1 2

PR510

@

0_0402_ 5%

1 2

17

18

BOOT

UGATE

SA00004 OV00

S5

TON

8

9

TON_1.35V

EN_1.35V

12

2

1

+1.35VP

+0.675VSP

12

12

19

20

PU501

21

VTT

PAD

VLDOIN

S3

7

EN_0.675VSP

@

PC515

12

1

VTTGND

2

VTTSNS

3

GND

+VTTREF P

4

VTTREF

5

VDDQ

FB

6

FB_1.35V

12

PR508
10K_040 2_1%

+1.35VP +1.35V

PR506

8.2K_040 2_1%

1 2

+1.35VP

Vout=0.75V* (1+Rup/Rdown)

PJ501

@

112

JUMP_43 X118

+0.675VSP +0.675VS

PC506

10U_0805_6.3V6K

2

PJ503

@

112

JUMP_43 X39

PC507

10U_0805_6.3V6K

12

PC509

0.033U_0 402_16V7K

+1.35VP

2

w w w . c h i n a f i x . c o m

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/03/ 03

3

Compal Secret Data

Deciphered Date

0.1U_0402_10V7K

2015/03/ 03

2

Title

Size Document Num ber Rev

Date: Sheet

Compal Electronics, Inc.

RT8207M

Tuesday, March 04, 2014

BE_BDW

1

of

40 52

1.0Custom

A

B

C

D

+1.8VGSP_ON

12

1 1

+3VALW

PJ601

@

112

JUMP_43X79

22U_0805_6.3VAM

PU601

1

FB

2

PG

2

12

PC602

3

IN

4

PGND

SY8003ADFC DFN 8P

SA00007QP00

PGND
SGND

9
8

7

EN

6

LX

5

NC

LX_1.8VGSP

FB=0.6V

2 2

PC601

0.1U_0402_16V7K

PL601

1UH_PH041H-1R0MS_3. 8A_20%

1 2

SH00000YG00

12

PR604

PR605

20K_0402_1%

4.7_0603_5%

@EMI@

FB_1.8VSP

12

PC606

PR606

10K_0402_1%

@EMI@

680P_0402_50V7K

Vout=0.6V* (1+Rup/Rdown)

PR601

1 2

180K_0402_1%

12

PR603

1M_0402_5%

3.8x3.8xH1.8
DCR: 20~25mohm
Idc / Isat: 3.8A

12

Rup

PC603

12

Rdown

DGPU_PWR_EN 8,9,19,30,42

+1.8VGSP

22U_0603_6.3V6M

22U_0603_6.3V6M

12

68P_0402_50V8J

PC604

12

12

TDC : 1.6A

PC605

Iocp : 3A
FSW : 1MHz

@

PJ602

2

+1.8VGSP +1.8VGS

112

JUMP_43X79

3 3

4 4

w w w . c h i n a f i x . c o m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

2014/03/03 2015/03/03

Compal Secret Data

Deciphered Date

C

Title

Size D ocument Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

+1.8VGS

BE_BDW

D

41 52Tuesday, March 04, 2014

1.0

5

D D

C C

3VLDO_0.95VS

12

PR612

@

0_0402_5%

ILMT_0.95VS 3VLDO_0.95VS

12

@

PR615
0_0402_5%

The current limit is set to 8A, 12A or 16A when this pin
is pull low, floating or pull high

B+

PL602

EMI@

HCB2012KF-121T50_0805

1 2

12

PC611

2200P_0402_50V7K

@EMI@

12

12

PC613

PC609

@

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6

@EMI@

4

12

1M_0402_1%
PR609

ILMT_0.95VS

PU602

8

IN

9

GND

3

BYP

ILMT

2

PG

LDO

SY8208DQNC_QFN10_3X3

SA000061Q00

EN

BS

LX

FB

6

10

4

7

5

BST_0.95VS

12

0_0603_5%

1 2

LX_0.95VS

PC619

4.7U_0603_6.3V6K

PR611

1

B+_0.95VS

12

PC610

0.1U_0603_25V7K

12

PC620

4.7U_0603_6.3V6K

PC607

0.1U_0402_16V7K

PC612

1 2

+3VALW

12

PR608

1 2

150K_0402_1%

3

DGPU_PWR_EN 8,9,19,30,41

PR610

@EMI@

1UH +-20% PCMB053T-1R0MS 7A

4.7_1206_5%

1 2

1 2

SH00000Z200

@EMI@

SNB_0.95VS

PL603

680P_0603_50V7K

1 2

Rup

FB = 0.6V

Rdown

PC608

22U_0603_6.3V6M

PR613

12

12

PC614

78.7K_0402_1%

12

133K_0402_1%

VFB=0.6V
Vout=0.6V* (1+Rup/Rdown)

330P_0402_50V7K

PR616

22U_0603_6.3V6M

PC615

PC616

12

12

2

+0.95VSP

12

22U_0603_6.3V6M

PC618

+0.95VSP

TDC 5A

Iocp 8A
FSW 800KHz

22U_0603_6.3V6M

PC617

12

JUMP_43X118 @

112

PJ603

1

2

+VGA_PCIE

B B

A A

w w w . c h i n a f i x . c o m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

2014/03/03 2015/03/03

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet of

0.95VS

BE_BDW

1

42 52Tuesday, March 04, 2014

1.0

5

D D

C C

PL701

EMI@

HCB2012KF-121T50_0805

1 2

B+

3VLDO_1.05VS

12

PR706

@

0_0402_5%

ILMT_1.05VS 3VLDO_1.05VS

12

@

PR708
0_0402_5%

B B

The current limit is set to 8A, 12A or 16A when this pin
is pull low, floating or pull high

PC701

@EMI@

12

2200P_0402_50V7K

+3VS

12

12

PC706

PC705

@

10U_0805_25V6K

0.1U_0402_25V6

@EMI@

1 2

PR701

10K_0402_5%

10U_0805_25V6K

+1.05VS_PGOOD30

12

PC707

4

B+_1.05VS

ILMT_1.05VS

+1.05VS_PGOOD

PU701

8

IN

9

GND

3

BYP

ILMT

2

PG

LDO

SY8208DQNC_QFN10_3X3

SA000061Q00

3

PR702

0_0402_5%

+3VALW

1 2

12

@

0.22U_0402_10V6K

PC702

12

1M_0402_1%
PR703

EN

BS

LX

FB

6

10

4

7

5

BST_1.05VS

0_0603_5%

1 2

LX_1.05VS

12

PC713

PR705

1

PC704

0.1U_0603_25V7K

1 2

12

PC714

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

SUSP# 30,35,40,44

PR704

@EMI@

1UH +-20% PCMB053T-1R0MS 7A

4.7_1206_5%

1 2

1 2

SH00000Z200

@EMI@

SNB_1.05VS

PL702

680P_0603_50V7K

1 2

PR707

Rup

FB = 0.6V

Rdown

PC703

12

100K_0402_5%

12

PR709

133K_0402_1%

VFB=0.6V
Vout=0.6V* (1+Rup/Rdown)

22U_0603_6.3V6M

PC709

12

12

PC708

330P_0402_50V7K

2

+1.05VSP

PC712

12

+1.05VSP

22U_0603_6.3V6M

TDC=4.5A

Iocp 8A
FSW 800KHz

22U_0603_6.3V6M

22U_0603_6.3V6M

PC711

PC710

12

12

JUMP_43X118 @

PJ701

112

1

2

+1.05VS

A A

w w w . c h i n a f i x . c o m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

2014/03/03 2015/03/03

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet of

+1.05VS

BE_BDW

1

43 52Tuesday, March 04, 2014

1.0

5

D D

PL801

HCB2012KF-121T50_0805

1 2

B+

C C

3VLDO_1.5VS

12

PR711

@

0_0402_5%

ILMT_1.5VS

12

@

PR712
0_0402_5%

The current limit is set to 8A, 12A or 16A when this pin
is pull low, floating or pull high

12

12

PC831

PC829

@

0.1U_0402_25V6
10U_0805_25V6K

@EMI@

2200P_0402_50V7K

@EMI@

B+_1.5VS

12

12

PC830

PC828

10U_0805_25V6K

ILMT_1.5VS

4

PU801

8

IN

9

GND

3

BYP

ILMT

2

PG

LDO

SY8208DQNC_QFN10_3X3

SA000061Q00

EN

BS

LX

FB

1

BST_1.5VS

6

LX_1.5VS

10

4

7

3VLDO_1.5VS

5

0_0603_5%

1 2

12

PC825

PR810
1M_0402_1%

PR818

12

4.7U_0603_6.3V6K

0.1U_0603_25V7K

PC823

4.7U_0603_6.3V6K

1 2

PC827

1 2

+3VALW

200K_0402_1%

12

PC832

0.01UF_0402_25V7K

3

PR815

12

PR817

@

4.7_1206_5%

1 2

1 2

1UH +-20% PCMB053T-1R0MS 7A

SH00000Z200

FB = 0.6V

SUSP# 30,35,40,43

SNB_1.5VS

PL802

Rup

Rdown

PC824

@

680P_0603_50V7K

1 2

12

PR816

30.1K_0402_1%

12

PR812

20K_0402_1%

PC833

12

12

PC826

330P_0402_50V7K

VFB=0.6V
Vout=0.6V* (1+Rup/Rdown)

2

+1.5VSP

12

22U_0603_6.3V6M

PC820

+1.5VSP

TDC 5.5A

Iocp 8A
FSW 800KHz

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

@

PC822

PC821

12

12

PJ801

2

112

JUMP_43X118@

+1.5VS

1

B B

A A

w w w . c h i n a f i x . c o m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

2014/03/03 2015/03/03

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

+1.5VSP

Size Document Number Rev

C

LA-A321PR01

Date: Sheet of

1

44 52Tuesday, March 04, 2014

1.0

A

1 1

+3VGS

12

12

12

PR903 10K_0402_1%

+3VGS

+3VGS

47K_0402_1%

ISEN3_VGA

VSUM-_VGA

PR928

499_0402_1%

1 2

ISEN2_VGA

ISEN1_VGA

12

PR936

@

51.1K_0402_1%

@

1 2

10K_0402_1%

1 2

10K_0402_5%

PR920

1 2

PR925

100K_0402_5%

1 2

VW_VGA

0.22U_0402_16V7K
PC915

390P_0402_50V7K

FB1_VGA

1 2

PR929

2.32K_0402_1%

1 2

Rdroop

1 2

PR902 0_0402_5%

PR915

1 2

PR916

@

1.91K_0402_1%

PR918

COMP_VGA

PC938

12

VSUM-_VGA

1000P_0402_50V7K

1000P_0402_50V7K

GPU_PWR_EN19,30

2 2

DGPU_PWROK8,9

Rbias

+3VGS

VR_TT#30

6.98K_0402_1%

1 2

PR926

3 3

150P_0402_50V8J

Rth

470K_0402_5%_TSM0B474J4702RE

1 2

PH902

SL200002E00

Rfset

12

12

PR927

PC914

5.9K_0402_1%
1000P_0402_50V7K

PC916

S CER CAP 150P 50V J NPO 0402

1 2

PR933

PC919

147K_0402_1%

FB2_VGA

1 2

1 2

for positive offset

VDDC_SEN21

4 4

VDDC_RTN21

1 2

PR943 0_0402_5%

@

1 2

PR946 0_0402_5%

@

A

PR904 10K_0402_1%

GPU_VID5

GPU_VID4

DPRSLPVR_VGA-1

PSI#_VGA

RBIAS_VGA

FB_VGA

12

12

PC921

0.22U_0402_16V7K

PC928

PC933

PR906 10K_0402_1%

PR905 10K_0402_1%@

GPU_VID3

PC902

@

PU901

1

PGOOD

2

PSI#

3

RBIAS

4

VR_TT#

5

NTC

6

VW

7

COMP

8

FB

9

ISEN3

10

ISEN2

41

AGND

VSEN_VGA

PC922

0.22U_0402_16V7K

12

12

12

GPU_VID2

0.1U_0402_16V7K

PR907 10K_0402_1%@

GPU_VID1

12

40

CLK_EN#

ISEN111VSEN12RTN13ISUM-14ISUM+15VDD

@

PC930

330P_0402_50V7K

12

GPU_VID6

VRON_VGA

38

39

37

VR_ON

DPRSLPVR

RTN_VGA

ISUM-_VGA

12

B

MOSFET: dual N / 5x6 DFN
H/S Rds(on): 5mohm(Typ), 8.5mohm(Max)
Idsm: 22A@Ta=25C, 17A@Ta=70C

L/S Rds(on): 2.4mohm(Typ), 3.2mohm(Max)
Idsm: 36A@Ta=25C, 29A@Ta=70C

Vboot regulation

12

PR909 10K_0402_1%@

GPU_VID5

12

PR913 10K_0402_1%

PR911 10K_0402_1%

PR910 10K_0402_1%@

PR912 10K_0402_1%@

GPU_VID3

GPU_VID2

GPU_VID4

GPU_VID1

12

0_0402_5%

1 2

PC937

1U_0603_10V6K

PR955

12

12

12

18

GPU_VID118GPU_VID218GPU_VID318GPU_VID418GPU_VID5

35

VID031VID132VID233VID334VID536VID6

VID4

30

BOOT2

29

UGATE2

28

PHASE2

27

VSSP2

26

LGATE2

25

VCCP

24

PWM3

23

LGATE1

22

VSSP1

21

PHASE1

VIN

IMON18BOOT119UGATE1

SA00003WG00

ISL62883CHRTZ-T_TQFN40_5X5

17

16

20

VDD_VGA

PR931 0_0402_5%@

VIN_VGA

1 2

+VGA_B+

PR934

1_0402_5%

1 2

12

12

PC923

1U_0603_10V6K

+5VS

PC924

0.22U_0603_25V7K

Cn

12

12

PC931

PC932

0.033U_0402_16V7K

0.22U_0402_16V7K

w w w . c h i n a f i x . c o m

PR948
887_0402_1%

1 2

Ri

B

12

.1U_0402_16V7K

1 2

10K_0402_1%

Rp Rntcs

12

PR945

11K_0402_1%

PC934

+5VS

PR930

@

VSUM+_VGA

12

PR944

2.61K_0402_1%

NTC_VGA

12

PH901
10K_0402_1%_TSM0A103F34D1RZ

Rntc

SL200002F00

VSUM-_VGA

C

+5VS

PU902

6

7

FCCM

3

PWM

4

GND

9

TP

SA000050900

ISL6208BCRZ-T_QFN8_2X2

BOOT2_VGA

C

D

+VGA_B+

12

12

PC927

PC936

10U_0805_25V6K

1

7

D1

G1

S1/D2

S2

4

5

PHASE2_VGA

1

2

D1

G1

S2

S2

4

5

3

1

2

D1

S2

S2

4

3

Compal Secret Data

G26S2

7

S1/D2

7

G1

5

10U_0805_25V6K

G26S2

S1/D2

G26S2

Deciphered Date

7x7xH3

CR: 0.98mohm

D
Idc / Isat: 28A

PL904

0.22UH 20% PCME064T-R22MS0R985 28A

12

12

PR949

3.65K_0402_1%

ISEN3_VGAVSUM+ _VGA ISEN2_VGA

+VGA_B+

12

12

PC904

PC905

2200P_0402_50V7K

@EMI@

Rsum

PR921

VSUM+_VGA

+VGA_B+

12

10U_0805_25V6K

12

PR939

3.65K_0402_1%

VSUM+_VGA

1 2

10K_0402_1%

10U_0805_25V6K

3.65K_0402_1%

12

PR953

4.7_1206_5%

SNUB1_VGA

RF@

12

PC935

PR952

RF@

680P_0603_50V7K

PC903

0.1U_0402_25V6

@EMI@

12

PR919

RF@

4.7_1206_5%

SNUB2_VGA

12

PC910

RF@

680P_0603_50V7K

12

PC918

PC917

10U_0805_25V6K

12

PR938

4.7_1206_5%

SNUB1_VGA

RF@

12

PC929

RF@

680P_0603_50V7K

D

HG3

UGATE1VCC

PHASE

BOOT1_VGA

BOOT

LGATE

2.2_0603_5%

PR954

2.2_0603_5%

2

1 2

8

5

PR901

0_0603_5%

UGATE2_VGA

1 2

PR917

BOOT2_2_VGA

1 2

LGATE2_VGA

+5VS

12

PC913

1U_0603_10V6K

UGATE1_VGA

BOOT1_1_VGA

1 2

PR935

2.2_0603_5%

PHASE1_VGA

LGATE1_VGA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

0.22U_0603_25V7K

1 2

AON6932A 2N DFN5X6-8

SB00000XJ10

LG3

PC906

0.22U_0603_25V7K

1 2

AON6932A 2N DFN5X6-8

SB00000XJ10

PR932

0_0603_5%

1 2

1 2

PC920

0.22U_0603_25V7K

PQ901

AON6932A 2N DFN5X6-8

PC908

2

PQ903

S2

3

HG2

PQ902

HG1

SB00000XJ10

2014/03/03 2015/03/03

SH00000OY00

12

12

PR951

PR958

10K_0402_1%

10K_0402_1%

ISEN1_VGA

EMI@

FBMA-L11-201209-121LMA50T_0805

1 2

EMI@

FBMA-L11-201209-121LMA50T_0805

1 2

12

PC901

0.22UH 20% PCME064T-R22MS0R985 28A

12

PL902

0.22UH 20% PCME064T-R22MS0R985 28A

12

ISEN1_VGA

FBMA-L11-201209-121LMA50T_0805

12

1 2

EMI@

10U_0805_25V6K

PL903

SH00000OY00

1 2

12

PR922

10K_0402_1%

ISEN2_VGA

1 2

PR940

ISEN1_VGA

SH00000OY00

12

PR941

10K_0402_1%

10K_0402_1%

ISEN2_VGA

Title

S

ize Document Number Rev

Date: Sheet of

E

+VGA_CORE

1

+

PC926

12

2

PR950

1_0402_1%

SGA20331E10

12

PR957

12

PR942

VSUM-_VGA

12

10K_0402_1%

VSUM-_VGA

1_0402_1%

330U 2V D2 LESR9M EEFSX H1.9

B+

Venus / XTX (45W)
Maximum Current: 52A
Peck Current: 78A
OCP setting: 93.6A
Frquency: 450KHz
Load line: 1.5mV/A

Ro

PR924

1_0402_1%

+VGA_CORE

1

+

PC907

2

SGA20331E10

330U 2V D2 LESR9M EEFSX H1.9

VSUM-_VGA

PL901

12

PR923

PR956

10K_0402_1%

ISEN3_VGA

PL905

PL906

10K_0402_1%

ISEN3_VGA

12

Compal Electronics, Inc.

ISL62883C

E

+VGA_CORE

1

+

PC925

2

SGA20331E10

330U 2V D2 LESR9M EEFSX H1.9

45 52Tuesday, March 04, 2014

1.0

5

D D

4

3

2

1

PC1102

1 2

PC1101

1000P_0402_50V7K

1 2

PR1106

97.6K_0402_1%

1 2

1 2

27.4K_0402_1%

1 2

12

12

PR1113

5.9K_0402_1%

12

6800P_0402_25V7K

Follow intel guideline

PR1101

@

1.91K_0402_1%

1 2

PH1101

SL200002E00

PR1111

33P_0402_50V8J

PC1112

PR1122

@

1.5K_0402_1%

1 2

PR1110

1 2

3.83K_0402_1%

12

@

12

@

PC1118

@

1 2

330P_0402_50V7K

PC1120

1 2

0.01U_0402_50V7K

PR1102

1 2

130_0402_1%

PR1103

1 2

54.9_0402_1%

VR_ON

IMON

VR_HOT_1#

NTC

COMP

12

PR1114

2K_0402_1%

12

PC1114

330P_0402_50V7K

w w w . c h i n a f i x . c o m

Local sense put on HW site

4

EMI@

PL1103

FBMA-L11-201209-121LMA50T_0805

1 2

EMI@

PL1101

FBMA-L11-201209-121LMA50T_0805

1 2

PR1104

90.9K_0402_1%

1 2

VR_SVID_DAT

VR_SVID_ALRT#

VR_SVID_CLK

20

21

PU1101

PAD

SCLK

1

VR_ON

2

PGOOD

3

IMON

ISL95813HRZ-T_QFN20_3X4

4

VR_HOT#

SA000073100

5

NTC

6

COMP

FB7RTN8ISUMN9ISUMP

FB

12

PR1115

@

10_0402_1%

PR1116

1.27K_0402_1%

Droop

PC1115

@

390P_0402_50V7K

PRGM1

19

17

18

SDA

PRGM1

ALERT#

ISUMN

10

ISUMP

LGATE

PHASE

UGATE

BOOT

PRGM2

VCC

16

15

14

13

12

11

OCP Setting

12

PC1119

@

0.082U_0402_16V7K

1 2

422_0402_1%

PC1121

@

1 2

4700P_0402_25V7K

12

PR1120

@

1 2

1.5K_0402_1%

LAGTE

PHASE

UAGTE

BOOT

PRGM2

PR1112

PR1117

PR1121

PR1108

2.2_0603_5%

1 2

12

124K_0402_1%

4.99M_0402_1%

Note:
PR1104=169K
=>Icc(max)=32A
fsw=700KHz

PC1108

0.22U_0603_16V7K

1 2

+5VS

12

PC1111

0.1U_0402_25V6

Note:
PR1112=124K
=>Slew rate=53mV/us
Vboot = 1.7V

RC Match

12

PC1116

0.022U_0402_25V7K

3

PR1105

0_0603_5%

1 2

12

PC1117

0.1U_0402_16V4Z

PQ1101

SB00000XJ10

AON6932A 2N DFN5X6-8

12

PR1119
11K_0402_1%

CPU_B+

2

1

7

D1

G1

S1/D2

S2

S2

4

5

3

12

PR1118

4.42K_0402_1%

12

PH1102
10KB_0402_5%_ERTJ0ER103J

SL200002F00

12

PC1104

PC1103

10U_0805_25V6K

10U_0805_25V6K

G26S2

2

CPU_B+

PC1107

SF000005200

12

12

12

PC1105

PC1106

0.01U_0402_50V7K

2200P_0402_50V7K

@EMI@

@EMI@

12

PR1107

RF@

12

PC1110

RF@

7x7xH3
DCR: 0.66mohm
Idc: 36A
Isat: 45A

PL1102

12

PR1109

3.65K_0603_1%

123

SH00000OY00

1 2

BE_BDW

1

0.22UH 20% PCME064T-R15MS0R667 36A

4.7_1206_5%

680P_0603_50V7K

Title

ISL95813 for BDW-Y&U(15W/28W) CPU

Size Document Number Rev

Date: Sheet

intel Shark Bay ULT 15W
TDC 10A
TDC 14A at PL2 for 40S
Peak Current: 32A
OCP current: 38.5A
Frequency: 750KHz
Load line -2.0mV/A

CPU_B+B+

1

+

2

33U_25V_M

+CPU_CORE

46 52Tuesday, March 04, 2014

of

1.0

+1.05VS

1U_0402_6.3V6K

Note:
VR_SVID_ALRT# Pull high on HW side

C C

VR_SVID_DAT11

VR_SVID_ALRT#11

VR_SVID_CLK11

VR_ON11

+1.05VS

VGATE11

Note:
VR_HOT# Pull high on HW side

VR_HOT#30

Over temperature protection:
OTP Setting: 100C active

B B

Pin5 (NTC) voltage <0.88V, Protect
Pin5 (NTC) voltage >0.92v, recovery

A A

5

470K_0402_5%_ TSM0B474J4702RE

12

PC1109

47P_0402_50V8J

PC1113

VCCSENSE11

VSSSENSE11,13

5

4

3

2

1

+VGA_CORE

+CPU_CORE

22u 0603 *22/ @*2

D D

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

PC1303

PC1302

PC1301

12

12

22U_0603_6.3V6M

22U_0603_6.3V6M

PC1311

12

C C

22U_0603_6.3V6M

12

PC1312

12

22U_0603_6.3V6M

@

@

PC1323

PC1327

12

12

12

22U_0603_6.3V6M

PC1313

12

12

22U_0603_6.3V6M

PC1304

PC1305

12

12

22U_0603_6.3V6M

22U_0603_6.3V6M

PC1315

PC1314

12

12

22U_0603_6.3V6M

22U_0603_6.3V6M

PC1307

PC1306

12

12

22U_0603_6.3V6M

22U_0603_6.3V6M

PC1316

PC1317

12

12

22U_0603_6.3V6M

22U_0603_6.3V6M

PC1308

12

22U_0603_6.3V6M

PC1318

12

22U_0603_6.3V6M

PC1309

PC1310

12

22U_0603_6.3V6M

22U_0603_6.3V6M

PC1320

PC1319

12

1

1

PC966

1U_0402_6.3V6K

PC974

1U_0402_6.3V6K

PC983

1U_0402_6.3V6K

PC993

10U_0603_6.3V6M

1

PC967

2

1U_0402_6.3V6K

1

PC975

2

1U_0402_6.3V6K

1

PC984

2

1U_0402_6.3V6K

1

PC994

2

10U_0603_6.3V6M

PC969

PC968

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

PC976

PC977

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

PC985

PC986

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

PC961

PC995

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

1

PC971

PC970

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

1

PC998

PC978

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

1

PC988

PC987

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

1

PC1001

PC1000

2

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

PC973

PC972

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

PC980

PC979

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

PC989

PC990

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

PC962

PC999

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

PC997

PC996

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

1

PC981

PC982

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

1

PC992

PC991

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

PC963

2

2

10U_0603_6.3V6M

B B

A A

w w w . c h i n a f i x . c o m

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/03/03 2015/03/03

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PWR-PROCESSOR_DECOUPLING

Size Document Num ber Rev

Custom

2

Date: Sheet

BE_BDW

of

47 52Tuesday, March 04, 20 14

1

1.0

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 1

for PWR

Reason for change PG# Modify List Date PhaseItem

1

D D

2

3

link with HW side

modify VCORE setting

for RF request

change net name +3VS_VGA or +3VGS45 11/15 SIV

1. Change the PR1120 from 280 Ohm to 287 Ohm.

46

2. Change the PR1117 from @ to 4.99MOhm.

3. Change the PR1118 from 2.61kOhm to 4.42kOhm.

4. Change the PC1101 from @ to 1000pF.

5. Change the PR1106 from @ to 97.5kOhm.

6. Change the PR1114 from 2kOhm to @.

7. Change the PC1114 from 330pF to @.

45

PR953, PC935, PR919, PC910, PR938, PC929 change to mount 11/19 SIV

11/15 SIV

4

5

6

C C

7

8

9

10

B B

11

SIV MEMO

Valure modify

AC detect valure setting

for EMI request 38 12/24 SIT

battery can't be remove del PC206, PD201, PC205, PR307, PQ306, PQ313

modify VCORE setting

modify VCORE setting

PR1101 change to NA

46

PC916 change to 150p

45

PR309 is changed from 392K_0402_1% to 124K_0402_1% (SD034124380)
PR312 is changed from 59K_0402_1% to 20K_0402_1% (SD034200280)

38

Add a resistor 249K_0402_1% (SD034249380) between pin 6 of PU301 and PACIN.
PC312 is changed from 2200pF_0402_25V_X7R to 0.01uF_0402_25V_X7R (SE075103K80)

Add 2caps to GND, Add 1 SNUB
(PC320=0603 680pF, PR319=1206 4.7ohm, PC306=0.1uF, PC307=2200pF)

Change PR1120 to 422ohm.
Change PR1104 to 90.9Kohm.

47 Add PC1320 22uF.

11/19 SIV46for RF request PR1107, PC1110 change to mount

12/24

12/24

12/24

SIT

SIT

SIT

12/24 SIT37

02/20 SVT46

02/20 SVT

A A

w w w . c h i n a f i x . c o m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

2014/03/03 2015/03/03

3

Compal Secret Data

Deciphered Date

Title

Size D ocument Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

PIR (PWR)

LA-B131P

48 52Tuesday, March 04, 2014

1

1.0

of

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 4

for HW

Reason for change PG# Modify List Date PhaseItem

1

D D

2

3

4

5

EMI recommend 27

EMI recommend 32 Change D21 from SC300001G00 to SC300001J00

HW design

6

7

HW design

8

10

11

12

13

14

9

HW design

Vendor recommend

HW design 06

HW design

HW design

C C

15

16

B B

17

18

19

HW design Add PCH_GPIO87 to JEDP1.725

HW design 27 Change R156 to short pad

EMI recommend 27 Add RA13 for EMI@

20

21

22

23

24

A A

25

26

HW design 30

HW design Change R243 to short pad31

HW design 33 Change R253 to short pad

HW design 35 Change R630 to short pad

EMI recommend 28 Add C323,C326,C327,C328,C329,C330,C331,C332 for @EMI@

HW design 32 Add R249,R250

w w w . c h i n a f i x . c o m

Change U9J.P1 from PCH_GPIO76 to DDI2_HDMI_HPD09 10/02 SIVHW design

26 Change D5, D6 from SC300001G00 to SC300001J00

Change D5, D6 from @EMI@ to EMI@

Change RA12 from SD028000080 to SM01000DF00

Change C254 from SE071220J80 to SE074221K80

Change C254 from @EMI@ to EMI@

07

Change C20 to @

Remove R201

11 Change C41, C45 to @HW design

Change C97,C119,C113,C115,C116 to @

Change C93,C94,C96,C98,C99,C100 to @15

Change C124,C126,C127,C128,C129,C131 to @

16HW design

Change C149,C143,C144,C147 to @

Change CV9 to @DIS@17HW design

25 Change C214 to @

Remove R722,R721

34 Change CL29 form 15p to 12p

Change R17,R21 to short pad

Change R24,R25,R26,R27 to RP31

07

Change R31,R33,R32,R55 to RP32

15 Change R101,R102 to short pad

16 Change R111,R112 to short padHW design

Remove RV17

18HW design

Move GPU_GPIO1 to RP19.7

Add CA12 for @EMI@

29 Change R217,R218,R257,R222,R199,R226 to short padHW design

Change R273,R274,R268 to short pad

Remove R266,R276,R214,R272

Move USB_CHG_EN#, USB_EN#, FAN_SPEED2, FAN_SPEED1 to RP33

10/29 SIVEMI recommend

10/29

10/29

11/06

11/06

11/06

11/06

11/06

11/06

11/06

11/07

11/07

11/07

11/07

11/07

11/07

11/07

11/07

11/07

11/07

11/07

11/07

11/07

11/07

11/10

SIV

SIV

SIV

SIV

SIV

SIV

SIV

SIV

SIV

SIV

SIV

SIV

SIV

SIV

SIV

SIV

SIV

SIV

SIV

SIV

SIV

SIV

SIV

SIV

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

2014/03/03 2015/03/03

3

Compal Secret Data

Deciphered Date

Title

Size D ocument Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

HW-PIR

BE_BDW

49 52Tuesday, March 04, 2014

1

1.0

of

5

4

3

2

1

Version change list (P.I.R. List) Page 2 of 4

for HW

Reason for change PG# Modify List Date PhaseItem

27

D D

28

29

30

31

32

33

HW design 07

EMI recommend 27 Add CA13 close to UA1 11/11

HW design Change USB_CHG_EN# to USB_CHG_EN

34

C C

35

36

37

38

39
40

41

42

43

B B

44

45

HW design 25 Remove JP5 11/15 SIV

Busyer suggestion 19 Change QV5 from SB000007H10 to SB00000QP00

Busyer suggestion

Busyer suggestion

HW design 32 swap D21 (Pin1=>Pin9, Pin3=>Pin1, Pin7=>Pin3, Pin9=>Pin7)

EMI recommend Change TS1 from SP050006F00 to SP050006800 11/20

EMI recommend

EMI recommend

EMI recommend

EMI recommend

EMI recommend

Change PCH_GPIO85 to PCH_USB_EN#09 11/10 SIVHW design

18 Add RV13 for THM_ALERT#HW design

Change JHDMI1 footprint to SINGA_2HE1638-012212F_19P-T28ME recommend

Change C59,C62,C66,C70,C75 from SE00000O000 to SE00000PL00

12HW design

Add C37,C138,C333@,C334,C335 SE00000PL00

RP31.1 & RP31.3 swap RP31.2 & RP31.4 swap => modify RP31 symbol

RP32.1 & RP32.2 swap RP32.3 & RP32.4 swap

30
32

Remove DGPU_PWR_EN, DGPU_HOLD_RST#

Change PCH_GPIO18 from RP10.5 to RP5.8

09HW design

Change PCH_GPIO23 from RP10.6 to RP28.5

Remove RP10

2130Change LV6, LV7 from SM01000BZ00 to SM01000FF00

Change L13,L14 from SM010016810 to SM01000LP00

26

25

Change CA12 from 2.2u to 220P

Change RA3 from 45.1 to 10.6

27

Change CA13 from 2.2u to 220P

28

Change C323,C326,C327,C328,C329,C330,C331,C332 from 0.1u to 2.2P

32

Change D16, D17 from ESD@ to @ESD@

Change D19 from ESD@ to @ESD@

33

Change D20 from @ESD@ to ESD@

11/10

11/10

11/10

SIV

SIV

SIV

11/10 SIV

SIV

11/11

SIV

11/12 SIV

11/15

11/15

11/15

SIV

SIV

SIV

11/18 SIV

SIV

12/02

12/02

12/02

12/02

12/02

SIV

SIV

SIV

SIV

SIV

A A

w w w . c h i n a f i x . c o m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

2014/03/03 2015/03/03

3

Compal Secret Data

Deciphered Date

Title

Size D ocument Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

HW-PIR

LA-B131P

50 52Tuesday, March 04, 2014

1

1.0

of

5

4

3

2

1

Version change list (P.I.R. List) Page 3 of 4

for HW

Reason for change PG# Modify List Date PhaseItem

1

D D

2

3

4

5

HW design

6

C C

7

8

HW design

HW design

9

10

37

38

HW design

HW design

HW design

39
40

41

B B

42

43

44

45

46
47
48
49
50
51
52
53

A A

54

55

56

5

HW design

HW design

HW design

HW design

EMI recommend

HW design

Busyer suggestion

Busyer suggestion

Busyer suggestion

Busyer suggestion

HW design 27 Change RA2, RA10 to short pad 12/24 SIT

EMI recommend

HW design

HW design

HW design

w w w . c h i n a f i x . c o m

HW design 25 Change L24 from EMI@ to @EMI@ 12/25 SIT

4

Add R266(@) 100K pull-high to +3VLP for NOVO#33 12/05 SITHW design

29 Add NET: DEW1_TI / DEW2_TIHW design

Add R276 10K pull-high to +3VS for DGPU_PWR_EN09HW design

Change R186, R193 from @ to TI@29Vendor recommend

Change +12VS_Panel to B+

Add JP5

25

Add RP10

Change R213 to short pad

Change R267 to @

Change net name from USB_EN# to USB1_EN#

30HW design

Add USB2_EN# to U26.89

Add R277 (10K) pull-high +5VALW

Change R270 to short pad

Change net name from USB_EN# to USB1_EN# by U29.4

Change net name from USB_EN# to USB2_EN# by U30.4

32

Delete R249, R250

Change PCH_USB_EN# to PCH_GPIO85

09

Delete R206 for RP10

08HW design

Change R46,R51,R53 to short pad

Change R34, R35, R39, R40 to short pad07

Change R79 to short pad

11

Change R88, R98 to short pad

15

Change R104 to short pad16HW design

18

19

Change RV45 to short pad

20

Change RV46, RV50, RV52, RV55, RV57, RV51 to short pad

Delete Q5, Q7

28

Add Q5A, Q5B

32

Change C306, C307 from 0.1u to100P

33

Change R230 from 300 ohm to 649 ohm

(X1 code) Change LV10, LV13 from SM01000BL00 to SM01000GG00

21

(X1 code) Change U11 from SA00006QR00 to SA741080400

08

(X1 code) Change U33 from SA00006QR00 to SA741080400

25

(X1 code) Change U27 from SA00006QR00 to SA741080400

30

Change RA12 from 120 ohm(SM01000DF00) to 300 ohm (SM01000I000)EMI recommend 27

3030Change C286, C287, C289, C291 from @ to EMI@

Change R260, R223 to short pad

Change R228, R229 to short pad

31

Change R260, R223 to short pad

19

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

2014/03/03 2015/03/03

3

Compal Secret Data

Deciphered Date

12/09

12/19

12/20

12/20

12/20

12/20

SIT

SIT

SIT

SITDelete R215, R504, R148 for RP10

SIT

SIT

SIT12/20Delete R252,R262

SIT12/20

12/20

12/20

12/20

SIT

SIT

SIT

SIT12/20

12/20Change RV44,RV32 to short pad

12/20

12/20

12/20

12/20

12/23

12/23

12/23

12/23

12/24

12/24

12/24

SIT

SIT

SIT

SIT

SIT

SIT

SIT

SIT

SIT

SIT

SIT

SIT

SIT12/24

12/24 SIT

12/25 SIT

Title

Size D ocument Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

HW-PIR

LA-B131P

51 52Tuesday, March 04, 2014

1

1.0

of

5

4

3

2

1

Version change list (P.I.R. List) Page 4 of 4

for HW

Reason for change PG# Modify List Date PhaseItem

57

D D

58

59

60

61
62
63
64
65

66

67
68
69

1
2

C C

3

HW design

HW design

HW design

HW design

HW design

HW design 12

HW design

HW design

4

5

6

7

DFx recommend

Busyer suggestion

HW design

8
9

10

11

12

B B

13

14

15

16

17

18

19

20
21

22

23

A A

24
25

HW design

HW design

HW design

HW design

HW design

HW design

HW design 30

HW design

HW design

HW design 25 Add R148 02/19 SVT

HW design 30 Delete net: BATT_LEN# 02/20 SVT

HW design

HW design

EMI recommend

Busyer suggestion 19 Change Q139 from SB000003W00 to SB00000ZN00 02/21 SVT

Vendor recommend

DFx recommend 32 Change C346@ to C346 02/26 SVT

w w w . c h i n a f i x . c o m

Change R275 to @29 12/27 SITHW design

28 Change C323, C326, C327, C328, C329, C330, C331, C332 from @EMI@ to EMI@HW design

Change R230 from 649 ohm 5% to 649 ohm 1%.31HW design

Change LV10, LV13 from SM01000GG00 to SM01000I300.21Vendor recommend

12

Change C59, C138, C66, C334, C75 from 47uF to 22uF

15

Change C89, R90, C107, R100 to @

16

Change R1456 to short pad

25

Change C225, C226 to @

Change L6 from SM010014520 to SD002000080 (0 ohm) and change location to R2

31

Change C300, C303 to @

Change R256 to short pad

Change C37, C62, C70, C335 to @

25

19

Change location C989 to R830

28

Change C327, C328, C329, C330, C331, C332, C323, C326 from EMI@ to @EMI@

Add U1(LDO), C344, C343

32

Add C345, C346

21

Change LV10, LV13 from SM01000I300 to SM01000F100

Add R249, R250

27

Change C253 from 1uF_0402 tp 1uF_0603

Change RG3 to short pad

06HW design

07

Change RG9, R38 to short pad

25

Change R2 to short pad

18

Change RV187 to short pad

Change R185 to short pad

27

Change R155, R157, R158 to short pad

26

Change RG6 to short pad

Change R225 to short pad

Change RV25 from 100K to 1K

18

Change RP21, PR22 from 680 ohm to 470 ohm

28

1918Change R829 from 470 ohm to 10 ohm

Change RV187 from short pad to 0 ohm

Change R164, R165, R166, R167 from 0 ohm to short pad

27

Change R196, R197, R198, R173 from 0 ohm to short pad SVT

Add RG2

34

Change RG5 from 10 ohm to 0 ohm 02/24 SVT

12/27

12/31

01/03

01/07

01/07

01/07

01/07

01/07

01/0733HW design

01/03

01/12

01/12

01/22

01/22

01/22

01/22

01/22

01/22

01/22

01/22

01/22

01/22

02/10

02/12

02/21

02/21

02/21

SIT

SIT

SIT

SIT

SIT

SITChange C120, R106 to @

SIT

SIT

SIT

SIT

SVTChange location L6 to R2

SVT

SVT01/14EMI recommend

SVT01/2027HW design

SVT

SVT

SVT

SVT01/22

SVT

SVT

SVT

SVT29

SVT

SVT

SVT

SVT

SVT

SVT

SVT

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

2014/03/03 2015/03/03

3

Compal Secret Data

Deciphered Date

Title

Size D ocument Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

HW-PIR

LA-B131P

52 52Tuesday, March 04, 2014

1

1.0

of