Compal LA-B015P ZAVA1, Inspiron 14 5000, Inspiron 15 5000, LA-B015P ZAVC1 Schematic

5

4

3

2

1

MODEL NAME : ZAVA1/ZAVC1
PCB NO : DA80011D000 LA-B015P-R1.0

D D

C C

Schematic Document

Intel BoardWell ULT

B B

A A

5

ZAVA1/ZAVC1
DIS AMD 25W/M2+DDR3x8

2014-10-17 Rev: 1.0

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/10/17 2018/04/30

2014/10/17 2018/04/30

2014/10/17 2018/04/30

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Cover Page

Cover Page

Cover Page
LA-B015P

LA-B015P

LA-B015P

1

of

of

of

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1 56Friday, October 17, 2014

1.0

1.0

1.0

5

4

3

2

1

D D

C C

B B

AMD OPAL_128bit_4GB

VRAM 256M*16
DDR 3 *4

VRAM 256M*16
DDR 3 *4

Page 53~5

4

Page 55~5

6

eDP Conn.

HDMI Conn.

Page 31

Page 20

NGFF 2230
WiFi/WiGi RTL8106E
/BT4.0

SATA HDD Conn.

64bit

AMD_OPAL
M2 29x29mm

64bit

Page 47~5

PCI-E

x1 x1

Port 6 Port 3

Page 26

Page 32

Ethernet

Port 0

PEG 2.0 x4

2

Page 21

SATA Rediver

Page 32

eDP

DDI

SATA3.0

Intel
Broadwell ULT-U
Processor
BGA 1168

Memory Bus (DDR3L)

Dual Channel

1.35V DDR3L 1600 MHz

USB 3.0

USB2.0

Port 4

Port 7

Port 5

Port 6

DDRIII-DIMM X2

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7

8GB Max

NGFF 2230
WiFi/WiGi/BT4.0

Digital Camera
(With Digital MIC)

Touch Screen

Card Reader
RTS5179

Page 17,1

Page 26

Page 31

Page 31

Page 25

8

Port 1

Port 0

Port 2

Port 1

Port 2

Port 4

Digital Mic.

USB 3.0 Conn. 1

USB 3.0 Conn. 2

USB 2.0 Conn. 3

USB3.0 Re-driver

Page 46

Page 24

Page 24

Page 25

3D Camera Conn.

Page 46

HD Audio

SPI ROM

8MB

A A

5

4

SPI

Page

9

Int.KBD Touch Pad

Page 27

ENE KBC
KB9012

Page 6~16

LPC Bus

33MHz

Page 30

I2C

PS/2

Page 27

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Audio Codec
ALC3234

2014/10/17 2018/04/30

2014/10/17 2018/04/30

2014/10/17 2018/04/30

Page 22

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Headphone Jack /
Mic. Jack combo

Int. Speaker R / L

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Block Diagram

Block Diagram

Block Diagram
LA-B015P

LA-B015P

LA-B015P

Page 22

Page 22

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2 56Friday, October 17, 2014

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1

Compal Confidential
File Name : LA-B015P

D D

C C

USB

FFC
16 pin

RJ45

CardReader Slot

HDMI

USB

CardReader/B

USB

B B

Audio Jack

FFC
8 pin

M/B

# 3D Camera Conn. (@ BOT)
Cable conbined by eDP cable

LED/B

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2014/10/17 2018/04/30

2014/10/17 2018/04/30

2014/10/17 2018/04/30

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

MB/DB Drawing

MB/DB Drawing

MB/DB Drawing
LA-B015P

LA-B015P

LA-B015P

1

1.0

1.0

3 56Friday, October 17, 2014

3 56Friday, October 17, 2014

3 56Friday, October 17, 2014

1.0

5

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3

2

1

Board ID Table for AD channel

Vcc 3.3V +/- 1%
Ra

Board ID

0
1

D D

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

C C

B B

18
19

SMBUS Control Table

EC_SMB_CK1
EC_SMB_DA1

EC_SMB_CK2
EC_SMB_DA2

SMBCLK
SMBDATA

SML0CLK
SML0DATA

SML1CLK
SML1DATA

100K +/- 1%

Rb V min

AD_BID

0 0.000V
12K +/- 1%
15K +/- 1%
20K +/- 1%
27K +/- 1%
33K +/- 1%
43K +/- 1%
56K +/- 1%

0.347V

0.423V 0.430V

0.541V

0.691V

0.807V

0.978V 0.992V

1.169V
75K +/- 1% 1.398V
100K +/- 1%

1.634V

1.849V 1.865V
160K +/- 1%
200K +/- 1%
240K +/- 1%
270K +/- 1%
330K +/- 1%
430K +/- 1%
560K +/- 1%
750K +/- 1%

2.015V

2.185V

2.316V

2.395V 2.408V

2.521V

2.667V

2.791V

2.905V 2.912V
NC

BATT

V

Charger

V

SOURCE

KB9012

KB9012

ULT

ULT

ULT

V typ

AD_BID

V

AD_BID

max

0.000V 0.300V

0.354V

0.360V

0.438V

0.550V

0.702V

0.819V

0.559V

0.713V

0.831V

1.006V

1.185V

1.200V

1.414V 1.430V

1.650V

1.667V

1.881V130K +/- 1%

2.031V

2.200V

2.329V

2.046V

2.215V

2.343V

2.421V

2.533V

2.677V 0xCA - 0xD3

2.800V

2.544V

2.687V

2.808V

2.919V

3.300V

FFS

V

V

V

3.300V

DIMMVGA

V

XDP

Thermal Sensor

EC AD3

0x00 - 0x0B
0x0C - 0x1C
0x1D - 0x26
0x27 - 0x30
0x31 - 0x3B
0x3C - 0x46
0x47 - 0x54
0x55 - 0x64
0x65 - 0x76
0x77 - 0x87
0x88 - 0x96
0x97 - 0xA3
0xA4 - 0xAD
0xAE - 0xB7
0xB8 - 0xC0
0xC1 - 0xC9

0xD4 - 0xDC
0xDD - 0xE6
0xE7 - 0xFF3.000V

HSW BOARD ID Table

Board ID

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

BDW BOARD ID Table

Board ID

0
1
2
3
4
5
6
7
8
9

Link

10
11
12
13
14
15
16
17
18

1.0(BDW)

UMA

SSI

PT

ST

1.0

UMA

1.0_3D CAM

SSI(BDW)

PT(BDW)

SSI_3D CAM

ST(BDW)

PT_3D CAM

ST_3D CAM

DIS(JET) DIS(Topaz)

SSI

SSI

PT

PT

ST

ST

1.0

1.0

DIS(JET) DIS(Topaz)

1.0_3D CAM

SSI(BDW)

PT(BDW)

SSI_3D CAM

ST(BDW)

PT_3D CAM

1.0(BDW)

ST_3D CAM

1.0_3D CAM

SSI(BDW)

PT(BDW)

SSI_3D CAM

ST(BDW)

PT_3D CAM

1.0(BDW)

ST_3D CAM

DIS(OPAL)

DIS(OPAL)

SSI
PT
ST

1.0

ULT

Port1
Port2
Port3
Port4

Port0
Port1
Port2
Port3
Port4
Port5
Port6
Port7

Lane 1
Lane 2
Lane 3
Lane 4
Lane 5

USB3.0

USB connector 1
USB connector 2

3D Camera

USB2.0

USB connector 1
USB connector 2
USB connector 3 (D/B)

MINI Card (WLAN)
Touch Screen Panel
Card Reader
Camera

PCI EXPRESS

10/100 LAN
MINI Card (WLAN)
PEG (AMD JET/TOBAZ)

CLOCK SIGNAL ( Diff. 100MHz )

Symbol Note :

: means Digital Ground

: means Analog Ground

A A

CLKOUT_PCIE0
CLKOUT_PCIE1
CLKOUT_PCIE2
CLKOUT_PCIE3
CLKOUT_PCIE4

10/100 LAN
MINI Card (WLAN)
dGPU

Lane 6

SATA

HDDSATA0
SATA1
SATA2
SATA3

CLKOUT_PCIE5

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2014/10/17 2018/04/30

2014/10/17 2018/04/30

2014/10/17 2018/04/30

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

ID Table / Function Map

ID Table / Function Map

ID Table / Function Map
LA-B015P

LA-B015P

LA-B015P

1

1.0

1.0

4 56Friday, October 17, 2014

4 56Friday, October 17, 2014

4 56Friday, October 17, 2014

1.0

5

4

3

2

1

SMBUS Address [0x9a]

D D

MCH
Shark bay

C C

AP2
AH1

AN1
AK1

AN1
AK1

MEM_SMBCLK
MEM_SMBDATA

SML0CLK
SML0DATA

SML1_SMBCLK
SML1_SMBDATA

79

EC_SMB_CK2

80

EC_SMB_DA2

2.2K

2.2K

1K

1K

2.2K

2.2K

+3.3V_ALW_PCH

+3.3V_ALW_PCH

+3.3V_ALW_PCH

2.2K

2.2K

N-MOS
N-MOS

N-MOS
N-MOS

+3VALW

EC_SMB_CK2
EC_SMB_DA2

10K

10K

DDR_XDP_WLAN_TP_SMBCLK
DDR_XDP_WLAN_TP_SMBDAT

+3VS

0 ohm
0 ohm

DDR_XDP_SMBCLK_R1
DDR_XDP_SMBDAT_R1

202

DIMM1

200

202

DIMM2

200

53
51

XDP1

SMBUS Address [A0]

SMBUS Address [A4]

SMBUS Address [TBD]

2.2K

N-MOS
N-MOS

2.2K

VGA_SMB_CK2
VGA_SMB_DA2

+3VS_VGA

T4
T3

UV28 GPU

SMBUS Address [0xXX]

2.2K

2.2K

77

B B

KBC

78

EC_SMB_CK1
EC_SMB_DA1

KB9012A4

+3VALW

0 ohm
0 ohm

100 ohm
100 ohm

SCL
SDA

11
10

3
1

PD1

POWERPU701

SMBUS Address [0x12]

Charger

4

BAT_ALERT

6 5

BATT_PRS

3

PBATT

SMBUS Address [0x16]

BATT
CONN

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/10/17 2018/04/30

2014/10/17 2018/04/30

2014/10/17 2018/04/30

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SMBus/I2C Connection Map

SMBus/I2C Connection Map

SMBus/I2C Connection Map
LA-B015P

LA-B015P

LA-B015P

1

5 56Friday, October 17, 2014

5 56Friday, October 17, 2014

5 56Friday, October 17, 2014

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1.0

1.0

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BDW_Pre-QS for DVT2 BDW_QS for DVT2

i3 CPU

i3 CPU

4

3

2

1

UC1A

D D

i5 CPU

UC1

I5_1.2G@

CL8065801674128 QG21 C0 1.2G

SA00007OS0L

i7 CPU

UC1

I7_1.2G@

CL8065801675027 QG22 C0 1.2G

SA00007OT0L

i5 CPU

UC1

I5_2.2G@

FH8065801620204 QH3G F0 2.2G

SA00008990L

i7 CPU

UC1

I7_2.4G@

FH8065801620004 QH3E F0 2.4G

SA000089A0L

DDI1_LANE_N0<20>
DDI1_LANE_P0<20>
DDI1_LANE_N1<20>
DDI1_LANE_P1<20>
DDI1_LANE_N2<20>
DDI1_LANE_P2<20>
DDI1_LANE_N3<20>
DDI1_LANE_P3<20>

DDI1_LANE_N0
DDI1_LANE_P0
DDI1_LANE_N1
DDI1_LANE_P1
DDI1_LANE_N2
DDI1_LANE_P2
DDI1_LANE_N3
DDI1_LANE_P3

C54

DDI1_TXN0

C55

DDI1_TXP0

B58

DDI1_TXN1

C58

DDI1_TXP1

B55

DDI1_TXN2

A55

DDI1_TXP2

A57

DDI1_TXN3

B57

DDI1_TXP3

C51

DDI2_TXN0

C50

DDI2_TXP0

C53

DDI2_TXN1

B54

DDI2_TXP1

C49

DDI2_TXN2

B50

DDI2_TXP2

A53

DDI2_TXN3

B53

DDI2_TXP3

@

HASWELL_MCP_E

DDI EDP

1 OF 19

EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1

EDP_TXN2
EDP_TXP2
EDP_TXN3

EDP_TXP3

EDP_AUXN
EDP_AUXP

EDP_RCOMP

EDP_DISP_UTIL

Rev1p2

C45
B46
A47
B47

C47
C46
A49
B49

A45
B45

D20
A43

EDP_COMP
EDP_DISP_UTIL

1 2

@

RC72
0_0402_5%

EDP_TX0# <31>
EDP_TX0 <31>
EDP_TX1# <31>
EDP_TX1 <31>

EDP_AUX# <31>
EDP_AUX <31>

EDP_BIA_PWM <10,31>

COMPENSATION PU FOR eDP

+VCCIOA_OUT

12

CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.

RC7124.9_0402_1%~D

BDW (ES2) CPU for 3D / 4G

UC1

1.8G1600@

CL8065801703601 QGH9 D0 1.8G

SA00007U90L

C C

UC1

1.6G1333@

CL8065801703602 QGHA D0 1.6G

SA00007UG0L

+1.05VS_PCH

1 2

RC58 49.9_0402_1%@

1 2

RC60 62_0402_5%

CAD Note:

B B

Avoid stub in the PWRGD path
while placing resistors RC115

DDR3 COMPENSATION SIGNALS

CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil

UC1

1.6G1600@

CL8065801703603 QGHB D0 1.6G

SA00007UH0L

H_CATERR#
H_PROCHOT#

12

RC66
10K_0402_5%

1

CC27
100P_0402_50V8J

@EMI@

2

ESD solution

12

RC68200_0402_1%

12

RC69120_0402_1%

12

RC70100_0402_1%

H_CPUPWRGD

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

H_PROCHOT#<30,34>

H_PROCHOT#

1

@EMI@

CC42
22P_0402_50V8J

2

PECI_EC<30>

DDR3_DRAMRST#_CPU<17>

DDR_PG_CTRL<17>

H_CATERR#
PECI_EC

1 2

RC67 56_0402_5%

H_PROCHOT#_R

H_CPUPWRGD

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

D61
K61
N62

K63

C61

AU60

AV60

AU61

AV15
AV61

UC1B

PROC_DETECT
CATERR
PECI

PROCHOT

PROCPWRGD

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_DRAMRST
SM_PG_CNTL1

@

THERMAL

MISC

PWR

DDR3

HASWELL_MCP_E

2 OF 19

SYS_RESET#

SYS_RESET#

7/15
XDP_TDI & XDP_TMS add Test Point for Factory.

J62

PRDY

K62

PREQ

E60

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7

Rev1p2

XDP_TCK

E61

XDP_TMS

E59

XDP_TRST#

F63

XDP_TDI

F62

XDP_TDO

J60

XDP_OBS0_R

H60

XDP_OBS1_R

H61
H62
K59
H63
K60
J61

1 2

RC141 0_0402_1%@

T111@
T112@
T113@
T114@
T115@
T116@

1 2

R3 0_0402_5%

PCH_JTAG_RST#

JTAG

PROC_TCK
PROC_TMS

PROC_TRST

PROC_TDI

PROC_TDO

SYS_RESET# <10>

12

+3VS

RC362
1K_0402_1%

1 2

CC17

0.1U_0402_10V7K

PCH_JTAG_RST# <8>

XDP_TDO
XDP_TCK
XDP_TRST#

1 8
2 7
3 6
4 5

RP45
51_8P4R_5%

PU/PD for JTAG signals

+1.05VS_PCH

DDR3_DRAMRST#_CPU

0.047U_0402_16V4Z

Place CC35
on BOT

A A

5

1

CC35

@ESD@

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2014/04/01 2015/04/30

2014/04/01 2015/04/30

2014/04/01 2015/04/30

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

MCP(1,2/19) eDP,XDP,MISC

MCP(1,2/19) eDP,XDP,MISC

MCP(1,2/19) eDP,XDP,MISC

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

LA-B015P

LA-B015P

LA-B015P

Date: Sheet

Date: Sheet

Date: Sheet

1

6 56Friday, October 17, 2014

6 56Friday, October 17, 2014

6 56Friday, October 17, 2014

of

of

of

0.1

0.1

0.1

5

Interleaved Memory

4

3

2

1

HASWELL_MCP_E

DDR CHANNEL B

SB_CK#0

SB_CK0

SB_CK#1

SB_CK1

SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3

SB_CS#0
SB_CS#1

SB_ODT0

SB_RAS

SB_WE

SB_CAS

SB_BA0
SB_BA1
SB_BA2

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8

SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15

SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7

SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7

AM38
AN38
AK38
AL38

AY49
AU50
AW49
AV50

AM32
AK32

AL32
AM35

AK35
AM33

AL35
AM36
AU49

AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46

AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18

AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18

M_CLK_DDR#2
M_CLK_DDR2
M_CLK_DDR#3
M_CLK_DDR3

DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

DDR_B_RAS#
DDR_B_WE#
DDR_B_CAS#

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

DDR_A_DQS#4
DDR_A_DQS#5
DDR_B_DQS#4
DDR_B_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_B_DQS#6
DDR_B_DQS#7

DDR_A_DQS4
DDR_A_DQS5
DDR_B_DQS4
DDR_B_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_B_DQS6
DDR_B_DQS7

M_CLK_DDR#2 <18>
M_CLK_DDR2 <18>
M_CLK_DDR#3 <18>
M_CLK_DDR3 <18>

DDR_CKE2_DIMMB <18>
DDR_CKE3_DIMMB <18>

DDR_CS2_DIMMB# <18>
DDR_CS3_DIMMB# <18>

DDR_B_RAS# <18>
DDR_B_WE# <18>
DDR_B_CAS# <18>

DDR_B_BS0 <18>
DDR_B_BS1 <18>
DDR_B_BS2 <18>

DDR_B_MA[0..15] <18>

DDR_A_DQS#[4..5] <17>
DDR_B_DQS#[4..5] <18>
DDR_A_DQS#[6..7] <17>
DDR_B_DQS#[6..7] <18>

DDR_A_DQS[4..5] <17>
DDR_B_DQS[4..5] <18>
DDR_A_DQS[6..7] <17>
DDR_B_DQS[6..7] <18>

AY31

AW31

AY29

AW29

AV31
AU31
AV29
AU29
AY27

AW27

AY25

AW25

AV27
AU27
AV25
AU25
AM29
AK29

AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25

AY23

AW23

AY21

AW21

AV23
AU23
AV21
AU21
AY19

AW19

AY17

AW17

AV19
AU19
AV17
AU17
AR21
AR22

AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18

AK20
AM20
AR18
AP18

AL28

AL25

AL21

AL18

UC1D

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

HASWELL_MCP_E

DDR CHANNEL A

SA_CLK#0

SA_CLK0

SA_CLK#1

SA_CLK1
SA_CKE0

SA_CKE1
SA_CKE2
SA_CKE3

SA_CS#0
SA_CS#1

SA_ODT0

SA_RAS

SA_WE

SA_CAS
SA_BA0

SA_BA1
SA_BA2

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8

SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15

SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7

SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7

SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1

AU37
AV37
AW36
AY36

AU43
AW43
AY42
AY43

AP33
AR32

AP32
AY34

AW34
AU34

AU35
AV35
AY41

AU36
AY37
AR38
AP36
AU39
AR36
AV40
AW39
AY39
AU40
AP35
AW41
AU41
AR35
AV42
AU42

AJ61
AN62
AM58
AM55
AV57
AV53
AL43
AL48

AJ62
AN61
AN58
AN55
AW57
AW53
AL42
AL49

AP49
AR51
AP51

M_CLK_DDR#0
M_CLK_DDR0
M_CLK_DDR#1
M_CLK_DDR1

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#

DDR_A_RAS#
DDR_A_WE#
DDR_A_CAS#

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDR_A_DQS#0
DDR_A_DQS#1
DDR_B_DQS#0
DDR_B_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_B_DQS#2
DDR_B_DQS#3

DDR_A_DQS0
DDR_A_DQS1
DDR_B_DQS0
DDR_B_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_B_DQS2
DDR_B_DQS3

M_CLK_DDR#0 <17>
M_CLK_DDR0 <17>
M_CLK_DDR#1 <17>
M_CLK_DDR1 <17>

DDR_CKE0_DIMMA <17>
DDR_CKE1_DIMMA <17>

DDR_CS0_DIMMA# <17>
DDR_CS1_DIMMA# <17>

DDR_A_RAS# <17>
DDR_A_WE# <17>
DDR_A_CAS# <17>

DDR_A_BS0 <17>
DDR_A_BS1 <17>
DDR_A_BS2 <17>

+SM_VREF_CA
+SM_VREF_DQ0
+SM_VREF_DQ1

DDR_A_MA[0..15] <17>

DDR_A_DQS#[0..1] <17>
DDR_B_DQS#[0..1] <18>
DDR_A_DQS#[2..3] <17>
DDR_B_DQS#[2..3] <18>

DDR_A_DQS[0..1] <17>
DDR_B_DQS[0..1] <18>
DDR_A_DQS[2..3] <17>
DDR_B_DQS[2..3] <18>

AH63
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57

AK58
AR57
AN57
AP55
AR55
AM54
AK54

AK55
AR54
AN54
AY58

AW58

AY56

AW56

AV58
AU58
AV56
AU56
AY54

AW54

AY52

AW52

AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51

AL58

AL55

UC1C

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

D D

C C

DDR_A_D[0..15]<17>

DDR_B_D[0..15]<18>

DDR_A_D[16..31]<17>

DDR_B_D[16..31]<18>

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31

DDR_A_D[32..47]<17>

DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46

DDR_B_D[32..47]<18>

DDR_A_D[48..63]<17>

DDR_B_D[48..63]<18>

DDR_A_D47
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

B B

Rev1p2

+1.35V

12

RC15

+SM_VREF_CA +SM_VREF_DQ1

1

CC8

0.022U_0402_16V7K

2

change 22nF

12

RC23

24.9_0402_1%~D

1.82K_0402_1%

12

RC21

1.82K_0402_1%

1 2

RC18

2.2_0402_1%

1

2

12

confirm by intel request PDG P141

4

3

@

+1.35V

12

RC16

+SM_VREF_DQ0_DIMM1+SM_VREF_CA_DIMM +SM_VREF_DQ1_DIMM2

CC9

0.022U_0402_16V7K

change 22nF change 22nF

RC24

24.9_0402_1%~D

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1.82K_0402_1%

1 2

RC19

2.2_0402_1%

12

RC22

1.82K_0402_1%

2014/04/01 2015/04/30

2014/04/01 2015/04/30

2014/04/01 2015/04/30

+SM_VREF_DQ0

1

2

12

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

+1.35V

12

12

3 OF 19

RC14

1.82K_0402_1%

1 2

RC17

2.2_0402_1%

RC20

1.82K_0402_1%

@

A A

5

4 OF 19

CC10

0.022U_0402_16V7K

RC25

24.9_0402_1%~D

Rev1p2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

MCP(3,4/19) DDR3

MCP(3,4/19) DDR3

MCP(3,4/19) DDR3
LA-B015P

LA-B015P

LA-B015P

1

7 56Wednesday, September 10, 2014

7 56Wednesday, September 10, 2014

7 56Wednesday, September 10, 2014

0.1

0.1

0.1

of

of

of

5

RTC Battery

4

3

+RTCVCC

12

RC1
330K_0402_1%

2

1

+RTCBATT

SATA_IREF

RSVD
RSVD

SATA_RCOMP

SATALED

Rev1p2

PCH_INTVRMEN

12

@

RC2
330K_0402_1%

J5
H5
B15
A15

J8
H8
A17
B17

J6
H6
B14
C15

F5
E5
C17
D17

V1
U1
V6
AC1

A12
L11
K10
C12
U3

EC_SMI#
PCH_GPIO35
ODD_DETECT#
PCH_GPIO37

SATA_IREF

SATA_RCOMP
SATA_ACT#

PCH_AZ_SDOUT
PCH_AZ_SYNC
PCH_AZ_RST#
PCH_AZ_BITCLK

+3VS

1 2

+1.05VS_ASATA3PLL

RP37
10K_8P4R_5%

PCH_AZ_SDOUT

SATA HDD

CAD note:
Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.
reference FFRD sch 0.5

+3VS

RC3 1K_0402_5%@

FLASH DESCRIPTOR SECURITY OVERRIDE

LOW = DESABLED (DEFAULT)
HIGH = ENABLED

SATA_PRX_DTX_N0_C <32>
SATA_PRX_DTX_P0_C <32>
SATA_PTX_DRX_N0_C <32>
SATA_PTX_DRX_P0_C <32>

PCH Rx side need use strap pin to update PCIE +/-

+3VS

RC107
10K_0402_5%

1 2

EC_SMI# <30>

ODD_DETECT#

1 2

RC126 0_0603_1%@

1 2

RC131 3.01K_0402_1%

SATA_ACT# <25>

ODD_DETECT#
PCH_GPIO35
PCH_GPIO37

within 500 mils

1 8
2 7
3 6
4 5

SATA Impedance Compensation

D D

3

1 2
2

1

1

CC26
1U_0603_10V6K

2

+RTCVCC

RC10
1K_0402_5%

W=20mils

DC1
BAT54CW_SOT323-3

+RTCVCC

1 2

RC7 1M_0402_5%

1 2
1 2

RC5 20K_0402_5%
RC6 20K_0402_5%

1

1

@

CMOS1 SHORT PADS~D

1 2

CC4

+CHGRTC

W=20mils

W=20mils

C C

+RTCVCC

+CHGRTC

2

2

1U_0402_6.3V6K

CC1

XTAL@

1 2

15P_0402_50V8J

CC2

XTAL@

15P_0402_50V8J

1 2

CMOS place near DIMM

RTC discharge by EC

B B

G

@

12

RC368
100K_0402_5%

1 8
2 7
3 6
4 5

5

RP48
51_8P4R_5%

RTC_DIS<30>

+1.05VS_PCH

A A

SRTCRST#
PCH_RTCRST#

@

61

D

DMN66D0LDW-7_SOT363-6

G

2

QC2B

S

@

34

D

DMN66D0LDW-7_SOT363-6
QC2A

S

PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

JP14

@

2

112

JUMP_43X39

JP12

@

2

112

JUMP_43X39

For GCLK

PCH_RTCX1<19>

12

XTAL@

YC1

32.768KHZ_12.5PF_Q13FC1350000

2

CC3
1U_0402_6.3V6K

1

PCH_AZ_CODEC_SDIN0<22>

ME_EN<30>

CMOS_CLR1

Shunt Clear CMOS

Open

ME_CLR1

Shunt Clear ME RTC Registers

Open

+3VLP

PCH_RTCX1

PCH_RTCX1

12

XTAL@

RC4
10M_0402_5%

PCH_RTCX2
INTRUDER#
PCH_INTVRMEN
SRTCRST#
PCH_RTCRST#

PCH_AZ_BITCLK
PCH_AZ_SYNC
PCH_AZ_RST#
PCH_AZ_CODEC_SDIN0

1 2

RC8 1K_0402_5%

PCH_JTAG_RST#<6>

7/15
PCH_JTAG_TCK add Test Point for Factory.

PCH_AZ_SDOUT

PCH_JTAG_RST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

CMOS setting

Keep CMOS

TPM setting

Keep ME RTC Registers

UC1E

AW5

RTCX1

AY5

RTCX2

AU6

INTRUDER

AV7

INTVRMEN

AV6

SRTCRST

AU7

RTCRST

AW8

HDA_BCLK/I2S0_SCLK

AV11

HDA_SYNC/I2S0_SFRM

AU8

HDA_RST/I2S_MCLK

AY10

HDA_SDI0/I2S0_RXD

AU12

HDA_SDI1/I2S1_RXD

AU11

HDA_SDO/I2S0_TXD

AW10

HDA_DOCK_EN/I2S1_TXD

AV10

HDA_DOCK_RST/I2S1_SFRM

AY8

I2S1_SCLK

AU62

PCH_TRST

AE62

PCH_TCK

AD61

PCH_TDI

AE61

PCH_TDO

AD62

PCH_TMS

AL11

RSVD

AC4

RSVD

AE63

JTAGX

AV2

RSVD

@

INTVRMEN - INTEGRATED SUS 1.05V VRM
ENABLE

High - Enable Internal VRs
Low - Enable External VRs

HASWELL_MCP_E

SATAAUDIO

SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3

SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2

SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1

SATA_TN2/PETN6_L1
SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0

SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0

SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37

RTC

JTAG

5 OF 19

HDA for Codec

1 2

PCH_AZ_CODEC_SDOUT<22>
PCH_AZ_CODEC_SYNC<22>

PCH_AZ_CODEC_RST#<22>

PCH_AZ_CODEC_BITCLK<22>

R2356 33_0402_5%EMI@

1 2

R2357 33_0402_5%EMI@

1 2

R2358 33_0402_5%EMI@

1 2

R2359 33_0402_5%EMI@

@EMI@

1

CC5
27P_0402_50V8J

2

EMI depop location

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/04/01 2015/04/30

2014/04/01 2015/04/30

2014/04/01 2015/04/30

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

MCP(5/19) RTC,SATA,HDA,JTAG

MCP(5/19) RTC,SATA,HDA,JTAG

MCP(5/19) RTC,SATA,HDA,JTAG
LA-B015P

LA-B015P

LA-B015P

1

of

of

of

8 56Wednesday, September 10, 2014

8 56Wednesday, September 10, 2014

8 56Wednesday, September 10, 2014

0.1

0.1

0.1

5

D D

AU14

AW12

AY12

AW11

AV12

AA3

Y7

Y4
AC2
AA2
AA4

Y6
AF1

@EMI@

C2326
68P_0402_50V8J

+3VALW_PCH

1

2

PCH_SPI_MOSI_1
PCH_SPI_MISO_1
PCH_SPI_WP1#
PCH_SPI_HOLD1#

1 2

R2334 1K_0402_1%

1 2

R2335 1K_0402_1%

LPC_LFRAME#<30>

EMI

1 2

RP39

1 8
2 7
3 6
4 5

15_8P4R_5%

LPC_LAD0<30>
LPC_LAD1<30>
LPC_LAD2<30>
LPC_LAD3<30>

EMI@

R2333
15_0402_1%

LPC_LAD0
LPC_LAD1
LPC_LAD2

LPC_LFRAME#

PCH_SPI_CLKPCH_SPI_CLK_R
PCH_SPI_CS0#

PCH_SPI_MOSI
PCH_SPI_MISO
PCH_SPI_WP#
PCH_SPI_HOLD#

UC1G

LAD0
LAD1
LAD2
LAD3
LFRAME

SPI_CLK
SPI_CS0
SPI_CS1
SPI_CS2
SPI_MOSI
SPI_MISO
SPI_IO2
SPI_IO3

@

4

HASWELL_MCP_E

LPC

SPI C-LINK

7 OF 19

SMBALERT/GPIO11

SML0ALERT/GPIO60

SMBUS

SML1ALERT/PCHHOT/GPIO73

SML1CLK/GPIO75

SML1DATA/GPIO74

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK

CL_DATA

CL_RST

Rev1p2

3

1 2

DE7 RB751V-40_SOD323-2

PCH_GPIO60 FW_UPDATE

AN2

PCH_SMB_ALERT#

AP2

MEM_SMBCLK

AH1

MEM_SMBDATA

AL2

PCH_GPIO60

AN1

SML0CLK

AK1

SML0DATA

AU4

PCH_HOT#

AU3

SML1_SMBCLK

AH3

SML1_SMBDATA

AF2
AD2
AF4

RC370 0_0402_5%@

10K_0402_5%

T97@
T98@
T99@

R2329

+3VALW_PCH

12

12

12

R2330
10K_0402_5%

FW_UPDATE <30,46>

MEM_SMBCLKLPC_LAD3

MEM_SMBDATA

2

MEM Bus : DDR/XDP/WLAN/TP

+3VS

+3VS

2

G

6 1

D

5

DMN66D0LDW-7_SOT363-6

3 4

SGD

QC1A

DMN66D0LDW-7_SOT363-6

S

10K_0402_5%

QC1B

R2331

12

12

R2332
10K_0402_5%

1

DDR_XDP_WLAN_TP_SMBCLK <17,18,32>

DDR_XDP_WLAN_TP_SMBDAT <17,18,32>

SML1 Bus : EC/Sensors

C C

B B

A A

U2302

WINBOND

64M W25Q64FVSSIQ SOIC 8P

SA000039A30

SPI ROM ( 8MByte )

PCH_SPI_CS0#
PCH_SPI_MISO_1

PCH_SPI_WP1#

5

U2302

1

CS#

2

DO(IO1)

HOLD#(IO3)

3

WP#(IO2)

4

GND

64M EN25Q64-104HIP SOP 8P

@

10/100 LAN ------->

WLAN(Mini Card)--->

WLAN_CLKREQ#<26>

VCC
CLK

DI(IO0)

8
7

PCH_SPI_HOLD1#

6

PCH_SPI_CLK_R

5

PCH_SPI_MOSI_1

dGPU--->

R2452

@

1 2

0_0402_5%~D

DII-DMN65D8LW-7~D

1 3

D

Q2409

G

2
12

R2453
100K_0402_5%~D

+3VALW_PCH

S

C2327

0.1U_0402_10V7K

1 2

WLAN_CLKREQ#_R

+3VS

+3VALW_PCH

9/10.
Add PU for 3D CAMERA Function

CLK_PCIE_LAN#<21>
CLK_PCIE_LAN<21>

LAN_CLKREQ#<21>

CLK_PCIE_WLAN#<26>
CLK_PCIE_WLAN<26>

CLK_PEG_VGA#<47>
CLK_PEG_VGA<47>

PEG_CLKREQ#<48>

+3VS_WLAN_NGFF

4

CLK_PCIE_LAN#
CLK_PCIE_LAN

CLK_PCIE_WLAN#
CLK_PCIE_WLAN
WLAN_CLKREQ#_R

CLK_PEG_VGA#
CLK_PEG_VGA

+3VS

RP42

1 8
2 7
3 6
4 5

10K_8P4R_5%

PCH_GPIO60

MEM_SMBCLK
MEM_SMBDATA
SML1_SMBCLK
SML1_SMBDATA

SML0CLK
SML0DATA

1 2

RP40

1 8
2 7
3 6
4 5

2.2K_0804_8P4R_5%

RP49

1 8
2 7
3 6
4 5

1K_0804_8P4R_5%

UC1F

C43

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

U2

PCIECLKRQ0/GPIO18

B41

CLKOUT_PCIE_N1

A41

CLKOUT_PCIE_P1

Y5

PCIECLKRQ1/GPIO19

C41

CLKOUT_PCIE_N2

B42

CLKOUT_PCIE_P2

AD1

PCIECLKRQ2/GPIO20

B38

CLKOUT_PCIE_N3

C37

CLKOUT_PCIE_P3

N1

PCIECLKRQ3/GPIO21

A39

CLKOUT_PCIE_N4

B39

CLKOUT_PCIE_P4

U5

PCIECLKRQ4/GPIO22

B37

CLKOUT_PCIE_N5

A37

CLKOUT_PCIE_P5

T2

PCIECLKRQ5/GPIO23

@

3

RC37310K_0402_5%

SML1_SMBCLK

SML1_SMBDATA

HASWELL_MCP_E

A25

XTAL24_IN

B25

XTAL24_OUT

K21

RSVD

M21

RSVD

DIFFCLK_BIASREF

CLOCK

SIGNALS

6 OF 19

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8

TESTLOW_AL8

CLKOUT_LPC_0
CLKOUT_LPC_1

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

2014/04/01 2015/04/30

2014/04/01 2015/04/30

2014/04/01 2015/04/30

C26
C35

C34
AK8
AL8

AN15
AP15

B35
A35

Rev1p2

Compal Secret Data

Compal Secret Data

Compal Secret Data

+3VALW_PCH

QH1B

DMN66D0LDW-7_SOT363-6

For GCLK

XTAL24_IN<19>

XTAL24_IN
XTAL24_OUT

CLK_BIASREF

SWAP_1
SWAP_2

CLKOUT_LPC0

Deciphered Date

Deciphered Date

Deciphered Date

2

2

G

61

S

D

DMN66D0LDW-7_SOT363-6

1M_0402_5%

RC12

1 2

XTAL@

RC13

3.01K_0402_1%

1 2

SWAP_2
SWAP_1

R2336 22_0402_5%

5

34

SGD

QH1A

XTAL24_IN

7/15.
Add CC6 for LCD flash issue ( issued by CD Factory)

CC6

3.3P_0402_50V8C

3

4

XTAL@

YC2
24MHZ_12PF_X3G024000DC1H

1

2

RP41 10K_8P4R_5%

1 8
2 7
3 6
4 5

12

EC_SMB_CK2 <30,33,48>

EC_SMB_DA2 <30,33,48>

12

CC7

15P_0402_50V8J

12

XTAL@

+1.05VS_AXCK_LCPLL

EMI@

CLK_PCI_LPC <30>

Title

Title

Title

MCP(6,7/19) CLK,SMB,SPI,LPC

MCP(6,7/19) CLK,SMB,SPI,LPC

MCP(6,7/19) CLK,SMB,SPI,LPC

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

LA-B015P

LA-B015P

LA-B015P

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

9 56Tuesday, September 16, 2014

9 56Tuesday, September 16, 2014

1

9 56Tuesday, September 16, 2014

0.1

0.1

0.1

of

of

of

5

4

3

2

1

PCH_PLTRST#

CC33

D D

C C

B B

+3VALW_PCH

+3V_DSW

1 2

RC27 10K_0402_5%

1 2

RC28 10K_0402_5%@

1 2

RC29 10K_0402_5%@

1 2

RC32 10K_0402_5%

1 2

RC31 8.2K_0402_5%

1 2

RC34 1K_0402_5%

1 2

RC39 10K_0402_5%

+3VS

1 2

RC36 8.2K_0402_5%

SYS_PWROK

CC31

@ESD@

0.047U_0402_16V4Z

Place CC31
on BOT

PCH_PWROK

CC34

@ESD@

0.047U_0402_16V4Z

Place CC34
close to RP50.2&RP50.3

+3VS

1 2

RC73 10K_0402_5%

1 2

RC74 10K_0402_5%

1 2

RC75 10K_0402_5%

1 2

RC76 10K_0402_5%

1 2

RC77 10K_0402_5%

1 2

RC79 10K_0402_5%

1 2

RC87 100K_0402_5%@
RC88 1K_0402_1%@

@

ME_SUS_PWR_ACK
SUSACK#
SUS_STAT#/LPCPD#

AC_PRESENT
PCH_BATLOW#
PCIE_WAKE#_R
PCH_SLP_WLAN#

CLKRUN#

1

2

1

2

DGPU_PWROK
PCH_TP_INT#
EDP_BIA_PWM
TS_RST#
DGPU_HOLD_RST#
FFS_INT1

ENVDD_PCH

12

CODEC_IRQ

PCH_DPWROK

RC33 0_0402_5%@

ME_SUS_PWR_ACK_R SUSACK#

RC35 0_0402_5%@

Note: SUSACK# and SUSWARN# can be tied together if
EC does not want to involve in the handshake mechanism
for the Deep Sleep state entry and exit
CAN be NC ,if not support Deep Sx

SUSACK# SUSACK#_R

SUSACK#<30>

SYS_PWROK<30>
PCH_PWROK<30>

SYS_PWROK

EC_RSMRST#<30>

ME_SUS_PWR_ACK<30>

ACIN<30,34,35,48>

PCH_BATLOW# Need pull high to VCCDSW3_3
(If no deep Sx , connect to VCCSUS3_3)

EDP_BIA_PWM<6,31>

PANEL_BKLEN<30>

RC37 0_0402_1%@

1 8
2 7
3 6
4 5

RP50
0_8P4R_5%

1 2

RC41 0_0402_1%@

1 2

RC42 0_0402_1%@

1 2

DH1 RB751V-40_SOD323-2

SIO_SLP_S0#<30>

TS_RST#<31>

1 2

1 2

1 2

SYS_RESET#<6>

PBTN_OUT#<30>

ENVDD_PCH<31>

DGPU_PWROK<30,42>
PXS_PWREN<11,37,41,42,49>

DGPU_HOLD_RST#<47>

@

RC81
0_0402_1%

FFS_INT1<32>

PCH_RSMRST#_R

PCH_RSMRST#_R
ME_SUS_PWR_ACK_R
PBTN_OUT#
AC_PRESENT
PCH_BATLOW#
SIO_SLP_S0#
PCH_SLP_WLAN#

12

PCH_TP_INT#
TS_RST#

CODEC_IRQ

SYS_RESET#
SYS_PWROK_R
PCH_PWROK_R
PM_APWROK_R
PCH_PLTRST#

EDP_BKLCTLEDP_BIA_PWM
PANEL_BKLEN
ENVDD_PCH

DGPU_PWROK
PXS_PWREN
DGPU_HOLD_RST#
FFS_INT1

T117 @

0.047U_0402_16V4Z

Place CC33
close to UC3.1 & UC3.2

UC1H

AK2

SUSACK

AC3

SYS_RESET

AG2

SYS_PWROK

AY7

PCH_PWROK

AB5

APWROK

AG7

PLTRST

AW6

RSMRST

AV4

SUSWARN/SUSPWRDNACK/GPIO30

AL7

PWRBTN

AJ8

ACPRESENT/GPIO31

AN4

BATLOW/GPIO72

AF3

SLP_S0

AM5

SLP_WLAN/GPIO29

@

UC1I

B8

EDP_BKLCTL

A9

EDP_BKLEN

C6

EDP_VDDEN

U6

PIRQA/GPIO77

P4

PIRQB/GPIO78

N4

PIRQC/GPIO79

N2

PIRQD/GPIO80

AD4

PME

U7

GPIO55

L1

GPIO52

L3

GPIO54

R5

GPIO51

L4

GPIO53

1

ESD@

2

PCH_PLTRST#

HASWELL_MCP_E

SYSTEM POWER MANAGEMENT

HASWELL_MCP_E

eDP SIDEBAND

GPIO

8 OF 19

+3VS

0.1U_0402_10V7K

5

1

IN1

VCC

OUT

2

IN2

GND

3

DPWROK: Tired toghter with RSMRST#
that do not support Deep Sx

DSWVRMEN

DPWROK

WAKE

CLKRUN/GPIO32

SUS_STAT/GPIO61

SUSCLK/GPIO62

SLP_S5/GPIO63

SLP_S4
SLP_S3

SLP_A
SLP_SUS
SLP_LAN

Rev1p2

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

DISPLAY

DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP

DDPB_HPD
DDPC_HPD

EDP_HPD

CC11

@

1 2

4

PLT_RST#

UC3

MC74VHC1G08DFT2G_SC70-5

AW7

DSWODVREN

AV5

PCH_DPWROK

AJ5

V5

CLKRUN#

AG4

SUS_STAT#/LPCPD#

AE6

SUSCLK

AP5

SIO_SLP_S5#

AJ6

SIO_SLP_S4#

AT4

SIO_SLP_S3#

AL5
AP4
AJ7

B9

CPU_DPB_CTRLCLK

C9

CPU_DPB_CTRLDAT

D9

CPU_DPC_CTRLCLK

D11

CPU_DPC_CTRLDAT

C5

CPU_DPB_AUX#

B6

CPU_DPC_AUX#

B5

CPU_DPB_AUX

A6

CPU_DPC_AUX

C8

DPB_HPD

A8

DPC_HPD

D6

CPU_EDP_HPD#

12

R159

100K_0402_5%

DSWODVREN - On Die DSW VR Enable
H

*

L

R2337 330K_0402_5%
R2338 330K_0402_5%@

T105@
T107@

T106@

PLT_RST# <21,26,30,47>

Enable(DEFAULT)

：

Disable

：

1 2
1 2

1 2

PCIE_WAKE#PCIE_WAKE#_R

@

RC97
0_0402_5%

SUSCLK <26>
SIO_SLP_S5# <30>

T103 PAD~D@

@

T104 PAD~D

SIO_SLP_S4# <30>
SIO_SLP_S3# <30>

SLP_SUS# <30>

CPU_DPB_CTRLCLK <20>
CPU_DPB_CTRLDAT <20>

DPB_HPD <20>

+RTCVCC

PCH_DPWROK <30>

PCIE_WAKE# <21,30>

DSWODVREN - ON DIE DSW VR ENABLE

HIGH = ENABLED (DEFAULT)

LOW = DISABLED

CPU_DPB_CTRLDAT
CPU_DPB_CTRLCLK
CPU_DPC_CTRLCLK
CPU_DPC_CTRLDAT

CPU_DPB_AUX#
CPU_DPB_AUX
CPU_DPC_AUX
CPU_DPC_AUX#

1 8
2 7
3 6
4 5

RP52

2.2K_8P4R_5%

1 8
2 7
3 6
4 5

RP51
100K_8P4R_5%

+3VS

Rev1p2

+3VS

2

G

TP_INT#<27>

A A

5

1 3

1 2

RC367 0_0402_5%

D

S

QC3
2N7002K_SOT23-3

@

4

PCH_TP_INT#

@

3

9 OF 19

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DPC_HPD

Compal Secret Data

Compal Secret Data

2014/04/01 2015/04/30

2014/04/01 2015/04/30

2014/04/01 2015/04/30

Compal Secret Data

12

RC84

100K_0402_5%

RC89

100K_0402_5%

Deciphered Date

Deciphered Date

Deciphered Date

2

12

CPU_EDP_HPD#

@

RC82
0_0402_1%

12

EDP_CPU_HPD <31>

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

MCP(8,9/19) DDI,EDP,GPIO

MCP(8,9/19) DDI,EDP,GPIO

MCP(8,9/19) DDI,EDP,GPIO
LA-B015P

LA-B015P

LA-B015P

1

0.1

0.1

0.1

of

of

of

10 56Wednesday, September 10, 2014

10 56Wednesday, September 10, 2014

10 56Wednesday, September 10, 2014

5

D D

12

DE5RB751V-40_SOD323-2

1 2

3D_CAM_EN<30,46>

C C

B B

3D_CAM_EN PCH_GPIO57

RC371 0_0402_5%@

+3VS

12

RC11 10K_0402_5%

RC98 100K_0402_5%

RC9 100K_0402_5%

+3V_DSW

RC105 10K_0402_5%

+3VALW_PCH

RC372 10K_0402_5%

RC103 10K_0402_5%
RC104 10K_0402_5%
RC110 10K_0402_5%
RC116 10K_0402_5%

+3VS

12

12

12

12

12
12
12
12

RP54

18
27
36
45

8.2K_8P4R_5%

DEVSLP0

SIO_EXT_SCI#

PCH_GPIO56

GPIO27

PCH_GPIO57

KB_DET#
PCH_GPIO44
SLATE_MODE_R
PCH_AUDIO_EN

ODD_DA#
BT_ON#
WL_OFF#
PXS_PWREN

WAKE_PCH#<30>

9/10.
Add PU for 3D CAMERA Function

PXS_PWREN <10,37,41,42,49>

4

T182 PAD~D@

EC_LID_OUT#<30>

BT_ON#<26>

1 2

@

RC38 0_0402_1%

KB_DET#<27>

WL_OFF#<26>

T174 PAD~D@
T124 PAD~D@
T125 PAD~D@

TS_INT#<31>

T126 PAD~D@
T127 PAD~D@

EC_SCI#<30>

DEVSLP0<32>

HDA_SPKR<22>

+3VS +3VS

+3VALW_PCH

3

12

@

RC119
10K_0402_5%

BBS_BIT

12

RC123
1K_0402_5%

HASWELL_MCP_E

GPIO

10 OF 19

CPU/
MISC

LPIO

+3VALW_PCH

RCIN/GPIO82

PCH_OPI_RCOMP

GSPI0_CS/GPIO83

GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86

GSPI1_CS/GPIO87

GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89

GSPI_MOSI/GPIO90
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART0_RTS/GPIO93
UART0_CTS/GPIO94

UART1_RXD/GPIO0

UART1_TXD/GPIO1
UART1_RST/GPIO2
UART1_CTS/GPIO3

I2C0_SDA/GPIO4
I2C0_SCL/GPIO5
I2C1_SDA/GPIO6
I2C1_SCL/GPIO7

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69

12

@

RC120
1K_0402_5%

HOST_ALERT1_R_N

THERMTRIP

SERIRQ

RSVD
RSVD

Rev1p2

D60
V4
T4
AW15
AF20
AB21

R6
L6
N6
L8
R7
L5
N7
K2
J1
K3
J2
G1
K4
G2
J3
J4
F2
F3
G4
F1
E3
F4
D3
E4
C3
E2

H_THERMTRIP#
KB_RST#
SERIRQ
PCH_OPI_COMP

PCH_GPIO83
PCH_GPIO84
PCH_GPIO85
BBS_BIT
DGPU_PRSNT#
PROJECT_ID
PCH_GPIO89
PCH_GPIO90
CPPE#
CPUSB#
PCH_GPIO93
PCH_GPIO94

FFS_INT2
LCD_CBL_DET#

I2C0_SDA
I2C0_SCL
I2C1_SDA
I2C1_SCL

PCH_GPIO66
CAM_DETECT

+3VS

12

@

RC121
1K_0402_5%

HDA_SPKR

PCH_AUDIO_EN
PCH_GPIO12

EC_LID_OUT#
ODD_DA#

BT_ON#
GPIO27
HOST_ALERT1_R_N
KB_DET#

PCH_GPIO56
PCH_GPIO57
SLATE_MODE_R
WL_OFF#
PCH_GPIO44
PCH_GPIO47
PCH_GPIO48
PCH_GPIO49
TS_INT#

PCH_GPIO14
PCH_GPIO25

PCH_GPIO46
PCH_GPIO9

EC_SCI#
DEVSLP0

SIO_EXT_SCI#
HDA_SPKR

12

@

RC118
1K_0402_5%

PCH_GPIO66

12

@

RC122
1K_0402_5%

UC1J

P1

BMBUSY/GPIO76

AU2

GPIO8

AM7

LAN_PHY_PWR_CTRL/GPIO12

AD6

GPIO15

Y1

GPIO16

T3

GPIO17

AD5

GPIO24

AN5

GPIO27

AD7

GPIO28

AN3

GPIO26

AG6

GPIO56

AP1

GPIO57

AL4

GPIO58

AT5

GPIO59

AK4

GPIO44

AB6

GPIO47

U4

GPIO48

Y3

GPIO49

P3

GPIO50

Y2

HSIOPC/GPIO71

AT3

GPIO13

AH4

GPIO14

AM4

GPIO25

AG5

GPIO45

AG3

GPIO46

AM3

GPIO9

AM2

GPIO10

P2

DEVSLP0/GPIO33

C4

SDIO_POWER_EN/GPIO70

L2

DEVSLP1/GPIO38

N5

DEVSLP2/GPIO39

V2

SPKR/GPIO81

@

GPIO66 GPIO86 GPIO15 GPIO81

TOP-BLOCK SWAP OVERRIDE

HIGH depop RC288 (DEFAULT)
LOW pop RC288

12

RC124
10K_0402_5%

PCH_GPIO46

BOOT BIOS STRAP BIT BBS

HIGH
LOW(DEFAULT)

+3VALW_PCH

12

RC125
10K_0402_5%

PCH_GPIO9

LPC
SPI

TLS CONFIDENTIALITY

HIGH
LOW(DEFAULT)

GPIO15 NOT Used

NO REBOOT STRAP

HIGH
LOW(DEFAULT)

1 2

RC101

49.9_0402_1%

FFS_INT2 <32>

CAM_DETECT <46>

CAM_DETECT

2

+1.05VS_PCH

12

R2346
1K_0402_5%

T177PAD~D @
T176PAD~D @

T179PAD~D @

T180PAD~D @
T181PAD~D @

RC363 0_0402_5%@
RC364 0_0402_5%@

RC365 0_0402_1%@
RC366 0_0402_1%@

12

12

1 2

RE74 10K_0402_5%

+1.05VS_PCH

KB_RST# <30>
SERIRQ <30>

JET@

RC112
10K_0402_5%

TOPAZ@

RC113
10K_0402_5%

12
12

12
12

+3VS

Close to R2346

1

CC28
100P_0402_50V8J

@ESD@

2

ESD solution

+3VS+3VS

12

UMA@

RC100
10K_0402_5%

12

DIS@

RC99
10K_0402_5%

I2C1_SDA_PNL <31>
I2C1_SCL_PNL <31>

I2C1_SDA_TP <27>
I2C1_SCL_TP <27>

+3VS +3VS

12

3D@

RC117
10K_0402_5%

PCH_GPIO85 PCH_GPIO89

SERIRQ
LCD_CBL_DET#
CPPE#
CPUSB#
FFS_INT2

I2C1_SDA
I2C1_SCL
I2C0_SDA
I2C0_SCL

KB_RST#
TS_INT#

NON3D@

RC130
10K_0402_5%

12

1 8
2 7
3 6
4 5

1

OPAL@

RC135
10K_0402_5%

NONOPAL@

RC139
10K_0402_5%

12

RC10210K_0402_5%

12

RC10610K_0402_5%

12

RC108100K_0402_5%

12

RC111100K_0402_5%

12

RC115100K_0402_5%

RP53

10K_0804_8P4R_5%

12

RC10910K_0402_5%

12

RC11410K_0402_5%

12

12

+3VS

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/04/01 2015/04/30

2014/04/01 2015/04/30

2014/04/01 2015/04/30

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

MCP(10/19) GPIO,LPIO,MISC

MCP(10/19) GPIO,LPIO,MISC

MCP(10/19) GPIO,LPIO,MISC
LA-B015P

LA-B015P

LA-B015P

1

of

of

of

11 56Tuesday, September 16, 2014

11 56Tuesday, September 16, 2014

11 56Tuesday, September 16, 2014

0.1

0.1

0.1

5

D D

4

3

2

1

PCIe

HASWELL_MCP_E

11 OF 19

AN8
AM8

AR7
AT7

AR8
AP8

AR10
AT10

AM15
AL15

AM13
AN13

AP11
AN11

AR13
AP13

G20
H20

C33
B34

E18
F18

B33
A33

AJ10
AJ11
AN10
AM10

AL3
AT1
AH2
AV3

USB20_JUSB1_N0
USB20_JUSB1_P0

USB20_JUSB2_N1
USB20_JUSB2_P1

USB20_JUSB3_N2
USB20_JUSB3_P2

USB20_MINI1_N4
USB20_MINI1_P4

USB20_TOUCH_N5
USB20_TOUCH_P5

USB20_CR_N6
USB20_CR_P6

USB20_CAM_N7
USB20_CAM_P7

USB3RN1_JUSB1
USB3RP1_JUSB1

USB3TN1_JUSB1
USB3TP1_JUSB1

USB3RN2_JUSB2
USB3RP2_JUSB2

USB3TN2_JUSB2
USB3TP2_JUSB2

USBRBIAS

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#

USB2N0
USB2P0

USB2N1
USB2P1

USB2N2
USB2P2

USB2N3
USB2P3

USB2N4
USB2P4

USB2N5
USB2P5

USB2N6
USB2P6

USB2N7
USB2P7

USB3RN1
USB3RP1

USB

USB3TN1
USB3TP1

USB3RN2
USB3RP2

USB3TN2
USB3TP2

USBRBIAS
USBRBIAS

RSVD
RSVD

OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43

Rev1p2

USB20_JUSB1_N0 <24>
USB20_JUSB1_P0 <24>

USB20_JUSB2_N1 <24>
USB20_JUSB2_P1 <24>

USB20_JUSB3_N2 <25>
USB20_JUSB3_P2 <25>

USB20_MINI1_N4 <26>
USB20_MINI1_P4 <26>

USB20_TOUCH_N5 <31>
USB20_TOUCH_P5 <31>

USB20_CR_N6 <25>
USB20_CR_P6 <25>

USB20_CAM_N7 <31>
USB20_CAM_P7 <31>

USB3RN1_JUSB1 <24>

USB3RP1_JUSB1 <24>
USB3TN1_JUSB1 <24>

USB3TP1_JUSB1 <24>

USB3RN2_JUSB2 <24>

USB3RP2_JUSB2 <24>
USB3TN2_JUSB2 <24>

USB3TP2_JUSB2 <24>

T118PAD~D @
T119PAD~D @

USB_OC0# <24>
USB_OC1# <25>

USB Conn JUSB1

USB Conn JUSB2

USB Conn JUSB3

Mini Card (WLAN)

Touch screen panel

Card Reader

Camera

USB Conn JUSB1

USB Conn JUSB2

12

RC90

22.6_0402_1%~D

CAD NOTE:
Route single-end 50-ohms and max 500-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15 mils.

UC1K

PEG_CRX_GTX_N0<47>
PEG_CRX_GTX_P0<47>

PEG_CTX_GRX_N0<47>
PEG_CTX_GRX_P0<47>

PEG_CRX_GTX_N1<47>
PEG_CRX_GTX_P1<47>

PEG_CTX_GRX_N1<47>
PEG_CTX_GRX_P1<47>

PEG_CRX_GTX_N2<47>
PEG_CRX_GTX_P2<47>

PEG_CTX_GRX_N2<47>
PEG_CTX_GRX_P2<47>

PEG_CRX_GTX_N3<47>
PEG_CRX_GTX_P3<47>

PEG_CTX_GRX_N3<47>

C C

10/100 LAN

NGFF WLAN

B B

PEG_CTX_GRX_P3<47>

PCIE_PRX_LANTX_N3<21>
PCIE_PRX_LANTX_P3<21>

PCIE_PTX_LANRX_N3<21>
PCIE_PTX_LANRX_P3<21>

PCIE_PRX_WLANTX_N4<26>
PCIE_PRX_WLANTX_P4<26>

PCIE_PTX_WLANRX_N4<26>
PCIE_PTX_WLANRX_P4<26>

PEG_CRX_GTX_N0
PEG_CRX_GTX_P0

PEG_CTX_GRX_N0
PEG_CTX_GRX_P0

PEG_CRX_GTX_N1
PEG_CRX_GTX_P1

PEG_CRX_GTX_N2
PEG_CRX_GTX_P2

PEG_CRX_GTX_N3
PEG_CRX_GTX_P3

PCIE_PRX_LANTX_N3
PCIE_PRX_LANTX_P3

PCIE_PTX_LANRX_N3
PCIE_PTX_LANRX_P3

PCIE_PRX_WLANTX_N4
PCIE_PRX_WLANTX_P4

PCIE_PTX_WLANRX_N4

USB3TN3_3D_CAM<46>
USB3TP3_3D_CAM<46>

+1.05VS_AUSB3PLL

USB3RN3_3D_CAM<46>
USB3RP3_3D_CAM<46>

1 2

CC18 0.1U_0402_10V7KDIS@

1 2

CC19 0.1U_0402_10V7KDIS@

1 2

CC20 0.1U_0402_10V7KDIS@

1 2

CC21 0.1U_0402_10V7KDIS@

1 2

CC22 0.1U_0402_10V7KDIS@

1 2

CC23 0.1U_0402_10V7KDIS@

1 2

CC24 0.1U_0402_10V7KDIS@

1 2

CC25 0.1U_0402_10V7KDIS@

1 2

CC32 0.1U_0402_10V7K

1 2

CC40 0.1U_0402_10V7K

1 2

CC36 0.1U_0402_10V7K

1 2

CC41 0.1U_0402_10V7K

USB3RN3_3D_CAM
USB3RP3_3D_CAM

USB3TN3_3D_CAM
USB3TP3_3D_CAM

RC91

3.01K_0402_1%

1 2

PEG_CTX_GRX_C_N0
PEG_CTX_GRX_C_P0

PEG_CTX_GRX_C_N1PEG_CTX_GRX_N1
PEG_CTX_GRX_C_P1PEG_CTX_GRX_P1

PEG_CTX_GRX_C_N2PEG_CTX_GRX_N2
PEG_CTX_GRX_C_P2PEG_CTX_GRX_P2

PEG_CTX_GRX_C_N3PEG_CTX_GRX_N3
PEG_CTX_GRX_C_P3PEG_CTX_GRX_P3

PCIE_PTX_LANRX_N3_C
PCIE_PTX_LANRX_P3_C

PCIE_PTX_WLANRX_N4_C
PCIE_PTX_WLANRX_P4_CPCIE_PTX_WLANRX_P4

T120PAD~D@
T121PAD~D@

PCH_PCIE_RCOMP

F10
E10

C23
C22

F8
E8

B23
A23

H10
G10

B21
C21

E6
F6

B22
A21

G11
F11

C29
B30

F13
G13

B29
A29

G17
F17

C30
C31

F15
G15

B31
A31

E15
E13
A27
B27

PERN5_L0
PERP5_L0

PETN5_L0
PETP5_L0

PERN5_L1
PERP5_L1

PETN5_L1
PETP5_L1

PERN5_L2
PERP5_L2

PETN5_L2
PETP5_L2

PERN5_L3
PERP5_L3

PETN5_L3
PETP5_L3

PERN3
PERP3

PETN3
PETP3

PERN4
PERP4

PETN4
PETP4

PERN1/USB3RN3
PERP1/USB3RP3

PETN1/USB3TN3
PETP1/USB3TP3

PERN2/USB3RN4
PERP2/USB3RP4

PETN2/USB3TN4
PETP2/USB3TP4

RSVD
RSVD
PCIE_RCOMP
PCIE_IREF

@

+3VALW_PCH

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/04/01 2015/04/30

2014/04/01 2015/04/30

2014/04/01 2015/04/30

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

1 8
2 7
3 6
4 5

RP55
10K_8P4R_5%

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

MCP(11/19) PCIE,USB

MCP(11/19) PCIE,USB

MCP(11/19) PCIE,USB
LA-B015P

LA-B015P

LA-B015P

1

0.1

0.1

0.1

of

of

of

12 56Wednesday, September 10, 2014

12 56Wednesday, September 10, 2014

12 56Wednesday, September 10, 2014

5

4

3

2

1

VCCST_PG_EC

D D

220P_0402_50V8J

Place C79
between R286 and UC1

VCCST_PG_EC<30>

1

C79

ESD@

2

VCCST_PG_EC

+1.05VS_PCH

12

R286
10K_0402_5%

+CPU_CORE

Define EC OD pin, need double confirm.

VR_ON

SVID ALERT

C C

VR_SVID_ALRT#<40>

SVID DATA

SVID_DAT need to pull-up double side
( PWR_VR & CPU )

VR_SVID_DAT<40>

B B

VCCSENSE<40>

VCCSENSE

+CPU_CORE

12

R1
100_0402_1%

+1.05VS_PCH

12

Place the PU

R252

resistors close to CPU

75_0402_5%

R254
43_0402_1%

12

H_CPU_SVIDALRT#

+1.05VS_PCH

Place the PU
resistors close to CPU

12

R256

@

R257
0_0402_1%

130_0402_1%

12

H_CPU_SVIDDATA

CAD Note: PU resistor on HW side

0.1U_0402_10V7K

Place C80
close to R250.1

1

C80

ESD@

2

VR_SVID_CLK<40>

H_VR_READY<40>

RF

RF@

C5212
68P_0402_50V8J

+1.05VS_PCH

@

R253

R253

150_0402_1%

1 2

1 2

INTEL Check list , XDP use only

CPU_PWR_DEBUG#

@

R255
10K_0402_5%

C40

1 2

22U_0603_6.3V6M

@ESD@

ESD solution

R245
0_0603_5%

VR_ON<30,40>

+1.35V

+VCCIO_OUT

@

+VCCIOA_OUT

H_CPU_SVIDCLK

1

2

1 2

+CPU_CORE

1 2

1 2
1 2

+CPU_CORE

+1.35V

1

2

+1.35V

+VCCIO_OUT_R

R2480_0402_1% @

R2500_0402_1% @
R2510_0402_1% @

+1.05VS_PCH

2.2U_0402_6.3V6M
C35

1

2

VCCSENSE

2.2U_0402_6.3V6M
C36

L59
J58

AH26

AJ31
AJ33

AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50

F59
N58

AC58

E63

AB23

T38 @

A59

E20
AD23
AA23
AE59

T39 @
T40 @
T41 @
T42 @
T43 @
T44 @
T45 @
T46 @
T47 @
T48 @
T49 @
T50 @
T51 @

AD60
AD59
AA59
AE60
AC59
AG58

AC22
AE22
AE23

AB57
AD57
AG57

L62

N63

L63
B59
F60
C59

D63
H59
P62
P60
P61
N59
N61
T59

U59
V59

C24
C28
C32

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDATA
VCCST_PG_EC
VR12.5_VR_ON_R
VR_READY_R

CPU_PWR_DEBUG#

VDDQ DECOUPLING

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1

2

10U_0603_6.3V6M

C38

C37

1

1

C39

2

2

UC1L

RSVD
RSVD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VCC
RSVD
RSVD

VCC_SENSE
RSVD
VCCIO_OUT
VCCIOA_OUT
RSVD
RSVD
RSVD

VIDALERT
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY

VSS
PWR_DEBUG
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

VCCST
VCCST
VCCST

VCC
VCC
VCC
VCC
VCC
VCC

@

10U_0603_6.3V6M

1

C41

2

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

Rev1p2

C36
C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
U57
W57

+CPU_CORE

HASWELL_MCP_E

12 OF 19

HSW ULT POWER

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

C72

C42

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

C74

C45

2

2

VSSSENSE<15,40>

A A

VSSSENSE

12

R2
100_0402_1%

5

CAD Note: PD resistor on HW side

+1.35V : 470UF/2V/7343 *2 (PWR)
10UF/6.3V/0603 * 6

2.2UF/6.3V/0402 * 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/04/01 2015/04/30

2014/04/01 2015/04/30

2014/04/01 2015/04/30

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

MCP(12/19) Power

MCP(12/19) Power

MCP(12/19) Power
LA-B015P

LA-B015P

LA-B015P

1

of

of

of

13 56Friday, October 17, 2014

13 56Friday, October 17, 2014

13 56Friday, October 17, 2014

0.1

0.1

0.1

5

4

3

2

1

+1.05VS_PCH

330U_D3_2.5VY_R6M

330U_D3_2.5VY_R6M

1

D D

Close to N8

1 2

+1.05VS_PCH

+1.05VS_PCH +1.05VS_AUSB3PLL

1 2

L1

2.2UH_LQM2MPN2R2NG0L_30%

+1.05VS_ASATA3PLL

1 2

L2

2.2UH_LQM2MPN2R2NG0L_30%
R267

0_0805_1%

1 2

@

1 2

L3

@

2.2UH_LQM2MPN2R2NG0L_30%

1 2

L4

C C

B B

2.2UH_LQM2MPN2R2NG0L_30%

+1.05VS_AXCK_LCPLL

1 2

L5

2.2UH_LQM2MPN2R2NG0L_30%

+1.5VS +3VS

+VCCHDA

Reserve for HDA issue, C77 close to AH14

+1.05VS_PCH

+3V_DSW

+3VALW_PCH

C57 1U_0402_6.3V6K@

1 2

C58 1U_0402_6.3V6K

1 2

C59 100U_1206_6.3V6M

1 2

C63 1U_0402_6.3V6K

1 2

C65 100U_1206_6.3V6M

+1.05VS_APLLOPI

C69 1U_0402_6.3V6K
C70 100U_1206_6.3V6M@

+1.05VS_AXCK_DCB

1 2

C83 1U_0402_6.3V6K

1 2

C84 100U_1206_6.3V6M

1 2

C85 1U_0402_6.3V6K

1 2

C86 100U_1206_6.3V6M

1 2

RC127 0_0402_5%

1 2

RC128 0_0402_5%@

1 2

RC129 0_0402_5%@

1 2

C77 0.1U_0402_10V7K

1 2

C50 1U_0402_6.3V6K

1 2

C53 1U_0402_6.3V6K

1 2

C81 1U_0402_6.3V6K

1 2

C78 22U_0603_6.3V6M

1 2
1 2

+1.05VS_AUSB3PLL

+1.05VS_ASATA3PLL

+1.05VS_APLLOPI

+1.05VS_PCH

+1.05VS_PCH

+VCCHDA+3VALW_PCH

1 2

C92 1U_0402_6.3V6K@

C91 1U_0402_6.3V6K@

+1.05VS_AXCK_DCB

+1.05VS_AXCK_LCPLL

Close to K9,M9

Close to AH10

Close to AC9/AA9/AE20/AE21

+1.05VS_PCH

+1.05VS_PCH

1 2

+3VALW_PCH

+1.05VS_PCH
+1.05VS_PCH

+3VALW_PCH

+VCCHDA

+3V_DSW

+3VS

UC1M

K9

VCCHSIO

L10

VCCHSIO

M9

VCCHSIO

N8

VCC1_05

P9

VCC1_05

B18

VCCUSB3PLL

B11

VCCSATA3PLL

Y20

RSVD

AA21

VCCAPLL

W21

VCCAPLL

12

J13

RC1420_0402_5% @

DCPSUS3

AH14

12

VCCHDA

AH13

RC1430_0402_5% @

DCPSUS2

AC9

VCCSUS3_3

AA9

VCCSUS3_3

AH10

VCCDSW3_3

V8

VCC3_3

W9

VCC3_3

J18

VCCCLK

K19

VCCCLK

A20

VCCACLKPLL

J17

VCCCLK

R21

VCCCLK

T21

VCCCLK

K18

RSVD

M20

RSVD

V21

RSVD

AE20

VCCSUS3_3

AE21

VCCSUS3_3

@

CD63

+

2

VRM/USB2/AZALIA

LPT LP POWER

@ESD@

mPHY

OPI

USB3

AXALIA/HDA

GPIO/LCC

1

CD65

+

2

HASWELL_MCP_E

@ESD@

13 OF 19

RTC

SPI

CORE

THERMAL SENSOR

SDIO/PLSS

SUS OSCILLATOR

USB2

+1.05VS_PCH

1 2

22U_0603_6.3V6M

@ESD@

1 2

22U_0603_6.3V6M

@ESD@

ESD solution

VCCSUS3_3

VCCRTC
DCPRTC

VCCSPI

VCCASW
VCCASW

VCC1_05
VCC1_05
VCC1_05
VCC1_05

VCC1_05
DCPSUSBYP
DCPSUSBYP

VCCASW

VCCASW

VCCASW

DCPSUS1
DCPSUS1

VCCTS1_5

VCC3_3
VCC3_3

VCCSDIO
VCCSDIO

DCPSUS4

RSVD
VCC1_05
VCC1_05

Rev1p2

+CPU_CORE

C46

C47

AH11
AG10
AE7

+VCCRTCEXT

Y8

AG14
AG13

J11
H11
H15
AE8
AF22
AG19
AG20
AE9
AF9
AG8
AD10
AD8

J15
K14
K16

U8
T9

AB8

AC20
AG16
AG17

1 2

C51 1U_0402_6.3V6K

1 2

C52 0.1U_0402_10V7K

1 2

C68 0.1U_0402_10V7K@

+1.05VS_PCH
+1.05VS_PCH

1 2

C60 10U_0603_6.3V6M

1 2

C61 1U_0402_6.3V6K

1 2

C62 1U_0402_6.3V6K

C66 22U_0603_6.3V6M@
C67 1U_0402_6.3V6K

RC137 0_0402_5%@

C93 1U_0402_6.3V6K

C71 0.1U_0402_10V7K

C73 1U_0402_6.3V6K

RC136 0_0402_5%@

C76 1U_0402_6.3V6K

1 2
1 2

1 2

1 2

1 2

1 2

1 2

C90 1U_0402_6.3V6K@
CC37 47U_0603_2.5V7@
CC38 47U_0603_2.5V7@

+1.05VS_PCH

1 2

@

+PCH_VCCDSW

1 2
1 2
1 2

12

R2640_0603_1% @

+RTCVCC

+3VALW_PCH

+1.05VS_PCH

+3VALW_PCH

+1.05VS_PCH

+1.5VS
+3VS

+3VS

+1.05VS_PCH

C64
1U_0402_6.3V6K

1 2

+PCH_VCCDSW +3V_DSW

+RTCVCC

1

C54

2

1U_0402_6.3V6K

+1.05VS_PCH

22U_0603_6.3V6M

ESD solution

22U_0603_6.3V6M

ESD solution

C5215

1 2

0.47U_0402_6.3V6K

@

C55

0.1U_0402_10V7K

C44

1 2

@ESD@

C43

1 2

ESD@

1

2

0.1U_0402_10V7K

+3VS

+1.35V+1.05VS_PCH

1

C56

2

Reserve for inrush
current issue

1 2

C82 22U_0603_6.3V6M

+3VS

1 2

+1.05VS_PCH

+1.05VS_PCH

+3VALW_PCH

A A

5

C87 1U_0402_6.3V6K

1 2

C88 1U_0402_6.3V6K

12

C75 0.1U_0402_10V7K

Close to V8

Close to J17

Close to R21

Close to AH14

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/04/01 2015/04/30

2014/04/01 2015/04/30

2014/04/01 2015/04/30

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

MCP(13/19) Power

MCP(13/19) Power

MCP(13/19) Power
LA-B015P

LA-B015P

LA-B015P

1

of

of

of

14 56Friday, October 17, 2014

14 56Friday, October 17, 2014

14 56Friday, October 17, 2014

0.1

0.1

0.1

5

D D

4

3

2

1

HASWELL_MCP_E

UC1N

A11

VSS

A14

VSS

A18

VSS

A24

VSS

A28

VSS

A32

VSS

A36

VSS

A40

VSS

A44

VSS

A48

VSS

A52

VSS

A56

VSS

AA1

VSS

AA58

VSS

AB10

VSS

AB20

VSS

C C

B B

AB22
AC61

AD21
AD63

AE10
AE58

AF11
AF12
AF14
AF15
AF17
AF18

AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57

AD3

AG1

AJ13
AJ14
AJ23
AJ25
AJ27
AJ29

VSS

AB7

VSS
VSS
VSS
VSS
VSS
VSS

AE5

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

@

14 OF 19

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

Rev1p2

AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20

AP22
AP23
AP26
AP29

AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49

AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63

AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55

HASWELL_MCP_E

UC1O

VSS
VSS
VSS
VSS

AP3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AR5

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AU1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

@

15 OF 19

Rev1p2

AV59

VSS

AV8

VSS

AW16

VSS

AW24

VSS

AW33

VSS

AW35

VSS

AW37

VSS

AW4

VSS

AW40

VSS

AW42

VSS

AW44

VSS

AW47

VSS

AW50

VSS

AW51

VSS

AW59

VSS

AW60

VSS

AY11

VSS

AY16

VSS

AY18

VSS

AY22

VSS

AY24

VSS

AY26

VSS

AY30

VSS

AY33

VSS

AY4

VSS

AY51

VSS

AY53

VSS

AY57

VSS

AY59

VSS

AY6

VSS

B20

VSS

B24

VSS

B26

VSS

B28

VSS

B32

VSS

B36

VSS

B4

VSS

B40

VSS

B44

VSS

B48

VSS

B52

VSS

B56

VSS

B60

VSS

C11

VSS

C14

VSS

C18

VSS

C20

VSS

C25

VSS

C27

VSS

C38

VSS

C39

VSS

C57

VSS

D12

VSS

D14

VSS

D18

VSS

D2

VSS

D21

VSS

D23

VSS

D25

VSS

D26

VSS

D27

VSS

D29

VSS

D30

VSS

D31

VSS

UC1P

HASWELL_MCP_E

D33

VSS

D34

VSS

D35

VSS

D37

VSS

D38

VSS

D39

VSS

D41

VSS

D42

VSS

D43

VSS

D45

VSS

D46

VSS

D47

VSS

D49

VSS

D5

VSS

D50

VSS

D51

VSS

D53

VSS

D54

VSS

D55

VSS

D57

VSS

D59

VSS

D62

VSS

D8

VSS

E11

VSS

E17

VSS

F20

VSS

F26

VSS

F30

VSS

F34

VSS

F38

VSS

F42

VSS

F46

VSS

F50

VSS

F54

VSS

F58

VSS

F61

VSS

G18

VSS

G22

VSS

G3

VSS

G5

VSS

G6

VSS

G8

VSS

H13

VSS

@

16 OF 19

VSS_SENSE

Rev1p2

H17

VSS

H57

VSS

J10

VSS

J22

VSS

J59

VSS

J63

VSS

K1

VSS

K12

VSS

L13

VSS

L15

VSS

L17

VSS

L18

VSS

L20

VSS

L58

VSS

L61

VSS

L7

VSS

M22

VSS

N10

VSS

N3

VSS

P59

VSS

P63

VSS

R10

VSS

R22

VSS

R8

VSS

T1

VSS

T58

VSS

U20

VSS

U22

VSS

U61

VSS

U9

VSS

V10

VSS

V3

VSS

V7

VSS

W20

VSS

W22

VSS

Y10

VSS

Y59

VSS

Y63

VSS

V58

VSS

AH46

VSS

V23

VSS

E62
AH16

VSS

12

@

RC163
100_0402_1%

VSSSENSE <13,40>

CAD Note: RC163 SHOULD BE PLACED CLOSE TO CPU

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/04/01 2015/04/30

2014/04/01 2015/04/30

2014/04/01 2015/04/30

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

MCP(14,15,16/19) VSS

MCP(14,15,16/19) VSS

MCP(14,15,16/19) VSS
LA-B015P

LA-B015P

LA-B015P

1

of

of

of

15 56Wednesday, September 10, 2014

15 56Wednesday, September 10, 2014

15 56Wednesday, September 10, 2014

0.1

0.1

0.1

5

D D

4

3

2

1

HASWELL_MCP_E

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

18 OF 19

Rev1p2

CFG STRAPS for CPU

CFG4

12

RC138
1K_0402_1%

Display Port Presence Strap

1: Disabled; No Physical Display Port

CFG4

attached to Embedded Display Port

0: Enabled; An external Display Port device is
connected to the Embedded Display Port

N23
R23
T23
U10

AL1
AM11
AP7
AU10
AU15
AW14
AY14

RSVD_N23
RSVD_R23
RSVD_T23
RSVD_U10

RSVD_AL1
RSVD_AM11
RSVD_AP7
RSVD_AU10
RSVD_AU15
RSVD_AW14
RSVD_AY14

@

T129PAD~D

@

T130PAD~D

@
@

T133PAD~D

@

T136PAD~D

@

T137PAD~D

@

T139PAD~D

@

T141PAD~D

@

T142PAD~D

@

T144PAD~D

@

T145PAD~D

UC1S

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

CFG16
CFG18
CFG17
CFG19

CFG_RCOMP
RSVD
RSVD

RSVD
RSVD
RSVD
TD_IREF

HASWELL_MCP_E

17 OF 19

DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4

DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_A62

DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
DAISY_CHAIN_NCTF_AW2
DAISY_CHAIN_NCTF_AW3

DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63

Rev1p2

HASWELL_MCP_E

RESERVED

19 OF 19

A3
A4

A60
A61
A62
AV1
AW1
AW2
AW3
AW61
AW62
AW63

RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP

RSVD

RSVD_TP
RSVD_TP

RSVD_TP

RSVD
RSVD

RSVD

PROC_OPI_RCOMP

RSVD
RSVD

RSVD
RSVD

Rev1p2

DC_TEST_A3_B3
DC_TEST_A4

DC_TEST_A60
DC_TEST_A61_B61
DC_TEST_A62
DC_TEST_AV1
DC_TEST_AW1
DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
DC_TEST_AY61_AW61

DC_TEST_AW63

AV63
AU63

C63
C62
B43

A51
B51

L60
N60
W23

Y22
AY15

AV62
D58

P22

VSS

N21

VSS

P20
R20

PROC_OPI_RCOMP

PROC_OPI_RCOMP

1 2

RC13449.9_0402_1%

T146PAD~D @
T147PAD~D @

T148PAD~D @
T149PAD~D @
T150PAD~D @

T151PAD~D @
T152PAD~D @

T153PAD~D @
T154PAD~D @
T155PAD~D @

T156PAD~D @

T157PAD~D @
T158PAD~D @

T160PAD~D @
T162PAD~D @

T168PAD~D @
T169PAD~D @
T170PAD~D @

T171PAD~D @
T172PAD~D @

T173PAD~D @

@ T131PAD~D

T128 PAD~D

@

T132 PAD~D

@

T134 PAD~D

@

T135 PAD~D

@

T138 PAD~D

@

T140 PAD~D

@

T143 PAD~D

RSVD_AT2
RSVD_AU44
RSVD_AV44
RSVD_D15

RSVD_F22
RSVD_H22
RSVD_J21

UC1Q

12

CFG_RCOMP
TDI_IREF

AY2

AY3
AY60
AY61
AY62

B2

B3
B61
B62
B63

C1
C2

CFG4

CFG_RCOMP

TDI_IREF

DAISY_CHAIN_NCTF_AY2
DAISY_CHAIN_NCTF_AY3
DAISY_CHAIN_NCTF_AY60
DAISY_CHAIN_NCTF_AY61
DAISY_CHAIN_NCTF_AY62
DAISY_CHAIN_NCTF_B2
DAISY_CHAIN_NCTF_B3
DAISY_CHAIN_NCTF_B61
DAISY_CHAIN_NCTF_B62
DAISY_CHAIN_NCTF_B63
DAISY_CHAIN_NCTF_C1
DAISY_CHAIN_NCTF_C2

@

AC60
AC62
AC63
AA63
AA60

Y62
Y61
Y60
V62
V61
V60
U60
T63
T62
T61
T60

AA62

U63

AA61

U62
V63

A5

E1
D1
J20

H18
B12

@

DC_TEST_AY2_AW2
DC_TEST_AY3_AW3

T166PAD~D@

T167PAD~D@

C C

B B

DC_TEST_AY60
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
TP_DC_TEST_B2
DC_TEST_A3_B3
DC_TEST_A61_B61

DC_TEST_B62_B63
DC_TEST_C1_C2 DC_TEST_AY62_AW62

T159PAD~D@
T161PAD~D@

T163PAD~D@
T164PAD~D@
T165PAD~D@

RC132 49.9_0402_1%

1 2

RC133 8.2K_0402_1%

AU44
AV44

UC1R

AT2

RSVD
RSVD
RSVD

D15

RSVD

F22

RSVD

H22

RSVD

J21

RSVD

@

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/04/01 2015/04/30

2014/04/01 2015/04/30

2014/04/01 2015/04/30

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

MCP(17,18,19/19) CFG,RSVD

MCP(17,18,19/19) CFG,RSVD

MCP(17,18,19/19) CFG,RSVD
LA-B015P

LA-B015P

LA-B015P

1

16 56Wednesday, September 10, 2014

16 56Wednesday, September 10, 2014

16 56Wednesday, September 10, 2014

of

of

of

0.1

0.1

0.1

5

4

3

2

1

JDIMM1

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

BELLW_80001-1021

CONN@

H=4mm

DQS0#

RESET#

DQS3#

VREF_CA

DQS5#

DQS7#

EVENT#

BOSS2

DQS0

DQ12
DQ13

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3
DQ30

DQ31

CKE1

CK1#

RAS#

ODT0
ODT1

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5
DQ46

DQ47
DQ52

DQ53

DQ54
DQ55

DQ60
DQ61

DQS7
DQ62

DQ63

GND2

+1.35V

2

VSS

4

DQ4

6

DQ5

8

VSS

10
12
14

VSS

16

DQ6

18

DQ7

20

VSS

22
24
26

VSS

28

DM1

30
32

VSS

34
36
38

VSS

40
42
44

VSS

46

DM2

48

VSS

50
52
54

VSS

56
58
60

VSS

62
64
66

VSS

68
70
72

VSS

74
76

VDD

78

A15

80

A14

82

VDD

84

A11

86

A7

88

VDD

90

A6

92

A4

94

VDD

96

A2

98

A0

100

VDD

102

CK1

104
106

VDD

108

BA1

110
112

VDD

114

S0#

116
118

VDD

120
122

NC

124

VDD

126
128

VSS

130
132
134

VSS

136

DM4

138

VSS

140
142
144

VSS

146
148
150

VSS

152
154
156

VSS

158
160
162

VSS

164
166
168

VSS

170

DM6

172

VSS

174
176
178

VSS

180
182
184

VSS

186
188
190

VSS

192
194
196

VSS

198
200

SDA

202

SCL

204

VTT

206
208

3

2-3A to 1 DIMMs/channel

DDR_A_D4
DDR_A_D5

DDR_A_DQS#0

DDR_A_DQS0
DDR_A_D6

DDR_A_D7
DDR_A_D12

DDR_A_D13

DDR3_DRAMRST#
DDR_A_D14

DDR_A_D15
DDR_A_D20

DDR_A_D21

DDR_A_D22
DDR_A_D23

DDR_A_D28
DDR_A_D29

DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D30

DDR_A_D31DDR_A_D27

DDR_A_MA15
DDR_A_MA14

DDR_A_MA11DDR_A_MA12
DDR_A_MA7DDR_A_MA9

DDR_A_MA6DDR_A_MA8
DDR_A_MA4DDR_A_MA5

DDR_A_MA2
DDR_A_MA0DDR_A_MA1

M_CLK_DDR1
M_CLK_DDR#1

DDR_A_BS1
DDR_A_RAS#

DDR_CS0_DIMMA#
M_ODT0

M_ODT1

DDR_A_D36
DDR_A_D37

DDR_A_D38
DDR_A_D39

DDR_A_D44
DDR_A_D45

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D46
DDR_A_D47

DDR_A_D52
DDR_A_D53

DDR_A_D54
DDR_A_D55

DDR_A_D60
DDR_A_D61

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

+0.675VS

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

@ESD@

1

CD3

0.1U_0402_10V7K

2

CAD NOTE
PLACE THE CAP NEAR TO
DIMM RESET PIN

DDR_CKE1_DIMMA <7>

M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>

DDR_A_BS1 <7>
DDR_A_RAS# <7>

DDR_CS0_DIMMA# <7>

2.2U_0402_6.3V6M

Issued Date

Issued Date

Issued Date

0.1U_0402_10V7K

CD22

CD21

1

1

2

2

DDR_XDP_WLAN_TP_SMBDAT <9,18,32>
DDR_XDP_WLAN_TP_SMBCLK <9,18,32>

2014/04/01 2015/04/30

2014/04/01 2015/04/30

2014/04/01 2015/04/30

+SM_VREF_CA_DIMM

1 2

@

RD4
0_0402_1%

DDR3_DRAMRST#<18> DDR3_DRAMRST#_CPU <6>

DDR3L SODIMM ODT GENERATION

+5VALW +1.35V

12

1 2

DDR_PG_CTRL<6>

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

R2347
220K_0402_5%~D

@

R2351
2M_0402_5%

2
3

1 2

@

RD5
0_0402_1%

QD2
BSS138-G_SOT23-3

1 3

D

U2303

NC1VCC
A
GND

74AUP1G07GW_TSSOP5

+1.35V

12

RD3
470_0402_5%

M_ODT

0.1U_0402_10V7K

Place CC31
between QD2 and R2349

S

M_ODT

G

2

0.675V_DDR_VTT_ON

5

4

Y

1 2

R2348 66.5_0402_1%

1 2

R2349 66.5_0402_1%

1 2

R2350 66.5_0402_1%

1 2

R2352 66.5_0402_1%

+1.35V

@

CD23

0.1U_0402_10V7K

1 2

0.675V_DDR_VTT_ON

Title

Title

Title

DDRIII DIMMA

DDRIII DIMMA

DDRIII DIMMA

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

LA-B015P

LA-B015P

LA-B015P

Date: Sheet

Date: Sheet

Date: Sheet

M_ODT0
M_ODT1

0.675V_DDR_VTT_ON <39>

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

1

CD64

1

ESD@

2

M_ODT2 <18>
M_ODT3 <18>

17 56Wednesday, September 10, 2014

17 56Wednesday, September 10, 2014

17 56Wednesday, September 10, 2014

0.1

0.1

0.1

of

of

of

+DIMM1_VREF_DQ

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CD10

CD11

2

330U_D3_2.5VY_R6M

1

CD15

+

2

RD6 10K_0402_5%

RD7 10K_0402_5%

1 2

@

RD1
0_0402_1%

1 2
1 2

+3VS

DDR_CKE0_DIMMA<7>

M_CLK_DDR0<7>
M_CLK_DDR#0<7>

DDR_CS1_DIMMA#<7>

+3VS

CD62

1 2

22U_0603_6.3V6M

ESD@

DDR_A_BS0<7>
DDR_A_WE#<7>

DDR_A_CAS#<7>

+1.35V

2.2U_0402_6.3V6M

0.1U_0402_10V7K

CD1

CD2

1

1

2

2

DDR_A_BS2<7>

2.2U_0402_6.3V6M

0.1U_0402_10V7K

1

1

@

CD30

CD31

2

2

D D

C C

B B

A A

Populate RD1, De-Populate RD7 for Intel DDR3
VREFDQ multiple methods M1
Populate RD7, De-Populate RD1 for Intel DDR3
VREFDQ multiple methods M3

DDR_A_DQS#[0..7]<7>
DDR_A_D[0..63]<7>
DDR_A_DQS[0..7]<7>
DDR_A_MA[0..15]<7>

Layout Note:
Place near JDIMM1

+1.35V

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CD4

2

+1.35V

10U_0603_6.3V6M

10U_0603_6.3V6M

CD16

1

2

Layout Note:
Place near JDIMM1.203,204

+0.675VS

0.1U_0402_10V7K
CD24

1

2

1U_0402_6.3V6K

1

CD5

2

10U_0603_6.3V6M

@

CD17

1

2

0.1U_0402_10V7K

1

2

1

1

CD6

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD12

CD18

1

1

2

2

0.1U_0402_10V7K
CD26

CD25

1

2

+SM_VREF_DQ0_DIMM1

All VREF traces should
have 10 mil trace width

Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket

1U_0402_6.3V6K

1U_0402_6.3V6K

CD7

10U_0603_6.3V6M

@

CD19

1

2

0.1U_0402_10V7K
CD27

1

2

1U_0402_6.3V6K

1

CD8

2

10U_0603_6.3V6M

CD20

1

2

10U_0603_6.3V6M

1

2

1

1

CD9

2

2

10U_0603_6.3V6M

CD14

CD13

1

1

2

2

10U_0603_6.3V6M

CD29

CD28

1

2

+1.35V

DDR_A_D0
DDR_A_D1

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_D26

DDR_CKE0_DIMMA DDR_CKE1_DIMMA

DDR_A_BS2

DDR_A_MA3

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_MA10

DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#

DDR_A_MA13

DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59

+0.675VS

ESD solution

5

4

5

4

3

2

1

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1
VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9
VSS925VSS10

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2
DQS247VSS17
VSS1849DQ22

51

DQ18
DQ1953VSS19
VSS2055DQ28

57

DQ24
DQ2559VSS21
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0
VDD175VDD2

77

NC1

79

BA2
VDD381VDD4
A12/BC#83A11

85

A9
VDD587VDD6

89

A8

91

A5
VDD793VDD8

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

BELLW_80011-1021
CONN@

H=4mm

VSS3

DQS0

VSS6

VSS8
DQ12
DQ13

DQ14
DQ15

DQ20
DQ21

DQ23

DQ29

DQS3
DQ30

DQ31

CKE1

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30
VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42
VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

VTT2

2
4

DQ4

6

DQ5

8
10
12
14
16

DQ6

18

DQ7

20
22
24
26
28

DM1

30
32
34
36
38
40
42
44
46

DM2

48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78

A15

80

A14

82
84
86

A7

88
90

A6

92

A4

94
96

A2

98

A0

100
102

CK1

104
106
108

BA1

110
112
114

S0#

116
118
120
122

NC2

124
126
128
130
132
134
136

DM4

138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170

DM6

172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

SDA

202

SCL

204
206

G2

2-3A to 1 DIMMs/channel

DDR_B_D22
DDR_B_D16

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D19
DDR_B_D20

DDR_B_D4
DDR_B_D5

DDR3_DRAMRST#

DDR_B_D6
DDR_B_D7

DDR_B_D13
DDR_B_D9

DDR_B_D11
DDR_B_D10

DDR_B_D30
DDR_B_D26

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D29
DDR_B_D28DDR_B_D24

DDR_CKE3_DIMMB
DDR_B_MA15

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2

DDR_B_MA0
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_BS1

DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
M_ODT3

DDR_B_D33
DDR_B_D34

DDR_B_D39
DDR_B_D37

DDR_B_D44
DDR_B_D41

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D47
DDR_B_D46

DDR_B_D51
DDR_B_D55

DDR_B_D48
DDR_B_D54

DDR_B_D56
DDR_B_D57

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D60
DDR_B_D61

1

2

CAD NOTE
PLACE THE CAP NEAR TO
DIMM RESET PIN

DDR3_DRAMRST# <17>

@ESD@

CD34

0.1U_0402_10V7K

DDR_CKE3_DIMMB <7>

M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>

DDR_B_BS1 <7>
DDR_B_RAS# <7>

DDR_CS2_DIMMB# <7>
M_ODT2 <17>

M_ODT3 <17>

2.2U_0402_6.3V6M

1

CD52

2

DDR_XDP_WLAN_TP_SMBDAT <9,17,32>
DDR_XDP_WLAN_TP_SMBCLK <9,17,32>

+SM_VREF_CA_DIMM

1 2

0.1U_0402_10V7K

@

RD10
0_0402_1%

CD53

1

2

+DIMM2_VREF_DQ

+SM_VREF_DQ1_DIMM2

D D

C C

B B

Populate RD4, De-Populate RD8 for Intel DDR3
VREFDQ multiple methods M1
Populate RD8, De-Populate RD4 for Intel DDR3
VREFDQ multiple methods M3

DDR_B_DQS#[0..7]<7>
DDR_B_D[0..63]<7>
DDR_B_DQS[0..7]<7>

DDR_B_MA[0..15]<7>

Layout Note:
Place near JDIMM2

+1.35V

1U_0402_6.3V6K

1

CD35

2

+1.35V

10U_0603_6.3V6M

10U_0603_6.3V6M

@

CD43

CD44

1

1

2

2

Layout Note:
Place near JDIMM2.203,204

+0.675VS

0.1U_0402_10V7K
CD54

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CD37

CD36

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

2

1

2

10U_0603_6.3V6M

@

CD46

CD45

1

1

2

2

0.1U_0402_10V7K

0.1U_0402_10V7K
CD56

CD55

1

2

All VREF traces should
have 10 mil trace width

Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CD38

2

10U_0603_6.3V6M

CD47

1

2

0.1U_0402_10V7K
CD57

1

2

1U_0402_6.3V6K

1

1

CD39

CD40

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD50

CD49

CD48

1

1

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD58

CD59

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CD42

CD41

2

2

330U_D3_2.5VY_R6M

1

CD51

+

2

1 2

@

RD8
0_0402_1%

+3VS

2.2U_0402_6.3V6M

CD32

1

2

DDR_CKE2_DIMMB<7>

12

RD12 10K_0402_5%

DDR_CS3_DIMMB#<7>

+3VS

0.1U_0402_10V7K

CD33

1

2

DDR_B_BS2<7>

M_CLK_DDR2<7>
M_CLK_DDR#2<7>

DDR_B_BS0<7>
DDR_B_WE#<7>

DDR_B_CAS#<7>

10K_0402_5%

12

RD13

+1.35V +1.35V

DDR_B_D23
DDR_B_D17

DDR_B_D21
DDR_B_D18

DDR_B_D3
DDR_B_D2

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D0
DDR_B_D1

DDR_B_D12
DDR_B_D8

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D14
DDR_B_D15

DDR_B_D31
DDR_B_D25

DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3

DDR_B_MA1
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_MA10

DDR_B_BS0
DDR_B_WE#

DDR_B_CAS#
DDR_B_MA13

DDR_CS3_DIMMB#

DDR_B_D32
DDR_B_D35

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D36
DDR_B_D38

DDR_B_D40
DDR_B_D45

DDR_B_D43
DDR_B_D42

DDR_B_D52
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D53

DDR_B_D63
DDR_B_D62

DDR_B_D58
DDR_B_D59

+0.675VS +0.675VS

0.1U_0402_10V7K

2.2U_0402_6.3V6M
CD61

1

1

@

CD60

2

2

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/04/01 2015/04/30

2014/04/01 2015/04/30

2014/04/01 2015/04/30

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

DDRIII DIMMB

DDRIII DIMMB

DDRIII DIMMB
LA-B015P

LA-B015P

LA-B015P

1

of

of

of

18 56Wednesday, September 10, 2014

18 56Wednesday, September 10, 2014

18 56Wednesday, September 10, 2014

0.1

0.1

0.1