Compal LA-A972P Schematics

A

B

C

D

E

COMPAL CONFIDENTIAL

MODEL NAME :

1 1

PCB NO :
BOM P/N :

GPIO MAP: 3.3b

Goliad MLK 12 UMA ENTRY

LA-A972P

4319RK31LXX

2 2

Goliad MLK 12" UMA ENTRY

Broadwell U Processor

2013-12-23

REV : 0.2 (X01)

@ : Nopop Component

EMC@ : EMI, ESD and RF Component

@EMC@ : EMI, ESD and RF Nopop Component

3 3

Layout Dell logo

COPYRIGHT 2013
ALL RIGHT RESERVED
REV: X01
PWB: FGFC2

4 4

DATE: 1352-01

MB PCB

MB PCB

Part Number

Part Number

Description

Description

PCB 14A LA-A972P REV0 MB W/O DOCKING 2

PCB 14A LA-A972P REV0 MB W/O DOCKING 2

DA8000ZB000

DA8000ZB000

A

B

CXDP@ : XDP Component

CONN@ : Connector Component

VPRO@ : Vpro Component
NVPRO@ : Non-Vpro Component

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

C

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Cover Sheet

Cover Sheet

Cover Sheet

LA-A972P

LA-A972P

LA-A972P

E

0.1

0.1

1 48Monday, March 17, 2014

1 48Monday, March 17, 2014

1 48Monday, March 17, 2014

0.1

A

B

C

D

E

Reverse Type

Goliad MLK 12 UMA Entry Block Diagram

Memory BUS (DDR3L)

PAGE 7

PAGE 27

1333/1600MHz

USB2.0[0]

USB POWER SHARE

Full Mini Card
mSATA

1 1

eDP CONN

PAGE 23

mDP CONN

PAGE 24

WIGIG_DP

2 2

HDMI CONN

PAGE 24

SD4.0

PAGE 29 PAGE 29

Card reader

O2 Micro OZ777FJ2LN

PCIE3 PCIE4

3 3

4 4

Smart Card

RFID

Intel Clarkville
I218LM

PAGE 28

Transformer

PAGE 28

RJ45

PAGE 28

TDA8034HN

Fingerprint
CONN

A

FP_USB

USH

BCM5882

USB2.0[6]

USH board

PAGE 27

Parade
PS8339

HDMI

PCI Express BUS

PCIE5_L0

WLAN/BT/

WIGIG

PAGE 30

WIGIG_DP

Dual Lane eDP1.3

DDI2

PAGE 25

USB2.0[2]

B

BROADWELL ULT

DDI1

PCIE1

SMSC SIO

ECE1099

PAGE 35

BC BUS

INTEL

USB

PAGE 6~17

SPI

LPC

SMSC KBC

MEC5085

PAGE 36

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

C

HD Audio I/F

SATA1

W25Q64CVSSIQ

64M 4K sector

W25Q32BVSSIQ

32M 4K sector

Discrete TPM
AT97SC3205

KB/TP CONN

PAGE 37

FAN CONN

PAGE 36

TPS2544

HDA Codec

ALC3234

PAGE 20

D

DDR3L-DIMM X2

BANK 0, 1, 2, 3

PAGE 33

PAGE 21

PAGE 18 19

INT.Speaker

Universal Jack

USB2.0[4]

USB2.0[5]

USB3.0[1]

USB2.0[3]
USB3.0[4]

USB2.0[1]

USB3.0[2]

Trough eDP Cable

PAGE 21

PAGE 21

Dig. MIC

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Block diagram

Block diagram

Block diagram

LA-A972P

LA-A972P

LA-A972P

LCD Touch

PAGE 23

Camera

PAGE 23

USB3.0/2.0+PS

PAGE 31

USB3.0/2.0

PAGE 31

USB3.0/2.0

PAGE 32

Trough eDP Cable

LID switch

SIM+HALL/B

USH CONN

CPU XDP Port

Automatic Power
Switch (APS)

DC/DC Interface

Power On/Off
SW & LED

2 48Monday, March 17, 2014

2 48Monday, March 17, 2014

2 48Monday, March 17, 2014

E

PAGE 27

PAGE 9

PAGE 9

PAGE 38

PAGE 39

0.1

0.1

0.1

5

4

3

2

1

POWER STATES

Signal

State

D D

C C

S0 (Full ON) / M0

S3 (Suspend to RAM) / M3 LOW HIGH HIGH ON ON ON OFF

S4 (Suspend to DISK) / M3 ON ON OFF

S5 (SOFT OFF) / M3 ON ON OFFLOW HIGHLOW

S3 (Suspend to RAM) / M-OFF

S4 (Suspend to DISK) / M-OFF HIGH

S5 (SOFT OFF) / M-OFF

PM TABLE

power
plane

SLP
S3#

HIGH

LOW HIGH HIGH

LOW HIGH HIGH LOW ON ONOFF OFF OFF

LOW LOW LOW ON OFF OFF OFF OFF

LOW LOW LOW LOW ON OFF OFF OFF OFF

+3.3V_ALW
+3.3V_ALW _PCH
+3.3V_RTC_LDO

SLP

SLP

S5#

S4#

HIGH HIGH

LOW

LOW

+3.3V_SUS+5V_ALW +5V_RUN
+1.35V_MEM

ALWAYS

SLP

PLANE

A#

HIGH

HIGH

+0.675V_DDR_VTT
+1.05V_RUN
+VCC_CORE

M

SUS

RUN

PLANE

PLANE

ON

ON

ON ON ON

OFF

OFF

+3.3V_M +3.3V_M
+1.05V_M+3.3V_RUN

PLANE

+1.05V_M
(M-OFF)

CLOCKS

OFF

OFF

OFF

PCIE

PCIE 1

PCIE 2

PCIE 3

PCIE 4

PCIE 5

PCIE 6

USB3.0

USB3.0 1

USB3.0 2

USB3.0 3

USB3.0 4

SATA

SATA 3

SATA 2

SATA 0

USB PORT#

0

1

2

3

4

5

6

7

JUSB1

JUSB3

WLAN + BT

JUSB2

Touch Screen

CAMERA

USH

WWAN

State

ON

S0

B B

S3

S5 S4/AC

S5 S4/AC doesn't exist

ON

ON

ON ON

ON

OFF

OFFOFF

OFFON

OFF

OFF

ON

ON

OFF

ON

OFF

OFFOFF

BDW
ULT

DESTINATION

JUSB1-->Rear left

JUSB3-->Right

MMI (CARD READER)

JUSB2-->Rear Right

LOM

WLAN - JNGFF1

WiGig - JNGFF1

NA

NA

JMINI3SATA 1

NA

DESTINATION

A A

USH

1

0

BIO

NA

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Port assignment

Port assignment

Port assignment

LA-A972P

LA-A972P

LA-A972P

3 40Monday, March 17, 2014

3 40Monday, March 17, 2014

3 40Monday, March 17, 2014

1

0.1

0.1

0.1

5

4

3

2

1

RUN_ON

TPS22966

D D

ADAPTER

EN_INVPWR

FDC654P

(QV1)

+BL_PWR_SRC

(UZ2)

+1.05V_RUN

A_ON

SY8208
(PU300)

+1.05V_M

MPHYP_PWR_EN

SI3456
(QZ6)

+1.05V_MODPHY

BATTERY +PWR_SRC

ALWON

C C

CHARGER

TPS51285

(PU100)

+5V_ALW

+3.3V_ALW

ISL95813
(PU501)

B B

H_VR_EN

+VCC_CORE

SUS_ON

+1.35V_MEM

RT8207
(PU200)

0.675V_DDR_VTT_ON

SUS_ON

TPS22966

(UZ8) (UZ9)

+3.3V_SUS

A_ON

AUX_EN_WOWL

TPS22966

(UZ2)

+3.3V_M

SIO_SLP_LAN#

TPS22966

(UZ3)

+3.3V_LAN

PCH_ALW_ON

EN_LCDPWR

APL3512

(UV24)

+LCDVDD

3.3V_HDD_EN

TPS22965

(UZ11)

+3.3V_RUN

RUN_ON

RUN_ON

TPS22966

+5V_RUN

USB_PWR_SHR_EN#

TPS2544

(UI3) (UI2)

+5V_USB_CHG_PWR

USB_PWR_EN1#

G547I2P81U

(UI1)

USB_PWR_EN2#

G547I2P81U

+USB_SIDE_PWR +USB_RIGHT_PW R

+0.675V_DDR_VTT

A A

+3.3V_WLAN

+3.3V_HDD

+3.3V_ALW_PCH

+3.3V_CAM

3.3V_CAM_EN#

LP2301ALT1G

(QZ1)

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Power rails

Power rails

Power rails

LA-A972P

LA-A972P

LA-A972P

1

4 40Monday, March 17, 2014

4 40Monday, March 17, 2014

4 40Monday, March 17, 2014

0.1

0.1

0.1

5

SMBUS Address [0x9a]

MEM_SMBCLK

AP2

MEM_SMBDATA

AH1

D D

C C

BDW

SML0CLK

AN1

SML0DATA

AK1

AU3AH3

SML1_SMBDATA

SML1_SMBCLK

B6A5

3A

3A

2.2K

+3.3V_ALW_PCH

2.2K

B4

A3

B5

A4

DOCK_SMB_CLK

DOCK_SMB_DAT

LCD_SMBCLK

LCD_SMDATA

1A

1A

1B

1B

KBC

A56

A50

B53

A49

B52

B50

A47

B7

A7

B48

B49

PBAT_SMBCLK

PBAT_SMBDAT

USH_SMBCLK

USH_SMBDAT

CARD_SMBCLK

CARD_SMBDAT

CHARGER_SMBCLK

CHARGER_SMBDAT

BAY_SMBDAT

BAY_SMBCLK

GPU_SMBDAT

GPU_SMBCLK

1C1CB59

MEC 5085

B B

A A

1E

1E

2B

2B

1G

1G

2D

2D

2A

2A

5

2.2K

2.2K

1K

1K

4

+3.3V_ALW_PCH

2.2K

2.2K

2.2K

2.2K

2.2K

2.2K

2.2K

2.2K

2.2K

2.2K

10K

10K

2.2K

2.2K

2.2K

2.2K

4

+3.3V_ALW_PCH

+3.3V_ALW

+3.3V_ALW

+3.3V_ALW

100 ohm

100 ohm

+3.3V_SUS

+3.3V_ALW

+3.3V_ALW

9

8

+3.3V_ALW

+3.3V_ALW

2N7002

2N7002

3

2

1

2.2K

+3.3V_RUN

2.2K

202

4

200

202

28

31

LOM

7

BATTERY

6

CONN

M9

L9

USH

200

53

51

DIMMA

DIMMB

XDP

Charger

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

SMbus Block diagram

SMbus Block diagram

SMbus Block diagram

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

LA-A972P

LA-A972P

LA-A972P

1

5 40Monday, March 17, 2014

5 40Monday, March 17, 2014

5 40Monday, March 17, 2014

0.1

0.1

0.1

5

4

3

2

1

UMA SATA port

Service Mode Switch:

D D

+RTC_CELL

330K_0402_5%

330K_0402_5%

12

RC1

RC1

PCH_INTVRMEN

INTVRMEN - INTEGRATED SUS 1.05V VRM

C C

ENABLE
High - Enable Internal VRs
Low - Enable External VRs

RC9 1M_0402_5%RC9 1M_0402_5%

+RTC_CELL

RC10 20K_0402_5%RC10 20K_0402_5%
RC8 20K_0402_5%RC8 20K_0402_5%

1 2

CC3 1U_0402_6.3V6KCC3 1U_0402_6.3V6K

ME_CLR1

Shunt Clear ME RTC Registers

B B

Open

+1.05V_M

TPM setting

Keep ME RTC Registers

RPC21

RPC21

1 8
2 7
3 6
4 5

51_0804_8P4R_5%

51_0804_8P4R_5%

12

RC18@ 1K_0402_1%RC18@ 1K_0402_1%

12

PCH_JTAG_TCK

RC21@51_0402_5%RC21@51_0402_5%

Add a switch to ME_FWP signal to unlock the ME region and
allow the entire region of the SPI flash to be updated using FPT.

1 2

1 2
1 2

PCH_JTAG_TDI
PCH_JTAG_TMS
PCH_JTAG_TDO

PCH_JTAG_JTAGX

+3.3V_ALW_PCH

112

CMOS1@SHORT PADS~DCMOS1@SHORT PADS~D

CC4

CC4

CMOS place near DIMM

CMOS_CLR1

Shunt Clear CMOS

Open

PT, ST pop RC2 & SW1; MP pop RC301.

12

RC2

RC2
1K_0402_5%

1K_0402_5%

ME_FWP_EC<36>

ME_FWP PCH has internal 20K PD.

FLASH DESCRIPTOR SECURITY OVERRIDE

LOW = ENABLE (DEFAULT) -->Pin1 & Pin3 short
HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short

CC1

CC1

1 2

12P_0402_50V8J

12P_0402_50V8J

CC2

CC2

1 2

12P_0402_50V8J

12P_0402_50V8J

2

1 2

1U_0402_6.3V6K

1U_0402_6.3V6K

CMOS setting

Keep CMOS

@

@

1 2

+1.05V_M

10K_0402_5%

10K_0402_5%

RC301

@RC301

@

ME_FWP

1 2

RC4@ 0_0402_5%RC4@ 0_0402_5%

12

YC1

YC1

32.768KHZ_12.5PF_9H03220008

32.768KHZ_12.5PF_9H03220008

PCH_AZ_CODEC_SDIN0<21>

RC300

RC300

@

@

1 2

12

ME_FWPME_FWP_EC

0_0402_5%

0_0402_5%

SW1

SW1

1
2
3
4
5

SS3-CMFTQR9_3P

SS3-CMFTQR9_3P

PCH_RTCRST#<9>

ME_FWP

PCH_JTAG_TRST#<9>

PCH_JTAG_JTAGX<9>

CC100

CC100
1U_0402_6.3V6K

1U_0402_6.3V6K

A
B
C
G1
G2

PCH_JTAG_TCK<9>
PCH_JTAG_TDI<9>
PCH_JTAG_TDO<9>
PCH_JTAG_TMS<9>

PCH_RTCX1PCH_RTCX1_R

10M_0402_5%

10M_0402_5%

12

RC7

RC7

PCH_RTCX2

INTRUDER#
PCH_INTVRMEN
SRTCRST#
PCH_RTCRST#

PCH_AZ_BITCLK
PCH_AZ_SYNC
PCH_AZ_RST#
PCH_AZ_CODEC_SDIN0

1 2

PCH_AZ_SDOUT

RC11 1K_0402_5%RC11 1K_0402_ 5%

PCH_JTAG_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

PM_TEST_RST

AW5

AY5
AU6
AV7
AV6
AU7

AW8

AV11

AU8
AY10
AU12
AU11

AW10

AV10

AY8

AU62
AE62
AD61
AE61
AD62
AL11

AC4
AE63

AV2

SATA0

E-Dock

E-Dock

E-Dock

UC1E

UC1E

RTCX1
RTCX2
INTRUDER
INTVRMEN
SRTCRST
RTCRST

HDA_BCLK/I2S0_SCLK
HDA_SYNC/I2S0_SFRM
HDA_RST/I2S_MCLK
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_SDO/I2S0_TXD
HDA_DOCK_EN/I2S1_TXD
HDA_DOCK_RST/I2S1_SFRM
I2S1_SCLK

PCH_TRST
PCH_TCK
PCH_TDI
PCH_TDO
PCH_TMS
RSVD
RSVD
JTAGX
RSVD

BDW-ULT-DDR3L_BGA1168

BDW-ULT-DDR3L_BGA1168

5 OF 19

5 OF 19

mSATA

mSATA

mSATA

NANAmSATA

BDW_ULT_DDR3L

BDW_ULT_DDR3L

RTC

RTC

AUDIO SATA

AUDIO SATA

JTAG

JTAG

HDA for Codec

1 2

PCH_AZ_CODEC_SDOUT<21>

A A

PCH_AZ_CODEC_SYNC<21>

PCH_AZ_CODEC_RST#<21>

PCH_AZ_CODEC_BITCLK<21>

RC19 33_0402_5%RC19 33_0402_5%

RC20 33_0402_5%RC20 33_0402_5%

RC22 33_0402_5%RC22 33_0402_5%

RC23 33_0402_5%

RC23 33_0402_5%
27P_0402_50V8J

27P_0402_50V8J

@EMC@

@EMC@

12

CC5

CC5

Reserve for EMI

5

1 2

1 2

EMC@

EMC@

1 2

PCH_AZ_SDOUT

PCH_AZ_SYNC

PCH_AZ_RST#

PCH_AZ_BITCLK

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

HDD

HDD

PCB

G12 UMA

G12 EntryNA

G14 DSC

G14 UMA

G14D_En

G14U_En

SATA2/PCIE6 L1SATA1

M2 3042
2nd PCIe Lane for PCIe Cache

NA NA

M2 3042
SATA-Cache(no HCA)

M2 3042
2nd PCIe Lane for PCIe Cache

NA

NA

SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3

SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2
SATA_TN1/PETN6_L2

SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1
SATA_TN2/PETN6_L1

SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0

SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0

SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37

SATA_IREF

RSVD
RSVD

SATA_RCOMP

SATALED

2

J5
H5
B15
A15

J8
H8
A17
B17

J6
H6
B14
C15

F5
E5
C17
D17

V1

MPCIE_RST#

U1
V6
AC1

A12
L11
K10
C12

SATA_COMP

U3

SATA_ACT#

SATA3/PCIE6 L0

M2 3042
(HCA & SATA-Cache)

M2 3030 WIGIG

M2 3042
(HCA & SATA-Cache)

M2 3030 WIGIG

contact to WWAN

SATA2/PCIE6_L1 contact to WWAN
SATA3/PCIE6 L0 contact to WLAN

contact to WWAN

contact to WLAN

NA

for DOCK

SATA_PRX_DTX_N1 <20>
SATA_PRX_DTX_P1 <20>
SATA_PTX_DRX_N1 <20>
SATA_PTX_DRX_P1 <20>

SATA HDD

for PCIe Cache (WWAN)

for SATA-CACHE (WWAN)

HDD_DET# <20>
SATA2_PCIE6_L1 <12>
mCARD_PCIE#_SATA_R <36,7>

+PCH_ASATA3PLL

SATA_ACT# <39>

MMICLK_REQ#<29,7>
DGPU_PWROK<10>

SATA Impedance Compensation

CAD note:
Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.

SATA_COMP

MPCIE_RST#
HDD_DET#

1 2

7
8

10K_8P4R_5%

10K_8P4R_5%

+PCH_ASATA3PLL

RC173.01K_0402_1% RC173.01K_0402_1%

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

CPU (1/12)

CPU (1/12)

CPU (1/12)

LA-A972P

LA-A972P

LA-A972P

1

RPC18

RPC18

+3.3V_RUN

3456
2
1

0.1

0.1

6 48Monday, March 17, 2014

6 48Monday, March 17, 2014

6 48Monday, March 17, 2014

0.1

5

UC1G

UC1G

AU14

LPC_LAD0<20,36>
LPC_LAD1<20,36>
LPC_LAD2<20,36>
LPC_LAD3<20,36>

LPC_LFRAME#<20,36>

D D

33_0402_5%

33_0402_5%

1 2

1 2

C C

PCH_SPI_CLK<27>

PCH_SPI_CS2#<27>
PCH_SPI_DO<27>

SPI_CLK32 SPI_CLK64

RC61

@EMC@

RC61

@EMC@

33P_0402_50V8J

33P_0402_50V8J

CC9

@EMC@

CC9

@EMC@

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#

PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#
PCH_SPI_CS2#
PCH_SPI_DO
PCH_SPI_DIN

PCH_SPI_DIN<27>

PCH_SPI_DO2
PCH_SPI_DO3

33_0402_5%

33_0402_5%

RC62

@EMC@

RC62

@EMC@

1 2

33P_0402_50V8J

33P_0402_50V8J

CC10

@EMC@

CC10

@EMC@

1 2

LAD0

AW12

LAD1

AY12

LAD2

AW11

LAD3

AV12

LFRAME

AA3

SPI_CLK

Y7

SPI_CS0

Y4

SPI_CS1

AC2

SPI_CS2

AA2

SPI_MOSI

AA4

SPI_MISO

Y6

SPI_IO2

AF1

SPI_IO3

BDW-ULT-DDR3L_BGA1168

BDW-ULT-DDR3L_BGA1168

7 OF 19

7 OF 19

+3.3V_SPI

1 2

RC29 1K_040 2_5%RC29 1K_04 02_5%

1 2

RC31 1K_040 2_5%RC31 1K_04 02_5%

SPI_PCH_DO2

SPI_PCH_DO3

MMI --->

+3.3V_RUN

RPC6

RPC6

4 5
3

6

2

7

1

8

10K_8P4R_5%

10K_8P4R_5%

B B

PCB

G12 UMA

SD card

G12 Entry NA

G14 DSC

G14 UMA

G14D_En

G14U_En

A A

SD card

SD card

SD card

SD card

CONTACTLESS_DET# <10,27>

LANCLK_REQ#

mCARD_PCIE#_SATA_R <36,6>
PCH_GPIO16 <12>

PCIE1 PCIE4

NA LOM

NA

NA

NA

NA

NA

5

10/100/1G LAN --->

WLAN (NGFF1)--->

WGIG (NGFF1)--->

HCA/PCIe cache (NGFF2)--->

PCIE3PCIE2

WLAN

LOM

WLAN

LOM

WLAN

LOM

WLAN

LOM

WLAN

LOM

WLAN

PCIE5

WIGIG

WIGIGSD card

GPU

WIGIG

GPU

WIGIG

4

BDW_ULT_DDR3L

BDW_ULT_DDR3L

LPC

LPC

SMBUS

SMBUS

SML1ALERT/PCHHOT/GPIO73

C-LINKSPI

C-LINKSPI

SPI_PCH_DIN
SPI_PCH_DO
SPI_PCH_CLK
SPI_PCH_DO3

SPI_PCH_DO2 SPI_PCH_DO2_64

SPI_PCH_DO3
SPI_PCH_CLK
SPI_PCH_DO
SPI_PCH_DIN

SPI_PCH_DO2 SPI_PCH_DO2_32

PCIECLK for UMA

CLK_PCIE_MMI#<29>
CLK_PCIE_MMI<29>

MMICLK_REQ#<29,6>

+3.3V_RUN

CLK_PCIE_LAN#<28>
CLK_PCIE_LAN<28>

LANCLK_REQ#<28>

CLK_PCIE_WLAN#<30>

CLK_PCIE_WLAN<3 0>

WLANCLK_REQ#<12,30 >

CLK_PCIE_WIGIG#<30>

CLK_PCIE_WIGIG<30>

WIGIGCLK_REQ#<12,30>

+3.3V_RUN

PCIE6

M2 3042
(HCA & SATA-Cache)

WIGIG

M2 3042
(HCA & SATA-Cache)

WIGIG

NA

4

SMBALERT/GPIO11

SMBCLK

SMBDATA

SML0ALERT/GPIO60

SML0CLK

SML0DATA

SML1CLK/GPIO75

SML1DATA/GPIO74

CL_CLK

CL_DATA

CL_RST

SOFTWARE TAA

RPC11

RPC11

1 8
2 7
3 6
4 5

33_0804_8P4R_5%

33_0804_8P4R_5%

1 2

RC38 33_0402_5%RC38 33_0402_5%

RPC12

RPC12

1 8
2 7
3 6
4 5

33_0804_8P4R_5%

33_0804_8P4R_5%

1 2

RC55 33_0402_5%

RC55 33_0402_5%

VPRO@

VPRO@

RC66 10K_0402_5%RC 66 10K_0402_5%

RC68 10K_0402_5%RC68 10K_0402_5%

AN2
AP2
AH1
AL2
AN1
AK1
AU4
AU3
AH3

AF2
AD2
AF4

SPI_DIN64
SPI_DO64
SPI_CLK64
SPI_PCH_DO3_64

VPRO@

VPRO@

SPI_PCH_DO3_32
SPI_CLK32
SPI_DO32
SPI_DIN32

MMICLK_REQ#

1 2

LANCLK_REQ#

WLANCLK_REQ#

WIGIGCLK_REQ#

1 2

PCI_CLK_LPC_0

PCI_CLK_LPC_1

CLK_PCI_MEC

CLK_PCI_LPDEBUG

MEM_SMBCLK
MEM_SMBDATA

SML0_SMBCLK
SML0_SMBDATA

SML1_SMBCLK
SML1_SMBDATA

PCH_CL_CLK1
PCH_CL_DATA1
PCH_CL_RST1#

RC74EMC@ 22_0402_5%RC74EMC@ 22_0402_5%

RC67EMC@ 22_04 02_5%RC67EMC@ 22_0402_ 5%

Reserve for EMI

PCH_SMB_ALERT# <11 >

PCH_GPIO73 <1 2>
SML1_SMBCLK <36>

SML1_SMBDATA <36>

PCH_CL_CLK1 <30>

PCH_CL_DATA1 <30>

PCH_CL_RST1# <30>

C43
C42

U2

B41
A41

PCH_GPIO19

C41

B42

AD1

B38

C37

N1

A39
B39

U5

B37
A37

PCH_GPIO23

1 2

1 2

12

@EMC@12 P_0402_50V8J

@EMC@12 P_0402_50V8J

CC12

CC12

12

@EMC@12P_0402_5 0V8J

@EMC@12P_0402_5 0V8J

CC13

CC13

SML0_SMBCLK

SML0_SMBDATA

UC1F

UC1F

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
PCIECLKRQ0/GPIO18

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1

Y5

PCIECLKRQ1/GPIO19

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
PCIECLKRQ2/GPIO20

CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
PCIECLKRQ3/GPIO21

CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
PCIECLKRQ4/GPIO22

CLKOUT_PCIE_N5
CLKOUT_PCIE_P5

T2

PCIECLKRQ5/GPIO23

BDW-ULT-DDR3L_BGA1168

BDW-ULT-DDR3L_BGA1168

6 OF 19

6 OF 19

3

MEM_SMBCLK

MEM_SMBDATA

RC30 0_0402_5%@RC30 0_0402_ 5%@

RC32 0_0402_5%@RC32 0_0402_ 5%@

SPI_PCH_CS0#

SPI_PCH_CS1#

BDW_ULT_DDR3L

BDW_ULT_DDR3L

CLOCK

CLOCK

SIGNALS

SIGNALS

CLK_PCI_MEC <36>

CLK_PCI_LPDEBUG <20,36>

+3.3V_RUN

5

3 4

QC1B

QC1B

DMN66D0LDW -7_SOT363-6

DMN66D0LDW -7_SOT363-6

12

12

1 2

RC35 0_0402_5%@RC35 0_04 02_5%@

1 2

RC50 0_0402_5%

RC50 0_0402_5%

VPRO@

VPRO@

XTAL24_IN

XTAL24_OUT

RSVD
RSVD

DIFFCLK_BIASREF

TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8

CLKOUT_LPC_0
CLKOUT_LPC_1

CLKOUT_ITPXDP

CLKOUT_ITPXDP_P

PCH_SPI_CS1#

RC224 0_0402_5%RC224 0_0402_5%

PCH_SPI_DO

RC225 0_0402_5%RC225 0_0402_5%

PCH_SPI_DIN

RC226 0_0402_5%RC226 0_0402_5%

PCH_SPI_CLK

RC227 0_0402_5%RC227 0_0402_5%

PCH_SPI_CS0#

RC228 0_0402_5%RC228 0_0402_5%

PCH_SPI_DO2

RC229 0_0402_5%RC229 0_0402_5%

RC230 0_0402_5%RC230 0_0402_5%

+3.3V_SPI

RC231 0_0402_5%RC231 0_0402_5%

126

QC1A

QC1A

DMN66D0LDW -7_SOT363-6

DMN66D0LDW -7_SOT363-6

LAN_SMBCLK <28>

LAN_SMBDATA <28>

SPI_PCH_CS0#_R
SPI_DIN64
SPI_PCH_DO2_64

SPI_PCH_CS1#_R
SPI_DIN32
SPI_PCH_DO2_32

A25

XTAL24_IN

B25

XTAL24_OUT

K21
M21
C26

CLK_BIASREF

C35

MCP_TESTLOW1

C34

MCP_TESTLOW2

AK8

MCP_TESTLOW3

AL8

MCP_TESTLOW4

AN15

PCI_CLK_LPC_0

AP15

PCI_CLK_LPC_1

B35
A35

12

12

12

12

12

12

12

+3.3V_M

12

2

Please place RC224~RC331 with JSPI1 at the same MB side.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

DDR_XDP_WAN_ SMBCLK <18,19,9>

DDR_XDP_WAN_ SMBDAT <18,19,9>

64Mb Flash ROM

UC2

UC2

1

/CS

2

DO(IO1)

3

/WP(IO2)
GND4DI(IO0)

W25Q64FVSSIQ_SO8

W25Q64FVSSIQ_SO8

32Mb Flash ROM

VPRO@

VPRO@

UC3

UC3

1

/CS

2

DO/IO1

3

/WP/IO2
GND4DI/IO0

W25Q32FVSSIQ_SO8

W25Q32FVSSIQ_SO8

1M_0402_5%

1M_0402_5%

RC63

RC63

1 2

1 2

RC65@ 0_04 02_5%RC65@ 0_0402_5%

to SPI ROMfrom CPU

SPI_PCH_CS1#

SPI_PCH_DO

SPI_PCH_DIN

SPI_PCH_CLK

SPI_PCH_CS0#

SPI_PCH_DO2

SPI_PCH_DO3PCH_SPI_DO3

JSPI1

JSPI1

1

1

2

2 2

3

3

4

4 4

5

5

6

6 6

7

7

8

8 8

9

9

10

10 10

11

11

12

12 12

13

13

14

14 14

15

15

16

16 16

17

17

18

18 18

19

19

20

20 20

E-T_6700K-Y20N-00L

E-T_6700K-Y20N-00L

CONN@

CONN@

1

RPC14

RPC14

1
2
3
4 5

2.2K_0804_8P4R_5%

2.2K_0804_8P4R_5%

VPRO@

VPRO@

CC8

CC8

12

15P_0402_50V8J

15P_0402_50V8J

CC11

CC11

12

15P_0402_50V8J

15P_0402_50V8J

+PCH_VCCACLKPLL

1 2

1 2

RC240 10K_0402_5%RC24 0 10 K_0402_5%

1 2

RC241 10K_0402_5%RC24 1 10 K_0402_5%

1 2

RC242 10K_0402_5%RC24 2 10 K_0402_5%

1 2

RC243 10K_0402_5%RC24 3 10 K_0402_5%

support LPC TPM

RC693.01K_0402_1% RC6 93.01K_0 402_1%

VCC

/HOLD(IO3)

CLK

VCC

/HOLD/IO3

CLK

XTAL24_OUT_R

support SPI TPM

+3.3V_SPI

0.1U_0402_25V6

0.1U_0402_25V6

8
7

SPI_PCH_DO3_64

6

SPI_CLK64

5

SPI_DO64

+3.3V_SPI

0.1U_0402_25V6

0.1U_0402_25V6

8
7

SPI_PCH_DO3_32

6

SPI_CLK32

5

SPI_DO32

3

4

24MHZ_12PF_X3G0240 00DC1H

24MHZ_12PF_X3G0240 00DC1H

1

2

MCP_TESTLOW1
MCP_TESTLOW2
MCP_TESTLOW3
MCP_TESTLOW4

SML1_SMBDATA
SML1_SMBCLK
MEM_SMBCLK
MEM_SMBDATA

SML0_SMBCLK

SML0_SMBDATA

DDR_XDP_WAN_ SMBDAT

DDR_XDP_WAN_ SMBCLK

CC6

CC6

1 2

CC7

CC7

1 2

YC2

YC2

CLK_BIASREF

LPC_0 LPC_1 LPC_0 LPC_1

SIO

DOCK

MEC

DEBUG

21

G1

22

G2

23

G3

24

G4

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

DOCK

CLKBUFF

DEBUG

SIO

MEC

TPM

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

CPU (2/12)

CPU (2/12)

CPU (2/12)

LA-A972P

LA-A972P

LA-A972P

1

8
7
6

12

12

7 48Monday, March 17, 2014

7 48Monday, March 17, 2014

7 48Monday, March 17, 2014

+3.3V_ALW_PCH

RC33499_0402_ 1% RC33499_0402_ 1%

RC34499_0402_ 1% RC34499_0402_ 1%

+3.3V_RUN

12

RN32.2K_04 02_5% RN32.2K_0402_5%

12

RN42.2K_04 02_5% RN42.2K_0402_5%

0.1

0.1

0.1

5

BDW_ULT_DDR3L

D D

DDR_A_D[0..63]<18>

C C

B B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

UC1C

UC1C

AH63

SA_DQ0

AH62

SA_DQ1

AK63

SA_DQ2

AK62

SA_DQ3

AH61

SA_DQ4

AH60

SA_DQ5

AK61

SA_DQ6

AK60

SA_DQ7

AM63

SA_DQ8

AM62

SA_DQ9

AP63

SA_DQ10

AP62

SA_DQ11

AM61

SA_DQ12

AM60

SA_DQ13

AP61

SA_DQ14

AP60

SA_DQ15

AP58

SA_DQ16

AR58

SA_DQ17

AM57

SA_DQ18

AK57

SA_DQ19

AL58

SA_DQ20

AK58

SA_DQ21

AR57

SA_DQ22

AN57

SA_DQ23

AP55

SA_DQ24

AR55

SA_DQ25

AM54

SA_DQ26

AK54

SA_DQ27

AL55

SA_DQ28

AK55

SA_DQ29

AR54

SA_DQ30

AN54

SA_DQ31

AY58

SA_DQ32

AW58

SA_DQ33

AY56

SA_DQ34

AW56

SA_DQ35

AV58

SA_DQ36

AU58

SA_DQ37

AV56

SA_DQ38

AU56

SA_DQ39

AY54

SA_DQ40

AW54

SA_DQ41

AY52

SA_DQ42

AW52

SA_DQ43

AV54

SA_DQ44

AU54

SA_DQ45

AV52

SA_DQ46

AU52

SA_DQ47

AK40

SA_DQ48

AK42

SA_DQ49

AM43

SA_DQ50

AM45

SA_DQ51

AK45

SA_DQ52

AK43

SA_DQ53

AM40

SA_DQ54

AM42

SA_DQ55

AM46

SA_DQ56

AK46

SA_DQ57

AM49

SA_DQ58

AK49

SA_DQ59

AM48

SA_DQ60

AK48

SA_DQ61

AM51

SA_DQ62

AK51

SA_DQ63

BDW_ULT_DDR3L

DDR CHANNEL A

DDR CHANNEL A

4

SA_CLK#0

SA_CLK0

SA_CLK#1

SA_CLK1

SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3

SA_CS#0
SA_CS#1

SA_ODT0

SA_RAS

SA_WE

SA_CAS

SA_BA0
SA_BA1
SA_BA2

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8

SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15

SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7

SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7

SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1

3

UC1D

AU37

M_CLK_DDR#0

AV37

M_CLK_DDR0

AW36

M_CLK_DDR#1

AY36

M_CLK_DDR1

AU43

DDR_CKE0_DIMMA

AW43

DDR_CKE1_DIMMA DDR_CKE2_DIMMB

AY42
AY43

AP33

DDR_CS0_DIMMA#

AR32

DDR_CS1_DIMMA# DDR_C S2_DIMMB#

AP32

AY34

DDR_A_RAS#

AW34

DDR_A_WE#

AU34

DDR_A_CAS#

AU35

DDR_A_BS0

AV35

DDR_A_BS1

AY41

DDR_A_BS2

AU36

DDR_A_MA0

AY37

DDR_A_MA1

AR38

DDR_A_MA2

AP36

DDR_A_MA3

AU39

DDR_A_MA4

AR36

DDR_A_MA5

AV40

DDR_A_MA6

AW39

DDR_A_MA7

AY39

DDR_A_MA8

AU40

DDR_A_MA9

AP35

DDR_A_MA10

AW41

DDR_A_MA11

AU41

DDR_A_MA12

AR35

DDR_A_MA13

AV42

DDR_A_MA14

AU42

DDR_A_MA15

AJ61

DDR_A_DQS#0

AN62

DDR_A_DQS#1

AM58

DDR_A_DQS#2

AM55

DDR_A_DQS#3

AV57

DDR_A_DQS#4

AV53

DDR_A_DQS#5

AL43

DDR_A_DQS#6

AL48

DDR_A_DQS#7

AJ62

DDR_A_DQS0

AN61

DDR_A_DQS1

AN58

DDR_A_DQS2

AN55

DDR_A_DQS3

AW57

DDR_A_DQS4

AW53

DDR_A_DQS5

AL42

DDR_A_DQS6

AL49

DDR_A_DQS7

AP49
AR51
AP51

M_CLK_DDR#0 <18>
M_CLK_DDR0 <18>
M_CLK_DDR#1 <18>
M_CLK_DDR1 <18>

DDR_CKE0_DIMMA <18>
DDR_CKE1_DIMMA <18>

DDR_CS0_DIMMA# <18>
DDR_CS1_DIMMA# <18>

DDR_A_RAS# <18>

DDR_A_WE# <18>

DDR_A_CAS# <18>

DDR_A_BS0 <18>
DDR_A_BS1 <18>
DDR_A_BS2 <18>

DDR_A_MA[0..15] <18>

DDR_A_DQS#[0..7] <18>

DDR_A_DQS[0..7] <18>

+SM_VREF_CA
+SM_VREF_DQ0
+SM_VREF_DQ1

DDR_B_D[0..63]<19>

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

UC1D

AY31

SB_DQ0

AW31

SB_DQ1

AY29

SB_DQ2

AW29

SB_DQ3

AV31

SB_DQ4

AU31

SB_DQ5

AV29

SB_DQ6

AU29

SB_DQ7

AY27

SB_DQ8

AW27

SB_DQ9

AY25

SB_DQ10

AW25

SB_DQ11

AV27

SB_DQ12

AU27

SB_DQ13

AV25

SB_DQ14

AU25

SB_DQ15

AM29

SB_DQ16

AK29

SB_DQ17

AL28

SB_DQ18

AK28

SB_DQ19

AR29

SB_DQ20

AN29

SB_DQ21

AR28

SB_DQ22

AP28

SB_DQ23

AN26

SB_DQ24

AR26

SB_DQ25

AR25

SB_DQ26

AP25

SB_DQ27

AK26

SB_DQ28

AM26

SB_DQ29

AK25

SB_DQ30

AL25

SB_DQ31

AY23

SB_DQ32

AW23

SB_DQ33

AY21

SB_DQ34

AW21

SB_DQ35

AV23

SB_DQ36

AU23

SB_DQ37

AV21

SB_DQ38

AU21

SB_DQ39

AY19

SB_DQ40

AW19

SB_DQ41

AY17

SB_DQ42

AW17

SB_DQ43

AV19

SB_DQ44

AU19

SB_DQ45

AV17

SB_DQ46

AU17

SB_DQ47

AR21

SB_DQ48

AR22

SB_DQ49

AL21

SB_DQ50

AM22

SB_DQ51

AN22

SB_DQ52

AP21

SB_DQ53

AK21

SB_DQ54

AK22

SB_DQ55

AN20

SB_DQ56

AR20

SB_DQ57

AK18

SB_DQ58

AL18

SB_DQ59

AK20

SB_DQ60

AM20

SB_DQ61

AR18

SB_DQ62

AP18

SB_DQ63

2

BDW_ULT_DDR3L

BDW_ULT_DDR3L

DDR CHANNEL B

DDR CHANNEL B

SB_CK#0

SB_CK0

SB_CK#1

SB_CK1

SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3

SB_CS#0
SB_CS#1

SB_ODT0

SB_RAS

SB_WE

SB_CAS

SB_BA0
SB_BA1
SB_BA2

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8

SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15

SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7

SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7

AM38
AN38
AK38
AL38

AY49
AU50
AW49
AV50

AM32
AK32

AL32

AM35
AK35
AM33

AL35
AM36
AU49

AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46

AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18

AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18

M_CLK_DDR#2
M_CLK_DDR2
M_CLK_DDR#3
M_CLK_DDR3

DDR_CKE3_DIMMB

DDR_CS3_DIMMB#

DDR_B_RAS#
DDR_B_WE#
DDR_B_CAS#

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

1

M_CLK_DDR#2 <19>
M_CLK_DDR2 <19>
M_CLK_DDR#3 <19>
M_CLK_DDR3 <19>

DDR_CKE2_DIMMB <19>
DDR_CKE3_DIMMB <19>

DDR_CS2_DIMMB# <19>
DDR_CS3_DIMMB# <19>

DDR_B_RAS# <19>

DDR_B_WE# <19>

DDR_B_CAS# <19>

DDR_B_BS0 <19>
DDR_B_BS1 <19>
DDR_B_BS2 <19>

DDR_B_MA[0..15] <19>

DDR_B_DQS#[0..7] <19>

DDR_B_DQS[0..7] <19>

BDW-ULT-DDR3L_BGA1168

BDW-ULT-DDR3L_BGA1168

3 OF 19

3 OF 19

A A

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

BDW-ULT-DDR3L_BGA1168

BDW-ULT-DDR3L_BGA1168

4 OF 19

4 OF 19

DELL CONFIDENTIAL/PROPRIETARY

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

CPU (3/12)

CPU (3/12)

CPU (3/12)

LA-A972P

LA-A972P

LA-A972P

1

8 48Monday, March 17, 2014

8 48Monday, March 17, 2014

8 48Monday, March 17, 2014

0.1

0.1

0.1

5

+3.3V_ALW_PCH

1 2

ME_SUS_PWR_ACK

RC79 10 K_0402_5%RC7 9 10K_ 0402_5%

1 2

SUSACK#

RC81 10 K_0402_5%RC8 1 10K_ 0402_5%

1 2

SUS_STAT#/LPCPD#

+PCH_VCCDSW3_3

D D

C C

B B

A A

RC82@ 10K_04 02_5%RC82@ 10 K_0402_5%

RPC1

RPC1

4 5

PCH_PCIE_WAKE#

3

6

2

7

1

8

10K_8P4R_5 %

10K_8P4R_5 %

1 2

PM_LANPHY_ENABLE

RC92 10K_ 0402_5%@ RC92 10K_ 0402_5%@

1 2

PCH_RSMRST#_Q

RC91 47 K_0402_5%RC9 1 47K_ 0402_5%

+3.3V_RUN

1 2

RC95@ 8.2K_0 402_5%RC95@ 8 .2K_0402_ 5%

+1.05V_VCCST

CAD Note:
Avoid stub in the PWRGD path
while placing resistors RC123

DDR3 COMPENSATION SIGNALS

CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil

ME_RESET#

PCH_JTAG_TDO<6>

PCH_JTAG_TDI

PCH_JTAG_TDI<6>

RUNPWROK<36>

1 2

H_CATERR#

RC114@ 49. 9_0402_1%R C114@ 49.9 _0402_1%

1 2

H_PROCHOT#

RC116 6 2_0402_5 %RC116 62_04 02_5%

H_PROCHOT#

1

@EMC@

@EMC@

CC20

CC20
22P_0402_ 50V8J

22P_0402_ 50V8J

2

EMI request add

H_CPUPWRGD

100P_0402_50V8J

100P_0402_50V8J

10K_0402_5%

10K_0402_5%

@EMC@

@EMC@

12

CC83

CC83

RC123

RC123

1

2

12

RC130200_ 0402_1% RC130200_0402_ 1%

12

RC131121_040 2_1% RC131121_ 0402_1%

12

RC132100_ 0402_1% RC132100_0402_ 1%

5

RC98 0_0 402_5%

RC98 0_0 402_5%

CXDP@

CXDP@

RC99 0_0 402_5%

RC99 0_0 402_5%

CXDP@

CXDP@

PCH_JTAG_TMS<6>

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

0.1U_0402_2 5V6

0.1U_0402_2 5V6

1 2

1 2

XDP_DBRESET#

RC80@ 8 .2K_0402_ 5%RC80@ 8. 2K_0402_5 %

AC_PRESENT <36,9>

PCH_BATLOW# <9>

PM_LANPHY_ENABLE <12,28>

+3.3V_RUN

CC17

CXDP@CC17

CXDP@

12

RUNPWROK

RUNPWROK

RUNPWROK

RUNPWROK

PCH_JTAG_TRST#<6>

PCH_JTAG_JTAGX<6>

UC7

UC7

14

VCC

2

TDO_XDP

1A

1

1OE

5

TDI_XDP_R

2A

4

2OE

9

PCH_JTAG_TMS

3A

10

3OE

12

TRST#_XDP

4A

13

4OE

74CBTLV3126BQ_ DHVQFN14_2P5X3

74CBTLV3126BQ_ DHVQFN14_2P5X3

reference Shark Bay ULT Validation Customer Debug Port
Implementation Requirement Rev 1.0

PCH_JTAG_TDO

PCH_JTAG_TCK

H_PROCHOT#<36,45,46>

12

ME_RESET#

CXDP@

CXDP@

RC121 56 _0402_5%RC121 56 _0402_5%

DDR3_DRAMRST#_CPU<18>

DDR_PG_CTRL<18>

4

1 2

RC77@ 0_040 2_5%RC77@ 0 _0402_5%

+3.3V_RUN

5

1

P

B

4

O

2

A

G

UC4@

UC4@

74AHC1G09GW_TSSO P5

74AHC1G09GW_TSSO P5

3

PLTRST_USH#<27>
PLTRST_MMI#<29>
PLTRST_LAN#<28>

3

1B

6

2B

8

3B

11

4B

7

GND

15

GND PAD

12

CPU_XDP_TRST#

RC1090_0402_5% CXDP@RC1090_0402_5% C XDP@

12

CPU_XDP_TCLK

RC1120_0402_5% CXDP@RC11 20_ 0402_5% CX DP@

12

TDO_XDP

RC115 @0_0402_5% RC115@0_0402_5%

12

TDI_XDP_R

RC118 @0_0402_5% RC118@0_0402_5%

12

CPU_XDP_TCLK

RC119 @0_0402_5% RC119@0_0402_5%

H_CATERR#
PECI_EC

PECI_EC<36>

1 2

H_PROCHOT#_R

H_CPUPWRGD

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

4

SYS_PWROK<36>
RESET_OUT#<15,36>

PCH_RSMRST#_Q<37>

ME_SUS_PWR_ACK<36>

SIO_PWRBTN#<36>

AC_PRESENT<36,9>

PCH_BATLOW#<9>

SIO_SLP_WLAN#<35>

CPU_XDP_TDO

CPU_XDP_TDI

CPU_XDP_TMS

CPU_XDP_TRST#

D61
K61
N62

K63

C61

AU60
AV60
AU61
AV15
AV61

SUSACK#<36>

3

+3.3V_RUN

5

1

SYS_RESET#

1 2

RC87@ 0_0402_5%RC87@ 0_0402_5%

1 2

RC88@ 0_0402_5%RC88@ 0_0402_5%

1 2

RC89@ 0_0402_5%RC89@ 0_0402_5%

UC1B

UC1B

PROC_DETECT
CATERR
PECI

PROCHOT

PROCPWRGD

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_DRAMRST
SM_PG_CNTL1

BDW-ULT-DDR3L_BGA1168

BDW-ULT-DDR3L_BGA1168

2 OF 19

2 OF 19

PCH_PLTRST#

TC7SH08FU_SSOP5~D

TC7SH08FU_SSOP5~D

SUSACK#
SYS_RESET#
SYS_PWROK

PM_APWROK_R
PCH_PLTRST#

PCH_RSMRST#_Q PCH_RTCRST#
ME_SUS_PWR_ACK
SIO_PWRBTN#
AC_PRESENT

PCH_BATLOW#

SIO_SLP_S0#
SIO_SLP_WLAN#

BDW_ULT_DDR3L

BDW_ULT_DDR3L

MISC

MISC

THERMAL

THERMAL

PWR

PWR

DDR3L

DDR3L

B

2

A

UC5

UC5

PCH_PLTRST#

UC1H

UC1H

AK2

SUSACK

AC3

SYS_RESET

AG2

SYS_PWROK

AY7

PCH_PWROK

AB5

APWROK

AG7

PLTRST

AW6

RSMRST

AV4

SUSWARN/SUSPWRDNACK/GPIO30

AL7

PWRBTN

AJ8

ACPRESENT/GPIO31

AN4

BATLOW/GPIO72

AF3

SLP_S0

AM5

SLP_WLAN/GPIO29

BDW-ULT-DDR3L_BGA1168

BDW-ULT-DDR3L_BGA1168

8 OF 19

8 OF 19

H_VCCST_PWRGD<15>

JTAG

JTAG

P

4

PCH_PLTRST#_EC

12

O

G

3

Fix Intel 7260 can not detect issue.
It will cause “floating” situation before 3V_RUN coming of AND gate

SYSTEM POWER MANAGEMENT

SYSTEM POWER MANAGEMENT

+1.05V_RUN

Place near JXDP1

RC102 1K_0402_5%

RC102 1K_0402_5%

CXDP@

CXDP@

H_CPUPWRGD

PROC_TCK
PROC_TMS

PROC_TRST

PROC_TDI

PROC_TDO

RC304

@RC304

@

100K_0402 _5%

100K_0402 _5%

BDW_ULT_DDR3L

BDW_ULT_DDR3L

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

@

@

@

@

12

12

CC18

CC18

CC19

CC19

RC5 need to close to JCPU1

1 2

1 2

RC103@ 1 K_0402_5%R C103@ 1 K_0402_5%

J62

CPU_XDP_PRDY#

PRDY

K62

CPU_XDP_PREQ#

PREQ

E60

CPU_XDP_TCLK

E61

CPU_XDP_TMS

E59

CPU_XDP_TRST#

F63

CPU_XDP_TDI

F62

CPU_XDP_TDO

J60

XDP_OBS0_R

BPM#0

H60

XDP_OBS1_R

BPM#1

H61

XDP_OBS2_R

BPM#2

H62

XDP_OBS3_R

BPM#3

K59

XDP_OBS4_R

BPM#4

H63

XDP_OBS5_R

BPM#5

K60

XDP_OBS6_R

BPM#6

J61

XDP_OBS7_R

BPM#7

PCH_PLTRST#_EC <20,27,30,36>

PM_APWROK<36>

1.05V_M_PWRGD<43>

DSWVRMEN

DPWROK

WAKE

CLKRUN/GPIO32

SUS_STAT/GPIO61

SUSCLK/GPIO62
SLP_S5/GPIO63

SLP_S4
SLP_S3

SLP_A
SLP_SUS
SLP_LAN

CFG0<13>
CFG1<13>

CFG2<13>
CFG3<13>

CFG4<13>
CFG5<13>

CFG6<13>
CFG7<13>

CPU_PWR_DEBUG#<15>

DDR_XDP_WAN_SMBDAT<18,19 ,7>

DDR_XDP_WAN_SMBCLK<18,19,7>

PCH_JTAG_TCK<6>

AW7
AV5
AJ5

V5
AG4
AE6
AP5

AJ6
AT4
AL5
AP4
AJ7

CPU_XDP_PREQ#
CPU_XDP_PRDY#

XDP_OBS0_R
XDP_OBS1_R

H_VCCST_PWRGD_XDP

SIO_PWRBTN#

SYS_PWROK

CPU_XDP_TCLK

CFG0
CFG1

CFG2
CFG3

CFG4
CFG5

CFG6
CFG7

T10 @PAD~D T10 @PAD~D
T11 @PAD~D T11 @PAD~D RC126
T12 @PAD~D T12 @PAD~D
T13 @PAD~D T13 @PAD~D
T14 @PAD~D T14 @PAD~D
T15 @PAD~D T15 @PAD~D

2

SIO_SLP_A#

1 2

PM_APWROK PM_APWROK_L

RC26 0_ 0402_5%@RC26 0 _0402_5%@

1 2

RC27 0_ 0402_5%@RC27 0 _0402_5%@

DSWODVREN
PCH_DPWROK

PCH_DPWROK <36>

PCH_PCIE_WAKE#

PCH_PCIE_WAKE# <35,36>

CLKRUN#
SUS_STAT#/LPCPD#
SUSCLK_R
SIO_SLP_S5#

SIO_SLP_S4#
SIO_SLP_S3#
SIO_SLP_A#
SIO_SLP_SUS#
SIO_SLP_LAN#

+3.3V_ALW_PCH

0.1U_0402_25V6

0.1U_0402_25V6

CC22@

CC22@

+1.05V_RUN

1K_0402_5%

1K_0402_5%

1 2

12

RC120

CXDP@

RC120

CXDP@

SYS_PWROK

13

19
21
23
25

31

37

47
49
51
53
55
57
59

CLKRUN# <10,36>

1 2

RC136 0_0402_5%@RC136 0_0402 _5%@

SIO_SLP_S5# <36>

T8 @PAD~DT8 @PAD~D
T9@PAD~DT9@PAD~D

SIO_SLP_S4# <36>
SIO_SLP_S3# <36>
SIO_SLP_A# <36>
SIO_SLP_SUS# <36>
SIO_SLP_LAN# <36,38>

JXDP1

JXDP1

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2
OBSDATA_A09OBSDATA_C0
OBSDATA_A111OBSDATA_C1
GND4
OBSDATA_A215OBSDATA_C2
OBSDATA_A317OBSDATA_C3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B027OBSDATA_D0
OBSDATA_B129OBSDATA_D1
GND10
OBSDATA_B233OBSDATA_D2
OBSDATA_B335OBSDATA_D3
GND12
PWRGOOD/HOOK039ITPCLK/HOOK4
HOOK141ITPCLK#/HOOK5
VCC_OBS_AB43VCC_OBS_CD
HOOK245RESET#/HOOK6
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16

Place near JXDP1.47

+3.3V_ALW2

5

1

B

2

A

3

SUSCLK <30>

GND1
OBSFN_C0
OBSFN_C1

GND3

GND5

GND7
OBSFN_D0
OBSFN_D1

GND9

GND11

GND13

DBR#/HOOK7

GND15

TD0

TRST#

TDI

TMS

GND17

CONN@SAMTE_BSH-030-01-L -D-A

CONN@SAMTE_BSH-030-01-L -D-A

Place near JXDP1.48

XDP_DBRESET#

P

4

PM_APWROK_R

O

G

UC6

UC6

TC7SH08FU_SSOP5~D

TC7SH08FU_SSOP5~D

+1.05V_RUN

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

0.1U_0402_25V6

0.1U_0402_25V6

CC21

12

CXDP@CC21

CXDP@

+3.3V_ALW_PCH

+PCH_VCCDSW3_3

+PCH_VCCDSW3_3

PCH_RTCRST#<6>

POWER_SW#_MB<36,39>

CFG17
CFG16

CFG8
CFG9

CFG10
CFG11

CFG19
CFG18

CFG12
CFG13

CFG14
CFG15

XDP_RST#_R
XDP_DBRESET#

TDO_XDP
TRST#_XDP
PCH_JTAG_TDI
PCH_JTAG_TMS

RC113 1K_0402_5 %

RC113 1K_0402_5 %

CXDP@

CXDP@

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Doc ument Number Rev

Size Doc ument Number Rev

Size Doc ument Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

DSWODVREN - ON DIE DSW VR ENABLE

HIGH = ENABLED (DEFAULT)

LOW = DISABLED

SIO_SLP_S3#

SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_A#

SYS_RESET#

SIO_SLP_S0#

CFG17 <13>
CFG16 <13>

CFG8 <13>
CFG9 <13>

CFG10 <13>
CFG11 <13>

CFG19 <13>
CFG18 <13>

CFG12 <13>
CFG13 <13>

CFG14 <13>
CFG15 <13>

12

RC106 1K_0402_5 %

RC106 1K_0402_5 %

CXDP@

CXDP@

1 2

CFG3CFG3_R

TDO_XDP

51_0402_5 % RC117

51_0402_5 %

XDP_DBRESET#

1K_0402_5 %

1K_0402_5 %

CPU_XDP_TMS

51_0402_5 %

51_0402_5 %

CPU_XDP_TDI

51_0402_5 %

51_0402_5 %

CPU_XDP_PREQ#

51_0402_5 %

51_0402_5 %

CPU_XDP_TDO

51_0402_5 %

51_0402_5 %

CPU_XDP_TCLK

51_0402_5 %

51_0402_5 %

CPU_XDP_TRST#

51_0402_5 %

51_0402_5 %

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

CPU (4/12)

CPU (4/12)

CPU (4/12)

1

+RTC_CELL

330K_0402_5%

330K_0402_5%

RC78

RC78

1 2

DSWODVREN

JAPS1

JAPS1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

GND

20

GND

CONN@

CONN@

ACES_50506-01 841-P01

ACES_50506-01 841-P01

20130726 same as Goliad

PCH_PLTRST#_EC

+1.05V_RUN

12

@

@

RC117

+3.3V_RUN

12

RC122

RC122

+1.05V_RUN

@

@

12

RC124

RC124

@

@

12

RC125

RC125

@

@

12

RC126

12

RC127

RC127

12

RC128

RC128

@

@

12

RC129

RC129

LA-A972P

LA-A972P

LA-A972P

9 48Monday, March 17, 2014

9 48Monday, March 17, 2014

9 48Monday, March 17, 2014

1

0.1

0.1

0.1

5

D D

DDI1_LANE_N0<25>

DDI1_LANE_P0<25>

DDI1_LANE_N1<25>

DDI1_LANE_P1<25>

DDI1_LANE_N2<25>

DDI1_LANE_P2<25>
DDI1_LANE_N3<25>
DDI1_LANE_P3<25>

DDI2_LANE_N0<24>

DDI2_LANE_P0<24>

DDI2_LANE_N1<24>

DDI2_LANE_P1<24>

DDI2_LANE_N2<24>

DDI2_LANE_P2<24>
DDI2_LANE_N3<24>

C C

+3.3V_RUN

RPC15

RPC15

7
8

10K_8P4R_5%

10K_8P4R_5%

1 2

RC139@ 100K_0402_5%RC139@ 100K_0402_5%

RC140@ 1K_0402_5%RC140@ 1K_0402_5%

B B

3456
2
1

12

SIO_RCIN# <12,36>

CLKRUN# <36,9>

USH_DET# <12,27>
IRQ_SERIRQ <12,36>

ENVDD_PCH

PCH_GPIO53

DDI2_LANE_P3<24>

4

UC1A

UC1A

C54

DDI1_TXN0

C55

DDI1_TXP0

B58

DDI1_TXN1

C58

DDI1_TXP1

B55

DDI1_TXN2

A55

DDI1_TXP2

A57

DDI1_TXN3

B57

DDI1_TXP3

C51

DDI2_TXN0

C50

DDI2_TXP0

C53

DDI2_TXN1

B54

DDI2_TXP1

C49

DDI2_TXN2

B50

DDI2_TXP2

A53

DDI2_TXN3

B53

DDI2_TXP3

BDW-ULT-DDR3L_BGA1168

BDW-ULT-DDR3L_BGA1168

1 OF 19

1 OF 19

UC1I

UC1I

B8

T16@ PAD~DT16@ PAD~D

PCH_GPIO52<12>

EDP_BIA_PWM
PANEL_BKLEN
ENVDD_PCH

DGPU_PWROK
HDD_FALL_INT

PCH_GPIO53

EDP_BKLCTL

A9

EDP_BKLEN

C6

EDP_VDDEN

U6

PIRQA/GPIO77

P4

PIRQB/GPIO78

N4

PIRQC/GPIO79

N2

PIRQD/GPIO80

AD4

PME

U7

GPIO55

L1

GPIO52

L3

GPIO54

R5

GPIO51

L4

GPIO53

BDW-ULT-DDR3L_BGA1168

BDW-ULT-DDR3L_BGA1168

9 OF 19

9 OF 19

eDP SIDEBAND

eDP SIDEBAND

PCIE

PCIE

EDP_BIA_PWM<23>
PANEL_BKLEN<23>

ENVDD_PCH<23,36>

CONTACTLESS_DET#<27,7>

DGPU_PWROK<6>

HDD_FALL_INT<12>

PCH_GPIO80<12>

TOUCHPAD_INTR#<12>

BDW_ULT_DDR3L

BDW_ULT_DDR3L

BDW_ULT_DDR3L

BDW_ULT_DDR3L

3

C45

EDP_CPU_LANE_N0

EDP_TXN0

B46

EDP_CPU_LANE_P0

EDP_TXP0

A47

EDP_CPU_LANE_N1

EDP_TXN1

B47

EDP_CPU_LANE_P1

EDP_TXP1

C47

EDP_TXN2

C46

EDP_TXP2

A49

EDP_TXN3

EDPDDI

EDPDDI

DISPLAY

DISPLAY

EDP_TXP3

EDP_AUXN
EDP_AUXP

EDP_RCOMP

EDP_DISP_UTIL

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPB_AUXN
DDPC_AUXN

DDPB_AUXP

DDPC_AUXP

DDPB_HPD
DDPC_HPD

EDP_HPD

B49

A45
B45

D20
A43

B9
C9
D9
D11

C5
B6
B5
A6

C8
A8
D6

EDP_CPU_AUX#
EDP_CPU_AUX

EDP_COMP

CPU_DPB_CTRLCLK
CPU_DPB_CTRLDAT
CPU_DPC_CTRLCLK
CPU_DPC_CTRLDAT

CPU_DPB_AUX#
CPU_DPC_AUX#
CPU_DPB_AUX
CPU_DPC_AUX

DPB_HPD
DPC_HPD
EDP_CPU_HPD

2

EDP_CPU_LANE_N0 <23>
EDP_CPU_LANE_P0 <23>
EDP_CPU_LANE_N1 <23>
EDP_CPU_LANE_P1 <23>

EDP_CPU_AUX# <23>
EDP_CPU_AUX <23>

CPU_DPB_CTRLCLK <25>

CPU_DPB_CTRLDAT <25>

CPU_DPC_CTRLCLK <24>

CPU_DPC_CTRLDAT <24>

CPU_DPB_AUX# <25>
CPU_DPC_AUX# <24>
CPU_DPB_AUX <25>
CPU_DPC_AUX <24>

DPB_HPD <25>
DPC_HPD <24>

EDP_CPU_HPD <23>

1

COMPENSATION PU FOR eDP

RPC2

RPC2

1

8

2

7

3

6

4 5

2.2K_0804_8P4R_5%

2.2K_0804_8P4R_5%

RPC20

RPC20

1

8

2

7

3

6

4 5

100K_0804_8P4R_5%

100K_0804_8P4R_5%

12

12

12

EDP_COMP

CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.

CPU_DPB_CTRLDAT
CPU_DPB_CTRLCLK
CPU_DPC_CTRLCLK
CPU_DPC_CTRLDAT

CPU_DPB_AUX#
CPU_DPB_AUX
CPU_DPC_AUX
CPU_DPC_AUX#

EDP_CPU_HPD

DPB_HPD

+VCCIOA_OUT

RC13324.9_0402_1% RC13324.9_0402_1%

+3.3V_RUN

RC141100K_0402_5% RC14110 0K_0402_5%

RC142100K_0402_5% RC14210 0K_0402_5%

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

CPU (5/12)

CPU (5/12)

CPU (5/12)

LA-A972P

LA-A972P

LA-A972P

10 48Monday, March 17, 2014

10 48Monday, March 17, 2014

10 48Monday, March 17, 2014

1

0.1

0.1

0.1

5

4

3

2

1

PCIE for UMA

D D

GPU

GPU

PCIE_PRX_WIGIGTX_N5
PCIE_PRX_WIGIGTX_P5

PCIE_PTX_WIGIGRX_N5
PCIE_PTX_WIGIGRX_P5

PCIE_PRX_GLANTX_N3
PCIE_PRX_GLANTX_P3

PCIE_PTX_GLANRX_N3
PCIE_PTX_GLANRX_P3

PCIE_PRX_WLANTX_N4
PCIE_PRX_WLANTX_P4

PCIE_PTX_WLANRX_N4
PCIE_PTX_WLANRX_P4

PCIE_PRX_MMITX_N1
PCIE_PRX_MMITX_P1

PCIE_PTX_MMIRX_N1
PCIE_PTX_MMIRX_P1

PCH_PCIE_RCOMP

PCIE6

M2 3042
(HCA & SATA-Cache)

WIGIG

M2 3042
(HCA & SATA-Cache)

WIGIG

NA

4

PCIE_PRX_WIGIGTX_N5<30>

WIGIG --->

C C

10/100/1G LAN --->

WLAN (Mini Card 2)--->

MMI -->

+PCH_AUSB3PLL

B B

PCB

PCIE1 PCIE4

G12 UMA

SD card

G12 Entry NA

G14 DSC

G14 UMA

G14D_En

G14U_En

A A

SD card

SD card

SD card

SD card

5

PCIE3PCIE2

NA LOM

NA

LOM

NA

LOM

NA

LOM

NA

LOM

NA

LOM

PCIE_PRX_WIGIGTX_P5<30>

PCIE_PTX_WIGIGRX_N5<30>
PCIE_PTX_WIGIGRX_P5<30>

PCIE_PRX_GLANTX_N3<28>
PCIE_PRX_GLANTX_P3<28>

PCIE_PTX_GLANRX_N3<28>
PCIE_PTX_GLANRX_P3<28>

PCIE_PRX_WLANTX_N4<30>
PCIE_PRX_WLANTX_P4<30>

PCIE_PTX_WLANRX_N4<30>
PCIE_PTX_WLANRX_P4<30>

PCIE_PRX_MMITX_N1<29>
PCIE_PRX_MMITX_P1<29>

PCIE_PTX_MMIRX_N1<29>
PCIE_PTX_MMIRX_P1<29>

USB3RN4<31>

USB3RP4<31>

USB3TN4<31>

USB3TP4<31>

RC149 3.01K_0402_1 %RC149 3.01K_0402_ 1%

1 2

PCIE5

WIGIG

WLAN

WIGIGSD card

WLAN

WLAN

WLAN

WIGIG

WLAN

WLAN

WIGIG

UC1K

UC1K

F10

PERN5_L0

E10

PERP5_L0

C23

PETN5_L0

C22

PETP5_L0

F8

PERN5_L1

E8

PERP5_L1

B23

PETN5_L1

A23

PETP5_L1

H10

PERN5_L2

G10

PERP5_L2

B21

PETN5_L2

C21

PETP5_L2

E6

PERN5_L3

F6

PERP5_L3

B22

PETN5_L3

A21

PETP5_L3

G11

PERN3

F11

PERP3

C29

PETN3

B30

PETP3

F13

PERN4

G13

PERP4

B29

PETN4

A29

PETP4

G17

PERN1/USB3RN3

F17

PERP1/USB3RP3

C30

PETN1/USB3TN3

C31

PETP1/USB3TP3

F15

PERN2/USB3RN4

G15

PERP2/USB3RP4

B31

PETN2/USB3TN4

A31

PETP2/USB3TP4

E15

RSVD

E13

RSVD

A27

PCIE_RCOMP

B27

PCIE_IREF

BDW-ULT-DDR3L_BGA1168

BDW-ULT-DDR3L_BGA1168

11 OF 19

11 OF 19

BDW_ULT_DDR3L

BDW_ULT_DDR3L

PCIE USB

PCIE USB

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

USB2N0
USB2P0

USB2N1
USB2P1

USB2N2
USB2P2

USB2N3
USB2P3

USB2N4
USB2P4

USB2N5
USB2P5

USB2N6
USB2P6

USB2N7
USB2P7

USB3RN1
USB3RP1

USB3TN1
USB3TP1

USB3RN2
USB3RP2

USB3TN2
USB3TP2

USBRBIAS

USBRBIAS

OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43

AN8

USBP0-

AM8

USBP0+

AR7

USBP1-

AT7

USBP1+

AR8

USBP2-

AP8

USBP2+

AR10

USBP3-

AT10

USBP3+

AM15

USBP4-

AL15

USBP4+

AM13

USBP5-

AN13

USBP5+

AP11

USBP6-

AN11

USBP6+

AR13
AP13

G20
H20

C33
B34

E18
F18

B33
A33

AJ10

USBRBIAS

AJ11
AN10

RSVD

AM10

RSVD

AL3

USB_OC0#

AT1

USB_OC1#

AH2

USB_OC2#

AV3

USB_OC3#

USBP0- <31>
USBP0+ <31>

USBP1- <32>
USBP1+ <32>

USBP2- <30>
USBP2+ <30>

USBP3- <31>
USBP3+ <31>

USBP4- <23>
USBP4+ <23>

USBP5- <23>
USBP5+ <23>

USBP6- <27>
USBP6+ <27>

USB3RN1 <31>
USB3RP1 <31>

USB3TN1 <31>
USB3TP1 <31>

USB3RN2 <32>
USB3RP2 <32>

USB3TN2 <32>
USB3TP2 <32>

USB_OC0# <31>
USB_OC1# <12,32>
USB_OC2# <12,31>
USB_OC3# <12>

2

-----> Ext Port 1 Charge

-----> Ext Port 3

-----> WLAN/BT

-----> Ext Port 2

-----> Touch

-----> Camera

-----> USH

-----> WWAN

-----> Ext USB3 Port 1 Charge

-----> Ext USB3 Port 3

-----> USB Port0 (JUSB1)

-----> USB Port1 (JUSB3)

-----> USB Port3 (JUSB2)

PCH_GPIO44<12>

KB_DET#<12,37>

USBRBIAS

USB_OC0#

12

22.6_0402_1%

22.6_0402_1%

RC152

RC152

PCH_SMB_ALERT#<7>

CAD NOTE:
Route single-end 50-ohms and max 500-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15
mils.

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

CPU (6/12)

CPU (6/12)

CPU (6/12)

PCB

USB2 7

G12 UMA W WAN

G12 Entry

G14 DSC

G14 UMA

G14D_En

G14U_En

RPC19

RPC19

4 5
3
2
1

10K_8P4R_5%

10K_8P4R_5%

LA-A972P

LA-A972P

LA-A972P

NA

WWAN

WWAN

NA

NA

+3.3V_ALW_PCH

6
7
8

11 48Monday, March 17, 2014

11 48Monday, March 17, 2014

11 48Monday, March 17, 2014

1

0.1

0.1

0.1

5

4

3

2

1

+PCH_VCCDSW3_3

+3.3V_RUN

D D

+3.3V_RUN

+3.3V_ALW_PCH

C C

B B

@

@

12

RC153 10K_0402_5%RC153 10K_0402_5%

RC155 100K_0402_5%RC155 100K_0402_5%

RC156 100K_0402_5%RC156 100K_0402_5%

RC245 100K_0402_5%RC245 100K_0402_5%

RC174 100K_0402_5%RC174 100K_0402_5%

RC175 100K_0402_5%RC175 100K_0402_5%

RC171

LAN_WAKE#

12

MPHYP_PWR_EN

12

SIO_EXT_SCI#

1 2

RPC10

RPC10

4 5
3
2
1

10K_8P4R_5%

10K_8P4R_5%

RPC5

RPC5

4 5
3
2
1

10K_8P4R_5%

10K_8P4R_5%

RPC7

RPC7

4 5
3
2
1

10K_8P4R_5%

10K_8P4R_5%

6
7

SLATE_MODE

8

SIO_EXT_SMI#

6

PCH_GPIO9

7

MEDIACARD_RST#

8

MEDIACARD_IRQ#

6
7
8

PCH_GPIO57

12

PCH_GPIO59

12

3.3V_CAM_EN#

12

NFC_IRQ

12

MPHYP_PWR_EN

10K_0402_5%RC171

10K_0402_5%

TPM_PIRQ#

RC247 10K_0402_5%RC247 10K_0402_5%

PCH_NFC_RST for Goliad

USB_OC2# <11,31>
PCH_GPIO46 <12>

PCH_GPIO73 <7>

USB_OC3# <11>
SIO_EXT_WAKE# <12,36>
USB_OC1# <11,32>

+3.3V_RUN

12

1K_0402_5%

1K_0402_5%

PM_LANPHY_ENABLE<28,9>

RC176@

RC176@

SIO_EXT_WAKE#<12,36>

PCH_GPIO16<7>

TPM_PIRQ#<27>

LAN_WAKE#<28,36>

MEDIACARD_IRQ#<29>

@ PAD~D

@ PAD~D

TOUCH_PANEL_INTR#<23>

MPHYP_PWR_EN<38>
KB_DET#<11,37>

@ PAD~D

@ PAD~D

T21

T21

3.3V_CAM_EN#<23>

SIO_EXT_SMI#<36>

PCH_GPIO46<12>

HDD_DEVSLP<20>

SIO_EXT_SCI#<36>

PCH_GPIO66

BDW_ULT_DDR3L

UC1J

UC1J

+3.3V_RUN

10K_0402_5%

10K_0402_5%

12

RC302@

RC302@

10K_0402_5%

10K_0402_5%

12

RC303

RC303

P1

BMBUSY/GPIO76

AU2

GPIO8

AM7

LAN_PHY_PWR_CTRL/GPIO12

AD6

GPIO15

Y1

GPIO16

T3

GPIO17

AD5

GPIO24

AN5

GPIO27

AD7

GPIO28

AN3

GPIO26

AG6

GPIO56

AP1

GPIO57

AL4

GPIO58

AT5

GPIO59

AK4

GPIO44

AB6

GPIO47

U4

GPIO48

Y3

GPIO49

P3

GPIO50

Y2

HSIOPC/GPIO71

AT3

GPIO13

AH4

GPIO14

AM4

GPIO25

AG5

GPIO45

AG3

GPIO46

AM3

GPIO9

AM2

GPIO10

P2

DEVSLP0/GPIO33

C4

SDIO_POWER_EN/GPIO70

L2

DEVSLP1/GPIO38

N5

DEVSLP2/GPIO39

V2

SPKR/GPIO81

BDW-ULT-DDR3L_BGA1168

BDW-ULT-DDR3L_BGA1168

10 OF 19

10 OF 19

DIMM_DETDIMM_DET

PCH_GPIO76
SIO_EXT_WAKE# SIO_RCIN#

HOST_ALERT1_R_N

TPM_PIRQ#

LAN_WAKE#

NFC_IRQ

MEDIACARD_RST#
PCH_GPIO57
SLATE_MODE

PCH_GPIO59
PCH_GPIO44

PCH_GPIO44<11>

DIMM_DET

SPKR<21>

PCH_GPIO49

TOUCH_PANEL_INTR#

MPHYP_PWR_EN
KB_DET#

PCH_GPIO14

3.3V_CAM_EN#
SIO_EXT_SMI#

PCH_GPIO9
PCH_GPIO10

SIO_EXT_SCI#
SPKR

T22

T22

T27@ PAD~DT27@ PAD~D

BDW_ULT_DDR3L

GPIO

GPIO

+3.3V_ALW_PCH

1K_0402_5%

1K_0402_5%

12

RC179

RC179

HOST_ALERT1_R_N

SERIAL IO

SERIAL IO

CPU/

CPU/
MISC

MISC

THRMTRIP

RCIN/GPIO82

SERIRQ

PCH_OPI_RCOMP

GSPI0_CS/GPIO83

GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86

GSPI1_CS/GPIO87

GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89

GSPI_MOSI/GPIO90
UART0_RXD/GPIO91

UART0_TXD/GPIO92
UART0_RTS/GPIO93
UART0_CTS/GPIO94

UART1_RXD/GPIO0

UART1_TXD/GPIO1
UART1_RST/GPIO2
UART1_CTS/GPIO3

I2C0_SDA/GPIO4

I2C0_SCL/GPIO5
I2C1_SDA/GPIO6
I2C1_SCL/GPIO7

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69

RSVD
RSVD

+3.3V_RUN

D60
V4
T4
AW15
AF20
AB21

R6
L6
N6
L8
R7
L5
N7
K2
J1
K3
J2
G1
K4
G2
J3
J4
F2
F3
G4
F1
E3
F4
D3
E4
C3
E2

1K_0402_5%

1K_0402_5%

12

RC180@

RC180@

H_THERMTRIP#_R

IRQ_SERIRQ
PCH_OPI_COMP

GC6_EVENT#_Q
GPU_GC6_FB_EN
PCH_GPIO85
BBS_BIT
PCH_GPIO87

3.3V_TP_EN

CPPE#
CPUSB#

FFS_INT2
LCD_CBL_DET#

I2C0_SDA
I2C0_SCL
I2C1_SDA_VMM
I2C1_SCL_VMM
USH_DET#
CAM_MIC_CBL_DET#
PCH_GPIO66
PCH_GPIO67
PCH_GPIO68
PCH_GPIO69

SPKR

SIO_RCIN# <10,36>

IRQ_SERIRQ <10,36>

T109@PAD~DT109@PAD~D

3.3V_TS_EN <23>

3.3V_HDD_EN <20>

LCD_CBL_DET# <23>

USH_DET# <10,27>
CAM_MIC_CBL_DET# <23>

12

RC161@0_0402_5% RC161@ 0_0402_5%

H_THERMTRIP# <36>

PCH_GPIO52<10>

HDD_FALL_INT<10>
WIGIGCLK_REQ#<30,7>
TOUCHPAD_INTR#<10>

SATA2_PCIE6_L1<6>

+1.05V_VCCST

RPC17

RPC17

7
8

10K_8P4R_5%

10K_8P4R_5%

RPC16

RPC16

7
8

10K_8P4R_5%

10K_8P4R_5%

RPC3

RPC3

7
8

10K_8P4R_5%

10K_8P4R_5%

RPC4

RPC4

7
8

10K_8P4R_5%

10K_8P4R_5%

RPC8

RPC8

1
2
3
4 5

2.2K_0804_8P4R_5%

2.2K_0804_8P4R_5%

RPC9

RPC9

7
8

10K_8P4R_5%

10K_8P4R_5%

1 2

RC17849.9_0402_1% RC17849.9_0402_1%

12

RC251K_0402_5% RC251K_ 0402_5%

+3.3V_RUN

3456
2
1

12

RC160100K_0402_5% RC160100K_0402_5%

12

RC158100K_0402_5% RC158100K_0402_5%

12

RC16310K_0402_5% RC16310 K_0402_5%

12

RC16410K_0402_5% RC16410K_0402_5%

3456
2
1

3456
2
1

3456
2
1

8
7
6

3456
2
1

H_THERMTRIP#

WLANCLK_REQ#<30,7>
PCH_GPIO80<10>

PCH_GPIO76

CPPE#

FFS_INT2

PCH_GPIO67

PCH_GPIO68

CAM_MIC_CBL_DET#

PCH_GPIO69
GC6_EVENT#_Q
PCH_GPIO87

TOUCH_PANEL_INTR#

3.3V_TP_EN
GPU_GC6_FB_EN

LCD_CBL_DET#
CPUSB#

3.3V_TS_EN
PCH_GPIO85

I2C1_SDA_VMM
I2C1_SCL_VMM
I2C0_SCL
I2C0_SDA

PCH_OPI_COMP

HIGH
LOW(DEFAULT)

A A

ENABLE
DISABLE

DIMM Detect

HIGH
LOW

1 DIMM
2 DIMM

TLS CONFIDENTIALITYTOP-BLOCK SWAP OVERRIDE

HIGH
LOW(DEFAULT)

ENABLE
DISABLE

No Reboot on TCO Timer expiration

HIGH
LOW(DEFAULT)

ENABLE
DISABLE

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

CPU (7/12)

CPU (7/12)

CPU (7/12)

LA-A972P

LA-A972P

LA-A972P

12 48Monday, March 17, 2014

12 48Monday, March 17, 2014

12 48Monday, March 17, 2014

1

0.1

0.1

0.1

5

D D

4

3

2

1

UC1S

UC1S

AC60

CFG0

CFG0<9>

CFG1

CFG1<9>
CFG2<9>
CFG3<9>

CFG4

CFG4<9>
CFG5<9>
CFG6<9>
CFG7<9>

CFG8

CFG8<9>

CFG9

CFG9<9>

CFG10

CFG10<9>
CFG11<9>
CFG12<9>
CFG13<9>

C C

B B

SAFE MODE BOOT

CFG10

A A

CFG10 CFG4

1K_0402_1%

1K_0402_1%

12

RC188@

RC188@

1: POWER FEATURES ACTIVATED DURING
RESET
0: POWER FEATURES (ESPECIALLY CLOCK
GATINE ARE NOT ACTIVATED

5

CFG14<9>
CFG15<9>

CFG16<9>
CFG18<9>
CFG17<9>
CFG19<9>

CFG_RCOMP

TDI_IREF

12

CFG_RCOMP

RC185 49.9_0402_1%RC185 49.9_0402 _1%

1 2

TDI_IREF

RC186 8.2K_0402_1%RC186 8.2K_0402_1%

NO SVID PROTOCOL CAPABLE VR CONNECTED

CFG9

CFG0

AC62

CFG1

AC63

CFG2

AA63

CFG3

AA60

CFG4

Y62

CFG5

Y61

CFG6

Y60

CFG7

V62

CFG8

V61

CFG9

V60

CFG10

U60

CFG11

T63

CFG12

T62

CFG13

T61

CFG14

T60

CFG15

AA62

CFG16

U63

CFG18

AA61

CFG17

U62

CFG19

V63

CFG_RCOMP

A5

RSVD

E1

RSVD

D1

RSVD

J20

RSVD

H18

RSVD

B12

TD_IREF

BDW-ULT-DDR3L_BGA1168

BDW-ULT-DDR3L_BGA1168

19 OF 19

19 OF 19

CFG9

1: VRS support SVID protocol are present
0:No VR support SVID is present
The chip will not generate(OR Respond to)
SVID activity

4

BDW_ULT_DDR3L

RESERVED

RESERVED

RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP

RSVD_TP

PROC_OPI_RCOMP

AV63
AU63

C63
C62
B43

RSVD

A51
B51

L60

N60

RSVD

W23

RSVD

Y22

RSVD

AY15

PROC_OPI_RCOMP

AV62

RSVD

D58

RSVD

P22

VSS

N21

VSS

P20

RSVD

R20

RSVD

T28@PAD~D T28@PAD~D
T29@PAD~D T29@PAD~D

T30@PAD~D T30@PAD~D
T31@PAD~D T31@PAD~D

T33@PAD~D T33@PAD~D
T34@PAD~D T34@PAD~D

T35@PAD~D T35@PAD~D

EAR-STALL/NOT STALL RESET SEQUENCE AFTER PCU PLL IS LOCKE

CFG0

CFG0

1K_0402_1%

1K_0402_1%

12

RC183@

RC183@

1:(Default) Normal Operation; No stall
0:Lane Reversed

CFG1

1K_0402_1%

1K_0402_1%

12

RC184@

RC184@

PCH/PCH LESS MODE SELECTION

1:(Default) Normal Operation

CFG1

0:Lane Reversed

PROC_OPI_RCOMP

12

1K_0402_1%

1K_0402_1%

RC189@

RC189@

ALLOW THE USE OF NOA ON LOCKED UNITS

CFG8

1 2

RC18749.9_040 2_1% RC18749.9_0402_1%

CFG8

1K_0402_1%

1K_0402_1%

12

RC190@

RC190@

1: Enable(Default): Noa will be disable in
locked units and enable in un-locked
units

0: Enable Noa will be available pegardless of
the locking of the unit

Display Port Presence Strap

1 : Disabled; No Physical Display Port
attached to Embedded Display Port

CFG4

0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

1K_0402_5%

1K_0402_5%

12

RC191

RC191

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

CPU (8/12)

CPU (8/12)

CPU (8/12)

LA-A972P

LA-A972P

LA-A972P

13 48Monday, March 17, 2014

13 48Monday, March 17, 2014

13 48Monday, March 17, 2014

1

0.1

0.1

0.1

BDW_ULT_DDR3L

CFG STRAPS for CPU

5

D D

C C

B B

4

DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
DC_TEST_AY60
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
TP_DC_TEST_B2
DC_TEST_A3_B3
DC_TEST_A61_B61

DC_TEST_B62_B63

DC_TEST_C1_C2

3

1

12

RC192@0_0402_5% RC192@0_04 02_5%

BDW_ULT_DDR3L

UC1Q

UC1Q

AY2

DAISY_CHAIN_NCTF_AY2

AY3

DAISY_CHAIN_NCTF_AY3

AY60

DAISY_CHAIN_NCTF_AY60

AY61

DAISY_CHAIN_NCTF_AY61

AY62

DAISY_CHAIN_NCTF_AY62

B2

DAISY_CHAIN_NCTF_B2

B3

DAISY_CHAIN_NCTF_B3

B61

DAISY_CHAIN_NCTF_B61

B62

DAISY_CHAIN_NCTF_B62

B63

DAISY_CHAIN_NCTF_B63

C1

DAISY_CHAIN_NCTF_C1

C2

DAISY_CHAIN_NCTF_C2

BDW-ULT-DDR3L_BGA1168

BDW-ULT-DDR3L_BGA1168

17 OF 19

17 OF 19

Package Daisy Chain:

1.B2-PKG-C1-PCB-C2-PKG-B3-PCB-A3-PKG-A4

2.A62-PKG-A61-PCB-B61-PKG-B62-PCB-B63-PKG-A60

3.AY60-PKG-AW61-PCB-AY61-PKG-AW62-PCB-AY62-PKG-AW63

4.AW1-PKG-AW3-PCB-AY3-PKG-AW2-PCB-AY2-PKG-AV1

UC1R

UC1R

AT2

RSVD

AU44

RSVD

AV44

RSVD

D15

RSVD

F22

RSVD

H22

RSVD

J21

RSVD

BDW-ULT-DDR3L_BGA1168

BDW-ULT-DDR3L_BGA1168

18 OF 19

18 OF 19

BDW_ULT_DDR3L

3

BDW_ULT_DDR3L

BDW_ULT_DDR3L

DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4

DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_A62

DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
DAISY_CHAIN_NCTF_AW2
DAISY_CHAIN_NCTF_AW3

DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63

12

RC195@0_0402_5% RC195@0_04 02_5%

A3
A4

A60
A61
A62
AV1
AW1
AW2
AW3
AW61
AW62
AW63

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

DC_TEST_A3_B3
DC_TEST_A4

DC_TEST_A60
DC_TEST_A61_B61
DC_TEST_A62
DC_TEST_AV1
DC_TEST_AW1
DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
DC_TEST_AW63

N23
R23
T23
U10

AL1
AM11
AP7
AU10
AU15
AW14
AY14

2

2

12

RC193@0_0402_5% RC193@0_04 02_5%

12

RC194@0_0402_5% RC194@0_04 02_5%

4

1

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

CPU (9/12)

CPU (9/12)

CPU (9/12)

LA-A972P

LA-A972P

LA-A972P

14 48Monday, March 17, 2014

14 48Monday, March 17, 2014

14 48Monday, March 17, 2014

1

0.1

0.1

0.1

5

4

3

2

1

ESD Request

+1.05V_RUN +VCCIO_OUT

+1.05V_RUN

D D

C C

12

RC197

RC197
150_0402_5%

150_0402_5%

CPU_PWR_DEBUG#

10K_0402_5%

10K_0402_5%

12

@

@

RC198

RC198

H_VR_EN

RESET_OUT#<36,9>

SVID ALERT

VIDALERT_N<45>

B B

SVID DATA

VIDSOUT<45>

VCC_SENSE

VCCSENSE<45>

A A

CAD Note: RC209 SHOULD BE PLACED CLOSE TO CPU

RESISTOR STUFFING OPTIONS ARE
PROVIDED FOR TESTING PURPOSES

12

H_VR_READY

RC2011.5K_040 2_5% RC2011.5K_0402_ 5%

1

2

3

+1.05V_VCCST

75_0402_1%

75_0402_1%

12

RC204

RC204

+1.05V_VCCST

110_0402_1%

110_0402_1%

12

RC208

RC208

VIDSOUT

+VCC_CORE

12

12

RC196 0_0603_5%@RC196 0 _0603_5%@

+1.05V_VCCST

10K_0402_5%

10K_0402_5%

12

RC199@

RC199@

UC8

UC8

NC

A

GND

74AUP1G07GW_TSSOP5

74AUP1G07GW_TSSOP5

100_0402_1%

100_0402_1%

RC209

RC209

+3.3V_ALW

5

1 2

VCC

CC35@ 0.1U_0402_2 5V6CC35@ 0.1U_0402_25V6

4

H_VCCST_PWRGD

Y

CAD Note: Place the PU resistors close to CPU
RC204 close to CPU 300 ­1500mils

12

H_CPU_SVIDALRT#

RC20743_04 02_5% RC20743_0402_5%

CAD Note: Place the PU resistors close to CPU
RC208close to CPU 300 - 1500mils

VCCSENSE

+VCC_CORE

+1.05V_RUN

+1.05V_RUN +3.3V_RUN

+1.05V_VCCST

1K_0402_5%

1K_0402_5%

RC202

RC202

1 2

1 2

CC23

CC23

1 2

CC79

CC79

1 2

CC84

CC84

1 2

CC85

CC85

H_VCCST_PWRGD

1

@EMC@

@EMC@

2

CC24

CC24
100P_0402_50V8J

100P_0402_50V8J

+1.05V_RUN +1.05V_VCCST

22U_0603_6.3V6M@EMC@

22U_0603_6.3V6M@EMC@

22U_0603_6.3V6M@EMC@

22U_0603_6.3V6M@EMC@

22U_0603_6.3V6M@EMC@

22U_0603_6.3V6M@EMC@

22U_0603_6.3V6M@EMC@

22U_0603_6.3V6M@EMC@

H_VCCST_PWRGD<9>
H_VR_EN<45>
H_VR_READY<45>

PJP23

@PJP23

@

1 2

PAD-OPEN1x1m

PAD-OPEN1x1m

+1.35V_MEM

+VCC_CORE

+1.35V_MEM

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

@

@

12

12

CC25

CC25

+1.35V_MEM

+VCC_CORE

VCCSENSE

+VCCIO_OUT
+VCCIOA_OUT

H_CPU_SVIDALRT#
VIDSCLK

VIDSCLK<45>

VIDSOUT
H_VCCST_PWRGD
H_VR_EN
H_VR_READY

CPU_PWR_DEBUG#<9>

T74@

T74@

PAD~D

PAD~D

T75@

T75@

PAD~D

PAD~D

T76@

T76@

PAD~D

PAD~D

T77@

T77@

PAD~D

PAD~D

+1.05V_VCCST

+VCC_CORE

22U_0603_6.3V6M

22U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

CC36

CC36

12

12

@

@

CC37

CC37

@

@

CC26

CC26

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

12

CC27

CC27

L59
J58

AH26

AJ31
AJ33

AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50

F59
N58

AC58

E63

AB23

A59
E20

AD23

AA23
AE59

L62
N63
L63
B59
F60
C59

D63
H59
P62
P60
P61
N59
N61

T59
AD60
AD59

AA59
AE60
AC59
AG58

U59
V59

AC22
AE22
AE23

AB57
AD57
AG57

C24
C28
C32

VDDQ DECOUPLING

10U_0603_6.3V6M

10U_0603_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

12

12

CC28

CC28

UC1L

UC1L

RSVD
RSVD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VCC
RSVD
RSVD

VCC_SENSE
RSVD
VCCIO_OUT
VCCIOA_OUT
RSVD
RSVD
RSVD

VIDALERT
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY

VSS
PWR_DEBUG
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

VCCST
VCCST
VCCST

VCC
VCC
VCC
VCC
VCC
VCC

BDW-ULT-DDR3L_BGA1168

BDW-ULT-DDR3L_BGA1168

12 OF 19

12 OF 19

CC29

CC29

10U_0603_6.3V6M

10U_0603_6.3V6M

@

@

12

CC30

CC30

BDW_ULT_DDR3L

BDW_ULT_DDR3L

10U_0603_6.3V6M

10U_0603_6.3V6M

12

HSW ULT POWER

HSW ULT POWER

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

12

CC31

CC31

10U_0603_6.3V6M

@

@

12

12

CC34

CC32

CC32

CC34

CC33

CC33

+VCC_CORE

C36

VCC

C40

VCC

C44

VCC

C48

VCC

C52

VCC

C56

VCC

E23

VCC

E25

VCC

E27

VCC

E29

VCC

E31

VCC

E33

VCC

E35

VCC

E37

VCC

E39

VCC

E41

VCC

E43

VCC

E45

VCC

E47

VCC

E49

VCC

E51

VCC

E53

VCC

E55

VCC

E57

VCC

F24

VCC

F28

VCC

F32

VCC

F36

VCC

F40

VCC

F44

VCC

F48

VCC

F52

VCC

F56

VCC

G23

VCC

G25

VCC

G27

VCC

G29

VCC

G31

VCC

G33

VCC

G35

VCC

G37

VCC

G39

VCC

G41

VCC

G43

VCC

G45

VCC

G47

VCC

G49

VCC

G51

VCC

G53

VCC

G55

VCC

G57

VCC

H23

VCC

J23

VCC

K23

VCC

K57

VCC

L22

VCC

M23

VCC

M57

VCC

P57

VCC

U57

VCC

W57

VCC

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

CPU (10/12)

CPU (10/12)

CPU (10/12)

LA-A972P

LA-A972P

LA-A972P

1

15 48Monday, March 17, 2014

15 48Monday, March 17, 2014

15 48Monday, March 17, 2014

0.1

0.1

0.1

5

PAD-OPEN1x1m

PAD-OPEN1x1m

+1.05V_MODPHY +1.05V_MODPHY_PCH

D D

+1.05V_MODPHY

C C

CC68 place near AA21

VCCAPLL
S0 Iccmax = 57mA

B B

+3.3V_ALW

@

@

PJP51

PJP51

1 2

CC40 place near K9;
CC44 place near L10
CC43 place near M9

VCCHSIO
S0 Iccmax = 1.838A

LC1

LC1

1 2

2.2UH_LQM2MPN2R2NG0L_3 0%

2.2UH_LQM2MPN2R2NG0L_3 0%

CC47 place near B18

VCCUSB3PLL
S0 Iccmax = 41mA

LC2

LC2

1 2

2.2UH_LQM2MPN2R2NG0L_3 0%

2.2UH_LQM2MPN2R2NG0L_3 0%

CC56 place near B11

VCCSATA3PLL
S0 Iccmax = 42mA

LC3

LC3

1 2

2.2UH_LQM2MPN2R2NG0L_3 0%

2.2UH_LQM2MPN2R2NG0L_3 0%

CC97 place near AH10

intel DG Rev 1.2 , page 500

47.3 Boot Strap Capacitor

1 2

RC216 0_ 0402_5%@ RC216 0_0402_ 5%@

1 2

RC217@ 0_04 02_5%RC2 17@ 0_0402 _5%

CC80 place near AH10

VCCDSW3_3
S0 Iccmax = 114mA

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

@

@

12

12

12

CC44

CC44

CC43

CC43

CC40

CC40

+PCH_AUSB3PLL

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

CC51

CC51

CC47

CC47

+PCH_ASATA3PLL+1.05V_MODPHY

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

CC56

CC56

CC55

CC55

12

12

+V1.05S_APLLOPI+1.05V_RUN

100U_1206_6.3V6M

100U_1206_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

12

12

CC67

CC67

CC68

CC68

+PCH_VCCDSW+PCH_VCCDSW3_3

1 2

CC97 0.47U_04 02_10V6K@ CC97 0.47 U_0402_10V6K@

+PCH_VCCDSW3_3+3.3V_ALW_PCH

1U_0402_6.3V6K

1U_0402_6.3V6K

@

@

12

CC80

CC80

+3.3V_ALW_PCH

12

0.1U_0402_10V7K

0.1U_0402_10V7K

+3.3V_ALW_PCH

CC57

CC57

4

+1.05V_RUN

1U_0402_6.3V6K

1U_0402_6.3V6K

@

@

12

CC53

CC53

CC57 place near AH14

CC63 place near AC9

22U_0603_6.3V6M

22U_0603_6.3V6M

+3.3V_RUN

CC63

CC63

12

2.2UH_LQM2MPN2R2NG0L_3 0%

2.2UH_LQM2MPN2R2NG0L_3 0%

CC78 place near J18

VCCCLK
S0 Iccmax = 200mA

+1.05V_RUN

2.2UH_LQM2MPN2R2NG0L_3 0%

2.2UH_LQM2MPN2R2NG0L_3 0%

CC82 place near A20

VCCACLKPLL
S0 Iccmax = 31mA

CC64 place near V8

2013/06/10 refer 6L_WP chnage to +3.3V_M, 6/14 change back

22U_0603_6.3V6M

22U_0603_6.3V6M

12

CC64

CC64

+1.05V_RUN

1U_0402_6.3V6K

1U_0402_6.3V6K

12

12

CC70

CC70

LC4

LC4

1 2

12

LC5

LC5

1 2

+1.05V_MODPHY_PCH

+PCH_AUSB3PLL

+PCH_ASATA3PLL

+V1.05S_APLLOPI

+PCH_VCCDSW3_3

+PCH_VCC1P05

+PCH_VCCACLKPLL

1U_0402_6.3V6K

1U_0402_6.3V6K

CC70 close to Pin J17
CC71 close to Pin R21

CC71

CC71

+3.3V_ALW_PCH

+PCH_VCC1P05+1.05V_RUN

100U_1206_6.3V6M

100U_1206_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

12

CC77

CC77

+PCH_VCCACLKPLL

100U_1206_6.3V6M

100U_1206_6.3V6M

CC81

CC81

12

12

3

+1.05V_RUN+1.05V_M

330U_D3_2.5VY_R6M

330U_D3_2.5VY_R6M

@EMC@

@EMC@

@EMC@

@EMC@

330U_D3_2.5VY_R6M

330U_D3_2.5VY_R6M

330U_D3_2.5VY_R6M

1

+

+

2

THERMAL SENSOR

THERMAL SENSOR

SUS OSCILLATOR

SUS OSCILLATOR

330U_D3_2.5VY_R6M

1

+

+

CC41

CC41

CC42

CC42

2

RTC

SERIAL IO

SERIAL IO

RTC

SPI

SPI

CORE

CORE

USB2

USB2

AH11

VCCSUS3_3

VCCRTC
DCPRTC

VCCSPI

VCCASW
VCCASW

VCC1_05
VCC1_05
VCC1_05
VCC1_05

VCC1_05
DCPSUSBYP
DCPSUSBYP

VCCASW

VCCASW

VCCASW

DCPSUS1
DCPSUS1

VCCTS1_5

VCC3_3
VCC3_3

VCCSDIO
VCCSDIO

DCPSUS4

VCC1_05

VCC1_05

RSVD

+PCH_RTC_VCCSUS3_3

AG10
AE7

+DCPRRTC

CC52 0.1U_04 02_10V7KCC52 0.1U_0402_10V7K

Y8

AG14

+1.05V_M

AG13

J11
H11
H15
AE8
AF22
AG19

+PCH_VCCDSW

AG20
AE9

CC61 CC62 place near AE9

AF9
AG8
AD10
AD8

J15

+1.5V_RUN

K14
K16

2013/06/10 refer 6L_WP chnage to float,6/14 change back

U8

CC69 place near U8

T9

AB8

AC20
AG16

CC72 place near AG16

AG17

1 2

@

@

12

CC39

CC39

+

+

BDW_ULT_DDR3L

GPIO/LPC

GPIO/LPC

LPT LP POWER

LPT LP POWER

BDW_ULT_DDR3L

HSIO

HSIO

OPI

OPI

USB3

USB3

HDA

HDA

VRM

VRM

UC1M

UC1M

K9

VCCHSIO

L10

VCCHSIO

M9

VCCHSIO

N8

VCC1_05

P9

VCC1_05

B18

VCCUSB3PLL

B11

VCCSATA3PLL

Y20

RSVD

AA21

VCCAPLL

W21

VCCAPLL

J13

DCPSUS3

AH14

VCCHDA

AH13

DCPSUS2

AC9

VCCSUS3_3

AA9

VCCSUS3_3

AH10

VCCDSW3_3

V8

VCC3_3

W9

VCC3_3

J18

VCCCLK

K19

VCCCLK

A20

VCCACLKPLL

J17

VCCCLK

R21

VCCCLK

T21

VCCCLK

K18

RSVD

M20

RSVD

V21

RSVD

AE20

VCCSUS3_3

AE21

VCCSUS3_3

BDW-ULT-DDR3L_BGA1168

BDW-ULT-DDR3L_BGA1168

13 OF 19

13 OF 19

CC78

CC78

1U_0402_6.3V6K

1U_0402_6.3V6K

CC82

CC82

2

CC59 and CC60 place near
J11; CC58 place near AE8

+3.3V_RUN

+1.05V_RUN

1U_0402_6.3V6K

1U_0402_6.3V6K

CC72

CC72

12

CC48,CC49, CC50 place near AG10

12

CC54 place near Y8

+1.05V_M

12

22U_0603_6.3V6M

22U_0603_6.3V6M

@

@

1U_0402_6.3V6K

1U_0402_6.3V6K

CC62

CC62

1

12

CC61

CC61

2

1U_0402_6.3V6K

1U_0402_6.3V6K

12

CC69

CC69

1

+RTC_CELL

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_10V7K

0.1U_0402_10V7K

12

12

@

@

CC49

CC49

CC50

CC50

CC48

CC48

+3.3V_M

0.1U_0402_10V7K

0.1U_0402_10V7K

@

@

12

CC54

CC54

+1.05V_RUN

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

CC59

CC59

12

CC58

CC58

+PCH_VCCDSW

10U_0603_6.3V6M

10U_0603_6.3V6M

12

CC60

CC60

RC211 5.11_040 2_1%RC211 5.11_ 0402_1%

CC65 place near AG19

+3.3V_RUN

0.1U_0402_10V7K

0.1U_0402_10V7K

12

CC66

CC66

+PCH_RTC_VCCSUS3_3 +3.3V_ALW_ PCH

1U_0402_6.3V6K

1U_0402_6.3V6K

12

CC73

CC73

CC73 place near AH11

VCCSUS3_3
S0 Iccmax = 63mA

Reminder below power rail need isolation for layout refer
attach file for more detail that from Intel review feedback.

12

+PCH_VCCDSW_R

1U_0402_6.3V6K

1U_0402_6.3V6K

12

CC65

CC65

12

RC212 @0_0402 _5% RC212@0_0402_5%

+3.3V_ALW

12

RC213@0_0402_5% RC213 @0_0402 _5%

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Doc ument Number Rev

Size Doc ument Number Rev

Size Doc ument Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

CPU (11/12)

CPU (11/12)

CPU (11/12)

LA-A972P

LA-A972P

LA-A972P

1

16 48Monday, Marc h 17, 2014

16 48Monday, Marc h 17, 2014

16 48Monday, Marc h 17, 2014

0.1

0.1

0.1

5

D D

BDW_ULT_DDR3L

BDW_ULT_DDR3L

UC1N

UC1N

A11

VSS

A14

VSS

A18

VSS

A24

VSS

A28

VSS

A32

VSS

A36

VSS

A40

VSS

A44

VSS

A48

VSS

A52

VSS

A56

VSS

AA1

VSS

AA58

VSS

AB10

VSS

AB20

VSS

AB22

VSS

AB7

VSS

AC61

VSS

AD21

VSS

AD3

VSS

AD63

VSS

AE10

VSS

AE5

VSS

AE58

C C

B B

AF11
AF12
AF14
AF15
AF17
AF18

AG1
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
AJ13
AJ14
AJ23
AJ25
AJ27
AJ29

BDW-ULT-DDR3L_BGA1168

BDW-ULT-DDR3L_BGA1168

14 OF 19

14 OF 19

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

4

BDW_ULT_DDR3L

BDW_ULT_DDR3L

UC1O

UC1O

AJ35

VSS

AJ39

VSS

AJ41

VSS

AJ43

VSS

AJ45

VSS

AJ47

VSS

AJ50

VSS

AJ52

VSS

AJ54

VSS

AJ56

VSS

AJ58

VSS

AJ60

VSS

AJ63

VSS

AK23

VSS

AK3

VSS

AK52

VSS

AL10

VSS

AL13

VSS

AL17

VSS

AL20

VSS

AL22

VSS

AL23

VSS

AL26

VSS

AL29

VSS

AL31

VSS

AL33

VSS

AL36

VSS

AL39

VSS

AL40

VSS

AL45

VSS

AL46

VSS

AL51

VSS

AL52

VSS

AL54

VSS

AL57

VSS

AL60

VSS

AL61

VSS

AM1

VSS

AM17

VSS

AM23

VSS

AM31

VSS

AM52

VSS

AN17

VSS

AN23

VSS

AN31

VSS

AN32

VSS

AN35

VSS

AN36

VSS

AN39

VSS

AN40

VSS

AN42

VSS

AN43

VSS

AN45

VSS

AN46

VSS

AN48

VSS

AN49

VSS

AN51

VSS

AN52

VSS

AN60

VSS

AN63

VSS

AN7

VSS

AP10

VSS

AP17

VSS

AP20

VSS

AP22
AP23
AP26
AP29

AP3
AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49

AR5
AR52

AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63

AU1
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59

AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55

BDW-ULT-DDR3L_BGA1168

BDW-ULT-DDR3L_BGA1168

15 OF 19

15 OF 19

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

3

AV59

VSS

AV8

VSS

AW16

VSS

AW24

VSS

AW33

VSS

AW35

VSS

AW37

VSS

AW4

VSS

AW40

VSS

AW42

VSS

AW44

VSS

AW47

VSS

AW50

VSS

AW51

VSS

AW59

VSS

AW60

VSS

AY11

VSS

AY16

VSS

AY18

VSS

AY22

VSS

AY24

VSS

AY26

VSS

AY30

VSS

AY33

VSS

AY4

VSS

AY51

VSS

AY53

VSS

AY57

VSS

AY59

VSS

AY6

VSS

B20

VSS

B24

VSS

B26

VSS

B28

VSS

B32

VSS

B36

VSS

B4

VSS

B40

VSS

B44

VSS

B48

VSS

B52

VSS

B56

VSS

B60

VSS

C11

VSS

C14

VSS

C18

VSS

C20

VSS

C25

VSS

C27

VSS

C38

VSS

C39

VSS

C57

VSS

D12

VSS

D14

VSS

D18

VSS

D2

VSS

D21

VSS

D23

VSS

D25

VSS

D26

VSS

D27

VSS

D29

VSS

D30

VSS

D31

VSS

UC1P

UC1P

D33

VSS

D34

VSS

D35

VSS

D37

VSS

D38

VSS

D39

VSS

D41

VSS

D42

VSS

D43

VSS

D45

VSS

D46

VSS

D47

VSS

D49

VSS

D5

VSS

D50

VSS

D51

VSS

D53

VSS

D54

VSS

D55

VSS

D57

VSS

D59

VSS

D62

VSS

D8

VSS

E11

VSS

E17

VSS

F20

VSS

F26

VSS

F30

VSS

F34

VSS

F38

VSS

F42

VSS

F46

VSS

F50

VSS

F54

VSS

F58

VSS

F61

VSS

G18

VSS

G22

VSS

G3

VSS

G5

VSS

G6

VSS

G8

VSS

H13

VSS

BDW-ULT-DDR3L_BGA1168

BDW-ULT-DDR3L_BGA1168

16 OF 19

16 OF 19

2

BDW_ULT_DDR3L

BDW_ULT_DDR3L

VSS_SENSE

1

H17

VSS

H57

VSS

J10

VSS

J22

VSS

J59

VSS

J63

VSS

K1

VSS

K12

VSS

L13

VSS

L15

VSS

L17

VSS

L18

VSS

L20

VSS

L58

VSS

L61

VSS

L7

VSS

M22

VSS

N10

VSS

N3

VSS

P59

VSS

P63

VSS

R10

VSS

R22

VSS

R8

VSS

T1

VSS

T58

VSS

U20

VSS

U22

VSS

U61

VSS

U9

VSS

V10

VSS

V3

VSS

V7

VSS

W20

VSS

W22

VSS

Y10

VSS

Y59

VSS

Y63

VSS

V58

VSS

AH46

VSS

V23

VSS

E62
AH16

VSS

VSSSENSE <45>

1 2

VSSSENSE

RC218 100_ 0402_1%RC218 10 0_0402_1%

CAD Note: RC218 SHOULD BE PLACED CLOSE TO CPU

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

CPU (12/12)

CPU (12/12)

CPU (12/12)

LA-A972P

LA-A972P

LA-A972P

1

17 48Monday, March 17, 2014

17 48Monday, March 17, 2014

17 48Monday, March 17, 2014

0.1

0.1

0.1

5

4

3

2

1

DDR_A_DQS#[0..7]<8>

DDR_A_D[0..63]<8>

DDR_A_DQS[0..7]<8>

D D

C C

B B

A A

DDR_A_MA[0..15]<8>

+1.35V_MEM

1U_0402_6.3V6K

1U_0402_6.3V6K

12

CD7

CD7

+1.35V_MEM

10U_0603_6.3V6M

10U_0603_6.3V6M

CD12

CD12

12

+0.675V_DDR_VTT

12

Layout Note:
Place near JDIMM1

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

12

12

CD2

CD2

CD3

CD3

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD13@

CD13@

CD14

CD14

12

12

Layout Note:
Place near
JDIMM1.203,204

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

12

CD24

CD24

CD25

CD25

5

Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

12

CD8

CD8

10U_0603_6.3V6M

10U_0603_6.3V6M

CD15

CD15

12

0.1U_0402_25V6

0.1U_0402_25V6

12

CD26

CD26

1U_0402_6.3V6K

12

12

12

12

CD9

CD9

CD4

CD4

CD11

CD11

CD10

CD10

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

@

@

CD17

CD17

CD16

CD16

12

12

0.1U_0402_25V6

0.1U_0402_25V6

12

12

CD27

CD27

330U_D3_2.5VY_R6M

330U_D3_2.5VY_R6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

12

CD20

CD20

CD18

CD18

CD19

CD19

12

12

+

+

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

12

CD29

CD29

CD28

CD28

1 2

RD15@ 0_0402_5 %RD15@ 0_0402_5%

1 2

RD16@ 0_0402_5 %RD16@ 0_0402_5%

+DIMM1_VREF_DQ

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

0.1U_0402_25V6

0.1U_0402_25V6

12

DDR_CKE0_DIMMA<8>

DDR_CS1_DIMMA#<8>

+3.3V_RUN

4

DDR_A_D8

12

CD5

CD5

CD1

CD1

DDR_A_D14 DDR_A_D15
DDR_A_D10 DDR_A_D11

DDR_A_D29
DDR_A_D28

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D31

DDR_A_D44 DDR_A_D45

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D43
DDR_A_D47

DDR_A_D51
DDR_A_D50

DDR_A_D49
DDR_A_D48

DDR_CKE0_DIMMA DDR_CKE1_DIMMA

DDR_A_BS2

DDR_A_BS2<8>

DDR_A_MA9

DDR_A_MA8

M_CLK_DDR0 M_CL K_DDR1

M_CLK_DDR0<8>

M_CLK_DDR#0 M_CLK_DDR#1

DDR_A_MA10

DDR_A_BS0

DDR_A_BS0<8>

DDR_A_WE#

DDR_A_WE#<8>

DDR_A_CAS#

DDR_A_CAS#<8>

DDR_A_MA13

DDR_CS1_DIMMA#

DDR_A_D0
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D6

DDR_A_D21
DDR_A_D20

DDR_A_D17
DDR_A_D16

DDR_A_D36 DDR_A_D37

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D38

DDR_A_D62
DDR_A_D58

DDR_A_D60
DDR_A_D61

+0.675V_DDR_VTT

0.1U_0402_25V6

0.1U_0402_25V6

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

@

@

12

12

CD31

CD31

CD32

CD32

H=4mm

Reverse Type

JDIMM1

JDIMM1

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

LCN_DAN06-K4406-0103

LCN_DAN06-K4406-0103

20130730 SP07000LT00 CIS Link OK

CONN@

CONN@

DQS0#

RESET#

DQS3#

VREF_CA

DQS5#

DQS7#

EVENT#

BOSS2

3

+1.35V_MEM+1.3 5V_MEM

2

VSS

4

DQ4

6

DQ5

8

VSS

10
12

DQS0

14

VSS

16

DQ6

18

DQ7

20

VSS

22

DQ12

24

DQ13

26

VSS

28

DM1

30
32

VSS

34

DQ14

36

DQ15

38

VSS

40

DQ20

42

DQ21

44

VSS

46

DM2

48

VSS

50

DQ22

52

DQ23

54

VSS

56

DQ28

58

DQ29

60

VSS

62
64

DQS3

66

VSS

68

DQ30

70

DQ31

72

VSS

74

CKE1

76

VDD

78

A15

80

A14

82

VDD

84

A11

86

A7

88

VDD

90

A6

92

A4

94

VDD

96

A2

98

A0

100

VDD

102

CK1

104

CK1#

106

VDD

108

BA1

110

RAS#

112

VDD

114

S0#

116

ODT0

118

VDD

120

ODT1

122

NC

124

VDD

126
128

VSS

130

DQ36

132

DQ37

134

VSS

136

DM4

138

VSS

140

DQ38

142

DQ39

144

VSS

146

DQ44

148

DQ45

150

VSS

152
154

DQS5

156

VSS

158

DQ46

160

DQ47

162

VSS

164

DQ52

166

DQ53

168

VSS

170

DM6

172

VSS

174

DQ54

176

DQ55

178

VSS

180

DQ60

182

DQ61

184

VSS

186
188

DQS7

190

VSS

192

DQ62

194

DQ63

196

VSS

198
200

SDA

202

SCL

204

VTT

206

GND2

208

DDR_A_D9
DDR_A_D12DDR_A_D13

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D25
DDR_A_D24

DDR3_DRAMRST#

DDR_A_D27
DDR_A_D26

DDR_A_D40DDR_A_D41

DDR_A_D42
DDR_A_D46

DDR_A_D52
DDR_A_D53

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D54
DDR_A_D55

DDR_A_MA15
DDR_A_MA14

DDR_A_MA11DDR_A_MA12
DDR_A_MA7

DDR_A_MA6
DDR_A_MA4DDR_A_MA5

DDR_A_MA2DDR_A_MA3
DDR_A_MA0DDR_A_MA1

DDR_A_BS1
DDR_A_RAS#

DDR_CS0_DIMMA#
M_ODT0

M_ODT1

DDR_A_D5
DDR_A_D4

DDR_A_D3
DDR_A_D7

DDR_A_D18
DDR_A_D19

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D22
DDR_A_D23

DDR_A_D32DDR_A_D33

DDR_A_D35
DDR_A_D39

DDR_A_D63
DDR_A_D59

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D56
DDR_A_D57

+0.675V_DDR_VTT

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

0.1U_0402_25V6

0.1U_0402_25V6

CD6@

CD6@

12

CAD NOTE
PLACE THE CAP NEAR TO DIMM RESET PIN

DDR_CKE1_DIMMA <8>

M_CLK_DDR1 <8>

M_CLK_DDR#1 <8>M_CLK_DDR#0<8>

DDR_A_BS1 <8>

DDR_A_RAS# <8>

DDR_CS0_DIMMA# <8>

+SM_VREF_CA_DIMM

0.1U_0402_25V6

0.1U_0402_25V6

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

CD22

CD22

CD23

CD23

12

12

DDR_XDP_WAN_SMBD AT <19,7, 9>

DDR_XDP_WAN_SMBC LK <19, 7,9>

+DIMM1_VREF_DQ

+5V_ALW

+1.35V_MEM

220K_0402_5%

220K_0402_5%

12

RD9

RD9

0.675V_DDR_VTT_ON

2M_0402_5%

2M_0402_5%

RD14@

RD14@

1 2

DDR_PG_CTRL<9>

2

+1.35V_MEM

470_0402_5%

470_0402_5%

12

RD2

RD2

1 2

RD3@ 0_0402 _5%RD3@ 0_0 402_5%

+1.35V_MEM

1.8K_0402_1%

1.8K_0402_1%

12

RD4

RD4

1 2

RD5 2_0 402_1%RD5 2_040 2_1%

1.8K_0402_1%

1.8K_0402_1%

12

RD6

RD6

24.9_0402_1%

24.9_0402_1%
RD7

RD7

DDR3L SODIMM ODT GENERATION

QD1

QD1
L2N7002WT1G_ SC-70-3

L2N7002WT1G_ SC-70-3

1 3

1

2

3

1 2

RD10 66.5_ 0402_1%RD10 66.5_0402_1%

1 2

RD11 66.5_ 0402_1%RD11 66.5_0402_1%

1 2

RD12 66.5_ 0402_1%RD12 66.5_0402_1%

1 2

RD13 66.5_ 0402_1%RD13 66.5_0402_1%

+1.35V_MEM

5

1 2

CD30@ 0.1 U_0402_25V6CD30@ 0.1U_0402_ 25V6

4

0.675V_DDR_VTT_ON

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

M_ODT0

M_ODT1

D

S

D

S

G

G

2

UD1

UD1

NC

VCC

A

Y

GND

74AUP1G07GW_TSS OP5

74AUP1G07GW_TSS OP5

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size Doc ument Number Rev

Size Doc ument Number Rev

Size Doc ument Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

DDR3_DRAMRST#_CPU <9>DDR3_DRAMRST#<19>

+SM_VREF_DQ0

0.022U_0402_16V7K

0.022U_0402_16V7K

CD21

CD21

12

12

DDR3L

DDR3L

DDR3L

LA-A972P

LA-A972P

LA-A972P

1

M_ODT2 <19>

M_ODT3 <19>

0.675V_DDR_VTT_ON <42>

18 48Monday, Marc h 17, 2014

18 48Monday, Marc h 17, 2014

18 48Monday, Marc h 17, 2014

0.1

0.1

0.1

5

DDR_B_DQS#[0..7]<8>

DDR_B_D[0..63]<8>

DDR_B_DQS[0..7]<8>

+1.35V_MEM

12

+1.35V_MEM

12

DDR_B_MA[0..15]<8>

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

12

CD38

CD38

CD37

CD37

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD45

CD45

CD46@

CD46@

12

+0.675V_DDR_VTT

0.1U_0402_25V6

0.1U_0402_25V6

CD57

CD57

12

Layout Note:
Place near JDIMM2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

12

12

12

CD39

CD39

CD40

CD40

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD47@

CD47@

CD48

CD48

12

12

12

Layout Note:
Place near
JDIMM2.203,204

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

CD58

CD58

CD59

CD59

12

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

CD41

CD41

10U_0603_6.3V6M

10U_0603_6.3V6M

CD49

CD49

0.1U_0402_25V6

0.1U_0402_25V6

CD60

CD60

1U_0402_6.3V6K

1U_0402_6.3V6K

12

12

12

CD43

CD43

CD42

CD42

CD44

CD44

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

12

CD52

CD52

CD50

CD50

CD51

CD51

12

12

12

+

+

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD61

CD61

CD62

CD62

12

12

D D

C C

B B

A A

Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket

330U_D3_2.5VY_R6M

330U_D3_2.5VY_R6M

CD53

CD53

+3.3V_RUN

4

+DIMM2_VREF_DQ

+3.3V_RUN

12

RD27@ 0_0402_5%RD27@ 0_0402_5%

3

H=4mm

Reverse Type

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

12

12

CD33

CD33

DDR_CKE2_DIMMB<8>

DDR_B_BS2<8>

M_CLK_DDR2<8>
M_CLK_DDR#2<8>

DDR_B_BS0<8>

DDR_B_WE#<8>

DDR_B_CAS#<8>

DDR_CS3_DIMMB#<8>

12

0_0402_5%

0_0402_5%

RD28@

RD28@

+1.35V_MEM +1.35V_MEM

DDR_B_D8 DDR_B_D9

0.1U_0402_25V6

0.1U_0402_25V6

DDR_B_D14

CD34

CD34

DDR_B_D10
DDR_B_D11

DDR_B_D28
DDR_B_D29

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D26
DDR_B_D27

DDR_B_D40
DDR_B_D41

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D46
DDR_B_D42

DDR_B_D56
DDR_B_D57

DDR_B_D59
DDR_B_D58

DDR_CKE2_DIMMB DDR_CKE3_DIMMB

DDR_B_BS2

DDR_B_MA9

DDR_B_MA8

M_CLK_DDR2 M_CLK_DDR3
M_CLK_DDR#2 M_CLK_DDR#3

DDR_B_MA10
DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

DDR_B_MA13
DDR_CS3_DIMMB#

DDR_B_D4

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D3
DDR_B_D7

DDR_B_D21
DDR_B_D20

DDR_B_D22
DDR_B_D23

DDR_B_D36 DDR_B_D37

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D35
DDR_B_D39

DDR_B_D52
DDR_B_D49

DDR_B_D48
DDR_B_D53

+0.675V_DDR_VTT +0.675V_DDR_VTT

0.1U_0402_25V6

0.1U_0402_25V6

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

@

@

12

12

CD64

CD64

CD63

CD63

JDIMM2

JDIMM2

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

LCN_DAN06-K4406-0103

LCN_DAN06-K4406-0103

CONN@

CONN@

DQS0#

RESET#

DQS3#

VREF_CA

DQS5#

DQS7#

EVENT#

BOSS2

2

VSS

4

DDR_B_D12

DQ4

6

DQ5

8

VSS

10

DDR_B_DQS#1

12

DDR_B_DQS1

DQS0

14

VSS

16

DDR_B_D13

DQ6

18

DDR_B_D15

DQ7

20

VSS

22

DDR_B_D25

DQ12

24

DDR_B_D24

DQ13

26

VSS

28

DM1

30

DDR3_DRAMRST#

32

VSS

34

DDR_B_D30

DQ14

36

DDR_B_D31

DQ15

38

VSS

40

DDR_B_D45

DQ20

42

DDR_B_D44

DQ21

44

VSS

46

DM2

48

VSS

50

DDR_B_D47

DQ22

52

DDR_B_D43

DQ23

54

VSS

56

DDR_B_D61

DQ28

58

DDR_B_D60

DQ29

60

VSS

62

DDR_B_DQS#7

64

DDR_B_DQS7

DQS3

66

VSS

68

DDR_B_D63

DQ30

70

DDR_B_D62

DQ31

72

VSS

74

CKE1

76

VDD

78

DDR_B_MA15

A15

80

DDR_B_MA14

A14

82

VDD

84

DDR_B_MA11DDR_B_MA12

A11

86

DDR_B_MA7

A7

88

VDD

90

DDR_B_MA6

A6

92

DDR_B_MA4DDR_B_MA5

A4

94

VDD

96

DDR_B_MA2DDR_B_MA3

A2

98

DDR_B_MA0DDR_B_MA1

A0

100

VDD

102

CK1

104

CK1#

106

VDD

108

DDR_B_BS1

BA1

110

DDR_B_RAS#

RAS#

112

VDD

114

DDR_CS2_DIMMB#

S0#

116

M_ODT2

ODT0

118

VDD

120

ODT1

122

NC

124

VDD

126
128

VSS

130

DDR_B_D5

DQ36

132

DDR_B_D0DDR_B_D1

DQ37

134

VSS

136

DM4

138

VSS

140

DDR_B_D2

DQ38

142

DDR_B_D6

DQ39

144

VSS

146

DDR_B_D16

DQ44

148

DDR_B_D17

DQ45

150

VSS

152

DDR_B_DQS#2

154

DDR_B_DQS2

DQS5

156

VSS

158

DDR_B_D19

DQ46

160

DDR_B_D18

DQ47

162

VSS

164

DQ52

166

DDR_B_D32DDR_B_D33

DQ53

168

VSS

170

DM6

172

VSS

174

DDR_B_D34

DQ54

176

DDR_B_D38

DQ55

178

VSS

180

DDR_B_D51

DQ60

182

DDR_B_D55

DQ61

184

VSS

186

DDR_B_DQS#6

188

DDR_B_DQS6

DQS7

190

VSS

192

DDR_B_D54

DQ62

194

DDR_B_D50

DQ63

196

VSS

198
200

SDA

202

SCL

204

VTT

206

GND2

208

0.1U_0402_25V6

0.1U_0402_25V6

12

CD35@

CD35@

CAD NOTE
PLACE THE CAP NEAR TO DIMM RESET PIN

DDR_CKE3_DIMMB <8>

M_CLK_DDR3 <8>

M_CLK_DDR#3 <8>

DDR_B_BS1 <8>
DDR_B_RAS# <8>

DDR_CS2_DIMMB# <8>

M_ODT2 <18>

M_ODT3 <18>

+SM_VREF_CA_DIMM

12

DDR_XDP_WAN_SMBDAT <18,7,9>

DDR_XDP_WAN_SMBCLK <18,7,9>

DDR3_DRAMRST# <18>

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

0.1U_0402_25V6

0.1U_0402_25V6

CD55

CD55

12

2

+1.35V_MEM

1.8K_0402_1%

1.8K_0402_1%

12

RD18

RD18

RD19 2_0402_1%RD19 2_0402_1%

1.8K_0402_1%

1.8K_0402_1%

12

RD20

RD20

+1.35V_MEM

1.8K_0402_1%

1.8K_0402_1%

12

RD22

+DIMM2_VREF_DQ

CD56

CD56

RD22

1 2

RD23 2_0402_1%RD23 2_0402_1%

1.8K_0402_1%

1.8K_0402_1%

12

RD24

RD24

1 2

1

+SM_VREF_CA+SM_VREF_CA_DIMM

0.022U_0402_16V7K

0.022U_0402_16V7K

CD36

CD36

12

24.9_0402_1%

24.9_0402_1%

12

RD21

RD21

+SM_VREF_DQ1

0.022U_0402_16V7K

0.022U_0402_16V7K

CD54

CD54

12

24.9_0402_1%

24.9_0402_1%

12

RD25

RD25

20130730 SP070 00LT00 CIS Link OK

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

DDR3L

DDR3L

DDR3L

LA-A972P

LA-A972P

LA-A972P

1

19 48Monday, March 17, 2014

19 48Monday, March 17, 2014

19 48Monday, March 17, 2014

0.1

0.1

0.1

5

D D

4

3

2

1

+3.3V_HDD source

C C

B B

A A

+3.3V_RUN

12

12

RN6

@

RN6

@

10K_0402_5%

10K_0402_5%

3.3V_HDD_EN

RN7

RN7
10K_0402_5%

10K_0402_5%

3.3V_HDD_EN<12>

+3.3V_RUN

+5V_ALW

+3.3V_HDD

0.1U_0402_25V6

0.1U_0402_25V6

CN1

CN1

1

2

Place near JMINI3

UZ11

UZ11

3

ON

1

7

VIN

2

VIN

4

VBIAS

6

CT

470P_0402_50V7K

470P_0402_50V7K

1

CZ65

CZ65

TPS22967DSGR_SON8_2X2

TPS22967DSGR_SON8_2X2

2

0.1U_0402_25V6

0.1U_0402_25V6

@

@

CN2

CN2

1

2

+3.3V_HDD_UZ11

VOUT

8

VOUT

5

GND

9

GND

PCH_PLTRST#_EC<27,30,36,9>

CLK_PCI_LPDEBUG<36,7>

SATA_PRX_DTX_P1<6>
SATA_PRX_DTX_N1<6>

SATA_PTX_DRX_N1<6>
SATA_PTX_DRX_P1<6>

+3.3V_HDD

1 2

0.1U_0402_10V7K

0.1U_0402_10V7K

1 2

@

@

PJP4@

PJP4@

+3.3V_HDD

PAD-OPEN1x3m

PAD-OPEN1x3m

CZ64

CZ64

@

@

1 2

HDD_DEVSLP

RN1 10K_0402_5%

RN1 10K_0402_5%

PCH_PLTRST#_EC

12
12

CN3 .01U_0402_16V7KCN3 .01U_0402_16V7K
CN4 .01U_0402_16V7KCN4 .01U_0402_16V7K

CN5 .01U_0402_16V7KCN5 .01U_0402_16V7K12
CN6 .01U_0402_16V7KCN6 .01U_0402_16V7K12

HDD_DET#<6>

Mini mSATA H=4

+3.3V_HDD +3.3V_HDD

SATA_PRX_DTX_P1_C
SATA_PRX_DTX_N1_C

SATA_PTX_DRX_N1_C
SATA_PTX_DRX_P1_C

HDD_DET#

JMINI3

CONN@

JMINI3

CONN@

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

GND2

LCN_DAN08-52406-0500

LCN_DAN08-52406-0500

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

LPC_LFRAME#
LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0

HDD_DEVSLP

LPC_LFRAME# <36,7>

LPC_LAD3 <36,7>
LPC_LAD2 <36,7>
LPC_LAD1 <36,7>
LPC_LAD0 <36,7>

HDD_DEVSLP <12>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

HDD CONN

HDD CONN

HDD CONN

LA-A972P

LA-A972P

LA-A972P

1

20 56Monday, March 17, 2014

20 56Monday, March 17, 2014

20 56Monday, March 17, 2014

0.1

0.1

0.1

2

place close to pin26

+VDDA_AVDD1

0.1U_0402_25V6

26
40

36

+VDDA_PVDD

41
46

+5V_RUN_PVDD

13

JD1

14
15

32

AUD_OUT_L

33

AUD_OUT_R

42
43

INT_SPK_L-

45

INT_SPK_R+

44

INT_SPK_R-

2
3
48

Place CA29 close to Codec

37
35

CA29 1U_060 3_10V6KCA29 1U_0603 _10V6K

CA35 2.2U_06 03_6.3V6KCA35 2.2U_0 603_6.3V6K

28
12

AUD_PC_BEEP

34

CA49 1U_060 3_10V6KCA49 1U_0603 _10V6K

25
38

+MIC1_VREFO_R

+MIC1_VREFO_L

4.7U_0603_6 .3V6K

4.7U_0603_6 .3V6K

4.7U_0603_6 .3V6K

4.7U_0603_6 .3V6K

+3.3V_RUN_AUDIO

@EMC@ CA3

@EMC@

@EMC@ CA4

@EMC@

680P_0402_50V7K

680P_0402_50V7K

1

CA3

CA4

2

0.1U_0402_25V6

12

CA8

CA8

1 2
1 2

RA7 2 4.9_0402_1 %RA7 24.9_04 02_1%
RA8 2 4.9_0402_1 %RA8 24.9_04 02_1%

1 2

RA14EMC@ 33_0402_ 5%RA14EMC@ 33_0402 _5%

12

12

12

21

4.7K_0402_5%

4.7K_0402_5%

RA24

RA24

1 2

12

RA1

RA1
10K_0402_ 5%

10K_0402_ 5%

EMC@

EMC@

2

3

3

DA1

DA1

L03ESDL5V0CC3-2_SOT23-3

L03ESDL5V0CC3-2_SOT23-3

1

1W x 1ch, 4 ohm (Transducer spec is 8Ohm/0.5Watt per unit, there are t wo transducer units in one speaker box.)

Internal Speakers Header

40 mils trace keep 20 mil spacing

EMC@

EMC@

INT_SPK_L+
INT_SPK_L­INT_SPK_R+
INT_SPK_R-

1000P_0402_50V7K

1000P_0402_50V7K

12

CA22@EMC@

CA22@EMC@

Close to UA1

B B

Place closely to Pin 13.

A A

LA6 BLM15PX 330SN1D_2P

LA6 BLM15PX 330SN1D_2P

EMC@

EMC@

LA7 BLM15PX 330SN1D_2P

LA7 BLM15PX 330SN1D_2P

EMC@

EMC@

LA8 BLM15PX 330SN1D_2P

LA8 BLM15PX 330SN1D_2P

EMC@

EMC@

LA9 BLM15PX 330SN1D_2P

LA9 BLM15PX 330SN1D_2P

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

12

12

12

CA19@EMC@

CA19@EMC@

CA24@EMC@

CA24@EMC@

CA23@EMC@

CA23@EMC@

1 2
1 2
1 2
1 2

10P_0402_50V8J

10P_0402_50V8J

CA33@EMC@

CA33@EMC@

JD1

2

3

1

Close to UA1 pin6

PCH_AZ_CODEC_BITCLK

33_0402_5%

33_0402_5%

12

RA17@EMC@

RA17@EMC@

12

Verb table configures as 1 JD mode with
internal 47K pull high to save external rBOM.

13

D

D

2

G

QA1

G

QA1

S

S

L2N7002WT1G_SC-70-3

L2N7002WT1G_SC-70-3

L03ESDL5V0CC3-2_SOT23-3

L03ESDL5V0CC3-2_SOT23-3

@EMC@

@EMC@

DA6

DA6

+3.3V_RUN_AUDIO

0.1U_0402_25V6

0.1U_0402_25V6

12

INT_SPKR_L+
INT_SPKR_L­INT_SPKR_R+

INT_SPKR_R+
INT_SPKR_R-

L03ESDL5V0CC3-2_SOT23-3

L03ESDL5V0CC3-2_SOT23-3

2

3

@EMC@

@EMC@

DA7

DA7

1

+MIC2_VREF_OUT

AUD_NB_MUTE#<35>

AUD_HP_NB_SENSE <35>

CA41

@

CA41

@

Add for solve
pop noise and
detect issue

20130730 CIS L ink OK

CONN@

CONN@

JSPK1

JSPK1

1

1

2

2

3

3

4

4

5

GND

6

GND

ACES_50279-00 40N-001

ACES_50279-00 40N-001

RA5 2 .2K_0402_ 5%RA5 2.2K_0402_5%

RA6 2 .2K_0402_ 5%RA6 2.2K_0402_5%

SLEEVE & RING2 trace width require least
40mil and its length as short as possible.

RA18 10 K_0402_5%RA18 10K_ 0402_5%

Digital Mic (Goliad MLK no single Mic)

2

1 2

PCH_AZ_CODEC_BITCLK<6>

PCH_AZ_CODEC_SDOUT<6>

PCH_AZ_CODEC_SYNC<6>

PCH_AZ_CODEC_SDIN0<6>

PCH_AZ_CODEC_RST#<6>

12

12

+3.3V_RUN_AUDIO

RING2

SLEEVE

+3.3V_RUN_AUDIO

1U_0603_10V6K

1U_0603_10V6K

12

CA31

CA31

place at AGND and DGND plane

CA10,CA11 close to pin1

0.1U_0402_25V6

0.1U_0402_25V6

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

0.1U_0402_25V6

0.1U_0402_25V6

CA10

CA10

CA11

CA11

12

12

12

CA50

CA50

Place RA9 close to UA1

1 2

RA9 33_0402_5%RA9 33_0402_5%

+MIC2_VREF_OUT

10U_0603_6.3V6M

10U_0603_6.3V6M

RA44 100K_0402_5%RA44 100K_0402_5%

12

12

12

CA51

CA51

1 2

@EMC@

@EMC@

RA35

RA35

0_0402_5%

0_0402_5%

1 2

@EMC@

@EMC@

RA36

RA36

0_0402_5%

0_0402_5%

1 2

@EMC@

@EMC@

RA37

RA37

0_0402_5%

0_0402_5%

SLEEVE

+RTC_CELL

100K_0402_5%

100K_0402_5%

12

RA21

RA21

34

5

6

QA2B

QA2B

1

QA2A

QA2A

DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

Realtek feedback
Prevent the Noise from Combo Jack
while system entry into S3 / S4 /S5

UA1

UA1

1

DVDD

9

DVDD-IO

RING2
SLEEVE

AUD_NB_MUTE#

1 2

PJP6@

PJP6@

EMC@ LA2

EMC@

EMC@ LA3

EMC@

6

BCLK

5

SDATA-OUT

10

SYNC

8

SDATA-IN

11

RESETB

21

LINE1-R(PORT-C-R)

22

LINE1-L(PORT-C-L)

30

LINE1-VREFO-R

31

LINE1-VREFO-L

23

LINE2-R(PORT-E-R)

24

LINE2-L(PORT-E-L)

16

MONO-OUT

29

MIC2-VREFO

17

MIC2-L(PORT-F-L)/RING

18

MIC2-R(PORT-F-R)/SLEEVE

19

MIC_CAP

20

NC

47

PDB

27

LDO1-CAP

39

LDO2-CAP

7

LDO3-CAP

4

DVSS

49

GND

ALC3234-CG_MQFN48 _6X6

ALC3234-CG_MQFN48 _6X6

1 2

LA10 BLM15PX3 30SN1D_2PEMC@ LA10 B LM15PX330SN1D _2PEMC@

1 2

LA2

1 2

LA3

1 2

LA11 BLM15PX3 30SN1D_2PEMC@ LA11 B LM15PX330SN1D _2PEMC@

SPDIFO/FRONT JD(JD3)/GPIO3

AUD_HP_OUT_L1AUD_HP_OUT_L

BLM15BD601S N1D_2P

BLM15BD601S N1D_2P

BLM15BD601S N1D_2P

BLM15BD601S N1D_2P

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

PCH_AZ_CODEC_BITCLK

PCH_AZ_CODEC_SDOUT

PCH_AZ_SDIN0_R

PCH_AZ_CODEC_RST#

MIC1_R
MIC1_L
+MIC1_VREFO_R
+MIC1_VREFO_L INT_SPK_L+

12

CA25 10U_06 03_6.3V6MCA25 10U_0603_6. 3V6M

1 2

@

@

RA41 0_04 02_5%

RA41 0_04 02_5%

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

12

CA53

CA53

CA52

CA52

@

@

RA40 0_04 02_5%

RA40 0_04 02_5%

1 2

PAD-OPEN1x2m

PAD-OPEN1x2m

RING2 RING2_R

AUD_HP_OUT_R AUD_HP_OUT_R1
SLEEVE

2

AUD_NB_MUTE#

AVDD1
AVDD2

CPVDD

PVDD1
PVDD2

HP/LINE1 JD(JD1)

MIC2/LINE2 JD(JD2)

HPOUT-L(PORT-I-L)

HPOUT-R(PORT-I-R)

SPK-OUT-L+

SPK-OUT-L­SPK-OUT-R+
SPK-OUT-R-

GPIO0/DMIC-DATA

GPIO1/DMIC-CLK

SPDIF-OUT/GPIO2

CBP
CBN

VREF

PCBEEP

CPVEE

AVSS1
AVSS2

CA43

CA43

1 2

MIC1_L

CA44

CA44

1 2

MIC1_R AUD_HP_OUT_R

@EMC@ CA1

@EMC@

@EMC@ CA2

@EMC@

680P_0402_50V7K

680P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K

1

1

1

CA1

CA2

2

2

2

EMI De-pop

12

RB751S40T1G_SOD523-2

RB751S40T1G_SOD523-2

2

1

10U_0603_6.3V6M

10U_0603_6.3V6M

CA9

CA9

DA4

DA4

4.7K_0402_5%

4.7K_0402_5%

RA25

RA25

EMC@

EMC@

DA2

DA2

L03ESDL5V0CC3-2_SOT23-3

L03ESDL5V0CC3-2_SOT23-3

1

LA5

LA5

1 2

BLM15PX600S N1D_2P

BLM15PX600S N1D_2P

place close to pin40

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

place close to pin36

1

CA16

CA16

2

AUD_HP_OUT_L
AUD_HP_OUT_R

AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width

DMIC0 <23>

DMIC_CLKDMIC_CLK_L

DMIC_CLK <23>

place close to pin12

12

CA27 0.1 U_0402_25V6CA27 0.1U_0402_25 V6

12

CA28 0.1 U_0402_25V6CA28 0.1U_0402_25 V6

RB751S40T1G_SOD523-2

RB751S40T1G_SOD523-2

21

DA5

DA5

1 2

AUD_HP_OUT_L

AUD_HP_NB_SENSE

EMC@

EMC@

2

3

DA3

DA3

12

L03ESDL5V0CC3-2_SOT23-3

L03ESDL5V0CC3-2_SOT23-3

RA2

RA2
100K_0402 _5%

100K_0402 _5%

1

1

+3.3V_RUN_AUDIO+5V_RUN_AUDIO +1. 5V_RUN +5V_RUN_AUDIO

12

12

0_0603_5%

0_0603_5%

0_0603_5%

0_0603_5%

RA3@

RA3@

RA4@

RA4@

+1.5V_RUN_AUDIO

0.1U_0402_25V6

0.1U_0402_25V6

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1

12

CA17

CA17

2

RA12 1K_04 02_5%RA12 1 K_0402_5%

RA13 1K_04 02_5%RA13 1 K_0402_5%

place close to pin41 place close to pin46

CA18

CA18

1 2

1 2

12

0.1U_0402_25V6

0.1U_0402_25V6

CA45

CA45

10U_0603_6.3V6M

10U_0603_6.3V6M

12

SPKR <12>

BEEP <36>

CA46

CA46

0.1U_0402_25V6

0.1U_0402_25V6

12

CA47

CA47

+MIC2_VREF_OUT

DMIC_CLK

12

place close to pin3

PJP9@

PJP9@

1 2

+5V_RUN

PAD-OPEN1X2m

PAD-OPEN1X2m

PJP10@

PJP10@

1 2

+3.3V_RUN +3.3V_RUN_AUDIO

PAD-OPEN1x1m

PAD-OPEN1x1m

HP-Out-Right Nokia-MIC

HP-Out-Left

Global Headset

Combo Jack

JHP1

JHP1

7
3

1

5

6

2
4

SINGA_2SJ3080-0 03111F

SINGA_2SJ3080-0 03111F

CONN@

CONN@

CA13 680P_04 02_50V7K

@EMC@

CA13 680P_04 02_50V7K

@EMC@

CA12 680P_04 02_50V7K

@EMC@

CA12 680P_04 02_50V7K

@EMC@

1

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

CIS Link OK

1

2

Place CA12 & CA13
close to Audio Jack

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Codec _ALC3235

Codec _ALC3235

Codec _ALC3235

LA-A972P

LA-A972P

LA-A972P

0_0805_5%

0_0805_5%

12

10U_0603_6.3V6M

10U_0603_6.3V6M

CA48

CA48

12

12

+5V_RUN_AUDIO

iPhone-MIC

Normal
Open

21 48Monday, Ma rch 17, 2014

21 48Monday, Ma rch 17, 2014

21 48Monday, Ma rch 17, 2014

RA39@

RA39@

1U_0603_10V4Z

1U_0603_10V4Z

@

@

CA26

CA26

22P_0402_50V8J

22P_0402_50V8J

@EMC@

@EMC@

CA30

CA30

0.1

0.1

0.1

2

B B

1

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

2

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

1

Title

Size Do cument Numbe r Rev

Size Do cument Numbe r Rev

Size Do cument Numbe r Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

DP 1.2 MST HUB

DP 1.2 MST HUB

DP 1.2 MST HUB

LA-A972P

LA-A972P

LA-A972P

22 48Monday, March 17, 201 4

22 48Monday, March 17, 201 4

22 48Monday, March 17, 201 4

0.1

0.1

0.1

5

ACES_50398-04 041-001

ACES_50398-04 041-001

D D

41

G1

42

G2

43

G3

44

G4

45

G5

JEDP1

JEDP1

CONN@

C C

Close to JEDP1.24~27

B B

CONN@

+BL_PWR_SRC +3.3V_RUN+3.3V_RUN +3.3V_TSP

0.1U_0603_50V7K

0.1U_0603_50V7K

12

@

@

CV7

CV7

BIA_PWM

4.7K_0402_5%

4.7K_0402_5%

12

RV1

RV1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

35

35

36

36

37

37

38

38

39

39

40

40

+LCDVDD

Close to JEDP1.11,12

DV1

DV1

1

BAT54CW_SOT323-3

BAT54CW_SOT323-3

+3.3V_TSP

TOUCH_PANEL_INTR# <12>

+3.3V_RUN
+3.3V_CAM

USBP5_D­USBP5_D+

CAM_MIC_CBL_DET# <12>

pin 15: LOOP_BACK

+BL_PWR_SRC

LV1

EMC@

LV1

EMC@

1 2

BLM15BB221SN1D_2P~D

DISP_ON

EDP_CPU_AUX#_C
EDP_CPU_AUX_C
EDP_CPU_LANE_P0_C
EDP_CPU_LANE_N0_C
EDP_CPU_LANE_P1_C
EDP_CPU_LANE_N1_C

0.1U_0402_25V6

0.1U_0402_25V6

12

3

EDP_BIA_PWM

2

BIA_PWM_EC

@

@

CV8

CV8

BLM15BB221SN1D_2P~D

EDP_CPU_HPD <10>

LCD_TST <36>

+LCDVDD

CV1 0.1U_0402_10V7KCV1 0.1U_040 2_10V7K
CV2 0.1U_0402_10V7KCV2 0.1U_040 2_10V7K
CV3 0.1U_0402_10V7KCV3 0.1U_040 2_10V7K
CV4 0.1U_0402_10V7KCV4 0.1U_040 2_10V7K
CV5 0.1U_0402_10V7KCV5 0.1U_040 2_10V7K
CV6 0.1U_0402_10V7KCV6 0.1U_040 2_10V7K

LCD_CBL_DET# <12>

+3.3V_CAM +3.3V_TSP

0.1U_0402_25V6

0.1U_0402_25V6

12

CZ1

CZ1

Close to JEDP1.33 Close to JEDP1.40 Close to JEDP1.1

EDP_BIA_PWM <10>

BIA_PWM_EC <36>

WebCAM

+3.3V_CAM +3.3V_RUN

3.3V_CAM_EN#<12>

change back to CCD_OFF at Goliad project

A A

USBP5+<11>

USBP5-<11>

1

5

LP2301ALT1G_SOT23- 3

LP2301ALT1G_SOT23- 3

EMC@

EMC@

LZ1

LZ1

1

2

443

DLW21HN900HQ2L_4P

DLW21HN900HQ2L_4P

QZ1

QZ1

123

D

D

2

3

G

G

S

S

USBP5_D+

USBP5_D-

BIA_PWM

@

@

4

DMIC0 <21>

DMIC_CLK <21>

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

12

12

CA5@EMC@

CA5@EMC@

CA6@EMC@

CA6@EMC@

223

3

1

1

ESD depop location

12
12
12
12
12
12

EDP_CPU_AUX# <10>

EDP_CPU_AUX <10>
EDP_CPU_LANE_P0 <10>
EDP_CPU_LANE_N0 <10>
EDP_CPU_LANE_P1 <10>
EDP_CPU_LANE_N1 <10>

3

USBP4_D­USBP4_D+

DV4

DV4

@EMC@

@EMC@

AZC199-02SPR7G_SOT23-3

AZC199-02SPR7G_SOT23-3

DLW21HN900HQ2L_4P

DLW21HN900HQ2L_4P

4

4

1

1

LV27

LV27

EMC@

EMC@

2

3

3

2

2

BATT_YELLOW_LED#<39>

BREATH_WHITE_LED#<39>

USBP4- <11>

USBP4+ <11>

BATT_WHITE_LED#<39>

PANEL_HDD_LED#<39>

+5V_ALW

LED CONN

CONN@

CONN@

JLED1

JLED1

GND2
GND1

6

6

5

5

4

4

3

3

2

2

1

1

ACES_50277-00 60N-001

ACES_50277-00 60N-001

8
7

1

20130822

For Touchscreen

+3.3V_RUN

0.1U_0402_25V6

DISP_ON

CV11

CV11

4.7K_0402_5%

4.7K_0402_5%

12

RV2

RV2

+PWR_SRC

0.1U_0402_25V6

12

@

@

CA7

CA7

DV2

DV2

1

BAT54CW_SOT323-3

BAT54CW_SOT323-3

S

S

4 5

100K_0402_5%

100K_0402_5%

12

RV4

RV4

PWR_SRC_ON

1 2

RV5 47K_0402_5%RV5 47 K_0402_5%

EN_INVPWR<36>

3

2

QV1

QV1

D

D

6

2
1

G

G

AO6405_TSOP6

AO6405_TSOP6

3

QV2

QV2

L2N7002WT1G_SC-70-3

L2N7002WT1G_SC-70-3

123

D

D

PANEL_BKLEN <10>

PANEL_BKEN_EC <35>

+BL_PWR_SRC

S

S

G

G

10K_0402_5%

10K_0402_5%

12

RV6

RV6

L2N7002WT1G_SC-70-3

L2N7002WT1G_SC-70-3

13

D

D

QV7

QV7

3.3V_TS_EN<12>

LCDVDD POWERBacklight POWER

0.1U_0603_50V7K

0.1U_0603_50V7K

12

CV12

CV12

LCD_VCC_TEST_EN<36>

ENVDD_PCH<10,36>

2

G

G

S

S

DV3

DV3

2

3

BAT54CW_SOT323-3

BAT54CW_SOT323-3

CV9@

CV9@

12

10U_0603_6.3V6M

10U_0603_6.3V6M

1

+LCDVDD

EN_LCDPWR

1 2

100K_0402_5%

100K_0402_5%

RV3

RV3

0.1U_0402_16V4Z

0.1U_0402_16V4Z

12

@

@

CZ2

CZ2

1000P_0402_50V7K

1000P_0402_50V7K

12

QV8

QV8

LP2301ALT1G_SOT23- 3

LP2301ALT1G_SOT23- 3

123

D

D

G

G

1

VOUT

2

GND

3

EN

AP2821KTR-G1_SOT23 -5

AP2821KTR-G1_SOT23 -5

2nd source SA00003AR00

S

S

+3.3V_ALW

UV24

UV24

5

VIN

VIN

0.01U_0402_16V7K

0.01U_0402_16V7K

4

@

@

CV10

CV10

12

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

eDP CONN & Touch screen

eDP CONN & Touch screen

eDP CONN & Touch screen

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

LA-A972P

LA-A972P

LA-A972P

1

23 48Monday, March 17, 2014

23 48Monday, March 17, 2014

23 48Monday, March 17, 2014

0.1

0.1

0.1

5

4

3

2

1

+5V_RUN

0.1U_0402_16V4Z

0.1U_0402_16V4Z

12

@

@

CV24

CV24

1

IN

GND2OUT

+3.3V_RUN

1 2

RV501 100K_0402_5%RV501 100K_0402_5%

1 2

RV502 100K_0402_5%RV502 100K_0402_5%

1 2

RV503 5.1M_0402_5%RV503 5.1M_0402_5%

12

RV504 1M_0402_5%RV504 1M_0402_5%

1 2

RV505 100K_0402_5%RV505 100K_0402_5%

2

AP2330W-7_SC59-3

AP2330W-7_SC59-3

UV10

UV10

3

AP2337SA-7_SOT23-3

AP2337SA-7_SOT23-3

mDP_AUX#_C

mDP_AUX_C

DPB_MB_P14

mDP_CA_DET

mDP_HPD

+VHDMI_VCC

0.1U_0402_10V7K

0.1U_0402_10V7K

10U_0603_6.3V6M

10U_0603_6.3V6M

CV27

CV27

12

12

CV30@

CV30@

HDMI connector

JHDMI1

JHDMI1

HDMI_HPD<25>

HDMI_DAT_AUX#

12

HDMI_CLK_AUX

HDMI_CEC

RV8@10K_04 02_5% RV8@10K_0 402_5%

TMDS_CON_CLK#

TMDS_CON_CLK
TMDS_CON_N0

TMDS_CON_P0
TMDS_CON_N1

TMDS_CON_P1
TMDS_CON_N2

TMDS_CON_P2

+3.3V_RUN

0.1U_0402_16V4Z

0.1U_0402_16V4Z

@

@

CV510

CV510

1

1

UV501

UV501

2

IN

GND2OUT

3

mDP_AUX#_C
mDP_LANE_N2_C
mDP_AUX_C
mDP_LANE_P2_C

mDP_LANE_N3_C
mDP_LANE_N1_C
mDP_LANE_P3_C
mDP_LANE_P1_C

DPB_MB_P14
mDP_LANE_N0_C
mDP_CA_DET
mDP_LANE_P0_C
mDP_HPD

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

LCN_AUF05-1922S10-0019

LCN_AUF05-1922S10-0019

20130730 DC232002PB0 CIS Link OK

+VDISPLAY_VCC

.01U_0402_16V7K

.01U_0402_16V7K

1

CV509

CV509

2

mDP connector

JmDP1

JmDP1

20

DP_PWR

19

GND

18

AUX_CH_N

17

LANE2_N

16

AUX_CH_P

15

LANE2_P

14

GND

13

GND

12

LANE3_N

11

LANE1_N

10

LANE3_P

9

LANE1_P

8

GND

7

GND

6

CONFIG2

5

LANE0_N

4

CONFIG1

3

LANE0_P

2

HOT-PLUG

1

GND

ACON_MAR2E-20K1800

ACON_MAR2E-20K1800

20130730 DC060008GB0 CIS Link OK

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

HDMI CONN

HDMI CONN

HDMI CONN

LA-A972P

LA-A972P

LA-A972P

CONN@

CONN@

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CK­CK_shield
CK+
D0­D0_shield
D0+
D1­D1_shield
D1+
D2­D2_shield
D2+

CONN@

CONN@

1

20

GND

21

GND

22

GND

23

GND

24

GND4

23

GND3

22

GND2

21

GND1

0.1

0.1

24 48Monday, March 17, 2014

24 48Monday, March 17, 2014

24 48Monday, March 17, 2014

0.1

2

2

3

2

2

3

2

2

3

2

2

3

VCC
BE3

A3

B3

BE2

A2

B2

100K_0402_5%

100K_0402_5%

12

RV507

RV507

13

D

D

QV502

QV502
L2N7002WT1G_SC-70-3

L2N7002WT1G_SC-70-3

S

S

+VHDMI_VCC

14
13

12

11
10

9

8

mDP_CA_DET#

4

TMDS_CON_CLK

TMDS_CON_CLK#

TMDS_CON_P2

TMDS_CON_N2

TMDS_CON_P1

TMDS_CON_N1

TMDS_CON_P0

TMDS_CON_N0

+3.3V_RUN

1 2

CV511

CV511

0.1U_0402_25V6

0.1U_0402_25V6

CPU_DPC_CTRLCLK <10>

CPU_DPC_CTRLDAT <10>

DPC_HPD<10>

12

DDI2_LANE_P3<10>

DDI2_LANE_N3<10>

DDI2_LANE_P2<10>

DDI2_LANE_N2<10>

DDI2_LANE_P1<10>

DDI2_LANE_N1<10>

DDI2_LANE_P0<10>

DDI2_LANE_N0<10>

L2N7002WT1G_SC-70-3

L2N7002WT1G_SC-70-3

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

CV501 0.1U_0402_10V7KCV501 0.1U_0402_10V7K

12

CV502 0.1U_0402_10V7KCV502 0.1U_0402_10V7K

12

CV503 0.1U_0402_10V7KCV503 0.1U_0402_10V7K

12

CV504 0.1U_0402_10V7KCV504 0.1U_0402_10V7K

12

CV505 0.1U_0402_10V7KCV505 0.1U_0402_10V7K

12

CV506 0.1U_0402_10V7KCV506 0.1U_0402_10V7K

12

CV507 0.1U_0402_10V7KCV507 0.1U_0402_10V7K

12

CV508 0.1U_0402_10V7KCV508 0.1U_0402_10V7K

+5V_RUN

G

G

123

mDP_HPD

D

S

D

S

QV501

QV501

mDP_LANE_P3_C

mDP_LANE_N3_C

mDP_LANE_P2_C

mDP_LANE_N2_C

mDP_LANE_P1_C

mDP_LANE_N1_C

mDP_LANE_P0_C

mDP_LANE_N0_C

+3.3V_RUN

3

D D

HDMI_LANE_P3<25>

HDMI_LANE_N3<25>

HDMI_LANE_P2<25>

HDMI_LANE_N2<25>

HDMI_LANE_P1<25>

HDMI_LANE_N1<25>

C C

HDMI_LANE_P0<25>

HDMI_LANE_N0<25>

HDMI_CLK_AUX<25>

HDMI_DAT_AUX#<25>

B B

CV512

CPU_DPC_AUX<10>

CPU_DPC_AUX#<10>

CV512

0.1U_0402_10V7K

0.1U_0402_10V7K

CV513

CV513

0.1U_0402_10V7K

0.1U_0402_10V7K

HDMI_CLK_AUX

HDMI_DAT_AUX#

AUX/DDC SW for DDI2 to Mini DP

12

SW_mDP_AUX_C

mDP_AUX_C

12

SW_mDP_AUX#_C

mDP_AUX#_C

1 2

RV7 2.2K_0402_5%RV7 2.2K_04 02_5%

1 2

RV9 2.2K_0402_5%RV9 2.2K_04 02_5%

EMC@

EMC@

LV3

LV3

1

1

443

DLW21HN900HQ2L_4P

DLW21HN900HQ2L_4P

EMC@

EMC@

LV6

LV6

1

1

443

DLW21HN900HQ2L_4P

DLW21HN900HQ2L_4P

EMC@

EMC@

LV10

LV10

1

1

443

DLW21HN900HQ2L_4P

DLW21HN900HQ2L_4P

EMC@

EMC@

LV12

LV12

1

1

443

DLW21HN900HQ2L_4P

DLW21HN900HQ2L_4P

UV502

UV502

1

BE0

2

A0

3

B0

4

BE1

5

A1

6

B1

7

GND

PI3C3125LEX_TSSOP14~D

PI3C3125LEX_TSSOP14~D

+3.3V_RUN

A A

mDP_CA_DET

mDP_CA_DET1function

mDP

0

HDMI

2

G

G

5

5

+3.3V_RUN

+3.3V_RUN

12

RV51

RV51

RV551

RV551

@

@

@

@

4.7K_0402_5%

4.7K_0402_5%

12

RV52

RV52

RV550

RV550

@

@

@

@

4.7K_0402_5%

4.7K_0402_5%

RV555 100K_0402_5%RV555 100K_0402_5%

@

@

RV68 100K_040 2_5%

RV68 100K_040 2_5%

RV554 100K_0402_5%RV554 100K_0402_5%

RV67 1M_0402_5%RV67 1M_0402_5%

12

12

RV54

RV54

@

@

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

12

12

RV61

RV61

@

@

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

PCB

D D

G12 UMA PS8339+PS8338

DP SWITCH

G12 Entry PS8339

G14 DSC

G14 UMA

G14D_En

G14U_En

C C

B B

PS8339+PS8338

PS8339

PS8339+PS8338

PS8339

MODE = L: Control Switching Mode, HDMI ID disable
= H: Automatic Switching Mode, HDMI ID disable
= M: Automatic Switching Mode, HDMI ID enable

TMDS_PRE = L: no pre-emphasis
= H: 1.5dB pre-emphasis
= M: 3.0dB pre-emphasis

TMDS_RT = L: Standard open drain driver
= H: Open drain driver with termination resistors

TMDS_DDCBUF = L: DDC pass through
= H: DDC active buffer
= M: DDC pass through with 40 kohm pull up resistor

PEQ = L: default, LEQ, compensate channel loss up to 12dB @ HBR2
= H: HEQ, compensate channel loss up to 15dB @ HBR2
= M: LLEQ, compensate channel loss up to 5dB @ HBR2

DP_CFG1 = L: default, auto test disable & input offset cancellation enable
= H: auto test enable & input offset cancellation enable
= M: auto test disable & input offset cancellation disable

DP_CFG0 = L: default, automatic EQ enable & AUX interception enable
= H: automatic EQ disable & AUX interception enable
= M: automatic EQ disable & AUX interception disable, no pre-emphasis, 800mVpp swing

1 2

1 2

1 2

1 2

12

RV55

RV55

4.7K_0402_5%

4.7K_0402_5%

12

RV62

RV62

@

@

4.7K_0402_5%

4.7K_0402_5%

4

WIGIG_AUX#

PS8339B_IN_CA_DET

WIGIG_AUX

PS8339B_OUT_CA_DET

12

RV56

RV56

RV57

RV57

@

@

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

12

RV63

RV63

RV64

RV64

@

@

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

3

0.1U_0402_25V6

0.1U_0402_25V6

12

CV66

CV66

CV62

CV62

PS8339B_DP_CFG0
PS8339B_MODE_SW

DDI1_LANE_P0_C
DDI1_LANE_N0_C

DDI1_LANE_P1_C
DDI1_LANE_N1_C

DDI1_LANE_P2_C
DDI1_LANE_N2_C

DDI1_LANE_P3_C
DDI1_LANE_N3_C

CPU_DPB_AUX_C
CPU_DPB_AUX#_C

CPU_DPB_CTRLCLK
CPU_DPB_CTRLDAT

PS8339B_IN_CA_DET

PS8339B_TMDS_DDCBUF

PS8339B_INPUT_EQ

PS8339B_MODE

RV50

RV50

4.99K_0402_1%

4.99K_0402_1%

+3.3V_RUN

0.1U_0402_25V6

0.1U_0402_25V6

12

CV69

CV69

UV7

UV7

14

VDD33

28

VDD33

41

VDD33

56

VDD33

44

DP_CFG0/SCL_CTL

45

SW/SDA_CTL

38

I2C_CTL_EN

3

IN_D0p

4

IN_D0n

6

IN_D1p

7

IN_D1n

9

IN_D2p

10

IN_D2n

12

IN_D3p

13

IN_D3n

52

IN_AUXp

51

IN_AUXn

50

IN_DDC_SCL

49

IN_DDC_SDA

11

IN_CA_DET

5

IN_HPD

1

CEXT

2

TMDS_DDCBUF

8

PEQ

27

REXT

46

PD

53

MODE

PS8339BQFN56GTR2-A0_QFN56_7X7

PS8339BQFN56GTR2-A0_QFN56_7X7

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

1

1

CV61

CV61

2

2

CV71 0.1U_0402_25V6CV71 0.1U_0402 _25V6

DDI1_LANE_P0<10>
DDI1_LANE_N0<10>

DDI1_LANE_P1<10>
DDI1_LANE_N1<10>

DDI1_LANE_P2<10>
DDI1_LANE_N2<10>

DDI1_LANE_P3<10>

DDI1_LANE_N3<10>

CPU_DPB_AUX<10>

12

12

12

RV60

RV60

RV58

RV58

@

@

@

@

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

12

12

12

RV66

RV66

RV65

RV65

@

@

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

CPU_DPB_AUX#<10>

CPU_DPB_CTRLCLK<10>
CPU_DPB_CTRLDAT<10>

PS8339B_TMDS_DDCBUF

PS8339B_INPUT_EQ

PS8339B_MODE

PS8339B_TMDS_PRE

PS8339B_TMDS_RT

PS8339B_DP_CFG1

PS8339B_DP_CFG0

PS8339B_MODE_SW

1 2

CV72 0.1U_0402_25V6CV72 0.1U_0402 _25V6

1 2

CV73 0.1U_0402_25V6CV73 0.1U_0402 _25V6

1 2

CV74 0.1U_0402_25V6CV74 0.1U_0402 _25V6

1 2

CV75 0.1U_0402_25V6CV75 0.1U_0402 _25V6

1 2

CV76 0.1U_0402_25V6CV76 0.1U_0402 _25V6

1 2

CV77 0.1U_0402_25V6CV77 0.1U_0402 _25V6

1 2

CV78 0.1U_0402_25V6CV78 0.1U_0402 _25V6

1 2

CV79 0.1U_0402_25V6CV79 0.1U_0402 _25V6

1 2

CV80 0.1U_0402_25V6CV80 0.1U_0402 _25V6

1 2

DPB_HPD<10>

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

12

CV60

CV60

12

2

DP_D0p
DP_D0n

DP_D1p
DP_D1n

DP_D2p
DP_D2n

DP_D3p
DP_D3n

DP_AUXp_SCL
DP_AUXn_SDA

DP_HPD

DP_CA_DET

DP_CFG1

TMDS_CH0p
TMDS_CH0n

TMDS_CH1p
TMDS_CH1n

TMDS_CH2p
TMDS_CH2n

TMDS_CLKp
TMDS_CLKn

TMDS_SCL

TMDS_SDA

TMDS_HPD

TMDS_RT

TMDS_PRE

Thermal/GND

GND
GND
GND

40
39

37
36

34
33

31
30

55
54
32

42

PS8339B_OUT_CA_DET

29

PS8339B_DP_CFG1

19
18

22
21

25
24

16
15

48
47

17

23

PS8339B_TMDS_RT

20

PS8339B_TMDS_PRE

26
35
43
57

WIGIG_LANE_P0 <30>
WIGIG_LANE_N0 <30>

WIGIG_LANE_P1 <30>
WIGIG_LANE_N1 <30>

WIGIG_LANE_P2 <30>
WIGIG_LANE_N2 <30>

WIGIG_LANE_P3 <30>
WIGIG_LANE_N3 <30>

WIGIG_AUX <30>
WIGIG_AUX# <30>
WIGIG_HPD <30>

HDMI_LANE_P0 <24>
HDMI_LANE_N0 <24>

HDMI_LANE_P1 <24>
HDMI_LANE_N1 <24>

HDMI_LANE_P2 <24>
HDMI_LANE_N2 <24>

HDMI_LANE_P3 <24>
HDMI_LANE_N3 <24>

HDMI_CLK_AUX <24>
HDMI_DAT_AUX# <24>

HDMI_HPD <24>

1

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

DP SW

DP SW

DP SW

LA-A972P

LA-A972P

LA-A972P

25 48Monday, March 17, 2014

25 48Monday, March 17, 2014

25 48Monday, March 17, 2014

1

0.1

0.1

0.1

5

D D

C C

B B

4

3

2

1

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

DP to VGA & VGA Conn

DP to VGA & VGA Conn

DP to VGA & VGA Conn

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

LA-A972P

LA-A972P

LA-A972P

1

26 47Monday, March 17, 2014

26 47Monday, March 17, 2014

26 47Monday, March 17, 2014

0.1

0.1

0.1

5

D D

4

3

2

1

PJP11@

PJP11@

V_BAT

GPIO_1
GPIO_2
GPIO_3

GPIO-Express-00

PP/GPIO

TESTBI

TESTI

NBO_1
NBO_2
NBO_3
NBO_4
NBO_5
NBO_6

+3.3V_M_TPM

12

1
2
17
6
7

9
8

5
13
14
15
27
28

+3.3V_SUS

1 2

RZ8 2.2K_0402_5%RZ8 2.2K_0402_5%

1 2

RZ9 2.2K_0402_5%RZ9 2.2K_0402_5%

1 2

RZ10 1M_04 02_5%RZ10 1M_0402_5%

USH_SMBCLK

USH_SMBDAT

USH_PWR_STATE#

0.1U_0402_25V6

0.1U_0402_25V6

@

@

CZ10

CZ10

12

Close to JUSH1

USH CONN

CONN@

CONN@

JUSH1

JUSH1

1

1

USBP6-<11>
USBP6+<11>

USH_SMBCLK<36>
USH_SMBDAT<36>

BCM5882_ALERT#<35>

+3.3V_SUS

+3.3V_RUN

+3.3V_SUS+3.3V_RUN+5V_RUN

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

@

@

CZ11

CZ11

12

12

@

@

CZ12

CZ12

+5V_RUN

PLTRST_USH#<9>
USH_PWR_STATE#<35>
CONTACTLESS_DET#<10,7>

USH_DET#<10,12>

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

GND

19

20

GND

20

CONCR_205200FW010

CONCR_205200FW010

21
22

SPI_DINTPM
SPI_DOTPM
SPI_CLKTPM
PCH_SPI_CS2#_R

TPM_PIRQ#<12>

+3.3V_M

UZ1

UZ1

3

VCC

10

VCC

19

VCC

24

VCC

26

MISO

23

MOSI

21

SPI_CLK

22

SPI_CS#

16

SPI_RST#

20

PIRQ#

25

GND

18

GND

11

GND

4

GND

AT97SC3205_TSSOP28~D

AT97SC3205_TSSOP28~D

1 2

PAD-OPEN1x1m

PAD-OPEN1x1m

+3.3V_M_TPM

0.1U_0402_25V6

0.1U_0402_25V6

4700P_0402_25V7K

4700P_0402_25V7K

2200P_0402_50V7K

2200P_0402_50V7K

2200P_0402_50V7K

2200P_0402_50V7K

CZ5

CZ5

CZ6

CZ6

CZ7

12

12

CZ4@

C C

PCH_SPI_DIN<7>

PCH_SPI_DO<7>

PCH_SPI_CLK<7>

PCH_SPI_CS2#<7>

SPI_CLKTPM

33_0402_5%

33_0402_5%

@EMC@

@EMC@

RZ35

RZ35

0.1U_0402_25V6

0.1U_0402_25V6

1 2

@EMC@

@EMC@

B B

A A

12

CZ9

CZ9

CZ4@

RZ30

RZ30

1 2

RZ29

RZ29

1 2

RZ26

RZ26

1 2

RZ17 0_0402_5%

@

RZ17 0_0402_5%

@

1 2

CZ7

12

12

33_0402_5%

33_0402_5%
33_0402_5%

33_0402_5%
33_0402_5%

33_0402_5%

PCH_PLTRST#_EC<20,30,36,9>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

USH & TPM

USH & TPM

USH & TPM

LA-A972P

LA-A972P

LA-A972P

1

27 48Monday, March 17, 2014

27 48Monday, March 17, 2014

27 48Monday, March 17, 2014

0.1

0.1

0.1

5

+3.3V_LAN

1 2

TP_LAN_JTAG_TMS

RL1@ 10K_0402_ 5%RL1@ 10K_0402_ 5%

1 2

TP_LAN_JTAG_TCK

RL2@ 10K_0402_ 5%RL2@ 10K_0402_ 5%

12

LANCLK_REQ#

RL4 4.7K_040 2_5%@ RL4 4.7K_0 402_5%@

+3.3V_LAN

10K_0402_5%

10K_0402_5%

+3.3V_ALW

+3.3V_LAN

5

UL2

UL2

P

B

A

G

TC7SH08FU_SSOP5

TC7SH08FU_SSOP5

3

SYS_LED_MASK#

34

34

27P_0402_50V8J

27P_0402_50V8J

CL13

CL13

1 2

CL15@

CL15@

1 2

0.1U_0402_1 0V7K

0.1U_0402_1 0V7K

4

Y

12

RL5@

RL5@

10K_0402_5%

10K_0402_5%

12

RL9@

RL9@

25MHZ_18PF_7 V25000034

25MHZ_18PF_7 V25000034

UZ8

UZ8

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2
VIN27VOUT2

TPS22966DPUR_SON14 _2X3

TPS22966DPUR_SON14 _2X3

LAN_ACTLED_YEL#

SYS_LED_MASK# <35,3 9>

LED_100_ORG#

LED_10_GRN#

D D

0.1U_0402_10V7K

0.1U_0402_10V7K

12

0.1U_0402_10V7K

0.1U_0402_10V7K

12

CL10

CL10

CL11

CL11

+5V_ALW

AUX_EN_WOWL

AUX_EN_WOWL

DMN66D0LDW-7 _SOT363-6

DMN66D0LDW-7 _SOT363-6

DMN66D0LDW-7 _SOT363-6

DMN66D0LDW-7 _SOT363-6

DMN66D0LDW-7 _SOT363-6

DMN66D0LDW-7 _SOT363-6

DMN66D0LDW-7 _SOT363-6

DMN66D0LDW-7 _SOT363-6

1 2

RL7 0_0402_5%@RL7 0_0402_5%@

0.1U_0402_10V7K

0.1U_0402_10V7K

12

CL8

CL8

1

2

QL1A

QL1A

126

QL1B

QL1B

5

SYS_LED_MASK#

QL2A

QL2A

126

SYS_LED_MASK#

QL2B

QL2B

5

5

PM_LANPHY_ENABLE<12 ,9>

+0.9V_LAN

0.1U_0402_10V7K

0.1U_0402_10V7K

22U_0603_6.3V6M

22U_0603_6.3V6M

CL12

CL12

1

12

CL9

CL9

2

Note:
+1.0V_LAN will work at 0.95V to 1.15V

C C

SUS_ON<36 ,42>

AUX_EN_WOWL<30 ,35>

1 2

RZ38 100K_0402 _5%RZ38 100K_ 0402_5%

B B

LOM_SPD100LE D_ORG#

LOM_SPD10LED_ GRN#

LOM_ACTLED_YEL#

LOM_SPD100LE D_ORG#

A A

LOM_SPD10LED_ GRN#

CLK_PCIE_LAN<7>
CLK_PCIE_LAN#<7>

PCIE_PRX_GLANTX_P3<11>

PCIE_PRX_GLANTX_N3<11>

PCIE_PTX_GLANRX_P3<11>

PCIE_PTX_GLANRX_N3<11>

LAN_SMBDATA<7>

LAN_WAKE#<12 ,36>

SMBus Device Address 0xC8

1 2

RL10@ 0_0402_ 5%RL10@ 0_ 0402_5%

YL1

YL1

1

3

IN

OUT

2

4

GND

GND

14

VOUT1

13

VOUT1

12

CT1

11

GND

10

CT2

9

VOUT2

8

15

GPAD

WLAN_LAN_DISBL# <35>

LANCLK_REQ#<7>

PLTRST_LAN#<9>

LAN_SMBCLK<7>

+3.3V_SUS_UZ8

+3.3V_WLAN_UZ8

+3.3V_SUS

12

CL1 0.1U_0402_ 10V7KCL1 0.1U_0402 _10V7K

12

CL2 0.1U_0402_ 10V7KCL2 0.1U_0402 _10V7K

1 2

CL5 0.1U_0402_ 10V7KCL5 0.1U_0402 _10V7K

1 2

CL6 0.1U_0402_ 10V7KCL6 0.1U_0402 _10V7K

LAN_DISABLE#_R<35>

T88@ PAD~DT88@ PAD~D
T89@ PAD~DT89@ PAD~D

12

RL11

RL11
1M_0402_5%

1M_0402_5%

27P_0402_50V8J

27P_0402_50V8J

CL14

CL14

1 2

12

PJP25

PJP25
PAD-OPEN1x1m

PAD-OPEN1x1m

@

@

1 2

CZ41 0.1U_0402_10V7K@CZ41 0.1U_0402_ 10V7K@

1 2

CZ43 47 0P_0402_5 0V7KCZ43 470P_0 402_50V7K

1 2

CZ42 47 0P_0402_5 0V7KCZ42 470P_0 402_50V7K

PJP27

PJP27

1 2

0.1U_0402_10V7K

0.1U_0402_10V7K
PAD-OPEN1x3m

PAD-OPEN1x3m

12

@

@

CZ53

CZ53

@

@

0.47U_0603_10V7K

0.47U_0603_10V7K

12

CL16

CL16

0.47U_0603_10V7K

0.47U_0603_10V7K

12

CL20

CL20

4

PCIE_PRX_GLANTX_P3_ C

PCIE_PRX_GLANTX_N3_C

PCIE_PTX_GLANRX_P3_ C

PCIE_PTX_GLANRX_N3_C

LAN_DISABLE#_R

LOM_ACTLED_YEL#
LOM_SPD100LE D_ORG#
LOM_SPD10LED_ GRN#

TP_LAN_JTAG_TDI
TP_LAN_JTAG_TDO
TP_LAN_JTAG_TMS
TP_LAN_JTAG_TCK

XTALOXTALO_R
XTALI

LAN_TEST_EN

1K_0402_5%

1K_0402_5%

3.01K_0402_1%

3.01K_0402_1%

12

12

RL12

RL12

RL13

RL13

+3.3V_WLAN

LAN_TX3-L_R

LAN_TX3+L_R

0.47U_0603_10V7K

0.47U_0603_10V7K

LAN_TX1-L_R

12

CL17

CL17

LAN_TX1+L_R

LAN_TX2-L_R

LAN_TX2+L_R

0.47U_0603_10V7K

0.47U_0603_10V7K

LAN_TX0-L_R

12

CL21

CL21

LAN_TX0+L_R

4

UL1

UL1

48

CLK_REQ_N

36

PE_RST_N

44

PE_CLKP

45

PE_CLKN

38

PETp

39

PETn

41

PERp

42

PERn

28

SMB_CLK

31

SMB_DATA

2

LANWAKE_N

3

LAN_DISABLE_N

26

LED0

27

LED1

25

LED2

32

JTAG_TDI

34

JTAG_TDO

33

JTAG_TMS

35

JTAG_TCK

9

XTAL_OUT

10

XTAL_IN

30

TEST_EN

12

RBIAS

WGI218LM-QQ8 9-B0_QFN48_6 X6~D

WGI218LM-QQ8 9-B0_QFN48_6 X6~D

10/15 change to
SP050006Y00 (S X'FORM_ NS692417 LAN)

TL1

TL1

1

TD1+

2

TD1-

3

TDCT1

4

TDCT2

5

TD2+

6

TD2-

7

TD3+

8

TD3-

9

TDCT3

10

TDCT4

11

TD4+

12

TD4-

NS692417

NS692417

GND

GND
CHASSIS

CHASSIS

PCIE

PCIE

SMBUS

SMBUS

JTAG LED

JTAG LED

MDI_PLUS0

MDI_MINUS0

MDI_PLUS1

MDI_MINUS1

MDI_PLUS2

MDI

MDI

MDI_MINUS2

MDI_PLUS3

MDI_MINUS3

SVR_EN_N

RSVD_VCC3P3_1

VDD3P3_IN

VDD3P3_4

VDD3P3_15
VDD3P3_19
VDD3P3_29

VDD0P9_47
VDD0P9_46
VDD0P9_37

VDD0P9_43

VDD0P9_11

VDD0P9_40
VDD0P9_22
VDD0P9_16

VDD0P9_8

CTRL0P9

VSS_EPAD

CL22

1:1

1:1

1:1

1:1

1 2

3

13

LAN_TX0+

14

LAN_TX0-

17

LAN_TX1+

18

LAN_TX1-

20

LAN_TX2+

21

LAN_TX2-

23

LAN_TX3+

24

LAN_TX3-

6

VCT_LAN_R1

1

+RSVD_VCC3P3_1

5

4

15
19
29

47
46
37

43

11

40
22
16
8

7

REGCTL_PNP10RES_BIAS

4.7UH_BRC2012T4R7 MD_20%

4.7UH_BRC2012T4R7 MD_20%

49

Place CL3, CL4 and LL1 close to UL1

TX1+

TX1-

TXCT1

TXCT2

TX2+

TX2-

1:1

1:1

TX3+

TX3-

TXCT3

TXCT4

1:1

1:1

TX4+

TX4-

EMC@

EMC@

150P_1808 _2.5KV8JCL22

150P_1808 _2.5KV8J

3

2

Layout Notice : Place bead as
close UL4 as possible

1 2
1 2

EMC@

EMC@

LL21 12NH_060 3CS-120EJTS_ 5%

LL21 12NH_060 3CS-120EJTS_ 5%

EMC@

EMC@

LL22 12NH_060 3CS-120EJTS_ 5%

LL22 12NH_060 3CS-120EJTS_ 5%

1 2

EMC@

EMC@

1 2

LL23 12NH_060 3CS-120EJTS_ 5%

LL23 12NH_060 3CS-120EJTS_ 5%

EMC@

EMC@

LL24 12NH_060 3CS-120EJTS_ 5%

LL24 12NH_060 3CS-120EJTS_ 5%

1 2

EMC@

EMC@

1 2

LL25 12NH_060 3CS-120EJTS_ 5%

LL25 12NH_060 3CS-120EJTS_ 5%

EMC@

EMC@

LL26 12NH_060 3CS-120EJTS_ 5%

LL26 12NH_060 3CS-120EJTS_ 5%

1 2
1 2

EMC@

EMC@

LL27 12NH_060 3CS-120EJTS_ 5%

LL27 12NH_060 3CS-120EJTS_ 5%

EMC@

EMC@

LL28 12NH_060 3CS-120EJTS_ 5%

LL28 12NH_060 3CS-120EJTS_ 5%

12

RL3 0_0402_ 5%@RL 3 0_0402_5 %@

12

RL6 4.7K_040 2_5%RL6 4.7K _0402_5%

+3.3V_LAN_OUT

RL8@ 0_ 0603_5%RL8@ 0_ 0603_5%

1U_0603_10V6K

1U_0603_10V6K

Pin 6 is SVR_EN in Clarkville

12

CL7

CL7

+0.9V_LAN

+0.9V_LAN

LL1

LL1

1 2

24

23

22

21
20

19

18

17

16

15
14

13

use 40mil trac e if necessary

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

NB_LAN_TX3-

NB_LAN_TX3+

NB_LAN_TX1-

NB_LAN_TX1+

NB_LAN_TX2-

NB_LAN_TX2+

NB_LAN_TX0-

NB_LAN_TX0+

+GND_CHASSIS

0.1U_0402_10V7K

0.1U_0402_10V7K

CL3

CL3

12

12

Z2805

Z2807

Z2806

Z2808

12

RL15 75_0402_1%RL15 75_0402_1%

12

Idc_min=500mA
DCR=100mohm

10U_0603_6.3V6M

10U_0603_6.3V6M

CL4

CL4

12

12

12

RL18 75_0402_1%RL18 75_0402_1%

RL17 75_0402_1%RL17 75_0402_1%

RL16 75_0402_1%RL16 75_0402_1%

+3.3V_LAN

LAN_TX0+L
LAN_TX0-L

LAN_TX1+L
LAN_TX1-L

LAN_TX2+L
LAN_TX2-L

LAN_TX3+L
LAN_TX3-L

+3.3V_LAN

LAN_TX0+L

LAN_TX0-L

LAN_TX1+L

LAN_TX1-L

LAN_TX2+L

LAN_TX2-L

LAN_TX3+L

LAN_TX3-L

LAN_ACTLED_YEL#LAN_ACTLED_YEL# LAN_ACTLED_YEL_R#

RL14 150_0402_5%RL14 150_0402_5 %

NB_LAN_TX3-

NB_LAN_TX3+

NB_LAN_TX1-

NB_LAN_TX2-

NB_LAN_TX2+

NB_LAN_TX1+

NB_LAN_TX0-

NB_LAN_TX0+

1 2

LED_10_GRN# LED_10 _GRN_R#

RL19 150_040 2_5%RL19 15 0_0402_5%

1 2

LED_100_ORG# LED_100_ORG_R#

RL20 150_040 2_5%RL20 15 0_0402_5%

2

1 2

1

1 2

RL21 5.6_0402_5%RL21 5.6_0402_5%

1 2

RL22 5.6_0402_5%RL22 5.6_0402_5%

1 2

RL23 5.6_0402_5%RL23 5.6_0402_5%

1 2

RL24 5.6_0402_5%RL24 5.6_0402_5%

1 2

RL25 5.6_0402_5%RL25 5.6_0402_5%

1 2

RL26 5.6_0402_5%RL26 5.6_0402_5%

1 2

RL27 5.6_0402_5%RL27 5.6_0402_5%

1 2

RL28 5.6_0402_5%RL28 5.6_0402_5%

470P_0402_50V7K

470P_0402_50V7K

12

CL18

CL18

DELL CONFIDENTIAL/PROPRIETARY

12

12

12

12

+3.3V_LAN

0.1U_0402_10V7K

0.1U_0402_10V7K

CL19

CL19

12

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

LAN_TX0+L_R

EMC@

EMC@

CL30

CL30

3.3P_0402_ 50V8J

3.3P_0402_ 50V8J

LAN_TX0-L_R

LAN_TX1+L_R

EMC@

EMC@

CL31

CL31

3.3P_0402_ 50V8J

3.3P_0402_ 50V8J

LAN_TX1-L_R

LAN_TX2+L_R

EMC@

EMC@

CL32

CL32

3.3P_0402_ 50V8J

3.3P_0402_ 50V8J

LAN_TX2-L_R

LAN_TX3+L_R

EMC@

EMC@

CL33

CL33

3.3P_0402_ 50V8J

3.3P_0402_ 50V8J

LAN_TX3-L_R

RJ45 LOM circuit

+3.3V_LAN:20mils

JLOM1

CONN@

JLOM1

CONN@

10

Yellow LED-

9

Yellow LED+

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

11

Green LED-

13

Orange LED-

12

Green-Orange LED+

SANTA_130456-341

SANTA_130456-341

20130726 same as Goliad

LAN

LAN

LAN

LA-A972P

LA-A972P

LA-A972P

1

15

GND

14

GND

rev1

rev1

28 48Monday, Ma rch 17, 2014

28 48Monday, Ma rch 17, 2014

28 48Monday, Ma rch 17, 2014

0.1

0.1

0.1

A

+3.3V_MMI

+3.3V_MMI

CR4 close to U27.42
CR6 close to U27.23

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

12

12

CR4

CR4

CR6

1 1

CR6

B

CR3 close to U27.9
CR1 CR2 close to U27.35

0.1U_0402_25V6

0.1U_0402_25V6

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

12

12

12

CR2

CR2

CR1

CR1

C

0.1U_0402_25V6

0.1U_0402_25V6

CR3

CR3

D

E

+3.3V_MMI

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

0.1U_0402_25V6

+1.2V_LDO

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

CR10

CR10

CR13

CR13

CR9

CR9

1 2

1 2

1 2

+1.2V_LDO

0.1U_0402_25V6

0.1U_0402_25V6

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

CR19

CR19

CR18

CR18

1 2

2 2

+3.3V_MMI

100K_0402_5%

100K_0402_5%

12

RR6

RR6

IO_LDOSEL

100K_0402_5%

100K_0402_5%

12

RR8@

RR8@

3 3

4 4

@

@

PJP26

PJP26

1 2

PAD-OPEN1x1m

PAD-OPEN1x1m

A

1 2

PCIE_PTX_MMIRX_P1<11>
PCIE_PTX_MMIRX_N1<11>

PCIE_PRX_MMITX_P1<11>
PCIE_PRX_MMITX_N1<11>

+3.3V_MMI+3.3V_RU N

0.1U_0402_25V6

CR7

CR7

CR8

CR8

1 2

1 2

If support RTD3 cold the AUX and MAIN power rail should be
use different power rail; for RTD3 hot please keep this circuit

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

CR21

CR21

CR22

CR22

1 2

1 2

1 2

RR2 191_ 0402_1%RR 2 191_0402 _1%

1 2

CR24 0.1U_0402_10V7KCR 24 0.1U_ 0402_10V7K

1 2

CR25 0.1U_0402_10V7KCR 25 0.1U_ 0402_10V7K

1 2

CR26 0.1U_0402_10V7KCR 26 0.1U_ 0402_10V7K

1 2

CR27 0.1U_0402_10V7KCR 27 0.1U_ 0402_10V7K

+3.3V_MMI

1 2

RR15 10K_0402_5%RR15 10K_0402_5 %

CLK_PCIE_MMI#<7>
CLK_PCIE_MMI<7>

PLTRST_MMI#<9>

MEDIACARD_IRQ#<12>

MMICLK_REQ#<6,7>

MEDIACARD_PWREN

B

PCIE_PTX_MMIRX_P1_C
PCIE_PTX_MMIRX_N1_C

PCIE_PRX_MMITX_P1_C
PCIE_PRX_MMITX_N1_C

MEDIACARD_PWREN SD_REXT

IO_LDOSEL

PE_REXT

UR1

UR1

9

PE_33VCCAIN

27

UHSII_33VCCAIN/NC

42

SD_33VCCD

23

SD_SKT_33VIN

13

AUX _33VIN

11

MAIN_LDO_VIN

10

MAIN_LDO_12VOUT

41

CORE_12VCCD

36

UHSII_12VCCAIN/NC

31

UHSII_12VCCAIN/NC

28

UHSII_12VCCAIN/NC

1

PE_12VCCAIN

4

PE_REXT

6

PE_RXP

5

PE_RXM

7

PE_TXP

8

PE_TXM

2

PE_REFCLKM

3

PE_REFCLKP

15

PE_RST#_GATE#

14

MAIN_LDO_EN

16

DEV_WAKE#

17

CLKREQ#

18

IO0_LDOSEL

OZ777FJ2LN_QFN 48_6X6

OZ777FJ2LN_QFN 48_6X6

OZ777FJ2LN

OZ777FJ2LN

please routing daisy chain

1. from UR1.38 (SD_D0) -> UR1.30 (SD_RCLK_P) -> LR3.4

2. From UR1.37 (SD_D1) -> UR1.29 (SD_RCLK_N) -> LR3.1

R231,R297,R306,R315,R333,R337 for EMI solution

12

AUX_LDO_CAP

SD_IO_LDO_CAP

SD_SKT_33VOUT

SD_SKT_18VOUT

SD_WPI

SD_CD#

SD_CLK

SD_CMD

MMC_D7
MMC_D6
MMC_D5
MMC_D4

SD_RCLK_M/NC

SD_RCLK_P/NC

SD_D1P/NC
SD_D1M/NC
SD_D0M/NC
SD_D0P/NC

SD_REXT/NC

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

C

+AUX_LDO

25

+SD_IO_LDO

22

+3.3V_RUN_CARD

24

+1.8V_RUN_CARD

20

SDWP

21

SD/MMCCD#

43

SD/MMCCLK_R

45

SD/MMCCMD

39
40
44
46
47

SD/MMCDAT3 SD/MMCDAT3_R

SD_D3

48

SD/MMCDAT2 SD/MMCDAT2_R

SD_D2

37

SD/MMCDAT1

SD_D1

38

SD/MMCDAT0

SD_D0

29
30
32

SD_UHS2_D1P

33

SD_UHS2_D1N

34

SD_UHS2_D0N

35

SD_UHS2_D0P

26

19

LED#

49

GND

1 2

RR1 EMC@ 10_04 02_5%RR1 EMC@ 10_0402 _5%

1 2

RR3@EMC@ 0_0402_5%RR3@EMC@ 0 _0402_5%

1 2

RR4@EMC@ 0_0402_5%RR4@EMC@ 0 _0402_5%

EMI solution for SD card

1 2

RR5 4.7K_040 2_1%RR5 4.7K_0402_1%

D

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

CR14

CR14

1 2

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_25V6

0.1U_0402_25V6

2

CR17

CR17

CR15

CR15

1

1 2

12

CR31 near UR1.22 CR34 near UR1.24

SD/MMCCLK

@EMC@

@EMC@

5P_0402_50V8C

5P_0402_50V8C

12

CR23

CR23

EMI depop location

+3.3V_RUN_CARD
+1.8V_RUN_CARD

1M_0402_5%

1M_0402_5%

12

SD/MMCCMD
SD/MMCCLK

SD/MMCCD#

0.1U_0402_25V6

0.1U_0402_25V6

SDWP

RR11

RR11

12

SD/MMCDAT0

CR35

CR35

SD/MMCDAT1
SD/MMCDAT2_R
SD/MMCDAT3_R
SD_UHS2_D0P
SD_UHS2_D0N
SD_UHS2_D1P
SD_UHS2_D1N

20130726 SP070011L00 CIS Li nk OK

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Card Reader

Card Reader

Card Reader

LA-A972P

LA-A972P

LA-A972P

1U_0402_6.3V6K

1U_0402_6.3V6K

CR31

CR31

CONN@

CONN@

4

14

2
5

18
19

7
8
9

1
11
12
16
15

3

6
10
13

E

+1.8V_RUN_CARD+3.3V_RUN_CARD

12

JSD1

JSD1

VDD/VDD1
VDD2
CMD
CLK

CARD DETECT
WRITE PROTEC

DAT0/RCLK+
DAT1/RCLK­DAT2
CD/DAT3
D0+
DO­D1+
D1-

GND1
GND2

VSS1

GND3

VSS2

GND4

VSS3

GND5

VSS4

GND6

VSS517GND7

ALPS_SCDADA0101_NR

ALPS_SCDADA0101_NR

29 4 8Monday, March 17, 2014

29 4 8Monday, March 17, 2014

29 4 8Monday, March 17, 2014

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

CR34

CR34

20
21
22
23
24
25
26

0.1

0.1

0.1

5

D D

C C

STATE #

CONFIG_0 CONFIG_21CONFIG_3 Module Type

0

8

14

B B

15

CONFIG_1

GND

GND

GND

HIGH

GND

HIGH

GND

HIGH HIGH

GND

GND

GND

HIGH

HIGH

GND

GND

GNDHIGH

HIGH

HIGH

4

NGFF for UMA

SSD-SATA

SSD-PCIE

3

2

1

NGFF slot A Key A

+3.3V_WLAN

CONN@

CONN@

JNGFF1

JNGFF1

1

USBP2+<11>
USBP2-<11>

WIGIG_LANE_N3<25>
WIGIG_LANE_P3<25>

WIGIG_LANE_N2<25>
WIGIG_LANE_P2<25>

PCIE_PTX_WLANRX_P4<11>
PCIE_PTX_WLANRX_N4<11>

PCIE_PTX_WIGIGRX_P5<11>
PCIE_PTX_WIGIGRX_N5<11>

AUX_EN_WOWL< 28,35>

EC_32KHZ_MEC5085<36>

WLAN_WIGIG60GHZ_DIS#<35>

BT_RADIO_DIS#<35>

1 2
1 2

CV145 0.1U_0402_25V6CV145 0.1U_0402_25V6
CV146 0.1U_0402_25V6CV146 0.1U_0402_25V6

1 2
1 2

CV147 0.1U_0402_25V6CV147 0.1U_0402_25V6
CV148 0.1U_0402_25V6CV148 0.1U_0402_25V6

WIGIG_HPD<25>

1 2

CZ13 0.1U_0402_10V7KCZ13 0.1U_0402_10V7K

1 2

CZ14 0.1U_0402_10V7KCZ14 0.1U_0402_10V7K

PCIE_PRX_WLANTX_P4<11>
PCIE_PRX_WLANTX_N4<11>

1 2

CZ21 0.1U_0402_10V7KCZ21 0.1U_0402_10V7K

1 2

CZ22 0.1U_0402_10V7KCZ22 0.1U_0402_10V7K

PCIE_PRX_WIGIGTX_P5<11>
PCIE_PRX_WIGIGTX_N5<11>

CLK_PCIE_WLAN<7>
CLK_PCIE_WLAN#<7>

WLANCLK_REQ#<12,7>
PCIE_WAKE#<35>

CLK_PCIE_WIGIG<7>
CLK_PCIE_WIGIG#<7>

+3.3V_ALW

5

UZ12

UZ12

1

P

B

2

A

G

TC7SH08FU_SSOP5

TC7SH08FU_SSOP5

3

1 2

DZ1

DZ1

RB751S40T1G_SOD523-2

RB751S40T1G_SOD523-2

1 2

DZ2

DZ2

RB751S40T1G_SOD523-2

RB751S40T1G_SOD523-2

WIGIG_LANE_N3_C
WIGIG_LANE_P3_C

WIGIG_LANE_N2_C
WIGIG_LANE_P2_C

PCIE_PTX_WLANRX_P4_C
PCIE_PTX_WLANRX_N4_C

PCIE_WAKE#

PCIE_PTX_WIGIGRX_P5_C
PCIE_PTX_WIGIGRX_N5_C

4

WIGIG_32KHZ_R WIGIG_32KHZ

Y

3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67

69

1 2

SUSCLK<9>

RZ56 0_0402_5%@ RZ56 0_0402_5%@

1 2

RZ57 0_0402_5%RZ57 0_0402_5%

WLAN_WIGIG60GHZ_DIS#_R

BT_RADIO_DIS#_R

BELLW_80148-3521

BELLW_80148-3521

2

1

2

4

3

4

6

5
7

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

GND

GND

PWR
Rail

WLAN_LED#

6

8

BT_LED#

8

10

12

WIGIG_AUX#_C

14

WIGIG_AUX_C

16
18

WIGIG_LANE_N1_C

20

WIGIG_LANE_P1_C

22
24

WIGIG_LANE_N0_C

26

WIGIG_LANE_P0_C

28
30
32
34
36
38
40
42
44

PCH_PLTRST#_EC

46

BT_RADIO_DIS#_R

48

WLAN_WIGIG60GHZ_DIS#_R

50
52
54
56
58

PCH_PLTRST#_EC

60
62
64
66

68

+3.3V_WLAN

0.1U_0402_25V6

0.1U_0402_25V6

12

CZ15@

CZ15@

Power Rating TBD

Voltage
Tolerance

PCH_CL_RST1# <7>

PCH_CL_DATA1 <7>

PCH_CL_CLK1 <7>

WIGIG_32KHZ

PCH_PLTRST#_EC <20,27,36,9>

WIGIGCLK_REQ# <12,7>

PCIE_WAKE#

0.047U_0402_16V4Z

0.047U_0402_16V4Z

0.047U_0402_16V4Z

0.047U_0402_16V4Z

12

12

CZ16

CZ16

CZ20

CZ20

1 2

Primary Power Aux Power

Peak Normal Normal

12

WIGIG_AUX# <25>

12

CV1500.1U_0402_25V6 CV1500.1U_0402_25V6

WIGIG_AUX <25>

CV1490.1U_0402_25V6 CV1490.1U_0402_25V6

12

WIGIG_LANE_N1 <25>

12

CV1520.1U_0402_25V6 CV1520.1U_0402_25V6

WIGIG_LANE_P1 <25>

CV1530.1U_0402_25V6 CV1530.1U_0402_25V6

12

WIGIG_LANE_N0 <25>

12

CV1560.1U_0402_25V6 CV1560.1U_0402_25V6

WIGIG_LANE_P0 <25>

CV1570.1U_0402_25V6 CV1570.1U_0402_25V6

47P_0402_50V8J

0.1U_0402_25V6

0.1U_0402_25V6

CZ17

CZ17

1 2

47P_0402_50V8J

0.1U_0402_25V6

0.1U_0402_25V6

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

12

12

@

@

CZ66

CZ66

CZ18

CZ18

CZ19

CZ19

+3.3V

WWAN

HCA-PCIE

NA

LED control circuit

3.3V_ALW for LID power

JSH1

JSH1

14

GND2

13

GND1

+3.3V_ALW

LID_CL#<36,39>

+3.3V_ALW

0.1U_0402_16V4Z

A A

0.1U_0402_16V4Z

1

@

@

C263

C263

2

5

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

CONCR_205120FW010

CONCR_205120FW010

CONN@

CONN@

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

BT_LED#

WLAN_LED#

2

+3.3V_WLAN

1 2

100K_0402_5%

100K_0402_5%

RZ14

RZ14

100K_0402_5%

100K_0402_5%

RZ15

RZ15

5

1 2

DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

34

QZ2B

QZ2B

DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

126

QZ2A

QZ2A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

NGFF Card

NGFF Card

NGFF Card

LA-A972P

LA-A972P

LA-A972P

WIRELESS_LED# <35,39>

30 40Monday, March 17, 2014

30 40Monday, March 17, 2014

30 40Monday, March 17, 2014

1

0.1

0.1

0.1

5

EMC@

EMC@

LI1

LI1

12

12

USB3TP1_C

USB3TN1_C

ILIM_SEL

+5V_ALW

1

1

443

DLW21HN900HQ2L_4P

DLW21HN900HQ2L_4P

EMC@

EMC@

LI2

LI2

1

1

443

DLW21HN900HQ2L_4P

DLW21HN900HQ2L_4P

UI3

UI3

1

2
3

13

4

5

6
7
8

TPS2544RTER_WQFN16_3X3

TPS2544RTER_WQFN16_3X3

USB3RP1<11>

USB3RN1<11>

D D

USB3TP1<11>

USB3TN1<11>

+5V_ALW

0.1U_0402_25V6

0.1U_0402_25V6

1

CI19

CI19

2

CI19 near UI3.1

+5V_ALW

C C

12

RI13

RI13

ILIM_SEL

10K_0402_5%

10K_0402_5%

USB_PWR_SHR_VBUS_EN<35>

USB_PWR_SHR_EN#<35,36>

CI5 0.1U_0402_10V7KCI5 0.1U_0402_10V7K

CI4 0.1U_0402_10V7KCI4 0.1U_0402_10V7K

USBP0-<11>
USBP0+<11>

USB_OC0#<11>

IN

DM_OUT
DP_OUT

FAULT#

ILIM_SEL

EN

CTL1
CTL2
CTL3

4

2

USB3RP1_D+

2

3

USB3RN1_D-

2

USB3TP1_D+

2

3

USB3TN1_D-

+5V_USB_CHG_PWR

12

OUT

10

PS_USBP0_D+

DP_IN

11

PS_USBP0_D-

DM_IN

15

ILIM_LO
ILIM_HI

16

9

NC

14

GND

17

GNDP

12

RI14

RI14

22.1K_0402_1%

22.1K_0402_1%

USB3RN1_D- USB3RN1_D-

USB3RP1_D+ USB3RP1_D+

USB3TN1_D- USB3TN1_D-

USB3TP1_D+ USB3TP1_D+

PS_USBP0_D+

PS_USBP0_D-

G12 UMA

G12 Entry NA

G14 DSC

G14 UMA

G14D_En

G14U_En

3

DI1

DI1

EMC@

EMC@

1

2

21 9

21 9

4

4

4

5

3

3

3

8

8

L05ESDL5V0NA-4_SLP2510P8-10-9

L05ESDL5V0NA-4_SLP2510P8-10-9

DLW21HN900HQ2L_4P

DLW21HN900HQ2L_4P

443

1

1

LI3

LI3

EMC@

EMC@

PCB

USB2 0

USB3102

USB3102 NX3DV221

USB3102 NX3DV221

NA

NA

9

10

10

8

7

7

7

6

65

65

2

3

USBP0_D+

2

USBP0_D-

USB2 3

NX3DV221

NA

NA

NA

+5V_USB_CHG_PWR

100U_1206_6.3V6M

100U_1206_6.3V6M

12

CI1

CI1

2

CONN@

CONN@

JUSB1

JUSB1

1

VBUS

USBP0_D-

EMC@

EMC@

DI2

DI2

223

AZC199-02SPR7G_SOT23-3

AZC199-02SPR7G_SOT23-3

1

1

USBP0_D+

USB3RN1_D­USB3RP1_D+

USB3TN1_D­USB3TP1_D+

0.1U_0402_25V6

0.1U_0402_25V6

12

CI3

CI3

3

2

D-

3

D+

4

GND

5

SSRX-

6

SSRX+

7

GND

8

SSTX-

9

SSTX+

SANTA_373070-2

SANTA_373070-2

20130730 DC233 00C0B0 CIS Link OK

1

10

GND

11

GND

12

GND

13

GND

EMC@

USB3TN4_C

USB3TP4_C

EMC@

LI9

LI9

1

1

443

DLW21HN900HQ2L_4P

DLW21HN900HQ2L_4P

EMC@

EMC@

LI8

LI8

1

1

443

DLW21HN900HQ2L_4P

DLW21HN900HQ2L_4P

2

USB3RN4_D-

2

3

2

USB3TN4_D-

2

3

USB3TP4_D+

USBP3+<11>

USBP3-<11>

4

DI6

DI6

EMC@

EMC@

1

USB3RN4_D- USB3RN4_D-USB3RP4_D+

USB3RP4_D+ USB3RP4_D+

USB3TN4_D- USB3TN4_D-

USB3TP4_D+ USB3TP4_D+

1

9

10

10

2

8

21 9

21 9

4

7

7

4

7

4

5

6

65

65

3

3

3

8

8

L05ESDL5V0NA-4_SLP2510P8-10-9

L05ESDL5V0NA-4_SLP2510P8-10-9

EMC@

EMC@

LI4

LI4

2

1

2

3

443

DLW21HN900HQ2L_4P

DLW21HN900HQ2L_4P

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

USBP3_D+

USBP3_D-

B B

A A

USB3TN4<11>

USB3TP4<11>

5

USB3RN4<11>

USB3RP4<11>

CI28 0.1U_0402_10V7KCI28 0.1U_0402_10V7K

CI27 0.1U_0402_10V7KCI27 0.1U_0402_10V7K

12

12

+USB_RIGHT_PWR

100U_1206_6.3V6M

100U_1206_6.3V6M

12

+5V_ALW

CONN@

CONN@

JUSB2

JUSB2

1

VBUS

2

D-

3

D+

4

GND

5

SSRX-

6

10

SSRX+

GND

7

11

GND

GND

8

12

SSTX-

GND

9

13

SSTX+

GND

SANTA_373070-2

SANTA_373070-2

20130730 DC233 00C0B0 CIS Link OK

+USB_RIGHT_PWR

UI2

UI2

1

8

GND

VOUT

2

7

VIN

VOUT

3

6

VIN

VOUT

5

EN4FLG

SY6288D10CAC_MSOP8

SY6288D10CAC_MSOP8

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

USB_OC2# <11,12>

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

USB3.0

USB3.0

USB3.0

LA-A972P

LA-A972P

LA-A972P

31 48Monday, March 17, 2014

31 48Monday, March 17, 2014

31 48Monday, March 17, 2014

1

0.1

0.1

0.1

223

1

0.1U_0402_25V6

0.1U_0402_25V6

CI12

CI12

USBP3_D­USBP3_D+

USB3RN4_D­USB3RP4_D+

USB3TN4_D­USB3TP4_D+

3

DI3

DI3

1

EMC@

EMC@

AZC199-02SPR7G_SOT23-3

AZC199-02SPR7G_SOT23-3

USB_PWR_EN2#<35>

0.1U_0402_25V6

0.1U_0402_25V6

12

CI8

CI8

CI10

CI10

10U_0603_6.3V6M

10U_0603_6.3V6M

@CI11

@

CI11

12

12

2

5

EMC@

EMC@

LI6

LI6

USB3TP2_C

USB3TN2_C

1

1

443

DLW21HN900HQ2L_4P

DLW21HN900HQ2L_4P

EMC@

EMC@

LI5

LI5

1

1

443

DLW21HN900HQ2L_4P

DLW21HN900HQ2L_4P

USB3RP2<11>

USB3TP2<11>

USB3TN2<11>

USB3RN2<11>

12

CI13 0.1U_0402_ 10V7KCI13 0.1U_0402_10V7 K

12

CI16 0.1U_0402_ 10V7KCI16 0.1U_0402_10V7 K

D D

4

2

USB3RP2_D+

2

3

USB3RN2_D-

2

USB3TP2_D+

2

3

USB3TN2_D-

3

DI4

DI4

EMC@

EMC@

1

USB3RN2_D- USB3RN2_D-

2

USB3RP2_D+

4

USB3TN2_D-

5

USB3TP2_D+

3

9

1

10

1

10

8

2

2

4

4

3

3

8

8

L05ESDL5V0NA-4_SLP2510P8-10-9

L05ESDL5V0NA-4_SLP2510P8-10-9

USB3RP2_D+

9

9

7

USB3TN2_D-

7

7

6

USB3TP2_D+

65

65

+USB_SIDE_PWR

12

2

EMC@

EMC@

DI5

DI5

223

AZC199-02SPR7G_SOT23-3

AZC199-02SPR7G_SOT23-3

1

1

USBP1_R_D­USBP1_R_D+

USB3RN2_D­USB3RP2_D+

USB3TN2_D­USB3TP2_D+

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

100U_1206_6.3V6M

100U_1206_6.3V6M

1

CI17

CI17

CI14

CI14

2

3

1

CONN@

CONN@

JUSB3

JUSB3

1

VBUS

2

D-

3

D+

4

GND

5

StdA-SSRX-

6

StdA-SSRX+

GND

7

GND-DRAIN

GND

8

StdA-SSTX-

GND

9

StdA-SSTX+

GND

TAITW_PUBAUE-09FLBS1FF4H0

TAITW_PUBAUE-09FLBS1FF4H0

10
11
12
13

+5V_ALW

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_25V6

0.1U_0402_25V6

@CI6

@

12

CI6

C C

DLW21HN900HQ2L_4P

USBP1+<11>

USBP1-<11>

B B

A A

DLW21HN900HQ2L_4P

443

1

1

LI7

LI7

EMC@

EMC@

2

USB_PWR_EN1#<35>

12

CI7

CI7

3

USBP1_R_D+

2

USBP1_R_D-

UI1

UI1

1

GND

VOUT

2

VIN

VOUT

3

VIN

VOUT

EN4FLG

SY6288D10CAC_MSOP8

SY6288D10CAC_MSOP8

+USB_SIDE_PWR

8
7
6
5

USB_OC1# <11,12>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

USB SW

USB SW

USB SW

LA-A972P

LA-A972P

LA-A972P

1

32 48Monday, March 17, 2014

32 48Monday, March 17, 2014

32 48Monday, March 17, 2014

0.1

0.1

0.1

5

D D

C C

4

3

2

1

NFC on USH/B

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

NFC

NFC

NFC

LA-A972P

LA-A972P

LA-A972P

1

33 48Monday, March 17, 2014

33 48Monday, March 17, 2014

33 48Monday, March 17, 2014

0.1

0.1

0.1

5

D D

C C

B B

4

3

2

1

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

E-Dock

E-Dock

E-Dock

LA-A972P

LA-A972P

LA-A972P

34 48Monday, March 17, 2014

34 48Monday, March 17, 2014

34 48Monday, March 17, 2014

1

0.1

0.1

0.1

5

+3.3V_ALW

RPE9

RPE9

1

8

USB_PWR_SHR_VBUS_EN

2

7

USB_PWR_EN2#

3456

USB_PWR_EN1#

100K_0804_8P4R_5 %

100K_0804_8P4R_5 %

1 2

D D

@

@

C C

RE87 10K_0402_5 %RE87 10K_0402_5%

RE21 10K_0402_5 %RE21 10K_0402_5%

B B

WLAN_WIGIG60GHZ_DIS#

RE8 100K_0402_ 5%RE8 100K_0 402_5%

1 2

1 2

1 2

1 2

BT_RADIO_DIS#

PROCHOT_GATE

SMB_ADDR

SYS_LED_MASK#

RE11 100K_0402_5%RE11 100K_0402_ 5%

RE83 100K_0402_5%

RE83 100K_0402_5%

USB_PWR_SHR_EN# <31,36>

AUD_HP_NB_SENSE<21>

BC_CLK_ECE1099<36>

SIO_SLP_WLAN#<9>

PANEL_BKEN_EC<23>

BC_DAT_ECE1099<36>

T97@ PAD~DT97@ PAD~D

LAN_DISABLE#_R<28>

AUD_NB_MUTE#<21>

AUX_EN_WOWL<28,30>

T98@ PAD~DT98@ PAD~D

BC_INT#_ECE1099<36>

4

+3.3V_ALW +3.3V_ALW_UE3

@

@

PJP14

PJP14

1 2

10U_0603_6.3V6M

10U_0603_6.3V6M

PAD-OPEN1x1m

PAD-OPEN1x1m

12

CE1

CE1

UE3

UE3

12

RE2410K_0402_ 5% RE2410K_04 02_5%

32

BC_DAT/SMB_DATA

33

BC_CLK/SMB_CLK

39

GPIO10/KSI0

40

GPIO11/KSI1

1

GPIO12/KSI2

2

GPIO13/KSI3

3

GPIO14/KSI4

4

GPIO15/KSI5

5

GPIO16/KSI6

6

GPIO17/KSI7

7

GPIO20/KSO00

34

BC_INT#/SMB_INT#

35

SMB_ADDR

37

RESERVED

38

TEST_PIN

ECE1099-FZG_QFN40 _6X6~D

ECE1099-FZG_QFN40 _6X6~D

BC_DAT_ECE1099
BC_CLK_ECE1099

EXPRESS_DET#

USB_DB_DET#

BC_INT#_ECE1099

SMB_ADDR

8

VCC

28

VCC

GPIO21/KSO01
GPIO22/KSO02
GPIO23/KSO03
GPIO24/KSO04
GPIO25/KSO05
GPIO26/KSO06
GPIO27/KSO07
GPIO30/KSO08
GPIO31/KSO09
GPIO32/KSO10
GPIO33/KSO11
GPIO34/KSO12
GPIO35/KSO13
GPIO36/KSO14
GPIO37/KSO15
GPIO00/KSO16
GPIO01/KSO17
GPIO02/KSO18
GPIO03/KSO19
GPIO04/KSO20
GPIO05/KSO21
GPIO06/KSO22

Thermal Slug(VSS)

GPIO07

3

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

12

12

CE2

CE2

CE3

CE3

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
29
30
31
36

41

SMART_DET#

BT_RADIO_DIS#

SYS_LED_MASK#

WLAN_WIGIG60GHZ_DIS#
PCIE_WAKE#_R
VGA_ID

MASK_SATA_LED#

USB_PWR_SHR_VBUS_EN
PROCHOT_GATE

USB_PWR_EN1#
USB_PWR_EN2#
TOUCH_SCREEN_PD#

T32@PAD~D T32@PAD~D

USH_PWR_STATE# <27>

BT_RADIO_DIS# <30>

WLAN_LAN_DISBL# <28>

SYS_LED_MASK# <28,39>
LED_SATA_DIAG_OUT# <39>
WIRELESS_LED# <30,39>

WLAN_WIGIG60GHZ_DIS# <30>

MASK_SATA_LED# <39>

USB_PWR_SHR_VBUS_EN <31>

BCM5882_ALERT# <27>

USB_PWR_EN1# <32>

USB_PWR_EN2# <31>

T96 @PAD~D T96 @PAD~D

2

PCIE_WAKE#_R

PCIE_WAKE#_R

Stuff RE275 and no stuff RE274 keep E5 design
Stuff RE274 and no stuff RE275 to save two GPIOs on EC(PCH_PCIE_WAKE# should be output with OD)

12

RE275 0_0402_5 %@ RE275 0_ 0402_5%@

12

RE3510K_0402_5% RE3510K_0402 _5%

1 2

Discrete

+3.3V_ALW

RE2740_0402 _5% @ RE2740_ 0402_5% @

VGA_ID

VGA_ID

@

1

PCIE_WAKE# <30>

PCH_PCIE_WAKE# <36,9>

+3.3V_ALW

1 2

RE84100K_0402_5% RE84100K_0402_5%

1 2

RE85100K_0402_5%@RE85100K_0402_5%

VGA_ID0

0

1UMA

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

ECE5048

ECE5048

ECE5048

LA-A972P

LA-A972P

LA-A972P

35 4 7Monday, March 17, 2014

35 4 7Monday, March 17, 2014

35 4 7Monday, March 17, 2014

1

0.1

0.1

0.1

11
12

1
2
3456

CONN@

CONN@

JDEG1

JDEG1

CONN@

CONN@

JLPDE1

JLPDE1

G1
G2

BC_DAT_ECE1099

PBAT_SMBDAT

PBAT_SMBCLK

FAN1_PWM

FAN1_TACH

EN_INVPWR

RESET_OUT#

MSDATA

LCD_TST

RUN_ON
SUS_ON

A_ON

PCH_ALW_ON

1U_0402_6.3V6K

1U_0402_6.3V6K

12

CE30

CE30

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND1

12

GND2

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

+3.3V_ALW

+3.3V_RUN

12

12

+3.3V_ALW

100K_0402_5%

100K_0402_5%

RE63

RE63

JTAG_RST#

100_0402_1%

100_0402_1%

RE65@

RE65@

49.9_0402_1%

49.9_0402_1%

12

RE71

RE71

MSCLK
MSDATA
HOST_DEBUG_TX

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

LPC_LFRAME#

PCH_PLTRST#_EC

5

5

678

123

4 5

10K_8P4R_5%

10K_8P4R_5%

RPE7

RPE7

JTAG_TDI
JTAG_TMS
JTAG_CLK
JTAG_TDO

CLK_PCI_LPDEBUG <20,7>

+3.3V_ALW

10K_0402_5%

10K_0402_5%

12

SUS_ON<28,42>

MEC_XTAL1

22P_0402_50V8J

22P_0402_50V8J

12

10K_0402_5%

10K_0402_5%

12

RE72

RE72

RE73

RE73

Pin8 5075_TXD for EC Debug
pin9 5048_TXD for SBIOS
debug

1 2

RE282 0_0402_5%

@

RE282 0_0402_5%

@

1 2

SUS_ON SUS_ON_EC

@

@

RE281 0_0402_5%

RE281 0_0402_5%

32 KHz Clock

1 2

YE1

YE1

32.768KHZ_12.5PF_Q1 3FC13500004 0

32.768KHZ_12.5PF_Q1 3FC13500004 0

CE28

CE28

100K_0402_5%

100K_0402_5%

12

RE75@

RE75@

+3.3V_ALW +3.3V_ALW_UE2

10U_0603_6.3V6 M

10U_0603_6.3V6 M

12

ACAV_IN ACAV_IN_NB

RE278 0_0402_5%

@

RE278 0_0402_5%

@

MEC_XTAL2

+3.3V_ALW

1 2

RE36 100K_0402_ 5%RE36 10 0K_0402_5%

1 2

RE37 2.2K_0402_5 %RE37 2.2K_040 2_5%

1 2

RE43 2.2K_0402_5 %RE43 2.2K_040 2_5%

D D

+3.3V_RUN

1 2

RE48 1 0K_0402_5 %RE48 1 0K_0402_5%

1 2

RE51 1 0K_0402_5 %RE51 1 0K_0402_5%

1 2

RE55 1 00K_0402_ 5%RE55 100K_04 02_5%

1 2

RE56 10K_0402_5%RE56 10K_0402_5%

1 2

RE86 10K_0402_5 %RE86 10K_04 02_5%

1 2

RE20 100K_0402 _5%RE20 100K_0402_ 5%

RPE10

RPE10

8
7

100K_0804_8P4R_ 5%

100K_0804_8P4R_ 5%

C C

B B

1

1

JTAG1 CONN@

@SHORT PADS~D

JTAG1 CONN@

@SHORT PADS~D

2

2

ACES_50521-01041-P01

ACES_50521-01041-P01

A A

HB_A531015-SCHR21

HB_A531015-SCHR21

1 2

CE21

CE21

SIO_SLP_S4#

1 2

12

@

@

PAD-OPEN1x1m

PAD-OPEN1x1m

22P_0402_50V8J

22P_0402_50V8J

CE29

CE29

4

+RTC_CELL

RE32@ 0_0402_5%RE32@ 0_0402_5%

+3.3V_ALW_UE2

+3.3V_ALW_UE2

PJP15

PJP15

0.1U_0402_25V6

0.1U_0402_25V6

@

@

12

12

CE16

CE16

for no-dock : A38 use LCD_TST
for no-dock : B41 use Free
for no-dock : A39 use SLP_ME_CSW_DEV#
for no-dock : B42 use Free

for no-dock : A21 use LID_CL_SIO#

trace width 20 mils
trace width 20 mils

for no-dock : A43 use BC_CLK_ECE1099
for no-dock : B45 use BC_DAT_ECE1099
for no-dock : A42 use BC_INT#_ECE1099

@EMC@RE66

@EMC@

10_0402_5%

10_0402_5%

RE66

Place close pin A29

BOARD_ID rise time is measured from 5%~68%.

4

1 2

0.1U_0402_25V6

0.1U_0402_25V6

12

12

CE17

CE17

0.1U_0402_25V6

0.1U_0402_25V6

12

CLK_PCI_MEC

@EMC@

4.7P_0402_50V8C

@EMC@

4.7P_0402_50V8C

CE34

CE34

EMI depop location

*

12

CE22

CE22

+RTC_CELL_VBAT

0.1U_0402_25V6

0.1U_0402_25V6

12

CE11

CE11

0.1U_0402_25V6

0.1U_0402_25V6

1U_0402_6.3V6K

1U_0402_6.3V6K

1

12

CE13

CE13

CE14

CE14

2

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_25V6

0.1U_0402_25V6

1

12

CE15

CE15

CE20

CE20

2

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

12

12

CE23

CE23

CE18

CE18

CE19

CE19

SML1_SMBDATA<7>
SML1_SMBCLK<7>

CLK_TP_SIO<37>
DAT_TP_SIO<37>

LCD_TST<23>

LCD_VCC_TEST_EN<23>

PBAT_SMBDAT<40>

PBAT_SMBCLK<40>

PS_ID<40>
SUSACK#<9>

BIA_PWM_EC<23>

BC_CLK_ECE1099<35>

BC_DAT_ECE1099<35>

BC_INT#_ECE1099<35>

SIO_SLP_S5#<9>
BEEP<21>
BC_CLK_ECE1117<37>

BC_DAT_ECE1117<37>

BC_INT#_ECE1117<37>

SIO_EXT_SMI#<12>

SIO_RCIN#<10,12>

IRQ_SERIRQ<10,12>

PCH_PLTRST#_EC<20,27,30,9>

CLK_PCI_MEC<7>

LPC_LFRAME#<20,7>

LPC_LAD0<20,7>
LPC_LAD1<20,7>
LPC_LAD2<20,7>
LPC_LAD3<20,7>

CLKRUN#<10,9>

SIO_EXT_SCI#<12>

12

MEC_XTAL2 MEC_XTAL2_R

RE61@ 0_0402_5%RE61@ 0_0402_5%

RE79 CE40

REV

X00

240K 4700p

X01

130K 4700p

4700p

X02

33K

1K

4700p

A00

3

+RTC_CELL

100K_0402_5%

100K_0402_5%

12

RE31

RE31

CE10@

CE10@

1 2

1U_0402_6.3V6K

1U_0402_6.3V6K

1 2

POWER_SW_IN#

RE33 10K_0402_5%RE33 10K_040 2_5%

1U_0402_6.3V6K

1U_0402_6.3V6K

12

CE12

CE12

UE2

UE2

B64

VBAT

A22

H_VTR

A58

VTR_ADC

B3

VTR

A11

VTR

A26

VTR

B35

VTR

A41

VTR

A52

VTR

A5

SML1_SMBDATA

GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA

B6

SML1_SMBCLK

GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK/GANG_DATA0

A37

CLK_TP_SIO

GPIO110/PS2_CLK2/GPTP-IN6

B40

DAT_TP_SIO BAT1_LED#

GPIO111/PS2_DAT2/GPTP-OUT6

A38

LCD_TST

GPIO112/PS2_CLK1A

B41

GPIO113/PS2_DAT1A

A39

LCD_VCC_TEST_EN

GPIO114/PS2_CLK0A

B42

GPIO115/PS2_DAT0A

B59

PBAT_SMBDAT

GPIO154/I2C1C_DATA/PS2_CLK1B/GANG_DATA5

A56

PBAT_SMBCLK

GPIO155/I2C1C_CLK/PS2_DAT1B/GANG_DATA6

A51

JTAG_TDI

GPIO145/I2C1K_DATA/JTAG_TDI

B55

JTAG_TDO

GPIO146/I2C1K_CLK/JTAG_TDO

B56

JTAG_CLK

GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK

A53

JTAG_TMS

GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS

B47

JTAG_RST#

JTAG_RST#

B22

FAN1_TACH

GPIO050/FAN_TACH1/GTACH0/GANG_START

A21

LID_CL_SIO#

GPIO051/FAN_TACH2/GANG _MODE

B23

SUS_ON_EC

GPIO052/FAN_TACH3/GTACH1/GANG_ERROR

B24

PS_ID

GPIO053/PWM0

A23

GPIO054/PWM1/GPWM1

B25

BIA_PWM_EC

GPIO055/PWM2

A24

FAN1_PWM

GPIO056/PWM3/GPWM0

A43

BC_CLK_ECE1099

GPIO123/BCM_A_CLK

B45

BC_DAT_ECE1099

GPIO122/BCM_A_DAT

A42

BC_INT#_ECE1099

GPIO121/BCM_A_INT#

B20

ACAV_IN_NB

GPIO032/BCM_E_CLK

A18

SIO_SLP_S5#

GPIO031/GPTP-OUT2/BCM_E_DAT

B19

BEEP

GPIO030/GPTP-IN2/BCM_E_INT#/GANG_DATA7

A20

BC_CLK_ECE1117

GPIO047/LSBCM_D_CLK

B21

BC_DAT_ECE1117

GPIO046/LSBCM_D_DAT/GANG_STROBE

A19

BC_INT#_ECE1117

GPIO045/LSBCM_D_INT#

A6

SIO_EXT_SMI#

GPIO011/nSMI

A27

SIO_RCIN#

GPIO061/LPCPD#

A28

IRQ_SERIRQ

SER_IRQ

B30

PCH_PLTRST#_EC

LRESET#

A29

CLK_PCI_MEC

PCI_CLK

B31

LPC_LFRAME#

LFRAME#

A30

LPC_LAD0

LAD0

B32

LPC_LAD1

LAD1

A31

LPC_LAD2

LAD2

B33

LPC_LAD3

LAD3

A32

CLKRUN#

CLKRUN#

A33

SIO_EXT_SCI#

GPIO100/NEC_SCI

A61

MEC_XTAL1

XTAL1

A62

XTAL2

AGND

VSS

B66

B11

B60

15mil

GPIO124/GPTP-OUT5/UART_RX/V2P_COUT_LO1

GPIO116/MSDATA/V2P_COUT_LO/TAP_SEL_STRAP

GPIO125/GPTP-IN5/PECI_REQUEST#/GANG_BUSY

VSS_ADC

VR_CAP

VSS_RO

H_VSS

B12

B54

B18

4.7U_0603_6.3 V6K

4.7U_0603_6.3 V6K

+VR_CAP

12

CE31

CE31

GPIO120/UART_TX/V2P_COUT_HI1

GPIO060/KBRST/BCM_B_INT#

GPIO117/MSCLK/V2P_COUT_HI

GPIO001/ECSPI_CS1/32KHZ_OUT

GPIO151/GPTP-IN4/GANG_DATA2

GPIO005/I2C1B_DATA/BCM_B_DAT

GPIO006/I2C1B_CLK/BCM_B_CLK

GPIO012/I2C1H_DATA/I2C2D_DATA

GPIO013/I2C1H_CLK/I2C2D_CLK/GANG_DATA3

GPIO130/I2C2A_DATA/BCM_C_DAT

GPIO131/I2C2A_CLK/BCM_C_CLK

GPIO141/I2C1F_DATA/I2C2B_DATA

GPIO142/I2C1F_CLK/I2C2B_CLK

PROCHOT_IN#/PROCHOT_IO#

EP

C1

GPIO021/RC_ID1
GPIO020/RC_ID2

GPIO014/GPTP-IN7/RC_ID3

GPIO025/UART_CLK

VCC_PWRGD

GPIO101/ECGP_SCLK
GPIO103/ECGP_MISO
GPIO105/ECGP_MOSI
GPIO102/BCM_C_INT#

GPIO104/SLP_S0#

GPIO127/A20M

GPIO156/LED1/GANG_DATA1

GPIO157/LED0

GPIO153/LED2/GANG_DATA4

GPIO027/GPTP-OUT1

GPIO026/GPTP-IN1

GPIO015/GPTP-OUT7

GPIO016/GPTP-IN8

GPIO017/GPTP-OUT8

GPIO107/NRESET_OUT

GPIO152/GPTP-OUT4

GPIO003/I2C1A_DATA

GPIO004/I2C1A_CLK

GPIO132/I2C1G_DATA

GPIO140/I2C1G_CLK

GPIO143/I2C1E_DATA

GPIO144/I2C1E_CLK

SYSPWR_PRES

VCI_OVRD_IN

VREF_PECI

PECI_DAT

DN1_DP1A/THERM
DP1_DN1A/VREF_T

DN2_DP2A
DP2_DN2A
DN3_DP3A
DP3_DN3A
DN4_DP4A
DP4_DN4A

THERMTRIP2#
GPIO002/THERMTRIP3#
GPIO024/THSEL_STRAP

MEC5085-LZY_DQFN132_11X11

MEC5085-LZY_DQFN132_11X11

POWER_SW#_MB <39,9>

A10
B10

BOARD_ID

B8

mCARD_PCIE#_SATA

B27

LAN_WAKE#

B44

HOST_DEBUG_TX

B46

ME_FWP_EC

B26

RUNPWROK

A25

EN_INVPWR

B36
B37
B38
A34

PCH_ALW_ON

A35

SIO_SLP_S3#

A36

PCH_DPWROK

GPIO106

A40

MSDATA

B43

MSCLK

A45

PCH_RSMRST#

B65

FWP#

nFWP

B57
B1
A55

BAT2_LED#

A1

ALW_PWRGD_3V_5V_EC

B28
B2
A8
B9

RUN_ON_EC

A9

PM_APWROK

B39

RESET_OUT#

A44

PCH_PCIE_WAKE#

A54

AC_PRESENT

B58

SIO_PWRBTN#

A3

EXPRESS_SMBDATA EXPRESS_SMBDATA

B4

EXPRESS_SMBCLK EXPRESS_SMBCLK

A4

A_ON

B5
B7
A7
B48

GPU_SMBDAT

B49

GPU_SMBCLK

A47

CHARGER_SMBDAT

B50

CHARGER_SMBCLK

B52
A49
B53

USH_SMBDAT

A50

USH_SMBCLK

A59

B62

BGP0

A64

ACAV_IN

A60

ALWON

VCI_OUT

B67

POWER_SW_IN#

VCI_IN0#

A63

DOCK_PWR_SW#

VCI_IN1#

B63

VCI_IN2#

VCI_IN2#

B68

POA_WAKE#

VCI_IN3#

B51

+PECI_VREF

A48

PECI_EC_RPECI_EC_R

B13

REM_DIODE1_N

A13

REM_DIODE1_P

B14

REM_DIODE2_N

A14

REM_DIODE2_P

A15
B16
A16

REM_DIODE4_N

B17

REM_DIODE4_P

B15

VIN

A17

VSET_5085

VSET

A12

VCP

B34

THERMATRIP2#

A2

THERMATRIP3#

B29

THSEL_STRAP

A46

H_PROCHOT#

1 2

B61

V_ISYS0

A57

RE64 4.7 K_0402_5%RE64 4. 7K_0402_5%

V_ISYS1

ESR <2ohms

+3.3V_RUN

10K_0402_5%

10K_0402_5%

12

RE67

RE67

100K_0402_5%

100K_0402_5%

RUNPWROK

RE68

RE68

DMN66D0LDW-7_SOT363 -6

DMN66D0LDW-7_SOT363 -6

34

QE2B

QE2B

5

RUN_ON#

DMN66D0LDW-7_SOT363 -6

DMN66D0LDW-7_SOT363 -6

QE2A

QE2A

BOARD_ID

+3.3V_ALW

+3.3V_ALW

12

6

2

RUN_ON<36,38>

130K_0402_5%

130K_0402_5%

12

RE79

RE79

4700P_0402_25 V7K

4700P_0402_25 V7K

12

CE40

CE40

1

+3.3V_ALW

10K_0402_5%

10K_0402_5%

12

RE81

RE81

FWP#

10K_0402_5%

10K_0402_5%

RE82@

RE82@

1 2

3

2

+3.3V_ALW

100K_0402_5%

100K_0402_5%

12

RE25

RE25

0.047U_0402_1 6V4Z

0.047U_0402_1 6V4Z

12

CE8

CE8

for no-dock : B2 use Free

RE57 1K_0402_5%RE57 1K_0402 _5%

100K_0402_5%

100K_0402_5%

12

RE58

RE58

PECI_EC <9>

C

C

2

B

B

E

E

QE3

QE3

3 1

MMBT3904WT1G_SC70-3~D

MMBT3904WT1G_SC70-3~D

MMBT3904WT1G_SC70-3~D

MMBT3904WT1G_SC70-3~D

E

E

31

B

B

2

C

C

QE7

QE7

C

C

2

B

B

E

E

QE6

QE6

3 1

MMBT3904WT1G_SC70-3~D

MMBT3904WT1G_SC70-3~D

2

12

RE26 10_0402_5%RE26 10_0402_5%

mCARD_PCIE#_SATA_R <6,7>

1 2

Location

CPU

DIMM

VGA

V.R

REM_DIODE1_P

REM_DIODE1_N

100P_0402_50V8 J

100P_0402_50V8 J

12

CE37@

CE37@

REM_DIODE4_P

REM_DIODE4_N

SIO_SLP_S3#

RUN_ON_EC

ALW_PWRGD_3V_5V_EC

0.1U_0402_25V6

0.1U_0402_25V6

CE25

CE25

12

C

C

B

B

E

E

QE5

QE5

3 1

MMBT3904WT1G_SC70-3~D

MMBT3904WT1G_SC70-3~D

2

LID_CL_SIO#

AC_DIS <46>

1 2

RE91 0_0402_5%

@

RE91 0_0402_5%

@

LAN_WAKE# <12,28>

ME_FWP_EC <6>
RUNPWROK <9>
EN_INVPWR <23>

SIO_SLP_S4# <9>
SIO_SLP_LAN# <38,9>

USB_PWR_SHR_EN# <31,35>
PCH_ALW_ON <38>
SIO_SLP_S3# <9>
PCH_DPWROK <9>

PCH_RSMRST# <37>

BREATH_LED# <39>

BAT1_LED# <39>

BAT2_LED# <39>

SIO_SLP_A# <9>

EC_32KHZ_MEC5085 <30>

ME_SUS_PWR_ACK <9>

PM_APWROK <9>

RESET_OUT# <15,9>

PCH_PCIE_WAKE# <35,9>

AC_PRESENT <9>

SIO_PWRBTN# <9>

A_ON <38>

SIO_EXT_WAKE# <12>

SYS_PWROK <9>

ENVDD_PCH <10,23>

CHARGER_SMBDAT <46>

CHARGER_SMBCLK <46>
SIO_SLP_SUS# <9>
PBAT_PRES# <40,46>

USH_SMBDAT <27>

USH_SMBCLK <27>

ACAV_IN <46>
ALWON <41>

1 2

RE60 43_0402_ 5%RE60 43_0402_ 5%

1 2

CE24 2200 P_0402_50V7 KCE24 2200P_0402_50V7K

1 2

CE26 2200 P_0402_50V7 KCE26 2200P_0402_50V7K

1 2

CE27 2200 P_0402_50V7 KCE27 2200P_0402_50V7K

CE24, CE26, CE27 Place near UE2

I_ADP <46>

H_PROCHOT# <45,46,9>

I_BATT <46>

I_SYS <46>

Setting for Thermal Design

Thermal diode mapping

5085 Channel

DP1/DN1

DP2/DN2

DN2a/DP2a WiGig

DP3/DN3

DP4/DN4

Place under CPU
Place CE35 close to the QE3 as possible

100P_0402_50V8 J

100P_0402_50V8 J

CE35@

CE35@

1 2

DP2/DN2 for SODIMM on QE5, place QE5 close
to SODIMM and CE37 close to QE5

DN2a/DP2a for WiGig on QE7, place QE7 close
to WiGig/WLAN and CE46 close to QE7

100P_0402_50V8 J

100P_0402_50V8 J

12

CE46@

CE46@

DP4/DN4 for Skin on QE6, place QE6 close to Vcore VR choke.

100P_0402_50V8 J

100P_0402_50V8 J

@

@

CE39

CE39

1 2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

LID_CL# <30,39>

1 2

RE280 0_0402_5%

@

RE280 0_0402_5%

@

1 2

RE279 0_0402_5%

@

RE279 0_0402_5%

@

1 2

RE283 0_0402_5%@RE283 0_0402_5%@

+3.3V_ALW2

Close to UE2 at least 250mils

+1.05V_RUN

REM_DIODE2_P

REM_DIODE2_N

RUN_ON <36,38>

ALW_PWRGD_3V_5V < 37,41>

GPU_SMBDAT
GPU_SMBCLK

BC_DAT_ECE1117
POA_WAKE#
VCI_IN2#

DOCK_PWR_SW#

THERMATRIP3#
CHARGER_SMBDAT
CHARGER_SMBCLK

PCH_RSMRST#

ACES_50277-0040N-001

ACES_50277-0040N-001

GND2
GND1

JFAN1

JFAN1

CONN@

CONN@

20130730 same as Goliad

+1.05V_RUN

1 2

RE70 2.2K_0 402_5%RE70 2.2K_0402_5%

H_THERMTRIP#<12>

0.1U_0402_25V6

0.1U_0402_25V6

1.58K_0402_1%

1.58K_0402_1%

12

12

CE38

CE38

RE77

RE77

Rest=1.58K , Tp=96 degree

DELL CONFIDENTIAL/PROPRIETARY

1

+3.3V_ALW

+3.3V_RUN

RPE3

RPE3

1

8

2

7

3

6

4 5

2.2K_0804_8P4R_ 5%

2.2K_0804_8P4R_ 5%

+3.3V_ALW

RPE5

RPE5

1

8

+RTC_CELL

2

7

3

6

4 5

100K_0804_8P4R_ 5%

100K_0804_8P4R_ 5%

12

RE62 100K_040 2_5%RE62 100K_0 402_5%

+3.3V_ALW

RPE6

RPE6

1

8

2

7

3

6

4 5

10K_8P4R_5%

10K_8P4R_5%

1 2

RE8847K_0402_5% RE8847K_0402_5%

6
5

4

4

3

FAN1_PWM

3

2

FAN1_TACH

2

1

1

12

reserve for DC fan

2

B

B

THSEL_STRAPVSET_5085

RE78 1K_0402_5 %R E78 1K_0402 _5%

Channel 1
Thermal Monitoring Interface Strap Option

HIGH
LOW

Compal E lectronics, Inc .

Compal E lectronics, Inc .

Compal E lectronics, Inc .

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

10U_0603_6.3V6 M

10U_0603_6.3V6 M

CE32

CE32

2 1

+3.3V_ALW

8.2K_0402_5%

8.2K_0402_5%

12

RE69

RE69

MMBT3904WT1G_SC70-3

MMBT3904WT1G_SC70-3

C

C

QE4

QE4

E

E

3 1

1 2

Thermistor Readings
Diode Readings

MEC50 85

MEC50 85

MEC50 85

LA-A972P

LA-A972P

LA-A972P

+5V_RUN

RB751S40T1G_SOD523-2

RB751S40T1G_SOD523-2

@

@

DE1

DE1

THERMATRIP2#

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

@

@

@

@

CE41

CE41

CE42

CE42

12

12

0.1U_0402_25V6

0.1U_0402_25V6

CE36

CE36

12

36 48Monday, March 17, 2014

36 48Monday, March 17, 2014

36 48Monday, March 17, 2014

0.1

0.1

0.1

5

D D

4

3

2

1

Touch Pad

+3.3V_RUN +3.3V_TP

@

@

PJP16

PJP16

1 2

PAD-OPEN1x1m

PAD-OPEN1x1m

DAT_TP_SIO<36>

CLK_TP_SIO<36>

C C

+3.3V_TP

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

12

12

RZ19

RZ19

RZ18

RZ18

DAT_TP_SIO

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

12

12

CZ30@EMC@

CZ30@EMC@

CZ31@EMC@

CZ31@EMC@

CLK_TP_SIO

EMI depop location

Keyboard

CONCR_205160FW010

CONCR_205160FW010

KB_DET#<11,12>

+5V_RUN

+3.3V_ALW

BC_INT#_ECE1117<36>

BC_DAT_ECE1117<36>

BC_CLK_ECE1117<36>

+3.3V_TP

DAT_TP_SIO

CLK_TP_SIO

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

GND1

18

GND2

JKBTP1

JKBTP1

CONN@

20130730 same as Goliad

CONN@

+5V_RUN+3.3V_ALW+3.3V_TP

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

12

12

12

CZ28@

CZ28@

CZ27@

CZ27@

Place close to JKBTP1

0.1U_0402_25V6

0.1U_0402_25V6

CZ29@

CZ29@

RSMRST circuit

+5V_ALW

33_0402_5%

@

33_0402_5%

@

12

RZ21

RZ21

UZ5

@UZ5

B B

A A

12

+5V_ALW_U41

0.01U_0402_16V7K

0.01U_0402_16V7K

@

@

CZ35

CZ35

@

1

VCC

RESET#

2

GND

RT9818A-44GU3_SC70-3

RT9818A-44GU3_SC70-3

+3.3V_ALW

10K_0402_5%

@

10K_0402_5%

@

12

RZ22

RZ22

3

RSMRST#

ALW_PWRGD_3V_5V<36,41>

PCH_RSMRST#<36>

1 2

RZ51 0_0402_5%

@

RZ51 0_0402_5%

@

1

2

+3.3V_ALW

B

A

CZ34@

CZ34@

1 2

0.1U_0402_25V6

0.1U_0402_25V6

5

P

4

O

G

UZ6

UZ6

3

TC7SH08FU_SSOP5~D

TC7SH08FU_SSOP5~D

PCH_RSMRST#_Q <9>

@eDP Cable

@eDP Cable

Part Number

Part Number

DC02C007P00 H-CONN SET 14A MB-EDP-LED-CAMERA

DC02C007P00 H-CONN SET 14A MB-EDP-LED-CAMERA

@eDP TS Cable

@eDP TS Cable

Part Number

Part Number

DC02C007Q00 H-CONN SET 14A MB-EDP-LED-CAMERA-TS

DC02C007Q00 H-CONN SET 14A MB-EDP-LED-CAMERA-TS

@DC-IN Cable

@DC-IN Cable

Part Number

Part Number

DC30100MF00 CONN SET 0VN DCJACK-MB 2DW1003-038110F

DC30100MF00 CONN SET 0VN DCJACK-MB 2DW1003-038110F

@RTC BATT

@RTC BATT

Part Number

Part Number

DC30100MF00 CONN SET 0VN DCJACK-MB 2DW1003-038110F

DC30100MF00 CONN SET 0VN DCJACK-MB 2DW1003-038110F

@FAN

@FAN

Part Number Description

Part Number Description

DC28A000800

DC28A000800

Description

Description

Description

Description

Description

Description

Description

Description

FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA

FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA

@USH Board FFC

@USH Board FFC

Part Number

Part Number

NBX0001KE00 FFC 26P G P0.5 PAD=0.3 47MM MB-USH

NBX0001KE00 FFC 26P G P0.5 PAD=0.3 47MM MB-USH

@KBTP FFC

@KBTP FFC

Part Number

Part Number

NBX0001KD00 FFC 16P G P0.5 PAD=0.3 82MM MB-KBTP

NBX0001KD00 FFC 16P G P0.5 PAD=0.3 82MM MB-KBTP

@NFC Board FFC

@NFC Board FFC

Part Number

Part Number

NBX0001KC00 FFC 15P F P0.5 PAD=0.3 40.5MM MB-NFC

NBX0001KC00 FFC 15P F P0.5 PAD=0.3 40.5MM MB-NFC

@FP FFC

@FP FFC

Part Number

Part Number

NBX0001KB00 FFC 8P F P0.5 PAD=0.3 22.5MM MB-FP

NBX0001KB00 FFC 8P F P0.5 PAD=0.3 22.5MM MB-FP

@SIM+Hall/B FFC

@SIM+Hall/B FFC

Part Number

Part Number

NBX0001CR00 FFC 12P G P0.5 PAD=0.3 73.3MM MB-SIM+HALL/B

NBX0001CR00 FFC 12P G P0.5 PAD=0.3 73.3MM MB-SIM+HALL/B

@Speak

@Speak

Part Number Description

Part Number Description

PK230003Q0L

PK230003Q0L

Description

Description

Description

Description

Description

Description

Description

Description

Description

Description

SPK PACK ZJX 2.0W 4 OHM FG

SPK PACK ZJX 2.0W 4 OHM FG

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Keyboard

Keyboard

Keyboard

LA-A972P

LA-A972P

LA-A972P

1

37 48Monday, March 17, 2014

37 48Monday, March 17, 2014

37 48Monday, March 17, 2014

0.1

0.1

0.1

5

4

3

2

1

1 2

1 2

1 2

12

CZ50

@CZ50

@

0.1U_0402_10V7K

0.1U_0402_10V7K

+3.3V_RUN_UZ9

PJP18 @

PJP18 @
PAD-OPEN1x3m

PAD-OPEN1x3m

CZ24 0.1U_0 402_10V7K@CZ24 0.1U_0402_10V7K@

1 2

PAD-OPEN1x2m

PAD-OPEN1x2m

+3.3V_ALW_PCH

12

+5V_RUN

12

+1.05V_M
Max Rating: 2495 mA

For No-Vpro HW configs

+1.05V_M +1.05V_RUN

1 2

RZ52 0.01_1206_1 %NVPRO@ RZ52 0.01 _1206_1%NVPRO@

1 2

PJP13@

PJP13@

+3.3V_M+3.3V_ALW

For No-Vpro HW configs

1 2

RZ54 0_0603_5 %NVPRO@ RZ54 0_0603_5%NVPRO @

PJP19

PJP19
PAD-OPEN1x1m

PAD-OPEN1x1m

@

@

1 2

CZ36 0.1U_0402_10V7K@CZ36 0.1U_0402 _10V7K@

1 2

CZ37 470P_0402_50V7KC Z37 470P_0402_50V7K

1 2

CZ62 470P_0402_50V7KC Z62 470P_0402_50V7K

1 2

CZ63 0.1U_040 2_10V7K@ CZ63 0.1U_040 2_10V7K@

PJP20

PJP20

12

+3.3V_LAN

PAD-OPEN1x1m

PAD-OPEN1x1m

@

@

PJP21

PJP21
PAD-OPEN1x3m

PAD-OPEN1x3m

@

@

1 2

CZ44 0.1U_0402_ 10V7K@ CZ44 0.1U_0402_ 10V7K@

1 2

CZ45 470P_0402_50V7KC Z45 470P_0402_50V7K

1 2

CZ46 1000P_0402_50V7KCZ46 1000P_0402_50V7K

PJP22@

PJP22@

1 2

+3.3V_RUN

0.1U_0402_10V7K

0.1U_0402_10V7K

PAD-OPEN1x3m

PAD-OPEN1x3m

12

CZ47

CZ47

@

@

+3.3V_M+3.3V_RUN

+1.05V_M +1.05V_MODPHY

QZ6

+1.05V_MODPHY

+3.3V_ALW2

100K_0402_5%

100K_0402_5%

2

12

RZ16

RZ16

MPHYP_PWR_EN#

DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

6

1

D D

MPHYP_PWR_EN<12>

+5V_ALW

100K_0402_5%

100K_0402_5%

12

RZ5

RZ5

DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

34

QZ10B

QZ10B

5

QZ10A

QZ10A

if support MODPHY off keep DSC solution

C C

B B

MODPHY timing spec 0.7V/us and <65us

SI3456DDV-T1-GE3_TSOP6

SI3456DDV-T1-GE3_TSOP6

1.05V_MODPHY_EN

QZ6

D

D

6

S

S

45
2
1

G

G

3

220P_0402_50V7K

220P_0402_50V7K

1

CZ25

CZ25

2

PJP36@

PJP36@

1 2

PAD-OPEN1x1m

PAD-OPEN1x1m

12

+1.05V_MODPHY+1.05V_RUN

+1.05V_RUN/+3.3V_M source

10U_0603_6.3V6M

10U_0603_6.3V6M

CZ38

CZ38

RUN_ON

A_ON

RUN_ON<36>

1 2

RZ41 0_0402_5%NVPRO@ RZ41 0_0 402_5%NVPR O@

1 2

RZ42 0_0402_5%VPRO@ RZ42 0_0402_5%VPRO@

A_ON<36>

+1.05V_M

+5V_ALW

RUN_ON

UZ2

VPRO@U Z2

VPRO@

1

VIN1

VOUT1

2

VIN1

VOUT1

3

ON1

CT1

4

VBIAS

GND

5

ON2

CT2

6

VIN2

VOUT2

VIN27VOUT2

GPAD

TPS22966DPUR_SON1 4_2X3

TPS22966DPUR_SON1 4_2X3

EN_+V1.05SP <43>

14
13

12

11

10

9
8

15

+1.05V_RUN_UZ7

VPRO@ CZ49

VPRO@

470P_0402_50V7K

470P_0402_50V7K

VPRO@ CZ23

VPRO@

470P_0402_50V7K

470P_0402_50V7K

+3.3V_M_UZ2

+1.05V_RUN

CZ49

CZ23

+3.3V_ALW_PCH/+3.3V_LAN source

+3.3V_ALW

UZ3

UZ3

1
2

PCH_ALW_ON<36 >

+5V_ALW

SIO_SLP_LAN#<36,9>

3

4

5

6

TPS22966DPUR_SON1 4_2X3

TPS22966DPUR_SON1 4_2X3

VIN1

VOUT1

VIN1

VOUT1

ON1

VBIAS

ON2

VIN2

VOUT2

VIN27VOUT2

GND

GPAD

CT1

CT2

14

+3.3V_ALW_PCH_UZ3

13

12

11

10

9

+3.3V_LAN_UZ3

8

15

+3.3V_RUN/+5V_RUN source

+5V_ALW

UZ9

UZ9

RUN_ON

+3.3V_ALW

1
2

3

4

5

6

TPS22966DPUR_SON1 4_2X3

TPS22966DPUR_SON1 4_2X3

VIN1

VOUT1

VIN1

VOUT1

ON1

VBIAS

ON2

VIN2

VOUT2

VIN27VOUT2

14

+5V_RUN_UZ9

13

12

CT1

11

GND

10

CT2

9
8

15

GPAD

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Power control

Power control

Power control

LA-A972P

LA-A972P

LA-A972P

1

38 4 8Monday, March 17, 2014

38 4 8Monday, March 17, 2014

38 4 8Monday, March 17, 2014

0.1

0.1

0.1

5

HDD LED solution for White LED

+3.3V_ALW

10K_0402_5%

10K_0402_5%

12

RZ24

RZ24

QZ3B

QZ3B

DMN66D0L DW-7_S OT363 -6

DMN66D0L DW-7_S OT363 -6

D D

SATA_A CT#<6>

MASK_SA TA_LED #< 35>

LED_SA TA_DIA G_OUT#<35>

DMN66D0L DW-7_S OT363 -6

DMN66D0L DW-7_S OT363 -6

5

QZ14B

QZ14B

5

DZ3

DZ3

34

1 2

RB751S 40T1G_ SOD52 3-2

RB751S 40T1G_ SOD52 3-2

DZ4

DZ4

1 2

RB751S 40T1G_ SOD52 3-2

RB751S 40T1G_ SOD52 3-2

34

DMN66D0L DW-7_S OT363 -6

DMN66D0L DW-7_S OT363 -6

SYS_LED_MASK#

DMN66D0L DW-7_S OT363 -6

DMN66D0L DW-7_S OT363 -6

MASK_BASE_LEDS #

QZ3A

QZ3A

126

QZ14A

QZ14A

126

SATA_LED#

4

3

2

1

Battery LED

+5V_ALW +5V_ ALW

LED7

LED7

21

W

W

43

Y

Y

2

2

1 3

+5V_ALW

1 3

PANEL_HDD_LED#

QZ4

QZ4

DDTA114EUA-7-F_SOT323-3

DDTA114EUA-7-F_SOT323-3

1 2

RZ27 6 80_04 02_5%RZ27 680_ 0402_ 5%

QZ12

QZ12

DDTA114EUA-7-F_SOT323-3

DDTA114EUA-7-F_SOT323-3

1 2

RZ36 270_ 0402_ 5%RZ 36 270_04 02_5%

PANEL_HD D_LED# <23>

LED6

LED6

2 1

SATA_LED

LTW-19 3ZDS5_ WHITE

LTW-19 3ZDS5_ WHITE

QZ5B

QZ5B

DMN66D0L DW-7_S OT363 -6

DMN66D0L DW-7_S OT363 -6

BAT2_L ED#<36>

BAT1_L ED#<36>

5

MASK_BASE_LEDS #

QZ5A

QZ5A

DMN66D0L DW-7_S OT363 -6

DMN66D0L DW-7_S OT363 -6

126

MASK_BASE_LEDS #

34

1 2

BAT2_LED#_Q BA TT_WHITE#

RZ25 3 90_04 02_5%RZ25 390_ 0402_ 5%

RZ43 1 K_040 2_5%R Z43 1 K_040 2_5%

BAT1_LED#_Q

RZ28 3 30_040 2_5%RZ28 330_04 02_5%

RZ44 3 90_04 02_5%RZ44 390_ 0402_ 5%

1 2

1 2

1 2

BATT_YELLOW#

LTW-29 5DSKS-5 A_YEL-W HITE

LTW-29 5DSKS-5 A_YEL-W HITE

BATT_W HITE_L ED# <2 3>

BATT_YE LLOW_ LED# <23>

WLAN LED solution for White LED

C C

WIREL ESS_LE D#<30,35>

B B

+3.3V_ALW

100K_0402_5%

100K_0402_5%

12

RZ31

RZ31

QZ7A

QZ7A

DMN66D0L DW-7_S OT363 -6

DMN66D0L DW-7_S OT363 -6

126

MASK_BASE_LEDS #

+3.3V_ALW

CZ48@

CZ48@

1 2

0.1U_040 2_25V6

0.1U_040 2_25V6

5

1

SYS_LED _MASK#<28,35>

LID_CL #<30 ,36>

B

2

A

P

4

MASK_BASE_LEDS #

O

G

UZ10

UZ10

TC7SH08 FU_SSOP 5~D

TC7SH08 FU_SSOP 5~D

3

POWER & INSTANT ON SWITCH

POWER _SW#_ MB<36,9 >

SW2

SW2

2

4

SKRBAA E010_4 P

SKRBAA E010_4 P

+5V_ALW

2

1

3

QZ9

QZ9

DDTA114EUA-7-F_SOT323-3

DDTA114EUA-7-F_SOT323-3

1 3

1 2

RZ33 3 90_04 02_5%RZ33 390_ 0402_ 5%

WLAN_LED

LED5

LED5

2 1

LTW-19 3ZDS5_ WHITE

LTW-19 3ZDS5_ WHITE

Breath LED

BREATH_ LED#<36>

QZ7B

QZ7B

DMN66D0L DW-7_S OT363 -6

DMN66D0L DW-7_S OT363 -6

5

MASK_BASE_LEDS #

34

BREATH_LED#_Q

LED3

LED3

LTW-19 3ZDS5_ WHITE

LTW-19 3ZDS5_ WHITE

1 2

BREATH_WHITE_L EDBREATH_WHITE_LED_ SNIFF

Place LED3 close to SW3

1 2

RZ34 6 80_040 2_5%RZ34 680_0 402_5 %

BREATH_WHITE_L ED#

1 2

RZ32 270_ 0402_ 5%RZ 32 270_04 02_5%

BREATH_ WHITE_ LED# < 23>

+5V_ALW

LED Circuit Control Table

SYS_LED_MASK# LID_CL#

Fiducial Mark

FD1@

FD1@

1

FIDUCIA L MARK~D

FIDUCIA L MARK~D

FD2@

FD2@

A A

1

FIDUCIA L MARK~D

FIDUCIA L MARK~D

FD3@

FD3@

1

FIDUCIA L MARK~D

FIDUCIA L MARK~D

FD4@

FD4@

1

FIDUCIA L MARK~D

FIDUCIA L MARK~D

Mask All LEDs (Sniffer Function)
Mask Base MB LEDs (Lid Closed)
Do not Mask LEDs (Lid Opened) 11

H1@

H1@

H_2P5

H_2P5

H_2P3

H_2P3

1

H7@

H7@

H_2P5

H_2P5

H_2P8

H_2P8

1

5

0
1 0

H16@

H4@

H4@

H2@

H2@

1

H8@

H8@

1

H6@

H6@

H3@

H3@

H5@

H5@

H_2P8

H_2P8

H_2P8

H_2P8

H_2P5

H_2P5

H_2P8

H_2P8

1

1

1

1

H10@

H10@

H12@

H12@

H18@

H9@

H9@

H_2P8

H_2P8

1

H18@

H11@

H11@

H_2P8

H_2P8

H_2P8

H_2P8

H_2P8

H_2P8

H_2P8

H_2P8

1

1

1

H16@

H13@

H13@

H15@

H15@

H14@

H14@

H_3P4

H_3P4

H_3P4

H_3P4

H_3P4

H_3P4

H_3P4

H_3P4

1

1

1

H17@

H17@

H_2P8

H_2P8

1

1

4

X

H21@

H21@

H20@

H20@

H19@

H19@

H_3P0N

H_3P0N

H_3P0N

H_3P0N

H_2P1

H_2P1

1

ST1

@S T1

@

ST2@

ST2@

CLIP_C 5P1

CLIP_C 5P1

H_3P3

H_3P3

1

1

1

1

ST3@

ST3@

H_3P3

H_3P3

1

1

3

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Do cument Numbe r Rev

Size Do cument Numbe r Rev

Size Do cument Numbe r Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

PAD, LED

PAD, LED

PAD, LED

LA-A972P

LA-A972P

LA-A972P

1

39 48Monday, March 17, 201 4

39 48Monday, March 17, 201 4

39 48Monday, March 17, 201 4

0.1

0.1

0.1

5

D D

Primary Battery Connector

LLTOP_ALLTOP C144 LS-109A9-L 9P BATT P2

LLTOP_ALLTOP C144 LS-109A9-L 9P BATT P2

1

1

2

2

3

PBAT_SMBCLK_C

3

4

PBAT_SMBDAT_C

4

5

12

PC3

PC3

C C

2200P_0402_50V7K~D

2200P_0402_50V7K~D

GND
GND

@

@

PBATT1

PBATT1

PBAT_PRES#_C

5

6

6

7

7

8

8

9

9

10
11

4

1

EMC@

EMC@

PD1

PD1
TVNST52302AB0_SOT523-3

TVNST52302AB0_SOT523-3

2

3

GND

1

PD2

PD2
TVNST52302AB0_SOT523-3

TVNST52302AB0_SOT523-3

2

3

PRP2

PRP2

100_0804_ 8P4R_5%

100_0804_ 8P4R_5%

EMC@

EMC@

18
27
36
45

3

PBATT+_C

PBAT_SMBCLK <37>
PBAT_SMBDAT <37 >

PL1

PL1

EMC@

EMC@

FBMJ4516HS72 0NT_2P~D

FBMJ4516HS72 0NT_2P~D

1 2

PL2

PL2

EMC@

EMC@

FBMJ4516HS72 0NT_2P~D

FBMJ4516HS72 0NT_2P~D

1 2

+PBATT

2

+3.3V_ALW

12

PR2

PR2

100K_0402 _5%

100K_0402 _5%

+3.3V_RTC_LDO

PD3

PD3

BAS40CW_SOT32 3-3

BAS40CW_SOT32 3-3

+COINCELL

12

PR1

PR1
1K_0402_5 %

1K_0402_5 %

+Z4012

2

3

1

PBAT_PRES# <36,48>

COIN RTC Battery

+COINCELL

+RTC_CELL

1

PC1

PC1
1U_0603_10V4Z

1U_0603_10V4Z

2

1

JRTC1

@JRTC1

@

1

1

G

22G

TYCO_2-177529 3-2~D

TYCO_2-177529 3-2~D

3
4

+3.3V_ALW

PR7

@ PR7

@

1 2

0_0402_5%

PL3

EMC@PL3

EMC@

BLM15AG102SN1D_2 P

BLM15AG102SN1D_2 P

NB_PSID

B B

12

PR10

100K_0402 _1%

100K_0402 _1%

15K_0402_ 1%

15K_0402_ 1%

PR10

PR12

PR12

2

3

PD5

PD5
AZC199-02SPR7 G_SOT23-3

AZC199-02SPR7 G_SOT23-3

EMC@

EMC@

1

0_0402_5%

1 3

D

D

1 2

2

B

B

E

E

1 2

S

S

PQ2

PQ2
FDV301N-G_SOT23-3

FDV301N-G_SOT23-3

G

G

2

C

C

PQ3

PQ3
MMST3904-7-F_SO T323-3

MMST3904-7-F_SO T323-3

3 1

PR9

PR9

33_0402_5 %

33_0402_5 %

1 2

+5V_ALW

12

PR11

PR11
10K_0402_ 1%

10K_0402_ 1%

PR8

PR8

2.2K_0402_ 5%

2.2K_0402_ 5%

1 2

PS_ID <36>

DC_IN+ Source

PL4

EMC@ PL4

EMC@

FBMJ4516HS72 0NT_2P

FBMJ4516HS72 0NT_2P

1 2

ACES_50299-00 50N-001

ACES_50299-00 50N-001

7

GND

6

GND

5

-DCIN_JACK

5

4

4

3

3

A A

2

2

1

1

@

@

PJPDC1

PJPDC1

5

+DCIN_JACK

EMC@PC9

EMC@

PC9

12

1000P_0603_50V7K

1000P_0603_50V7K

PJP1

PJP1

1 2

PAD-OPEN 1x3m

PAD-OPEN 1x3m

12

EMC@PC22

EMC@

PR16

PR16

PC22

10U_0805_25V6K

10U_0805_25V6K

@

@

+DC_IN

12

4.7K_0805_5%

4.7K_0805_5%

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR D ISCLOSED TO ANY THIRD PA RTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

3

2

Title

+DCIN

+DCIN

+DCIN

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

LA-A902P

LA-A902P

LA-A902P

1

40 47Monday, Ma rch 17, 2014

40 47Monday, Ma rch 17, 2014

40 47Monday, Ma rch 17, 2014

0.1

0.1

0.1

A

DELL CONFIDENTIAL/PROPRIETARY

PC105

PC105

2200P_0402_50V7K

2200P_0402_50V7K

EMC12UnonD@

EMC12UnonD@

1 1

PL100

@EMC@PL100

@EMC@

1UH +-20% 6.6A 5X5X3 MOLDING

1UH +-20% 6.6A 5X5X3 MOLDING

1 2

1 2

PAD-OPEN 1x3m

PAD-OPEN 1x3m

2 2

+PWR_SRC

+3.3V_ALWP

3 3

+3V5V_PWR_SRC

PJP100

PJP100

2.2UH +-20% 7.8A 7X7X3 MOLDING

2.2UH +-20% 7.8A 7X7X3 MOLDING

1 2

1

+

+

PC113

PC113

2

150U_D_6.3VM_R15M

150U_D_6.3VM_R15M

12

12

PC101

PC101

PC105

PC105

10U_0805_25V6K

10U_0805_25V6K

2200P_0402_50V7K

2200P_0402_50V7K

@EMC@

@EMC@

SIS412DN-T1-GE3_POWERPAK8-5

SIS412DN-T1-GE3_POWERPAK8-5

PL101

PL101

PR111

PR111

@EMC@

@EMC@

4.7_1206_5%

4.7_1206_5%

PC111

@EMC@ PC111

@EMC@

680P_0603_50V7K

680P_0603_50V7K

PQ100

PQ100

12

SNUB_3V

12

B

ALW_PW RGD_3V_5V<36>

3 5

241

PQ102

PQ102
SI7716ADN-T1-GE3_POWERPAK8-5

SI7716ADN-T1-GE3_POWERPAK8-5

3 5

241

+3.3V_ALW

100K_0402_1%

100K_0402_1%

0_0402_5%

0_0402_5%

1 2

PC109

PC109

0.1U_0603_25V7K

0.1U_0603_25V7K

1 2

+3.3V_ALW2

PR100

PR100

6.49K_0402_1%

6.49K_0402_1%

1 2

PR102

PR102

10K_0402_1%

10K_0402_1%

1 2

20K_0402_1%

20K_0402_1%

PR105

PR105

12

PR107

PR107

PR108

PR108

PGOOD_3V_5V

PR110

PR110

2.2_0603_5%

2.2_0603_5%

1 2

BST_3V_C B ST_3V

+3V5V_PWR_SRC

12

EN

UG_3V

SW2

LG_3V

+3.3V_RTC_LDO

12

PR103

PR103

0_0402_5%

0_0402_5%

PU100

PU100

5

CS2

6

EN2

7

PGOOD

10

TPS51285BRUKR_QFN20_3X3

TPS51285BRUKR_QFN20_3X3

DRVH2

9

VBST2

8

SW2

DRVL211VIN12VREG5

PC117

PC117

0.1U_0603_25V7K

0.1U_0603_25V7K

C

PR101

PR101

15K_0402_1%

15K_0402_1%

1 2

PR104

PR104

10K_0402_1%

10K_0402_1%

1 2

12

PC100

PC100

4.7U_0603_10V6K

4.7U_0603_10V6K

3

4

VFB2

VREG3

13

12

12

16.9K_0402_1%

16.9K_0402_1%

PR106

PR106

1

2

21

CS1

PAD

VFB1

14

VO1

PR114

PR114

200_0402_1%

200_0402_1%

19

1 2

VCLK

16

UG_5V

DRVH1

17

VBST1

18

SW1

DRVL1

EN1

15

20

EN

12

PC118

PC118

4.7U_0603_10V6K

4.7U_0603_10V6K

+5V_ALW2

PR109

PR109

2.2_0603_5%

2.2_0603_5%

1 2

BST_5V BST_5V_C

SW1

LG_5V

D

PC110

PC110

0.1U_0603_25V7K

0.1U_0603_25V7K

1 2

SI7716ADN-T1-GE3_POWERPAK8-5

SI7716ADN-T1-GE3_POWERPAK8-5

PQ103

PQ103

PQ101

PQ101

3 5

241

SIS412DN-T1-GE3_POWERPAK8-5

SIS412DN-T1-GE3_POWERPAK8-5

3 5

241

+3V5V_PWR_SRC

12

PC102

PC102

10U_0805_25V6K

10U_0805_25V6K

PL102

PL102

3.3UH +-20% 6.3A 7X7X3 MOLDING

3.3UH +-20% 6.3A 7X7X3 MOLDING

1 2

12

@EMC@

@EMC@

PR112

PR112

4.7_1206_5%

4.7_1206_5%

SNUB_5V

12

@EMC@

@EMC@

PC114

PC114

680P_0603_50V7K

680P_0603_50V7K

E

+5V_ALWP

1

+

+

PC115

PC115

2

150U_D_6.3VM_R15M

150U_D_6.3VM_R15M

EN

PR113

3.3 VALWP
TDC: 4.5 A
Peak Current: 6.4 A
OCP Current: 7.68 A
Cap ESR(@20 ): 18 mohm
Choke DCR(@20 ): 15.5 mohm

TYP MAX
H/S Rds(on) :24.0 mohm , 30.0 mohm
L/S Rds(on) :13.5 mohm , 16.5 mohm

4 4

℃

℃

A

ALWON<36>

B

PR113

0_0402_5%

0_0402_5%

1 2

PJP101

PJP101

+5V_ALWP

+3.3V_ALWP

12

PC119

PC119

1U_0603_10V6K

1U_0603_10V6K

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

1 2

PAD-OPEN 1x3m

PAD-OPEN 1x3m

PJP102

PJP102

1 2

PAD-OPEN 1x3m

PAD-OPEN 1x3m

+5V_ALW

+3.3V_ALW

D

5 VALWP
TDC: 3.5 A
Peak Current: 5.0 A
OCP Current: 6.0 A
Cap ESR(@20 ): 18 mohm
Choke DCR(@20 ): 25 mohm

TYP MAX
H/S Rds(on) :24.0 mohm , 30.0 mohm
L/S Rds(on) :13.5 mohm , 16.5 mohm

℃

℃

Compal Ele ctronics, Inc.

Compal Ele ctronics, Inc.

Compal Ele ctronics, Inc.

Title

Title

Title

Size Doc ument Number Rev

Size Doc ument Number Rev

Size Doc ument Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

+5V_ALW/3.3V_ALW

+5V_ALW/3.3V_ALW

+5V_ALW/3.3V_ALW

LA-A902P

LA-A902P

LA-A902P

E

41 47Monday, March 17, 2014

41 47Monday, March 17, 2014

41 47Monday, March 17, 2014

0.1

0.1

0.1

5

PC203

PC203

2200P_0402_50V7K

2200P_0402_50V7K

EMC12UnonD@

EMC12UnonD@

PJP200

+PWR_SRC

D D

PJP200

PAD-OPEN 1x2m~D

PAD-OPEN 1x2m~D

21

1.35V_B+

12

12

PC201

PC201

PC200

PC200

@

@

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

+1.35V_MEN_P

PL200

PL200

1UH +-20% 11A 7X7X3 MOLDING

1UH +-20% 11A 7X7X3 MOLDING

1 2

220U_D2_2VY_R17M

220U_D2_2VY_R17M

C C

B B

1.35 _MEN
TDC: 6.6 A
Peak Current: 9.5 A
OCP Current: 11.4 A
Cap ESR(@20 ): 17 mohm
Choke DCR(@20 ): 7.4 mohm

TYP MAX
H/S Rds(on) : 24.0 mohm , 30.0 mohm
L/S Rds(on) : 13.5 mohm , 16.5 mohm

A A

1

PC207

PC207

+

+

2

℃

℃

Mode S3 S5 +1.35V_MEN +V_DDR_REF +0.675V_P
S5 L L off off off
S3 L H on on off(Hi-Z)
S0 H H on on on

5

12

PR203

PR203

4.7_1206_5%

4.7_1206_5%

SNUB_1.35V

12

PC208

PC208

680P_0603_50V7K

680P_0603_50V7K

@EMC@

@EMC@

@EMC@

@EMC@

SUS_ON<36,38>

SI7716ADN-T1-GE3_POWERPAK8-5

SI7716ADN-T1-GE3_POWERPAK8-5

4

12

PC203

PC203

2200P_0402_50V7K

2200P_0402_50V7K

@EMC@

@EMC@

PQ200

SIS412DN-T1-GE3_POWERPAK8-5

SIS412DN-T1-GE3_POWERPAK8-5

PQ200

PQ201

PQ201

PR207

PR207

0_0402_5%

0_0402_5%

1 2

+1.35V_MEN_P

4

3

PR200

PR200

1 2

2.2_0603_5%

2.2_0603_5%

BOOT_1.35V_C

12

PC204

PC204

0.22U_0603_16V7K

0.22U_0603_16V7K

3 5

241

PR202

PR202

1 2

5.1_0603_5%

+5V_ALW

3 5

241

5.1_0603_5%

BOOT_1.35V

PR201

PR201

19.6K_0402_1%

19.6K_0402_1%

1 2

1U_0603_10V6K

1U_0603_10V6K

PC211

PC211

1U_0603_10V6K

1U_0603_10V6K

DH_1.35V

SW_1.35V

DL_1.35V

PC209

PC209

VDD_1.35V

CS_1.35V

12

15

14

13

12

11

PR204

PR204
0_0603_5%

0_0603_5%

16

17

PHASE

UGATE

LGATE

PGND

CS

RT8207MZQW_W QFN20_3X3

RT8207MZQW_W QFN20_3X3

VDDP

VDD

PGOOD

TON

9

10

18

BOOT

S5

8

+5V_ALW

PR206

PR206

1.35V_B+

S5_1.35V

12

PC215

@

PC215

@

.1U_0402_16V7K

.1U_0402_16V7K

PJP203

PJP203

2

112

JUMP_1x3m

JUMP_1x3m

PJP204

PJP204

2

112

JUMP_1x3m

JUMP_1x3m

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

0.675V_DDR_VTT_ON<18>

+1.35V_MEM

3

1 2

768K_0402_1%

768K_0402_1%

PR210

PR210

0_0402_5%

0_0402_5%

1 2

+1.35V_MEN_P

FB sense trace

+0.675V_P

+VLDOIN_1.35V

19

VLDOIN

S3

7

2

PJP201

PJP201

1 2

PAD-OPEN1x1m

PAD-OPEN1x1m

20

PU200

PU200

21

VTT

PAD

1

VTTGND

2

VTTSNS

3

GND

4

+V_DDR_REF

VTTREF

5

VDDQ

FB sense trace

FB

when FB pull down to GND

6

PR205

PR205

8.06K_0402_1%

8.06K_0402_1%

PJP202

PJP202

1 2

PAD-OPEN1x1m

PAD-OPEN1x1m

1 2

PC213

PC213

100P_0402_50V8J

100P_0402_50V8J

1 2

12

10K_0402_1%

10K_0402_1%
PR209

PR209

1.35V_FB

DELL CONFIDENTIAL/PROPRIETARY

2

1

0.675 Volt
TDC 0.7 A
Peak Current 1.0 A
OCP Current 2.6 A

+1.35V_MEN_P

+0.675V_P

12

PC205

PC205

22U_0805_6.3V6M

22U_0805_6.3V6M

+V_DDR_REF

+1.35V_MEN_P

PC212

PC212

0.033U_0402_16V7K

0.033U_0402_16V7K

12

PC214

PC214

@

@

.1U_0402_16V7K

.1U_0402_16V7K

+0.675V_DDR_VTT

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

+1.35V_MEN/+0.675V_DDR_VTT

+1.35V_MEN/+0.675V_DDR_VTT

+1.35V_MEN/+0.675V_DDR_VTT

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

LA-A902P

LA-A902P

LA-A902P

42 47Monday, March 17, 2014

42 47Monday, March 17, 2014

42 47Monday, March 17, 2014

1

0.1

0.1

0.1

5

+1.05V_MEN
TDC: 5.7 A

D D

Peak Current: 8.1 A
OCP Current: 9 .7 A fix by IC
Choke DCR(@20 ): 14.0 mohm

℃

4

3

2

1

PC300

PC300

2200P_0402_50V7K

2200P_0402_50V7K

EMC12UnonD@

EMC12UnonD@

1M_0402_1%

1M_0402_1%
PR303

PR303

PR305

PR305

4.7_1206_5%

4.7_1206_5%

1 2

PL301

PL301

1 2

EN_+V1.05SP <9,36>

@EMC@

@EMC@

680P_0603_50V7K

680P_0603_50V7K

1 2

SNB_1.05V

12

12

PC301

PC301

PR307

PR307

7.5K_0402_1%

7.5K_0402_1%

PR309

PR309

1K_0402_5%

1K_0402_5%

PR310

PR310
10K_0402_1%

10K_0402_1%

+1.05V_MP

PAD-OPEN 1x2m~D

PAD-OPEN 1x2m~D

+1.05V_MP

12

12

PC304

PC304

12

12

12

12

PC305

PC305

PC306

PC306

PC307

PC307

PC308

47U_0805_6.3V6M

47U_0805_6.3V6M

47U_0805_6.3V6M

330P_0402_50V7K

330P_0402_50V7K

47U_0805_6.3V6M

PC308

22U_0805_6.3VAM

22U_0805_6.3VAM

22U_0805_6.3VAM

22U_0805_6.3VAM

@

@

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

+1.05V_M

+1.05V_M

+1.05V_M

LA-A902P

LA-A902P

LA-A902P

PJP300

PJP300

21

+1.05V_M

0.1

0.1

43 47Monday, March 17, 2014

43 47Monday, March 17, 2014

43 47Monday, March 17, 2014

1

0.1

12

@EMC@

@EMC@

+PWR_SRC

C C

+3.3V_ALW

12

PR306

@

PR306

@

0_0402_5%

0_0402_5%

ILMT_1.05V

12

@

@

PR308

B B

A A

PR308
0_0402_5%

0_0402_5%

PAD-OPEN 1x2m~D

PAD-OPEN 1x2m~D

5

PJP302

PJP302

PU300

PU300

21

12

PC300

PC300

2200P_0402_50V7K

2200P_0402_50V7K

@EMC@

@EMC@

1.05V_M_PWRGD
<15>

+3.3V_ALW

PC303

PC303

10U_0805_25V6K

10U_0805_25V6K

+V1.05SP_B+

12

PR313

PR313

0_0402_5%

0_0402_5%

1 2

PR315

PR315

1 2

100K_0402_1%

100K_0402_1%

4

1.05V_MP_PWROK

8

IN

9

GND

3

ILMT_1.05V

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

ILMT

2

PG

SY8208DQNC_QFN10_3X3

SY8208DQNC_QFN10_3X3

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

1

PC302

EN

BYP

LDO

PC302

0.1U_0603_25V7K

0.1U_0603_25V7K

1 2

6

BS

10

LX

4

FB

7

5

12

12

PC309

PC309

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

PC310

PC310

3

BST_+V1.05SP_CBST_+V1.05SP

+3.3V_ALW

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

PR312

PR312

0_0603_5%

0_0603_5%

1 2

0.68UH +-20% 7.9A 5X5X3 MOLDING

0.68UH +-20% 7.9A 5X5X3 MOLDING

SW_+V1.05SP

FB_+V1.05SP

5

4

3

2

1

D D

+1.5V_RUN
TDC: 0.47 A
Peak Current: 0.67 A

+3.3V_RUN

+5V_ALW

12

PC400

PC400

1U_0402_6.3V6K

1U_0402_6.3V6K

PC402

PC402

7

8

@EMC@

@EMC@

POK

EN

6

5

VIN

4

VOUT

VCNTL

3

VOUT

2

FB

9

VIN

GND

PU400

PU400

1

APL5930KAI-TRG_SO8

APL5930KAI-TRG_SO8

C C

B B

A A

+3.3V_RUN

1 2

100K_0402_5%

100K_0402_5%

47K_0402_5%

47K_0402_5%

PR400

PR400

12

12

@

@

PR401

PR401

.1U_0402_16V7K

.1U_0402_16V7K

PJP400

PJP400

PAD-OPEN1x1m

PAD-OPEN1x1m

+1.5V_VIN

12

12

PC401

PC401

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K

PR402

PR402

8.66K_0402_1%

8.66K_0402_1%

12

12

PR403

PR403
10K_0402_1%

10K_0402_1%

1.5VSP

12

PC403

PC403

0.01U_0402_25V7K

0.01U_0402_25V7K

PAD-OPEN1x1m

PAD-OPEN1x1m

12

PC404

PC404
22U_0805_6.3V6M

22U_0805_6.3V6M

PJP401

PJP401

1 2

+1.5V_RUN

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

+1.5VSP

+1.5VSP

+1.5VSP

LA-A902P

LA-A902P

LA-A902P

0.1

0.1

44 47Monday, March 17, 2014

44 47Monday, March 17, 2014

44 47Monday, March 17, 2014

1

0.1

5

VREF

100K 1% 0402 B25/50 4250K

100K 1% 0402 B25/50 4250K

12

12

VREF

PC507

PC507

@

@

PH500

PH500

PC501

PC501

12

PR529

PR529

PR524

PR524

12

.1U_0402_16V7K

.1U_0402_16V7K

15

16

14

13

VBAT

SLEWA

THERM

COMP26VCLK31V5A28DROP25ALERT#

29

27

12

12

12

110_0402_1%

110_0402_1%

OCP-I

12

PC500

PC500

4700P_0603_50V7K

4700P_0603_50V7K

12

11

10

9

IMON

OCP-I

O-USR

F-IMAX

B-RAMP

PGOOD

GND33GND

VR_HOT#30VREF

TPS51624RSM QFN 32P VCORE IC

TPS51624RSM QFN 32P VCORE IC

32

VR_HOT#

12

1U_0603_10V7K

1U_0603_10V7K

PC510

PC510

PC514

PC514

PC511

PC511

0.1U_0402_25V6

0.1U_0402_25V6

12

75_0402_1%

75_0402_1%

PR500

PR500

@

@

D D

+VCC_PWR_SRC

+3.3V_RUN
+3.3V_RUN

C C

B B

VIDSCLK<15>

VIDALERT_N<15>

VIDSOUT<15>

A A

1 2

PR535

PR535

4.75K_0402_1%

4.75K_0402_1%

SLEWA

39K_0402_5%~N

39K_0402_5%~N

PR511

PR511

1 2

10K_0402_5%

10K_0402_5%

PC506

@

PC506

@

1 2

100P_0402_50V8J

100P_0402_50V8J

PR523

PR523

1 2

10K_0402_5%

10K_0402_5%

PC512

PC512

1500P_0402_50V7K

1500P_0402_50V7K

+5V_ALW

PR510

PR510

CSN1

GFB

1 2

12

CSP1

VFB

PR527

PR527

54.9_0402_1%

54.9_0402_1%

PR505

PR505

12

10K_0402_5%

10K_0402_5%

PU500

PU500

17

CSP1

18

CSN1

19

CSN2

20

CSP2

21

PU3

22

N/C

23

GFB

24

VFB

PR521

PR521

1 2

4.22K_0402_1%

4.22K_0402_1%

0.33U_0603_10V7K

0.33U_0603_10V7K

1 2

PR526

PR526

10_0603_1%

10_0603_1%

H_PROCHOT#<9,36,46>

+1.05V_VCCST

12

PR528

PR528

@

@

75_0402_1%

75_0402_1%

+VCC_PWR_SRC

12

PR518

@

PR518

@

2M_0402_1%

2M_0402_1%

1 2

12

2M_0402_1%

2M_0402_1%

PR525

@

PR525

@

27K_0402_1%

27K_0402_1%

VR_ON

12

SKIP#
PWM1
PWM2

PR534

PR534

4

IMON

12

12

75_0402_1%

75_0402_1%

F-IMAX

12

150K_0402_1%

150K_0402_1%

H_VR_EN <15>

@

@

PR513

PR513

1 2

75_0402_1%

75_0402_1%

PR516

@

PR516

@

1 2

1.91K_0402_1%

1.91K_0402_1%

PR519

PR519

1 2

1_0603_5%

1_0603_5%

PC505

1U_0603_10V6K

PC505

1U_0603_10V6K

VCCSENSE<15>

from processor

VSSSENSE<17>

12

PR503

PR503

12

PR508

PR508

@

@

PR501

PR501

PR502

PR502

316K_0402_1%

316K_0402_1%

OCP-I

B-RAMP

12

PR506

PR506

PR507

PR507

39K_0402_1%

39K_0402_1%

PR536

PR536

1 2

0_0402_5%

0_0402_5%

SKIP#

8

PWM1

7
6
5
4

N/C

3
2

VDD

1

VDIO

VIDSOUT

12

0_0402_5%

0_0402_5%

VIDALERT_N

VIDSCLK

47P_0402_50V8J

47P_0402_50V8J

681K_0402_1%

681K_0402_1%

100K_0402_1%

100K_0402_1%

PR504

PR504

O-USR

PR509

PR509

+3.3V_RUN

+3.3V_RUN

12

36.5K_0402_1%

36.5K_0402_1%

12

20K_0402_1%

20K_0402_1%

0_0402_5%

0_0402_5%

1 2

+PWR_SRC

PR539

PR539

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

3

1 2

PAD-OPEN 4x4m

PAD-OPEN 4x4m

@EMC@

@EMC@

1 2

FBMA-L11-453215800LMA90T_2P

FBMA-L11-453215800LMA90T_2P

H_VR_READY <15>

PWM1

TI recommend 1 nF

PR531

PR531

1 2

VFB

PR532

PR532

1 2

GFB

PJP500

PJP500

PL501

PL501

PC503

PC503

1000P_0402_50V7K

1000P_0402_50V7K

1 2

PR522

PR522

4.7_1206_5%

4.7_1206_5%

EMC12UnonD@

EMC12UnonD@

+VCC_PWR_SRC

12

12

12

PC517

PC517

PC515

PC515

PC516

PC516

@

@

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

PC504

PC504

1 2

CORE_BOOT_C

0.1U_0402_25V6

0.1U_0402_25V6

1 2

PR517

PR517

2.2_0603_5%

2.2_0603_5%

CSD97374CQ4M_SON8_3P5X4P5

CSD97374CQ4M_SON8_3P5X4P5

CPU 15W
TDC 10 A
Peak Current 32 A
OCP Current 38.4 A
DC Load line -2.0 mV/A
Choke DCR: 0.66m +-7% ohm
Icc_Dyn_VID1 27 A
PH500 B value: 4250k 1%
PH501 B value: 3370k 1%

12

PC518

PC518

@

@

10U_0805_25V6K

10U_0805_25V6K

9
8
7

CORE_BOOT

6

CORE_BOOT_R

5

2

PC508

PC508

680P_0603_50V7K

680P_0603_50V7K

EMC12UnonD@

EMC12UnonD@

1

+

+

PC519

PC519

2

100U_D_20VM_R55M

100U_D_20VM_R55M

PU501

PU501

PGND2
PWM

VSW

BOOT

PGND1

VDD

BOOT_R

SKIP#

VIN

1U_0603_10V7K

1U_0603_10V7K

12

@EMC@

@EMC@

PC520

PC520

2200P_0402_50V7K

2200P_0402_50V7K

4
3
2
1

SKIP#1

PC509

PC509

PC520

PC520

2200P_0402_50V7K

2200P_0402_50V7K

EMC12UnonD@

EMC12UnonD@

CORE_SW

1 2

SKIP#

PR520

PR520

0_0402_5%

0_0402_5%

12

+5V_RUN

12

PR522

PR522

CORE_SNUB

12

@EMC@

@EMC@

PC508

PC508

@EMC@

@EMC@

PR512

PR512

2.15K_0402_1%

2.15K_0402_1%

1 2

4.7_1206_5%

4.7_1206_5%

680P_0603_50V7K

680P_0603_50V7K

1

PL500

PL500

0.15UH_ETQP4LR15AFM_29A_20%

0.15UH_ETQP4LR15AFM_29A_20%

PR514

PR514

1

4

3

2

CORE_SW_CSP

12

PH501

PH501

12

12

PR515

PR515

10K +-1% 0402 B25/50 3370K

20K_0402_1%

20K_0402_1%

10K +-1% 0402 B25/50 3370K

3.01K_0402_1%

3.01K_0402_1%

12

PC502

PC502

0.068U_0402_16V7K

0.068U_0402_16V7K

+VCC_CORE

CSP1

PC513

PC513

12

0.068U_0402_16V7K

0.068U_0402_16V7K

CSN1

DELL CONFIDENTIAL/PROPRIETARY

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

+VCC_CORE

+VCC_CORE

+VCC_CORE

LA-A902P

LA-A902P

LA-A902P

45 47Monday, March 17, 2014

45 47Monday, March 17, 2014

45 47Monday, March 17, 2014

1

0.1

0.1

0.1

A

SIS496EDNT-T1-GE3 1N POWERPAK1 212-8

SIS496EDNT-T1-GE3 1N POWERPAK1 212-8
PQ709

PQ709

+DC_IN

1 1

CHARGER_SMBCLK
CHARGER_SMBDAT
pull up 10K in HW side (R82 7 R828)

2 2

3 3

12

ACAV_IN<36,46>

PC731

PC731

0.022U_0603_50V7K

0.022U_0603_50V7K

100K_0402_1 %

100K_0402_1 %

154K_0402_1 %

154K_0402_1 %

4

12

PR737

PR737

4.7_0402_1%

4.7_0402_1%

DCX124EK-7-F_SC7 4R-6

DCX124EK-7-F_SC7 4R-6

PQ708A

@PQ708A

@

BQ24770_REGN

12

PR713

PR713

12

PR715

PR715

GNDA_CHG

PR725

PR725

1K_0402_1%

1K_0402_1%

PR729

@PR729

@

154K_0402_1 %

154K_0402_1 %

PQ710

PQ710
SI7716ADN-T1-GE3_POWERP AK8-5

SI7716ADN-T1-GE3_POWERP AK8-5

1

1

+DC_IN_SS

2

2

35

3 5

4

12

PC730

PC730

0.1U_0402_25V6

0.1U_0402_25V6

@

@

PQ708B

PQ708B

2

DCX124EK-7-F_SC74R-6

DCX124EK-7-F_SC74R-6

4 3

AC_DIS <36>

5

PQ711

PQ711

G

G

12

2

DMN65D8LW-7_SOT323 -3

DMN65D8LW-7_SOT323 -3

13

D

S

D

S

PR709

PR709

1M_0402_1%

1M_0402_1%

PR711

PR711

49.9K_0402_ 1%

49.9K_0402_ 1%

12

PC711

PC711

12

0.1U_0402_25V6

0.1U_0402_25V6

GNDA_CHG

@

@

PT1

PT1

CHARGER_SMBDAT<36>

CHARGER_SMBCLK<36>

@

@

PR716 0 _0402_5%PR7 16 0_0 402_5%

1 2

PR718 0 _0402_5%PR7 18 0_0 402_5%

1 2

PR720 0 _0402_5%PR7 20 0_0 402_5%

1 2

PC718

PC718

100P_0402_50V8J

100P_0402_50V8J

GNDA_CHG

PR728 0 _0402_5%PR728 0_0 402_5%

1 2

Maximum charging current is 7.2A

GNDA_CHG

16

BQ24770_REGN

12

12

AC Det
Max:16.82V
Typ :16.54V
Min :16.26V

I_ADP<36>

I_BATT<36>

I_SYS<36>

H_PROCHOT#<9,36 ,45,46>

PBAT_PRES#<36,40>

12

PR731

PR731

4.02K_0402_1%

4.02K_0402_1%

+DC_IN

PR710

PR710

294K_0402_1%

294K_0402_1%

1 2

PAD~D

PAD~D

PT2

PT2

PAD~D

PAD~D

PC719

PC719

1 2

1 2

100P_0402_50V8J

100P_0402_50V8J

+PBATT

SDMK0340L-7-F_SOD 323-2~D

SDMK0340L-7-F_SOD 323-2~D

+DC_IN

SDMK0340L-7-F_SOD 323-2~D

SDMK0340L-7-F_SOD 323-2~D

12

PR730

PR730

4.02K_0402_ 1%

4.02K_0402_ 1%

PR714

PR714

PR788

PR788

1 2

20K_0402_1%

20K_0402_1%

B

PD704

PD704

PD705

PD705

10_1206_5%

10_1206_5%

1U_0805_25V6K

1U_0805_25V6K

1 2

+SDC_IN

12

12

PR708

PR708

PC709

PC709

12

0_0402_5%

0_0402_5%

PR717 0 _0402_5%PR7 17 0_0 402_5%

1 2

12

+DCIN

PR704

PR704
0_0402_5%

0_0402_5%

1 2

PC701

PC701

1U_0603_25V6K

1U_0603_25V6K

1 2

GNDA_CHG

PU700

PU700

28

VCC

3

CMSRC

6

ACDET

11

SDA

12

SCL

5

ACOK

7

IADP

8

IDCHG

9

PMON

10

/PROCHOT

13

CMPIN

14

CMPOUT

15

/BATPRES

16

CELL

29

PWPD

BQ24777RUYR WQFN 28 P CHARGER

BQ24777RUYR WQFN 28 P CHARGER

GNDA_CHG

GNDA_CHG

PR701

PR701

0.01_1206_1 %

0.01_1206_1 %

342

CSSP_1

PR703

PR703

1 2

100_0402_1 %

100_0402_1 %

PC702

PC702

0.1U_0402_25V6

0.1U_0402_25V6

1 2

4

2

ACP

ACDRV

PJP701

PJP701

1 2

PAD-OPEN1x1m

PAD-OPEN1x1m

EMC@

EMC@

1UH_PCMB042T-1R0MS_4.5A_20 %

1UH_PCMB042T-1R0MS_4.5A_20 %

+PWR_SRC_AC CHAGER_SRC

1

@

@

0.1U_0402_25V6

0.1U_0402_25V6

1

ACN

REGN

BTST

HIDRV

PHASE

LODRV

GND

NC

SRP

SRN

/BATDRV

BAT

CSSN_1

1 2

PC703

PC703

PR705

PR705
0_0402_5%

0_0402_5%

1 2

24

25

26

27

23

22

21

10K_0402_1%

10K_0402_1%

20

19

18

17

PC729

PC729

1U_0603_25V6K

1U_0603_25V6K

2.2_0603_5%

2.2_0603_5%

1 2

CHG_UGATE

CHG_SW

CHG_LGATE

PR799

PR799

1 2

1 2

PR723

PR723

10_0603_1%

10_0603_1%

1 2

GNDA_CHG

GNDA_CHG

BQ24770_REGN

PR712

PR712

BQ24770_REGN

PR722

PR722

4.02K_0402_ 1%

4.02K_0402_ 1%

1 2

+PBATT

CHG_BTS_CCHG_BTS

PAD-OPEN 1x2m~D

PAD-OPEN 1x2m~D

12

PC712

PC712

0.047U_0603_25V7K~D

0.047U_0603_25V7K~D

PJP700

PJP700

PL700

PL700

C

PC710

PC710

1 2

1U_0603_10V6K

1U_0603_10V6K

D

12

PC713

PC713

PR726

PR726

PC721

4.7_1206_5%

4.7_1206_5%

EMC12UnonD@

EMC12UnonD@

12

PC705

PC705

10U_0805_25V6K

10U_0805_25V6K

+VCHGR

@EMC@PC722

@EMC@

PC722

PC728

PC728

@

@

1 2

GNDA_CHG

1000P_0603_50V7K

1000P_0603_50V7K

Near PL701

+PWR_SRC

12

PC706

PC706

@

@

10U_0805_25V6K

10U_0805_25V6K

22U_0805_25V6M

22U_0805_25V6M

12

PC723

PC723

10U_0805_25V6K

10U_0805_25V6K

0.1U_0603_25V7K

0.1U_0603_25V7K

PC721

EMC12UnonD@

EMC12UnonD@

12

PC707

@ PC707

@

12

PC724

PC724

12

12

PC708

PC708

@

@

22U_0805_25V6M

22U_0805_25V6M

22U_0805_25V6M

22U_0805_25V6M

12

12

PC725

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

@ PC725

@

21

2200P_0402_50V7K

2200P_0402_50V7K

EMC12UnonD@

EMC12UnonD@

12

PC714

PC714

22U_0805_25V6M

22U_0805_25V6M

0.1U_0402_25V6

0.1U_0402_25V6

12

PC715

PC715

PC726

PC726

1 2

22U_0805_25V6M

22U_0805_25V6M

12

PC716

PC716

22U_0805_25V6M

22U_0805_25V6M

+PWR_SRC

12

12

PC717

PC717

22U_0805_25V6M

22U_0805_25V6M

PR721

PR721

0.01_1206_1 %

0.01_1206_1 %

342

0.1U_0402_25V6

0.1U_0402_25V6

1 2

PC704

PC704

1

PC727

PC727

0.1U_0402_25V6

0.1U_0402_25V6

7

1

G1

D2/S1

5

6

2

D1

2.2UH +-20% 12A 10X10X 4 MOLDING

2.2UH +-20% 12A 10X10X 4 MOLDING

PQ704

PQ704

S24S2

S23G2

PC721

@EMC@PC7 21

@EMC@

1000P_0603_ 50V7K

1000P_0603_ 50V7K

BATDRV#

12

PC713

2200P_0402_50V7K

2200P_0402_50V7K

@EMC@ PC713

@EMC@

PL701

PL701

PR726

PR726

4.7_1206_5%

4.7_1206_5%

@EMC@

@EMC@

1 2

CHG_SNUB

AON6970_DFN5X6D-8-7

AON6970_DFN5X6D-8-7

12

GNDA_CHG

PD703

PD703

PDS5100H-13_POW ERDI5-3

PDS5100H-13_POW ERDI5-3

3

1

+VCHGR

4 4

SI4835DDY-T1-E3_SO8

SI4835DDY-T1-E3_SO8

1
2
3 6

BATDRV#

2

PQ701

PQ701

8
7

5

4

+PBATT

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Charger

Charger

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR D ISCLOSED TO ANY THIRD PA RTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

C

Charger

Size Doc ument Number Rev

Size Doc ument Number Rev

Size Doc ument Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

LA-A902P

LA-A902P

LA-A902P

D

46 47Mo nday, March 17, 2014

46 47Mo nday, March 17, 2014

46 47Mo nday, March 17, 2014

0.1

0.1

0.1

5

4

3

2

1

+VCC_CORE

D D

1

PC900

PC900
22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

PC901

PC901
22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

PC902

PC902
22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

PC903

PC903
22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

PC904

PC904
22U_0805_6.3V6M

22U_0805_6.3V6M

2

Based on _RF Cheng. Hill



(11257) for PT 20131107

962

1

PC913

PC913
22U_0805_6.3V6M

22U_0805_6.3V6M

2

C C

B B

1

PC914

PC914
22U_0805_6.3V6M

22U_0805_6.3V6M

2

220U 2.5V Y D2 ESR9M H 1.9 SX

220U 2.5V Y D2 ESR9M H 1.9 SX

1

PC966

PC966

+

+

2

1

PC915

PC915

2.2U_0805_10V6K

2.2U_0805_10V6K

2

1

PC916

PC916

2.2U_0805_10V6K

2.2U_0805_10V6K

2

1

@

@

PC917

PC917
22U_0805_6.3V6M

22U_0805_6.3V6M

2

PC105

PC105

2200P_0402_50V7K

2200P_0402_50V7K

EMC14UnonD@

EMC14UnonD@

PC203

PC203

2200P_0402_50V7K

2200P_0402_50V7K

EMC14UnonD@

EMC14UnonD@

PC300

PC300

2200P_0402_50V7K

2200P_0402_50V7K

EMC14UnonD@

EMC14UnonD@

PR522

PR522

4.7_1206_5%

4.7_1206_5%

EMC14UnonD@

EMC14UnonD@

PC520

PC520

2200P_0402_50V7K

2200P_0402_50V7K

EMC14UnonD@

EMC14UnonD@

PC713

PC713

2200P_0402_50V7K

2200P_0402_50V7K

EMC14UnonD@

EMC14UnonD@

PR726

PR726

PC106

PC106

@

@

0.1U_0402_25V6

0.1U_0402_25V6

PC206@

PC206@

0.1U_0402_25V6

0.1U_0402_25V6

PC311

PC311

@

@

0.1U_0402_25V6

0.1U_0402_25V6

PC508

PC508

680P_0603_50V7K

680P_0603_50V7K

EMC14UnonD@

EMC14UnonD@

@

@

PC521

PC521

0.1U_0402_25V6

0.1U_0402_25V6

@

@

PC732

PC732

0.1U_0402_25V6

0.1U_0402_25V6

PC721

PC721

680P_0603_50V7K

4.7_1206_5%

4.7_1206_5%

EMC14UnonD@

EMC14UnonD@

A A

680P_0603_50V7K

EMC14UnonD@

EMC14UnonD@

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROCESSOR DECOUPLING

PROCESSOR DECOUPLING

PROCESSOR DECOUPLING

LA-A902P

LA-A902P

LA-A902P

47 47Monday, March 17, 2014

47 47Monday, March 17, 2014

47 47Monday, March 17, 2014

1

0.1

0.1

0.1

5

4

3

2

1

Version Change List ( P. I. R. List )

Item Issue DescriptionDate

D D

47 VCC_CORE 10/8 Compal

2 X01

42 1.35V_MEN 10/8 RICHTEK T o prevent IC damage Add PR204

3 X01

46 Charger 10/8 Compal Fine tune divider voltage Change PR715, PR729 to 154k

4

41,43,44

C C

5 X01

6

7

8

9

B B

10 Charger 3/03 Compal46 To set OVP level Remove PR729 X02

11 Charger 3/03 Compal46 To set IC function Remove PC720 Add PR788, PR799 X02

12 DCIN 3/03 Compal40 For ME change request Change PBATT1 X02

13 DCIN 3/03 Compal40 For EMC change request Add PD5 PC20 PC21 PC22 Remove PC11 X02

+1.05V_M
+1.5V_RUN
+3V/+5V

45 VCC_CORE 10/31 Compal Fine tune IMON

Charger 12/05 Compal

Request
Owner

To prevent acoustic noise issue

10/22 Compal To improve the ability of anti-noise

Has the same behavior with dock circuit Add PQ71146 Charger 12/05 Compal

To add 2nd source Remove PQ702 Add PQ709, PQ71046 Charger 12/05

Compal

To reduce leakage current Remove PD701 Add PD704, PD70546 X01

Solution Description Rev.Page# Title

Remove PC923, PC924, PC925, PC926, PC927, PC928, PC929, PC930, PC931,
PC940, PC941, PC943, PC946, PC947, PC948
Add PC966

Change PR307 to 7.5k
Change PR310, PR102, PR104, PR403 to 10k
Change PR100 to 6.49k
Change PR101 to 15k
Change PR402 to 8.66k

Add PR518, PR524, PR525

Pop PR522,PC508, PR726, PC721, PC713, PL501, PC520ALL ALL 10/31 Compal RF request

X011

X01

X01

X01

X01

A A

DELL CONFIDENT IAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

PWR P.I.R (1/1)

PWR P.I.R (1/1)

PWR P.I.R (1/1)

LA-A902P

LA-A902P

LA-A902P

1

48 48Monday, March 17, 2014

48 48Monday, March 17, 2014

48 48Monday, March 17, 2014

0.1

0.1

0.1

5

4

3

2

1

Version Change List ( P. I. R. List )

TitlePage# Rev.Solution Description

D D

2

27

3

36

HW 2013/10/81 COMPAL 0.2(X01)

6 Follow intel reference circuit. Add CC100, RC300 on CPU pin AC4, net name is PM_TEST_RST

HW

HW

Date Issue DescriptionItem

2013/10/8

2013/10/8

Request
Owner

COMPAL

COMPAL

Dell drop POA function.

Dell drop POA function.

Change JUSH1 from 26 pin to 20 pin, pin define follow E5

remove POA_WAKE# off page symbol
remove POA_ON/OFF#,make UE2.B62 to be NC pin

0.2(X01)

0.2(X01)

4

C C

5

2013/10/9 COMPAL24 HW correct HDMI schematic error. swap HDMI LANE0 & LANE2 BUS

6

7

8

9

24

36

10 2013/10/14 COMPAL follow intel latest design guide.

B B

11

2013/10/9

HW

HW COMPAL RF requirement. add CC14, CC15 and move CC12, CC13 to behind the resistor (RC72)7 2013/10/16 0.2(X01)

HW COMPAL

2013/10/1720,23,31,32 follow ESD recommend list.12

COMPAL2013/10/9HW22

Follow EMC suggestion

COMPAL2013/10/9HW23

reserved for S3 within 2s , system shutdown

COMPAL2013/10/9HW9

issue debug.

board ID change. RE79 change to 130KCOMPAL2013/10/9HW36

COMPALHW

SATA ciruit issue Swap mSATA P & N

Change LI1,LI2,LI3,LI4,LI5,LI6,LI7,LI8,LI9,LV3,LV6,LV10,LV12,LV27
From SM070003K00 (S COM FI_ CHILISIN CMMI21T-900Y-N)
To SM070003Y00 (S COM FI_ MURATA DLW21HN900HQ2L)

add RC26, reserved RC27.

pop RE56 and change from 8.2K to 10K , it's RESET_OUT# pull down
resistor

change all ESD diode CPN
change DI2, DI3, DI5, DV4 from SCA00001100(S ZEN ROW PJDLC05C 3P C/A
SOT23) to SC600001600(S DIO ROW AZC199-02S.R7G C/C SOT23 ESD)
change DI1,DI6,DI4 from SC300002800(S DIO(BR) TVWDF1004AD0 DFN ESD)
to SC300002C00(S DIO(BR) L05ESDL5V0NA-4 SLP2510P8 ESD)
change DA1,DA2,DA3,DA6,DA7 from SCA00001L00(S ZEN ROW L30ESDL5V0C3-2
C/A SOT23 ESD) to SCA00002900(S ZEN ROW L03ESDL5V0CC3-2 C/A SOT-23
ESD)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)power doesn't split VPRO & NPRO BOM. add RZ41, RZ42, reserve it for VPRO & NVPRO option.2013/10/17 COMPALHW3813

A A

0.2(X01)SSI design will cause LED behavior error. QL1 Pin2,5 & QL2 Pin2 change from MASK_BASE_LEDS# to SYS_LED_MASK#2013/10/17 COMPALHW3914

DELL CONFIDENT IAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

EE P.I.R (1/3)

EE P.I.R (1/3)

EE P.I.R (1/3)

LA-A972P

LA-A972P

LA-A972P

60 70Monday, March 17, 2014

60 70Monday, March 17, 2014

60 70Monday, March 17, 2014

1

0.3

0.3

0.3

5

4

3

2

1

Version Change List ( P. I. R. List )

TitlePage# Rev.Solution Description

D D

15

16

17

20

28, 36, 38

HW

HW

HW COMPAL 0.2(X01)2013/10/2412

Date Issue DescriptionItem

2013/10/17

2013/10/17

18

19

C C

6, 7, 22,

20

28

HW 0.2(X01)

21

22

23

HW 2013/10/29 COMPAL 0.2(X01)30

2013/10/29 COMPAL To solve backdrive issue. Change TPM_ PIRQ# pull up ( RC247) to +3.3V_RUN from +3.3V_ALW_PCH 0.2(X01)12 HW

24

25

26

B B

2013/11/2 0.2(X01)7

2013/11/2

27

Request
Owner

COMPAL

COMPAL

COMPAL 0.2(X01)HW EMC request. Add RA42, RA43.21

To solve Line-on HDD dirty shut down issue.

follow Dell requirement.

debug usage. add RC301COMPAL 0.2(X01)2013/10/246 HW

reserve it to prevent PCH_PLTRST# floating
when power on

follow xtal vender suggest 2013/10/23 COMPAL

it's designed for E5 Goliad, E6 GMLK doesn't
need.

SMBUS Pull High Add RN3&RN4 pull high to +3.3V_RUN for DDR_XDP_WAN_SMBDAT/SMBCLKHW COMPAL

follow vender suggestion. It's for 15KV
ESD fail issue.

GPIO 14 is sus power well, it has risk to
cause back drive.

UZ8 Pin2 change from +3.3V_ALW to 3.3V_RUN

Add back SUS_ON, change control pin from SUS_ON to SIO_SLP_S4#

1. UZ8.3 from SIO_SLP_S4# to SUS_ON

2. UE2.B23 → SUS_ON_EC , RPE10.2 → SUS_ON

3. add RE282, RE281, RE280, RE279

4. UE2.B9 → RUN_ON_EC

add RC304, 100K pull down, on PCH_PLTRST#_EC 0.2(X01)9 HW 2013/10/28 COMPAL

1 CC1 &CC2 change from 18PF to 3PF
2 CC8 & CC11 change from 18PF to 15PF
3 CL13 & CL14 change from 33PF to 27PF
4 RV81 change from 0 ohm to 2.2K & CV113 change to 18PF

remove RZ1COMPAL 0.2(X01)HW 2013/10/2923

add CA12, CA13
change DA1, DA2, DA3, DA4 from GNDA to GND

0.2(X01)

0.2(X01)

0.2(X01)add PJP36, depop QZ6, QZ10, RZ16, RZ5, CZ25, CZ38Dell doesn't support MODPHY.COMPAL2013/10/30HW30

0.2(X01)COMPAL2013/11/05HW21

0.2(X01)move TPM_PIRQ# from PCH_GPIO14 to PCH_GPIO17, add T21 on PCH_GPIO14COMPAL2013/11/05HW1228

0.3(X01)HW21 COMPAL2013/12/1739

0.3(X01)22 COMPALHW 2013/12/1740

A A

DELL CONFIDENT IAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

EE P.I.R (2/3)

EE P.I.R (2/3)

EE P.I.R (2/3)

LA-A972P

LA-A972P

LA-A972P

61 70Monday, March 17, 2014

61 70Monday, March 17, 2014

61 70Monday, March 17, 2014

1

0.3

0.3

0.3

5

4

3

2

1

Version Change List ( P. I. R. List )

TitlePage# Rev.Solution Description

D D

29

30

Date Issue DescriptionItem

2013/12/17

2013/12/17

Request
Owner

0.3(X01)22 COMPALHW

Base on Pre-PT RSMRST EA result22 COMPALHW

2. remove QZ12,RZ48,RZ49,RZ50

0.3(X01)1.POP RE88,UZ6,RE51

31

22

COMPALHW 2013/12/17

0.3(X01)

Intel recommendCOMPAL2013/12/27HW32 0.3(X01)Change RC33, RC34 from 1k to 499 ohm7

C C

B B

A A

DELL CONFIDENT IAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

EE P.I.R (3/3)

EE P.I.R (3/3)

EE P.I.R (3/3)

LA-A971P

LA-A971P

LA-A971P

62 70Monday, March 17, 2014

62 70Monday, March 17, 2014

62 70Monday, March 17, 2014

1

0.3

0.3

0.3