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Vinafix.com
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COMPAL CONFIDENTIAL
B
C
D
E
1 1
PCB NO :
BOM P/N :
LA-A961P
4319RL31L01
MODEL NAME :
ZBU10
GPIO MAP: 3.6C
2 2
Goliad MLK 14" UMA
Broadwell U
2014-10-07
REV : 1.0(A00)
@ : Nopop Component
EMC@ : EMI, ESD and RF Component
@EMC@ : EMI, ESD and RF Nopop Component
3 3
CXDP@ : XDP Component
CONN@ : Connector Component
VPRO@ : VPRO Component
Layout Dell logo
NVPRO@ : NVPRO Component
COPYRIGHT 2014
ALL RIGHT RESERVED
REV: X02
PWB: 407FT
4 4
MB PCB
@
Part Number
DAA00084000
Description
PCB 0VN LA-A961P REV0 UMA MB WITH DOCKING
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
B
C
D
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Cover Sheet
Cover Sheet
Cover Sheet
LA-A961P
LA-A961P
LA-A961P
1 53Tuesday, October 07, 2014
1 53Tuesday, October 07, 2014
1 53Tuesday, October 07, 2014
E
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1.0
1.0
Page 2
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B
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Reverse Type
Goliad MLK 14 UMA Block Diagram
Memory BUS (DDR3L)
1 1
eDP CONN
PAGE 23
Dual Lane eDP1.3
INTEL
PAGE 25
USB2.0[2]
DDI2
DDI1
SMSC SIO
PCIE1
ECE5048
PAGE 35
BC BUS
BROADWELL ULT
PAGE 6~17
SPI
LPC
SMSC KBC
USB
HD Audio I/F
SATA1
TAA option
W25Q64CVSSIQ
64M 4K sector
W25Q32BVSSIQ
32M 4K sector
Discrete TPM
AT97SC3205
KB/TP CONN
PAGE 37
mDP CONN
PAGE 24
will change to VMM 2330
DOCKING
CONN
2 2
3 3
PAGE 34
DOCK_USB2.0[0]
DOCK_USB2.0[3]
DOCK_USB3.0[1]
VGA
DP
DP
DAI
LAN
SATA0
IDT
VMM2320
HDMI CONN
SD4.0
PAGE 29 PAGE 29
PCIE3 PCIE4
Intel Clarkville
I218LM
PAGE 28
Transformer
PAGE 28
PAGE 22
PAGE 24
PCIE6_L0
WWAN/LTE
Parade
PS8338
DP
PAGE 26
WIGIG_DP
Card reader
O2 Micro OZ777FJ2LN
PCIE6_L1
PAGE 30
USB2.0[7]
Parade
PS8339
DP
HDMI
PCI Express BUS
PCIE5_L0
WLAN/BT/
WIGIG
PAGE 30
WIGIG_DP
1333/1600MHz
DOCKED_LIO_EN
USB2.0[3]
DOCKED
USB2.0[0]
USB3.0[1]
PAGE 7
PAGE 27
NX3DV221
USB20 Switch
PAGE 31
PI3USB3102
USB3&2 Switch
PAGE 31
USB2.0[1]
USB3.0[2]
SATA3 CONN
DDR3L-DIMM X2
BANK 0, 1, 2, 3
DOCK _USB2.0[3]
SW_USB2.0[0]
SW_USB3.0[1]
HDA Codec
ALC3235
PAGE 20
PAGE 21
PAGE 18 19
USB2.0[4]
USB2.0[5]
SW_USB2.0[3]
USB3.0[4]
TPS2544
USB POWER SHARE
DOCK _USB2.0[0]
DOCK_USB3.0[1]
INT.Speaker
Universal Jack
PAGE 21
PAGE 21
Dig. MIC
Trough eDP Cable
LCD Touch
PAGE 23
Camera
PAGE 23
USB3.0/2.0
USB2.0[0]_PS
PAGE 31
USB3.0/2.0+PS
USB3.0/2.0
IO/B
Trough eDP Cable
LID switch
USH CONN
CPU XDP Port
Automatic Power
Switch (APS)
PAGE 31
IO/B
IO/B
PAGE 27
PAGE 9
PAGE 9
MEC5085
RJ45
PAGE 28
4 4
Smart Card
TDA8034HN
USH
PAGE 36
FAN CONN
PAGE 36
Near Field
PAGE 33
Communications con
Free Fall sensor
DC/DC Interface
Power On/Off
SW & LED
PAGE 20
PAGE 38
IO/B
PAGE 32,39
BCM5882
RFID
Fingerprint
CONN
A
FP_USB
PAGE 27
USB2.0[6]
USH board
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
B
C
D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Block diagram
Block diagram
Block diagram
LA-A961P
LA-A961P
LA-A961P
2 53Tuesday, October 07, 2014
2 53Tuesday, October 07, 2014
2 53Tuesday, October 07, 2014
E
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1
POWER STATES
State
D D
S0 (Full ON) / M0
S3 (Suspend to RAM) / M3 LOW HIGH HIGH ON ON ON OFF
S4 (Suspend to DISK) / M3 ON ON OFF
S5 (SOFT OFF) / M3 ON ON OFFLOW HIGHLOW
S3 (Suspend to RAM) / M-OFF
S4 (Suspend to DISK) / M-OFF HIGH
S5 (SOFT OFF) / M-OFF
Signal
SLP
S3#
HIGH
LOW HIGH HIGH
LOW HIGH HIGH LOW ON ONOFF OFF OFF
LOW LOW LOW ON OFF OFF OFF OFF
LOW LOW LOW LOW ON OFF OFF OFF OFF
SLP
SLP
S5#
S4#
HIGH HIGH
LOW
LOW
SLP
A#
HIGH
HIGH
ALWAYS
PLANE
ON
M
PLANE
ON
SUS
RUN
PLANE
PLANE
ON ON ON
OFF
OFF
CLOCKS
OFF
OFF
OFF
PCIE
PCIE 1
PCIE 2
PCIE 3
PCIE 4
PCIE 5
PCIE 6
USB3.0
USB3.0 1
USB3.0 2
USB3.0 3
USB3.0 4
SATA
SATA 3
DESTINATION
JUSB1-->Rear left
JUSB3-->Right
MMI (CARD READER)
JUSB2-->Rear Right
LOM
WLAN - JNGFF1
WiGig - JNGFF1
HCA & SATA Cache - JNGFF2
C C
PM TABLE
power
plane
+3.3V_ALW
+3.3V_ALW_PCH
+3.3V_RTC_LDO
+3.3V_SUS+5V_ALW +5V_RUN
+1.35V_MEM
+0.675V_DDR_VTT
+1.05V_RUN
+VCC_CORE
+3.3V_M +3.3V_M
+1.05V_M+3.3V_RUN
+1.05V_M
(M-OFF)
USB PORT#
State
0
1
S0
B B
S3
S5 S4/AC
S5 S4/AC doesn't exist
ON
ON
ON ON
ON
OFF
OFFOFF
OFFON
OFF
OFF
ON
ON
ON
ON
OFF
OFF
OFFOFF
BDW
ULT
2
3
4
5
6
7
0
SATA 2
JSATA1SATA 1
SATA 0
JDOCK1
DESTINATION
JUSB1 or DOCK1
JUSB3
WLAN + BT
JUSB2 or DOCK2
Touch Screen
CAMERA
USH
WWAN
BIO
SATA Cache - JNGFF2
USH
A A
1
NA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Port assignment
Port assignment
Port assignment
LA-A961P
LA-A961P
LA-A961P
3 53Tuesday, October 07, 2014
3 53Tuesday, October 07, 2014
3 53Tuesday, October 07, 2014
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1
RUN_ON
D D
ADAPTER
EN_INVPWR
FDC654P
(QV1)
+BL_PWR_SRC
PCH_ALW_ON
TPS22966
(UZ7)
DOCKED
TPS22966
(UV13)
MPHYP_PWR_EN
SI3456
(QZ6)
+1.05V_MODPHY
A_ON
SY8208
(PU300)
+1.05V_M
+3.3V_ALW_PCH+1.05V_RUN
BATTERY +PWR_SRC
ALWON
C C
+1.05V_RUN_VMM
+3.3V_RUN_VMM
TPS51285
(PU100)
+5V_ALW
CHARGER
+3.3V_ALW
USB_PWR_SHR_EN#
3.3V_HDD_EN
ISL95813
(PU501)
B B
H_VR_EN
+VCC_CORE
SUS_ON
+1.35V_MEM
RT8207
(PU200)
0.675V_DDR_VTT_ON
+3.3V_M
SUS_ON
A_ON
TPS22966
(UZ8) (UZ9)
+3.3V_WLAN
AUX_EN_WOWL
TPS22966
(UZ2)
3.3V_WWAN_EN
SIO_SLP_LAN#
TPS22966
(UL3)
+3.3V_LAN
EN_LCDPWR
APL3512
(UV24)
+LCDVDD
+3.3V_RUN
RUN_ON
RUN_ON
TPS22966
+5V_RUN
TPS2544
(UI3)
+5V_USB_CHG_PWR
USB_PWR_EN1#
G547I2P81U
(U2)
+USB_RIGHT_PWR +USB_RIGHT_PWR
USB_PWR_EN2#
G547I2P81U
(UI2)
I/O Borad
+0.675V_DDR_VTT
A A
5
+3.3V_SUS
+3.3V_WWAN
4
+3.3V_HDD
+3.3V_CAM
3.3V_CAM_EN#
LP2301ALT1G
(QZ1)
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Power rails
Power rails
Power rails
LA-A961P
LA-A961P
LA-A961P
4 53Tuesday, October 07, 2014
4 53Tuesday, October 07, 2014
4 53Tuesday, October 07, 2014
1
1.0
1.0
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Vinafix.com
5
SMBUS Address [0x9a]
B4
A3
MEM_SMBCLK
MEM_SMBDATA
SML0CLK
SML0DATA
2.2K
2.2K
DOCK_SMB_CLK
DOCK_SMB_DAT
+3.3V_ALW_PCH
AP2
AH1
D D
BDW
AN1
AK1
AU3AH3
SML1_SMBDATA
SML1_SMBCLK
B6A5
3A
3A
1A
1A
1K
1K
2.2K
2.2K
4
+3.3V_ALW_PCH
2.2K
2.2K
+3.3V_ALW_PCH
+3.3V_ALW
2N7002
2N7002
3
28
31
LOM
2
202
200
202
200
53
51
DIMMA
DIMMB
XDP
1
10K
10K
4
6
+3.3V_RUN
G Sensor
C C
B5
A4
LCD_SMBCLK
LCD_SMDATA
1B
1B
2.2K
2.2K
+3.3V_ALW
2.2K
KBC
A56
1C1CB59
PBAT_SMBCLK
2.2K
PBAT_SMBDAT
+3.3V_ALW
100 ohm
100 ohm
7
6
BATTERY
CONN
2.2K
A50
B53
USH_SMBCLK
USH_SMBDAT
2.2K
B B
MEC 5085
1E
1E
2.2K
2.2K
A49
B52
CARD_SMBCLK
CARD_SMBDAT
2B
2B
10K
B50
A47
CHARGER_SMBCLK
CHARGER_SMBDAT
1G
1G
10K
2.2K
2.2K
B7
A7
BAY_SMBDAT
BAY_SMBCLK
A A
2D
2D
2.2K
2.2K
B48
2A
2A
5
GPU_SMBDAT
GPU_SMBCLK
B49
4
+3.3V_SUS
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
M9
L9
USH
9
8
Charger
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
SMbus Block diagram
SMbus Block diagram
SMbus Block diagram
LA-A961P
LA-A961P
LA-A961P
5 53Tuesday, October 07, 2014
5 53Tuesday, October 07, 2014
5 53Tuesday, October 07, 2014
1
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UMA SATA port
Service Mode Switch:
D D
+RTC_CELL
330K_0402_5%
12
RC1
Add a switch to ME_FWP signal to unlock the ME region and
allow the entire region of the SPI flash to be updated using FPT.
+3.3V_ALW_PCH
12
RC2
1K_0402_5%
ME_FWP_EC<36>
1 2
RC301@ 0_0402_5%
PT,ST pop RC2 and SW1 : MP pop RC301
ME_FWPME_FWP_EC
ME_FWP
@
SW1
1
1
2
2
3
3
SS3-CMFTQR9_3P
5
G2
4
G1
SATA0
E-Dock
mSATA
mSATA
E-Dock
mSATA
E-Dock
NANAmSATA
HDD
HDD
PCB
G12 UMA
G12 EntryNA
G14 DSC
G14 UMA
G14D_En
G14U_En
SATA2/PCIE6 L1SATA1
M2 3042
2nd PCIe Lane for PCIe Cache
NA NA
M2 3042
SATA-Cache(no HCA)
M2 3042
2nd PCIe Lane for PCIe Cache
NA
NA
SATA3/PCIE6 L0
M2 3042
(HCA & SATA-Cache)
M2 3030 WIGIG
M2 3042
(HCA & SATA-Cache)
M2 3030 WIGIG
NA
contact to WWAN
SATA2/PCIE6_L1 contact to WWAN
SATA3/PCIE6 L0 contact to WLAN
contact to WWAN
contact to WLAN
ME_FWP PCH has internal 20K PD.
PCH_INTVRMEN
INTVRMEN - INTEGRATED SUS 1.05V VRM
ENABLE
C C
High - Enable Internal VRs
Low - Enable External VRs
1 2
RC9 1M_0402_5%
+RTC_CELL
1 2
CC3
ME_CLR1
B B
Shunt Clear ME RTC Registers
Open
+1.05V_M
1U_0402_6.3V6K
TPM setting
Keep ME RTC Registers
RPC21
1 8
2 7
3 6
4 5
51_0804_8P4R_5%
RC18@ 1K_0402_1%
@
RC21
1 2
1 2
RC10 20K_0402_5%
RC8 20K_0402_5%
SRTCRST#
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
12
PCH_JTAG_JTAGX
12
PCH_JTAG_TCK
51_0402_5%
HDA for Codec
PCH_AZ_CODEC_SDOUT<21>
A A
PCH_AZ_CODEC_SYNC<21>
PCH_AZ_CODEC_RST#<21>
PCH_AZ_CODEC_BITCLK<21>
5
RC19 33_0402_5%
RC20 33_0402_5%
RC22 33_0402_5%
RC23 33_0402_5%
27P_0402_50V8J
@EMC@
12
CC5
Reserve for EMI
FLASH DESCRIPTOR SECURITY OVERRIDE
LOW = ENABLE (DEFAULT) -->Pin1 & Pin3 short
HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short
CC1
1 2
15P_0402_50V8J
CC2
1 2
15P_0402_50V8J
1
1
2
CMOS1@SHORT PADS~D
1 2
CC4
CMOS place near DIMM
CMOS_CLR1
1U_0402_6.3V6K
CMOS setting
Shunt Clear CMOS
Open
1 2
1 2
1 2
1 2
EMC@
PCH_AZ_SDOUT
PCH_AZ_SYNC
PCH_AZ_RST#
PCH_AZ_BITCLK
12
2
Keep CMOS
1 2
RC4@ 0_0402_5%
YC1
32.768KHZ_12.5PF_9H03220008
PCH_RTCRST#<9>
PCH_AZ_CODEC_SDIN0<21>
ME_FWP
PCH_JTAG_TRST#<9>
PCH_JTAG_TCK<9>
PCH_JTAG_TDI<9>
PCH_JTAG_TDO<9>
PCH_JTAG_TMS<9>
PCH_JTAG_JTAGX<9>
+1.05V_M
4
PCH_RTCX1PCH_RTCX1_R
10M_0402_5%
12
RC7
PCH_RTCX2
INTRUDER#
PCH_INTVRMEN
SRTCRST#
PCH_RTCRST#
PCH_AZ_BITCLK
PCH_AZ_SYNC
PCH_AZ_RST#
PCH_AZ_CODEC_SDIN0
1 2
1 2
RC300@
10K_0402_5%
PCH_AZ_SDOUT
PCH_JTAG_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PM_TEST_RST
RC11 1K_0402_5%
PM_TEST_RST
CC100
1U_0402_6.3V6K
1 2
UC1E
AW5
RTCX1
AY5
RTCX2
AU6
INTRUDER
AV7
INTVRMEN
AV6
SRTCRST
AU7
RTCRST
AW8
HDA_BCLK/I2S0_SCLK
AV11
HDA_SYNC/I2S0_SFRM
AU8
HDA_RST/I2S_MCLK
AY10
HDA_SDI0/I2S0_RXD
AU12
HDA_SDI1/I2S1_RXD
AU11
HDA_SDO/I2S0_TXD
AW10
HDA_DOCK_EN/I2S1_TXD
AV10
HDA_DOCK_RST/I2S1_SFRM
AY8
I2S1_SCLK
AU62
PCH_TRST
AE62
PCH_TCK
AD61
PCH_TDI
AE61
PCH_TDO
AD62
PCH_TMS
AL11
RSVD
AC4
RSVD
AE63
JTAGX
AV2
RSVD
BDW-ULT-DDR3L_BGA1168
5 OF 19
@
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
BDW_ULT_DDR3L
RTC
AUDIO SATA
JTAG
SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3
SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2
SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2
SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1
SATA_TN2/PETN6_L1
SATA_TP2/PETP6_L1
SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0
SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0
SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37
SATA_IREF
RSVD
RSVD
SATA_RCOMP
SATALED
2
J5
H5
B15
A15
J8
H8
A17
B17
J6
H6
B14
C15
F5
E5
C17
D17
V1
U1
V6
AC1
A12
L11
K10
C12
U3
SATA2_PCIE6_L1
SATA_COMP
SATA_ACT#
SATA_PRX_DKTX_N0_C <34>
SATA_PRX_DKTX_P0_C <34>
SATA_PTX_DKRX_N0_C <34>
SATA_PTX_DKRX_P0_C <34>
SATA_PRX_DTX_N1 <20>
SATA_PRX_DTX_P1 <20>
SATA_PTX_DRX_N1 <20>
SATA_PTX_DRX_P1 <20>
PCIE_PRX_SATATX_N6_L1 <30>
PCIE_PRX_SATATX_P6_L1 <30>
PCIE_PTX_SATARX_N6_L1 <30>
PCIE_PTX_SATARX_P6_L1 <30>
PCIE_PRX_SATATX_N6_L0 <30>
PCIE_PRX_SATATX_P6_L0 <30>
PCIE_PTX_SATARX_N6_L0 <30>
PCIE_PTX_SATARX_P6_L0 <30>
MPCIE_RST# <12>
HDD_DET# <6,20>
SATA2_PCIE6_L1 <12,35>
mCARD_PCIE#_SATA <12,36>
SATA_ACT# <39>
TOUCH_PANEL_INTR#<12,23>
HDD_FALL_INT<10,20>
PCH_GPIO87<12>
HDD_DET#<6,20>
+PCH_ASATA3PLL
for DOCK
SATA HDD
for PCIe Cache (WWAN)
for SATA-CACHE (WWAN)
RPC18
45
3
6
2
7
1
8
10K_8P4R_5%
SATA Impedance Compensation
+PCH_ASATA3PLL
SATA_COMP
CAD note:
Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.
1 2
RC173.01K_0402_1%
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (1/12)
CPU (1/12)
CPU (1/12)
LA-A961P
LA-A961P
LA-A961P
6 53Tuesday, October 07, 2014
6 53Tuesday, October 07, 2014
6 53Tuesday, October 07, 2014
1
+3.3V_RUN
1.0
1.0
1.0
Page 7
Vinafix.com
5
UC1G
AU14
AW12
AY12
AW11
AV12
AA3
Y7
Y4
AC2
AA2
AA4
Y6
AF1
BDW-ULT-DDR3L_BGA1168
7 OF 19
LAD0
LAD1
LAD2
LAD3
LFRAME
SPI_CLK
SPI_CS0
SPI_CS1
SPI_CS2
SPI_MOSI
SPI_MISO
SPI_IO2
SPI_IO3
SPI_CLK64
@EMC@
CC10
@EMC@
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#
PCH_SPI_CS2#
PCH_SPI_DO
PCH_SPI_DIN
PCH_SPI_DO2
PCH_SPI_DO3
LPC_LAD0<35,36>
LPC_LAD1<35,36>
LPC_LAD2<35,36>
LPC_LAD3<35,36>
LPC_LFRAME#<35,36>
D D
SPI_CLK32
33_0402_5%
RC61
@EMC@
1 2
33P_0402_50V8J
CC9
@EMC@
C C
1 2
PCH_SPI_CLK<27>
PCH_SPI_CS2#<27>
PCH_SPI_DO<27>
PCH_SPI_DIN<27>
33_0402_5%
RC62
1 2
33P_0402_50V8J
1 2
BDW_ULT_DDR3L
LPC
+3.3V_SPI
RC29 1K_0402_5%
RC31 1K_0402_5%
MMI --->
+3.3V_RUN
RPC6
4 5
MMICLK_REQ#
3
6
2
7
1
8
PCB
10K_8P4R_5%
PCIE1 PCIE4
SD card
B B
G12 UMA
G12 Entry NA
G14 DSC
G14 UMA
G14D_En
G14U_En
A A
SD card
SD card
SD card
SD card
DGPU_PWROK <10>
WLANCLK_REQ# <7,30>
NA LOM
NA
NA
NA
NA
NA
5
PCH_GPIO76 <12>
PCIE3PCIE2
LOM
LOM
LOM
LOM
LOM
10/100/1G LAN --->
WLAN (NGFF1)--->
WGIG (NGFF1)--->
HCA/PCIe cache (NGFF2)--->
PCIE5
WLAN
WLAN
WLAN
WLAN
WLAN
WLAN
WIGIG
WIGIGSD card
GPU
WIGIG
GPU
WIGIG
4
SMBUS
C-LINKSPI
1 2
1 2
SMBALERT/GPIO11
SML0ALERT/GPIO60
SML1ALERT/PCHHOT/GPIO73
SML1CLK/GPIO75
SML1DATA/GPIO74
SPI_PCH_DO2
SPI_PCH_DO3
PCIECLK for UMA
CLK_PCIE_MMI#<29>
CLK_PCIE_MMI<29>
MMICLK_REQ#<29>
+3.3V_RUN
CLK_PCIE_LAN#<28>
CLK_PCIE_LAN<28>
LANCLK_REQ#<12,28>
CLK_PCIE_WLAN#<30>
CLK_PCIE_WLAN<30>
WLANCLK_REQ#<7,30>
CLK_PCIE_WIGIG#<30>
CLK_PCIE_WIGIG<30>
WIGIGCLK_REQ#<12,30>
CLK_PCIE_SATA#<30>
CLK_PCIE_SATA<30>
SATACLK_REQ#<30>
+3.3V_RUN
PCIE6
M2 3042
(HCA & SATA-Cache)
WIGIG
M2 3042
(HCA & SATA-Cache)
WIGIG
NA
4
AN2
AP2
AH1
AL2
AN1
AK1
AU4
AU3
AH3
AF2
AD2
AF4
MEM_SMBCLK
MEM_SMBDATA
SML0_SMBCLK
SML0_SMBDATA
SML1_SMBCLK
SML1_SMBDATA
PCH_CL_CLK1
PCH_CL_DATA1
PCH_CL_RST1#
SMBCLK
SMBDATA
SML0CLK
SML0DATA
CL_CLK
CL_DATA
CL_RST
SOFTWARE TAA
1 8
SPI_PCH_DIN
2 7
SPI_PCH_DO
3 6
SPI_PCH_CLK
4 5
SPI_PCH_DO3
1 2
SPI_PCH_DO2 SPI_PCH_DO2_64
RC38 33_0402_5%
1 8
SPI_PCH_DO3
2 7
SPI_PCH_CLK
3 6
SPI_PCH_DO
4 5
SPI_PCH_DIN
1 2
SPI_PCH_DO2 SPI_PCH_DO2_32
RC55 33_0402_5%
MMICLK_REQ#
RC66 10K_0402_5%
1 2
LANCLK_REQ#
WLANCLK_REQ#
WIGIGCLK_REQ#
RC68 10K_0402_5%
1 2
PCI_CLK_LPC_0
PCI_CLK_LPC_1
CLK_PCI_SIO
CLK_PCI_MEC
CLK_PCI_LPDEBUG
CLK_PCI_DOCK
PCH_SMB_ALERT# <12>
PCH_GPIO73 <9>
SML1_SMBCLK <36>
SML1_SMBDATA <36>
PCH_CL_CLK1 <30>
PCH_CL_DATA1 <30>
PCH_CL_RST1# <30>
RPC11
SPI_DIN64
SPI_DO64
SPI_CLK64
SPI_PCH_DO3_64
33_0804_8P4R_5%
RPC12
SPI_PCH_DO3_32
SPI_CLK32
SPI_DO32
SPI_DIN32
33_0804_8P4R_5%
VPRO@
VPRO@
PCH_GPIO19
RC72EMC@ 22_0402_5%
1 2
1 2
RC74EMC@ 22_0402_5%
RC67EMC@ 22_0402_5%
1 2
1 2
RC70EMC@ 22_0402_5%
Reserve for EMI
3
MEM_SMBCLK
MEM_SMBDATA
SML0_SMBCLK
SML0_SMBDATA
UC1F
C43
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
U2
PCIECLKRQ0/GPIO18
B41
CLKOUT_PCIE_N1
A41
CLKOUT_PCIE_P1
Y5
PCIECLKRQ1/GPIO19
C41
CLKOUT_PCIE_N2
B42
CLKOUT_PCIE_P2
AD1
PCIECLKRQ2/GPIO20
B38
CLKOUT_PCIE_N3
C37
CLKOUT_PCIE_P3
N1
PCIECLKRQ3/GPIO21
A39
CLKOUT_PCIE_N4
B39
CLKOUT_PCIE_P4
U5
PCIECLKRQ4/GPIO22
B37
CLKOUT_PCIE_N5
A37
CLKOUT_PCIE_P5
T2
PCIECLKRQ5/GPIO23
BDW-ULT-DDR3L_BGA1168
6 OF 19
12
@EMC@12P_0402_50V8J
CC12
12
@EMC@12P_0402_50V8J
CC13
12
@EMC@12P_0402_50V8J
CC14
12
@EMC@12P_0402_50V8J
CC15
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
RC30 0_0402_5%@
RC32 0_0402_5%@
SPI_PCH_CS0#
SPI_PCH_CS1#
BDW_ULT_DDR3L
CLOCK
SIGNALS
CLK_PCI_SIO <35>
CLK_PCI_MEC <36>
CLK_PCI_LPDEBUG <36>
CLK_PCI_DOCK <34>
+3.3V_RUN
2
1
6
QC1A
5
DMN66D0LDW-7_SOT363-6
3 4
QC1B
DMN66D0LDW-7_SOT363-6
12
12
1 2
RC35@ 0_0402_5%
1 2
RC50 0_0402_5%
@
XTAL24_OUT
DIFFCLK_BIASREF
TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8
CLKOUT_LPC_0
CLKOUT_LPC_1
CLKOUT_ITPXDP
CLKOUT_ITPXDP_P
XTAL24_IN
RSVD
RSVD
LAN_SMBCLK <28>
LAN_SMBDATA <28>
SPI_PCH_CS0#_R
SPI_DIN64
SPI_PCH_DO2_64
SPI_PCH_CS1#_R
SPI_DIN32
SPI_PCH_DO2_32
A25
XTAL24_IN
B25
XTAL24_OUT
K21
M21
C26
CLK_BIASREF
C35
MCP_TESTLOW1
C34
MCP_TESTLOW2
AK8
MCP_TESTLOW3
AL8
MCP_TESTLOW4
AN15
PCI_CLK_LPC_0
AP15
PCI_CLK_LPC_1
B35
A35
from CPU to SPI ROM
PCH_SPI_CS1#
PCH_SPI_DO
PCH_SPI_DIN
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_DO2
PCH_SPI_DO3
+3.3V_SPI
RC224 0_0402_5%
RC225 0_0402_5%
RC226 0_0402_5%
RC227 0_0402_5%
RC228 0_0402_5%
RC229 0_0402_5%
RC230 0_0402_5%
RC231 0_0402_5%
2
DDR_XDP_WAN_SMBCLK <9,18,19,20>
DDR_XDP_WAN_SMBDAT <9,18,19,20>
64Mb Flash ROM
UC2
1
/CS
2
DO(IO1)
3
/WP(IO2)
4
GND
W25Q64FVSSIQ_SO8
32Mb Flash ROM
UC3
1
/CS
2
DO/IO1
3
/WP/IO2
4
GND
W25Q32FVSSIQ_SO8
VPRO@
1M_0402_5%
RC63
1 2
1 2
RC65@ 0_0402_5%
JSPI1
12
12
12
12
12
12
12
+3.3V_M
12
2
SPI_PCH_CS1#
SPI_PCH_DO
SPI_PCH_DIN
SPI_PCH_CLK
SPI_PCH_CS0#
SPI_PCH_DO2
SPI_PCH_DO3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
RPC14
2.2K_0804_8P4R_5%
12
12
1 2
1 2
1 2
1 2
1 2
DOCK
DEBUG
1
2
3
4 5
+PCH_VCCACLKPLL
RC693.01K_0402_1%
+3.3V_SPI
0.1U_0402_25V6
8
VCC
7
6
CLK
5
DI(IO0)
8
VCC
7
6
CLK
5
DI/IO0
XTAL24_OUT_R
SPI_PCH_DO3_64
SPI_CLK64
SPI_DO64
+3.3V_SPI
0.1U_0402_25V6
SPI_PCH_DO3_32
SPI_CLK32
SPI_DO32
3
4
24MHZ_12PF_X3G024000DC1H
1
2
MCP_TESTLOW1
MCP_TESTLOW2
MCP_TESTLOW3
MCP_TESTLOW4
/HOLD(IO3)
/HOLD/IO3
support SPI TPM
LPC_0 LPC_1 LPC_0 LPC_1
1
2 2
SIO
MEC
DOCK
DEBUG
3
4 4
5
6 6
7
8 8
9
10 10
11
12 12
13
14 14
15
16 16
17
18 18
19
20 20
21
G1
22
G2
23
G3
24
G4
E-T_6700K-Y20N-00L
CONN@
MEM_SMBCLK
MEM_SMBDATA
SML1_SMBCLK
SML1_SMBDATA
SML0_SMBCLK
SML0_SMBDATA
CC6
1 2
CC7
1 2
VPRO@
CC8
15P_0402_50V8J
YC2
CC11
15P_0402_50V8J
CLK_BIASREF
RC240 10K_0402_5%
RC241 10K_0402_5%
RC242 10K_0402_5%
RC243 10K_0402_5%
support LPC TPM
CLKBUFF
SIO
MEC
TPM
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (2/12)
CPU (2/12)
CPU (2/12)
LA-A961P
LA-A961P
LA-A961P
1
8
7
6
12
12
7 53Tuesday, October 07, 2014
7 53Tuesday, October 07, 2014
7 53Tuesday, October 07, 2014
+3.3V_ALW_PCH
RC33499_0402_1%
RC34499_0402_1%
1.0
1.0
1.0
Page 8
Vinafix.com
5
4
3
2
1
D D
DDR_A_D[0..63]<18>
C C
B B
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
AH63
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51
UC1C
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
BDW_ULT_DDR3L
DDR CHANNEL A
SA_CLK#0
SA_CLK0
SA_CLK#1
SA_CLK1
SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3
SA_CS#0
SA_CS#1
SA_ODT0
SA_RAS
SA_WE
SA_CAS
SA_BA0
SA_BA1
SA_BA2
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7
SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1
BDW_ULT_DDR3L
DDR CHANNEL B
SB_CK#0
SB_CK0
SB_CK#1
SB_CK1
SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3
SB_CS#0
SB_CS#1
SB_ODT0
SB_RAS
SB_WE
SB_CAS
SB_BA0
SB_BA1
SB_BA2
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7
AM38
AN38
AK38
AL38
AY49
AU50
AW49
AV50
AM32
AK32
AL32
AM35
AK35
AM33
AL35
AM36
AU49
AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46
AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18
AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18
AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18
UC1D
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
DDR_B_D[0..63]<19>
AU37
M_CLK_DDR#0
AV37
M_CLK_DDR0
AW36
M_CLK_DDR#1
AY36
M_CLK_DDR1
AU43
DDR_CKE0_DIMMA
AW43
DDR_CKE1_DIMMA DDR_CKE2_DIMMB
AY42
AY43
AP33
DDR_CS0_DIMMA#
AR32
DDR_CS1_DIMMA# DDR_CS2_DIMMB#
AP32
AY34
DDR_A_RAS#
AW34
DDR_A_WE#
AU34
DDR_A_CAS#
AU35
DDR_A_BS0
AV35
DDR_A_BS1
AY41
DDR_A_BS2
AU36
DDR_A_MA0
AY37
DDR_A_MA1
AR38
DDR_A_MA2
AP36
DDR_A_MA3
AU39
DDR_A_MA4
AR36
DDR_A_MA5
AV40
DDR_A_MA6
AW39
DDR_A_MA7
AY39
DDR_A_MA8
AU40
DDR_A_MA9
AP35
DDR_A_MA10
AW41
DDR_A_MA11
AU41
DDR_A_MA12
AR35
DDR_A_MA13
AV42
DDR_A_MA14
AU42
DDR_A_MA15
AJ61
DDR_A_DQS#0
AN62
DDR_A_DQS#1
AM58
DDR_A_DQS#2
AM55
DDR_A_DQS#3
AV57
DDR_A_DQS#4
AV53
DDR_A_DQS#5
AL43
DDR_A_DQS#6
AL48
DDR_A_DQS#7
AJ62
DDR_A_DQS0
AN61
DDR_A_DQS1
AN58
DDR_A_DQS2
AN55
DDR_A_DQS3
AW57
DDR_A_DQS4
AW53
DDR_A_DQS5
AL42
DDR_A_DQS6
AL49
DDR_A_DQS7
AP49
AR51
AP51
M_CLK_DDR#0 <18>
M_CLK_DDR0 <18>
M_CLK_DDR#1 <18>
M_CLK_DDR1 <18>
DDR_CKE0_DIMMA <18>
DDR_CKE1_DIMMA <18>
DDR_CS0_DIMMA# <18>
DDR_CS1_DIMMA# <18>
DDR_A_RAS# <18>
DDR_A_WE# <18>
DDR_A_CAS# <18>
DDR_A_BS0 <18>
DDR_A_BS1 <18>
DDR_A_BS2 <18>
DDR_A_MA[0..15] <18>
DDR_A_DQS#[0..7] <18>
DDR_A_DQS[0..7] <18>
+SM_VREF_CA
+SM_VREF_DQ0
+SM_VREF_DQ1
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
M_CLK_DDR#2
M_CLK_DDR2
M_CLK_DDR#3
M_CLK_DDR3
DDR_CKE3_DIMMB
DDR_CS3_DIMMB#
DDR_B_RAS#
DDR_B_WE#
DDR_B_CAS#
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
M_CLK_DDR#2 <19>
M_CLK_DDR2 <19>
M_CLK_DDR#3 <19>
M_CLK_DDR3 <19>
DDR_CKE2_DIMMB <19>
DDR_CKE3_DIMMB <19>
DDR_CS2_DIMMB# <19>
DDR_CS3_DIMMB# <19>
DDR_B_RAS# <19>
DDR_B_WE# <19>
DDR_B_CAS# <19>
DDR_B_BS0 <19>
DDR_B_BS1 <19>
DDR_B_BS2 <19>
DDR_B_MA[0..15] <19>
DDR_B_DQS#[0..7] <19>
DDR_B_DQS[0..7] <19>
BDW-ULT-DDR3L_BGA1168
3 OF 19
A A
BDW-ULT-DDR3L_BGA1168
4 OF 19
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (3/12)
CPU (3/12)
CPU (3/12)
LA-A961P
LA-A961P
LA-A961P
1
8 53Tuesday, October 07, 2014
8 53Tuesday, October 07, 2014
8 53Tuesday, October 07, 2014
1.0
1.0
1.0
Page 9
Vinafix.com
5
+3.3V_ALW_PCH
D D
+3.3V_RUN
C C
+1.05V_VCCST
B B
A A
1 2
RC79 10K_0402_5%
1 2
RC81 10K_0402_5%
1 2
RC82@ 10K_0402_5%
+3.3V_ALW_PCH
RPC1
4 5
3
6
2
7
1
8
10K_8P4R_5%
1 2
RC91 47K_0402_5%
1 2
RC95@ 8.2K_0402_5%
PCH_JTAG_TDO<6>
PCH_JTAG_TDI<6>
1 2
RC114@ 49.9_0402_1%
1 2
RC116 62_0402_5%
H_PROCHOT#
1
@EMC@
CC20
22P_0402_50V8J
2
EMI request add
H_CPUPWRGD
100P_0402_50V8J
10K_0402_5%
EMC@
12
RC123
CC83
1
2
CAD Note:
Avoid stub in the PWRGD path
while placing resistors RC123
ME_SUS_PWR_ACK
SUSACK#
SUS_STAT#/LPCPD#
KB_DET#
USB_OC3#
PCH_RSMRST#_Q
ME_RESET#
PCH_JTAG_TDI
PCH_JTAG_TMS<6>
RUNPWROK<35,36>
H_CATERR#
H_PROCHOT#
CC17
0.1U_0402_25V6
1 2
RC98 0_0402_5%
CXDP@
RUNPWROK
1 2
RC99 0_0402_5%
CXDP@
RUNPWROK
RUNPWROK
RUNPWROK
XDP_DBRESET#
RC80@ 8.2K_ 0402_5%
KB_DET# <12,37>
SIO_EXT_WAKE# <12,36>
USB_OC3# <11>
+3.3V_RUN
CXDP@
12
TDO_XDP
TDI_XDP_R
PCH_JTAG_TMS
TRST#_XDP
PCH_JTAG_TRST#<6>
PCH_JTAG_JTAGX<6>
UC7
CXDP@
14
VCC
2
1A
1
1OE
5
2A
4
2OE
9
3A
10
3OE
12
4A
13
4OE
74CBTLV3126BQ_DHVQFN14_2P5X3
reference Shark Bay ULT Validation Customer Debug Port
Implementation Requirement Rev 1.0
PCH_JTAG_TDO
PCH_JTAG_TCK
H_PROCHOT#<36,45,46>
DDR3_DRAMRST#_CPU<18>
DDR3 COMPENSATION SIGNALS
12
SM_RCOMP0
RC130200_0402_1%
12
SM_RCOMP1
RC131121_0402_1%
12
SM_RCOMP2
RC132100_0402_1%
CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil
5
4
1 2
RC77@ 0_0402_5%
+3.3V_RUN
1
2
12
ME_RESET#
PLTRST_VMM2320#<22>
GND PAD
12
CPU_XDP_TRST#
RC1090_0402_ 5% CXDP@
12
CPU_XDP_TCLK
RC1120_0402_5% CXDP@
12
TDO_XDP
RC115 @0_0402_5%
12
TDI_XDP_R
RC118 @0_0402_5%
12
CPU_XDP_TCLK
RC119 @0_0402_5%
PECI_EC<36>
1 2
RC121 56_0402_5%
DDR_PG_CTRL<18>
DDR3_DRAMRST#_CPU
CC101 place near AV15
4
5
P
B
4
O
A
G
74AHC1G09GW_TSSOP5
3
PLTRST_USH#<27>
PLTRST_MMI#<29>
PLTRST_LAN#<28>
3
1B
6
2B
8
3B
11
4B
7
GND
15
H_CATERR#
PECI_EC
H_PROCHOT#_R
H_CPUPWRGD
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
0.1U_0402_25V6
12
UC4@
SYS_PWROK<36>
RESET_OUT#<15,36>
PCH_RSMRST#_Q<37>
ME_SUS_PWR_ACK<36>
SIO_PWRBTN#<36>
AC_PRESENT<12,36>
PCH_BATLOW#<12>
SIO_SLP_WLAN#<35>
CPU_XDP_TDO
CPU_XDP_TDI
CPU_XDP_TMS
CPU_XDP_TRST#
@EMC@
CC101
3
+3.3V_RUN
5
1
SYS_RESET#
1 2
RC219@ 0_0402_5%
1 2
RC87@ 0_0402_5%
1 2
RC88@ 0_0402_5%
1 2
RC89@ 0_0402_5%
SUSACK#<36>
PCH_BATLOW#
UC1B
D61
PROC_DETECT
K61
CATERR
N62
PECI
K63
PROCHOT
C61
PROCPWRGD
AU60
SM_RCOMP0
AV60
SM_RCOMP1
AU61
SM_RCOMP2
AV15
SM_DRAMRST
AV61
SM_PG_CNTL1
BDW-ULT-DDR3L_BGA1168
2 OF 19
PCH_PLTRST#
TC7SH08FU_SSOP5~D
PCH_PLTRST#
AK2
SUSACK#
AC3
SYS_RESET#
AG2
SYS_PWROK
AY7
AB5
PM_APWROK_R
AG7
PCH_PLTRST#
MISC
THERMAL
PWR
DDR3L
AW6
AV4
AL7
AJ8
AN4
AF3
AM5
H_VCCST_PWRGD<15>
BDW_ULT_DDR3L
PCH_RSMRST#_Q PCH_RTCRST#
ME_SUS_PWR_ACK
SIO_PWRBTN#
AC_PRESENT
SIO_SLP_S0#
SIO_SLP_WLAN#
P
B
4
PCH_PLTRST#_EC
O
2
A
G
UC5
3
UC1H
SUSACK
SYS_RESET
SYS_PWROK
PCH_PWROK
APWROK
PLTRST
RSMRST
SUSWARN/SUSPWRDNACK/GPIO30
PWRBTN
ACPRESENT/GPIO31
BATLOW/GPIO72
SLP_S0
SLP_WLAN/GPIO29
BDW-ULT-DDR3L_BGA1168
8 OF 19
SYSTEM POWER MANAGEMENT
+1.05V_RUN
Place near JXDP1
RC102 1K_0 402_5%
CXDP@
H_CPUPWRGD
PROC_TCK
PROC_TMS
JTAG
PROC_TRST
PROC_TDI
PROC_TDO
12
RC304
@
100K_0402_5%
BDW_ULT_DDR3L
0.1U_0402_25V6
0.1U_0402_25V6
@
@
12
12
CC19
CC18
RC5 need to close to JCPU1
1 2
1 2
RC103@ 1K_0 402_5%
DDR_XDP_WAN_SMBDAT<7,18,19,20>
DDR_XDP_WAN_SMBCLK<7,18,19,20>
J62
CPU_XDP_PRDY#
PRDY
K62
CPU_XDP_PREQ#
PREQ
E60
CPU_XDP_TCLK
E61
CPU_XDP_TMS
E59
CPU_XDP_TRST#
F63
CPU_XDP_TDI
F62
CPU_XDP_TDO
J60
XDP_OBS0_R
BPM#0
H60
XDP_OBS1_R
BPM#1
H61
XDP_OBS2_R
BPM#2
H62
XDP_OBS3_R
BPM#3
K59
XDP_OBS4_R
BPM#4
H63
XDP_OBS5_R
BPM#5
K60
XDP_OBS6_R
BPM#6
J61
XDP_OBS7_R
BPM#7
PCH_PLTRST#_EC <27,30,35,36>
PM_APWROK P M_APWROK_L
PM_APWROK< 36>
1.05V_M_PWRGD<43>PCH_GPIO73 <7>
DSWVRMEN
DPWROK
WAKE
CLKRUN/GPIO32
SUS_STAT/GPIO61
SUSCLK/GPIO62
SLP_S5/GPIO63
SLP_S4
SLP_S3
SLP_A
SLP_SUS
SLP_LAN
CPU_XDP_PREQ#
CPU_XDP_PRDY#
CFG0<13>
CFG1<13>
CFG2<13>
CFG3<13>
CFG4<13>
CFG5<13>
CFG6<13>
CFG7<13>
H_VCCST_PWRGD_XDP
CPU_PWR_DEBUG#<15>
PCH_JTAG_TCK<6>
RC26@ 0_0402 _5%
RC27 0_0402_5%@
AW7
DSWODVREN
AV5
PCH_DPWROK
AJ5
PCH_PCIE_WAKE#
V5
CLKRUN#
AG4
SUS_STAT#/LPCPD#
AE6
SUSCLK_R
AP5
SIO_SLP_S5#
AJ6
SIO_SLP_S4#
AT4
SIO_SLP_S3#
AL5
SIO_SLP_A#
AP4
SIO_SLP_SUS#
AJ7
SIO_SLP_LAN#
CFG0
CFG1
CFG2
CFG3
XDP_OBS0_R
XDP_OBS1_R
CFG4
CFG5
CFG6
CFG7
SIO_PWRBTN#
SYS_PWROK
CPU_XDP_TCLK
+3.3V_ALW_PCH
0.1U_0402_25V6
CC22@
T10 @PAD~D
T11 @PAD~D
T12 @PAD~D
T13 @PAD~D
T14 @PAD~D
T15 @PAD~D
1 2
1 2
RC136 0_0402_5%@
+1.05V_RUN
JXDP1
1
3
5
7
13
19
21
23
25
31
37
41
45
47
49
51
53
55
57
59
1K_0402_5%
RC120
CXDP@
1 2
SYS_PWROK
12
Place near JXDP1.47
2
+3.3V_ALW2
5
CLKRUN# <12,35,36>
SIO_SLP_S5# <36>
T8 @PAD~D
T9@PAD~D
SIO_SLP_S4# <36>
SIO_SLP_S3# <36>
SIO_SLP_A# <36>
SIO_SLP_SUS# <36>
SIO_SLP_LAN# <28,36>
Place near JXDP1.48
1
P
B
2
A
G
TC7SH08FU_SSOP5~D
3
SUSCLK <30>
GND1
OBSFN_C0
OBSFN_C1
GND3
GND5
GND7
OBSFN_D0
OBSFN_D1
GND9
GND11
GND13
ITPCLK#/HOOK5
RESET#/HOOK6
DBR#/HOOK7
GND15
TRST#
GND17
CONN@SA MTE_BSH-030-01-L-D-A
XDP_DBRESET#
SIO_SLP_A#
PCH_DPWROK <36>
PCH_PCIE_WAKE# <12,35,36>
1 2
GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A09OBSDATA_C0
OBSDATA_A111OBSDATA_C1
GND4
OBSDATA_A215OBSDATA_C2
OBSDATA_A317OBSDATA_C3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B027OBSDATA_D0
OBSDATA_B129OBSDATA_D1
GND10
OBSDATA_B233OBSDATA_D2
OBSDATA_B335OBSDATA_D3
GND12
PWRGOOD/HOOK039ITPCLK/HOOK4
HOOK1
VCC_OBS_AB43VCC_OBS_CD
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16
O
TD0
TDI
TMS
4
PM_APWROK_R
UC6
+1.05V_RUN
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
12
+PCH_VCCDSW3_3
+PCH_VCCDSW3_3
XDP_RST#_R
XDP_DBRESET#
TDO_XDP
TRST#_XDP
PCH_JTAG_TDI
PCH_JTAG_TMS
0.1U_0402_25V6
CC21
CXDP@
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
1
+RTC_CELL
330K_0402_5%
RC78
1 2
DSWODVREN
DSWODVREN - ON DIE DSW VR ENABLE
HIGH = ENABLED (DEFAULT)
LOW = DISABLED
JAPS1
+3.3V_ALW_PCH
PCH_RTCRST#<6>
POWER_SW#_M B<32,36,39>
CFG17
CFG16
CFG8
CFG9
CFG10
CFG11
CFG19
CFG18
CFG12
CFG13
CFG14
CFG15
RC113 1K_0402_5%
CXDP@
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
SIO_SLP_S3#
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_A#
SYS_RESET#
SIO_SLP_S0#
CFG17 <13>
CFG16 <13>
CFG8 <13>
CFG9 <13>
CFG10 <13>
CFG11 <13>
CFG19 <13>
CFG18 <13>
CFG12 <13>
CFG13 <13>
CFG14 <13>
CFG15 <13>
RC106 1K_0402_5%
CXDP@
1 2
CFG3CFG3_R
TDO_XDP
51_0402_5%
1 2
CFG3
RC305 1K_0402_5%CXDP@
XDP_DBRESET#
1K_0402_5%
CPU_XDP_TMS
51_0402_5%
CPU_XDP_TDI
51_0402_5%
CPU_XDP_PREQ#
51_0402_5%
CPU_XDP_TDO
51_0402_5%
CPU_XDP_TCLK
51_0402_5%
CPU_XDP_TRST#
51_0402_5%
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
CPU (4/12)
CPU (4/12)
CPU (4/12)
12
LA-A961P
LA-A961P
LA-A961P
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
GND
20
GND
CONN@
ACES_50506-01841-P01
20130726 same as Goliad
PCH_PLTRST#_EC
+1.05V_RUN
12
@
RC117
+3.3V_RUN
12
RC122
+1.05V_RUN
@
12
RC124
@
12
RC125
@
12
RC126
12
RC127
12
RC128
@
12
RC129
9 53Tuesday, October 07, 2014
9 53Tuesday, October 07, 2014
1
9 53Tuesday, October 07, 2014
1.0
1.0
1.0
Page 10
Vinafix.com
5
D D
4
3
2
1
BDW_ULT_DDR3L
PCIE
BDW_ULT_DDR3L
EDPDDI
DISPLAY
EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1
EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3
EDP_AUXN
EDP_AUXP
EDP_RCOMP
EDP_DISP_UTIL
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP
DDPB_HPD
DDPC_HPD
EDP_HPD
C45
B46
A47
B47
C47
C46
A49
B49
A45
B45
D20
A43
B9
C9
D9
D11
C5
B6
B5
A6
C8
A8
D6
EDP_CPU_LANE_N0
EDP_CPU_LANE_P0
EDP_CPU_LANE_N1
EDP_CPU_LANE_P1
EDP_CPU_AUX#
EDP_CPU_AUX
EDP_COMP
CPU_DPB_CTRLCLK
CPU_DPB_CTRLDAT
CPU_DPC_CTRLCLK
CPU_DPC_CTRLDAT
CPU_DPB_AUX#
CPU_DPC_AUX#
CPU_DPB_AUX
CPU_DPC_AUX
DPC_HPD
EDP_CPU_HPD
EDP_CPU_LANE_N0 <23>
EDP_CPU_LANE_P0 <23>
EDP_CPU_LANE_N1 <23>
EDP_CPU_LANE_P1 <23>
EDP_CPU_AUX# <23>
EDP_CPU_AUX <23>
CPU_DPB_CTRLCLK <25>
CPU_DPB_CTRLDAT <25>
CPU_DPC_CTRLCLK <24>
CPU_DPC_CTRLDAT <24>
CPU_DPB_AUX# <25>
CPU_DPC_AUX# <24>
CPU_DPB_AUX <25>
CPU_DPC_AUX <24>
DPB_HPD <25>
DPC_HPD <24>
EDP_CPU_HPD <23>
COMPENSATION PU FOR eDP
+VCCIOA_OUT
RPC2
1
2
3
4 5
RPC20
1
2
3
4 5
12
RC13324.9_0402_1%
8
7
6
8
7
6
12
RC141100K_0402_5%
12
RC142100K_0402_5%
EDP_COMP
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
CPU_DPB_CTRLCLK
CPU_DPB_CTRLDAT
CPU_DPC_CTRLDAT
CPU_DPC_CTRLCLK
CPU_DPB_AUX#
CPU_DPB_AUX
CPU_DPC_AUX#
CPU_DPC_AUX
EDP_CPU_HPD
DPB_HPD
2.2K_0804_8P4R_5%
100K_0804_8P4R_5%
+3.3V_RUN
UC1A
C54
DDI1_LANE_N0<25>
DDI1_LANE_P0<25>
DDI1_LANE_N1<25>
DDI1_LANE_P1<25>
DDI1_LANE_N2<25>
DDI1_LANE_P2<25>
DDI1_LANE_N3<25>
DDI1_LANE_P3<25>
DDI2_LANE_N0<24>
DDI2_LANE_P0<24>
DDI2_LANE_N1<24>
DDI2_LANE_P1<24>
DDI2_LANE_N2<24>
DDI2_LANE_P2<24>
DDI2_LANE_N3<24>
C C
+3.3V_RUN
B B
RPC15
45
3
6
2
7
1
8
10K_8P4R_5%
1 2
RC139@ 100K_0402_5%
RC140@ 1K_0402_5%
12
ENVDD_PCH
PCH_GPIO53
GC6_EVENT#_Q <12>
CPUSB# <12>
USH_DET# <12,27>
CAM_MIC_CBL_DET# <12,23>
DDI2_LANE_P3<24>
EDP_BIA_PWM
PANEL_BKLEN
ENVDD_PCH
DGPU_PWROK
HDD_FALL_INT
PCH_GPIO53
CONTACTLESS_DET#<12,27>
DGPU_PWROK<7>
HDD_FALL_INT<6,20>
TOUCHPAD_INTR#<12>
EDP_BIA_PWM<23>
PANEL_BKLEN<23>
ENVDD_PCH<23,36>
PCH_GPIO80<12>
T16@ PAD~D
PCH_GPIO52<12>
DDI1_TXN0
C55
DDI1_TXP0
B58
DDI1_TXN1
C58
DDI1_TXP1
B55
DDI1_TXN2
A55
DDI1_TXP2
A57
DDI1_TXN3
B57
DDI1_TXP3
C51
DDI2_TXN0
C50
DDI2_TXP0
C53
DDI2_TXN1
B54
DDI2_TXP1
C49
DDI2_TXN2
B50
DDI2_TXP2
A53
DDI2_TXN3
B53
DDI2_TXP3
BDW-ULT-DDR3L_BGA1168
1 OF 19
UC1I
B8
EDP_BKLCTL
A9
EDP_BKLEN
C6
EDP_VDDEN
U6
PIRQA/GPIO77
P4
PIRQB/GPIO78
N4
PIRQC/GPIO79
N2
PIRQD/GPIO80
AD4
PME
U7
GPIO55
L1
GPIO52
L3
GPIO54
R5
GPIO51
L4
GPIO53
BDW-ULT-DDR3L_BGA1168
9 OF 19
eDP SIDEBAND
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (5/12)
CPU (5/12)
CPU (5/12)
LA-A961P
LA-A961P
LA-A961P
10 53Tuesday, October 07, 2014
10 53Tuesday, October 07, 2014
10 53Tuesday, October 07, 2014
1
1.0
1.0
1.0
Page 11
Vinafix.com
5
4
3
2
1
PCIE for UMA
D D
PCIE_PRX_WIGIGTX_N5<30>
WIGIG --->
10/100/1G LAN --->
C C
WLAN (Mini Card 2)--->
MMI -->
+PCH_AUSB3PLL
B B
PCB
G12 UMA
PCIE1 PCIE4
SD card
G12 Entry NA
G14 DSC
G14 UMA
G14D_En
SD card
SD card
SD card
PCIE3PCIE2
NA LOM
NA
LOM
NA
LOM
NA
LOM
NA
LOM
PCIE_PRX_WIGIGTX_P5<30>
PCIE_PTX_WIGIGRX_N5<30>
PCIE_PTX_WIGIGRX_P5<30>
PCIE_PRX_GLANTX_N3<28>
PCIE_PRX_GLANTX_P3<28>
PCIE_PTX_GLANRX_N3<28>
PCIE_PTX_GLANRX_P3<28>
PCIE_PRX_WLANTX_N4<30>
PCIE_PRX_WLANTX_P4<30>
PCIE_PTX_WLANRX_N4<30>
PCIE_PTX_WLANRX_P4<30>
PCIE_PRX_MMITX_N1<29>
PCIE_PRX_MMITX_P1<29>
PCIE_PTX_MMIRX_N1<29>
PCIE_PTX_MMIRX_P1<29>
USB3RN4<31>
USB3RP4<31>
USB3TN4<31>
USB3TP4<31>
1 2
RC149 3.01K_0402_1%
PCIE5
WLAN
WLAN
WLAN
WLAN
WLAN
WIGIG
WIGIGSD card
GPU
WIGIG
GPU
PCIE_PRX_WIGIGTX_N5
PCIE_PRX_WIGIGTX_P5
PCIE_PTX_WIGIGRX_N5
PCIE_PTX_WIGIGRX_P5
PCIE_PRX_GLANTX_N3
PCIE_PRX_GLANTX_P3
PCIE_PTX_GLANRX_N3
PCIE_PTX_GLANRX_P3
PCIE_PRX_WLANTX_N4
PCIE_PRX_WLANTX_P4
PCIE_PTX_WLANRX_N4
PCIE_PTX_WLANRX_P4
PCIE_PRX_MMITX_N1
PCIE_PRX_MMITX_P1
PCIE_PTX_MMIRX_N1
PCIE_PTX_MMIRX_P1
PCH_PCIE_RCOMP
PCIE6
M2 3042
(HCA & SATA-Cache)
WIGIG
M2 3042
(HCA & SATA-Cache)
WIGIG
UC1K
F10
PERN5_L0
E10
PERP5_L0
C23
PETN5_L0
C22
PETP5_L0
F8
PERN5_L1
E8
PERP5_L1
B23
PETN5_L1
A23
PETP5_L1
H10
PERN5_L2
G10
PERP5_L2
B21
PETN5_L2
C21
PETP5_L2
E6
PERN5_L3
F6
PERP5_L3
B22
PETN5_L3
A21
PETP5_L3
G11
PERN3
F11
PERP3
C29
PETN3
B30
PETP3
F13
PERN4
G13
PERP4
B29
PETN4
A29
PETP4
G17
PERN1/USB3RN3
F17
PERP1/USB3RP3
C30
PETN1/USB3TN3
C31
PETP1/USB3TP3
F15
PERN2/USB3RN4
G15
PERP2/USB3RP4
B31
PETN2/USB3TN4
A31
PETP2/USB3TP4
E15
RSVD
E13
RSVD
A27
PCIE_RCOMP
B27
PCIE_IREF
BDW-ULT-DDR3L_BGA1168
11 OF 19
BDW_ULT_DDR3L
PCIE USB
USB2N0
USB2P0
USB2N1
USB2P1
USB2N2
USB2P2
USB2N3
USB2P3
USB2N4
USB2P4
USB2N5
USB2P5
USB2N6
USB2P6
USB2N7
USB2P7
USB3RN1
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USBRBIAS
USBRBIAS
RSVD
RSVD
OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43
AN8
AM8
AR7
AT7
AR8
AP8
AR10
AT10
AM15
AL15
AM13
AN13
AP11
AN11
AR13
AP13
G20
H20
C33
B34
E18
F18
B33
A33
AJ10
AJ11
AN10
AM10
AL3
AT1
AH2
AV3
USBP0USBP0+
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
USBRBIAS
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USBP0- <31>
USBP0+ <31>
USBP1- <32>
USBP1+ <32>
USBP2- <30>
USBP2+ <30>
USBP3- <31>
USBP3+ <31>
USBP4- <23>
USBP4+ <23>
USBP5- <23>
USBP5+ <23>
USBP6- <27>
USBP6+ <27>
USBP7- <30>
USBP7+ <30>
USB3RN1 <31>
USB3RP1 <31>
USB3TN1 <31>
USB3TP1 <31>
USB3RN2 <32>
USB3RP2 <32>
USB3TN2 <32>
USB3TP2 <32>
USB_OC0# <31>
USB_OC1# <12,32>
USB_OC2# <31>
USB_OC3# <9>
-----> Ext Port 1
-----> Ext Port 2 charge
-----> WLAN/BT
-----> Ext Port 3
-----> Touch
-----> Camera
-----> USH
-----> WWAN
-----> Ext USB3 Port 1 charge
-----> Ext USB3 Port 2
-----> USB Port0 (JUSB1)
-----> USB Port1 (JUSB3)
-----> USB Port3 (JUSB2)
GPIO57<12>
SIO_EXT_SMI#<12,36>
USBRBIAS
CAD NOTE:
Route single-end 50-ohms and max 500-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15
mils.
GPIO57
USB_OC0#
USB_OC2#
22.6_0402_1%
12
PCB
G12 UMA WWAN
G12 Entry
G14 DSC
G14 UMA
G14D_En
G14U_En
RPC19
4 5
3
2
1
10K_8P4R_5%
RC152
USB2 7
WWAN
WWAN
6
7
8
NA
NA
NA
+3.3V_ALW_PCH
G14U_En
A A
SD card
NA
LOM
WLAN
WIGIG
NA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (6/12)
CPU (6/12)
CPU (6/12)
LA-A961P
LA-A961P
LA-A961P
11 53Tuesday, October 07, 2014
11 53Tuesday, October 07, 2014
11 53Tuesday, October 07, 2014
1
1.0
1.0
1.0
Page 12
Vinafix.com
5
+PCH_VCCDSW3_3
12
1 2
RPC10
4 5
3
2
1
1 2
RPC5
4 5
3
2
1
RPC7
4 5
3
2
1
LAN_WAKE#
12
MPHYP_PWR_EN
12
SIO_EXT_SCI#
TPM_PIRQ#
MEDIACARD_IRQ#
6
MEDIACARD_RST#
7
SLATE_MODE
8
PCH_GPIO44
PM_LANPHY_ENABLE
6
7
8
PCH_GPIO46
6
PCH_GPIO9
7
8
12
PCH_GPIO59
12
3.3V_CAM_EN#
12
NFC_IRQ
12
MPHYP_PWR_EN
10K_0402_5%
PCH_BATLOW# <9>
AC_PRESENT <9,36>
PCH_PCIE_WAKE# <9,35,36>
PCH_GPIO46 <12>
USB_OC1# <11,32>
PCH_SMB_ALERT# <7>
+3.3V_RUN
1K_0402_5%
12
PCH_GPIO76<7>
PM_LANPHY_ENABLE<28>
TOUCH_PANEL_INTR#<6,23>
RC176@
PCH_GPIO66
TPM_PIRQ#<27>
GPIO57<11>
MEDIACARD_IRQ#<29>
MPHYP_PWR_EN<38>
KB_DET#<9,37>
@ PAD~D
RC153 10K_0402_5%
+3.3V_RUN
D D
RC155 100K_0402_5%
RC156 100K_0402_5%
+3.3V_RUN
RC247 10K_0402_5%
+PCH_VCCDSW3_3
+3.3V_ALW_PCH
C C
10K_8P4R_5%
RC92 10K_0402_5%@
10K_8P4R_5%
10K_8P4R_5%
B B
RC245 100K_0402_5%
RC174 100K_0402_5%
RC175 100K_0402_5%
@
RC171
SIO_EXT_WAKE#<9,36>
PCH_GPIO16<12>
LAN_WAKE#<28,36>
T22
@ PAD~D
T21
3.3V_CAM_EN#<23>
SIO_EXT_SMI#<11,36>
PCH_GPIO46<12>
T27@ PAD~D
mSATA_DEVSLP<30>
HDD_DEVSLP<20>
SIO_EXT_SCI#<36>
SPKR<21>
4
UC1J
PCH_GPIO76
SIO_EXT_WAKE# SIO_RCIN#
HOST_ALERT1_R_N
LAN_WAKE#
NFC_IRQ
MEDIACARD_RST#
GPIO57
SLATE_MODE
PCH_GPIO59
PCH_GPIO44
DIMM_DET
PCH_GPIO49
TOUCH_PANEL_INTR#
MPHYP_PWR_EN
KB_DET#
PCH_GPIO14
3.3V_CAM_EN#
SIO_EXT_SMI#
PCH_GPIO9
PCH_GPIO10
SIO_EXT_SCI#
SPKR
+3.3V_RUN
P1
BMBUSY/GPIO76
AU2
GPIO8
AM7
LAN_PHY_PWR_CTRL/GPIO12
AD6
GPIO15
Y1
GPIO16
T3
GPIO17
AD5
GPIO24
AN5
GPIO27
AD7
GPIO28
AN3
GPIO26
AG6
GPIO56
AP1
GPIO57
AL4
GPIO58
AT5
GPIO59
AK4
GPIO44
AB6
GPIO47
U4
GPIO48
Y3
GPIO49
P3
GPIO50
Y2
HSIOPC/GPIO71
AT3
GPIO13
AH4
GPIO14
AM4
GPIO25
AG5
GPIO45
AG3
GPIO46
AM3
GPIO9
AM2
GPIO10
P2
DEVSLP0/GPIO33
C4
SDIO_POWER_EN/GPIO70
L2
DEVSLP1/GPIO38
N5
DEVSLP2/GPIO39
V2
SPKR/GPIO81
BDW-ULT-DDR3L_BGA1168
10 OF 19
10K_0402_5%
12
RC302@
DIMM_DET
10K_0402_5%
12
RC303
BDW_ULT_DDR3L
GPIO
+3.3V_ALW_PCH
1K_0402_5%
12
RC179
HOST_ALERT1_R_N
3
CPU/
MISC
SERIAL IO
THRMTRIP
RCIN/GPIO82
SERIRQ
PCH_OPI_RCOMP
RSVD
RSVD
GSPI0_CS/GPIO83
GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86
GSPI1_CS/GPIO87
GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89
GSPI_MOSI/GPIO90
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART0_RTS/GPIO93
UART0_CTS/GPIO94
UART1_RXD/GPIO0
UART1_TXD/GPIO1
UART1_RST/GPIO2
UART1_CTS/GPIO3
I2C0_SDA/GPIO4
I2C0_SCL/GPIO5
I2C1_SDA/GPIO6
I2C1_SCL/GPIO7
SDIO_CLK/GPIO64
SDIO_CMD/GPIO65
SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69
+3.3V_RUN
D60
V4
T4
AW15
AF20
AB21
R6
GC6_EVENT#_Q
L6
GPU_GC6_FB_EN
N6
PCH_GPIO85
L8
BBS_BIT
R7
L5
3.3V_TP_EN
N7
K2
J1
CPPE#
K3
CPUSB#
J2
G1
K4
G2
FFS_INT2
J3
LCD_CBL_DET#
J4
F2
PCH_GPIO4
F3
PCH_GPIO5
G4
PCH_GPIO6
F1
PCH_GPIO7
E3
USH_DET#
F4
CAM_MIC_CBL_DET#
D3
PCH_GPIO66
E4
PCH_GPIO67
C3
PCH_GPIO68
E2
PCH_GPIO69
1K_0402_5%
12
RC180@
H_THERMTRIP#_R
IRQ_SERIRQ
PCH_OPI_COMP
SPKR
2
SIO_RCIN# <36>
IRQ_SERIRQ <35,36>
GC6_EVENT#_Q <10>
T109@PAD~D
PCH_GPIO87 <6>
3.3V_TS_EN <12,23>
3.3V_HDD_EN <28>
CPUSB# <10>
FFS_INT2 <20>
LCD_CBL_DET# <23>
USH_DET# <10,27>
CAM_MIC_CBL_DET# <10,23>
12
RC161@0_0402_5%
MPCIE_RST#<6>
CLKRUN#<9,35,36>
H_THERMTRIP# <36>
3.3V_TS_EN<12,23>
PCH_GPIO80<10>
PCH_GPIO52<10>
TOUCHPAD_INTR#<10>
WIGIGCLK_REQ#<7,30>
CONTACTLESS_DET#<10,27>
PCH_GPIO16<12>
LANCLK_REQ#<7,28>
mCARD_PCIE#_SATA<6,36>
SATA2_PCIE6_L1<6,35>
H_THERMTRIP#
IRQ_SERIRQ
SIO_RCIN#
CPPE#
FFS_INT2
PCH_GPIO67
PCH_GPIO68
GPU_GC6_FB_EN
PCH_GPIO85
3.3V_TP_EN
PCH_GPIO5
LCD_CBL_DET#
PCH_GPIO6
PCH_GPIO7
PCH_GPIO4
PCH_GPIO69
PCH_OPI_COMP
1
RPC17
6
7
8
10K_8P4R_5%
RPC16
6
7
8
10K_8P4R_5%
RPC3
6
7
8
10K_8P4R_5%
RPC4
6
7
8
10K_8P4R_5%
RPC8
1
2
3
4 5
10K_0804_8P4R_5%
RPC9
6
7
8
10K_8P4R_5%
1 2
12
45
3
2
1
12
12
12
12
45
3
2
1
45
3
2
1
45
3
2
1
8
7
6
45
3
2
1
RC17849.9_0402_1%
+1.05V_VCCST
RC251K_0402_5%
+3.3V_RUN
RC160100K_0402_5%
RC158100K_0402_5%
RC16310K_0402_5%
RC16410K_0402_5%
HIGH
LOW(DEFAULT)
A A
ENABLE
DISABLE
HIGH
LOW
1 DIMM
2 DIMM
DIMM Detect
TLS CONFIDENTIALITYTOP-BLOCK SWAP OVERRIDE
HIGH
LOW(DEFAULT)
ENABLE
DISABLE
No Reboot on TCO Timer expiration
HIGH
LOW(DEFAULT)
ENABLE
DISABLE
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (7/12)
CPU (7/12)
CPU (7/12)
LA-A961P
LA-A961P
LA-A961P
12 53Tuesday, October 07, 2014
12 53Tuesday, October 07, 2014
12 53Tuesday, October 07, 2014
1
1.0
1.0
1.0
Page 13
Vinafix.com
5
D D
4
3
2
1
CFG STRAPS for CPU
UC1S
AC60
12
CFG_RCOMP
TDI_IREF
CFG0
CFG1
CFG4
CFG8
CFG9
CFG10
CFG_RCOMP
TDI_IREF
CFG0
AC62
CFG1
AC63
CFG2
AA63
CFG3
AA60
CFG4
Y62
CFG5
Y61
CFG6
Y60
CFG7
V62
CFG8
V61
CFG9
V60
CFG10
U60
CFG11
T63
CFG12
T62
CFG13
T61
CFG14
T60
CFG15
AA62
CFG16
U63
CFG18
AA61
CFG17
U62
CFG19
V63
CFG_RCOMP
A5
RSVD
E1
RSVD
D1
RSVD
J20
RSVD
H18
RSVD
B12
TD_IREF
BDW-ULT-DDR3L_BGA1168
19 OF 19
CFG0<9>
CFG1<9>
CFG2<9>
CFG3<9>
CFG4<9>
CFG5<9>
CFG6<9>
CFG7<9>
CFG8<9>
CFG9<9>
CFG10<9>
CFG11<9>
CFG12<9>
CFG13<9>
C C
CFG14<9>
CFG15<9>
CFG16<9>
CFG18<9>
CFG17<9>
CFG19<9>
RC185 49.9_0402_1%
1 2
RC186 8.2K_0402_1%
BDW_ULT_DDR3L
RESERVED
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
PROC_OPI_RCOMP
RSVD
RSVD
VSS
VSS
RSVD
RSVD
AV63
AU63
C63
C62
B43
A51
B51
L60
N60
W23
Y22
AY15
PROC_OPI_RCOMP
AV62
D58
P22
N21
P20
R20
PROC_OPI_RCOMP
1 2
T28@PAD~D
T29@PAD~D
T30@PAD~D
T31@PAD~D
T33@PAD~D
T34@PAD~D
T35@PAD~D
EAR-STALL/NOT STALL RESET SEQUENCE AFTER PCU PLL IS LOCKE
CFG0
1:(Default) Normal Operation; No stall
0:Lane Reversed
PCH/PCH LESS MODE SELECTION
CFG1
RC18749.9_0402_1%
1:(Default) Normal Operation
0:Lane Reversed
CFG1
CFG0
1K_0402_1%
12
RC183@
1K_0402_1%
12
RC184@
B B
SAFE MODE BOOT
CFG10
A A
CFG10 CFG4
1K_0402_1%
12
RC188@
NO SVID PROTOCOL CAPABLE VR CONNECTED
1: POWER FEATURES ACTIVATED DURING
RESET
0: POWER FEATURES (ESPECIALLY CLOCK
GATINE ARE NOT ACTIVATED
CFG9
CFG9
12
1K_0402_1%
RC189@
1: VRS support SVID protocol are present
0:No VR support SVID is present
The chip will not generate(OR Respond to)
SVID activity
ALLOW THE USE OF NOA ON LOCKED UNITS
CFG8
CFG8
1: Enable(Default): Noa will be disable in
locked units and enable in un-locked
units
0: Enable Noa will be available pegardless of
the locking of the unit
1K_0402_1%
12
RC190@
CFG4
1K_0402_5%
12
RC191
Display Port Presence Strap
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (8/12)
CPU (8/12)
CPU (8/12)
LA-A961P
LA-A961P
LA-A961P
13 53Tuesday, October 07, 2014
13 53Tuesday, October 07, 2014
13 53Tuesday, October 07, 2014
1
1.0
1.0
1.0
Page 14
Vinafix.com
5
D D
C C
4
DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
DC_TEST_AY60
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
TP_DC_TEST_B2
DC_TEST_A3_B3
DC_TEST_A61_B61
DC_TEST_B62_B63
DC_TEST_C1_C2
UC1Q
AY2
DAISY_CHAIN_NCTF_AY2
AY3
DAISY_CHAIN_NCTF_AY3
AY60
DAISY_CHAIN_NCTF_AY60
AY61
DAISY_CHAIN_NCTF_AY61
AY62
DAISY_CHAIN_NCTF_AY62
B2
DAISY_CHAIN_NCTF_B2
B3
DAISY_CHAIN_NCTF_B3
B61
DAISY_CHAIN_NCTF_B61
B62
DAISY_CHAIN_NCTF_B62
B63
DAISY_CHAIN_NCTF_B63
C1
DAISY_CHAIN_NCTF_C1
C2
DAISY_CHAIN_NCTF_C2
BDW-ULT-DDR3L_BGA1168
17 OF 19
3
1
BDW_ULT_DDR3L
3
12
RC195@0_0402_5%
12
RC192@0_0402_5%
DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4
DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_A62
DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
DAISY_CHAIN_NCTF_AW2
DAISY_CHAIN_NCTF_AW3
DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63
A3
DC_TEST_A3_B3
A4
DC_TEST_A4
A60
DC_TEST_A60
A61
DC_TEST_A61_B61
A62
DC_TEST_A62
AV1
DC_TEST_AV1
AW1
DC_TEST_AW1
AW2
DC_TEST_AY2_AW2
AW3
DC_TEST_AY3_AW3
AW61
DC_TEST_AY61_AW61
AW62
DC_TEST_AY62_AW62
AW63
DC_TEST_AW63
2
2
12
RC193@0_0402_5%
12
RC194@0_0402_5%
4
1
Package Daisy Chain:
1.B2-PKG-C1-PCB-C2-PKG-B3-PCB-A3-PKG-A4
2.A62-PKG-A61-PCB-B61-PKG-B62-PCB-B63-PKG-A60
3.AY60-PKG-AW61-PCB-AY61-PKG-AW62-PCB-AY62-PKG-AW63
4.AW1-PKG-AW3-PCB-AY3-PKG-AW2-PCB-AY2-PKG-AV1
UC1R
AT2
RSVD
AU44
RSVD
B B
A A
AV44
RSVD
D15
RSVD
F22
RSVD
H22
RSVD
J21
RSVD
BDW-ULT-DDR3L_BGA1168
18 OF 19
BDW_ULT_DDR3L
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
N23
R23
T23
U10
AL1
AM11
AP7
AU10
AU15
AW14
AY14
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (9/12)
CPU (9/12)
CPU (9/12)
LA-A961P
LA-A961P
LA-A961P
14 53Tuesday, October 07, 2014
14 53Tuesday, October 07, 2014
14 53Tuesday, October 07, 2014
1
1.0
1.0
1.0
Page 15
Vinafix.com
5
4
3
2
1
ESD Request
+1.05V_RUN +VCCIO_OUT
+1.05V_RUN
D D
C C
12
RC197
150_0402_5%
CPU_PWR_DEBUG#
10K_0402_5%
12
@
RC198
H_VR_EN
RESET_OUT#<9,36>
SVID ALERT
VIDALERT_N<45>
B B
SVID DATA
VIDSOUT<45>
RESISTOR STUFFING OPTIONS ARE
PROVIDED FOR TESTING PURPOSES
12
+1.05V_VCCST
75_0402_1%
12
RC204
+1.05V_VCCST
110_0402_1%
12
RC208
VCC_SENSE
VCCSENSE<45>
A A
CAD Note: RC209 SHOULD BE PLACED CLOSE TO CPU
H_VR_READY
RC2011.5K_0402_5%
+VCC_CORE
1
2
3
12
RC196 0_0603_5%@
+1.05V_VCCST
UC8
NC
A
GND
74AUP1G07GW_TSSOP5
VIDSOUT
100_0402_1%
RC209
12
10K_0402_5%
12
RC199@
+3.3V_ALW
5
VCC
Y
CAD Note: Place the PU resistors close to CPU
RC204 close to CPU 300 1500mils
12
RC20743_0402_5%
CAD Note: Place the PU resistors close to CPU
RC208close to CPU 300 - 1500mils
VCCSENSE
1 2
CC35@ 0.1U_0402_25V6
4
H_VCCST_PWRGD
H_CPU_SVIDALRT#
+VCC_CORE
+1.05V_RUN
+1.05V_RUN +3.3V_RUN
+1.05V_VCCST
1K_0402_5%
RC202
1 2
1 2
CC23
1 2
CC79
1 2
CC84
1 2
CC85
H_VCCST_PWRGD
1
EMC@
2
CC24
100P_0402_50V8J
+1.05V_RUN +1.05V_VCCST
22U_0603_6.3V6M@EMC@
22U_0603_6.3V6M@EMC@
22U_0603_6.3V6M@EMC@
22U_0603_6.3V6M@EMC@
H_VCCST_PWRGD<9>
H_VR_EN<36,45>
H_VR_READY<45>
PJP23
@
1 2
PAD-OPEN1x1m
+1.35V_MEM
+VCC_CORE
+1.35V_MEM
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
@
@
12
12
+1.35V_MEM
+VCC_CORE
+VCCIO_OUT
+VCCIOA_OUT
VIDSCLK<45>
CPU_PWR_DEBUG#<9>
T74@
PAD~D
T75@
PAD~D
T76@
PAD~D
T77@
PAD~D
+1.05V_VCCST
+VCC_CORE
22U_0603_6.3V6M
1U_0402_6.3V6K
CC36
12
12
@
CC37
CC26
CC25
VCCSENSE
H_CPU_SVIDALRT#
VIDSCLK
VIDSOUT
H_VCCST_PWRGD
H_VR_EN
H_VR_READY
2.2U_0402_6.3V6M
12
CC27
L59
J58
AH26
AJ31
AJ33
AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50
F59
N58
AC58
E63
AB23
A59
E20
AD23
AA23
AE59
L62
N63
L63
B59
F60
C59
D63
H59
P62
P60
P61
N59
N61
T59
AD60
AD59
AA59
AE60
AC59
AG58
U59
V59
AC22
AE22
AE23
AB57
AD57
AG57
C24
C28
C32
VDDQ DECOUPLING
10U_0603_6.3V6M
2.2U_0402_6.3V6M
12
12
UC1L
RSVD
RSVD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VCC
RSVD
RSVD
VCC_SENSE
RSVD
VCCIO_OUT
VCCIOA_OUT
RSVD
RSVD
RSVD
VIDALERT
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY
VSS
PWR_DEBUG
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VCCST
VCCST
VCCST
VCC
VCC
VCC
VCC
VCC
VCC
BDW-ULT-DDR3L_BGA1168
12 OF 19
CC29
CC28
10U_0603_6.3V6M
@
12
CC30
BDW_ULT_DDR3L
HSW ULT POWER
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
12
12
CC32
CC31
10U_0603_6.3V6M
@
12
12
CC33
CC34
+VCC_CORE
C36
VCC
C40
VCC
C44
VCC
C48
VCC
C52
VCC
C56
VCC
E23
VCC
E25
VCC
E27
VCC
E29
VCC
E31
VCC
E33
VCC
E35
VCC
E37
VCC
E39
VCC
E41
VCC
E43
VCC
E45
VCC
E47
VCC
E49
VCC
E51
VCC
E53
VCC
E55
VCC
E57
VCC
F24
VCC
F28
VCC
F32
VCC
F36
VCC
F40
VCC
F44
VCC
F48
VCC
F52
VCC
F56
VCC
G23
VCC
G25
VCC
G27
VCC
G29
VCC
G31
VCC
G33
VCC
G35
VCC
G37
VCC
G39
VCC
G41
VCC
G43
VCC
G45
VCC
G47
VCC
G49
VCC
G51
VCC
G53
VCC
G55
VCC
G57
VCC
H23
VCC
J23
VCC
K23
VCC
K57
VCC
L22
VCC
M23
VCC
M57
VCC
P57
VCC
U57
VCC
W57
VCC
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (10/12)
CPU (10/12)
CPU (10/12)
LA-A961P
LA-A961P
LA-A961P
15 53Tuesday, October 07, 2014
15 53Tuesday, October 07, 2014
15 53Tuesday, October 07, 2014
1
1.0
1.0
1.0
Page 16
Vinafix.com
5
4
3
2
1
12
+
GPIO/LPC
330U_D3_2.5VY_R6M
@
CC39
BDW_ULT_DDR3L
HSIO
OPI
USB3
HDA
VRM
+1.05V_RUN+1.05V_M
@EMC@
330U_D3_2.5VY_R6M
1
+
CC41
2
THERMAL SENSOR
SERIAL IO
SUS OSCILLATOR
RTC
SPI
CORE
USB2
1
+
2
330U_D3_2.5VY_R6M
@EMC@
CC42
VCCSUS3_3
DCPSUSBYP
DCPSUSBYP
VCCRTC
DCPRTC
VCCSPI
VCCASW
VCCASW
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCCASW
VCCASW
VCCASW
DCPSUS1
DCPSUS1
VCCTS1_5
VCC3_3
VCC3_3
VCCSDIO
VCCSDIO
DCPSUS4
RSVD
VCC1_05
VCC1_05
AH11
AG10
AE7
Y8
AG14
AG13
J11
H11
H15
AE8
AF22
AG19
AG20
AE9
AF9
AG8
AD10
AD8
J15
K14
K16
U8
T9
AB8
AC20
AG16
AG17
+PCH_RTC_VCCSUS3_3
1 2
+DCPRRTC
CC52 0.1U_0402_10V7K
+1.05V_M
+PCH_VCCDSW
CC61 CC62 place near AE9
+1.5V_RUN
2013/06/10 refer 6L_WP chnage to float,6/14 change back
CC69 place near U8
CC72 place near AG16
CC59 and CC60 place near
J11; CC58 place near AE8
12
+3.3V_RUN
12
+1.05V_RUN
1U_0402_6.3V6K
CC72
12
CC48,CC49, CC50 place near AG10
0.1U_0402_10V7K
12
@
CC48
CC54 place near Y8
+1.05V_M
1U_0402_6.3V6K
CC61
1U_0402_6.3V6K
CC69
1U_0402_6.3V6K
12
CC58
22U_0603_6.3V6M
1
@
CC62
2
+3.3V_RUN
12
12
12
+RTC_CELL
0.1U_0402_10V7K
CC49
+1.05V_RUN
1U_0402_6.3V6K
CC59
0.1U_0402_10V7K
CC66
1U_0402_6.3V6K
12
CC50
+3.3V_M
0.1U_0402_10V7K
@
12
CC54
+PCH_VCCDSW
10U_0603_6.3V6M
12
CC60
RC211 5.11_0402_1%
CC65 place near AG19
+PCH_RTC_VCCSUS3_3 +3.3V_ALW_PCH
1U_0402_6.3V6K
12
CC73
CC73 place near AH11
VCCSUS3_3
S0 Iccmax = 63mA
12
+PCH_VCCDSW_R
1U_0402_6.3V6K
12
CC65
12
RC212 @0_0402_5%
+3.3V_ALW
12
RC213@0_0402_5%
+1.05V_MODPHY +1.05V_MODPHY_PCH
D D
+1.05V_MODPHY
C C
CC68 place near AA21
VCCAPLL
S0 Iccmax = 57mA
B B
PJP51@
1 2
PAD-OPEN1x1m
CC40 place near K9;
CC44 place near L10
CC43 place near M9
VCCHSIO
S0 Iccmax = 1.838A
LC1
1 2
2.2UH_LQM2MPN2R2NG0L_30%
CC47 place near B18
VCCUSB3PLL
S0 Iccmax = 41mA
LC2
1 2
2.2UH_LQM2MPN2R2NG0L_30%
CC56 place near B11
VCCSATA3PLL
S0 Iccmax = 42mA
LC3
1 2
2.2UH_LQM2MPN2R2NG0L_30%
CC97 place near AH10
intel DG Rev 1.2 , page 500
47.3 Boot Strap Capacitor
CC97 0.47U_0402_10V6K@
1 2
12
12
12
12
1U_0402_6.3V6K
@
CC43
+PCH_AUSB3PLL
22U_0603_6.3V6M
CC51
+PCH_ASATA3PLL+1.05V_MODPHY
22U_0603_6.3V6M
CC55
+V1.05S_APLLOPI+1.05V_RUN
100U_1206_6.3V6M
12
CC67
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
CC44
CC40
UC1M
AH14
AH13
AH10
AE20
AE21
AA21
W21
K9
L10
M9
N8
P9
B18
B11
Y20
J13
AC9
AA9
V8
W9
J18
K19
A20
J17
R21
T21
K18
M20
V21
VCCHSIO
VCCHSIO
VCCHSIO
VCC1_05
VCC1_05
VCCUSB3PLL
VCCSATA3PLL
RSVD
VCCAPLL
VCCAPLL
DCPSUS3
VCCHDA
DCPSUS2
VCCSUS3_3
VCCSUS3_3
VCCDSW3_3
VCC3_3
VCC3_3
VCCCLK
VCCCLK
VCCACLKPLL
VCCCLK
VCCCLK
VCCCLK
RSVD
RSVD
RSVD
VCCSUS3_3
VCCSUS3_3
BDW-ULT-DDR3L_BGA1168
13 OF 19
LPT LP POWER
CC64 place near V8
1U_0402_6.3V6K
12
12
CC70
12
+1.05V_MODPHY_PCH
+PCH_AUSB3PLL
+PCH_ASATA3PLL
+V1.05S_APLLOPI
+PCH_VCCDSW3_3
+PCH_VCC1P05
+PCH_VCCACLKPLL
1U_0402_6.3V6K
CC70 close to Pin J17
CC71 close to Pin R21
CC71
+3.3V_ALW_PCH
+PCH_VCC1P05+1.05V_RUN
100U_1206_6.3V6M
1U_0402_6.3V6K
12
CC77
CC78
22U_0603_6.3V6M
12
CC47
+3.3V_ALW_PCH
22U_0603_6.3V6M
CC56
12
1U_0402_6.3V6K
CC68
+PCH_VCCDSW+PCH_VCCDSW3_3
0.1U_0402_10V7K
12
+1.05V_RUN
+3.3V_ALW_PCH
CC57
22U_0603_6.3V6M
+3.3V_RUN
CC63
12
1 2
2.2UH_LQM2MPN2R2NG0L_30%
CC78 place near J18
VCCCLK
S0 Iccmax = 200mA
1U_0402_6.3V6K
@
12
CC53
CC57 place near AH14
CC63 place near AC9
22U_0603_6.3V6M
2013/06/10 refer 6L_WP chnage to +3.3V_M, 6/14 change back
12
CC64
+1.05V_RUN
LC4
1 2
RC216 0_0402_5%@
+3.3V_ALW
1 2
RC217@ 0_0402_5%
CC80 place near AH10
VCCDSW3_3
S0 Iccmax = 114mA
A A
+PCH_VCCDSW3_3+3.3V_ALW_PCH
+1.05V_RUN
1U_0402_6.3V6K
@
12
CC80
LC5
1 2
2.2UH_LQM2MPN2R2NG0L_30%
CC82 place near A20
VCCACLKPLL
S0 Iccmax = 31mA
+PCH_VCCACLKPLL
100U_1206_6.3V6M
CC81
12
1U_0402_6.3V6K
CC82
12
Reminder below power rail need isolation for layout refer
attach file for more detail that from Intel review feedback.
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (11/12)
CPU (11/12)
CPU (11/12)
LA-A961P
LA-A961P
LA-A961P
1
16 53Tuesday, October 07, 2014
16 53Tuesday, October 07, 2014
16 53Tuesday, October 07, 2014
1.0
1.0
1.0
Page 17
Vinafix.com
5
D D
4
3
2
1
BDW_ULT_DDR3L
UC1N
A11
VSS
A14
VSS
A18
VSS
A24
VSS
A28
VSS
A32
VSS
A36
VSS
A40
VSS
A44
VSS
A48
VSS
A52
VSS
A56
VSS
AA1
VSS
AA58
VSS
AB10
VSS
AB20
VSS
AB22
VSS
AB7
VSS
AC61
VSS
AD21
VSS
AD3
VSS
AD63
VSS
AE10
VSS
AE5
VSS
AE58
C C
B B
VSS
AF11
VSS
AF12
VSS
AF14
VSS
AF15
VSS
AF17
VSS
AF18
VSS
AG1
VSS
AG11
VSS
AG21
VSS
AG23
VSS
AG60
VSS
AG61
VSS
AG62
VSS
AG63
VSS
AH17
VSS
AH19
VSS
AH20
VSS
AH22
VSS
AH24
VSS
AH28
VSS
AH30
VSS
AH32
VSS
AH34
VSS
AH36
VSS
AH38
VSS
AH40
VSS
AH42
VSS
AH44
VSS
AH49
VSS
AH51
VSS
AH53
VSS
AH55
VSS
AH57
VSS
AJ13
VSS
AJ14
VSS
AJ23
VSS
AJ25
VSS
AJ27
VSS
AJ29
VSS
BDW-ULT-DDR3L_BGA1168
14 OF 19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20
AP22
AP23
AP26
AP29
AP3
AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49
AR5
AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63
AU1
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55
BDW_ULT_DDR3L
UC1O
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BDW-ULT-DDR3L_BGA1168
15 OF 19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AV59
AV8
AW16
AW24
AW33
AW35
AW37
AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31
UC1P
D33
VSS
D34
VSS
D35
VSS
D37
VSS
D38
VSS
D39
VSS
D41
VSS
D42
VSS
D43
VSS
D45
VSS
D46
VSS
D47
VSS
D49
VSS
D5
VSS
D50
VSS
D51
VSS
D53
VSS
D54
VSS
D55
VSS
D57
VSS
D59
VSS
D62
VSS
D8
VSS
E11
VSS
E17
VSS
F20
VSS
F26
VSS
F30
VSS
F34
VSS
F38
VSS
F42
VSS
F46
VSS
F50
VSS
F54
VSS
F58
VSS
F61
VSS
G18
VSS
G22
VSS
G3
VSS
G5
VSS
G6
VSS
G8
VSS
H13
VSS
BDW-ULT-DDR3L_BGA1168
16 OF 19
BDW_ULT_DDR3L
VSS_SENSE
H17
VSS
H57
VSS
J10
VSS
J22
VSS
J59
VSS
J63
VSS
K1
VSS
K12
VSS
L13
VSS
L15
VSS
L17
VSS
L18
VSS
L20
VSS
L58
VSS
L61
VSS
L7
VSS
M22
VSS
N10
VSS
N3
VSS
P59
VSS
P63
VSS
R10
VSS
R22
VSS
R8
VSS
T1
VSS
T58
VSS
U20
VSS
U22
VSS
U61
VSS
U9
VSS
V10
VSS
V3
VSS
V7
VSS
W20
VSS
W22
VSS
Y10
VSS
Y59
VSS
Y63
VSS
V58
VSS
AH46
VSS
V23
VSS
VSS
E62
AH16
VSSSENSE
VSSSENSE <45>
1 2
RC218 100_0402_1%
CAD Note: RC218 SHOULD BE PLACED CLOSE TO CPU
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (12/12)
CPU (12/12)
CPU (12/12)
LA-A961P
LA-A961P
LA-A961P
17 53Tuesday, October 07, 2014
17 53Tuesday, October 07, 2014
17 53Tuesday, October 07, 2014
1
1.0
1.0
1.0
Page 18
Vinafix.com
5
4
3
2
1
DDR_A_DQS#[0..7]<8>
DDR_A_D[0..63]<8>
DDR_A_DQS[0..7]<8>
DDR_A_MA[0..15]<8>
D D
Note:
Check voltage tolerance of
Layout Note:
Place near JDIMM1
+1.35V_MEM
1U_0402_6.3V6K
12
12
CD7
CD2
10U_0603_6.3V6M
CD12
CD13@
12
12
Layout Note:
Place near
JDIMM1.203,204
0.1U_0402_25V6
0.1U_0402_25V6
12
CD24
1U_0402_6.3V6K
10U_0603_6.3V6M
CD25
1U_0402_6.3V6K
1U_0402_6.3V6K
12
CD3
10U_0603_6.3V6M
CD14
12
0.1U_0402_25V6
12
1U_0402_6.3V6K
12
12
CD9
CD8
10U_0603_6.3V6M
10U_0603_6.3V6M
@
CD15
CD16
12
12
0.1U_0402_25V6
12
CD26
CD27
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
CD4
CD17
12
CD11
CD10
10U_0603_6.3V6M
10U_0603_6.3V6M
12
CD19
CD18
12
12
10U_0603_6.3V6M
CD28
+
10U_0603_6.3V6M
12
CD29
1U_0402_6.3V6K
12
C C
B B
A A
+1.35V_MEM
10U_0603_6.3V6M
12
+0.675V_DDR_VTT
12
VREF_DQ at the DIMM socket
330U_D3_2.5VY_R6M
CD20
1 2
RD15@ 0_0402_5%
1 2
RD16@ 0_0402_5%
+DIMM1_VREF_DQ
+3.3V_RUN
2.2U_0402_6.3V6M
0.1U_0402_25V6
12
12
CD5
DDR_CKE0_DIMMA<8>
DDR_A_BS2<8>
M_CLK_DDR0<8>
DDR_A_BS0<8>
DDR_A_WE#<8>
DDR_A_CAS#<8>
DDR_CS1_DIMMA#<8>
2.2U_0402_6.3V6M
@
12
CD31
DDR_A_D8
CD1
DDR_A_D14 DDR_A_D15
DDR_A_D10 DDR_A_D11
DDR_A_D29
DDR_A_D28
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_A_D44 DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D43
DDR_A_D47
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_CKE0_DIMMA DDR_CKE1_DIMMA
DDR_A_BS2
DDR_A_MA9
DDR_A_MA8
M_CLK_DDR0 M_CLK_DDR1
M_CLK_DDR#0 M_CLK_DDR#1
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_CS1_DIMMA#
DDR_A_D0
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D6
DDR_A_D21
DDR_A_D20
DDR_A_D17
DDR_A_D16
DDR_A_D36 DDR_A_D37
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D38
DDR_A_D62
DDR_A_D58
DDR_A_D60
DDR_A_D61
+0.675V_DDR_VTT
0.1U_0402_25V6
12
CD32
20130807 SP07000P700 CIS Link OK
5
4
H=4mm
Reverse Type
JDIMM1
1
VREF_DQ
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DM0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
DQ16
41
DQ17
43
VSS
45
DQS2#
47
DQS2
49
VSS
51
DQ18
53
DQ19
55
VSS
57
DQ24
59
DQ25
61
VSS
63
DM3
65
VSS
67
DQ26
69
DQ27
71
VSS
73
CKE0
75
VDD
77
NC
79
BA2
81
VDD
83
A12/BC#
85
A9
87
VDD
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VDD
101
CK0
103
CK0#
105
VDD
107
A10/AP
109
BA0
111
VDD
113
WE#
115
CAS#
117
VDD
119
A13
121
S1#
123
VDD
125
TEST
127
VSS
129
DQ32
131
DQ33
133
VSS
135
DQS4#
137
DQS4
139
VSS
141
DQ34
143
DQ35
145
VSS
147
DQ40
149
DQ41
151
VSS
153
DM5
155
VSS
157
DQ42
159
DQ43
161
VSS
163
DQ48
165
DQ49
167
VSS
169
DQS6#
171
DQS6
173
VSS
175
DQ50
177
DQ51
179
VSS
181
DQ56
183
DQ57
185
VSS
187
DM7
189
VSS
191
DQ58
193
DQ59
195
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
207
BOSS1
BELLW_80001-1021
CONN@
DQS0#
DQS0
DQ12
DQ13
RESET#
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQS3#
DQS3
DQ30
DQ31
CKE1
CK1#
RAS#
ODT0
ODT1
VREF_CA
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQS5#
DQS5
DQ46
DQ47
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQS7#
DQS7
DQ62
DQ63
EVENT#
GND2
BOSS2
3
+1.35V_MEM+1.35V_MEM
2
VSS
4
DQ4
DQ5
VSS
VSS
DQ6
DQ7
VSS
VSS
DM1
VSS
VSS
VSS
DM2
VSS
VSS
VSS
VSS
VSS
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
VDD
BA1
VDD
S0#
VDD
NC
VDD
VSS
VSS
DM4
VSS
VSS
VSS
VSS
VSS
VSS
DM6
VSS
VSS
VSS
VSS
VSS
SDA
SCL
VTT
DDR_A_D9
6
DDR_A_D12DDR_A_D13
8
10
DDR_A_DQS#1
12
DDR_A_DQS1
14
16
18
20
22
DDR_A_D25
24
DDR_A_D24
26
28
30
DDR3_DRAMRST#
32
34
DDR_A_D27
36
DDR_A_D26
38
40
42
DDR_A_D40DDR_A_D41
44
46
48
50
DDR_A_D42
52
DDR_A_D46
54
56
DDR_A_D52
58
DDR_A_D53
60
62
DDR_A_DQS#6
64
DDR_A_DQS6
66
68
DDR_A_D54
70
DDR_A_D55
72
74
76
78
DDR_A_MA15
80
DDR_A_MA14
82
84
DDR_A_MA11DDR_A_MA12
86
DDR_A_MA7
88
90
DDR_A_MA6
92
DDR_A_MA4DDR_A_MA5
94
96
DDR_A_MA2DDR_A_MA3
98
DDR_A_MA0DDR_A_MA1
100
102
104
106
108
DDR_A_BS1
110
DDR_A_RAS#
112
114
DDR_CS0_DIMMA#
116
M_ODT0
118
120
M_ODT1
122
124
126
128
130
DDR_A_D5
132
DDR_A_D4
134
136
138
140
DDR_A_D3
142
DDR_A_D7
144
146
DDR_A_D18
148
DDR_A_D19
150
152
DDR_A_DQS#2
154
DDR_A_DQS2
156
158
DDR_A_D22
160
DDR_A_D23
162
164
166
DDR_A_D32DDR_A_D33
168
170
172
174
DDR_A_D35
176
DDR_A_D39
178
180
DDR_A_D63
182
DDR_A_D59
184
186
DDR_A_DQS#7
188
DDR_A_DQS7
190
192
DDR_A_D56
194
DDR_A_D57
196
198
200
202
204
+0.675V_DDR_VTT
206
208
0.1U_0402_25V6
CD6@
12
CAD NOTE
PLACE THE CAP NEAR TO DIMM RESET PIN
DDR_CKE1_DIMMA <8>
M_CLK_DDR1 <8>
M_CLK_DDR#1 <8>M_CLK_DDR#0<8>
DDR_A_BS1 <8>
DDR_A_RAS# <8>
DDR_CS0_DIMMA# <8>
+SM_VREF_CA_DIMM
2.2U_0402_6.3V6M
0.1U_0402_25V6
CD22
CD23
12
12
DDR_XDP_WAN_SMBDAT <7,9,19,20>
DDR_XDP_WAN_SMBCLK <7,9,19,20>
1 2
RD3@ 0_0402_5%
+1.35V_MEM
1.8K_0402_1%
12
+DIMM1_VREF_DQ
1.8K_0402_1%
12
+5V_ALW
DDR_PG_CTRL<9>
DDR3L SODIMM ODT GENERATION
+1.35V_MEM
220K_0402_5%
12
RD9
0.675V_DDR_VTT_ON
2M_0402_5%
RD14@
1 2
QD1
L2N7002WT1G_SC-70-3
123
D
S
G
UD1
1
NC
2
A
3
GND
74AUP1G07GW_TSSOP5
+1.35V_MEM
RD4
1 2
RD5 2_0402_1%
RD6
1 2
RD10 66.5_0402_1%
1 2
RD11 66.5_0402_1%
1 2
RD12 66.5_0402_1%
1 2
RD13 66.5_0402_1%
+1.35V_MEM
5
VCC
4
Y
470_0402_5%
12
RD2
DDR3_DRAMRST#_CPU <9>DDR3_DRAMRST#<19>
0.022U_0402_16V7K
CD21
12
24.9_0402_1%
12
RD7
M_ODT0
M_ODT1
1 2
CD30@ 0.1U_0402_25V6
0.675V_DDR_VTT_ON
+SM_VREF_DQ0
M_ODT2 <19>
M_ODT3 <19>
0.675V_DDR_VTT_ON <42>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDR3L
DDR3L
DDR3L
LA-A961P
LA-A961P
LA-A961P
1
18 53Tuesday, October 07, 2014
18 53Tuesday, October 07, 2014
18 53Tuesday, October 07, 2014
1.0
1.0
1.0
Page 19
Vinafix.com
5
4
3
2
1
H=4mm
+DIMM2_VREF_DQ
DDR_B_DQS#[0..7]<8>
DDR_B_D[0..63]<8>
DDR_B_DQS[0..7]<8>
+1.35V_MEM
1U_0402_6.3V6K
12
+1.35V_MEM
10U_0603_6.3V6M
12
+0.675V_DDR_VTT
DDR_B_MA[0..15]<8>
Layout Note:
Place near JDIMM2
1U_0402_6.3V6K
12
12
CD38
CD39
10U_0603_6.3V6M
CD47@
CD46@
12
12
Layout Note:
Place near
JDIMM2.203,204
0.1U_0402_25V6
CD58
CD57
12
12
1U_0402_6.3V6K
12
CD41
CD40
10U_0603_6.3V6M
10U_0603_6.3V6M
CD48
12
0.1U_0402_25V6
0.1U_0402_25V6
CD59
12
1U_0402_6.3V6K
12
CD37
10U_0603_6.3V6M
CD45
12
0.1U_0402_25V6
12
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
12
10U_0603_6.3V6M
CD49
12
10U_0603_6.3V6M
CD60
12
1U_0402_6.3V6K
12
12
CD43
CD42
CD50
CD61
CD44
10U_0603_6.3V6M
10U_0603_6.3V6M
12
CD52
CD51
12
12
12
+
10U_0603_6.3V6M
CD62
D D
C C
B B
A A
330U_D3_2.5VY_R6M
CD53
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
+3.3V_RUN
RD27@ 0_0402_5%
+3.3V_RUN
12
2.2U_0402_6.3V6M
12
0.1U_0402_25V6
12
CD33
CD34
DDR_CKE2_DIMMB<8>
DDR_B_BS2<8>
M_CLK_DDR2<8>
M_CLK_DDR#2<8>
DDR_B_BS0<8>
DDR_B_WE#<8>
DDR_B_CAS#<8>
DDR_CS3_DIMMB#<8>
12
0_0402_5%
RD28@
2.2U_0402_6.3V6M
12
+1.35V_MEM +1.35V_MEM
DDR_B_D8 DDR_B_D9
DDR_B_D14
DDR_B_D10
DDR_B_D11
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D26
DDR_B_D27
DDR_B_D40
DDR_B_D41
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D42
DDR_B_D56
DDR_B_D57
DDR_B_D59
DDR_B_D58
DDR_CKE2_DIMMB DDR_CKE3_DIMMB
DDR_B_BS2
DDR_B_MA9
DDR_B_MA8
M_CLK_DDR2 M_CLK_DDR3
M_CLK_DDR#2 M_CLK_DDR#3
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_B_D4
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D3
DDR_B_D7
DDR_B_D21
DDR_B_D20
DDR_B_D22
DDR_B_D23
DDR_B_D36 DDR_B_D37
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D35
DDR_B_D39
DDR_B_D52
DDR_B_D49
DDR_B_D48
DDR_B_D53
+0.675V_DDR_VTT
0.1U_0402_25V6
@
12
CD64
CD63
Reverse Type
JDIMM2
1
VREF_DQ
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DM0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
DQ16
41
DQ17
43
VSS
45
DQS2#
47
DQS2
49
VSS
51
DQ18
53
DQ19
55
VSS
57
DQ24
59
DQ25
61
VSS
63
DM3
65
VSS
67
DQ26
69
DQ27
71
VSS
73
CKE0
75
VDD
77
NC
79
BA2
81
VDD
83
A12/BC#
85
A9
87
VDD
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VDD
101
CK0
103
CK0#
105
VDD
107
A10/AP
109
BA0
111
VDD
113
WE#
115
CAS#
117
VDD
119
A13
121
S1#
123
VDD
125
TEST
127
VSS
129
DQ32
131
DQ33
133
VSS
135
DQS4#
137
DQS4
139
VSS
141
DQ34
143
DQ35
145
VSS
147
DQ40
149
DQ41
151
VSS
153
DM5
155
VSS
157
DQ42
159
DQ43
161
VSS
163
DQ48
165
DQ49
167
VSS
169
DQS6#
171
DQS6
173
VSS
175
DQ50
177
DQ51
179
VSS
181
DQ56
183
DQ57
185
VSS
187
DM7
189
VSS
191
DQ58
193
DQ59
195
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
207
BOSS1
BELLW_80001-1021
CONN@
DQS0#
DQS0
DQ12
DQ13
RESET#
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQS3#
DQS3
DQ30
DQ31
CKE1
CK1#
RAS#
ODT0
ODT1
VREF_CA
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQS5#
DQS5
DQ46
DQ47
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQS7#
DQS7
DQ62
DQ63
EVENT#
GND2
BOSS2
2
VSS
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
DDR_B_D12
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D13
DDR_B_D15
DDR_B_D25
DDR_B_D24
DDR3_DRAMRST#
DDR_B_D30
DDR_B_D31
DDR_B_D45
DDR_B_D44
DDR_B_D47
DDR_B_D43
DDR_B_D61
DDR_B_D60
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D63
DDR_B_D62
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11DDR_B_MA12
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4DDR_B_MA5
DDR_B_MA2DDR_B_MA3
DDR_B_MA0DDR_B_MA1
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
DDR_B_D5
DDR_B_D0DDR_B_D1
DDR_B_D2
DDR_B_D6
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D19
DDR_B_D18
DDR_B_D32DDR_B_D33
DDR_B_D34
DDR_B_D38
DDR_B_D51
DDR_B_D55
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D54
DDR_B_D50
+0.675V_DDR_VTT
DDR3_DRAMRST# <18>
0.1U_0402_25V6
12
CD35@
CAD NOTE
PLACE THE CAP NEAR TO DIMM RESET PIN
DDR_CKE3_DIMMB <8>
M_CLK_DDR3 <8>
M_CLK_DDR#3 <8>
DDR_B_BS1 <8>
DDR_B_RAS# <8>
DDR_CS2_DIMMB# <8>
M_ODT2 <18>
M_ODT3 <18>
+SM_VREF_CA_DIMM
2.2U_0402_6.3V6M
0.1U_0402_25V6
CD55
12
12
DDR_XDP_WAN_SMBDAT <7,9,18,20>
DDR_XDP_WAN_SMBCLK <7,9,18,20>
+1.35V_MEM
1.8K_0402_1%
12
RD18
+SM_VREF_CA+SM_VREF_CA_DIMM
1 2
RD19 2_0402_1%
1.8K_0402_1%
12
RD20
+1.35V_MEM
1.8K_0402_1%
12
+DIMM2_VREF_DQ
CD56
RD22
1 2
RD23 2_0402_1%
1.8K_0402_1%
12
RD24
0.022U_0402_16V7K
CD36
12
24.9_0402_1%
12
RD21
+SM_VREF_DQ1
0.022U_0402_16V7K
CD54
12
24.9_0402_1%
12
RD25
DQ4
DQ5
VSS
VSS
DQ6
DQ7
VSS
VSS
DM1
VSS
VSS
VSS
DM2
VSS
VSS
VSS
VSS
VSS
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
VDD
BA1
VDD
S0#
VDD
NC
VDD
VSS
VSS
DM4
VSS
VSS
VSS
VSS
VSS
VSS
DM6
VSS
VSS
VSS
VSS
VSS
SDA
SCL
VTT
20130807 SP07000P700 CIS Link OK
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDR3L
DDR3L
DDR3L
LA-A961P
LA-A961P
LA-A961P
1
19 53Tuesday, October 07, 2014
19 53Tuesday, October 07, 2014
19 53Tuesday, October 07, 2014
1.0
1.0
1.0
Page 20
Vinafix.com
5
4
3
2
1
D D
SATA_PTX_DRX_P1<6>
SATA_PTX_DRX_N1<6>
SATA_PRX_DTX_N1<6>
SATA_PRX_DTX_P1<6>
1 2
CN38 0.01U_0402_16V7K
1 2
CN37 0.01U_0402_16V7K
1 2
CN36 0.01U_0402_16V7K
1 2
CN35 0.01U_0402_16V7K
SATA_PTX_DRX_P1_RP_C
SATA_PTX_DRX_N1_RP_C
SATA_PRX_DTX_N1_RP_C
SATA_PRX_DTX_P1_RP_C
Bypass SATA Repeater
+5V_HDD
100K_0402_5%
12
RN1@
FFS_INT2_Q
DMN66D0LDW-7_SOT363-6
34
QN1B
5
QN1A
HDD_FALL_INT<6,10>
DDR_XDP_WAN_SMBDAT<7,9,18,19>
DDR_XDP_WAN_SMBCLK<7,9,18,19>
12
FFS_INT2
FFS_INT2
+3.3V_RUN
100K_0402_5%
RN2
2
12
DMN66D0LDW-7_SOT363-6
6
1
C C
+3.3V_RUN
1 2
1 2
1 2
DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK
FFS_INT2<12>
HDD_DEVSLP
RN3 2.2K_0402_5%
RN4 2.2K_0402_5%
+3.3V_HDD
RN5@ 10K_0402_5%
+3.3V_RUN
0.1U_0402_25V6
10U_0603_6.3V6M
12
CN1
Free Fall Sensor
CN2
11
UN1
LNG3DM
1
9
7
6
4
8
LNG3DMTR_LGA16_3X3
RES
VDD_IO
RES
VDD14RES
RES
INT 1
GND
INT 2
GND
SDO/SA0
SDA / SDI / SDO
SCL/SPC
CS
NC
NC
10
13
15
16
5
12
2
3
B B
A A
+5V_HDD +3.3V_HDD
0.1U_0402_25V6
1000P_0402_50V7K
CN14
CN13
12
12
12
Place near HDD CONN
JSATA1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
GND1
18
18
GND2
19
19
GND3
20
20
GND4
E-T_0870K-F20C-22L
CONN@
21
22
23
24
HDD_DET#<6>
SATA_PTX_DRX_P1_RP_C
SATA_PTX_DRX_N1_RP_C
SATA_PRX_DTX_N1_RP_C
SATA_PRX_DTX_P1_RP_C
+3.3V_HDD
HDD_DET#
+5V_HDD
FFS_INT2_Q
0.1U_0402_25V6
0.1U_0402_25V6
CN16
@
12
CN15
HDD_DEVSLP<12>
PJP5@
+5V_RUN
1 2
PAD-OPEN1x1m
20131025 link SP01001GG00
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
HDD CONN
HDD CONN
HDD CONN
LA-A961P
LA-A961P
LA-A961P
20 53Tuesday, October 07, 2014
20 53Tuesday, October 07, 2014
20 53Tuesday, October 07, 2014
1
1.0
1.0
1.0
Page 21
Vinafix.com
2
1
1W x 1ch, 4ohm (Transducer spec is 8Ohm/0.5Watt per unit, there are two transducer units in one speaker box.)
Internal Speakers Header
40 mils trace keep 20 mil spacing
INT_SPK_L+
INT_SPK_LINT_SPK_R+
INT_SPK_R-
1000P_0402_50V7K
1000P_0402_50V7K
12
12
CA22@EMC@
B B
Close to UA1
1 2
LA6 BLM15PX330SN1D_2PEMC@
1 2
LA7 BLM15PX330SN1D_2PEMC@
1 2
LA8 BLM15PX330SN1D_2PEMC@
1 2
LA9 BLM15PX330SN1D_2PEMC@
1000P_0402_50V7K
1000P_0402_50V7K
12
12
CA23@EMC@
CA24@EMC@
CA19@EMC@
INT_SPKR_L+
INT_SPKR_LINT_SPKR_R+
INT_SPKR_R+
INT_SPKR_R-
L03ESDL5V0CC3-2_SOT23-3
2
2
3
3
DA6@EMC@
1
1
CONN@
JSPK1
1
1
2
2
3
3
4
4
5
GND1
6
L03ESDL5V0CC3-2_SOT23-3
GND2
E-T_4280K-F04N-05L
DA7@EMC@
20130726 CIS Link OK
Close to UA1 pin6
PCH_AZ_CODEC_BITCLK
@EMC@
33_0402_5%
12
RA17
15P_0402_50V8J
12
CA33@EMC@
Verb table configures as 1 JD mode with
Place closely to Pin 13.
Place closely to Pin 14 for DOCK only
A A
DMN66D0LDW-7_SOT363-6
AUD_SENSE_A
AUD_SENSE_B
+3.3V_RUN_AUDIO +3.3V_RUN_AUDIO
100K_0402_5%
12
RA29
2
QA3A
internal 47K pull high to save external rBOM.
13
D
2
QA1
G
S
L2N7002WT1G_SC-70-3
100K_0402_5%
12
RA28
6
1
12
1 2
RA38 100K_0402_5%
200K_0402_5%
12
RA27
100K_0402_5%
12
34
5
QA3B
DMN66D0LDW-7_SOT363-6
0.1U_0402_25V6
CA41
@
RA26
BCLK: Audio serial data bus bit clock input/output
LRCK: Audio serial data bus word clock input/output
AUD_NB_MUTE#<35>
+3.3V_RUN_AUDIO
AUD_HP_NB_SENSE <32,35>
Add for solve
pop noise and
detect issue
+3.3V_RUN_AUDIO
DOCK_MIC_DET <35>DOCK_HP_DET<35>
Digital Mic (Goliad MLK no single Mic)
2
+3.3V_RUN_AUDIO
PCH_AZ_CODEC_BITCLK<6>
PCH_AZ_CODEC_SDOUT<6>
PCH_AZ_CODEC_SYNC<6>
PCH_AZ_CODEC_SDIN0<6>
PCH_AZ_CODEC_RST#<6>
DAI_12MHZ#<34>
DAI_BCLK#<34>
DAI_DO#<34>
DAI_LRCK#<34>
DAI_DI<34>
1 2
RA18 10K_0402_5%
place at AGND and DGND plane
CA11 close to pin9
CA10 close to pin3
0.1U_0402_25V6
CA11
CA10
12
12
Place RA9 close to UA1
1 2
RA9 33_0402_5%
1 2
RA30EMC@ 22_0402_5%
1 2
RA31EMC@ 22_0402_5%
1 2
RA32 33_0402_5%
1U_0603_10V6K
12
CA31
1 2
@EMC@
RA35
0_0402_5%
1 2
@EMC@
RA36
0_0402_5%
1 2
@EMC@
RA37
0_0402_5%
SLEEVE
+RTC_CELL
34
5
QA2A
0.1U_0402_25V6
CA50
12
100K_0402_5%
12
RA21
6
1
DMN66D0LDW-7_SOT363-6
4.7U_0603_6.3V6K
12
AUD_NB_MUTE#
QA2B
DMN66D0LDW-7_SOT363-6
Realtek feedback
Prevent the Noise from Combo Jack
while system entry into S3 / S4 /S5
100K_0402_5%
2
I2S_MCLK
I2S_BCLK
I2S_DO
RA44
EN_I2S_NB_CODEC#<35>
PCH_AZ_CODEC_BITCLK
PCH_AZ_CODEC_SDOUT
PCH_AZ_SDIN0_R
PCH_AZ_CODEC_RST#
Place RA32 close to codec
CA51
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
12
12
1 2
PAD-OPEN1x2m
AUD_NB_MUTE#
CA52
MIC1_L
MIC1_R
12
PJP6@
CA53
4.7U_0603_6.3V6K
UA1
1
I2S I/F Float
3
DVDD_IO
9
DVDD
6
BCLK
5
SDATA-OUT
10
SYNC
8
SDATA-IN
11
RESET#
15
I2S_MCLK
16
I2S_SCLK
17
I2S_DOUT
18
I2S_LRCK
24
I2S_DIN
19
MIC1-L(PORT-B-L)
20
MIC1-R(PORT-B-R)
48
EAPD+PD
21
LDO1-CAP
39
LDO2-CAP
7
LDO3-CAP
49
GND
ALC3235-CG_MQFN48_6X6
AVDD1
AVDD2
CPVDD
PVDD1
PVDD2
HP/MIC1 JD(JD1)
I2S_IN/I2S_OUT JD(JD2)
TV Mode/LINE1-JD (JD3)
LINE1-L(PORT-C-L)/RING2
LINE1-R(PORT-C-R)/SLEEVE
LINE1-VREFO
MIC-CAP
HPOUT-L(PORT-A-L)
HPOUT-R(PORT-A-R)
SPK-OUT-L+
SPK-OUT-L-
SPK-OUT-R+
SPK-OUT-R-
PCBEEP
GPIO0/DMIC-CLK
GPIO1/DMIC-DATA12
SPDIF-OUT/DMIC-DATA34/GPIO2
CBN
CBP
CPVEE
VREF
MIC1-VREFO
AVSS1
AVSS2
CA43
1 2
MIC1_L
4.7U_0603_6.3V6K
CA44
1 2
MIC1_R
4.7U_0603_6.3V6K
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
place close to pin27
+VDDA_AVDD1
0.1U_0402_25V6
12
CA8
27
40
38
+VDDA_PVDD
41
46
+5V_RUN_PVDD
13
AUD_SENSE_A
14
AUD_SENSE_B
1 2
22
RA45 0_0402_5%@
28
RING2
29
SLEEVE
23
31
33
32
42
43
45
44
12
2
4
47
35
36
34
25
30
26
37
1 2
CA25 10U_0603_6.3V6M
AUD_OUT_L
AUD_OUT_R
RA7 24.9_0402_1%
RA8 24.9_0402_1%
INT_SPK_L+
INT_SPK_L-
INT_SPK_R+
INT_SPK_R-
AUD_PC_BEEP
DMIC_CLK_L
GMLK no single MIC
Place CA29 close to Codec
12
CA29 1U_0603_10V6K
12
12
CA49 1U_0603_10V6K
CA35
+MIC1_VREF_OUT
1 2
10U_0603_6.3V6M
BLM15PX600SN1D_2P
12
CA9
place close to pin40
For Bo noise issue
+3.3V_RUN_AUDIO
SLEEVE/RING2 please keep 40 mils trace width
RING2 <32>
SLEEVE <32>
1 2
1 2
place close to pin12
12
CA27 0.1U_0402_25V6
12
CA28 0.1U_0402_25V6
1 2
RA14EMC@ 33_0402_5%
2.2U_0402_6.3V6M
RB751S40T1G_SOD523-2
RB751S40T1G_SOD523-2
21
21
DA4
4.7K_0402_5%
4.7K_0402_5%
RA24
RA25
1 2
1 2
AUD_HP_OUT_L
AUD_HP_OUT_R
DMIC_CLK
DA5
+5V_RUN_AUDIO +1.5V_RUN
LA5
4.7U_0603_6.3V6K
1
2
+VREFOUT
AUD_HP_OUT_L
AUD_HP_OUT_R
+1.5V_RUN_AUDIO
place close to pin38
CA16
AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width
0.1U_0402_25V6
1
12
CA17
2
AUD_HP_OUT_L <32>
AUD_HP_OUT_R <32>
1 2
RA12 1K_0402_5%
1 2
RA13 1K_0402_5%
DMIC_CLK <23>
DMIC0 <23>
4.7U_0603_6.3V6K
CA18
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
1
Date: Sheet of
12
SPKR <12>
BEEP <36>
+5V_RUN +5V_RUN_AUDIO
+3.3V_RUN +3.3V_RUN_AUDIO
HP-Out-Left
+3.3V_RUN_AUDIO
12
0_0603_5%
RA3@
place close to pin41 place close to pin46
0_0603_5%
RA4@
0.1U_0402_25V6
12
CA45
0.1U_0402_25V6
10U_0603_6.3V6M
1
12
CA46
CA47
2
1 2
RING2
1 2
SLEEVE
+VREFOUT
DMIC_CLK
place close to pin2
PJP9@
1 2
PAD-OPEN1X2m
PJP10@
1 2
PAD-OPEN1x1m
HP-Out-Right Nokia-MIC
Global Headset
Combo Jack
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Codec _ALC3235
Codec _ALC3235
Codec _ALC3235
LA-A961P
LA-A961P
LA-A961P
+5V_RUN_AUDIO
0_0805_5%
12
RA39@
10U_0603_6.3V6M
1
CA48
2
1U_0603_10V4Z
12
22P_0402_50V8J
12
iPhone-MIC
21 53Tuesday, October 07, 2014
21 53Tuesday, October 07, 2014
21 53Tuesday, October 07, 2014
+VREFOUT
RA52.2K_0402_5%
RA62.2K_0402_5%
@
CA26
@EMC@
CA30
1.0
1.0
1.0
Page 22
Vinafix.com
2
1
+1.05V_RUN_VMM
LV22
1 2
BLM15PX181SN1D_2P
+1.05V_RUN_VMM
LV23
1 2
BLM15PX181SN1D_2P
B B
+3.3V_RUN_VMM
LV24
1 2
BLM15PX181SN1D_2P
+1.05V_VMM_VDD
12
12
+1.05V_VMM_VDDTX
0.1U_0402_25V6
10U_0603_6.3V6M
CV90
12
12
+3.3V_RUN_VDDIO
12
10U_0603_6.3V6M
1U_0603_10V6K
CV91
10U_0603_6.3V6M
CV82
CV87
12
CV94
0.1U_0402_25V6
12
0.1U_0402_25V6
12
0.01U_0402_16V7K
CV92
0.1U_0402_25V6
12
0.1U_0402_25V6
12
CV84
CV83
0.01U_0402_16V7K
12
CV88
CV89
0.01U_0402_16V7K
CV93
12
0.01U_0402_16V7K
12
CV96
CV95
+3.3V_RUN_VDDA
0.01U_0402_16V7K
0.01U_0402_16V7K
12
12
CV85
0.01U_0402_16V7K
12
CV97
CV86
UV8B
E6
VDD
E7
VDD
E8
VDD
E9
VDD
H6
VDD
H7
VDD
H8
VDD
H9
VDD
E3
VDDRX
G3
VDDRX
C8
VDDTX0
C9
VDDTX0
F12
VDDTX1
G12
VDDTX1
J3
VDDLP
E5
VDDLP
H3
NC
F3
VDDRXA1
D3
VDDRX
E10
NC
C7
VDDTX0A1
C6
VDDTX0A2
H11
NC
E12
VDDTX1A1
D12
VDDTX1A2
J10
VGA_AVDD
K8
VGA_AVDD
K9
VGA_AVDD
K10
VGA_AVDD
J2
VDDSA
C3
VDDHRX_33
C4
VDDHRX_33
C11
VDDHTX0_33
C12
VDDIO
K3
VDDIO
K4
VDDIO
K11
VDDIO
K12
VDDIO
J4
VDDXT3V
VMM3320BJGR_BGA168
3.3V Analog
1V Digital 1 V Analog 3.3V IO
VDDRX_33
VDDTX0_33
VDDTX1_33
VGA_AVDD33
VGA_AVDD33
VGA_AVSS
VGA_AVSS
VGA_AVSS
VGA_AVSS
VGA_AVSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Goliad MLK should be use DOCKED to control TPS22966
Huston 14"/15" use jumper
+1.05V_RUN
DOCKED<28,31,35>
+5V_ALW
A A
DOCKED
+3.3V_RUN
+1.05V_RUN +1.05V_RUN_VMM
1 2
PAD-OPEN1x1m
+3.3V_RUN +3.3V_RUN_VMM
1 2
PAD-OPEN1x1m
1
2
3
4
5
6
TPS22966DPUR_SON14_2X3
PJP24@
PJP25@
UV13
VIN1
VIN1
ON1
VBIAS
ON2
VIN2
VIN27VOUT2
VOUT1
VOUT1
VOUT2
GPAD
CT1
GND
CT2
14
+1.05V_VMM_UV10
13
12
11
10
9
8
+3.3V_VMM_UV10
15
+1.05V_RUN_VMM
12
PJP28
PAD-OPEN1x1m
@
1 2
CV518 0.1U_0402_10V7K
1 2
CV116 470P_0402_50V7K
1 2
CV117 470P_0402_50V7K
1 2
PAD-OPEN1x1m
0.1U_0402_10V7K
CV118
1 2
PJP27@
+3.3V_RUN_VDDA +3.3V_RUN_VMM
H5
C10
H12
K6
K7
C5
D5
D6
D7
D8
D9
D10
D11
E4
E11
F4
F5
F6
F7
F8
F9
F10
F11
G4
G5
G6
G7
G8
G9
G10
G11
H4
D4
J5
J11
J12
K5
H10
J6
J7
J8
J9
+3.3V_RUN_VMM
DOCKED
0.01U_0402_16V7K
0.01U_0402_16V7K
CV98
+3.3V_ALW
2
0.1U_0402_25V6
12
12
CV99
CV100
12
100K_0402_5%
@
12
RV701
DOCKED#
DMN66D0LDW-7_SOT363-6
6
@
QV700A
1
12
LV25
1 2
BLM15PX181SN1D_2P
10U_0603_6.3V6M
12
CV101
+3.3V_RUN_VMM
27MHZ_12PF_X1E000021042600
22P_0402_50V8J
CV115
+3.3V_RUN_VMM
5
UV8A
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
VMM2320_HPD<26>
PLTRST_VMM2320#<9>
VMM2320_P0<26>
VMM2320_N0<26>
VMM2320_P1<26>
VMM2320_N1<26>
VMM2320_P2<26>
VMM2320_N2<26>
VMM2320_P3<26>
VMM2320_N3<26>
VMM2320_AUX<26>
VMM2320_AUX#<26>
12
VMM_GPIO9
RV731M_0402_5% @
12
SW_DPC_AUX
RV741M_0402_5%
12
SW_DPB_AUX
RV751M_0402_5%
12
RED_DOCK
RV76150_0402_1%
12
GREEN_DOCK
RV77150_0402_1%
12
BLUE_DOCK
RV78150_0402_1%
12
LP_CTL
RV79@100K_0402_5%
12
LP_CTL
RV5162.2K_0402_5% @
YV2
1
3
IN
OUT
2
4
GND
GND
RV81 2.2K_0402_5%
18P_0402_50V8J
12
CV113
EEPROM
UV9
VMM_SPI_CS#
VMM_SPI_DIN
VMM_SPI_WP#
10_0402_5%
@
12
RV702
DMN66D0LDW-7_SOT363-6
34
@
QV700B
1
CS#
2
DO(IO1)
HOLD#(IO3)
3
WP#(IO2)
GND4DI(IO0)
W25X10CVSNIG_SO8
1M_0402_5%
12
RV80
VCC
CLK
VMM2320_P0_C
CV1020.1U_0402_10V7K
VMM2320_N0_C
CV1030.1U_0402_10V7K
VMM2320_P1_C
CV1040.1U_0402_10V7K
VMM2320_N1_C
CV1050.1U_0402_10V7K
VMM2320_P2_C
CV1060.1U_0402_10V7K
VMM2320_N2_C
CV1070.1U_0402_10V7K
VMM2320_P3_C
CV1080.1U_0402_10V7K
VMM2320_N3_C
CV1090.1U_0402_10V7K
VMM2320_AUX_C
CV1100.1U_0402_10V7K
VMM2320_AUX#_C
CV1110.1U_0402_10V7K
SRCDET
+3.3V_RUN_VDDIO
VMM_SPI_WP#
VMM_SPI_CS#
VMM_SPI_CLK
VMM_SPI_DIN
VMM_SPI_DO
VMM_GPIO4
VMM_GPIO5
VMM_GPIO6
VMM_GPIO7
VMM_GPIO8
VMM_GPIO9
LP_CTL
+3.3V_RUN_VMM
8
7
VMM_SPI_HOLD
6
VMM_SPI_CLK
5
VMM_SPI_DO
CLK_27M_IN
CLK_27M_OUT
CV114
1 2
0.1U_0402_25V6
G1
RxP0
G2
RxN0
F1
RxP1
F2
RxN1
E1
RxP2
E2
RxN2
D1
RxP3
D2
RxN3
H1
RxAUXP
H2
RXAUXN
C2
RxSRCDET
J1
RxHPD
A13
RSTN_IN
B5
VDDIO
B6
VDDIO
B1
NC
A4
SPICS
B3
SPICLK
B4
SPIDI
A3
SPIDO
D14
GPIO0
D13
GPIO1
C14
GPIO2
C13
GPIO3
B14
GPIO4
B13
GPIO5
C1
GPIO6
M12
GPIO7
M13
NC
L3
NC
B2
LP_CTL
A5
LP_EN
K2
RX_STS
L2
TX0_STS
M1
TX1_STS
M2
TX2_STS
K1
XIN
L1
XOUT
VMM3320BJGR_BGA168
Tx0P0
Tx0N0
Tx0P1
Tx0N1
Tx0P2
Tx0N2
Tx0P3
Tx0N3
CAD0
Tx0AUXP
Tx0AUXN
Tx0DDCSCL
Tx0DDCSDA
Tx0HPD
Tx1P0
Tx1N0
Tx1P1
Tx1N1
Tx1P2
Tx1N2
Tx1P3
Tx1N3
CAD1
Tx1AUXP
Tx1AUXN
Tx1DDCSCL
Tx1DDCSDA
Tx1HPD
VGA_VSYNC
VGA_HSYNC
VGA_RP
VGA_RN
VGA_GP
VGA_GN
VGA_BP
VGA_BN
VGA_SCL
VGA_SDA
VGA_DET
VGA_IREF
SSDA
SSCL
RxDDCSDA
RxDDCSCL
NC
NC
NC
NC
NC
B7
A7
B8
A8
B9
A9
B10
A10
A14
B11
SW_DPC_AUX
A11
SW_DPC_AUX#
B12
VMM_DPC_CTRLCLK
A12
VMM_DPC_CTRLDAT
A6
E13
E14
F13
F14
G13
G14
H13
H14
M14
J13
SW_DPB_AUX
J14
SW_DPB_AUX#
K13
VMM_DPB_CTRLCLK
L14
VMM_DPB_CTRLDAT
K14
L9
M9
M6
L6
M7
L7
M8
L8
L4
M4
M3
VMM2320_VGA_DET
M5
VMM2320_VGA_IREF
L5
VMM2320_VGA_NC
A1
I2C1_SDA_VMM
A2
I2C1_SCL_VMM
M11
M10
L12
L13
L11
L10
VMM_SPI_WP#
VMM_GPIO4
VMM_GPIO5
VMM_GPIO8
VMM_GPIO7
SW_DPB_AUX#
VMM_GPIO6
SRCDET
VMM_DPB_CTRLDAT
VMM_DPB_CTRLCLK
I2C1_SDA_VMM
I2C1_SCL_VMM
VMM_DPC_CTRLDAT
VMM_DPC_CTRLCLK
SW_DPC_AUX#
VMM_SPI_CS#
VMM_SPI_HOLD
VMM2320_VGA_DET
VMM2320_VGA_IREF
DPC_LANE_P0 <34>
DPC_LANE_N0 <34>
DPC_LANE_P1 <34>
DPC_LANE_N1 <34>
DPC_LANE_P2 <34>
DPC_LANE_N2 <34>
DPC_LANE_P3 <34>
DPC_LANE_N3 <34>
DPC_CA_DET <26,34>
SW_DPC_AUX <26>
SW_DPC_AUX# <26>
VMM_DPC_CTRLCLK <26>
VMM_DPC_CTRLDAT <26>
DPC_DOCK_HPD <34>
DPB_LANE_P0 <34>
DPB_LANE_N0 <34>
DPB_LANE_P1 <34>
DPB_LANE_N1 <34>
DPB_LANE_P2 <34>
DPB_LANE_N2 <34>
DPB_LANE_P3 <34>
DPB_LANE_N3 <34>
DPB_CA_DET <26,34>
SW_DPB_AUX <26>
SW_DPB_AUX# <26>
VMM_DPB_CTRLCLK <26>
VMM_DPB_CTRLDAT <26>
DPB_DOCK_HPD <34>
VSYNC_DOCK <34>
HSYNC_DOCK <34>
RED_DOCK <34>
GREEN_DOCK <34>
BLUE_DOCK <34>
CLK_DDC2_DOCK <34>
DAT_DDC2_DOCK <34>
T108@ PAD~D
+3.3V_RUN_VMM
12
RV517 @2.2K_0402_5%
12
RV518 @2.2K_0402_5%
12
RV519 @2.2K_0402_5%
1 2
RV14 2.2K_0402_5%
1 2
RV15 2.2K_0402_5%
1 2
RV821M_0402_5%
1 2
RV832.2K_0402_5%
1 2
RV841M_0402_5%
RPV1
1
8
2
7
3
6
4 5
2.2K_0804_8P4R_5%
RPV2
1
8
2
7
3
6
4 5
2.2K_0804_8P4R_5%
1 2
RV851M_0402_5%
12
RV8610K_0402_5%
12
RV872.2K_0402_5%
12
RV8810K_0402_5%
1 2
RV893.74K_0402_1%
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
DP 1.2 MST HUB
DP 1.2 MST HUB
DP 1.2 MST HUB
LA-A961P
LA-A961P
LA-A961P
22 53Tuesday, October 07, 2014
22 53Tuesday, October 07, 2014
22 53Tuesday, October 07, 2014
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
2
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Page 23
Vinafix.com
5
CONN@
20130808 link OK
D D
C C
+BL_PWR_SRC +5V_RUN+5V_RUN +5V_TSP
JEDP1
41
G1
42
G2
43
G3
44
G4
45
G5
ACES_50398-04041-001
0.1U_0603_50V7K
12
@
CV7
+5V_TSP
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
USBP5_D-
13
USBP5_D+
14
15
16
pin15 connect to GND (loopback)
17
18
19
20
21
22
DISP_ON
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
+LCDVDD
0.1U_0402_25V6
12
TOUCH_PANEL_INTR# <6,12>
+3.3V_RUN
+3.3V_CAM
CAM_MIC_CBL_DET# <10,12>
+BL_PWR_SRC
1 2
LV1
EMC@
EDP_CPU_HPD <10>
LCD_TST <35>
+LCDVDD
EDP_CPU_AUX#_C
EDP_CPU_AUX_C
EDP_CPU_LANE_P0_C
EDP_CPU_LANE_N0_C
EDP_CPU_LANE_P1_C
EDP_CPU_LANE_N1_C
LCD_CBL_DET# <12>
+3.3V_CAM +5V_TSP
@
CV8
BIA_PWM
BLM15BB221SN1D_2P~D
CV1 0.1U_0402_10V7K
CV2 0.1U_0402_10V7K
CV3 0.1U_0402_10V7K
CV4 0.1U_0402_10V7K
CV5 0.1U_0402_10V7K
CV6 0.1U_0402_10V7K
0.1U_0402_25V6
12
@
CZ1
4
AZC199-02SPR7G_SOT23-3
2
DMIC0 <21>
DMIC_CLK <21>
100P_0402_50V8J
100P_0402_50V8J
12
12
CA5@EMC@
CA6@EMC@
3
@EMC@
DV4
1
ESD depop location
3
USBP4_DUSBP4_D+
LV27
EMC@
4
4
1
1
DLW21HN900HQ2L_4P
2
3
3
2
2
USBP4- <11>
USBP4+ <11>
1
LED CONN
JLED1
+5V_ALW
BATT_WHITE_LED#<39>
BATT_YELLOW_LED#<39>
PANEL_HDD_LED#<39>
BREATH_WHITE_LED#<39>
1
1
2
2
3
3
4
4
5
5
6
6
7
GND
8
GND
E-T_4260K-Q06N-23L
CONN@
20130726 same as Goliad
12
12
12
12
12
12
EDP_CPU_AUX# <10>
EDP_CPU_AUX <10>
EDP_CPU_LANE_P0 <10>
EDP_CPU_LANE_N0 <10>
EDP_CPU_LANE_P1 <10>
EDP_CPU_LANE_N1 <10>
For Touchscreen
0.1U_0402_16V4Z
12
CZ2
+3.3V_RUN
0.1U_0402_25V6
@
12
@
CA7
47K_0402_5%
12
RV6
QV8
LP2301ALT1G_SOT23-3
123
D
S
G
Close to JEDP1.24~27
BIA_PWM
4.7K_0402_5%
12
RV1
B B
Close to JEDP1.11,12
DV1
3
1
2
BAT54CW_SOT323-3
WebCAM
+3.3V_CAM +3.3V_RUN
3.3V_CAM_EN#<12>
change back to CCD_OFF at Goliad project
USBP5+<11>
A A
LZ1 EMC@
1
1
4
4
DLW21HN900HQ2L_4P
Close to JEDP1.33 Close to JEDP1.40 Close to JEDP1.1
EDP_BIA_PWM
BIA_PWM_EC
LP2301ALT1G_SOT23-3
2
3
QZ1
123
D
2
3
EDP_BIA_PWM <10>
BIA_PWM_EC <36>
S
G
USBP5_D+
USBP5_D-
L2N7002WT1G_SC-70-3
13
DV2
3
DISP_ON
4.7K_0402_5%
12
RV2
+PWR_SRC
1000P_0402_50V7K
12
CV11
1
BAT54CW_SOT323-3
S
4 5
270K_0402_5%
12
RV4
PWR_SRC_ON
1 2
RV5 47K_0402_5%
EN_INVPWR<36>USBP5-<11>
2
QV1
G
AO6405_TSOP6
3
L2N7002WT1G_SC-70-3
D
6
2
1
QV2
123
D
PANEL_BKLEN <10>
PANEL_BKEN_EC <35>
+BL_PWR_SRC
12
S
G
LCDVDD POWERBacklight POWER
0.1U_0603_50V7K
CV12
3.3V_TS_EN<12>
LCD_VCC_TEST_EN<35>
ENVDD_PCH<10,36>
D
2
G
S
10U_0603_6.3V6M
DV3
2
1
3
BAT54CW_SOT323-3
QV7
CV9@
+LCDVDD
12
EN_LCDPWR
1 2
100K_0402_5%
RV3
1
VOUT
GND
EN
VIN
VIN
2
3
AP2821KTR-G1_SOT23-5
2nd source SA000028Y10
UV24
+3.3V_ALW
5
4
0.01U_0402_16V7K
@
CV10
12
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
eDP CONN & Touch screen
eDP CONN & Touch screen
eDP CONN & Touch screen
LA-A961P
LA-A961P
LA-A961P
23 53Tuesday, October 07, 2014
23 53Tuesday, October 07, 2014
23 53Tuesday, October 07, 2014
1
1.0
1.0
1.0
Page 24
Vinafix.com
5
4
3
2
1
@
CV24
12
+3.3V_RUN
+5V_RUN
1
GND2OUT
AP2330W-7_SC59-3
IN
UV10
3
+VHDMI_VCC
12
0.1U_0402_10V7K
10U_0603_6.3V6M
CV27
12
CV30@
HDMI connector
JHDMI1 CONN@
HDMI_HPD<25>
HDMI_DAT_AUX#
12
RV8@10K_0402_5%
HDMI_CLK_AUX
HDMI_CEC
TMDS_CON_CLK#
TMDS_CON_CLK
TMDS_CON_N0
TMDS_CON_P0
TMDS_CON_N1
TMDS_CON_P1
TMDS_CON_N2
TMDS_CON_P2
19
HP_DET
18
+5V
17
DDC/CEC_GND
16
SDA
15
SCL
14
Reserved
13
CEC
12
CK-
9
8
7
6
5
4
3
2
1
CK_shield
CK+
D0D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
GND
GND
GND
GND
11
10
LCN_AUF05-1922S10-0019
20
21
22
23
+VHDMI_VCC
D D
HDMI_LANE_P3<25>
HDMI_LANE_N3<25>
HDMI_LANE_P2<25>
HDMI_LANE_N2<25>
HDMI_LANE_P1<25>
HDMI_LANE_N1<25>
HDMI_CLK_AUX<25>
HDMI_DAT_AUX#<25>
C C
HDMI_LANE_P0<25>
HDMI_LANE_N0<25>
HDMI_CLK_AUX
HDMI_DAT_AUX#
HDMI_LANE_P3 TMDS_CON_CLK
HDMI_LANE_N3
HDMI_LANE_P2
HDMI_LANE_N2
HDMI_LANE_P1
HDMI_LANE_N1
HDMI_LANE_P0
HDMI_LANE_N0
1 2
RV7 2.2K_0402_5%
1 2
RV9 2.2K_0402_5%
LV3EMC@
4
1
DLW21HN900HQ2L_4P
4
1
DLW21HN900HQ2L_4P
4
1
DLW21HN900HQ2L_4P
4
1
DLW21HN900HQ2L_4P
3
4
1
2
LV6EMC@
3
4
1
2
LV10EMC@
3
4
1
2
LV12EMC@
3
4
1
2
3
2
3
2
3
2
3
2
TMDS_CON_CLK#
TMDS_CON_P2
TMDS_CON_N2
TMDS_CON_P1
TMDS_CON_N1
TMDS_CON_P0
TMDS_CON_N0
0.1U_0402_16V4Z
20130726 2nd AUF05-1922S10-0019 CIS Link OK
+3.3V_RUN
0.1U_0402_16V4Z
@
CV510
1
1
UV501
2
12
123
D
mDP_LANE_P3_C
12
mDP_LANE_N3_C
12
mDP_LANE_P2_C
12
mDP_LANE_N2_C
12
mDP_LANE_P1_C
12
mDP_LANE_N1_C
12
mDP_LANE_P0_C
12
mDP_LANE_N0_C
mDP_HPD
+3.3V_RUN
1 2
RV501 100K_0402_5%
1 2
RV502 100K_0402_5%
1 2
RV503 5.1M_0402_5%
RV504 1M_0402_5%
1 2
RV505 100K_0402_5%
AP2337SA-7_SOT23-3
mDP_AUX#_C
mDP_AUX_C
12
DPB_MB_P14
mDP_CA_DET
mDP_HPD
DDI2_LANE_P3<10>
B B
CPU_DPC_AUX<10>
CPU_DPC_AUX#<10>
A A
AUX/DDC SW for DDI1 to Mini DP
CV512
12
0.1U_0402_10V7K
CV513
12
0.1U_0402_10V7K
SW_mDP_AUX_C
mDP_AUX_C
SW_mDP_AUX#_C
mDP_AUX#_C
mDP_CA_DET
mDP_CA_DET1function
mDP
0
HDMI
UV502
1
BE0
2
A0
3
B0
4
BE1
5
A1
6
B1
7
GND
PI3C3125LEX_TSSOP14~D
+3.3V_RUN
2
G
VCC
BE3
A3
B3
BE2
A2
B2
100K_0402_5%
12
RV507
13
D
QV502
L2N7002WT1G_SC-70-3
S
14
13
12
11
10
9
8
mDP_CA_DET#
+3.3V_RUN
1 2
CV511
0.1U_0402_25V6
CPU_DPC_CTRLCLK <10>
CPU_DPC_CTRLDAT <10>
DPC_HPD<10>
DDI2_LANE_N3<10>
DDI2_LANE_P2<10>
DDI2_LANE_N2<10>
DDI2_LANE_P1<10>
DDI2_LANE_N1<10>
DDI2_LANE_P0<10>
DDI2_LANE_N0<10>
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
CV501 0.1U_0402_10V7K
CV502 0.1U_0402_10V7K
CV503 0.1U_0402_10V7K
CV504 0.1U_0402_10V7K
CV505 0.1U_0402_10V7K
CV506 0.1U_0402_10V7K
CV507 0.1U_0402_10V7K
CV508 0.1U_0402_10V7K
+5V_RUN
G
S
QV501
L2N7002WT1G_SC-70-3
IN
GND2OUT
3
mDP_AUX#_C
mDP_LANE_N2_C
mDP_AUX_C
mDP_LANE_P2_C
mDP_LANE_N3_C
mDP_LANE_N1_C
mDP_LANE_P3_C
mDP_LANE_P1_C
DPB_MB_P14
mDP_LANE_N0_C
mDP_CA_DET
mDP_LANE_P0_C
mDP_HPD
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
+VDISPLAY_VCC
.01U_0402_16V7K
1
CV509
2
mDP connector
CONN@
JmDP1
20
DP_PWR
19
GND
18
AUX_CH-
17
LAN2-
16
AUX_CH+
15
LAN2+
14
GND
13
GND
12
LAN3-
11
LAN1-
10
LAN3+
9
LAN1+
8
GND
7
GND
6
CA_DET
5
LAN0-
4
CFG1
3
LAN0+
2
HP_DET
1
GND
FOX_3V112M1-RA4A2-7H
20130726 DC060007NB0 CIS Link OK
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
HDMI CONN
HDMI CONN
HDMI CONN
LA-A961P
LA-A961P
LA-A961P
GND
GND
GND
GND
21
22
23
24
24 53Tuesday, October 07, 2014
24 53Tuesday, October 07, 2014
24 53Tuesday, October 07, 2014
1.0
1.0
1.0
Page 25
Vinafix.com
5
+3.3V_RUN
PCB
D D
G12 UMA
DP SWITCH
PS8339+DP8338
G12 Entry PS8339
G14 DSC
G14 UMA
G14D_En
G14U_En
C C
PS8339+DP8338
PS8339+DP8338
PS8339
PS8339
RV551
@
4.7K_0402_5%
RV550
@
4.7K_0402_5%
1 2
RV555 100K_0402_5%@
1 2
RV68 100K_0402_5%
@
1 2
RV554 100K_0402_5%@
1 2
RV67 1M_0402_5%
+3.3V_RUN
12
12
12
12
RV55
RV54
RV51
@
@
4.7K_0402_5%
4.7K_0402_5%
12
12
RV52
@
4.7K_0402_5%
RV62
RV61
@
@
4.7K_0402_5%
PS8338_AUX#
PS8339B_IN_CA_DET
PS8338_AUX
PS8339B_OUT_CA_DET
12
12
RV56
4.7K_0402_5%
4.7K_0402_5%
12
12
RV64
@
4.7K_0402_5%
4.7K_0402_5%
4
DDI1_LANE_P0<10>
DDI1_LANE_N0<10>
DDI1_LANE_P1<10>
DDI1_LANE_N1<10>
DDI1_LANE_P2<10>
DDI1_LANE_N2<10>
DDI1_LANE_P3<10>
DDI1_LANE_N3<10>
CPU_DPB_AUX<10>
12
12
12
RV60
RV58
RV57
4.7K_0402_5%
RV63
4.7K_0402_5%
@
@
4.7K_0402_5%
4.7K_0402_5%
12
RV65
@
4.7K_0402_5%
12
RV66
4.7K_0402_5%
PS8339B_TMDS_DDCBUF
12
CPU_DPB_AUX#<10>
CPU_DPB_CTRLCLK<10>
CPU_DPB_CTRLDAT<10>
PS8339B_INPUT_EQ
PS8339B_MODE
PS8339B_TMDS_PRE
PS8339B_TMDS_RT
PS8339B_DP_CFG1
PS8339B_DP_CFG0
PS8339B_MODE_SW
3
0.01U_0402_16V7K
0.01U_0402_16V7K
1
1
12
CV61
CV62
2
2
1 2
CV71 0.1U_0402_25V6
1 2
CV72 0.1U_0402_25V6
1 2
CV73 0.1U_0402_25V6
1 2
CV74 0.1U_0402_25V6
1 2
CV75 0.1U_0402_25V6
1 2
CV76 0.1U_0402_25V6
1 2
CV77 0.1U_0402_25V6
1 2
CV78 0.1U_0402_25V6
1 2
CV79 0.1U_0402_25V6
1 2
CV80 0.1U_0402_25V6
DPB_HPD<10>
2.2U_0402_6.3V6M
12
CV60
12
RV50
4.99K_0402_1%
+3.3V_RUN
0.1U_0402_25V6
0.1U_0402_25V6
12
CV66
CV69
PS8339B_DP_CFG0
PS8339B_MODE_SW
DDI1_LANE_P0_C
DDI1_LANE_N0_C
DDI1_LANE_P1_C
DDI1_LANE_N1_C
DDI1_LANE_P2_C
DDI1_LANE_N2_C
DDI1_LANE_P3_C
DDI1_LANE_N3_C
CPU_DPB_AUX_C
CPU_DPB_AUX#_C
CPU_DPB_CTRLCLK
CPU_DPB_CTRLDAT
PS8339B_IN_CA_DET
PS8339B_TMDS_DDCBUF
PS8339B_INPUT_EQ
PS8339B_MODE
UV7
14
VDD33
28
VDD33
41
VDD33
56
VDD33
44
DP_CFG0/SCL_CTL
45
SW/SDA_CTL
38
I2C_CTL_EN
3
IN_D0p
4
IN_D0n
6
IN_D1p
7
IN_D1n
9
IN_D2p
10
IN_D2n
12
IN_D3p
13
IN_D3n
52
IN_AUXp
51
IN_AUXn
50
IN_DDC_SCL
49
IN_DDC_SDA
11
IN_CA_DET
5
IN_HPD
1
CEXT
2
TMDS_DDCBUF
8
PEQ
27
REXT
46
PD
53
MODE
PS8339BQFN56GTR2-A0_QFN56_7X7
DP_AUXn_SDA
2
DP_D0p
DP_D0n
DP_D1p
DP_D1n
DP_D2p
DP_D2n
DP_D3p
DP_D3n
DP_AUXp_SCL
DP_HPD
DP_CA_DET
DP_CFG1
TMDS_CH0p
TMDS_CH0n
TMDS_CH1p
TMDS_CH1n
TMDS_CH2p
TMDS_CH2n
TMDS_CLKp
TMDS_CLKn
TMDS_SCL
TMDS_SDA
TMDS_HPD
TMDS_RT
TMDS_PRE
GND
GND
GND
Thermal/GND
40
39
37
36
34
33
31
30
55
PS8338_AUX
54
PS8338_AUX#
32
42
PS8339B_OUT_CA_DET
29
PS8339B_DP_CFG1
19
18
22
21
25
24
16
15
48
47
17
23
PS8339B_TMDS_RT
20
PS8339B_TMDS_PRE
26
35
43
57
PS8338_P0 <26>
PS8338_N0 <26>
PS8338_P1 <26>
PS8338_N1 <26>
PS8338_P2 <26>
PS8338_N2 <26>
PS8338_P3 <26>
PS8338_N3 <26>
PS8338_AUX <26>
PS8338_AUX# <26>
PS8338_HPD <26>
HDMI_LANE_P0 <24>
HDMI_LANE_N0 <24>
HDMI_LANE_P1 <24>
HDMI_LANE_N1 <24>
HDMI_LANE_P2 <24>
HDMI_LANE_N2 <24>
HDMI_LANE_P3 <24>
HDMI_LANE_N3 <24>
HDMI_CLK_AUX <24>
HDMI_DAT_AUX# <24>
HDMI_HPD <24>
1
MODE = L: Control Switching Mode, HDMI ID disable
= H: Automatic Switching Mode, HDMI ID disable
= M: Automatic Switching Mode, HDMI ID enable
TMDS_PRE = L: no pre-emphasis
= H: 1.5dB pre-emphasis
= M: 3.0dB pre-emphasis
B B
A A
TMDS_RT = L: Standard open drain driver
= H: Open drain driver with termination resistors
TMDS_DDCBUF = L: DDC pass through
= H: DDC active buffer
= M: DDC pass through with 40 kohm pull up resistor
PEQ = L: default, LEQ, compensate channel loss up to 12dB @ HBR2
= H: HEQ, compensate channel loss up to 15dB @ HBR2
= M: LLEQ, compensate channel loss up to 5dB @ HBR2
DP_CFG1 = L: default, auto test disable & input offset cancellation enable
= H: auto test enable & input offset cancellation enable
= M: auto test disable & input offset cancellation disable
DP_CFG0 = L: default, automatic EQ enable & AUX interception enable
= H: automatic EQ disable & AUX interception enable
= M: automatic EQ disable & AUX interception disable, no pre-emphasis, 800mVpp swing
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DP SW
DP SW
DP SW
LA-A961P
LA-A961P
LA-A961P
25 53Tuesday, October 07, 2014
25 53Tuesday, October 07, 2014
25 53Tuesday, October 07, 2014
1
1.0
1.0
1.0
Page 26
Vinafix.com
5
+3.3V_RUN
12
RV610
@
4.7K_0402_5%
12
RV616
@
4.7K_0402_5%
+3.3V_RUN
RV601 4.7K_0402_5%
RV602 4.7K_0402_5%
RV604 100K_0402_5%
RV605 100K_0402_5%
RV606 1M_0402_5%
RV607 1M_0402_5%
RV608 100K_0402_5%
RV609 100K_0402_5%
12
12
RV611
RV612
@
@
4.7K_0402_5%
4.7K_0402_5%
12
12
RV617
RV618
@
@
4.7K_0402_5%
4.7K_0402_5%
PCB
DP SWITCH
G12 UMA PS8339+DP8338
G12 Entry PS8339
D D
G14 DSC
G14 UMA
G14D_En
G14U_En
C C
PS8339+DP8338
PS8339+DP8338
PS8339
PS8339
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
12
RV613
@
4.7K_0402_5%
12
RV619
@
4.7K_0402_5%
4
PS8338_CFG0
PS8338_SW
VMM2320_AUX#
WIGIG_AUX#
OUT1_CA_DET
OUT2_CA_DET
VMM2320_AUX
WIGIG_AUX
12
RV614
@
4.7K_0402_5%
12
RV620
@
4.7K_0402_5%
3
+3.3V_RUN
0.01U_0402_16V7K
0.01U_0402_16V7K
12
12
CV604
CV603
1 2
PS8338_P0<25>
PS8338_N0<25>
PS8338_P1<25>
PS8338_N1<25>
PS8338_P2<25>
PS8338_N2<25>
PS8338_P3<25>
PS8338_N3<25>
12
12
RV603
RV615
@
@
4.7K_0402_5%
4.7K_0402_5%
PS8338B_P0
PS8338B_P1
PS8338B_PC10
PS8338B_PC11
PS8338B_PC20
PS8338B_PC21
PS8338B_PEQ
12
RV100
@
4.7K_0402_5%
CV606 0.1U_0402_25V6
1 2
CV607 0.1U_0402_25V6
1 2
CV608 0.1U_0402_25V6
1 2
CV609 0.1U_0402_25V6
1 2
CV610 0.1U_0402_25V6
1 2
CV611 0.1U_0402_25V6
1 2
CV612 0.1U_0402_25V6
1 2
CV613 0.1U_0402_25V6
PS8338_HPD<25>
PS8338_AUX<25>
PS8338_AUX#<25>
0.1U_0402_25V6
12
0.1U_0402_25V6
12
CV601
PS8338_P0_C
PS8338_N0_C
PS8338_P1_C
PS8338_N1_C
PS8338_P2_C
PS8338_N2_C
PS8338_P3_C
PS8338_N3_C
PS8338B_P1
PS8338B_P0
PS8338_CFG0
PS8338B_PC10
PS8338B_PC11
PS8338B_PC20
PS8338B_PC21
Dock has high priority when both ports plugged
CV600
UV600
5
VDD33
21
VDD33
30
VDD33
51
VDD33
57
VDD33
6
IN_D0p
7
IN_D0n
9
IN_D1p
10
IN_D1n
12
IN_D2p
13
IN_D2n
15
IN_D3p
16
IN_D3n
4
IN_CA_DET
3
IN_HPD
2
I2C_CTL_EN
1
Pl1/SCL_CTL
60
Pl0/SDA_CTL
22
IN_DDC_SCL
23
IN_DDC_SDA
24
IN_AUXp
25
IN_AUXn
59
CFG0
58
CFG1
56
PC10
55
PC11
54
PC20
53
PC21
11
GND
19
GND
52
GND
61
PAD(GND)
PS8338BQFN60GTR-A0_QFN60_5X9
OUT1_D0p
OUT1_D0n
OUT1_D1p
OUT1_D1n
OUT1_D2p
OUT1_D2n
OUT1_D3p
OUT1_D3n
OUT2_D0p
OUT2_D0n
OUT2_D1p
OUT2_D1n
OUT2_D2p
OUT2_D2n
OUT2_D3p
OUT2_D3n
OUT1_AUXp_SCL
OUT1_AUXn_SDA
OUT2_AUXp_SCL
OUT2_AUXn_SDA
OUT1_CA_DET
OUT1_HPD
OUT2_CA_DET
OUT2_HPD
PEQ
CEXT
REXT
50
49
47
46
45
44
42
41
40
39
37
36
35
34
32
31
26
27
28
29
43
48
33
38
18
SW
8
14
PD
17
20
0.1U_0402_25V6
12
CV602
2
OUT1_CA_DET
OUT2_CA_DET
PS8338_SW
PS8338B_PEQ
12
RV600
4.99K_0402_1%
1
WIGIG_LANE_P0 <30>
WIGIG_LANE_N0 <30>
WIGIG_LANE_P1 <30>
WIGIG_LANE_N1 <30>
WIGIG_LANE_P2 <30>
WIGIG_LANE_N2 <30>
WIGIG_LANE_P3 <30>
WIGIG_LANE_N3 <30>
VMM2320_P0 <22>
VMM2320_N0 <22>
VMM2320_P1 <22>
VMM2320_N1 <22>
VMM2320_P2 <22>
VMM2320_N2 <22>
VMM2320_P3 <22>
VMM2320_N3 <22>
WIGIG_AUX <30>
WIGIG_AUX# <30>
VMM2320_AUX <22>
VMM2320_AUX# <22>
WIGIG_HPD <30>
VMM2320_HPD <22>
Port switching control or priority configuration. Internal pull down ~150KΩ, 3.3V I/O
2.2U_0402_6.3V6M
For Control Switching Mode (CFG0 = L):
SW = L: Port1 is selected (default)
12
CV605
SW = H: Port2 is selected
For Automatic Switching Mode (CFG0 = H):
SW = L: Port1 has higher priority when both ports are plugged (default)
SW = H: Port2 has higher priority when both ports are plugged
AUX/DDC SW for DPB to E-DOCK AUX/DDC SW for DPC to E-DOCK
UV11
1
BE0
12
SW_DPB_AUX<22>
B B
A A
DPB_DOCK_AUX<34>
SW_DPB_AUX#<22>
DPB_DOCK_AUX#<34>
5
SW_DPB_AUX_C
CV119 0.1U_0402_10V7K
DPB_DOCK_AUX
12
SW_DPB_AUX#_C
CV120 0.1U_0402_10V7K
DPB_DOCK_AUX#
1 2
1 2
DPB_CA_DET
DPB_CA_DET
DPC_CA_DET
DPB_CA_DET<22,34>
RV508 1M_0402_5%
RV509 1M_0402_5%
2
3
4
5
6
7
+3.3V_RUN_VMM
2
G
VCC
A0
BE3
B0
BE1
A1
B1
GND
PI3C3125LEX_TSSOP14~D
12
13
100K_0402_5%
D
S
RV90
L2N7002WT1G_SC-70-3
A3
B3
BE2
A2
B2
DPB_CA_DET#
QV9
4
+3.3V_RUN_VMM
14
13
12
11
10
9
8
CV124
1 2
0.1U_0402_25V6
VMM_DPB_CTRLCLK <22>
VMM_DPB_CTRLDAT <22>
1
2
2
3
4
5
6
7
+3.3V_RUN_VMM
2
G
12
SW_DPC_AUX<22>
DPC_DOCK_AUX<34>
SW_DPC_AUX#<22>
DPC_DOCK_AUX#<34>
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
CV122 0.1U_0402_10V7K
CV123 0.1U_0402_10V7K
DPC_CA_DET<22,34>
SW_DPC_AUX_C
DPC_DOCK_AUX
12
SW_DPC_AUX#_C
DPC_DOCK_AUX#
DPC_CA_DET
UV12
BE0
VCC
A0
BE3
B0
BE1
A1
B1
GND
PI3C3125LEX_TSSOP14~D
100K_0402_5%
12
13
D
S
RV91
L2N7002WT1G_SC-70-3
A3
B3
BE2
A2
B2
DPC_CA_DET#
QV10
DELL CONFIDENTIAL/PROPRIETARY
+3.3V_RUN_VMM
14
13
12
11
10
9
8
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
CV121
1 2
0.1U_0402_25V6
VMM_DPC_CTRLCLK <22>
VMM_DPC_CTRLDAT <22>
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
DP SW
DP SW
DP SW
LA-A961P
LA-A961P
LA-A961P
26 53Tuesday, October 07, 2014
26 53Tuesday, October 07, 2014
26 53Tuesday, October 07, 2014
1
1.0
1.0
1.0
Page 27
Vinafix.com
5
D D
4
3
2
1
V_BAT
GPIO_1
GPIO_2
GPIO_3
PP/GPIO
TESTBI
TESTI
NBO_1
NBO_2
NBO_3
NBO_4
NBO_5
NBO_6
+3.3V_M_TPM
12
1
2
17
6
7
9
8
5
13
14
15
27
28
+3.3V_SUS
0.1U_0402_25V6
@
CZ10
12
12
Close to JUSH1
1 2
RZ8 2.2K_0402_5%
1 2
RZ9 2.2K_0402_5%
1 2
RZ10 1M_0402_5%
+3.3V_SUS+3.3V_RUN+5V_RUN
0.1U_0402_25V6
0.1U_0402_25V6
@
CZ11
12
@
CZ12
USH_SMBCLK
USH_SMBDAT
USH_PWR_STATE#
0.047U_0402_16V4Z
12
PLTRST_USH#
EMC@
CZ68
USBP6-<11>
USBP6+<11>
USH_SMBCLK<36>
USH_SMBDAT<36>
BCM5882_ALERT#<35>
+3.3V_SUS
+3.3V_RUN
+5V_RUN
PLTRST_USH#<9>
USH_PWR_STATE#<35>
CONTACTLESS_DET#<10,12>
USH_DET#<10,12>
20131016 change back to 20pin
USH CONN
JUSH1
22
GND2
21
GND1
20
20
19
19
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E-T_6705K-Y20N-00L
CONN@
+3.3V_M_TPM
4700P_0402_25V7K
2200P_0402_50V7K
PCH_PLTRST#_EC<9,30,35,36>
12
CZ6
12
33_0402_5%
33_0402_5%
33_0402_5%
TPM_PIRQ#<12>
2200P_0402_50V7K
CZ7
SPI_DINTPM
SPI_DOTPM
SPI_CLKTPM
PCH_SPI_CS2#_R
0.1U_0402_25V6
CZ5
12
12
C C
PCH_SPI_DIN<7>
PCH_SPI_DO<7>
PCH_SPI_CLK<7>
PCH_SPI_CS2#<7>
SPI_CLKTPM
33_0402_5%
@EMC@
RZ35
0.1U_0402_25V6
1 2
@EMC@
B B
12
CZ9
CZ4@
1 2
RZ30
1 2
RZ29
1 2
RZ26
1 2
RZ17@ 0_0402_5%
+3.3V_M
3
10
19
24
26
23
21
22
16
20
25
18
11
4
1 2
UZ1
VCC
VCC
VCC
VCC
MISO
MOSI
SPI_CLK
SPI_CS#
SPI_RST#
PIRQ#
GND
GND
GND
GND
AT97SC3205_TSSOP28~D
PJP11@
PAD-OPEN1x1m
GPIO-Express-00
For ESD solution
Close to JUSH1
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
USH & TPM
USH & TPM
USH & TPM
LA-A961P
LA-A961P
LA-A961P
27 53Tuesday, October 07, 2014
27 53Tuesday, October 07, 2014
27 53Tuesday, October 07, 2014
1
1.0
1.0
1.0
Page 28
Vinafix.com
5
+3.3V_LAN
1 2
1 2
0.1U_0402_10V7K
0.1U_0402_10V7K
12
CL10
CL9
+3.3V_ALW
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
SW_ACTLED_YEL#
SW_100_ORG#
SW_10_GRN#
TP_LAN_JTAG_TMS
TP_LAN_JTAG_TCK
12
LANCLK_REQ#
RL7 0_0402_5%@
0.1U_0402_10V7K
12
12
CL11
+3.3V_ALW
+5V_ALW
DMN66D0LDW-7_SOT363-6
1
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
1
DMN66D0LDW-7_SOT363-6
1 2
0.1U_0402_10V7K
CL8
QL1A
2
SYS_LED_MASK#
QL1B
5
SYS_LED_MASK#
QL2A
2
SYS_LED_MASK#
QL2B
5
5
+3.3V_LAN
12
12
27P_0402_50V8J
CL13
1 2
UL3
1
VIN1
2
VIN1
3
ON1
4
VBIAS
5
ON2
6
VIN2
VIN27VOUT2
TPS22966DPUR_SON14_2X3
+3.3V_LAN
CL15@
1 2
0.1U_0402_10V7K
5
1
P
B
4
O
2
A
G
UL2
TC7SH08FU_SSOP5
3
6
LAN_ACTLED_YEL#
SYS_LED_MASK# <35,39>
34
LED_100_ORG#
6
LED_10_GRN#
34
10K_0402_5%
RL5@
10K_0402_5%
RL9@
RL10@ 0_0402_5%
3
OUT
4
GND
25MHZ_18PF_7V25000034
VOUT1
VOUT1
CT1
GND
CT2
VOUT2
GPAD
RL1@ 10K_0402_5%
RL2@ 10K_0402_5%
RL4 4.7K_0402_5%@
D D
PM_LANPHY_ENABLE<12>
+0.9V_LAN
22U_0603_6.3V6M
1
12
CL12
2
Note:
+1.0V_LAN will work at 0.95V to 1.15V
C C
SIO_SLP_LAN#<9,36>
3.3V_HDD_EN<12>
+3.3V_RUN
12
RN6
@
10K_0402_5%
3.3V_HDD_EN
B B
12
RN7
10K_0402_5%
+3.3V_LAN
12
RL29
1M_0402_5%
+3.3V_LAN
12
RL30
A A
1M_0402_5%
LANCLK_REQ#<7,12>
PLTRST_LAN#<9>
CLK_PCIE_LAN<7>
CLK_PCIE_LAN#<7>
PCIE_PRX_GLANTX_P3<11>
PCIE_PRX_GLANTX_N3<11>
PCIE_PTX_GLANRX_P3<11>
PCIE_PTX_GLANRX_N3<11>
LAN_SMBCLK<7>
LAN_SMBDATA<7>
LAN_WAKE#<12,36>
SMBus Device Address 0xC8
1 2
YL1
1
IN
2
GND
+3.3V_LAN
12
PJP12
PAD-OPEN1x1m
14
+3.3V_LAN_UL3
13
12
11
10
9
+3.3V_HDD_UL3
8
15
WLAN_DISBL# <35>
@
1 2
CZ36 0.1U_0402_10V7K@
1 2
CZ37 470P_0402_50V7K
CL24 470P_0402_50V7K
CL23 0.1U_0402_10V7K@
PJP66@
PAD-OPEN1x1m
LAN_DISABLE#_R<35>
T88@ PAD~D
T89@ PAD~D
12
RL11
1M_0402_5%
1 2
1 2
1 2
PJP17
PAD-OPEN1x1m
@
12
CL1 0.1U_0402_10V7K
12
CL2 0.1U_0402_10V7K
1 2
CL5 0.1U_0402_10V7K
1 2
CL6 0.1U_0402_10V7K
27P_0402_50V8J
CL14
12
+3.3V_HDD
12
+3.3V_HDD+3.3V_RUN
0.47U_0603_10V7K
12
CL16
0.47U_0603_10V7K
12
CL20
4
PCIE_PRX_GLANTX_P3_C
PCIE_PRX_GLANTX_N3_C
PCIE_PTX_GLANRX_P3_C
PCIE_PTX_GLANRX_N3_C
LAN_DISABLE#_R
LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
TP_LAN_JTAG_TDI
TP_LAN_JTAG_TDO
TP_LAN_JTAG_TMS
TP_LAN_JTAG_TCK
XTALOXTALO_R
XTALI
LAN_TEST_EN
3.01K_0402_1%
1K_0402_5%
12
12
RL13
RL12
SW_LAN_TX1-
SW_LAN_TX1+
0.47U_0603_10V7K
SW_LAN_TX0-
12
CL17
SW_LAN_TX0+
SW_LAN_TX3-
SW_LAN_TX3+
0.47U_0603_10V7K
SW_LAN_TX2-
12
CL21
SW_LAN_TX2+
4
UL1
48
CLK_REQ_N
36
PE_RST_N
44
PE_CLKP
45
PE_CLKN
38
PETp
39
PETn
41
PERp
42
PERn
28
SMB_CLK
31
SMB_DATA
2
LANWAKE_N
3
LAN_DISABLE_N
26
LED0
27
LED1
25
LED2
32
JTAG_TDI
34
JTAG_TDO
33
JTAG_TMS
35
JTAG_TCK
9
XTAL_OUT
10
XTAL_IN
30
TEST_EN
12
RBIAS
WGI218LM-QQ89-B0_QFN48_6X6~D
TL1
1
TD1+
2
TD1-
3
TDCT1
4
TDCT2
5
TD2+
6
TD2-
7
TD3+
8
TD3-
9
TDCT3
10
TDCT4
11
TD4+
12
TD4-
MHPC_NS692417
GND
GND
CHASSIS
CHASSIS
PCIE
SMBUS
JTAG LED
MDI_PLUS0
MDI_MINUS0
MDI_PLUS1
MDI_MINUS1
MDI_PLUS2
MDI
MDI_MINUS2
MDI_PLUS3
MDI_MINUS3
SVR_EN_N
RSVD_VCC3P3_1
VDD3P3_IN
VDD3P3_4
VDD3P3_15
VDD3P3_19
VDD3P3_29
VDD0P9_47
VDD0P9_46
VDD0P9_37
VDD0P9_43
VDD0P9_11
VDD0P9_40
VDD0P9_22
VDD0P9_16
VDD0P9_8
CTRL0P9
VSS_EPAD
CL22
3
13
LAN_TX0+
14
LAN_TX0-
17
LAN_TX1+
18
LAN_TX1-
20
LAN_TX2+
21
LAN_TX2-
23
LAN_TX3+
24
LAN_TX3-
6
VCT_LAN_R1
1
+RSVD_VCC3P3_1
5
4
15
19
29
47
46
37
43
11
40
22
16
8
7
REGCTL_PNP10RES_BIAS
49
Place CL3, CL4 and LL1 close to UL1
1:1
1:1
1:1
1:1
1 2
EMC@
150P_1808_2.5KV8J
3
2
Layout Notice : Place bead as
close UL4 as possible
1 2
RL21 5.6_0603_5%EMC@
1 2
RL22 5.6_0603_5%EMC@
1 2
RL23 5.6_0603_5%EMC@
1 2
RL24 5.6_0603_5%EMC@
1 2
RL25 5.6_0603_5%EMC@
1 2
RL26 5.6_0603_5%EMC@
1 2
RL27 5.6_0603_5%EMC@
1 2
RL28 5.6_0603_5%EMC@
RL3 0_0402_5%@
RL6 4.7K_0402_5%
+3.3V_LAN_OUT
+0.9V_LAN
1 2
24
TX1+
23
TX1-
22
TXCT1
21
TXCT2
20
TX2+
19
TX2-
18
TX3+
17
TX3-
16
TXCT3
15
TXCT4
14
TX4+
13
TX4-
use 40mil trace if necessary
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
12
12
RL8@ 0_0603_5%
1U_0603_10V6K
12
CL7
+0.9V_LAN
LL14.7UH_BRC2012T4R7MD_20%
0.1U_0402_10V7K
10U_0603_6.3V6M
CL3
12
12
NB_LAN_TX1-
NB_LAN_TX1+
Z2805
Z2807
NB_LAN_TX0-
NB_LAN_TX0+ NB_LAN_TX0-
NB_LAN_TX3-
NB_LAN_TX3+
Z2806
Z2808
NB_LAN_TX2-
NB_LAN_TX2+
+GND_CHASSIS
12
12
RL16 75_0402_1%
RL15 75_0402_1%
+3.3V_LAN
12
Idc_min=500mA
DCR=100mohm
CL4
12
12
RL17 75_0402_1%
RL18 75_0402_1%
LAN_TX0+L
LAN_TX0-L
LAN_TX1+L
LAN_TX1-L
LAN_TX2+L
LAN_TX2-L
LAN_TX3+L
LAN_TX3-L
+3.3V_LAN
+3.3V_LAN
12
LAN_TX0+L
LAN_TX0-L
LAN_TX1+L
LAN_TX1-L
LAN_TX2+L
LAN_TX2-L
LAN_TX3+L
LAN_TX3-L
DOCKED<22,31,35>
LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
LAN_ACTLED_YEL# LAN_ACTLED_YEL_R#
NB_LAN_TX3NB_LAN_TX3+
NB_LAN_TX1NB_LAN_TX2NB_LAN_TX2+
NB_LAN_TX1+
LED_10_GRN# LED_10_GRN_R#
LED_100_ORG# LED_100_ORG_R#
NB_LAN_TX0+
2
LAN ANALOG SWITCH
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
12
12
CL26
CL25
RL14 150_0402_5%
RL19 150_0402_5%
RL20 150_0402_5%
1 2
1 2
1 2
CL27
UL4
2
A0+
3
A0-
6
A1+
7
A1-
9
A2+
10
A2-
11
A3+
12
A3-
13
SEL
15
LEDA0
16
LEDA1
42
LEDA2
5
PD
43
PAD_GND
PI3L720ZHEX_TQFN42_9X3P5~D
12
1
1: TO DOCK
DOCKED
0: TO RJ45
1
4
8
14
21
30
39
VDD
VDD
VDD
VDD
VDD
470P_0402_50V7K
0.1U_0402_10V7K
12
CL18
VDD
VDD
+3.3V_LAN
CL19
LEDB0
LEDB1
LEDB2
LEDC0
LEDC1
LEDC2
B0+
B0-
B1+
B1-
B2+
B2-
B3+
B3-
C0+
C0-
C1+
C1-
C2+
C2-
C3+
C3-
38
SW_LAN_TX0+
37
SW_LAN_TX0-
34
SW_LAN_TX1+
33
SW_LAN_TX1-
29
SW_LAN_TX2+
28
SW_LAN_TX2-
25
SW_LAN_TX3+
24
SW_LAN_TX3-
17
SW_ACTLED_YEL#
18
SW_100_ORG#
41
SW_10_GRN#
36
DOCK_LOM_TRD0+ <34>
35
DOCK_LOM_TRD0- <34>
32
DOCK_LOM_TRD1+ <34>
31
DOCK_LOM_TRD1- <34>
27
DOCK_LOM_TRD2+ <34>
26
DOCK_LOM_TRD2- <34>
23
DOCK_LOM_TRD3+ <34>
22
DOCK_LOM_TRD3- <34>
19
DOCK_LOM_ACTLED_YEL# <34>
20
DOCK_LOM_SPD100LED_ORG# <34>
40
DOCK_LOM_SPD10LED_GRN# <34>
RJ45 LOM circuit
+3.3V_LAN:20mils
JLOM1
CONN@
10
Yellow LED-
9
Yellow LED+
8
PR4-
7
PR4+
6
PR2-
5
PR3-
4
PR3+
3
PR2+
2
PR1-
1
PR1+
11
Green LED-
13
Orange LED-
12
Green-Orange LED+
SANTA_130456-511
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
LAN
LAN
LAN
LA-A961P
LA-A961P
LA-A961P
1
GND
GND
GND
GND
28 53Tuesday, October 07, 2014
28 53Tuesday, October 07, 2014
28 53Tuesday, October 07, 2014
17
16
15
14
1.0
1.0
1.0
Page 29
Vinafix.com
A
B
C
D
E
+3.3V_MMI
+3.3V_MMI
CR4 close to U27.42
CR6 close to U27.23
0.1U_0402_25V6
0.1U_0402_25V6
12
12
1 1
+1.2V_LDO
4.7U_0603_6.3V6K
CR9
1 2
+1.2V_LDO
2 2
+3.3V_MMI
100K_0402_5%
12
RR6
IO_LDOSEL
100K_0402_5%
12
RR8@
3 3
+3.3V_RUN +3.3V_MMI
PJP26@
1 2
PAD-OPEN1x1m
CR6
CR4
+3.3V_MMI
4.7U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
CR13
CR10
1 2
1 2
0.1U_0402_25V6
4.7U_0603_6.3V6K
CR19
CR18
1 2
1 2
PCIE_PTX_MMIRX_P1<11>
PCIE_PTX_MMIRX_N1<11>
PCIE_PRX_MMITX_P1<11>
PCIE_PRX_MMITX_N1<11>
CR7
1 2
1 2
If support RTD3 cold the AUX and MAIN power rail should be
use different power rail; for RTD3 hot please keep this circuit
0.1U_0402_25V6
0.1U_0402_25V6
CR22
CR21
1 2
1 2
CR24 0.1U_0402_10V7K
1 2
1 2
CR25 0.1U_0402_10V7K
1 2
CR26 0.1U_0402_10V7K
1 2
CR27 0.1U_0402_10V7K
+3.3V_MMI
1 2
RR15 10K_0402_5%
0.1U_0402_25V6
CR8
CR3 close to U27.9
CR1 CR2 close to U27.35
4.7U_0603_6.3V6K
12
12
CR1
RR2 191_0402_1%
CLK_PCIE_MMI#<7>
CLK_PCIE_MMI<7>
PLTRST_MMI#<9>
MEDIACARD_IRQ#<12>
MMICLK_REQ#<7>
MEDIACARD_PWREN
0.1U_0402_25V6
0.1U_0402_25V6
12
CR2
CR3
1 2
PCIE_PTX_MMIRX_P1_C
PCIE_PTX_MMIRX_N1_C
PCIE_PRX_MMITX_P1_C
PCIE_PRX_MMITX_N1_C
MEDIACARD_PWREN
IO_LDOSEL
PE_REXT
UR1
9
PE_33VCCAIN
27
UHSII_33VCCAIN/NC
42
SD_33VCCD
23
SD_SKT_33VIN
13
AUX _33VIN
11
MAIN_LDO_VIN
10
MAIN_LDO_12VOUT
41
CORE_12VCCD
36
UHSII_12VCCAIN/NC
31
UHSII_12VCCAIN/NC
28
UHSII_12VCCAIN/NC
1
PE_12VCCAIN
4
PE_REXT
6
PE_RXP
5
PE_RXM
7
PE_TXP
8
PE_TXM
2
PE_REFCLKM
3
PE_REFCLKP
15
PE_RST#_GATE#
14
MAIN_LDO_EN
16
DEV_WAKE#
17
CLKREQ#
18
IO0_LDOSEL
OZ777FJ2LN_QFN48_6X6
OZ777FJ2LN
please routing daisy chain
1. from UR1.38 (SD_D0) -> UR1.30 (SD_RCLK_P) -> LR3.4
2. From UR1.37 (SD_D1) -> UR1.29 (SD_RCLK_N) -> LR3.1
R231,R297,R306,R315,R333,R337 for EMI solution
AUX_LDO_CAP
SD_IO_LDO_CAP
SD_SKT_33VOUT
SD_SKT_18VOUT
SD_WPI
SD_CD#
SD_CLK
SD_CMD
MMC_D7
MMC_D6
MMC_D5
MMC_D4
SD_D3
SD_D2
SD_D1
SD_D0
SD_RCLK_M/NC
SD_RCLK_P/NC
SD_D1P/NC
SD_D1M/NC
SD_D0M/NC
SD_D0P/NC
SD_REXT/NC
LED#
GND
12
+AUX_LDO
25
+SD_IO_LDO
22
24
20
21
43
45
39
40
44
46
47
48
37
38
29
30
32
33
34
35
26
19
49
+3.3V_RUN_CARD
+1.8V_RUN_CARD
SDWP
SD/MMCCD#
SD/MMCCMD
SD/MMCDAT3 SD/MMCDAT3_R
SD/MMCDAT2 SD/MMCDAT2_R
SD/MMCDAT1
SD/MMCDAT0
SD_UHS2_D1P
SD_UHS2_D1N
SD_UHS2_D0N
SD_UHS2_D0P
SD_REXT
RR1 EMC@ 10_0402_5%
1 2
1 2
RR3@EMC@ 0_0402_5%
RR4@EMC@ 0_0402_5%
1 2
EMI solution for SD card
1 2
RR5 4.7K_0402_1%
1 2
4.7U_0603_6.3V6K
CR14
0.1U_0402_25V6
CR15
1 2
+3.3V_RUN_CARD
+1.8V_RUN_CARD
1M_0402_5%
12
1U_0402_6.3V6K
2
CR17
1
12
+1.8V_RUN_CARD+3.3V_RUN_CARD
1U_0402_6.3V6K
CR31
4.7U_0603_6.3V6K
12
CR34
CR31 near UR1.22 CR34 near UR1.24
SD/MMCCLKSD/MMCCLK_R
@EMC@
5P_0402_50V8C
12
CR23
EMI depop location
JSD1
4
VDD/VDD1
14
VDD2
SD/MMCCMD
SD/MMCCLK
SD/MMCCD#
0.1U_0402_25V6
RR11
12
SDWP
SD/MMCDAT0
CR35
SD/MMCDAT1
SD/MMCDAT2_R
SD/MMCDAT3_R
SD_UHS2_D0P
SD_UHS2_D0N
SD_UHS2_D1P
SD_UHS2_D1N
2
CMD
5
CLK
18
CARD DETECT
19
WRITE PROTEC
7
DAT0/RCLK+
8
DAT1/RCLK-
9
DAT2
1
CD/DAT3
11
D0+
12
DO-
16
D1+
15
D1-
3
VSS1
6
VSS2
10
VSS3
13
VSS4
VSS517GND7
T-SOL_156-2000302608_NR-S
GND1
GND2
GND3
GND4
GND5
GND6
20
21
22
23
24
25
26
4 4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
A
B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C
D
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Card Reader
Card Reader
Card Reader
LA-A961P
LA-A961P
LA-A961P
E
29 53Tuesday, October 07, 2014
29 53Tuesday, October 07, 2014
29 53Tuesday, October 07, 2014
1.0
1.0
1.0
Page 30
Vinafix.com
5
+3.3V_WW AN
1 2
mSATA_DEVSLP
RZ39@ 10K_0402_5%
1 2
WWAN_PW R_EN
RZ50@ 0_0402_5%
D D
PCIE_PTX_SATARX_N6_L1<6>
PCIE_PTX_SATARX_P6_L1< 6>
PCIE_PTX_SATARX_N6_L0<6>
PCIE_PTX_SATARX_P6_L0< 6>
+3.3V_WW AN
0.047U_0402_16V4Z
C C
0.047U_0402_16V4Z
12
12
12
CZ51
CZ52
STATE #
0
8
14
B B
15
NGFF_CONFIG_3<35>
USBP7+<11>
USBP7-<11>
NGFF_CONFIG_0<35>
WWAN_W AKE#<35>
PCIE_PRX_SATATX_N6_L1<6>
PCIE_PRX_SATATX_P6_L1< 6>
1 2
CZ58 0.1U_0402_10V7K
1 2
CZ59 0.1U_0402_10V7K
PCIE_PRX_SATATX_P6_L0< 6>
PCIE_PRX_SATATX_N6_L0<6>
1 2
CZ32 0.1U_0402_10V7K
1 2
CZ33 0.1U_0402_10V7K
NGFF_CONFIG_1<35>
NGFF_CONFIG_2<35>
33P_0402_50V8J
33P_0402_50V8J
22U_0603_6.3V6M
1
12
CZ55
CZ53
CZ54
2
CONFIG_0 CONFIG_21CONFIG_3 Module Type
GND
GND
CLK_PCIE_SATA#<7>
CLK_PCIE_SATA<7>
1
+
2
CONFIG_1
PCIE_PTX_SATARX_N6_L1_C
PCIE_PTX_SATARX_P6_L1_C
PCIE_PTX_SATARX_N6_L0_C
PCIE_PTX_SATARX_P6_L0_C
150U_B2_6.3VM_R35M
@
CZ57
GND
HIGH
GND
HIGH
GND
HIGH HIGH
NGFF slot B Key B
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
ANTCTL0
ANTCTL1
ANTCTL2
ANTCTL3
51
53
55
57
59
61
63
65
67
69
20130726 80149-3221 CIS Link OK
WWAN_RADIO_DIS#<35>
HW_GPS_DISABLE2#<35>
GND
GND
GND
HIGH
HIGH
SIM Card Push-Push
+SIM_PWR
UIM_RESET
1U_0402_6.3V6K
UIM_CLK
12
C263
UIM_DATA
UIM_DET
A A
UIM_CLK
UIM_RESET
UIM_DATA
JSIM1
CONN@
1
VCC
2
RST
3
CLK
4
D+
5
GND_1
6
VPP
7
I/O
8
D-
9
DET
10
COM
T-SOL_159-1000302602
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
11
12
13
14
15
16
17
18
20130726 SP070011M00 CIS Link OK
33P_0402_50V8J
33P_0402_50V8J
@
12
CZ63
33P_0402_50V8J
@
@
12
12
CZ64
CZ65
CONN@
JNGFF2
1
1
3
3
5
5
7
7
9
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
GND
BELLW_80149-3221
4
+3.3V_WW AN
2
2
4
4
6
6
8
WWAN_RADIO_DIS#_R
8
10
10
12
12
14
14
16
16
18
HW_GPS_DISABLE2#_R
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
60
62
62
64
64
66
66
68
GND
1 2
DZ5
RB751S40T1G_SOD523-2
1 2
DZ6
RB751S40T1G_SOD523-2
GND
GND
GNDHIGH
HIGH
SSD-SATA
SSD-PCIE
WWAN
HCA-PCIE
HIGH
1 2
3.3V_WWA N_EN
RZ40 100 K_0402_5%
AUX_EN_WOWL<35>
+5V_ALW
3.3V_WWA N_EN<35>
1 2
AUX_EN_WOWL
RZ38 100 K_0402_5%
WWAN_PW R_EN
WWAN_LED#
UIM_RESET
UIM_CLK
UIM_DATA
PCH_PLTRST#_EC
PCIE_WAKE#
UIM_DET
NA
NGFF for UMA
+SIM_PWR
mSATA_DEVSLP <12>
SATACLK_REQ# <7>
WWAN_RADIO_DIS#_R
HW_GPS_DISABLE2#_R
+3.3V_WW AN
UZ2
1
VIN1
VOUT1
2
VIN1
VOUT1
3
ON1
CT1
4
VBIAS
GND
5
ON2
CT2
6
VIN2
VOUT2
VIN27VOUT2
GPAD
TPS22966DPUR_SON14_2X3
ANTCTL0
ANTCTL1
ANTCTL2
ANTCTL3
14
+3.3V_WLAN_UZ2
13
12
11
10
9
8
15
+3.3V_WLAN
12
CZ49
470P_0402_50V7K
CZ23
470P_0402_50V7K
+3.3V_WW AN_UZ2
3
PCIE_PTX_WIGIGRX_P5<11>
PCIE_PTX_WIGIGRX_N5<11>
WLAN_WIGIG60GHZ_DIS#< 35>
JANT1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
GND
10
GND
ACES_50208-00801-003
CONN@
PJP32
PAD-OPEN1x3m
@
1 2
CZ24 0.1U_0402_10V7K@
1 2
1 2
1 2
12
PAD-OPEN1x3m
CZ50
@
0.1U_0402_10V7K
2
1
NGFF slot A Key A
CONN@
JNGFF1
1
1
USBP2+<11>
USBP2-<11>
WIGIG_LANE_N3<26>
WIGIG_LANE_P3<26>
WIGIG_LANE_N2<26>
WIGIG_LANE_P2<26>
PCIE_PTX_WLANRX_P4< 11>
PCIE_PTX_WLANRX_N4<11>
EC_32KHZ_MEC5085<35,36>
BT_RADIO_DIS#<35>
1 2
1 2
CV145 0.1U_0 402_25V6
CV146 0.1U_0 402_25V6
1 2
1 2
CV147 0.1U_0 402_25V6
CV148 0.1U_0 402_25V6
WIGIG_HPD<26>
1 2
CZ13 0.1U_0402_10V 7K
1 2
CZ14 0.1U_0402_10V 7K
PCIE_PRX_WLANTX_P4< 11>
PCIE_PRX_WLANTX_N4<11>
CLK_PCIE_WLAN<7>
CLK_PCIE_WLAN#<7>
WLANCLK_REQ#<7>
PCIE_WAKE#<35>
1 2
CZ21 0.1U_0402_10V 7K
1 2
CZ22 0.1U_0402_10V 7K
PCIE_PRX_WIGIGTX_P5<11>
PCIE_PRX_WIGIGTX_N5<11>
CLK_PCIE_WIGIG<7>
CLK_PCIE_WIGIG#<7>
AUX_EN_WOWL
+3.3V_ALW
1
B
2
A
1 2
DZ1
RB751S40T1G_SOD523-2
1 2
DZ2
RB751S40T1G_SOD523-2
WIGIG_LANE_N3_C
WIGIG_LANE_P3_C
WIGIG_LANE_N2_C
WIGIG_LANE_P2_C
PCIE_PTX_WLANRX_P4_C
PCIE_PTX_WLANRX_N4_C
PCIE_WAKE#
PCIE_PTX_WIGIGRX_P5_C
PCIE_PTX_WIGIGRX_N5_C
5
UZ11
P
4
Y
G
TC7SH08FU_SSOP5
3
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
61
63
63
65
65
67
67
69
GND
BELLW_80148-3221
20130726 80148-3221 CIS Link OK
1 2
SUSCLK<9>
RZ56 0_0402_5%@
WIGIG_32KHZ_R WIGIG_32KHZ
WLAN_WIGIG60GHZ_DIS#_R
BT_RADIO_DIS#_R
1 2
RZ57@ 0_0402_5%
+3.3V_WLAN
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
60
62
62
64
64
66
66
68
GND
WLAN_LED#
BT_LED#
WIGIG_AUX#_C
WIGIG_AUX_C
WIGIG_LANE_N1_C
WIGIG_LANE_P1_C
WIGIG_LANE_N0_C
WIGIG_LANE_P0_C
WIGIG_32KHZ
PCH_PLTRST#_EC
BT_RADIO_DIS#_R
WLAN_WIGIG60GHZ_DIS#_R
PCH_PLTRST#_EC
PCIE_WAKE#
+3.3V_WLAN
0.1U_0402_25V6
12
CZ15@
0.047U_0402_16V4Z
12
CZ20
12
12
CV1500.1U_0402_25V6
CV1490.1U_0402_25V6
12
12
CV1520.1U_0402_25V6
CV1530.1U_0402_25V6
12
12
CV1560.1U_0402_25V6
CV1570.1U_0402_25V6
PCH_CL_RST1# <7>
PCH_CL_DATA1 <7>
PCH_CL_CLK1 <7>
PCH_PLTRST#_EC <9,27,35,36>
WIGIGCLK_REQ# <7,12>
0.1U_0402_25V6
0.047U_0402_16V4Z
12
CZ17
CZ16
1 2
WIGIG_AUX# <26>
WIGIG_AUX <26>
WIGIG_LANE_N1 <26>
WIGIG_LANE_P1 < 26>
WIGIG_LANE_N0 <26>
WIGIG_LANE_P0 < 26>
0.1U_0402_25V6
CZ18
1 2
4.7U_0603_6.3V6K
47P_0402_50V8J
12
12
@
CZ66
CZ19
Power Rating TBD
PWR
Rail
+3.3V
Voltage
Tolerance
Primary Power Aux Power
Peak Normal Normal
LED control circuit
+3.3V_WLAN
100K_0402_5%
100K_0402_5%
RZ15
RZ14
1 2
BT_LED#
WLAN_LED#
PJP13@
+3.3V_WW AN
WWAN_LED#
1 2
5
QZ2B
DMN66D0LDW-7_SOT363-6
126
QZ2A
DMN66D0LDW-7_SOT363-6
100K_0402_5%
RZ37
1 2
34
+3.3V_WW AN+3.3V_ALW
126
QZ11A
DMN66D0LDW-7_SOT363-6
WIRELESS_LED# <35,39>
5
34
QZ11B
DMN66D0LDW-7_SOT363-6
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
NGFF Card
NGFF Card
NGFF Card
LA-A961P
LA-A961P
LA-A961P
30 53Tuesday, October 07, 2014
30 53Tuesday, October 07, 2014
30 53Tuesday, October 07, 2014
1
1.0
1.0
1.0
Page 31
Vinafix.com
5
LI1EMC@
12
12
4
4
1
1
DLW21HN900HQ2L_4P
LI2EMC@
4
4
1
1
DLW21HN900HQ2L_4P
UI4
3
VDD
9
VDD
12
VDD
16
VDD
20
VDD
29
VDD
1
TX+
2
TX-
4
RX+
5
RX-
6
D+
7
D-
8
USB_ID
10
SS_SEL
32
HS_SEL
PI3USB3102ZLEX_TQFN32_6X3
3
2
SW_USB3RN1
SW_USB3RP1
D D
SW_USB3TN1 USB3TN1_C
CI4 0.1U_0402_10V7K
SW_USB3TP1 USB3TP1_C
CI5 0.1U_0402_10V7K
+3.3V_SUS
0.1U_0402_25V6
4.7U_0603_6.3V6K
12
C C
0.1U_0402_25V6
12
12
CI419@
CI420
0.1U_0402_25V6
0.1U_0402_25V6
12
CI418@
USB3TP1<11>
USB3TN1<11>
USB3RP1<11>
USB3RN1<11>
USBP0+<11>
USBP0-<11>
0.1U_0402_25V6
12
CI415
0.1U_0402_25V6
12
12
CI417@
CI414
CI416
DOCKED<22,28,35>
check port mapping
function
DOCKED
Dock
1
M/B
0
3
2
3
2
TX+A
TX-A
RX+A
RX-A
USB_IDA
TX+B
TX-B
RX+B
RX-B
USB_IDB
HGND
3
2
D+A
D+B
OE#
GND
GND
4
USB3RN1_D-
USB3RP1_D+
USB3TN1_D-
USB3TP1_D+
31
SW_USB3TP1
30
SW_USB3TN1
27
SW_USB3RP1
26
SW_USB3RN1
19
SW_USBP0+
18
SW_USBP0-
D-A
17
25
24
23
22
15
14
D-B
13
11
21
28
33
DOCK_USB3TP1 <34>
DOCK_USB3TN1 <34>
DOCK_USB3RP1 <34>
DOCK_USB3RN1 <34>
DOCK_USBP0+ <34>
DOCK_USBP0- <34>
USB3RN1_D- USB3RN1_DUSB3RP1_D+ USB3RP1_D+
USB3TN1_D- USB3TN1_DUSB3TP1_D+ USB3TP1_D+
PS_USBP0_D+
PS_USBP0_D-
PCB
G12 UMA
G12 Entry NA
G14 DSC
G14 UMA
G14D_En
G14U_En
3
DI1 EMC@
1
2
4
5 6
3
L05ESDL5V0NA-4_SLP2510P8-10-9
1
4
DLW21HN900HQ2L_4P
USB2 0
USB3102
LI3 EMC@
1
4
9
8
7
2
USBP0_R_D+
2
3
USBP0_R_D-
3
USB2 3
NX3DV221
NA
USB3102 NX3DV221
USB3102 NX3DV221
NA
NA
NA
NA
+5V_USB_CHG_PWR
100U_1206_6.3V6M
12
2
JUSB1
USB3TP1_D+
USB3TN1_D-
0.1U_0402_25V6
12
CI3
CI1
AZC199-02SPR7G_SOT23-3
2
3
USBP0_R_D+
USBP0_R_D-
USB3RP1_D+
DI2 EMC@
USB3RN1_D-
9
SSTX+
1
VBUS
8
SSTX-
3
D+
7
GND
2
D-
6
SSRX+
4
GND
5
SSRX-
TAITW_PUBAU4-09FLBS1FF4H0
CONN@
GND
GND
GND
GND
1
10
11
12
13
20130726 DC23300BOB0 CIS Link OK
1
+5V_ALW
12
near UI3.1
0.1U_0402_25V6
1
CI19
2
USB_PWR_SHR_VBUS_EN<35>
10U_0603_6.3V6M
@
CI13
+5V_ALW
12
RI13
SW_USBP0SW_USBP0+
USB_OC0#<11>
USB_PWR_SHR_EN#<35,36>
ILIM_SEL
10K_0402_5%
+5V_ALW
ILIM_SEL
UI3
1
IN
2
DM_OUT
3
DP_OUT
13
FAULT#
4
ILIM_SEL
5
EN
6
CTL1
7
CTL2
8
CTL3
TPS2544RTER_WQFN16_3X3
DP_IN
DM_IN
ILIM_LO
ILIM_HI
GNDP
OUT
GND
NC
+5V_USB_CHG_PWR
12
10
PS_USBP0_D+
11
PS_USBP0_D-
15
16
RI14
9
14
17
12
22.1K_0402_1%
+USB_RIGHT_PWR
USB3TP4_D+
B B
A A
USB3TN4<11>
USB3TP4<11>
+3.3V_SUS
12
USB3RN4<11>
USB3RP4<11>
0.1U_0402_25V6
DOCKED_LIO_EN<35>
CI38
12
CI28 0.1U_0402_10V7K
12
CI27 0.1U_0402_10V7K
USBP3+<11>
USBP3-<11>
LI9EMC@
1
1
4
4
DLW21HN900HQ2L_4P
1
USB3TN4_C
4
USB3TP4_C
DLW21HN900HQ2L_4P
support APR/SPR/LIO Dock
10
9
8
7
6
NX3DV221GM_XQFN10U10_2X1P55
100U_1206_6.3V6M
2
2
3
3
LI8EMC@
1
2
3
4
UI5
1
1D+
VCC
2
1D-
S
3
2D+
D+
4
2D-
D-
5
GND
OE#
2
3
SW_USBP3+
SW_USBP3-
USB3RN4_D-
USB3TN4_D-
USB3TP4_D+
DOCK_USBP3+ <34>
DOCK_USBP3- <34>
DI6 EMC@
USB3RN4_D- USB3RN4_D-USB3RP4_D+
USB3RP4_D+ USB3RP4_D+
USB3TN4_D- USB3TN4_DUSB3TP4_D+ USB3TP4_D+
SW_USBP3+
SW_USBP3-
1
2
4
5 6
3
L05ESDL5V0NA-4_SLP2510P8-10-9
LI4
EMC@
1 2
DLW21HN900HQ2L_4P
9
8
7
34
+5V_ALW
USBP3_D+
USBP3_D-
0.1U_0402_25V6
12
12
CI8
CI10
2
0.1U_0402_25V6
10U_0603_6.3V6M
@
CI12
CI11
12
12
check port mapping
DOCKED_LIO_EN
5
function
Dock
1
M/B
0
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
USB3TN4_DUSBP3_D+
USBP3_DUSB3RP4_D+
AZC199-02SPR7G_SOT23-3
3
USB3RN4_D-
DI3 EMC@
1
USB_PWR_EN2#<35>
DELL CONFIDENTIAL/PROPRIETARY
JUSB2
CONN@
9
SSTX+
1
VBUS
8
SSTX-
3
D+
7
GND
2
D-
6
SSRX+
4
GND
5
SSRX-
TAITW_PUBAU4-09FLBS1FF4H0
GND
GND
GND
GND
10
11
12
13
20130726 DC23300BOB0 CIS Link OK
+USB_RIGHT_PWR
UI2
1
2
3
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
8
GND
VOUT
7
VIN
VOUT
6
VIN
VOUT
5
EN4FLG
SY6288D10CAC_MSOP8
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
USB3.0
USB3.0
USB3.0
LA-A961P
LA-A961P
LA-A961P
USB_OC2# <11>
1
31 53Tuesday, October 07, 2014
31 53Tuesday, October 07, 2014
31 53Tuesday, October 07, 2014
1.0
1.0
1.0
Page 32
Vinafix.com
5
4
3
2
1
USB3.0 repeater
+3.3V_RUN
D D
C C
B B
+3.3V_RUN
12
RI16
4.7K_0402_5%
12
RI20
4.7K_0402_5%
@
12
12
12
12
RI25
RI18
4.7K_0402_5%
@
RI24
4.7K_0402_5%
@
RI19
4.7K_0402_5%
4.7K_0402_5%
@
@
12
12
12
RI23
RI22
4.7K_0402_5%
4.7K_0402_5%
@
@
12
RI34
RI36
4.7K_0402_5%
4.7K_0402_5%
@
@
B_EQ0
B_EQ1
B_DE0
B_DE1
PD#
TEST
12
12
RI35
RI37
4.7K_0402_5%
4.7K_0402_5%
@
@
12
RI38
4.7K_0402_5%
@
I2C_EN
+3.3V_RUN
12
12
CI30
CI29
0.1U_0402_10V7K
0.01U_0402_16V7K
RI4 2K_0402_1%
12
I/O CONN
USB3RP2_IO
USB3RN2_IO
PD#
TEST
I2C_EN
POWER_SW#_MB<9,36,39>
BREATH_WHITE_LED<39>
USB_PWR_EN1#<35>
AUD_HP_NB_SENSE<21,35>
USB_OC1#<11,12>
AUD_HP_OUT_R<21>
RING2<21>
SLEEVE<21>
AUD_HP_OUT_L<21>
UI7
1
VDD
13
VDD
15
A_EQ1/SDA_CTL
16
A_DE0/SCL_CTL
17
A_EQ0/NC
18
A_DE1/NC
19
A_INp
20
A_INn
9
B_INp
8
B_INn
5
PD#
7
REXT
14
TEST
24
I2C_EN
PS8713BTQFN24GTR2_TQFN24_4X4
POWER_SW#_MB
BREATH_WHITE_LED
USB3TP2<11>
USB3TN2<11>
USBP1+<11>
USBP1-<11>
LID_CL#<35,39>
+3.3V_ALW
+3.3V_RUN
USB3RP2_IO
USB3RN2_IO
B_EQ1/I2C_ADDR1
B_DE0/I2C_ADDR0
B_EQ0/NC
B_DE1/NC
A_OUTp
A_OUTn
B_OUTp
B_OUTn
GND
GND
GPAD
+5V_ALW
4
3
2
6
12
11
22
USB3RP2_RP
23
USB3RN2_RP
10
21
25
JIO1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
GND
32
GND
ACES_50506-03041-P01
B_EQ1
B_DE0
B_EQ0
B_DE1
12
CI32 0.1U_0402_10V7K
12
CI31 0.1U_0402_10V7K
+5V_ALW +3.3V_ALW +3.3V_RUN
12
0.1U_0402_16V4Z
0.1U_0402_16V4Z
@
@
12
CI34
CI33
USB3RP2 <11>
USB3RN2 <11>
0.1U_0402_16V4Z
@
12
CI35
20130807 SP01000Q610 CIS LinkOK
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
USB SW
USB SW
USB SW
LA-A961P
LA-A961P
LA-A961P
32 53Tuesday, October 07, 2014
32 53Tuesday, October 07, 2014
32 53Tuesday, October 07, 2014
1
1.0
1.0
1.0
Page 33
Vinafix.com
5
D D
C C
4
3
2
1
NFC on USH/B
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
NFC
NFC
NFC
LA-A961P
LA-A961P
LA-A961P
33 53Tuesday, October 07, 2014
33 53Tuesday, October 07, 2014
33 53Tuesday, October 07, 2014
1
1.0
1.0
1.0
Page 34
Vinafix.com
5
4
3
2
1
JDOCK1
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
61
63
63
65
65
67
67
69
69
71
71
73
73
75
75
77
77
79
79
81
81
83
83
85
85
87
87
89
89
91
91
93
93
95
95
97
97
99
99
101
101
103
103
105
105
107
107
109
109
111
111
113
113
115
115
117
117
119
119
121
121
123
123
125
125
127
127
129
129
131
131
133
133
135
135
137
137
139
139
141
141
143
143
145
GND1
146
PWR1
147
PWR1
151
Shield_G
152
Shield_G
153
Shield_G
154
Shield_G
155
Shield_G
156
Shield_G
JAE_WD2F144WB7-DT
CONN@
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
GND2
PWR2
PWR2
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
WD2F144WB7
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
148
149
150
157
158
159
160
161
162
DOCK_AC_OFF
DPB_CA_DET
DPB_DOCK_LANE_P0
DPB_DOCK_LANE_N0
DPB_DOCK_LANE_P1
DPB_DOCK_LANE_N1
DPB_DOCK_LANE_P2
DPB_DOCK_LANE_N2
DPB_DOCK_LANE_P3
DPB_DOCK_LANE_N3
DPB_DOCK_AUX
DPB_DOCK_AUX#
DPB_DOCK_HPD
SATA_PRX_DKTX_P0
SATA_PRX_DKTX_N0
SATA_PTX_DKRX_P0
SATA_PTX_DKRX_N0
DOCK_USBP0+ <31>
DOCK_DET_R#
0.1U_0603_50V7K
C318
12
DOCK_AC_OFF <47>
DOCK_LOM_SPD100LED_ORG# <28>
DPB_CA_DET <22,26>DPC_CA_DET<22,26>
1 2
R260 33_0402_5%EMC@
1 2
R261 33_0402_5%EMC@
1 2
R254 33_0402_5%EMC@
1 2
R256 33_0402_5%EMC@
1 2
R262 33_0402_5%EMC@
1 2
R264 33_0402_5%EMC@
1 2
R258 33_0402_5%EMC@
1 2
R267 33_0402_5%EMC@
DPB_DOCK_AUX <26>
DPB_DOCK_AUX# <26>
ACAV_DOCK_SRC# <47>
DAT_DDC2_DOCK <22>
CLK_DDC2_DOCK <22>
12
12
C312 0.01U_0402_16V7K
C313 0.01U_0402_16V7K
1 2
1 2
C314 0.01U_0402_16V7K
C315 0.01U_0402_16V7K
DOCK_USBP0- <31>
CLK_KBD <36>
DAT_KBD <36>
DOCK_USB3RN1 <31>
DOCK_USB3RP1 <31>
DOCK_USB3TN1 <31>
DOCK_USB3TP1 <31>
BREATH_LED# <36,39>
DOCK_LOM_ACTLED_YEL# <28>
DOCK_LOM_TRD0+ <28>
DOCK_LOM_TRD0- <28>
DOCK_LOM_TRD1+ <28>
DOCK_LOM_TRD1- <28>
+LOM_VCT
DOCK_LOM_TRD2+ <28>
DOCK_LOM_TRD2- <28>
DOCK_LOM_TRD3+ <28>
DOCK_LOM_TRD3- <28>
DOCK_DCIN_IS+ <46>
DOCK_DCIN_IS- <46>
DOCK_POR_RST# <36>
10_0402_5%
EMC@
12
R41
DPB_LANE_P0_C
DPB_LANE_N0_C
DPB_LANE_P1_C
DPB_LANE_N1_C
DPB_LANE_P2_C
DPB_LANE_N2_C
DPB_LANE_P3_C
DPB_LANE_N3_C
EMI solution for E-Docking USB
D19
1 2
RB751S40T1G_SOD523-2
10_0402_5%
EMC@
12
R6
C294 0.1U_0402_10V7K
C296 0.1U_0402_10V7K
C298 0.1U_0402_10V7K
C303 0.1U_0402_10V7K
C305 0.1U_0402_10V7K
C307 0.1U_0402_10V7K
C308 0.1U_0402_10V7K
C309 0.1U_0402_10V7K
SATA_PRX_DKTX_P0_C <6>
SATA_PRX_DKTX_N0_C <6>
SATA_PTX_DKRX_P0_C <6>
SATA_PTX_DKRX_N0_C <6>
+LOM_VCT
1U_0402_6.3V6K
@
12
C316
CLK_PCI_DOCKDAI_12MHZ# DAI_BCLK#
10_0402_5%
12
R273
EMC@
12
12
12
12
12
12
12
12
DOCK_DET#
DPB_LANE_P0 <22>
DPB_LANE_N0 <22>
DPB_LANE_P1 <22>
DPB_LANE_N1 <22>
DPB_LANE_P2 <22>
DPB_LANE_N2 <22>
DPB_LANE_P3 <22>
DPB_LANE_N3 <22>
0.033U_0402_16V7K
12
@
C311
Close to DOCK
Its for Enhance ESD on dock
issue.
DOCK_USBP3+ <31>
DOCK_USBP3- <31>
1 2
R272100K_0402_5%
DPB_DOCK_HPD
+3.3V_ALW2
100K_0402_5%
12
R271
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
4.7U_0805_25V6-K
@
C33
DOCK_DET_1
DPC_CA_DET
DPC_DOCK_LANE_P0
DPC_DOCK_LANE_N0
DPC_DOCK_LANE_P1
DPC_DOCK_LANE_N1
DPC_DOCK_LANE_P2
DPC_DOCK_LANE_N2
DPC_DOCK_LANE_P3
DPC_DOCK_LANE_N3
DPC_DOCK_AUX
DPC_DOCK_AUX#
BLUE_DOCK
RED_DOCK
GREEN_DOCK
0.1U_0603_50V7K
C317
12
L30ESD24VC3-2_SOT23-3
2
3
D20 @
1
DOCK_LOM_SPD10LED_GRN#<28>
12
DPC_LANE_P0<22>
DPC_LANE_N0<22>
D D
C C
B B
DPC_LANE_P1<22>
DPC_LANE_N1<22>
DPC_LANE_P2<22>
DPC_LANE_N2<22>
DPC_LANE_P3<22>
DPC_LANE_N3<22>
DPC_DOCK_HPD
C302 0.1U_0402_10V7K
12
C295 0.1U_0402_10V7K
12
C297 0.1U_0402_10V7K
12
C299 0.1U_0402_10V7K
12
C304 0.1U_0402_10V7K
12
C306 0.1U_0402_10V7K
12
C300 0.1U_0402_10V7K
12
C301 0.1U_0402_10V7K
DPC_DOCK_HPD<22> DPB_DOCK_HPD <22>
Close to DOCK
Its for Enhance ESD on
dock issue.
100K_0402_5%
12
R268
DPC_LANE_P0_C
DPC_LANE_N0_C
DPC_LANE_P1_C
DPC_LANE_N1_C
DPC_LANE_P2_C
DPC_LANE_N2_C
DPC_LANE_P3_C
DPC_LANE_N3_C
0.033U_0402_16V7K
12
SLICE_BAT_PRES#<35,40,47> DOCK_DET# <35,47>
+DOCK_PWR_BAR +DOCK_PWR_BAR
1 2
R259 33_0402_5%EMC@
1 2
R252 33_0402_5%EMC@
1 2
R253 33_0402_5%EMC@
1 2
R255 33_0402_5%EMC@
1 2
R257 33_0402_5%EMC@
1 2
R263 33_0402_5%EMC@
1 2
R265 33_0402_5%EMC@
1 2
R266 33_0402_5%EMC@
DPC_DOCK_AUX<26>
DPC_DOCK_AUX#<26>
DPC_DOCK_HPD
+NBDOCK_DC_IN_SS
C310@
BLUE_DOCK<22>
RED_DOCK<22>
GREEN_DOCK<22>
HSYNC_DOCK<22>
VSYNC_DOCK<22>
CLK_MSE<36>
DAT_MSE<36>
DAI_BCLK#<21>
DAI_LRCK#<21>
DAI_DI<21>
DAI_DO#<21>
DAI_12MHZ#<21>
D_LAD0<35>
D_LAD1<35>
D_LAD2<35>
D_LAD3<35>
D_LFRAME#<35>
D_CLKRUN#<35>
D_SERIRQ<35>
D_DLDRQ1#<35>
CLK_PCI_DOCK<7>
DOCK_SMB_CLK<36>
DOCK_SMB_DAT<36>
DOCK_SMB_ALERT#<35,40>
DOCK_PSID<40>
DOCK_PWR_BTN#<36>
12
20130726 SP0300019A0 CIS Link OK
4.7P_0402_50V8C
12
C43EMC@
A A
4.7P_0402_50V8C
12
C42EMC@
4.7P_0402_50V8C
12
C319EMC@
EMI depop location
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
E-Dock
E-Dock
E-Dock
LA-A961P
LA-A961P
LA-A961P
34 53Tuesday, October 07, 2014
34 53Tuesday, October 07, 2014
34 53Tuesday, October 07, 2014
1
1.0
1.0
1.0
Page 35
Vinafix.com
5
4
3
2
1
+3.3V_ALW
RPE9
1
8
USB_PWR_SHR_VBUS_EN
2
7
6
100K_0804_8P4R_5%
D D
C C
B B
1 2
RE5 100K_0402_5%
1 2
RE10 100K_0402_5%
1 2
RE8 100K_0402_5%
1 2
RE9 100K_0402_5%
8
7
6
100K_0804_8P4R_5%
1 2
RE11 100K_0402_5%
1 2
RE12 100K_0402_5%
1 2
RE83 100K_0402_5%@
1 2
RE21 10K_0402_5%
1 2
RE20 100K_0402_5%
Discrete
RPE4
VGA_ID
VGA_ID
@
3
45
1
2
3
45
USB_PWR_EN1#
USB_PWR_EN2#
SLICE_BAT_PRES#
WWAN_RADIO_DIS#
WLAN_WIGIG60GHZ_DIS#
DOCK_SMB_ALERT#
NGFF_CONFIG_0
NGFF_CONFIG_1
NGFF_CONFIG_2
NGFF_CONFIG_3
BT_RADIO_DIS#
PROCHOT_GATE
EXPRESS_DET# for 15U no dock only
SYS_LED_MASK#
LCD_TST
+3.3V_ALW
1 2
RE87100K_0402_5%
1 2
RE85100K_0402_5%
VGA_ID0
0
USB_PWR_SHR_EN# <31,36>
USB_PWR_EN2#<31>
EN_I2S_NB_CODEC#<21>
USH_PWR_STATE#<27>
EN_DOCK_PWR_BAR<47>
HW_GPS_DISABLE2#<30>
LCD_VCC_TEST_EN<23>
AUD_HP_NB_SENSE<21,32>
USB_PWR_EN1#<32>
SLICE_BAT_PRES#<34,40,47>
WLAN_WIGIG60GHZ_DIS#<30>
USB_PWR_SHR_VBUS_EN<31>
BT_RADIO_DIS#<30>
WWAN_RADIO_DIS#<30>
SIO_SLP_WLAN#<9>
DOCKED_LIO_EN<31>
LAN_DISABLE#_R<28>
DOCK_SMB_ALERT#<34,40>
T96@ PAD~D
PANEL_BKEN_EC<23>
PSID_DISABLE#<40>
AUD_NB_MUTE#<21>
3.3V_WWAN_EN<30>
WWAN_WAKE#<30>
SLICE_BAT_ON<47>
T97@ PAD~D
T99@ PAD~D
EC5048_TX<36>
T98@ PAD~D
BCM5882_ALERT#<27>
SYS_LED_MASK#<28,39>
WIRELESS_LED#<30,39>
PROCHOT_GATE
LID_CL_SIO#
DOCK_SMB_ALERT#
TOUCH_SCREEN_PD#
USB_PWR_EN2#
EN_I2S_NB_CODEC#
USH_PWR_STATE#
EN_DOCK_PWR_BAR
HW_GPS_DISABLE2#HW_GPS_DISABLE2#
LCD_TST<23>
DOCKED<22,28,31>
DOCK_DET#<34,47>
LCD_TST
PSID_DISABLE#
DOCKED
DOCK_DET#
AUD_NB_MUTE#
LCD_VCC_TEST_EN
WWAN_WAKE#
AUD_HP_NB_SENSE
USB_PWR_EN1#
SLICE_BAT_ON
SLICE_BAT_PRES#
EXPRESS_DET#
SMART_DET#
WLAN_WIGIG60GHZ_DIS#
EC5048_TX
USB_DB_DET#
VGA_ID
SYS_LED_MASK#
WIRELESS_LED#
BT_RADIO_DIS#
WWAN_RADIO_DIS#
1UMA
+3.3V_ALW +3.3V_ALW_UE1
12
B52
A49
B53
A50
B54
A51
B55
A52
A33
B36
A34
B37
A35
B38
A36
A37
B40
A38
B41
A39
B42
A40
B43
A41
B44
B32
A31
B33
B15
A15
B16
A16
A1
B2
A2
B3
A3
B45
A42
B4
A59
B62
A58
B61
A56
B59
A55
B58
B47
A45
B48
A46
B49
A47
B50
A48
B13
A13
A53
B57
B14
A14
B17
B18
@
1 2
10U_0603_6.3V6M
PAD-OPEN1x1m
CE1
UE1
GPIOA0
GPIOA1
GPIOA2
GPIOA3
GPIOA4
GPIOA5
GPIOA6
GPIOA7
GPIOB0
GPIOB1
GPOC2
GPOC3
GPOC4
GPOC5
GPOC6/TACH4
GPIOC7
GPIOD0
GPIOC1
GPIOC0
GPIOB7
GPIOB6
GPIOB5
GPIOB4
GPIOB3
GPIOB2
GPIOD1
GPIOD2
GPIOD3
GPIOD4
GPIOD5
GPIOD6
GPIOD7
GPIOE0/RXD
GPIOE1/TXD
GPIOE2/RTS#
GPIOE3/DSR#
GPIOE4/CTS#
GPIOE5/DTR#
GPIOE6/RI#
GPIOE7/DCD#
GPIOF0
GPIOF1
GPIOF2
GPIOF3/TACH8
GPIOF4/TACH7
GPIOF5
GPIOF6
GPIOF7
GPIOG0/TACH5
GPIOG1
GPIOG2
GPIOG3
GPIOG4
GPIOG5
GPIOG6
GPIOG7/TACH6
GPIOH0
GPIOH1
SYSOPT1/GPIOH2
SYSOPT0/GPIOH3
GPIOH4
GPIOH5
GPIOH6
GPIOH7
PJP14
B5
A17
B30
A43
A54
VCC1
VCC1
VCC1
VCC1
VCC1
ECE5048-LZY_DQFN132_11X11~D
0.1U_0402_25V6
12
12
CE2
GPIOI0
GPIOI1
GPIOI2/TACH0
GPIOI3
GPIOI4
GPIOI5
GPIOI6
GPIOI7
GPIOJ0
GPIOJ1/TACH1
GPIOJ2/TACH2
GPIOJ3
GPIOJ4
GPIOJ5
GPIOJ6
GPIOJ7
GPIOK0
GPIOK1/TACH3
GPIOK2
GPIOK3
GPIOK4
GPIOK5
GPIOK6
GPIOK7
GPIOL0/PWM7
GPIOL1/PWM8
GPIOL2/PWM0
GPIOL3/PWM1
GPIOL4/PWM3
GPIOL5/PWM2
GPIOL6
GPIOL7/PWM5
GPIOM1
GPIOM3/PWM4
GPIOM4/PWM6
LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
PCICLK
CLKRUN#
LDRQ1#
SER_IRQ
14.318MHZ/GPIOM0
CLK32/GPIOM2
DLAD0
DLAD1
DLAD2
DLAD3
DLFRAME#
DCLKRUN#
DLDRQ1#
DSER_IRQ
BC_INT#
BC_DAT
BC_CLK
PWRGD
OUT65
TEST_PIN
CAP_LDO
DB Version 0.4
+3.3V_ALW
0.1U_0402_25V6
0.1U_0402_10V7K
12
CE3
CE4
A23
B63
A60
A61
B65
A62
B66
A63
DOCK_AC_OFF_EC
B67
AUX_EN_WOWL
A64
A5
B6
A6
GPIO_PSID_SELECT
B7
A7
DOCK_HP_DET
B8
DOCK_MIC_DET
A8
B9
MASK_SATA_LED#
B10
PCIE_WAKE#_R
A10
LED_SATA_DIAG_OUT#
B11
A11
B12
NGFF_CONFIG_0
A12
B60
A57
B64
B68
A9
B1
A18
NGFF_CONFIG_1
A44
NGFF_CONFIG_2
B34
NGFF_CONFIG_3
B39
B51
DIS_BAT_PROCHOT#
A27
LPC_LAD0
A26
LPC_LAD1
B26
LPC_LAD2
B25
LPC_LAD3
A21
LPC_LFRAME#
B22
PCH_PLTRST#_EC
A28
CLK_PCI_SIO
B20
CLKRUN#
A22
LPC_LDRQ1#
B21
A32
B35
B29
D_LAD0
B28
D_LAD1
A25
D_LAD2
A24
D_LAD3
B23
D_LFRAME#
A19
D_CLKRUN#
B24
D_DLDRQ1#
A20
D_SERIRQ
A29
BC_INT#_ECE5048
B31
BC_DAT_ECE5048
A30
BC_CLK_ECE5048
A4
RUNPWROK
B56
B19
RE24 10K_0402_5%
B46
+CAP_LDO
B27
VSS
C1
EP
0.1U_0402_25V6
12
CE5
1 2
0.1U_0402_25V6
12
CE6
SATA2_PCIE6_L1 <6,12>
DOCK_AC_OFF_EC <47>
AUX_EN_WOWL <30>
GPIO_PSID_SELECT <40>
DOCK_HP_DET <21>
DOCK_MIC_DET <21>
MASK_SATA_LED# <39>
LED_SATA_DIAG_OUT# <39>
NGFF_CONFIG_0 <30>
WLAN_DISBL# <28>
NGFF_CONFIG_1 <30>
NGFF_CONFIG_2 <30>
NGFF_CONFIG_3 <30>
DIS_BAT_PROCHOT# <47>
LPC_LAD0 <7,36>
LPC_LAD1 <7,36>
LPC_LAD2 <7,36>
LPC_LAD3 <7,36>
LPC_LFRAME# <7,36>
PCH_PLTRST#_EC <9,27,30,36>
CLK_PCI_SIO <7>
CLKRUN# <9,12,36>
IRQ_SERIRQ <12,36>
EC_32KHZ_MEC5085 <30,36>
D_LAD0 <34>
D_LAD1 <34>
D_LAD2 <34>
D_LAD3 <34>
D_LFRAME# <34>
D_CLKRUN# <34>
D_DLDRQ1# <34>
D_SERIRQ <34>
BC_INT#_ECE5048 <36>
BC_DAT_ECE5048 <36>
BC_CLK_ECE5048 <36>
RUNPWROK <9,36>
4.7U_0603_6.3V6K
12
CE7
+CAP_LDO trace width 20 mils
CLK_PCI_SIO
PCIE_WAKE#_R
RE275@ 0_0402_5%
Stuff RE275 and no stuff RE274 keep E5 design
Stuff RE274 and no stuff RE275 to save two GPIOs on EC(PCH_PCIE_WAKE# should be output with OD)
LID_CL_SIO#
33_0402_5%
12
RE27@EMC@
PCIE_WAKE#_R
WWAN_WAKE#
LPC_LDRQ1#
D_DLDRQ1#
D_SERIRQ
D_CLKRUN#
12
SLICE_BAT_ON
RE17 100K_0402_5%
+3.3V_ALW
100K_0402_5%
12
RE25
0.047U_0402_16V4Z
12
CE8
RE26 10_0402_5%
12
12
RE27610K_0402_5%
RPE8
1
8
2
7
3
6
4 5
100K_0804_8P4R_5%
1 2
12
12
RE3510K_0402_5%
+3.3V_RUN
PCH_PCIE_WAKE# <9,12,36>
RE2740_0402_5% @
LID_CL# <32,39>
PCIE_WAKE# <30>
33P_0402_50V8J
12
CE9@EMC@
A A
E M I d e p o p l o c a t i o n
E M I d e p o p l o c a t i o n
E M I d e p o p l o c a t i o nE M I d e p o p l o c a t i o n
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
ECE5048
ECE5048
ECE5048
LA-A961P
LA-A961P
LA-A961P
1
35 53Tuesday, October 07, 2014
35 53Tuesday, October 07, 2014
35 53Tuesday, October 07, 2014
1.0
1.0
1.0
Page 36
Vinafix.com
BC_DAT_ECE5048
PBAT_SMBDAT
PBAT_SMBCLK
FAN1_PWM
FAN1_TACH
EN_INVPWR
RESET_OUT#
CLK_KBD
DAT_KBD
CLK_MSE
DAT_MSE
MSDATA
DOCK_POR_RST#
RUN_ON
SUS_ON
A_ON
PCH_ALW_ON
+3.3V_ALW
1U_0402_6.3V6K
12
CE30
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
12
+3.3V_RUN
1
2
3
4
5
6
7
8
9
10
100K_0402_5%
12
RE63
JTAG_RST#
100_0402_1%
12
RE65@
+3.3V_ALW
49.9_0402_1%
12
RE71
MSCLK
MSDATA
HOST_DEBUG_TX
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PCH_PLTRST#_EC
5
123
5
10K_8P4R_5%
678
RPE7
4 5
JTAG_TDI
JTAG_TMS
JTAG_CLK
JTAG_TDO
CLK_PCI_LPDEBUG <7>
32 KHz Clock
1 2
MEC_XTAL1
22P_0402_50V8J
YE1
32.768KHZ_12 .5PF_Q13FC1 35000040
12
CE28
+3.3V_ALW
10K_0402_5%
10K_0402_5%
12
12
RE73
RE72
Pin8 5085_TXD f or EC Debug
pin9 5048_TXD f or SBIOS
debug
100K_0402_5%
10K_0402_5%
12
12
RE75@
RE74
+3.3V_ALW +3.3V_ALW_UE2
@
1 2
10U_0603_6.3V6M
PAD-OPEN1x1m
12
CE21
MEC_XTAL2
22P_0402_50V8J
12
CE29
EC5048_TX <35>
+3.3V_ALW
1 2
RE36 100K_040 2_5%
1 2
RE37 2.2K_0402 _5%
1 2
RE43 2.2K_0402 _5%
D D
+3.3V_RUN
1 2
RE48 10K_0402_5%
1 2
RE51 10K_0402_5%
1 2
RE55 100K_0402_5%
1 2
RE56 10K_0402_5%
+5V_RUN
RPE2
1
8
2
7
3
6
4 5
4.7K_8P4R_ 5%
1 2
RE86 10K_0402_5%
1 2
RE277 1 00K_0402_ 5%
RPE10
1
8
2
7
3456
100K_0804 _8P4R_5%
C C
B B
A A
JTAG1 CONN@
@SHORT PADS~D
1
1
2
2
CONN@
JDEG1
ACES_50521-01041-P01
CONN@
JLPDE1
11
G1
12
G2
10
HB_A531015-SCHR21
GND1
GND2
1
2
3
4
5
6
7
8
9
+RTC_CELL
+3.3V_ALW_UE2
+3.3V_ALW_UE2
PJP15
for no-dock : A43 use BC_CLK_ECE1099
for no-dock : B45 use BC_DAT_ECE1099
for no-dock : A42 use BC_INT#_ECE1099
4
1 2
RE32@ 0_0402_5%
0.1U_0402_25V6
0.1U_0402_25V6
@
12
12
12
CE16
CE17
for no-dock : A38 use LCD_TST
for no-dock : B41 use Free
for no-dock : A39 use SLP_ME_CSW_DEV#
for no-dock :B42 use Free
for no-dock : A21 use LID_CL_SIO#
trace width 20 mils
trace width 20 mils
CLK_PCI_MEC
@EMC@
10_0402_5%
12
RE66
@EMC@
4.7P_0402_50V8C
12
CE34
Place close pin A29
0.1U_0402_25V6
12
CE11
0.1U_0402_25V6
12
CE13
0.1U_0402_25V6
12
CE20
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
12
12
12
CE18
CE22
CE23
CE19
SML1_SMBDATA<7>
SML1_SMBCLK<7>
CLK_TP_SIO<37>
DAT_TP_SIO<37 >
CLK_KBD<34>
DAT_KBD<34>
CLK_MSE<34>
DAT_MSE<34>
PBAT_SMBDAT<40>
PBAT_SMBCLK<40>
DOCK_POR_RST#<34> DOCK_SMB_CLK <34>
PS_ID<40>
SUSACK#<9>
BIA_PWM_EC<23>
BC_CLK_ECE5048<35>
BC_DAT_ECE5048<35>
BC_INT#_ECE5048<35>
ACAV_IN_NB<46, 47>
SIO_SLP_S5#<9>
BEEP<21>
BC_CLK_ECE1117<37>
BC_DAT_ECE1117<37>
BC_INT#_ECE1117<37>
SIO_EXT_SMI#<11,12>
SIO_RCIN#<12>
IRQ_SERIRQ<12,35>
PCH_PLTRST#_EC<9,27,30,35>
CLK_PCI_MEC<7>
LPC_LFRAME#<7,35>
LPC_LAD0<7,35>
LPC_LAD1<7,35>
LPC_LAD2<7,35>
LPC_LAD3<7,35>
CLKRUN#<9,12,35>
SIO_EXT_SCI#<12>
MEC_XTAL2 MEC_XTAL2_R
RE61@ 0_0402_5%
EMI depop locat ion
RE79 CE40
240K 4700p
130K 4700p
4700p
33K
*
1K
4700p
BOARD_ID rise time is measured from 5%~68%.
4
3
+RTC_CELL_VBAT
1U_0402_6.3V6K
1
CE14
2
1U_0402_6.3V6K
1
CE15
2
SML1_SMBDATA
SML1_SMBCLK
CLK_TP_SIO
DAT_TP_SIO BAT1_LED#
CLK_KBD
DAT_KBD
CLK_MSE
DAT_MSE
PBAT_SMBDAT
PBAT_SMBCLK
JTAG_TDI
JTAG_TDO
JTAG_CLK
JTAG_TMS
JTAG_RST#
FAN1_TACH
SUS_ON_EC
BIA_PWM_EC
FAN1_PWM
BC_CLK_ECE5048
BC_DAT_ECE5048
BC_INT#_ECE5048
SIO_SLP_S5#
BEEP
BC_CLK_ECE1117
BC_DAT_ECE1117
BC_INT#_ECE1117
SIO_EXT_SMI#
SIO_RCIN#
PCH_PLTRST#_EC
CLK_PCI_MEC
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLKRUN#
SIO_EXT_SCI#
MEC_XTAL1
12
UE2
B64
VBAT
A22
H_VTR
A58
VTR_ADC
B3
VTR
A11
VTR
A26
VTR
B35
VTR
A41
VTR
A52
VTR
A5
GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA
B6
GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK/GANG_DATA0
A37
GPIO110/PS2_CLK2/GPTP-IN6
B40
GPIO111/PS2_DAT2/GPTP-OUT6
A38
GPIO112/PS2_CLK1A
B41
GPIO113/PS2_DAT1A
A39
GPIO114/PS2_CLK0A
B42
GPIO115/PS2_DAT0A
B59
GPIO154/I2C1C_DATA/PS2_CLK1B/GANG_DATA5
A56
GPIO155/I2C1C_CLK/PS2_DAT1B/GANG_DATA6
A51
GPIO145/I2C1K_DATA/JTAG_TDI
B55
GPIO146/I2C1K_CLK/JTAG_TDO
B56
GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK
A53
GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS
B47
JTAG_RST#
B22
GPIO050/FAN_TACH1/GTACH0/GANG_START
A21
GPIO051/FAN_TACH2/GANG _MODE
B23
GPIO052/FAN_TACH3/GTACH1/GANG_ERROR
B24
GPIO053/PWM0
A23
GPIO054/PWM1/GPWM1
B25
GPIO055/PWM2
A24
GPIO056/PWM3/GPWM0
A43
GPIO123/BCM_A_CLK
B45
GPIO122/BCM_A_DAT
A42
GPIO121/BCM_A_INT#
B20
GPIO032/BCM_E_CLK
A18
GPIO031/GPTP-OUT2/BCM_E_DAT
B19
GPIO030/GPTP-IN2/BCM_E_INT#/GANG_DATA7
A20
GPIO047/LSBCM_D_CLK
B21
GPIO046/LSBCM_D_DAT/GANG_STROBE
A19
GPIO045/LSBCM_D_INT#
A6
GPIO011/nSMI
A27
GPIO061/LPCPD#
A28
SER_IRQ
B30
LRESET#
A29
PCI_CLK
B31
LFRAME#
A30
LAD0
B32
LAD1
A31
LAD2
B33
LAD3
A32
CLKRUN#
A33
GPIO100/NEC_SCI
A61
XTAL1
A62
XTAL2
AGND
VSS
B66
B11
15mil
+RTC_CELL
12
POWER_SW_IN#
12
GPIO124/GPTP-OUT5/UART_RX/V2P_COUT_LO1
GPIO116/MSDATA/V2P_COUT_LO/TAP_SEL_STRAP
GPIO125/GPTP-IN5/PECI_REQUEST#/GANG_BUSY
GPIO013/I2C1H_CLK/I2C2D_CLK/GANG_DATA3
VSS_ADC
VR_CAP
VSS_RO
H_VSS
B60
B12
B54
B18
4.7U_0603_6.3V6K
+VR_CAP
12
CE31
100K_0402_5%
RE31
1 2
RE33 10K_04 02_5%
1U_0402_6.3V6K
CE12
GPIO014/GPTP-IN7/RC_ID3
GPIO120/UART_TX/V2P_COUT_HI1
GPIO060/KBRST/BCM_B_INT#
GPIO101/ECGP_SCLK
GPIO103/ECGP_MISO
GPIO105/ECGP_MOSI
GPIO102/BCM_C_INT#
GPIO117/MSCLK/V2P_COUT_HI
GPIO156/LED1/GANG_DATA1
GPIO153/LED2/GANG_DATA4
GPIO027/GPTP-OUT1
GPIO001/ECSPI_CS1/32KHZ_OUT
GPIO015/GPTP-OUT7
GPIO017/GPTP-OUT8
GPIO107/NRESET_OUT
GPIO151/GPTP-IN4/GANG_DATA2
GPIO152/GPTP-OUT4
GPIO003/I2C1A_DATA
GPIO005/I2C1B_DATA/BCM_B_DAT
GPIO006/I2C1B_CLK/BCM_B_CLK
GPIO012/I2C1H_DATA/I2C2D_DATA
GPIO130/I2C2A_DATA/BCM_C_DAT
GPIO131/I2C2A_CLK/BCM_C_CLK
GPIO132/I2C1G_DATA
GPIO140/I2C1G_CLK
GPIO141/I2C1F_DATA/I2C2B_DATA
GPIO142/I2C1F_CLK/I2C2B_CLK
GPIO143/I2C1E_DATA
GPIO002/THERMTRIP3#
GPIO024/THSEL_STRAP
PROCHOT_IN#/PROCHOT_IO#
EP
C1
1U_0402_6.3 V6K
GPIO021/RC_ID1
GPIO020/RC_ID2
GPIO025/UART_CLK
VCC_PWRGD
GPIO104/SLP_S0#
GPIO127/A20M
GPIO157/LED0
GPIO026/GPTP-IN1
GPIO016/GPTP-IN8
GPIO004/I2C1A_CLK
GPIO144/I2C1E_CLK
SYSPWR_PRES
VCI_OVRD_IN
VREF_PECI
DN1_DP1A/THERM
DP1_DN1A/VREF_T
THERMTRIP2#
MEC5085-LZY_DQFN132_11X11
ESR <2ohms
+3.3V_RUN
10K_0402_5%
12
RUNPWROK
RE67
DMN66D0LDW-7_SOT363-6
34
QE2B
5
REV
X00
X01
X02
A00
BOARD_ID
+3.3V_ALW
12
12
+3.3V_ALW
100K_0402_5%
12
RE68
RUN_ON#
DMN66D0LDW-7_SOT363-6
6
QE2A
RUN_ON<36,38>
33K_0402_5%
RE79
4700P_0402_25V7K
CE40
2
1
+3.3V_ALW
10K_0402_5%
12
RE81
FWP#
10K_0402_5%
RE82@
1 2
3
1 2
GPIO106
VCI_OUT
VCI_IN0#
VCI_IN1#
VCI_IN2#
VCI_IN3#
PECI_DAT
DN2_DP2A
DP2_DN2A
DN3_DP3A
DP3_DN3A
DN4_DP4A
DP4_DN4A
V_ISYS0
V_ISYS1
CE10@
nFWP
BGP0
VIN
VSET
VCP
2
+RTC_CELL
100K_0402_5%
12
RE62
RE42 10K_ 0402_5%
1U_0402_6.3V6K
12
CE45
for no-dock : B2 use Free
RE57 1K_040 2_5%
100K_0402_5%
12
RE58
PECI_EC <9>
Location
DIMM
C
2
B
E
QE3
3 1
MMBT3904WT1G_SC70-3~D
MMBT3904WT1G_SC70-3~D
E
31
B
2
C
QE7
C
2
B
E
QE6
3 1
MMBT3904WT1G_SC70-3~D
1 2
1 2
CPU
VGA
V.R
POWER_SW#_MB <9,32,39>
A10
B10
BOARD_ID
B8
B27
LAN_WAKE#
B44
HOST_DEBUG_TX
B46
ME_FWP_EC
B26
RUNPWROK
A25
EN_INVPWR
B36
B37
B38
USB_PWR_SHR_EN#
A34
PCH_ALW_ON
A35
SIO_SLP_S3#
A36
PCH_DPWROK
A40
MSDATA
B43
MSCLK
A45
PCH_RSMRST#
B65
FWP#
B57
B1
A55
BAT2_LED#
A1
ALW_PWRGD_3V_5V_EC
B28
B2
A8
B9
RUN_ON_EC
A9
PM_APWROK
B39
RESET_OUT#
A44
PCH_PCIE_WAKE#
A54
AC_PRESENT
B58
SIO_PWRBTN#
A3
DOCK_SMB_DAT DOCK_SMB_DAT
B4
DOCK_SMB_CLK DOCK_SMB_CLK
A4
A_ON
B5
B7
A7
B48
GPU_SMBDAT
B49
GPU_SMBCLK
A47
CHARGER_SMBDAT
B50
CHARGER_SMBCLK
B52
A49
B53
USH_SMBDAT
A50
USH_SMBCLK
A59
B62
A64
ACAV_IN
A60
ALWON
B67
POWER_SW_IN#
A63
DOCK_PWR_SW#
B63
VCI_IN2#
B68
POA_WAKE#
B51
+PECI_VREF
A48
PECI_EC_RPECI_EC_R
B13
REM_DIODE1_N
A13
REM_DIODE1_P
B14
REM_DIODE2_N
A14
REM_DIODE2_P
A15
B16
A16
REM_DIODE4_N
B17
REM_DIODE4_P
B15
A17
VSET_5085
A12
B34
THERMATRIP2#
A2
THERMATRIP3#
B29
THSEL_STRAP
A46
H_PROCHOT#
B61
1 2
A57
RE64 4 .7K_0402_5 %
DOCK_PWR_SW#
AC_DIS <40,46,47 >
mCARD_PCIE#_SATA <6,12>
LAN_WAKE# <12,28>
ME_FWP_EC <6>
RUNPWROK <9,35>
EN_INVPWR <23>
SIO_SLP_S4# <9>
SIO_SLP_LAN# <9,28>
USB_PWR_SHR_EN# <31,35>
PCH_ALW_ON <38>
SIO_SLP_S3# <9>
PCH_DPWROK <9>
PCH_RSMRST# <37>
BREATH_LED# <34,39>
BAT1_LED# <39>
BAT2_LED# <39>
SIO_SLP_A# <9>
EC_32KHZ_MEC5085 <30,35>
ME_SUS_PWR_ACK <9>
PM_APWROK <9>
RESET_OUT# <9,15>
PCH_PCIE_WAKE# <9,12,35>
AC_PRESENT <9,12>
SIO_PWRBTN# <9>
DOCK_SMB_DAT <34>
A_ON <38>
SIO_EXT_WAKE# <9,12>
SYS_PWROK <9>
ENVDD_PCH <10,23>
CHARGER_SMBDAT <46>
CHARGER_SMBCLK <46 >
SIO_SLP_SUS# <9>
PBAT_PRES# <40,46,47>
USH_SMBDAT <27>
USH_SMBCLK <27>
ACAV_IN <46,47>
ALWON <41>
1 2
RE60 43_0402_5 %
1 2
CE24 220 0P_0402_ 50V7K
1 2
CE26 220 0P_0402_ 50V7K
1 2
CE27 220 0P_0402_ 50V7K
CE24, CE26, CE27 Place near UE2
I_ADP <46>
H_PROCHOT# <9,45,46 >
I_BATT <46>
I_SYS <46>
S e t t i n g f o r T h e r m a l D e s i g n
S e t t i n g f o r T h e r m a l D e s i g n
S e t t i n g f o r T h e r m a l D e s i g nS e t t i n g f o r T h e r m a l D e s i g n
Thermal diode mapping
5085 Channel
DP1/DN1
DP2/DN2
DN2a/DP2a WiGig
DP3/DN3
DP4/DN4
Place under CPU
Place CE35 close to the QE3 as possible
100P_0402_50V8J
CE35@
1 2
DP2/DN2 for SODIMM on QE5, place QE5 close
to SODIMM and CE37 close to QE5
DN2a/DP2a for WiGig on QE7, place QE7 close
to WiGig/WLAN and CE46 close to QE7
100P_0402_50V8J
12
CE46@
DP4/DN4 for Skin on QE6, place QE6 close to Vcore VR choke.
100P_0402_50V8J
@
CE39
1 2
SIO_SLP_S4#
SUS_ON_EC
SIO_SLP_S3#
RUN_ON_EC
ALW_PWRGD_3V_5V_EC
12
REM_DIODE1_P
REM_DIODE1_N
100P_0402_50V8J
12
CE37@
REM_DIODE4_P
REM_DIODE4_N
CE44@
1 2
1U_0402_6.3 V6K
@
@
+3.3V_ALW2
0.1U_0402_25V6
CE25
C
2
B
E
QE5
3 1
MMBT3904WT1G_SC70-3~D
DOCK_PWR_BTN# <34>
1 2
RE282@ 0_0402_ 5%
1 2
RE281 0_0402_5%@
1 2
RE280 0_0402_5%
1 2
RE279@ 0_0402_ 5%
1 2
RE283 0_0402_5%
+1.05V_RUN
+1.05V_RUN
H_VR_EN<15,45>
REM_DIODE2_P
REM_DIODE2_N
20130726 same as Goliad
0.1U_0402_25V6
12
Rest=1.58K , Tp=96 degree
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
1
SUS_ON <38,42>
RUN_ON <36,3 8>
ALW_PWRGD_3V_5V <37, 41>
RPE3
1
2
JFAN1
CONN@
GND1
GND2
1
1
2
2
3
3
4
4
5
6
3
4 5
2.2K_0804_ 8P4R_5%
RPE5
1
2
3
4 5
100K_0804 _8P4R_5%
RPE6
1
2
3
4 5
10K_8P4R_5 %
1 2
FAN1_PWM
FAN1_TACH
12
GPU_SMBDAT
GPU_SMBCLK
BC_DAT_ECE1117
POA_WAKE#
VCI_IN2#
THERMATRIP3#
CHARGER_SMBDAT
CHARGER_SMBCLK
PCH_RSMRST#
ACES_50271-00 40N-001
reserve for DC fan
1 2
RE70 2.2 K_0402_5%
1 2
@
RE284 2.2 K_0402_5 %
H_THERMTRIP#<12>
1.58K_0402_1%
12
CE38
RE77
DELL CONFIDENTIAL/PROPRIETARY
2
B
THSEL_STRAPVSET_5085
RE78 1K_0402_5%
Channel 1
Thermal Monitoring Interface Strap Option
HIGH
LOW
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
+3.3V_ALW
8
7
6
+3.3V_ALW
8
7
6
+3.3V_ALW
8
7
6
RE8847K_0 402_5%
10U_0603_6.3V6M
RB751S40T1G_SOD523-2
@
CE32
2 1
+3.3V_ALW
8.2K_0402_5%
12
RE69
MMBT3904WT1G_SC70-3
1
C
QE4
E
3
1 2
Thermistor Readings
Diode Readings
MEC5085
MEC5085
MEC5085
LA-A961P
LA-A961P
LA-A961P
+3.3V_RUN
+RTC_CELL
+5V_RUN
DE1
THERMATRIP2#
12
0.1U_0402_25V6
CE36
36 53Tuesday, October 07, 2014
36 53Tuesday, October 07, 2014
36 53Tuesday, October 07, 2014
1.0
1.0
1.0
Page 37
Vinafix.com
5
D D
4
3
2
1
Touch Pad
+3.3V_RUN +3.3V_TP
PJP16
@
1 2
PAD-OPEN1x1m
DAT_TP_SIO<36>
CLK_TP_SIO<36>
C C
+3.3V_TP
4.7K_0402_5%
12
12
4.7K_0402_5%
12
RZ18
RZ19
DAT_TP_SIO
CLK_TP_SIO
10P_0402_50V8J
10P_0402_50V8J
12
CZ30@EMC@
CZ31@EMC@
Keyboard
JKBTP1 CONN@
1
KB_DET#<9,12>
+5V_RUN
+3.3V_ALW
BC_INT#_ECE1117<36>
BC_DAT_ECE1117<36>
BC_CLK_ECE1117<36>
+3.3V_TP
DAT_TP_SIO
CLK_TP_SIO
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
GND1
18
GND2
ACES_50506-01641-P01
+5V_RUN+3.3V_ALW+3.3V_TP
0.1U_0402_25V6
0.1U_0402_25V6
12
12
CZ27@
0.1U_0402_25V6
12
CZ28@
Place close to JKBTP1
CZ29@
20130726 same as Goliad
EMI depop location
RSMRST circuit
+5V_ALW
@
33_0402_5%
12
RZ21
@
UZ5
1
VCC
RESET#
2
GND
RT9818A-44GU3_SC70-3
3
12
+5V_ALW_U41
0.01U_0402_16V7K
@
CZ35
B B
ALW_PWRGD_3V_5V<36,41>
RSMRST#
+3.3V_ALW
10K_0402_5%
12
@
RZ22
PCH_RSMRST#<36>
1 2
RZ51@ 0_0402_5%
1
2
+3.3V_ALW
5
P
B
A
G
3
CZ34@
1 2
0.1U_0402_25V6
4
O
UZ6
TC7SH08FU_SSOP5~D
PCH_RSMRST#_Q <9>
@IO FFC
Part Number
DA30000GZ00 FPC 0VN LF-9591P REV0 M/B-IO/B
@eDP TS Cable
Part Number
DC02C004S00 H-CONN SET 0VN MB-LCD-LED-CAM-TS
@eDP Cable
Part Number
DC02C004T00 H-CONN SET 0VN MB-LCD-LED-CAM
@SATA Cable
Part Number
DC02C004K00 H-CONN SET 0VN MB-HDD
@DC-IN Cable
Part Number
DC30100MF00 CONN SET 0VN DCJACK-MB 2DW1003-038110F
@RTC BATT
Part Number
DC30100MF00 CONN SET 0VN DCJACK-MB 2DW1003-038110F
@FAN
Part Number Description
DC28A000800
Description
Description
Description
Description
Description
Description
FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA
@MEDIA Board FFC
Part Number
NBX0001CW00 FFC 8P G P0.5 PAD0.3 50MM MB-MEDIA/B 0VN
@KBTP FFC
Part Number
NBX0001CZ00 FFC 15P G P.5 PAD.3 85MM MB-NFC MODU 0VN
@NFC Board FFC
Part Number
NBX0001CZ00 FFC 15P G P.5 PAD.3 85MM MB-NFC MODU 0VN
@USH Board FFC
Part Number
NBX0001CY00 FFC 20P G P0.5 PAD=0.3 75MM MB-USH/B 0VN
@FP FFC
Part Number
NBX0001D100 FFC 6P G P0.5 PAD=0.3 75MM USH/B-FP 0VN
@Speak
Part Number Description
PK230003Q0L
Description
Description
Description
Description
Description
SPK PACK ZJX 2.0W 4 OHM FG
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Keyboard
Keyboard
Keyboard
LA-A961P
LA-A961P
LA-A961P
37 53Tuesday, October 07, 2014
37 53Tuesday, October 07, 2014
37 53Tuesday, October 07, 2014
1
1.0
1.0
1.0
Page 38
Vinafix.com
5
4
3
2
1
+1.05V_MODPHY
+3.3V_ALW2
100K_0402_5%
2
12
RZ16
MPHYP_PWR_EN#
DMN66D0LDW-7_SOT363-6
6
QZ10A
1
D D
MPHYP_PWR_EN<12>
+5V_ALW
5
+1.05V_M +1.05V_MODPHY
100K_0402_5%
12
RZ5
1.05V_MODPHY_EN
DMN66D0LDW-7_SOT363-6
34
QZ10B
QZ6
SI3456DDV-T1-GE3_TSOP6
D
6
S
45
2
1
G
3
220P_0402_50V7K
1
CZ25
2
PJP36@
1 2
PAD-OPEN1x1m
10U_0603_6.3V6M
CZ38
12
+1.05V_MODPHY+1.05V_RUN
if support MODPHY off keep DSC solution
C C
MODPHY timing spec 0.7V/us and <65us
+1.05V_M
Max Rating: 2495 mA
RZ52 0.01_1206_1%@
RUN_ON
A_ON
+3.3V_M/+3.3V_SUS source
+1.05V_RUN/+3.3V_ALW_PCH source
For No-Vpro HW configs
1 2
For No-Vpro HW configs
1 2
RZ46 0_0603_5%@
PCH_ALW_ON<36>
1 2
RZ41
@
1 2
RZ42@ 0_0402_5%
SUS_ON<36,42>
A_ON<36>
+1.05V_RUN+1.05V_M
RUN_ON<36>
0_0402_5%
+3.3V_M+3.3V_RUN
+1.05V_M
+5V_ALW
+3.3V_ALW
+5V_ALW
EN_+V1.05SP <43>
+3.3V_ALW
UZ7
1
VIN1
2
VIN1
3
ON1
4
VBIAS
5
ON2
6
VIN2
VIN27VOUT2
TPS22966DPUR_SON14_2X3
UZ8
1
VIN1
2
VIN1
3
ON1
4
VBIAS
5
ON2
6
VIN2
VIN27VOUT2
TPS22966DPUR_SON14_2X3
VOUT1
VOUT1
GND
VOUT2
GPAD
VOUT1
VOUT1
GND
VOUT2
GPAD
14
13
12
CT1
11
10
CT2
9
8
15
14
13
12
CT1
11
10
CT2
9
8
15
+1.05V_RUN
+1.05V_RUN_UZ7
+3.3V_ALW_PCH_UZ7
+3.3V_SUS
12
+3.3V_SUS_UZ8
CZ40 0.1U_0402_10V7K@
CZ41 470P_0402_50V7K
CZ42 470P_0402_50V7K
+3.3V_M_UZ8
12
RZ53@
0_0603_5%
CZ39 0.1U_0402_10V7K@
1 2
CZ62 470P_0402_50V7K
1 2
CZ60 470P_0402_50V7K
PJP29@
1 2
0.1U_0402_10V7K
12
PAD-OPEN1x1m
@
CZ56
PJP19
PAD-OPEN1x1m
@
1 2
1 2
1 2
1 2
RZ47@ 0_0603_5%
0.1U_0402_10V7K
12
CZ43
@
12
+3.3V_ALW_PCH
+3.3V_M
B B
A A
+3.3V_RUN/+5V_RUN source
+5V_ALW
RUN_ON
+3.3V_ALW
UZ9
1
VIN1
VOUT1
2
VIN1
VOUT1
3
ON1
VBIAS
GND
ON2
VIN2
VOUT2
VIN27VOUT2
GPAD
CT1
CT2
4
5
6
TPS22966DPUR_SON14_2X3
14
13
12
11
10
9
8
15
+5V_RUN
+5V_RUN_UZ9
+3.3V_RUN_UZ9
12
PJP21
PAD-OPEN1x3m
@
1 2
CZ44 0.1U_0402_10V7K@
1 2
CZ45 470P_0402_50V7K
1 2
CZ46 1000P_0402_50V7K
1 2
0.1U_0402_10V7K
PAD-OPEN1x3m
12
PJP22@
CZ47
@
+3.3V_RUN
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Power control
Power control
Power control
LA-A961P
LA-A961P
LA-A961P
1
38 53Tuesday, October 07, 2014
38 53Tuesday, October 07, 2014
38 53Tuesday, October 07, 2014
1.0
1.0
1.0
Page 39
Vinafix.com
5
4
3
2
1
HDD LED solution for White LED
+3.3V_ALW
10K_0402_5%
12
RZ24
QZ3B
D D
SATA_ACT#<6>
MASK_SATA_LED#<35>
LED_SATA_DIAG_OUT#<35>
DMN66D0LDW-7_SOT363-6
5
DMN66D0LDW-7_SOT363-6
34
RB751S40T1G_SOD523-2
RB751S40T1G_SOD523-2
QZ14B
34
5
DZ3
1 2
DZ4
1 2
SYS_LED_MASK#
MASK_BASE_LEDS#
QZ3A
DMN66D0LDW-7_SOT363-6
126
QZ14A
DMN66D0LDW-7_SOT363-6
126
SATA_LED#
2
+5V_ALW
2
PANEL_HDD_LED#
QZ4
DDTA114EUA-7-F_SOT323-3
1 3
1 2
RZ27 220_0402_5%
QZ12
DDTA114EUA-7-F_SOT323-3
1 3
1 2
RZ36 150_0402_5%
PANEL_HDD_LED# <23>
LED6
2 1
SATA_LED
LTW-193ZDS5_WHITE
Battery LED
BAT2_LED#<36>
BAT1_LED#<36>
QZ5B
DMN66D0LDW-7_SOT363-6
5
MASK_BASE_LEDS#
QZ5A
DMN66D0LDW-7_SOT363-6
126
MASK_BASE_LEDS#
+5V_ALW +5V_ALW
LED7
34
BAT2_LED#_Q BATT_WHITE#
RZ25 390_0402_5%
RZ43 390_0402_5%
BAT1_LED#_Q
RZ28 330_0402_5%
RZ44 390_0402_5%
1 2
1 2
1 2
1 2
BATT_YELLOW#
LTW-295DSKS-5A_YEL-WHITE
BATT_WHITE_LED# <23>
BATT_YELLOW_LED# <23>
21
W
43
Y
WLAN LED solution for White LED
+3.3V_ALW
100K_0402_5%
SYS_LED_MASK#<28,35>
12
RZ31
DMN66D0LDW-7_SOT363-6
MASK_BASE_LEDS#
LID_CL#<32,35>
1
QZ7A
2
1
2
+3.3V_ALW
B
A
6
CZ48@
1 2
0.1U_0402_25V6
5
P
4
O
G
UZ10
TC7SH08FU_SSOP5~D
3
MASK_BASE_LEDS#
C C
WIRELESS_LED#<30,35>
B B
+5V_ALW
2
QZ9
DDTA114EUA-7-F_SOT323-3
1 3
1 2
RZ33 390_0402_5%
WLAN_LED
LED5
2 1
LTW-193ZDS5_WHITE
Breath LED
BREATH_LED#<34,36>
PWR SW
QZ7B
DMN66D0LDW-7_SOT363-6
34
5
MASK_BASE_LEDS#
POWER_SW#_MB<9,32,36>
BREATH_LED#_Q
POWER_SW#_MB
1 2
BREATH_WHITE_LED
RZ32 150_0402_5%
1 2
RZ34 220_0402_5%
BREATH_WHITE_LED#
SW2
2
4
SKRBAAE010_4P~D
POWER & INSTANT ON SWITCH
BREATH_WHITE_LED <32>
BREATH_WHITE_LED# <23>
1
3
LED Circuit Control Table
SYS_LED_MASK# LID_CL#
Fiducial Mark
FD1@
1
FIDUCIAL MARK~D
FD2@
A A
1
FIDUCIAL MARK~D
FD3@
1
FIDUCIAL MARK~D
FD4@
1
FIDUCIAL MARK~D
5
Mask All LEDs (Sniffer Function)
Mask Base MB LEDs (Lid Closed)
Do not Mask LEDs (Lid Opened) 11
H2@
H4@
H_2P8
H_3P8
H1@
H3@
H_2P8
H_2P8
1
1
H7@
H9@
H8@
H_3P8
H_3P8
1
1
H6@
H5@
H_2P8
H_2P8
H_2P8
1
H_3P8
1
1
H10@
H_3P3
1
1
1
H13@
H12@
H11@
H_2P8
H_2P8
H_3P3
H_2P8
1
1
1
H19@
H21@
H_3P1
1
1
H_2P8
H18@
1
0
1 0
H15@
H14@
H16@
H27@
H_2P8
H_2P8
H_2P8
1
1
1
1
H20@
H22@
H_2P1N
H_3P1
1
H_2P1X2P6
1
4
X
ST2@
CLIP_C5P5
1
ST3@
CLIP_C5P5
1
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PAD, LED
PAD, LED
PAD, LED
LA-A961P
LA-A961P
LA-A961P
1
39 53Tuesday, October 07, 2014
39 53Tuesday, October 07, 2014
39 53Tuesday, October 07, 2014
1.0
1.0
1.0
ST1@
H23@
CLIP_C5P5
1
1
Page 40
Vinafix.com
5
4
3
2
1
+COINCELL
COIN RTC Battery
12
PR1
+3.3V_RTC_LDO
D D
Primary Battery Connector
LLTOP_ALLTOP C144LS-109A9-L 9P BATT P2
12
PC3
2200P_0402_50V7K~D
C C
B B
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
GND
11
GND
@
PBATT1
PC22
PBAT_SMBCLK_C
PBAT_SMBDAT_C
PBAT_PRES#_C
GND
PC22
1
EMC@
PD1
TVNST52302AB0_SOT523-3
2
3
PL3
EMC@
BLM15AG102SN1D_2P
1
PD2
TVNST52302AB0_SOT523-3
2
3
PRP2
100_0804_8P4R_5%
PD5
AZC199-02SPR7G_SOT23-3
EMC12U@
12
2
3
PD5
EMC@
PESD5V0U2BT_SOT23-3
1
EMC@
18
27
36
45
100K_0402_1%
15K_0402_1%
PR10
PR12
1 2
1 2
PBATT+_C
PBAT_SMBCLK <36>
PBAT_SMBDAT <36>
PR7
@
1 2
0_0402_5%
1 3
D
G
2
C
2
PQ3
B
MMST3904-7-F_SOT323~D
E
3 1
33_0402_5%
S
PQ2
FDV301N-G_SOT23-3
PL1
EMC@
FBMJ4516HS720NT_2P~D
1 2
EMC@
PL2
FBMJ4516HS720NT_2P~D
1 2
PR9
1 2
+5V_ALW
12
PR11
10K_0402_1%
+PBATT
PR13
@
1 2
10K_0402_5%
+3.3V_ALW
12
SDMK0340L-7-F_SOD323-2~D
SLICE_BAT_PRES#<34,35,47>
+3.3V_ALW
PR8
2.2K_0402_5%
1 2
BAS40CW SOT-323
PR2
100K_0402_5%
PBAT_PRES# <36,46,47>
PQ1
PD4
1 2
1 2
NB_PSID_TS5A63157NB_PSID
PSID_DISABLE# <35>
DMG2301U-7 1P SOT23-3
1 3
1
2
PR6
@
0_0402_5%
DOCK_PSID<34> GPIO_PSID_SELECT <35>
12
1K_0402_5%
+Z4012
2
3
PD3
1
3
2
PC4
1500P_0402_50V7K
PU1
1
NO
2
GND
NC3COM
TS5A63157DCKR_SC70-6~D
+COINCELL
+RTC_CELL
1
PC1
1U_0603_10V4Z
2
DOCK_SMB_ALERT# <34,35>
6
IN
5
+5V_ALW
V+
4
PS_ID <36>
PT3@
PAD~D
JRTC1
@
1
3
1
G
4
22G
TYCO_2-1775293-2~D
PC5
DCX124EK-7-F PNP/NPN_SC74-6~D
AC_DIS <36,46,47>
0.022U_0805_50V7K
DC_IN+ Source
+DC_IN
1 2
4
12
PR14
1M_0402_5%
FDMC6679AZ_MLP8-5
1
2
3 5
1 2
10K_0402_5%
12
PR18
1M_0402_5%
PQ4
PR17
4
SOFT_START_GC <47>
+DC_IN_SS
12
PR15
100K_0402_5%
12
PC10
10U_0805_25V6K
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
+DCIN
+DCIN
+DCIN
LA-A961P
LA-A961P
LA-A961P
1
40 53Tuesday, October 07, 2014
40 53Tuesday, October 07, 2014
40 53Tuesday, October 07, 2014
1.0
1.0
1.0
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEIT HER THIS SHEET NOR THE IN FORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTR ONICS, INC.
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
EMC12U@
PL4
EMC@
1 2
PJP1
1 2
PAD-OPEN 1x3m
10U_0805_25V6K
EMC15U@
@
2
12
12
PC11
0.1U_0603_25V7K
@EMC@
16
PR16
4.7K_0805_5%
@
PQ6B
4 3
5
PQ6A
@
DCX124EK-7-F PNP/NPN_SC74-6~D
10U_0805_25V6K
FBMJ4516HS720NT_2P
PJPDC1
@
7
GND
6
GND
5
-DCIN_JACK
5
4
4
3
+DCIN_JACK
3
A A
2
2
1
1
ACES_50299-0050N-001
12
PC9
EMC@
1000P_0603_50V7K
5
Page 41
Vinafix.com
PC105
A
PC106
PC105
PC106
B
C
D
E
+3V5V_PWR_SRC
PC105
2200P_0402_50V7K
@EMC@
2.2UH_7.8A_20%
1 2
+
PC111
680P_0603_50V7K
EMC14U@
PC111
680P_0603_50V7K
EMC15U@
2200P_0402_50V7K
EMC15U@
12
12
PL101
12
PC101
PC106
0.1U_0402_25V6
10U_0805_25V6K
@EMC@
PR111
4.7_1206_5%
@EMC@
PC111
680P_0603_50V7K
@EMC@
0.1U_0402_25V6
EMC15U@
PQ100
123
SIS412DN-T1-GE3_POWERPAK8-5
12
PQ102
123
SNUB_3V
SI7716ADN-T1-GE3_POWERPAK8-5
12
5
5
ALW_PWRGD_3V_5V<36,37>
4
0.1U_0603_25V7K
4
ALWON<36>
B
+3.3V_ALW
PR107
100K_0402_1%
@
PR108
1 2
0_0402_5%
PC109
1 2
2.2_0603_5%
1 2
BST_3V_C BST_3V
+3V5V_PWR_SRC
EN
1 2
PR100
6.49K_0402_1%
1 2
PR102
10K_0402_1%
1 2
1 2
PGOOD_3V_5V
PR110
@
PR113
0_0402_5%
EMC@
+3.3V_ALW2
12
PR105
20K_0402_1%
UG_3V
LG_3V
12
PC119
1U_0603_10V6K
+3.3V_RTC_LDO
PR101
15K_0402_1%
1 2
12
12
PC100
0_0402_5%
4.7U_0603_10V6K
3
4
5
CS2
VFB2
VREG3
TPS51285BRUKR_QFN20_3X3
DRVL211VIN12VREG5
13
12
PC117
0.1U_0603_25V7K
EN
SW2
PU100
6
7
10
9
8
FB_3V
PR103
@
EN2
PGOOD
DRVH2
VBST2
SW2
+5V_ALWP
+3.3V_ALWP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
PR104
10K_0402_1%
1 2
12
16.9K_0402_1%
1
CS1
DRVH1
DRVL1
15
PAD
VO1
VCLK
VBST1
SW1
PR106
21
14
PR114
200_0402_1%
19
1 2
16
UG_5V
PR109
17
18
2.2_0603_5%
1 2
BST_5V BST_5V_C
SW1
LG_5V
+5V_ALW2
PJP101
1 2
PAD-OPEN 1x3m
PJP102
1 2
PAD-OPEN 1x3m
PR112
4.7_1206_5%
EMC14U@
PR112
4.7_1206_5%
EMC15U@
+5V_ALW
+3.3V_ALW
PC110
0.1U_0603_25V7K
1 2
PC114
680P_0603_50V7K
EMC14U@
PC114
680P_0603_50V7K
EMC15U@
D
FB_5V
2
VFB1
EN1
20
EN
12
PC118
4.7U_0603_10V6K
+3V5V_PWR_SRC
12
12
SNUB_5V
12
PC102
3.3UH_6.3A_20%
1 2
PR112
4.7_1206_5%
@EMC@
PC114
680P_0603_50V7K
@EMC@
10U_0805_25V6K
PL102
PC115
220U_6.3V_M
5
4
4
PQ101
123
SIS412DN-T1-GE3_POWERPAK8-5
5
PQ103
123
SI7716ADN-T1-GE3_POWERPAK8-5
5VALWP
TDC 3.5 A
Peak Current 5.0 A
OCP Current 6.0 A
TYP MAX
H/S Rds(on) 24mohm , 30mohm
L/S Rds(on) 13.5mohm , 16.5mohm
Choke DCR 25mohm
CAP ESR 18mohm
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
+5V_ALW/3.3V_ALW
+5V_ALW/3.3V_ALW
+5V_ALW/3.3V_ALW
LA-A961P
LA-A961P
LA-A961P
E
1
+
2
+5V_ALWP
41 53Tuesday, October 07, 2014
41 53Tuesday, October 07, 2014
41 53Tuesday, October 07, 2014
1.0
1.0
1.0
2200P_0402_50V7K
EMC12U@
1 1
2200P_0402_50V7K
EMC14U@
2 2
0.1U_0402_25V6
EMC12U@
PC105
PC106
0.1U_0402_25V6
EMC14U@
past green mask in X-build phase
PL100
@EMC@
1UH +-20% 6.6A
1 2
PJP100
1 2
PAD-OPEN 1x3m
+PWR_SRC
+3.3V_ALWP
1
PC113
220U_6.3V_M
2
3 3
3VALWP
TDC 4.5 A
Peak Current 6.4 A
OCP Current 7.68 A
TYP MAX
4 4
H/S Rds(on) 24mohm , 30mohm
L/S Rds(on) 13.5mohm , 16.5mohm
Choke DCR 15.5mohm
CAP ESR 18mohm
PR111
4.7_1206_5%
EMC14U@
PR111
4.7_1206_5%
EMC15U@
A
Page 42
Vinafix.com
PC203
5
PC206
PC203
PC206
4
PC203
PC206
3
2
1
0.675Volt +/- 5%
2200P_0402_50V7K
EMC15U@
+PWR_SRC
D D
0.1U_0402_25V6
PJP200
PAD-OPEN 1x2m~D
EMC15U@
21
2200P_0402_50V7K
1.35V_B+
12
12
PC200
10U_0805_25V6K
EMC12U@
PC201
@
10U_0805_25V6K
+1.35V_MEN_P
PL200
1UH_11A_20%
1 2
220U_D2_2VY_R17M
1
PC207
C C
PR203
4.7_1206_5%
EMC14U@
PR203
4.7_1206_5%
EMC15U@
B B
+
2
PC208
680P_0603_50V7K
EMC14U@
PC208
680P_0603_50V7K
EMC15U@
12
PR203
4.7_1206_5%
@EMC@
SNUB_1.35V
12
PC208
@EMC@
680P_0603_50V7K
0.1U_0402_25V6
EMC12U@
12
12
PC206
PC203
0.1U_0402_25V6
2200P_0402_50V7K
@EMC@
@EMC@
SIS412DN-T1-GE3_POWERPAK8-5
SI7716ADN-T1-GE3_POWERPAK8-5
SUS_ON<36,38>
PQ200
PQ201
@
1 2
0_0402_5%
2200P_0402_50V7K
EMC14U@
5
4
123
5
4
123
PR207
12
0.1U_0402_25V6
PC215
@
.1U_0402_16V7K
EMC14U@
BOOT_1.35V_C
12
PC204
1 2
2.2_0603_5%
0.22U_0603_16V7K
1 2
5.1_0603_5%
+5V_ALW
PR200
PR202
S5_1.35V
BOOT_1.35V
PR201
19.6K_0402_1%
1 2
1U_0603_10V6K
PC211
1U_0603_10V6K
DH_1.35V
SW_1.35V
DL_1.35V
PC209
VDD_1.35V
0.675V_DDR_VTT_ON<18>
CS_1.35V
12
+5V_ALW
1.35V_B+
15
14
13
12
11
PR204
0_0603_5%
16
17
PHASE
LGATE
PGND
CS
VDDP
VDD
1 2
768K_0402_1%
UGATE
RT8207MZQW_WQFN20_3X3
PGOOD
TON
9
10
PR206
@
PR210
1 2
0_0402_5%
18
8
BOOT
S5
+VLDOIN_1.35V
20
19
VTT
VLDOIN
VTTGND
VTTSNS
VTTREF
FB
S3
6
7
PJP201
PU200
PAD
GND
VDDQ
1 2
PAD-OPEN1x1m
21
1
2
3
4
+V_DDR_REF
5
+1.35V_MEN_P
FB sense trace
when FB pull down to GND
PR205
8.06K_0402_1%
1.35V_FB
1 2
PC213
100P_0402_50V8J
1 2
12
10K_0402_1%
PR209
TDC 0.7 A
Peak Current 1.0 A
OCP Current 2.6 A fix by IC
12
PC205
22U_0805_6.3V6M
+1.35V_MEN_P
12
PC214
@
.1U_0402_16V7K
+0.675V_P
+V_DDR_REF
PC212
0.033U_0402_16V7K
+1.35V_MEN_P
Mode S3 S5 +1.35V_MEN +V_DDR_REF +0.675V_P
S5 L L off off off
S3 L H on on off
FB sense trace
S0 H H on on on
+1.35V_MEM
TDC 6.6 A
Peak Current 9.5 A
OCP Current 11.4 A
TYP MAX
H/S Rds(on) 24mohm , 30mohm
A A
L/S Rds(on) 13.5mohm , 16.5mohm
Choke DCR 7.4mohm
+1.35V_MEN_P
CAP ESR 17mohm
5
4
PJP203
2
112
JUMP_1x3m
PJP204
2
112
JUMP_1x3m
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+1.35V_MEM
3
+0.675V_P
PJP202
1 2
PAD-OPEN1x1m
+0.675V_DDR_VTT
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
+1.35V_MEN/+0.675V_DDR_VTT
+1.35V_MEN/+0.675V_DDR_VTT
+1.35V_MEN/+0.675V_DDR_VTT
LA-A961P
LA-A961P
LA-A961P
42 53Tuesday, October 07, 2014
42 53Tuesday, October 07, 2014
42 53Tuesday, October 07, 2014
1
1.0
1.0
1.0
Page 43
Vinafix.com
5
4
3
2
1
PC311
D D
+PWR_SRC
C C
+3.3V_ALW
12
PR306
@
0_0402_5%
ILMT_1.05V
12
PR308
@
0_0402_5%
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
PJP302
PAD-OPEN 1x2m~D
EMC14U@
PC311
EMC12U@
PC311
EMC15U@
21
12
1.05V_M_PWRGD<9>
+3.3V_ALW
+1.05V_MEM
PC300
2200P_0402_50V7K
EMC14U@
PC300
2200P_0402_50V7K
EMC12U@
PC300
2200P_0402_50V7K
EMC15U@
12
PC300
PC311
0.1U_0402_25V6
2200P_0402_50V7K
@EMC@
@EMC@
+V1.05SP_B+
12
PC303
10U_0805_25V6K
@
PR313
1 2
0_0402_5%
1 2
PR315
100K_0402_1%
ILMT_1.05V
1.05V_MP_PWROK
PU300
8
IN
EN
GND
ILMT
PG
BS
LX
FB
BYP
LDO
9
3
2
SYX198DQNC_QFN10_3X3
1
6
BST_+V1.05SP
10
4
7
5
12
0.1U_0603_25V7K
1 2
SW_+V1.05SP
12
PC310
PC309
4.7U_0603_6.3V6K
EN_+V1.05SP
PC302
BST_+V1.05SP_C
+3.3V_ALW
4.7U_0603_6.3V6K
12
1M_0402_1%
PR303
PR312
0_0603_5%
1 2
@EMC@
4.7_1206_5%
1 2
0.68UH +-20% 7.9A
FB_+V1.05SP
PR305
SNB_1.05V
PL301
1 2
EN_+V1.05SP <38>
PC301
@EMC@
680P_0603_50V7K
1 2
12
PR307
7.5K_0402_1%
PR309
12
PR310
10K_0402_1%
PJP300
2
+1.05V_MP
112
JUMP_43X118
+1.05V_M
+1.05V_MP
12
12
PC304
PC305
330P_0402_50V7K
47U_0805_6.3V6M
PR305
4.7_1206_5%
EMC14U@
PR305
12
1K_0402_5%
12
PC306
47U_0805_6.3V6M
680P_0603_50V7K
12
PC307
PC301
EMC14U@
PC301
12
PC308
@
22U_0805_6.3VAM
22U_0805_6.3VAM
TDC 5.7 A
Peak Current 8.1 A
B B
OCP Current 9.72 A
TYP MAX
Choke DCR 13.0mohm , 14.0mohm
4.7_1206_5%
EMC15U@
680P_0603_50V7K
EMC15U@
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
3
2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
+1.05V_M
+1.05V_M
+1.05V_M
LA-A961P
LA-A961P
LA-A961P
43 53Tuesday, October 07, 2014
43 53Tuesday, October 07, 2014
43 53Tuesday, October 07, 2014
1
1.0
1.0
1.0
Page 44
Vinafix.com
5
4
3
2
1
D D
+3.3V_RUN
PR400
1 2
100K_0402_5%
PR401
C C
+1.5V_RUN
TDC 0.47 A
Peak Current 0.67 A
B B
@
12
12
47K_0402_5%
+5V_ALW
PAD-OPEN1x1m
12
PC400
1U_0402_6.3V6K
6
5
+1.5V_VIN
POK
EN
VIN
4
VOUT
VCNTL
3
VOUT
2
FB
9
VIN
GND
1
PU400
APL5930KAI-TRG_SO8
7
8
PC402
.1U_0402_16V7K
@EMC@
PJP400
12
12
PC401
4.7U_0805_6.3V6K
PR402
8.66K_0402_1%
PR403
10K_0402_1%
PJP401
1.5VSP
12
12
PC403
0.01U_0402_25V7K
12
1 2
PAD-OPEN1x1m
12
PC404
22U_0805_6.3V6M
+1.5V_RUN
+3.3V_RUN
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
3
2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
+1.5V_RUN
+1.5V_RUN
+1.5V_RUN
LA-A961P
LA-A961P
LA-A961P
44 53Tuesday, October 07, 2014
44 53Tuesday, October 07, 2014
44 53Tuesday, October 07, 2014
1
1.0
1.0
1.0
Page 45
Vinafix.com
5
4
3
PL501
2
PC520
PC521
1
VREF
100K_0402_1%_NCP15WF104F03RC
12
PR505
PU500
17
CSP1
18
CSN1
19
CSN2
20
CSP2
21
PU3
22
N/C
23
GFB
24
VFB
@
1 2
4.87K_0402_1%
10_0603_1%
H_PROCHOT#<9,36,46>
10K_0402_5%
PR521
PR526
1 2
VREF
PC507
PH500
12
PC501
.1U_0402_16V7K
15
16
14
13
VBAT
SLEWA
THERM
COMP26VCLK31V5A28DROP
25
29
27
1 2
@
PR534
0_0402_5%
12
1 2
@
PR500
75_0402_1%
1 2
D D
+VCC_PWR_SRC
SLEWA
PR510
39K_0402_5%~N
PR511
1 2
10K_0402_5%
CSN1
1 2
CSP1
+3.3V_RUN
+3.3V_RUN
VFB
GFB
C C
PC506
@
1 2
100P_0402_50V8J
PR523
1 2
10K_0402_5%
1 2
1 2
PR535
4.75K_0402_1%
PC512
1500P_0402_50V7K
0.33U_0603_10V7K
+5V_ALW
+1.05V_VCCST
B B
12
PR527
VIDSCLK<15>
VIDALERT_N<15>
VIDSOUT<15>
A A
54.9_0402_1%
5
12
12
PR529
PR528
@
75_0402_1%
110_0402_1%
+VCC_PWR_SRC
12
PR518
@
2M_0402_1%
1 2
PR524
@
2M_0402_1%
12
PR525
@
27K_0402_1%
12
1 2
PC500
4700P_0603_50V7K
12
11
10
9
IMON
OCP-I
O-USR
F-IMAX
B-RAMP
VR_ON
PGOOD
ALERT#
GND33GND
VR_HOT#30VREF
TPS51624RSM_QFN32_4X4
32
VR_HOT#
1 2
PC510
1U_0603_10V7K
PC514
PC511
0.1U_0402_25V6
OCP-I
SKIP#
PWM1
PWM2
VDD
VDIO
1 2
N/C
IMON
47P_0402_50V8J
OCP-I
FBMA-L11-453215800LMA90T_2P
EMC12U@
PR501
@
1 2
PR506
1 2
8
7
6
5
4
3
2
1
VIDSCLK
PR502
@
1 2
365K_0402_1%
B-RAMP
PR507
1 2
39K_0402_1%
12
@
PR536
0_0402_5%
SKIP#
PWM1
VIDSOUT
1 2
PC505
1U_0603_10V6K
VIDALERT_N
PR503
75_0402_1%
150K_0402_1%
1 2
681K_0402_1%
F-IMAX
PR508
1 2
100K_0402_1%
H_VR_EN <15,36>
@
PR513
1 2
75_0402_1%
PR516
@
1 2
1.91K_0402_1%
PR519
12
1_0603_5%
VCORE Load line & IMON
PR501
316K_0402_1%
EMC12U@
PR501
301K_0402_1%
EMC14U@
PR501
301K_0402_1%
EMC15U@
VCCSENSE<15>
from processor
VSSSENSE<17>
PR504
1 2
O-USR
PR509
1 2
+3.3V_RUN
+3.3V_RUN
PR521
4.42K_0402_1%
EMC12U@
PR521
3.92K_0402_1%
EMC14U@
PR521
3.92K_0402_1%
EMC15U@
36.5K_0402_1%
20K_0402_1%
@
1 2
0_0402_5%
+PWR_SRC
past green mask in X-build phase
PR539
H_VR_READY <15>
PWM1
@
PR531
1 2
0_0402_5%
@
PR532
1 2
0_0402_5%
PL501
FBMA-L11-453215800LMA90T_2P
EMC15U@
PJP500
1 2
@EMC@
1 2
FBMA-L11-453215800LMA90T_2P
PAD-OPEN 4x4m
PL501
PC503
1000P_0402_50V7K
1 2
+VCC_PWR_SRC
PC515
CORE_BOOT_C
10U_0805_25V6K
TI recommend 1nF
VFB
GFB
12
12
12
PC517
PC516
@
10U_0805_25V6K
10U_0805_25V6K
PC504
1 2
CORE_BOOT
0.1U_0402_25V6
12
CORE_BOOT_R
PR517
2.2_0603_5%
CSD97374CQ4M_SON8_3P5X4P5
CPU 15W
TDC 10 A
Peak Current 32 A
OCP Current 38.4 A
DC Load line -2.0 mV/A
Icc_Dyn_VID1 27 A
Choke DCR: 0.66m +-7% ohm
PH500 B Value : 4250k 1%
PH501 B Value : 3370k 1%
12
PC518
@
10U_0805_25V6K
9
8
7
6
5
2200P_0402_50V7K
680P_0402_50V7K
1
+
PC520
PC519
2
100U_D_20VM_R55M
@EMC@
PU501
PGND2
PWM
VSW
BOOT
PGND1
VDD
BOOT_R
SKIP#
VIN
1U_0603_10V7K
EMC12U@
PC520
EMC15U@
12
2200P_0402_50V7K
4
3
2
1
SKIP#1
PC509
0.1U_0402_25V6
0.1U_0402_25V6
12
PC521
0.1U_0402_25V6
@EMC@
1 2
1 2
CORE_SW
@
PR520
0_0402_5%
EMC12U@
PC521
EMC15U@
SKIP#
+5V_RUN
2.15K_0402_1%
PR522
4.7_1206_5%
4.7_1206_5%
4.7_1206_5%
PR522
4.7_1206_5%
@EMC@
PR512
680P_0603_50V7K
EMC15U@
EMC14U@
EMC12U@
12
CORE_SNUB
12
EMC15U@
PR522
680P_0603_50V7K
EMC14U@
PR522
680P_0603_50V7K
EMC12U@
PL500
0.15UH_PCME064T-R15MS0R667_36A_20%
4
3
PC508
680P_0603_50V7K
@EMC@
12
12
PR514
20K_0402_1%
PC508
PC508
PC508
PR515
+VCC_CORE
1
2
CSP1
12
PH501
12
1 2
1 2
PC502
0.068U_0402_16V7K
PC513
3.01K_0402_1%
10K_0402_1%_TSM0A103F34D1RZ
0.068U_0402_16V7K
CSN1
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
+VCC_CORE
+VCC_CORE
+VCC_CORE
LA-A961P
LA-A961P
LA-A961P
45 53Tuesday, October 07, 2014
45 53Tuesday, October 07, 2014
45 53Tuesday, October 07, 2014
1
1.0
1.0
1.0
Page 46
Vinafix.com
A
PQ700
SI4835DDY-T1-GE3_SO8
8
100K_0402_1%
154K_0402_1%
BQ24770_REGN
12
12
7
5
BQ24770_REGN
12
PR713
12
PR715
GNDA_CHG
CHARGER_CELL_PIN
+DC_IN_SS
1 1
CHARGER_SMBCLK
CHARGER_SMBDAT
pull up 10K in HW side (R827 R828)
2 2
ACAV_IN<36,47>
AC_DIS<36,40,47>
DMN65D8LW-7_SOT323-3
20140318 Change by TI
, change from 100k to 1k
to avoid false trigger
changer SYSOVP
PQ712
13
D
2
G
S
PR725
1K_0402_1%
PR729
@
154K_0402_1%
1
2
36
4
PR700
@
1 2
I_ADP<36>
I_BATT<36>
I_SYS<36>
H_PROCHOT#<9,36,45>
PBAT_PRES#<36,40,47>
0_0402_5%
AC Det
Max:15.122V
Typ :14.973V
Min :14.823V
6.49K_0402_1%
PC711
0.1U_0402_25V6
GNDA_CHG
CHARGER_SMBDAT<36>
CHARGER_SMBCLK<36>
PR716
@
1 2
@
PR718
1 2
PR720
@
1 2
GNDA_CHG
DC_BLOCK_GC <47>
+SDC_IN
PR710
34K_0402_1%
PR711
12
12
@
PT1
PAD~D
@
PT2
PAD~D
0_0402_5%
0_0402_5%
0_0402_5%
PC719
PC718
1 2
100P_0402_50V8J
100P_0402_50V8J
@
PR728
0_0402_5%
1 2
CSS_GC<47>
+DOCK_PWR_BAR
SDMK0340L-7-F_SOD323-2~D
+DC_IN_SS
SDMK0340L-7-F_SOD323-2~D
+PBATT
+PBATT
+PBATT+PBATT
SDMK0340L-7-F_SOD323-2~D
1 2
PR788
1 2
20K_0402_1%
B
+SDC_IN
@
12
NTR4502PT1G_SOT23-3
12
+DCIN
PR717
0_0402_5%
CMPIN
CMPOUT
PC700
0.1U_0603_25V7K
PQ702
PC701
1U_0603_25V6K
1 2
28
11
12
10
13
14
15
16
29
GNDA_CHG
GNDA_CHG
@
PR702
1 2
0_0402_5%
PD705
12
PD704
12
PD702
12
PR708
10_1206_5%
PC709
10U_0805_25V6K
12
0_0402_5%
@
PR714
1 2
@
1 2
1 2
/BATPRES<47>
PR701
0.01_1206_1%
4
3
13
D
2
G
S
CSSP_1
PR703
100_0402_1%
12
PR704
@
0_0402_5%
PC702
0.1U_0402_25V6
1 2
4
2
PU700
ACP
VCC
ACDRV
3
CMSRC
6
ACDET
SDA
SCL
5
ACOK
7
IADP
8
IDCHG
9
ISYS
/PROCHOT
CMPIN
CMPOUT
/BATPRES
CELL
PWPD
BQ24777RUYR_WQFN28_4x4
PJP701
1 2
PAD-OPEN1x1m
1
2
13
D
2
PQ701
G
NTR4502PT1G_SOT23-3
S
CSSN_1
12
12
PR705
@
0_0402_5%
1 2
PC703
0.1U_0402_25V6
1
ACN
24
REGN
25
CHG_BTS CHG_BTS_C
BTST
26
HIDRV
27
PHASE
23
LODRV
22
GND
21
1 2
NC
10K_0402_1%
20
SRP
19
SRN
18
/BATDRV
17
BAT
PQ703A
SI3993CDV-T1-GE3_TSOP6
S
G
1
12
PR706
100K_0402_1%
GNDA_CHGGNDA_CHG
BQ24770_REGN
PR712
2.2_0603_5%
1 2
CHG_UGATE
CHG_SW
CHG_LGATE
PR799
BQ24770_REGN
PR722
4.02K_0402_1%
1 2
1 2
PR723
10_0603_1%
+PBATT
+PBATT
+PBATT+PBATT
1 2
PC729
GNDA_CHG
1U_0603_25V6K
PR707
100K_0402_1%
C
PL700
EMC@
1UH +-20% 6.6A
past green mask in X-build phase
D
65
SI3993CDV-T1-GE3_TSOP6
12
PC712
@
1 2
PAD-OPEN 4x4m
PQ703B
S
G
3
12
0.047U_0603_25V7K~D
PJP700
D
42
@
PR709
0_0402_5%
PC710
1 2
1U_0603_10V6K
12
12
DOCK_DCIN_IS+ <34>
DOCK_DCIN_IS- <34>
DK_CSS_GC <47>
7
S1/D2
G26S2
5
PQ705
AON6970_DFN5X6D-8-7
1D12
G1
S2
S2
4
3
CHAGER_SRC+PWR_SRC_AC
0.1U_0402_25V6
0.1U_0402_25V6
3.3UH +-20% PIMB104T 10A
1 2
CHG_SNUB
12
PC721
1000P_0603_50V7K
@EMC@
D
TYP MAX
H/S Rds(on) 7.4mohm , 8.8mohm
L/S Rds(on) 2.6mohm , 3.1mohm
Choke DCR 5.8mohm , 7.0mohm
EMC14U@
EMC12U@
PC732
0.1U_0402_25V6
@EMC@
PC732
PC732
12
PC713
@EMC@
2200P_0402_50V7K
2200P_0402_50V7K
12
12
PC714
22U_0805_25V6M
2200P_0402_50V7K
PC713
EMC14U@
PC713
EMC12U@
PC715
22U_0805_25V6M
Near PL701
+PWR_SRC
12
12
12
PC705
PC704
10U_0805_25V6K
10U_0805_25V6K
12
12
12
PC716
PC717
22U_0805_25V6M
22U_0805_25V6M
12
12
PC708
PC707
PC706
@
10U_0805_25V6K
10U_0805_25V6K
22U_0805_25V6M
+PWR_SRC
1
2
0.1U_0402_25V6
@
PC728
1 2
+VCHGR
PC722
0.1U_0603_25V7K
@EMC@
GNDA_CHG
12
12
PC723
10U_0805_25V6K
12
12
PC725
PC724
10U_0805_25V6K
10U_0805_25V6K
@
PL701
12
PR726
4.7_1206_5%
@EMC@
0.1U_0402_25V6
GNDA_CHG
PC726
1 2
PR721
0.01_1206_1%
4
3
PC727
0.1U_0402_25V6
1 2
3 3
GNDA_CHG
ACAV_IN_NB<36,47>
PR745
100K_0402_1%
PR743
@
0_0402_5%
+DC_IN
12
12
12
PR737
649K_0402_1%
PR738
3M_0402_5%
12
PR740
10K_0402_1%
12
100P_0402_50V8J
PC737
12
CMPIN
CMPOUT
PC741
100P_0402_50V8J
1 2
PR726
4.7_1206_5%
EMC12U@
PR726
4.7_1206_5%
EMC14U@
PR726
BATDRV# <47>
PC721
1000P_0603_50V7K
EMC12U@
PC721
680P_0603_50V7K
EMC14U@
PC721
+3.3V_ALW
1000P_0603_50V7K
4.7_1206_5%
EMC15U@
4 4
EMC15U@
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEIT HER THIS SHEET NOR THE IN FORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTR ONICS, INC.
C
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Charger
Charger
Charger
LA-A961P
LA-A961P
LA-A961P
D
46 53Tuesday, October 07, 2014
46 53Tuesday, October 07, 2014
46 53Tuesday, October 07, 2014
1.0
1.0
1.0
Page 47
Vinafix.com
5
PD800
D D
C C
+VCHGR
PDS5100H-13_POWERDI5-3
BATDRV#<46>
1
PQ800
SI4835DDY-T1-GE3_SO8
1
2
3 6
4
+3.3V_ALW
AC_DIS<36,40,46>
PR832
DC_IN_SS
DK_PWRBAR
33
34
35
DC_IN_SS
DK_PWRBAR
CHARGERVR_DCIN
ERC2
12
PC817
0.1U_0402_25V4Z~D
28
29
30NC31
32
GND
PBatt+
BLK_MOSFET_GC
DK_AC_OFF_EN
ACAV_IN_NB
DSCHRG_MOSFET_GC
DK_AC_OFF_EN
SL_BAT_PRES#
BLKNG_MOSFET_GC
NBDK_DCINSS
SS_DCBLK_GC
EN_DK_PWRBAR17P33ALW
16
15
18
EN_DK_PWRBAR
STSTART_DCBLOCK_GC
3301_PWRSRC
1 2
100_0603_1%
PR838
1 2
100_0603_1%
27
P50ALW
26
PBATT_OFF
25
24
23
GND
22
21
20
19
CD3301BRHHR_QFN36_6X6~D
@
0_0402_5%
1 2
P33ALW
PR860
1 2
100_0603_1%
PR859
B B
PR835
100K_0402_5%
ACAV_IN<36,46,47>
PR846
SOFT_START_GC<40>
1 2
1 2
DC_BLOCK_GC<46>
1 2
47_0805_5%~D
0.1U_0603_50V4Z
PR847
100_0603_1%
@
PR851
1 2
0_0402_5%
1 2
@
PR855 0_0402_5%
+DC_IN
+3.3V_ALW2
ACAV_DOCK_SRC#<34>
+SDC_IN
+3.3V_ALW2
A A
PC813
@
PR842
1 2
0_0402_5%
5
+DC_IN_SS
12
ACAVDK_SRCACAVDK_SRC
12
PC815
0.1U_0603_25V7K
CD3301_DCIN
ERC1
ACAVIN
P33ALW2
1
2
3
4
5
6
7
8
9
37
DK_CSS_GC<46>
PR831
1 2
100_0603_1%
PU800
DC_IN
SS_GC
ERC1
ACAVDK_SRC
GND
SDC_IN
DC_BLK_GC
ACAV_IN
P33ALW2
TP
CSS_GC<46>
PC816
0.047U_0603_25V7M
36
NC
CSS_GC10DK_CSS_GC11ERC312ERC213GND14PWR_SRC
ERC3
12
@
+PBATT
3
2
8
7
5
@
PR895
0_0402_5%
1 2
100K_0402_5%
PR828
1 2
10K_0402_5%
+DOCK_PWR_BAR
+PBATT
@
1 2
P50ALW
0_0402_5%
1 2
CD_PBATT_OFF
@
PR845 0_0402_5%
DK_AC_OFF
DK_AC_OFF_ENCD3301_SDC_IN
SL_BAT_PRES#
+3.3V_ALW
PR874
1 2
1M_0402_5%
4
DMG2301U-7 1P SOT23-3
12
PR830
13
D
2
G
S
PR843
3301_ACAV_IN_NB
1 2
@
0_0402_5%
1 2
+PWR_SRC_AC
4
@
PQ829
1
3
13
2
2
PQ832
DMN65D8LW-7_SOT323-3
+5V_ALW
SLICE_BAT_ON <35>
@
PR848
0_0402_5%
1 2
1 2
@
PR850 0_0402_5%
@
PR854
0_0402_5%
PR863
@
+DOCK_PWR_BAR
PD815
2
3
BAT54CW_SOT323-3
PR858
1 2
1M_0402_5%
SLICE_BAT_PRES# <34,35,40>
+NBDOCK_DC_IN_SS
1 2
PR857 0_0402_5%
PDS5100H-13_POWERDI5-3
DMN65D8LDW-7_SOT363-6
DMN65D8LDW-7_SOT363-6
1
12
10K_0402_5%
ACAV_IN_NB <36,46>
DOCK_AC_OFF_EC <35>
EN_DOCK_PWR_BAR <35>
PQ813B
4
5
0_0402_5%
1 2
DOCK_DET#<34,35,47>
DOCK_AC_OFF <34>
PR844
PD808
FDS6679AZ-G_SO8
PQ813A
3
@
PR853
2
100K_0402_5%
2
PR829
100K_0402_5%
61
3
+PWR_SRC_AC
PC807
1 2
0.47U_0805_25V6K
36
241
1
578
3
5
123
36
241
PQ815
SDMK0340L-7-F_SOD323-2~D
PR826
12
12
+3.3V_ALW2
1 2
100K_0402_5%
3
PQ810
FDS6679AZ-G_SO8
PR814
330K_0402_5%
PQ826
FDMC6679AZ_MLP8-5
4
1500P_0402_50V7K
578
PD813
2
2
PR827
1 2
12
@
PC809
12
13
1
3
@
PR811
0_0402_5%
12
PQ814
PR822
D
S
PQ816
DMN65D8LW-7_SOT323-3
PD817
NTR4502PT1G_SOT23-3
1
BAT54CW_SOT323-3
Purpose: Trigger PROCHOT# when
active battery is removed from
system.
Allows EC to re-establish
system performance for battery
next in line.
STSTART_DCBLOCK_GC
PR818
100K_0402_5%
1 2
12
10K_0402_5%
13
2
G
DIS_BAT_PROCHOT#<35>
TC7SH08FU_SSOP5~D
Vth=0.5-1.5V
3
+DC_IN_SS
2
+NBDOCK_DC_IN_SS
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+3.3V_ALW
12
PR810
100K_0402_5%
+3.3V_ALW2
PU806
4
O
2
PBAT_PRES#<36,40,46>
PC810
0.1U_0402_10V7K
5
1
P
B
2
A
G
3
2
@
PR812
1 2
0_0402_5%
12
ACAV_IN<36,46,47>
PC805
0.1U_0402_10V7K
1 2
ACAV_IN#
100K_0402_5%
+3.3V_ALW
5
1
P
B
O
2
A
G
PU804
3
TC7SH08FU_SSOP5~D
1 2
100K_0402_5%
61
2
DMN65D8LDW-7_SOT363-6
+3.3V_ALW2
12
PR864
3
PQ817B
5
4
4
PR819
PQ817A
DMN65D8LDW-7_SOT363-6
ACAV_IN#
+3.3V_ALW
12
61
PQ806A
2
+3.3V_ALW
12
PR813
100K_0402_5%
3
PQ806B
5
4
DMN65D8LDW-7_SOT363-6
+3.3V_ALW2
DOCK_DET# <34,35,47>
1
PR815
100K_0402_5%
PR816
@
0_0402_5%
1 2
DMN65D8LDW-7_SOT363-6
Purpose: Turn on the PQ817
for primary or module bay
battery to provide power to
dock side without AC exist.
/BATPRES <46>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Selector
Selector
Selector
LA-A961P
LA-A961P
LA-A961P
1
47 53Tuesday, October 07, 2014
47 53Tuesday, October 07, 2014
47 53Tuesday, October 07, 2014
1.0
1.0
1.0
Page 48
Vinafix.com
5
+VCC_CORE
4
3
2
1
D D
1
PC900
22U_0805_6.3V6M
2
1
PC901
22U_0805_6.3V6M
2
1
PC902
22U_0805_6.3V6M
2
1
PC903
22U_0805_6.3V6M
2
1
PC904
22U_0805_6.3V6M
2
Based on _RF Cheng. Hill
1
PC913
22U_0805_6.3V6M
2
1
PC914
22U_0805_6.3V6M
2
1
@
PC915
22U_0805_6.3V6M
2
1
@
PC916
22U_0805_6.3V6M
2
1
@
PC917
22U_0805_6.3V6M
2
961
220U 2.5V Y D2 ESR9M H1.9 SX
1
PC966
+
2
C C
B B
961
VCORE Load line & IMON
PR501
324K_0402_1%
EMC14UwithD@
4.22K_0402_1%
PR521
EMC14UwithD@
2200P_0402_50V7K
2200P_0402_50V7K
2200P_0402_50V7K
2200P_0402_50V7K
2200P_0402_50V7K
(11257) for PT 20131107
PC105
EMC14UwithD@
PC203
EMC14UwithD@
PC300
EMC14UwithD@
PR522
4.7_1206_5%
EMC14UwithD@
PC520
EMC14UwithD@
PC713
EMC14UwithD@
PR726
PC106
0.1U_0402_25V6
EMC14UwithD@
PC206
0.1U_0402_25V6
EMC14UwithD@
PC311
0.1U_0402_25V6
EMC14UwithD@
PC508
680P_0603_50V7K
EMC14UwithD@
PC521
0.1U_0402_25V6
EMC14UwithD@
PC732
0.1U_0402_25V6
EMC14UwithD@
PC721
4.7_1206_5%
EMC14UwithD@
A A
680P_0603_50V7K
EMC14UwithD@
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR DECOUPLING
PROCESSOR DECOUPLING
PROCESSOR DECOUPLING
LA-A961P
LA-A961P
LA-A961P
48 53Tuesday, October 07, 2014
48 53Tuesday, October 07, 2014
48 53Tuesday, October 07, 2014
1
1.0
1.0
1.0
Page 49
Vinafix.com
5
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )
Request
Request
Title
Item
ItemItem
D D
Page# Rev.
Page#Page#
6
TitlePage#
TitleTitle
HW 2013/10/161 COMPAL 0.2(X01)
Date
Date Issue Description
DateDate
RequestRequest
Owner
Owner
OwnerOwner
4
Issue DescriptionItem
Issue DescriptionIssue Description
Follow intel reference circuit.
3
Add CC100, RC300 on CPU pin AC4, net name is PM_TEST_RST
2
Solution Description
Solution DescriptionSolution Description
1
Rev.Solution Description
Rev.Rev.
2
3
4
C C
5
6
7
8
9
10
B B
11
27
36
22
36
36
9
38 2013/10/20
28 2013/10/20
HW
HW
HW
HW
HW
HW 2013/10/20
HW
2013/10/16
2013/10/16
2013/10/16
2013/10/16
2013/10/16
2013/10/16
COMPAL
COMPAL
COMPAL
COMPAL
COMPAL
COMPALHW
COMPAL
COMPAL
Dell drop POA function.
Dell drop POA function.
IC version changed. VMM2320 circuit change:
board ID change. RE79 change to 130K
follow intel latest design guide.
HDMI ciruit issue swap TMDS_CON_P/N2 & TMDS_CON_P/N0
RF requirement. add CC14, CC15 and move CC12, CC13 to behind the resistor (RC72)7
power doesn't split VPRO & NPRO BOM.
SSI design will cause LED behavior error. ChangeQL1,QL2 MASK_BASE_LEDS# to SYS_LED_MASK#
To solve Line-on HDD dirty shut down issue. Add RN6,RN7 and reserved RN730 2013/10/22
Change JUSH1 from 26 pin to 20 pin, pin define follow E5
remove POA_WAKE# off page symbol
remove POA_ON/OFF#,make UE2.B62 to be NC pin
1. UV8 from VMM2320 change to VMM 2330 (SA00007G800)
2. UV8 pin J3, E5 to +1.05V_RUN
3. VMM_SPI_WP# reserved RV517, 2.2K resistor PU to +3.3V_RUN_VMM
4. VMM_GPIO4,reserved RV518, 2.2K resistor PU to +3.3V_RUN_VMM
5. VMM_GPIO5 reserved RV519, 2.2K resistor PU to +3.3V_RUN_VMM
6. UV8 pin B5, B6 change to +3.3V_RUN_VMM
7. LP_CTL reserved RV516, 2.2K resistor PU to +3.3V_RUN_VMM
8. Depop RV73
pop RE56 and change from 8.2K to 10K , it's RESET_OUT# pull down
resistor
add RZ41, RZ42, reserve it for VPRO & NVPRO option.
0.2(X01)
0.2(X01)
0.2(X01)
0.2(X01)
0.2(X01)
0.2(X01)
0.2(X01)COMPALHW
0.2(X01)COMPAL
0.2(X01)
0.2(X01)HW
0.2(X01)
12
28
14
15
38
A A
HW 0.2(X01)
HW13
HW
2013/10/23 COMPAL 1 CC1 &CC2 change from 18PF to 5PF
2013/10/309 COMPALHW
debug usage. add RC3012013/10/236 COMPAL
follow xtal vender suggest 6, 7, 22,
reserve it to prevent PCH_PLTRST# floating
when power on
No support MODPHY add PJP36, depop QZ6, QZ10, RZ16, RZ5, CZ25, CZ38HW 2013/10/30 COMPAL 0.2(X01)16
2 CC8 & CC11 change from 18PF to 15PF
3 CL13 & CL14 change from 33PF to 27PF
4 RV81 change from 0 ohm to 2.2K & CV113 change to 18PF
add RC304, 100K pull down, on PCH_PLTRST#_EC
Change TPM_PIRQ# pull up ( RC247) to +3.3V_RUN from +3.3V_ALW_PCHTo solve backdrive issue.COMPAL12 2013/10/30
0.2(X01)
0.2(X01)
0.2(X01)
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE P.I.R (1/4)
EE P.I.R (1/4)
EE P.I.R (1/4)
LA-A961P
LA-A961P
LA-A961P
49 53Tuesday, October 07, 2014
49 53Tuesday, October 07, 2014
49 53Tuesday, October 07, 2014
1
1.0
1.0
1.0
Page 50
Vinafix.com
5
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )
Request
Request
Title
Item
ItemItem
D D
17
Page# Rev.
Page#Page#
TitlePage#
TitleTitle
HW COMPAL
Date
Date Issue Description
DateDate
RequestRequest
Owner
Owner
OwnerOwner
4
Issue DescriptionItem
Issue DescriptionIssue Description
USB3.0 EA finetune Pop RI22013/11/232 0.2(X01)
3
2
Solution Description
Solution DescriptionSolution Description
1
Rev.Solution Description
Rev.Rev.
COMPALHW18
19
20
21 2013/11/6 UMA Dock has one dimm config add DIMM_DET on UC1.U48 to replace PCH_GPIO48 ,Reserve RC302 &RC303 0.2(X01)
C C
23
24
25
B B
12
38
25
22
22
HW
HW
HW
2013/11/2
2013/11/6 1 pop RE282, depop RE281. change SUS_ON control pin from
2013/11/622 0.2(X01)
2013/11/6
2013/11/6
2013/11/6
COMPALHW
COMPALHW
COMPALHW
COMPAL
COMPAL
COMPAL
HDMI EA finetune Pop RV55,RV622013/11/225
Dell request.37 add RZ48, RZ49, QZ15
Dell request36 HW COMPAL
UMA Dock has VPRO & N-VPRO config
follow vender suggest to solve "Bo" noise
follow vender suggest
To solve CRT display jitter issue
depop UZ5, UZ6, RZ21, RZ22, CZ35,RC91
add RZ51, change QZ12 from 3904 to 3906. make RPE6 to be NC pin, add
RE88
SUS_ON_EC to SIO_SLP_S4#
2 change RC91, RE88 from 10K to 47K
change PJP18 to RZ53 ,PJP19 to RZ47 for VPRO config
Add RZ52,RZ46 for NVPRO config
1.UA1 pin22 add RA45 0 ohm PU to +3.3V_RUN_AUDIO
2.UA1 pin21 add RA44 100k ohm to GND
1.RPC8 change from 2.2k to 10k
2.UC1.F2 &RPC8.3 change name from I2C0_SDA to PCH_GPIO4
3.UC1.F3 &RPC8.4 change name from I2C0_SCL to PCH_GPIO5
4.UC1.G4 &RPC8.1 change name from I2C1_SDA_VMM to PCH_GPIO6
5.UC1.F1 &RPC8.2 change name from I2C1_SCL_VMM to PCH_GPIO7
6.RPV2.1 connect to I2C1_SDA_VMM
8.RPV2.2 connect to I2C1_SCL_VMM
9.Depop RV516, CV116, CV117
1.LV23,LV25 change from BLM15AX102SN1D to BLM15PX181SN1D
2.CV90,CV101 change from 1uF to 10uF
0.2(X01)
0.2(X01)
0.2(X01)
0.2(X01)
0.2(X01)
0.2(X01)
26
27
28
A A
37
22
30 2013/11/6
HW
HW
HW
2013/11/6
2013/11/6
COMPAL
COMPAL
COMPAL
Base on Pre-PT RSMRST EA result
follow vender suggestion
Support New NFC module
1.POP RE88,UZ6,RE51
2. remove QZ12,RZ48,RZ49,RZ50
1. change LV22 , LV24
From SM01000N400 S SUPPRE_ MURATA BLM15AX102SN1D 0402
To SM01000NO00 S SUPPRE_ MURATA BLM15PX181SN1D 0402
2. change CV82, CV94 from 1uF to 10uF
3. UV8 pin D3 from +1.05V_VMM_VDDTX to +1.05V_VMM_VDD.
4. UV8 Pin H3, E10, H11 change to NC
5. Change UV8 pin B5, B6 from +3.3V_RUN_VMM to +3.3V_RUN_VDDIO"
Pop R2,R3 & Remove PJP50
0.2(X01)
0.2(X01)
0.2(X01)
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE P.I.R (2/4)
EE P.I.R (2/4)
EE P.I.R (2/4)
LA-A961P
LA-A961P
LA-A961P
50 53Tuesday, October 07, 2014
50 53Tuesday, October 07, 2014
50 53Tuesday, October 07, 2014
1
1.0
1.0
1.0
Page 51
Vinafix.com
5
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )
Request
Request
Title
Item
ItemItem
D D
29
Page# Rev.
Page#Page#
TitlePage#
TitleTitle
HW
Date
Date Issue Description
DateDate
2013/11/632
RequestRequest
Owner
Owner
OwnerOwner
4
Issue DescriptionItem
Issue DescriptionIssue Description
3
RA7,RA8 change to 24.9ohmCOMPAL follow vender suggestion
2
Solution Description
Solution DescriptionSolution Description
1
Rev.Solution Description
Rev.Rev.
0.2(X01)
30
31
32
33
C C
34
35
36
37
B B
36 HW 2013/11/6
2014/02/06HW38
25
32
33
29
9,16
30
HW
HW 0.3(X01)
HW
HW
HW
HW
2014/02/10
2014/02/24
2014/03/06
2014/03/06
2014/03/06
COMPAL
COMPAL
COMPAL
COMPAL
COMPAL
COMPAL
COMPAL
COMPAL2014/03/06
definition different
For MODPHY power rail contril by JUMP
directly
Base on PS8338 datasheet, PI0 have 2 level,
PI1 have 3 level
USB3.0 repeator Change USB3.0 repeator from PS8711 to PS8713
Remove NFC Funciton
EMI test fail , back to SSI SD card
connector.
follow intel DG 1.2
intel Wigig need 32K clock when DSx
Add RE283 to separate EC and ALW_PWRGD_3V_5VFor Delray EC common code GPIO
1.change PJP36 pin1 from +1.05V_M to +1.05V_RUN 0.3(X01)
For PI0, delete RV66
For PI1, add RV100 PD to GND
Remove NFC circuit
1.remove RC221
2.remove Q1,Q2,U1,R1,R2,R3,C1,C2,C3,C4,C5,RC36,RC37,RC246
3.NC PCH_GPIO28 ; PCH_GPIO70
4.net name PCH_GPIO59 instead of NFC_DET#
change JSD1
from ALPS_SCDADA0101_19P_NR to TAITW_PSDCT6-20GLBS1NN4H_19P-T
1.reserved 0.47uF for +PCH_VCCDSW3_3 , near CPU AH10 pin
2.add 10K pull high to +PCH_VCCDSW3_3 for PM_LANPHY_ENABLE,
leave RPC1. pin 7 NC
1.Add UZ11&RZ56(@)&RZ57
2.JNGFF1.44 change to WIGIG_32KHZ from SUSCLK
3.JNGFF2.60 change to NC from SUSCL
0.2(X01)
0.3(X01)
0.3(X01)
0.3(X01)
0.3(X01)
0.3(X01)
0.3(X01)Change R272 from 10K to 100K, and pull up to +3.3V_ALW2COMPAL To solve Power leakage issue.34 HW38 2014/03/06
39
40
41
42
43
A A
9
30,38
9,27
36
28 HW 2014/06/09
HW
HW
HW
2014/05/09 COMPAL
2014/05/09
2014/05/09
COMPAL
COMPAL
COMPAL DVT2.0 Board ID RE79 change from 130K to 33KHW 2014/05/19
COMPAL
reduce 0 ohm quantity
ESD request
WLAN can’t recognize during
enable Unobtrusive mode(Fn+B)
CFG3 add RC305 1k PD
RC50,RZ42,RZ57,RZ47,RZ53 ,RE283 change to 0-ohm short
ADD CZ68,CC101
Add RL29,RL30 1M PU add on SW_100_ORG# & SW_10_GRN#
0.4(X02)XDP config use
0.4(X02)
0.4(X02)
0.4(X02)
0.4(X02)
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE P.I.R (3/4)
EE P.I.R (3/4)
EE P.I.R (3/4)
LA-A961P
LA-A961P
LA-A961P
51 53Tuesday, October 07, 2014
51 53Tuesday, October 07, 2014
51 53Tuesday, October 07, 2014
1
1.0
1.0
1.0
Page 52
Vinafix.com
5
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )
Request
Request
Title
Item
ItemItem
D D
44
Page# Rev.
Page#Page#
TitlePage#
TitleTitle
Date
Date Issue Description
DateDate
2014/06/09
RequestRequest
Owner
Owner
OwnerOwner
COMPAL
4
Issue DescriptionItem
Issue DescriptionIssue Description
3
2
Solution Description
Solution DescriptionSolution Description
1
Rev.Solution Description
Rev.Rev.
0.4(X02)Follow OZ request No stuff RR11, CR35HW29
45
46
47
48
C C
B B
28 HW
36
28,35
HW
HW
2014/06/16
2014/06/30
2014/08/25HW27,15,0951 COMPAL For ESD Stuff CC24,CC83 0.5(X02)
COMPAL
COMPAL2014/06/30
COMPAL Correct net nameChange WLAN_LAN_DISBL# to WLAN_DISBL#
COMPALHW22 2014/07/02
COMPAL Stuff RR11, CR35Follow OZ requestHW2949 0.4(X02)2014/07/15
Reserver +3.3V_HDD source reserve 1x1m jump PJP66 between +3.3V_RUN and +3.3V_HDD
Rreserve RE284 switch H_VR_EN log incorrect thermal event during remove battery only
Add discharge schematic to meet
VMM3320 Spec.
Follow Huston RV4 from 100k Change to 270KCOMPAL2014/07/25HW50 23 0.5(X02)
Remove ME switch.(SW1) RC301 change to 0 ohm shortCOMPAL2014/10/07HW52 1.0(A00)06
Add QV700,RV701,RV702
0.4(X02)
0.4(X02)
0.4(X02)
0.4(X02)
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE P.I.R (4/4)
EE P.I.R (4/4)
EE P.I.R (4/4)
LA-A961P
LA-A961P
LA-A961P
52 53Monday, October 13, 2014
52 53Monday, October 13, 2014
52 53Monday, October 13, 2014
1
1.0
1.0
1.0
Page 53
Vinafix.com
5
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )
Request
Request
Item
Item Issue Description
ItemItem
D D
Page# Title
Page#Page#
1 10/8 Compal
2 X01
45 VCC_CORE 10/8 Compal
Selector47
Title
TitleTitle
Date
DateDate
RequestRequest
Owner
Owner
OwnerOwner
Remove slice battery support circuit
To prevent acoustic noise issue
4
Issue DescriptionDate
Issue DescriptionIssue Description
3
Remove PC808, PC811, PC812 , PC814, PD806, PD807, PD811, PD814, PD819,
PD821, PQ801, PQ807, PQ809, PQ811, PQ812, PQ818, PQ821, PQ828, PQ830,
PQ831, PR802, PR804, PR808, PR813, PR815, PR816, PR817, PR821, PR823,
PR825, PR834, PR836, PR837, PR839, PR849, PR852, PR861, PU805, PU807,
PU808
Remove PC923, PC924, PC925, PC926, PC927, PC928, PC929, PC930, PC931,
PC940, PC941, PC943, PC946, PC947, PC948
Add PC966
2
Solution Description
Solution Description Rev.
Solution DescriptionSolution Description
1
Rev.Page#
Rev.Rev.
X01
3 X01
4 X01
C C
5 X01
6 X01
7 X01
8 X01
B B
10
42 1.35V_MEN 10/8 RICHTEK To prevent IC damage Add PR204
46 Charger 10/8 Compal Fine tune divider voltage
41,43,44
46 Charger 10/25 Compal
+1.05V_M
+1.5V_RUN
+3V/+5V
10/22 Compal To improve the ability of anti-noise
Change /BATPRES pin control net from /BATPRES
to PBAT_PRES#
45 VCC_CORE 10/31 Compal Fine tune IMON
Change PR713, PR725 to 100k
Change PR715, PR729 to 154k
Change PR307 to 7.5k
Change PR310, PR102, PR104, PR403 to 10k
Change PR100 to 6.49k
Change PR101 to 15k
Change PR402 to 8.66k
Pop PR728
Depop PR816
Add PR518, PR524, PR525
ALL ALL 10/31 Compal RF request Add PC521, PC206, PC106, PC311, PC732 ( 0.1uF )
ALL ALL 10/31 Compal RF request
Pop PR111,PC111,PR112,PC114,PR203,PC208,PR305,PC301,PR522,PC508,
(4.7ohm, 680pF)
46 Charger 10/31 Compal PR703 change to 100ohmTo prevent VCP trigger PROCHOT# X01
4611
4612
Charger 7/7
6/26Charger
Compal
Compal
For peak power shifting, to avoid back to back turn
on toO slowly when battery remove.
for decrease audible noise, Use charger BQ24777
PG2.0 with work around of 3.3uH inductor,
and alignment with Houston, so add 2*10uF caps
in PC706, PC707
1)depop PQ6
2)new add PQ712, Drain connect to ACAV_IN
3)depop PQ829
1) PL701 change from 2.2U to 3.3u
from (SH00000YF00) S COIL 2.2UH +-20% 12A 10X10X4 MOLDING
to (SH00000IC00) S COIL 3.3UH +-20% PIMB104T-3R3MS 10A to
2) add 0805 MLCC in PC706, PC707
(SE00000QK00) S CER CAP 10U 25V K X5R 0805 H1.25
X019
X03
X03
13
A A
40
41
14 40
+DCIN
+3V/+5V
5
7/10
2014
/9/26
Compal
Compal+DCIN
EMI requirement: Please help to pop PD5, PC119(1uF)
to implement in DVT2.0 BOM.
follow Houston/ EMI requirement: remove main source
(AMC) (SC600001600)
S DIO ROW AZC199-02S.R7G C/C SOT23 ESD
to avoid negative spike to demage PD5
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
Pop
1)PD5 P/N:(SC600001600) S DIO ROW AZC199-02S.R7G C/C SOT23 ESD
2)PC119 P/N:(SE080105K80) S CER CAP 1U 10V K X5R 0603
Change from
(SC600001600) S DIO ROW AZC199-02S.R7G C/C SOT23 ESD
to
(SCA00000T00) S ZEN ROW PESD5V0U2BT 3P C/C SOT23 ESD
(H=1.1mm)
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PWR P.I.R (1/1)
PWR P.I.R (1/1)
PWR P.I.R (1/1)
LA-A961P
LA-A961P
LA-A961P
X03
A00
1.0
1.0
53 53Tuesday, October 07, 2014
53 53Tuesday, October 07, 2014
53 53Tuesday, October 07, 2014
1
1.0
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