Compal LA-A821P Bay Trail M Schematic

Intel BayTrail-M Platform

1 1

Date : 2013/05/22 Version 0.1

2 2

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/01/03 2014/01/03

Compal Secret Data

Deciphered Date

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Title

Bay Trail M LA-A821P

Cover Page

0.1

1 40Monday, July 01, 2013

0.1

204pin DDR3L-SO-DIMM X1

Memory BUS

P.14

1 1

LVDS Conn. Colay eDP

P.17

LVDS Translator RTD2132R-CG

P.16

XDP-SFF-26Pin Debug Conn.

P.13

DDI Port1

HDMI Conn.

P.18

DDI Port0

VALLEYVIEW-M

RJ45

2 2

P.21

RTL8106E-CG 10/100M RTL8111G-CG 1G

P.21

port 1

SATA SSD NGFF B TYPE

P.22

PCIE x4 port 2

SATA II x2

port 0

SATA HDD Conn.

P.19

SPI

SOC

FCBGA 1170 Pin

LPC BUS

Dual Channel

1.35V DDR3L 1066/1333

PCIE x4 port3

page 05~12

HD Audio

USB2.0 x3

USB3.0 x1

204pin DDR3L-SO-DIMM X1

P.15

port 0

USB 3.0 Conn

USB 2.0 Conn

PCIeMini Card WLAN PCIe port 3

P.20

port 3port 1

USB HUB FE1.1s(STT)

port 1

P.23P.23 P.23

port 2

Touch Screen

P.17

port 3

Int. Camera

P.17

NGFF E TYPE

3 3

Sub Boards

RTC CKT.

CardReader GL834L(HUB Port0) +USB(Port 2)+ Audio Combo jack

4 4

P.22

DC/DC Interface CKT.

Power Circuit DC/DC

Touch pad/LED B

P.22

LED/Power On/Off

SPI ROM

1.8V (8MB)

P.8

P.26

P.28~P.36

P.24

KB9012QF A4

P.08

P.25

Int.KBD

P.26

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

HDA Codec

ALC259

2014/01/03 2014/01/03

P.24

SPK Conn

Compal Secret Data

P.22

Deciphered Date

WLAN PCIe port 4

P.22

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Block Diagrams

Bay Trail M LA-A821P

2 40Monday, July 01, 2013

0.1

Voltage Rails

VIN

BATT+ 12V Battery power supply

B+

1 1

RTCVCC RTC Battery Power

+1.0VALW

+1.8VALW +1.8v Always power rail

+3VALW +3.3v Always power rail

+5VALW

+SOC_VCC Core voltage for SOC

+SOC_VNN GFX voltage for SOC

+0.675VS +0.675V power rail for DDR3L Terminator

+1.0VS

2 2

+1.05VS

+1.35VS

+1.5VS

+1.8VS

+3VS

+5VS

19V Adapter power supply

AC or battery power rail for power circuit. (19V/12V)

+1.0v Always power rail

+5.0v Always power rail

+1.35V power rail for DDR3L+1.35V

+1.0v system power rail

+1.05v system power rail

+1.35v system power rail

+1.5v system power rail

+1.8v system power rail

+3.3v system power rail

+5.0v system power rail

Board ID / SKU ID Table for AD channel

S0 S3 S4/S5Power Plane Description

ON ON

ONON

ON ONON

OFF

F OFF

ON ON

ONONOFF OFF

ON OFF OFF

Vcc 3.3V +/- 5%

100K +/- 5%Ra/Rc/Re

Board ID

Rb / Rd / Rf V min

0 1 2 3 4 5 6

8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%

7 NC

BOARD ID Table

Board ID

0 1 2 3 4 5 6

AD_BID

0.216 V

0.436 V

0.712 V

1.036 V

1.453 V

1.935 V

2.500 V

PCB Revision

0 V

V typ

AD_BID

max

0 V 0 V

0.250 V 0.289 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

1.650 V 1.759 V

2.200 V

3.300 V

2.341 V

3.300 V

BOM Option Table

Item BOM Structure

Unpop @

XDP (Debug Port)

TPM TPM@

CONN@Connector XDP@ EMC@EMC requirement @EMC@EMC requirement unpop

TS@Touch Screen RS@R short TEST@Test Point

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

3 3

EC SM Bus1 address

Device

Smart Battery

Address Address

0001 011X b

EC SM Bus2 address

Device

SOC SM Bus address

Device Address

SO-DIMM A (JDIMM1) SO-DIMM B (JDIMM2)

4 4

A0h A2h

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

BOM config

PCB P/N

EVT BOM config

43 level BOM table

Compal Secret Data

Deciphered Date

2014/01/03 2014/01/03

BOM Structure43 Level Description

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Notes List

Bay Trail M LA-A821P

0.1

3 40Monday, July 01, 2013

0.1

Power ON

+RTCVCC

RTCRST#

D D

C C

B B

EC_ON

+3VALW/+5VALW

+1.0VALW

+1.8VALW

+1.2VALW

ON/OFFBTN#

EC_RSMRST#

PBTN_OUT#

PMC_SLP_S4#

SUSPWRDNACK

SYSON

+1.35V

R_PWROK

PMC_SLP_S3#

VR_ON

+CORE_VNN

+CORE_VCC

VGET

SUSP#

+1.0VS

+1.05VS

+1.35VS

+1.5VS

+1.8VS

+3VS

+5VS

+0.675VS

KBRST#

PMC_CORE_PWROK

DDR_CORE_PWROK

PMC_PLTRST#

100 ms

20 ms

100 ms

120 ms

20ms

.446 ms

0.606 ms

0.878 ms

0.973 ms

1.171 ms

1.757 ms

2.343 ms

6.774 ms

50 ms

100 ms

T0: +RTCVCC stable to RTCRST# high > 9ms T1: VR ramp up time from 10% to 90% voltage level < 2ms T2 :Rail to subsequent rail turn on delay < 2ms T3 :+VALWAS stable to EC_RSMRST# high > 10ms T4 :+VS rails stable to PMC_CORE_PWROK > TBD

NOTE:

A A

1. T1 and T2 are recommended time for all the VR rails unless specified otherwise. The VR ramp up time T2 and subsequent rail delay T3 are put in place to avoid inrush current which may be caused by multiple loads turning on simultaneously or fast charging of VR output decoupling.

2. Platform devices other than SOC sequencing are not explicitly shown as they are not limited by the SOC sequencing requirement.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2014/01/03 2014/01/03

Compal Secret Data

Deciphered Date

Compal Ele ctronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Power Sequence

Bay Trail M LA-A821P

4 40Monday, July 01, 2013

0.1

D D

DDR_A_MA[0..15]<14>

DDR_A_DM[0..7]<14> DDR_B_DM[0..7]<15>

DDR_A_RAS#<14> DDR_A_CAS#<14> DDR_A_WE#<14>

DDR_A_BS0<14> DDR_A_BS1<14>

C C

B B

DDR_A_BS2<14>

DDR_A_CS0#<14>

DDR_A_CS2#<14>

DDR_A_CKE0<14>

DDR_A_CKE2<14>

DDR_A_ODT0<14>

DDR_A_ODT2<14>

DDR_A_CLK0<14> DDR_A_CLK0#<14>

DDR_A_CLK2<14> DDR_A_CLK2#<14>

DDR_A_RST#<14>

+DDR_SOC_VREF

1 2 1 2

DDR_PWROK<32> DDR_CORE_PWROK<8>

1 2 1 2 1 2

Follow CRB v1. 15

RC1100K_0402_5% RC1100K_04 02_5% RC2100K_0402_5% RC2100K_04 02_5%

RC323.2_0402_1% RC323.2_0402_1% RC429.4_0402_1% RC429.4_0402_1% RC5162_0402_1% RC5162_0402_1%

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_TERMN0 DDR_TERMN1

DDR_RCOMP0 DDR_RCOMP1 DDR_RCOMP2

Close To SOC P in

+1.35V

1 2

RC6

4.7K_0402_1%

1 2

RC7

4.7K_0402_1%

UC1A

K45

DRAM0_MA_0

H47

DRAM0_MA_1

L41

DRAM0_MA_2

H44

DRAM0_MA_3

H50

DRAM0_MA_4

G53

DRAM0_MA_5

H49

DRAM0_MA_6

D50

DRAM0_MA_7

G52

DRAM0_MA_8

E52

DRAM0_MA_9

K48

DRAM0_MA_10

E51

DRAM0_MA_11

F47

DRAM0_MA_12

J51

DRAM0_MA_13

B49

DRAM0_MA_14

B50

DRAM0_MA_15

G36

DRAM0_DM_0

B36

DRAM0_DM_1

F38

DRAM0_DM_2

B42

DRAM0_DM_3

P51

DRAM0_DM_4

V42

DRAM0_DM_5

Y50

DRAM0_DM_6

Y52

DRAM0_DM_7

M45

DRAM0_RAS#

M44

DRAM0_CAS#

H51

DRAM0_WE#

K47

DRAM0_BS_0

K44

DRAM0_BS_1

D52

DRAM0_BS_2

P44

DRAM0_CS_0#

P45

DRAM0_CS_2#

C47

DRAM0_CKE_0

D48

RESERVED_D48

F44

DRAM0_CKE_2

E46

RESERVED_E46

T41

DRAM0_ODT_0

P42

DRAM0_ODT_2

M50

DRAM0_CKP_0

M48

DRAM0_CKN_0

P50

DRAM0_CKP_2

P48

DRAM0_CKN_2

P41

DRAM0_DRAMRST#

AF44

DRAM_VREF

AF42

ICLK_DRAM_TERMN_AF42

AH42

ICLK_DRAM_TERMN_AH42

AD42

DRAM_VDD_S4_PWROK

AB42

DRAM_CORE_PWROK

AD44

DRAM_RCOMP_0

AF45

DRAM_RCOMP_1

AD45

DRAM_RCOMP_2

AF40

RESERVED_AF40

AF41

RESERVED_AF41

AD40

RESERVED_AD40

AD41

RESERVED_AD41

LLEYVIEW-M_FCBGA1170

+DDR_SOC_VREF

CC1

CC1 .1U_0402_16V7K

.1U_0402_16V7K

0.675V

1 OF 13

DRAM0_DQ_0 DRAM0_DQ_1 DRAM0_DQ_2 DRAM0_DQ_3 DRAM0_DQ_4 DRAM0_DQ_5 DRAM0_DQ_6 DRAM0_DQ_7 DRAM0_DQ_8

DRAM0_DQ_9 DRAM0_DQ_10 DRAM0_DQ_11 DRAM0_DQ_12 DRAM0_DQ_13 DRAM0_DQ_14 DRAM0_DQ_15 DRAM0_DQ_16 DRAM0_DQ_17 DRAM0_DQ_18 DRAM0_DQ_19 DRAM0_DQ_20 DRAM0_DQ_21 DRAM0_DQ_22 DRAM0_DQ_23 DRAM0_DQ_24 DRAM0_DQ_25 DRAM0_DQ_26 DRAM0_DQ_27 DRAM0_DQ_28 DRAM0_DQ_29 DRAM0_DQ_30 DRAM0_DQ_31 DRAM0_DQ_32 DRAM0_DQ_33 DRAM0_DQ_34 DRAM0_DQ_35 DRAM0_DQ_36 DRAM0_DQ_37 DRAM0_DQ_38 DRAM0_DQ_39 DRAM0_DQ_40 DRAM0_DQ_41 DRAM0_DQ_42 DRAM0_DQ_43 DRAM0_DQ_44 DRAM0_DQ_45 DRAM0_DQ_46 DRAM0_DQ_47 DRAM0_DQ_48 DRAM0_DQ_49 DRAM0_DQ_50 DRAM0_DQ_51 DRAM0_DQ_52 DRAM0_DQ_53 DRAM0_DQ_54 DRAM0_DQ_55 DRAM0_DQ_56 DRAM0_DQ_57 DRAM0_DQ_58 DRAM0_DQ_59 DRAM0_DQ_60 DRAM0_DQ_61 DRAM0_DQ_62 DRAM0_DQ_63

DRAM0_DQSP_0 DRAM0_DQSN_0 DRAM0_DQSP_1 DRAM0_DQSN_1 DRAM0_DQSP_2 DRAM0_DQSN_2 DRAM0_DQSP_3 DRAM0_DQSN_3 DRAM0_DQSP_4 DRAM0_DQSN_4 DRAM0_DQSP_5 DRAM0_DQSN_5 DRAM0_DQSP_6 DRAM0_DQSN_6 DRAM0_DQSP_7 DRAM0_DQSN_7

M36 J36 P40 M40 P36 N36 K40 K42 B32 C32 C36 A37 C33 A33 C37 B38 F36 G38 F42 J42 G40 C38 G44 D42 A41 C41 A45 B46 C40 B40 B48 B47 K52 K51 T52 T51 L51 L53 R51 R53 T47 T45 Y40 V41 T48 T50 Y42 AB40 V45 V47 AD48 AD50 V48 V50 AB44 Y45 V52 W51 AC53 AC51 W53 Y51 AD52 AD51

J38 K38 C35 B34 D40 F40 B44 C43 N53 M52 T42 T44 Y47 Y48 AB52 AA51

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7

DDR_A_DQS[0..7] <14>

DDR_B_MA[0..15]<15>DDR_A_D[0..63] <14> DDR_B_D[0..63] <15>

DDR_B_RAS#<15> DDR_B_CAS#<15>

DDR_B_WE#<15>

DDR_B_BS0<15> DDR_B_BS1<15> DDR_B_BS2<15>

DDR_B_CS0#<15>

DDR_B_CS2#<15>

DDR_B_CKE0<15>

DDR_B_CKE2<15>

DDR_B_ODT0<15>

DDR_B_ODT2<15>

DDR_B_CLK0<15>

DDR_B_CLK0#<15>

DDR_B_CLK2<15>

DDR_B_CLK2#<15>

DDR_B_RST#<15>

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

AW41

AY45 BB47

BB44 BB50 BC53 BB49 BF50 BC52 BE52 AY48 BE51 BD47 BA51 BH49 BH50

BD38 BH36 BC36 BH42 AT51 AM42 AK50 AK52

AV45 AV44 BB51

AY47 AY44 BF52

AT44

AT45

BG47 BE46 BD44 BF48

AP41

AT42

AV50 AV48

AT50 AT48

AT41

UC1B

DRAM1_MA_0 DRAM1_MA_1 DRAM1_MA_2 DRAM1_MA_3 DRAM1_MA_4 DRAM1_MA_5 DRAM1_MA_6 DRAM1_MA_7 DRAM1_MA_8 DRAM1_MA_9 DRAM1_MA_10 DRAM1_MA_11 DRAM1_MA_12 DRAM1_MA_13 DRAM1_MA_14 DRAM1_MA_15

DRAM1_DM_0 DRAM1_DM_1 DRAM1_DM_2 DRAM1_DM_3 DRAM1_DM_4 DRAM1_DM_5 DRAM1_DM_6 DRAM1_DM_7

DRAM1_RAS# DRAM1_CAS# DRAM1_WE#

DRAM1_BS_0 DRAM1_BS_1 DRAM1_BS_2

DRAM1_CS_0#

DRAM1_CS_2#

DRAM1_CKE_0 RESERVED_BE46 DRAM1_CKE_2 RESERVED_BF48

DRAM1_ODT_0

DRAM1_ODT_2

DRAM1_CKP_0 DRAM1_CKN_0

DRAM1_CKP_2 DRAM1_CKN_2

DRAM1_DRAMRST#

LLEYVIEW-M_FCBGA1170

2 OF 13

DRAM1_DQ_0 DRAM1_DQ_1 DRAM1_DQ_2 DRAM1_DQ_3 DRAM1_DQ_4 DRAM1_DQ_5 DRAM1_DQ_6 DRAM1_DQ_7 DRAM1_DQ_8

DRAM1_DQ_9 DRAM1_DQ_10 DRAM1_DQ_11 DRAM1_DQ_12 DRAM1_DQ_13 DRAM1_DQ_14 DRAM1_DQ_15 DRAM1_DQ_16 DRAM1_DQ_17 DRAM1_DQ_18 DRAM1_DQ_19 DRAM1_DQ_20 DRAM1_DQ_21 DRAM1_DQ_22 DRAM1_DQ_23 DRAM1_DQ_24 DRAM1_DQ_25 DRAM1_DQ_26 DRAM1_DQ_27 DRAM1_DQ_28 DRAM1_DQ_29 DRAM1_DQ_30 DRAM1_DQ_31 DRAM1_DQ_32 DRAM1_DQ_33 DRAM1_DQ_34 DRAM1_DQ_35 DRAM1_DQ_36 DRAM1_DQ_37 DRAM1_DQ_38 DRAM1_DQ_39 DRAM1_DQ_40 DRAM1_DQ_41 DRAM1_DQ_42 DRAM1_DQ_43 DRAM1_DQ_44 DRAM1_DQ_45 DRAM1_DQ_46 DRAM1_DQ_47 DRAM1_DQ_48 DRAM1_DQ_49 DRAM1_DQ_50 DRAM1_DQ_51 DRAM1_DQ_52 DRAM1_DQ_53 DRAM1_DQ_54 DRAM1_DQ_55 DRAM1_DQ_56 DRAM1_DQ_57 DRAM1_DQ_58 DRAM1_DQ_59 DRAM1_DQ_60 DRAM1_DQ_61 DRAM1_DQ_62 DRAM1_DQ_63

DRAM1_DQSP_0 DRAM1_DQSN_0 DRAM1_DQSP_1 DRAM1_DQSN_1 DRAM1_DQSP_2 DRAM1_DQSN_2 DRAM1_DQSP_3 DRAM1_DQSN_3 DRAM1_DQSP_4 DRAM1_DQSN_4 DRAM1_DQSP_5 DRAM1_DQSN_5 DRAM1_DQSP_6 DRAM1_DQSN_6 DRAM1_DQSP_7 DRAM1_DQSN_7

BG38 BC40 BA42 BD42 BC38 BD36 BF42 BC44 BH32 BG32 BG36 BJ37 BG33 BJ33 BG37 BH38 AU36 AT36 AV40 AT40 BA36 AV36 AY42 AY40 BJ41 BG41 BJ45 BH46 BG40 BH40 BH48 BH47 AY52 AY51 AP52 AP51 AW51 AW53 AR51 AR53 AP47 AP45 AK40 AM41 AP48 AP50 AK42 AH40 AM45 AM47 AF48 AF50 AM48 AM50 AH44 AK45 AM52 AL51 AG53 AG51 AL53 AK51 AF52 AF51

BF40 BD40 BG35 BH34 BA38 AY38 BH44 BG43 AU53 AV52 AP42 AP44 AK47 AK48 AH52 AJ51

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

DDR_B_DQS0 DDR_B_DQS#0 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS7 DDR_B_DQS#7

DDR_B_DQS[0..7] <15> DDR_B_DQS#[0..7] <15>DDR_A_DQS#[0..7] <14>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2014/01/03 2014/01/03

Compal Secret Data

Deciphered Date

Compal Ele ctronics, Inc.

Title

VLV-M SOC Memory DDR3L

Size Document Number Rev

Bay Trail M LA-A821P

Date: Sheet of

5 40Monday, July 01, 2013

0.1

UC1C

AK12

AK13 AM14 AM13

AB14

AV3 AV2 AT2 AT3 AR3 AR1 AP3 AP2

AL3 AL1

D27

C26 C28

B28 C27 B26

AM3 AM2

T3 AB3 AB2

W3 W1

R1 AD6 AD4 AB9 AB7

V6 A29 C29

B30 C30

DDI0_TXP_0 DDI0_TXN_0 DDI0_TXP_1 DDI0_TXN_1 DDI0_TXP_2 DDI0_TXN_2 DDI0_TXP_3 DDI0_TXN_3

DDI0_AUXP DDI0_AUXN

DDI0_HPD

DDI0_DDCDATA DDI0_DDCCLK

DDI0_VDDEN DDI0_BKLTEN DDI0_BKLTCTL

DDI0_RCOMP_P DDI0_RCOMP_N RESERVED_AM14 RESERVED_AM13 VSS_AM3 VSS_AM2

RESERVED_T2 RESERVED_T3 RESERVED_AB3 RESERVED_AB2 RESERVED_Y3 RESERVED_Y2 RESERVED_W3 RESERVED_W1 RESERVED_V2 RESERVED_V3 RESERVED_R3 RESERVED_R1 RESERVED_AD6 RESERVED_AD4 RESERVED_AB9 RESERVED_AB7 RESERVED_Y4 RESERVED_Y6 RESERVED_V4 RESERVED_V6 GPIO_S0_NC_13 GPIO_S0_NC14 RESERVED_AB14 GPIO_S0_NC_12 RESERVED_C30

H_HDMI_TX2+<18> H_HDMI_TX2-<18> H_HDMI_TX1+<18> H_HDMI_TX1-<18> H_HDMI_TX0+<18>

D D

HDMI

H_HDMI_TX0-<18> H_HDMI_TXC+<18> H_HDMI_TXC-<18>

HDMI_HPD#<18,7>

UMA_HDMI_DATA<18> UMA_HDMI_CLK<18>

RC9

1 2

402_0402_1%

DDI0_RCOMPP DDI0_RCOMPN

Follow CRB v1.15 0ohm till to GND

C C

B B

+1.8VS

RC10

RC10 10K_0402_5%

10K_0402_5%

RC11

RC11 10K_0402_5%

10K_0402_5%

GPIO_NC13 GPIO_NC14

T1T1

GPIO_NC12

T2T2

Follow CRB v1.15

LLEYVIEW-M_FCBGA1170

GPIO_S0_NC[13]: Multiplexed with Hardware Str aps Pin:MDSI_DDCDATA

A A

LLEYVIEW-M_FCBGA1170

1.8V

AG3

DDI1_TXP_0 DDI1_TXN_0 DDI1_TXP_1 DDI1_TXN_1 DDI1_TXP_2 DDI1_TXN_2 DDI1_TXP_3 DDI1_TXN_3

DDI1_AUXP DDI1_AUXN

DDI1_HPD

DDI1_VDDEN

VSS_AH3 VSS_AH2

VGA_RED

VGA_BLUE

VGA_GREEN

VGA_IREF VGA_IRTN

VGA_HSYNC VGA_VSYNC

Issued Date

AG1 AF3 AF2 AD3 AD2 AC3 AC1

AK3 AK2

K30

P30 G30

N30 J30 M30

AH3 AH2

AH14 AH13 AF14 AF13

BA3 AY2 BA1 AW1 AY3

BD2 BF2

BC1 BC2

T7 T9 AB13 AB12 Y12 Y13 V10 V9 T12 T10 V14 V13 T14 T13 T6 T4 P14

F34 M32 D28 J28 K34 D34 F32 F28 K28 J34 N32 D32

1.0V1.0V

1.0V

1.8V

DDI1_DDCDATA

1.8V

DDI1_DDCCLK

1.8V

DDI1_BKLTEN

1.8V

DDI1_BKLTCTL

RESERVED_AH14 RESERVED_AH13 RESERVED_AF14 RESERVED_AF13

3.3V

VGA_DDCCLK

3.3V

VGA_DDCDATA

RESERVED_T7

RESERVED_T9 RESERVED_AB13 RESERVED_AB12

RESERVED_Y12 RESERVED_Y13 RESERVED_V10

RESERVED_V9

RESERVED_T12 RESERVED_T10 RESERVED_V14 RESERVED_V13 RESERVED_T14 RESERVED_T13

RESERVED_T6

RESERVED_T4

RESERVED_P14

GPIO_S0_NC_15 GPIO_S0_NC_16 GPIO_S0_NC_17 GPIO_S0_NC_18 GPIO_S0_NC_19 GPIO_S0_NC_20 GPIO_S0_NC_21 GPIO_S0_NC_22 GPIO_S0_NC_23 GPIO_S0_NC_24 GPIO_S0_NC_25

3 OF 10

GPIO_S0_NC_26

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDI1_ENABLE

DDI1_ENVDD DDI1_ENBKL DDI1_PWM

1 2

RC8 2.2K_0402_5%RC8 2.2K_0402_5%

+1.8VS

Follow CRB v1.15 0ohm till to GND

DDI1_PWM

Compal Secret Data

2014/01/03 2014/01/03

Compal Secret Data

Deciphered Date

H_EDP_TXP0 <16> H_EDP_TXN0 <16> H_EDP_TXP1 <16> H_EDP_TXN1 <16>

H_EDP_AUXP <16> H_EDP_AUXN <16>

H_EDP_HPD# <17>

+1.8VS

eDP Panel

UC8

NL17SZ07DFT2G_SC70-5

SA00004BV00

LVDS@

1 2

RC64 0_0402_5%

1 2

IEDP@

RC65 0_0402_5%

Title

Size Document Number Rev

Custom

Date: Sheet of

IEDP@

1 2

EC_ENBKL_R

RC87 0_0402_5%

+1.8VS

UC6

DDI1_ENBKL

DDI1_ENVDD

SOC_PWM_TL LCD_ENVDD SOC_PWM_EDP

DDI1_ENBKL DDI1_ENVDD DDI1_PWM

EC_ENBKL_R

Bay Trail M LA-A821P

NL17SZ07DFT2G_SC70-5

SA00004BV00

+1.8VS

UC7

NL17SZ07DFT2G_SC70-5

SA00004BV00

SOC_PWM_TL <16>

SOC_PWM_EDP <17>

+3VS

RPC1

45 36 27 18

4.7K_0804_8P4R_5%

RPC2

18 27 36 45

100K_0804_8P4R_5%

+3VS

1 2

4.7K_0402_5%

RB24

Compal Electronics, Inc.

VLV-M SOC Display

EC_ENBKL <16,25>

EC_ENBKL_R <17>

LCD_ENVDD <17>

0504

6 40Monday, July 01, 2013

0.1

UC1D

SATA_PTX_DRX_P0<19>

D D

HDD

SSD

Follow CRB V1.15 0ohm till to G ND

Follow CRB v1.15

C C

B B

SOC_SCI#<8>

+1.8VS

SATA_PTX_DRX_N0<19>

SATA_PRX_C_DTX_P0<19> SATA_PRX_C_DTX_N0<19>

SATA_PTX_DRX_P1<22> SATA_PTX_DRX_N1<22>

SATA_PRX_C_DTX_P1<22> SATA_PRX_C_DTX_N1<22>

T3T3

1 2

RC18 10K_0402_5%RC18 10K_0402_5%

1 2

RC12

402_0402_1%

SOC_SCI# DEVSLP_SOC SATA_LED#_SOC

SATA_RCOMPP SATA_RCOMPN

BF6

SATA_TXP_0

BG7

SATA_TXN_0

AU16

SATA_RXP_0

AV16

SATA_RXN_0

BD10

SATA_TXP_1

BF10

SATA_TXN_1

AY16

SATA_RXP_1

BA16

SATA_RXN_1

BB10

VSS_BB10

BC10

VSS_BC10

BA12

SATA_GP0 / GPIO_S0_SC_0

AY14

SATA_GP1 / SATA_DEVSLP_0 / GPIO_S0_SC_1

AY12

SATA_LED# / GPIO_S0_SC_2

AU18

SATA_RCOMP_P

AT18

SATA_RCOMP_N

AT22

MMC1_CLK / GPIO_S0_SC_16

AV20

MMC1_D0 / GPIO_S0_SC_17

AU22

MMC1_D1 / GPIO_S0_SC_18

AV22

MMC1_D2 / GPIO_S0_SC_19

AT20

MMC1_D3 / GPIO_S0_SC_20

AY24

MMC1_D4 / GPIO_S0_SC_21

AU26

MMC1_D5 / GPIO_S0_SC_22

AT26

MMC1_D6 / GPIO_S0_SC_23

AU20

MMC1_D7 / GPIO_S0_SC_24

AV26

MMC1_CMD / GPIO_S0_SC_25

BA24

MMC1_RST# / SATA_DEVSLP_0 / GPIO_S0_SC_26

AY18

MMC1_RCOMP

BA18

SD2_CLK / GPIO_S0_SC_27

AY20

SD2_D0 / GPIO_S0_SC_28

BD20

SD2_D1 / GPIO_S0_SC_29

BA20

SD2_D2 / GPIO_S0_SC_30

BD18

SD2_D3_CD# / GPIO_S0_SC_31

BC18

SD2_CMD / GPIO_S0_SC_32

AY26

SD3_CLK / GPIO_S0_SC_33

AT28

SD3_D0 / GPIO_S0_SC_34

BD26

SD3_D1 / GPIO_S0_SC_35

AU28

SD3_D2 / GPIO_S0_SC_36

BA26

SD3_D3 / GPIO_S0_SC_37

BC24

SD3_CD# / GPIO_S0_SC_38

AV28

SD3_CMD / GPIO_S0_SC_39

BF22

SD3_1P8EN / GPIO_S0_SC_40

BD22

SD3_PWREN# / GPIO_S0_SC_41

BF26

SD3_RCOMP

LLEYVIEW-M_FCBGA1170

PCIE_CLKREQ_0# / GPIO_S0_SC_3 PCIE_CLKREQ_1# / GPIO_S0_SC_4 PCIE_CLKREQ_2# / GPIO_S0_SC_5 PCIE_CLKREQ_3# / GPIO_S0_SC_6

SD3_WP / GPIO_S0_SC_7

HDA_RST# / LPE_I2S0_CLK / GPIO_S0_SC_8

HDA_SYNC / LPE_I2S0_FRM / GPIO_S0_SC_9

HDA_CLK / LPE_I2S0_DATAOUT / GPIO_S0_SC_10

HDA_SDO / LPE_I2S0_DATAIN / GPIO_S0_SC_11

HDA_SDI0 / LPE_I2S1_CLK / GPIO_S0_SC_12

HDA_SDI1 / LPE_I2S1_FRM / GPIO_S0_SC_13

HDA_DOCKRST# / LPE_I2S1_DATAOUT / GPIO_S0_SC_14

HDA_DOCKEN# / LPE_I2S1_DATAIN / GPIO_S0_SC_15

LPE_I2S2_CLK / SATA_DEVSLP_1 / GPIO_S0_SC_62

4 OF 10

LPE_I2S2_FRM / GPIO_S0_SC_63

LPE_I2S2_DATAIN / GPIO_S0_SC_64

LPE_I2S2_DATAOUT / GPIO_S0_SC_65

PCIE_TXP_0 PCIE_TXN_0

PCIE_RXP_0 PCIE_RXN_0

PCIE_TXP_1 PCIE_TXN_1

PCIE_RXP_1 PCIE_RXN_1

PCIE_TXP_2 PCIE_TXN_2

PCIE_RXP_2 PCIE_RXN_2

PCIE_TXP_3 PCIE_TXN_3

PCIE_RXP_3 PCIE_RXN_3

VSS_BB7 VSS_BB5

PCIE_RCOMP_P PCIE_RCOMP_N

RESERVED_BB4 RESERVED_BB3

RESERVED_AV10

RESERVED_AV9

HDA_LPE_RCOMP

RESERVED_P34 RESERVED_N34

RESERVED_AK9 RESERVED_AK7

PROCHOT#

AY7 AY6

AT14 AT13

AV6 AV4

AT10 AT9

AT7

PCIE_PTX_LANRX_P3

AT6

PCIE_PTX_LANRX_N3

AP12

PCIE_PRX_C_LANTX_P3

AP10

PCIE_PRX_C_LANTX_N3

AP6

PCIE_PTX_WLANRX_ P4

AP4

PCIE_PTX_WLANRX_ N4

AP9

PCIE_PRX_WLANTX_ P4

AP7

PCIE_PRX_WLANTX_ N4

BB7 BB5

BG3

PCIE_CLKREQ_0#

BD7

PCIE_CLKREQ_1#

BG5

LAN_CLKREQ#

BE3

WLAN_CLKREQ#

BD5

AP14

PCIE_RCOMPP

AP13

PCIE_RCOMPN

BB4 BB3

AV10 AV9

BF20

HDA_RCOMP

BG22

HDA_RST#

BH20

HDA_SYNC

BJ21

HDA_BIT_CLK

BG20

HDA_SDOUT

BG19 BG21 BH18 BG18

BF28 BA30

GPIO_S0_SC_63

BD28 BC30

GPIO_S0_SC_65

P34 N34

AK9 AK7

C24

Internal PD 2K

PCIE_PTX_WLANRX_ P4 PCIE_PTX_WLANRX_ N4

1 2

CC2.1U_0402_16V7K CC2.1U_0402_16V7K

1 2

CC3.1U_0402_16V7K CC3.1U_0402_16V7K

Ultra@

1 2

CC4.1U_0402_16V7K

1 2

CC5.1U_0402_16V7K

Ultra@

Follow CRB V1.15 0ohm till to G ND

1 2

RC13

402_0402_1%

1 2

RC1449.9_0402_1% RC1449.9_0402_1%

AZ_SDIN0_HD <24>

T4T4 T5T5 T6T6

DEVSLP1 <22>

RC17

33.2_0402_1%

1 2

ESD@

CC7

CC7 10P_0402_50V8J

10P_0402_50V8J

+1.0VS

H_PROCHOT# <25>

NonUltra@

1 2 1 2

NonUltra@

PCIE_PTX_C_LANRX_P3 <21> PCIE_PTX_C_LANRX_N3 < 21>

PCIE_PRX_C_LANTX_P3 <21> PCIE_PRX_C_LANTX_N3 < 21>

PCIE_PTX_C_WLANR X_P4 <20> PCIE_PTX_C_WLANR X_N4 <20>

PCIE_PRX_WLANTX_ P4 <20> PCIE_PRX_WLANTX_ N4 <20>

8411 Pin 36 O/D

LAN_CLKREQ# <21> WLAN_CLKREQ# <20> HDMI_HPD# <18,6>

HDA_SDOUT HDA_SYNC HDA_BIT_CLK HDA_RST#

GPIO_S0_SC_63: BIOS/EFI Boot St rap (BBS) BIOS Boot Select ion 0 = LPC 1 = SPI

10K_0402_5%

RC15

CC83.1U_0402_16V7K

CC83.1U_0402_16V7K CC82.1U_0402_16V7K

CC82.1U_0402_16V7K

PCIE_PTX_C_WLANR X_P4_M <20> PCIE_PTX_C_WLANR X_N4_M <20>

AZ_BITCLK_HD

RPC3

18 27 36 45

33_0804_8P4R_5%

EMC@

10K_0402_5%

GPIO_S0_SC_65GPIO_S0_SC_63

LAN

PCIE_CLKREQ_0# LAN_CLKREQ#

LAN

WLAN_CLKREQ# PCIE_CLKREQ_1#

1 2

CC6

@EMC@CC6

@EMC@

22P_0402_50V8J

AZ_SDOUT_HD <24>

AZ_SYNC_HD <24>

AZ_BITCLK_HD <24> AZ_RST_HD# <24>

GPIO_S0_SC_65: Security Flash D escriptors 0 = Override 1 = Normal Opera tion (Internal P U)

+1.8VS+1.8VS

RC16

EC programing :

igh"for Flash BI OS

TXE_DBG <25>

QC1

BSS138W-7-F_SOT323-3

+1.8VS

RPC7

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

For EMI

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2014/01/03 2014/01/03

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

VLV-M SOC SATA/PCI-E/HDA

Bay Trail M LA-A821P

7 40Monday, July 01, 2013

0.1

XTAL_25M_IN_R<20>

+1.8VALW

D D

C C

SPI_CS0# SPI_MISO SPI_CLK SPI_MOSI

B B

A A

Close To SOC < 1000mil

1 2

RC25 51_0 402_5%X DP@RC25 51_0402_5%XDP@

RP52

1 8 2 7 3 6 4 5

51_0804_8P4R_5%

XDP@

RC23 4.02 K_0402_1%RC23 4.02K_0402_1 % RC24 47.5 _0402_1%RC24 47.5 _0402_1%

RPC5

1 8 2 7 3 6 4 5

22_0804_8P4R_5%

EMC@

+BIOS_SPI

1 2

RC33 3.3K _0402_5%RC33 3.3K_0402_5%

1 2

RC35 3.3K _0402_5%RC35 3.3K_0402_5%

XDP_H_PRDY#

XDP_H_TDI XDP_H_TMS XDP_H_TCK XDP_H_TRST#

XTAL_25M_IN XTAL_25M_OUT

1 2 1 2

LAN

WLAN

XDP_H_TCK<13> XDP_H_TRST#<13> XDP_H_TMS<13> XDP_H_TDI<13>

XDP_H_TDO<13> XDP_H_PRDY#<13>

XDP_H_PREQ_BUF#<13>

SOC_SPI_CS0# SOC_SPI_MISO SOC_SPI_CLK SOC_SPI_MOSI

CLK_LAN#<21> CLK_LAN<21>

CLK_WLAN#<20> CLK_WLAN<20>

T8T8

1 2

RC29

49.9_0402_1%

ICLK_ICOMP ICLK_RCOMP

SOC_SPI_CS0#

SOC_SPI_MISO SOC_SPI_MOSI SOC_SPI_CLK

SOC_KBRST#

SOC_LID_OUT#

SOC_SMI#

GPIO_RCOMP

SPI ROM ( 8MByte ) 1.8V

UC5

SPI_CS0#

CS#

SPI_MISO

DO(IO1)

SPI_WP#

WP#(IO2)

GND

W25Q64DWSS IG_SO8

18P_0402_50V8J

NOGCLK@

UC1E

AH12

ICLK_OSCIN

AH10

ICLK_OSCOUT

AD9

RESERVED_AD9

AD14

ICLK_ICOMP

AD13

ICLK_RCOMP

AD10

RESERVED_AD10

AD12

RESERVED_AD12

AF6

PCIE_CLKN_0

AF4

PCIE_CLKP_0

AF9

PCIE_CLKN_1

AF7

PCIE_CLKP_1

AK4

PCIE_CLKN_2

AK6

PCIE_CLKP_2

AM4

PCIE_CLKN_3

AM6

PCIE_CLKP_3

AM9

RESERVED_AM9

AM10

RESERVED_AM10

BH7

PMC_PLT_CLK_0 / GPIO_S0_SC_96

BH5

PMC_PLT_CLK_1 / GPIO_S0_SC_97

BH4

PMC_PLT_CLK_2 / GPIO_S0_SC_98

BH8

PMC_PLT_CLK_3 / GPIO_S0_SC_99

BH6

PMC_PLT_CLK_4 / GPIO_S0_SC_100

BJ9

PMC_PLT_CLK_5 / GPIO_S0_SC_101

D14

TAP_TCK

G12

TAP_TRST#

F14

TAP_TMS

F12

TAP_TDI

G16

TAP_TDO

D18

TAP_PRDY#

F16

TAP_PREQ#

AT34

RESERVED_AT34

C23

PCU_SPI_CS_0#

C21

PCU_SPI_CS_1# / GPIO_S5_21

B22

PCU_SPI_MISO

A21

PCU_SPI_MOSI

C22

PCU_SPI_CLK

B18

GPIO_S5_0

B16

GPIO_S5_1 / PMC_WAKE_PCIE_1

C18

GPIO_S5_2 / PMC_WAKE_PCIE_2

A17

GPIO_S5_3 / PMC_WAKE_PCIE_3

C17

GPIO_S5_4

C16

GPIO_S5_5 / PMU_SUSCLK_1

B14

GPIO_S5_6 / PMU_SUSCLK_2

C15

GPIO_S5_7 / PMU_SUSCLK_3

C13

GPIO_S5_8

A13

GPIO_S5_9

C19

GPIO_S5_10

N26

GPIO_RCOMP

LLEYVIEW-M_FCBGA1170

VCC

SPI_HOLD#

HOLD#(IO3)

SPI_CLK

CLK

SPI_MOSI

DI(IO0)

CC9

RC32 0_04 02_5%RS@RC3 2 0_0402_5%RS@

CC19 .1U_0402_16V7KCC19 .1U_04 02_16V7K

RC34 3.3K _0402_5%RC34 3.3K_0402_5%

CC20 10P_0402_50V8J

10P_0402_50V8J

GCLK@

YC1

NOGCLK@YC1

NOGCLK@

25MHZ_10PF_7V25000014

GND

Place near to Y C1

RTC domain

5 OF 13

1 2

Reserve for EMI(Near SPI ROM)

1 2

@EMC@CC20

@EMC@

RC36 33_0402_5%

33_0402_5%

RCL60_0402_5%

XTAL_25M_IN

RC20

RC20 1M_0402_5%

1M_0402_5%

NOGCLK@

XTAL_25M_OUT

CC10

CC10 18P_0402_50V8J

18P_0402_50V8J

NOGCLK@

SIO_UART1_RXD / GPIO_S0_SC_70

SIO_UART1_TXD / GPIO_S0_SC_71 SIO_UART1_RTS# / GPIO_S0_SC_72 SIO_UART1_CTS# / GPIO_S0_SC_73

SIO_UART2_RXD / GPIO_S0_SC_74

SIO_UART2_TXD / GPIO_S0_SC_75 SIO_UART2_RTS# / GPIO_S0_SC_76 SIO_UART2_CTS# / GPIO_S0_SC_77

PMC_SUSPWRDNACK / GPIO_S5_11

PMC_SUSCLK_0 / GPIO_S5_12 PMC_SLP_S0IX# / GPIO_S5_13

PMC_WAKE_PCIE_0# / GPIO_S5_15

PMC_PWRBTN# / GPIO_S5_16

PMC_SUS_STAT# / GPIO_S5_18

PMC_CORE_PWROK

SIO_PWM_0 / GPIO_S0_SC_94 SIO_PWM_1 / GPIO_S0_SC_95

SIO_SPI_CS# / GPIO_S0_SC_66 SIO_SPI_MISO / GPIO_S0_SC_67 SIO_SPI_MOSI / GPIO_S0_SC_68

SIO_SPI_CLK / GPIO_S0_SC_69

+1.8VALW+BIOS_SPI

SPI_CLK

@EMC@RC36

@EMC@

PMC_SLP_S4# PMC_SLP_S3#

GPIO_S5_14

PMC_ACPRESENT

PMC_BATLOW#

PMC_RSTBTN# PMC_PLTRST#

GPIO_S5_17

ILB_RTC_TEST#

ILB_RTC_RST#

PMC_RSMRST#

ILB_RTC_X1 ILB_RTC_X2

ILB_RTC_EXTPAD

RTC_VCC_P22

SVID_ALERT#

SVID_DATA

SVID_CLK

GPIO_S5_22 GPIO_S5_23 GPIO_S5_24 GPIO_S5_25 GPIO_S5_26 GPIO_S5_27 GPIO_S5_28 GPIO_S5_29 GPIO_S5_30

1.8V 3

PMC_PLTRST#

AU34 AV34 BA34 AY34

BF34 BD34 BD32 BF32

D26 G24 F18 F22 D22 J20 D20 F26 K26 J26 BG9 F20 J24 G18

C11 C12

B10 B7

C9 A9 B8 P22

B24 A25 C25

AU32 AT32

K24 N24 M20 J18 M18 K18 K20 M22 M24

AV32 BA28 AY28 AY30

+RTCVCC

PMC_PCIE_WAKE# PMC_BATLOW# GPIO_S5_14 LS_OE

32.768k output

PMC_SLP_S4# PMC_SLP_S3# GPIO_S5_14 PMC_ACIN PMC_PCIE_WAKE# PMC_BATLOW# PMC_PWRBTN#

GPIO_S5_17

RTC_TEST# EC_RSMRST# RTC_RST#

EC_RSMRST# PMC_CORE_PWROK

ILB_RTC_X1 ILB_RTC_X2 ILB_RTC_EXTPAD

+RTCVCC

VR_SVID_ALERT#_SOC VR_SVID_DATA_SOC

SSD_DETECT#

XDP_OBSDATA_A0 <13> XDP_OBSDATA_A1 <13> XDP_OBSDATA_A2 <13> XDP_OBSDATA_A3 <13>

RC30

RC30 20K_0402_1%

20K_0402_1%

1 2 1 2

RC31

RC31 20K_0402_1%

20K_0402_1%

CC18

1U_0402_6.3V6K

1 8 2 7 3 6 4 5

CLK_EC <20>

XDP_RSTBTN# <13> PMC_PLTRST# <13>

T15T15

RTC_TEST# <13>

EC_RSMRST# <13,25> PMC_CORE_PWROK <13,25>

1 2

CC14

CC14 .1U_0402_16V7K

.1U_0402_16V7K

1 2

RC38 20_0 402_1%RC38 20_0 402_1%

1 2

RC39 16.9 _0402_1%RC39 16.9 _0402_1%

CC17

CC17 1U_0402_6.3V6K

1U_0402_6.3V6K

RTC_TEST# RTC_RST#

JCMOS

JCMOS SHORT PADS

SHORT PADS

Clear CMOS RTC_RST close to RAM d oor

+1.8VALW

RPC4

10K_0804_8P4R_5%

+1.0VS

RC37

73.2_0402_1%

1 2

RC85 10K_0402_5%RC85 10K_0402_5%

ILB_RTC_X1_R<20>

Check Intel

VR_SVID_ALRT# <35>

VR_SVID_DAT < 35>

VR_SVID_CLK <35>

TP_INTR# <22>

+1.8VS

Place near to Y C2

ILB_RTC_X1 ILB_RTC_X2

CC15

18P_0402_50V8J

NOGCLK@

+1.8VS +3VS

RC21

UC2

4.7K_0402_5%

NL17SZ07DFT2G_SC70-5

SA00004BV00

FOR EMI/ESD Require 01/15

1 2

XDP_RSTBTN#

CC11

ESD@CC11

ESD@

.1U_0402_16V7K

1 2

PMC_PLTRST#

CC12

ESD@CC12

ESD@

0.01U_0402_16V7K

1 2

RC26 100K_0402_5%RC26 100K_0402_5%

PMC_CORE_PWROK

1 2

CC13 .1U_0402_16V7K

.1U_0402_16V7K

GCLK@

RCL70_0402_5%

NOGCLK@

NOGCLK@ 1 2

RC28 10M_0402_5%

NOGCLK@

1 2

YC2

32.768KHZ_12.5PF_Q13FC135000040

10mil

+RTCVCC

.3V

PLT_RST_BUF# <20,21,25>

PLT_RST Buffer

SOC_SERIRQ<9>

SOC_SCI#<7>

ESD@CC13

ESD@

CC16

CC16 18P_0402_50V8J

18P_0402_50V8J

NOGCLK@

DC1

DC1 BAS40-04_SOT23-3

BAS40-04_SOT23-3

CC8

CC8 .1U_0402_16V7K

.1U_0402_16V7K

PMC_SLP_S3# PMC_SLP_S4# SOC_KBRST# SOC_LID_OUT# SOC_SERIRQ SOC_SMI# SOC_SCI# PMC_PWRBTN#

LS_OE

PMC_CORE_PWROK

+RTCBATT

+3VL

PMC_ACIN

+1.8VALW

RC22

2.2K_0402_5%

RB751V40_SC76-2

UC3

VCCA

TXB0108PWR_TSSOP20

+1.8VS

RC83

RC83 10K_0402_5%

10K_0402_5%

SSD_DETECT#

RC84

RC84 10K_0402_5%

10K_0402_5%

DC2

+3VL

VCCB

GND

+1.35VS+3VS

UC4

NL17SZ07DFT2G_SC70-5

SA00004BV00

ACIN <25,30>

Ultra Non-Ultra

SSD_DETECT# <22>

RC27

RC27 10K_0402_5%

10K_0402_5%

1.35VV RTC

DDR_CORE_PWROK <5>

EC_SLP_S3# <25> EC_SLP_S4# <25> KB_RST# <25> EC_LID_OUT# <25> SERIRQ <2 5> EC_SMI# <25> EC_SCI# <25> PBTN_OUT# <25>

GPIO94

PROJECT_ID

0 1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2014/01/03 2014/01/03

Compal Secret Data

Deciphered Date

Compal Ele ctronics, Inc.

Title

VLV-M SOC CLK/PMU/SPI

Size Document Number Rev

Bay Trail M LA-A821P

Date: Sheet of

Date: Sheet

8 40Monday, July 01, 2013

0.1

D D

RIGHT PORT REAR(2.0)

RIGHT PORT FRONT(S&C)

LEFT PORT

USB Hub

C C

+1.8VALW

B B

RPC8

1 8

USB_OC0#

2 7

USB_OC1#

3 6

LAN_EN

4 5

PASSWORD_CLEAR#

10K_0804_8P4R_5%

ILB_LPC_CLK_0 : Output of 25MHz, Need Check w ith EC

ILB_LPC_CLK_1 is for CLK_0 f eedback.(Input) Set to Outpot for Normal Usa ge

DC3 RB751V40_SC76-2DC3 RB751V40_SC76-2

DC4 RB751V40_SC76-2DC4 RB751V40_SC76-2

USB_CHG_OC# <23,25>

USB_OC#1 <22,25 >

NOTE: Ref checklist rev1.0 p.25 USB_HSIC_RCOMP must NOT float if they are not being used.

LPC_AD0<25> LPC_AD1<25> LPC_AD2<25> LPC_AD3<25> LPC_FRAME#<25> LPC_CLK_EC<25>

SOC_SERIRQ<8>

CC21 10P_0402_50V8J

10P_0402_50V8J

USB20_P0<23> USB20_N0<23>

USB20_P1<23> USB20_N1<23>

USB20_P2<22> USB20_N2<22>

USB20_P3<23> USB20_N3<23>

@EMC@CC21

@EMC@

LAN_EN<21>

LPC_CLK_0

JPW

JPW SHORT PADS

SHORT PADS

1 2

RC411K_0402_1% RC411K_0402_1%

1 2

RC421K_0402_1% RC421K_0402_1%

1 2

RC45

45.3_0402_1%

1 2

RC47

RC47 0_0402_5%

0_0402_5%

1 2

RC49 45.3_0402_1%RC49 4 5.3_0402_1%

1 2

PASSWORD_CLEAR#

LAN_EN

ICLK_USB_TERMP ICLK_USB_TERMN

USB_OC0# USB_OC1#

USB_RCOMP

USB_PLL_MON

HSIC_RCOMP

LPC_RCOMP

RC5049.9_0402_1% RC5049.9_0402_1%

LPC_CLK_0

RC5122_0402_5% EMC@ RC5122_0402_5% E MC@

PCU_SMB_DATA PCU_SMB_CLK PCU_SMB_ALERT#

UC1F

GPIO_S5_31

GPIO_S5_32

GPIO_S5_33

GPIO_S5_34

GPIO_S5_35

GPIO_S5_36

GPIO_S5_37

GPIO_S5_38

GPIO_S5_39

GPIO_S5_40

GPIO_S5_41

GPIO_S5_42

B12

GPIO_S5_43

M16

USB_DP0

K16

USB_DN0

J14

USB_DP1

G14

USB_DN1

K12

USB_DP2

J12

USB_DN2

K10

USB_DP3

H10

USB_DN3

D10

ICLK_USB_TERMP

F10

ICLK_USB_TERMN

C20

USB_OC_0# / GPIO_S5_19

B20

USB_OC_1# / GPIO_S5_20

USB_RCOMPO

USB_RCOMPI

M13

USB_PLL_MON

USB_HSIC0_DATA

USB_HSIC0_STROBE

USB_HSIC1_DATA

USB_HSIC1_STROBE

USB_HSIC_RCOMP

BF18

LPC_RCOMP / VGA_RCOMP

BH16

ILB_LPC_AD_0 / GPIO_S0_SC_42

BJ17

ILB_LPC_AD_1 / GPIO_S0_SC_43

BJ13

ILB_LPC_AD_2 / GPIO_S0_SC_44

BG14

ILB_LPC_AD_3 / GPIO_S0_SC_45

BG17

ILB_LPC_FRAME# / GPIO_S0_SC_46

BG15

ILB_LPC_CLK_0 / GPIO_S0_SC_47

BH14

ILB_LPC_CLK_1 / GPIO_S0_SC_48

BG16

ILB_LPC_CLKRUN# / GPIO_S0_SC_49

BG13

ILB_LPC_SERIRQ / GPIO_S0_SC_50

BG12

PCU_SMB_DATA / GPIO_S0_SC_51

BH10

PCU_SMB_CLK / GPIO_S0_SC_52

BG11

PCU_SMB_ALERT# / GPIO_S0_SC_53

LLEYVIEW-M_FCBGA1170

GPIO_S0_SC_57 / PCU_UART_TXD

GPIO_S0_SC_61 / PCU_UART_RXD

ILB_8254_SPKR / GPIO_S0_SC_54

SIO_I2C0_DATA / GPIO_S0_SC_78

SIO_I2C0_CLK / GPIO_S0_SC_79

SIO_I2C1_DATA / GPIO_S0_SC_80

SIO_I2C1_CLK / GPIO_S0_SC_81

SIO_I2C2_DATA / GPIO_S0_SC_82

SIO_I2C2_CLK / GPIO_S0_SC_83

SIO_I2C3_DATA / GPIO_S0_SC_84

SIO_I2C3_CLK / GPIO_S0_SC_85

SIO_I2C4_DATA / GPIO_S0_SC_86

SIO_I2C4_CLK / GPIO_S0_SC_87

SIO_I2C5_DATA / GPIO_S0_SC_88

SIO_I2C5_CLK / GPIO_S0_SC_89

SIO_I2C6_DATA / GPIO_S0_SC_90

SIO_I2C6_CLK / GPIO_S0_SC_91 / SD3_WP

6 OF 13

RESERVED_M10

RESERVED_M9

RESERVED_P6 RESERVED_P7

RESERVED_M7

USB3_REXT0

RESERVED_P10 RESERVED_P12

RESERVED_M4 RESERVED_M6

USB3_RXP0 USB3_RXN0

USB3_TXP0 USB3_TXN0

RESERVED_H8 RESERVED_H7

RESERVED_H4 RESERVED_H5

GPIO_S0_SC_55 GPIO_S0_SC_56

GPIO_S0_SC_58 GPIO_S0_SC_59 GPIO_S0_SC_60

GPIO_S0_SC_092 GPIO_S0_SC_093

M10 M9

P6 P7

M7 M12

P10 P12

M4 M6

D4 E3

K6 K7

H8 H7

H4 H5

BD12 BC12 BD14 BC14 BF14 BD16 BC16

BH12

BH22 BG23

BG24 BH24

BG25 BJ25

BG26 BH26

BF27 BG27

BH28 BG28

BJ29 BG29

BH30 BG30

USB3_REXT0

GPIO_S0_SC_56 DBG_UART_TXD

DBG_UART_RXD

SOC_SPKR

GPIO_S0_SC_92 GPIO_S0_SC_93

1 2

RC40

1.24K_0402_1%

1 2

U3RXDP1 <23> U3RXDN1 <23>

U3TXDP1 <23> U3TXDN1 <23>

T13T13

T14T14

SOC_SPKR <24 >

RC7922_0402_5% @EMC@ RC7922_0402_5% @EMC@ RC8022_0402_5% @EMC@ RC8022_0402_5% @EMC@

T11T11 T12T12

PDA (Platform Debug Assistan t) Test Points

RIGHT PORT REAR(3.0)

+1.8VS

PM_I2CSDA1 <22> PM_I2CSCL1 <22>

RC43

@RC43

10K_0402_5%

RC48

@RC48

10K_0402_5%

GPIO_S0_SC_56: A16 Swap Overr ide 0 = Enable 1 = Disable Reference EDS Page 216

+1.8VS+1.8VS

RPC6

PCU_SMB_CLK

PCU_SMB_DATA

PCU_SMB_ALERT#

Pull High at E C side

DDR(15,16) Minicard(21)

A A

EC(24)

EC_SMB_CK2<14,15,20,22,25>

EC_SMB_DA2<14,15,20,22,25>

1 3

QC3

BSS138W-7-F_SOT323-3

QC4

BSS138W-7-F_SOT323-3

4.7K_0804_8P4R_5%

PCU_SMB_CLK

PCU_SMB_DATA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2014/01/03 2014/01/03

Compal Secret Data

Deciphered Date

Compal Ele ctronics, Inc.

Title

VLV-M SOC USB/LPC/SMBus

Size Document Number Rev

Bay Trail M LA-A821P

Date: Sheet of

9 40Monday, July 01, 2013

0.1

UC1G

+SOC_VCC

TP2_CORE_VCC_S0iX

10000mA

15000mA

RC56

RC56 100_0402_1%

100_0402_1%

RC57

RC57 100_0402_1%

100_0402_1%

+SOC_VNN

D D

C C

T9T9

+SOC_VNN +SOC_VCC

B B

VGFX_VSNS<35> VCORE_VSNS<35> VCORE_GSNS<35>

RC55

100_0402_1%

UC1G

AA27

CORE_VCC_S0iX_AA27

AA29

CORE_VCC_S0iX_AA29

AA30

CORE_VCC_S0iX_AA30

AC27

CORE_VCC_S0iX_AC27

AC29

CORE_VCC_S0iX_AC29

AC30

CORE_VCC_S0iX_AC30

AD27

CORE_VCC_S0iX_AD27

AD29

CORE_VCC_S0iX_AD29

AD30

CORE_VCC_S0iX_AD30

AF27

CORE_VCC_S0iX_AF27

AF29

CORE_VCC_S0iX_AF29

AG27

CORE_VCC_S0iX_AG27

AG29

CORE_VCC_S0iX_AG29

AG30

CORE_VCC_S0iX_AG30

P26

CORE_VCC_S0iX_P26

P27

CORE_VCC_S0iX_P27

U27

CORE_VCC_S0iX_U27

U29

CORE_VCC_S0iX_U29

V27

CORE_VCC_S0iX_V27

V29

CORE_VCC_S0iX_V29

V30

CORE_VCC_S0iX_V30

Y27

CORE_VCC_S0iX_Y27

Y29

CORE_VCC_S0iX_Y29

Y30

CORE_VCC_S0iX_Y30

AA22

TP2_CORE_VCC_S0iX

AM22

UNCORE_VNN_S3_AM22

AK32

UNCORE_VNN_S3_AK32

AK30

UNCORE_VNN_S3_AK30

AK29

UNCORE_VNN_S3_AK29

AK27

UNCORE_VNN_S3_AK27

AK25

UNCORE_VNN_S3_AK25

AK24

UNCORE_VNN_S3_AK24

AK22

UNCORE_VNN_S3_AK22

AJ24

UNCORE_VNN_S3_AJ24

AJ22

UNCORE_VNN_S3_AJ22

AG24

UNCORE_VNN_S3_AG24

AG22

UNCORE_VNN_S3_AG22

AF24

UNCORE_VNN_S3_AF24

AF22

UNCORE_VNN_S3_AF22

AD22

UNCORE_VNN_S3_AD22

AC24

UNCORE_VNN_S3_AC24

AC22

UNCORE_VNN_S3_AC22

AA24

UNCORE_VNN_S3_AA24

AD24

UNCORE_VNN_S3_AD24

BB8

UNCORE_VNN_SENSE

P28

CORE_VCC_SENSE_P28

N28

CORE_VSS_SENSE_N28

LLEYVIEW-M_FCBGA1170

DRAM_VDD_S4_AD38 DRAM_VDD_S4_AF38

DRAM_VDD_S4_A48 DRAM_VDD_S4_AK38 DRAM_VDD_S4_AM38 DRAM_VDD_S4_AV41 DRAM_VDD_S4_AV42 DRAM_VDD_S4_BB46 DRAM_VDD_S4_BD49 DRAM_VDD_S4_BD52 DRAM_VDD_S4_BD53 DRAM_VDD_S4_BF44 DRAM_VDD_S4_BG51

DRAM_VDD_S4_BJ48

DRAM_VDD_S4_C51

DRAM_VDD_S4_D44

DRAM_VDD_S4_F49

DRAM_VDD_S4_F52

DRAM_VDD_S4_F53

DRAM_VDD_S4_H46

DRAM_VDD_S4_M41 DRAM_VDD_S4_M42

DRAM_VDD_S4_V38

DRAM_VDD_S4_Y38

ICLK_V1P35_S3_F2_AG18

ICLK_V1P35_S3_F1_AJ19

VGA_V1P35_S3_F1_BD1

DRAM_V1P35_S0iX_F1_AD36

UNCORE_V1P35_S0iX_F2_AG32

UNCORE_V1P35_S0iX_F3_V36

UNCORE_V1P35_S0iX_F4_U36

UNCORE_V1P35_S0iX_F5_AA25

UNCORE_V1P35_S0iX_F6_AF19 UNCORE_V1P35_S0iX_F1_AG19

7 OF 13

AD38 AF38

A48 AK38 AM38 AV41 AV42 BB46 BD49 BD52 BD53 BF44 BG51 BJ48 C51 D44 F49 F52 F53 H46 M41 M42 V38 Y38

AG18 AJ19

BD1

AD36

AG32 V36 U36

AA25

AF19 AG19

20mil

DRAM_VDD_S4_CLK

+1.35V_SOC

VGA_V1P35_S3_F1

For EVT measurement

1 2

RC54 0_0402_5%RC54 0_0402_5%

1 2

CC23 1U_0402_6.3V6KCC23 1U_0402_6.3V6K

1 2

CC24 .1U_0402_16V7KCC24 .1U_0402_16V7K

CC25 2.2U_0402_6.3V6MCC25 2.2U_0402_6.3V6M

CC26 2.2U_0402_6.3V6MCC26 2.2U_0402_6.3V6M

CC27 2.2U_0402_6.3V6MCC27 2.2U_0402_6.3V6M

CC28 2.2U_0402_6.3V6MCC28 2.2U_0402_6.3V6M

1056mA

LC1

1 2

BLM18AG601SN1D_2P

1 2

CC29 10U_0603_6.3V6MCC29 10U_0603_6.3V6M

1 2

CC30 22U_0603_6.3V6MCC30 22U_0603_6.3V6M

1 2

CC31 1U_0402_6.3V6KCC31 1U_0402_6.3V6K

1 2

CC32 1U_0402_6.3V6KCC32 1U_0402_6.3V6K

1 2

CC33 1U_0402_6.3V6KCC33 1U_0402_6.3V6K

1 2

CC34 1U_0402_6.3V6KCC34 1U_0402_6.3V6K

1 2

CC35 1U_0402_6.3V6KCC35 1U_0402_6.3V6K

1 2

CC36 1U_0402_6.3V6KCC36 1U_0402_6.3V6K

1 2

CC37 1U_0402_6.3V6KCC37 1U_0402_6.3V6K

1 2

CC38 1U_0402_6.3V6KCC38 1U_0402_6.3V6K

1 2

CC39 1U_0402_6.3V6KCC39 1U_0402_6.3V6K

+1.35VS

PJ1

JP@PJ1

JP@

JUMP_43X118

PJ2

JP@PJ2

JP@

JUMP_43X118

+1.35V

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2014/01/03 2014/01/03

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

VLV-M SOC Power

Bay Trail M LA-A821P

0.1

10 40Monday, July 01, 2013

0.1

D D

+1.0VALW

UNCORE_V1P0_G3 1uF*4

USB3_V1P0_G3 0.01uF*1

+1.0VS

C C

B B

DRAM_V1P0_S0iX 1uF*4

DDI_V1P0_S0iX 1uF*4

UNCORE_V1P0_S0iX 22uF*3 1uF*2

PCIE_SATA_V1P0_S3 1uF*1 UNCORE_V1P0_S3 1uF*1 PCIE_V1P0_S3 1uF*1 VGA_V1P0_S3 1uF*1 USB_V1P0_S3 0.1uF*1 USB3DEV_V1P0_S3 0.01uF*1 GPIO_V1P0_S3 1uF*1 SVID_V1P0_S3 1uF*1

1 2

CC40 1U_0402_6.3V6KCC 40 1U_0402_6.3V6 K

1 2

CC41 1U_0402_6.3V6KCC 41 1U_0402_6.3V6 K

1 2

CC42 1U_0402_6.3V6KCC 42 1U_0402_6.3V6 K

1 2

CC43 1U_0402_6.3V6KCC 43 1U_0402_6.3V6 K

1 2

CC45 0.01U_0402_16V7KCC45 0.01U_0402_16V7K

1 2

CC49 1U_0402_6.3V6KCC 49 1U_0402_6.3V6 K

1 2

CC50 1U_0402_6.3V6KCC 50 1U_0402_6.3V6 K

1 2

CC52 1U_0402_6.3V6KCC 52 1U_0402_6.3V6 K

1 2

CC53 1U_0402_6.3V6KCC 53 1U_0402_6.3V6 K

1 2

CC54 1U_0402_6.3V6KCC 54 1U_0402_6.3V6 K

1 2

CC55 1U_0402_6.3V6KCC 55 1U_0402_6.3V6 K

1 2

CC56 1U_0402_6.3V6KCC 56 1U_0402_6.3V6 K

1 2

CC58 1U_0402_6.3V6KCC 58 1U_0402_6.3V6 K

1 2

CC62 22U_0603_6.3V6MCC62 22U_0603_6.3V6M

1 2

CC63 22U_0603_6.3V6MCC63 22U_0603_6.3V6M

1 2

CC65 22U_0603_6.3V6MCC65 22U_0603_6.3V6M

1 2

CC66 1U_0402_6.3V6KCC66 1U_0402_6.3V6K

1 2

CC67 1U_0402_6.3V6KCC67 1U_0402_6.3V6K

1 2

CC68 1U_0402_6.3V6KCC68 1U_0402_6.3V6K

1 2

CC70 1U_0402_6.3V6KCC70 1U_0402_6.3V6K

1 2

CC72 1U_0402_6.3V6KCC72 1U_0402_6.3V6K

1 2

CC74 1U_0402_6.3V6KCC74 1U_0402_6.3V6K

1 2

CC75 .1U_0402_16V7KCC75 .1U_0402_16V7K

1 2

CC76 0.01U_0402_16V7KCC76 0.01U_0402_16V7K

1 2

CC77 1U_0402_6.3V6KCC77 1U_0402_6.3V6K

1 2

CC78 1U_0402_6.3V6KCC78 1U_0402_6.3V6K

T10T10

TP_CORE_V1P05_S4

UC1H

U22

UNCORE_V1P0_G3_U22

V22

UNCORE_V1P0_G3_V22

UNCORE_V1P0_G3_C5

UNCORE_V1P0_G3_B6

Y19

USB3_V1P0_G3_Y19

USB3_V1P0_G3_C3

V32

SVID_V1P0_S3_V32

BJ6

VGA_V1P0_S3_BJ6

AD35

DRAM_V1P0_S0iX_AD35

AF35

DRAM_V1P0_S0iX_AF35

AF36

DRAM_V1P0_S0iX_AF36

AA36

DRAM_V1P0_S0iX_AA36

AJ36

DRAM_V1P0_S0iX_AJ36

AK35

DRAM_V1P0_S0iX_AK35

AK36

DRAM_V1P0_S0iX_AK36

Y35

DRAM_V1P0_S0iX_Y35

Y36

DRAM_V1P0_S0iX_Y36

AK19

DDI_V1P0_S0iX_AK19

AK21

DDI_V1P0_S0iX_AK21

AJ18

DDI_V1P0_S0iX_AJ18

AM16

DDI_V1P0_S0iX_AM16

AN29

VIS_V1P0_S0iX_AN29

AN30

VIS_V1P0_S0iX_AN30

V24

VIS_V1P0_S0iX_V24

Y22

VIS_V1P0_S0iX_Y22

Y24

VIS_V1P0_S0iX_Y24

AF16

UNCORE_V1P0_S3_AF16

AF18

UNCORE_V1P0_S3_AF18

Y18

UNCORE_V1P0_S3_Y18

UNCORE_V1P0_S3_G1

AK18

PCIE_V1P0_S3_AK18

AM18

PCIE_V1P0_S3_AM18

AM21

PCIE_V1P0_S3_AM21

AN21

PCIE_V1P0_S3_AN21

AN18

PCIE_SATA_V1P0_S3_AN18

AN19

SATA_V1P0_S3_AN19

AF21

UNCORE_V1P0_S0iX_AF21

AG21

UNCORE_V1P0_S0iX_AG21

M14

USB_V1P0_S3_M14

U18

USB_V1P0_S3_U18

U19

USB_V1P0_S3_U19

AN25

GPIO_V1P0_S3_AN25

RESERVED_F1

AF30

TP_CORE_V1P05_S4_AF30

LLEYVIEW-M_FCBGA1170

202mA

5487mA

CORE_V1P0_S3_AC32

CORE_V1P0_S3_Y32

CORE_V1P05_S3_AA33

CORE_V1P05_S3_AF33 CORE_V1P05_S3_AG33 CORE_V1P05_S3_AG35

CORE_V1P05_S3_U33 CORE_V1P05_S3_U35

CORE_V1P05_S3_V33

720mA

UNCORE_V1P8_G3_U24

PCU_V1P8_G3_V25 USB_V1P8_G3_N20

53mA

PMU_V1P8_G3_U25

UNCORE_V1P8_G3_AA18

84mA

UNCORE_V1P8_S3_AM30 UNCORE_V1P8_S3_AN32

UNCORE_V1P8_S3_U38

58mA

HDA_V1P5_S3_AM32

PCU_V3P3_G3_N22

10mA

USB_V3P3_G3_N18 USB_V3P3_G3_P18

13mA

VGA_V3P3_S3_AN24

SD3_V1P8V3P3_S3_AN27

LPC_V1P8V3P3_S3_AM27

35mA

USB_HSIC_V1P2_G3_V18

VSS_AD16 VSS_AD18

8 OF 13

Follow CRBv1.15

AC32

+1.05VS_SOC

Y32

AA33 AF33 AG33 AG35 U33 U35 V33

U24 V25 N20 U25 AA18

AM30 AN32 U38

AM32

N22

+3VALW_SOC

N18 P18

AN24

+3VS_SOC

AN27

AM27

V18

AD16 AD18

1 2

RC58 0_0402_5%RC5 8 0_0402_5%

1 2

CC44 0.47U_0402_6.3V6KCC44 0.47U_0402_6.3V6K

1 2

CC46 1U_0402_6.3V6KCC46 1U_0402_6.3V6K

1 2

CC47 1U_0402_6.3V6KCC47 1U_0402_6.3V6K

1 2

CC48 1U_0402_6.3V6KCC48 1U_0402_6.3V6K

1 2

CC51 1U_0402_6.3V6KCC51 1U_0402_6.3V6K

1 2

CC57 1U_0402_6.3V6KCC57 1U_0402_6.3V6K

1 2

CC59 1U_0402_6.3V6KCC59 1U_0402_6.3V6K

1 2

CC60 1U_0402_6.3V6KCC60 1U_0402_6.3V6K

1 2

CC61 1U_0402_6.3V6KCC61 1U_0402_6.3V6K

1 2

CC64 1U_0402_6.3V6KCC64 1U_0402_6.3V6K

For EVT measurement

1 2

RC59 0_0402_5%RC5 9 0_0402_5%

1 2

CC69 .1U_0402_16V7KCC69 .1U_0402_16V7K

1 2

CC71 1U_0402_6.3V6KCC71 1U_0402_6.3V6K

1 2

CC73 1U_0402_6.3V6KCC73 1U_0402_6.3V6K

For EVT measurement

1 2

RC60 0_0402_5%RC6 0 0_0402_5%

1 2

CC79 1U_0402_6.3V6KCC79 1U_0402_6.3V6K

1 2

CC80 1U_0402_6.3V6KCC80 1U_0402_6.3V6K

+1.05VS

CORE_V1P05_S3 1uF*3

+1.8VALW

PMC_V1P8_G3 1uF*1

+1.8VS

UNCORE_V1P8_S3 1uF*4

+1.5VS

HDA_LPE_V1P5V1P8_S3 1uF*1

+3VALW

USB_V3P3_G3 0.1uF*1 USB_ULPI_V1P8_S3 1uF*1 PCU_V3P3_G3 1uF*1

+3VS

VGA_V3P3_S3 1uF*1

+1.0VALW

USB_HSIC_V1P2_G3 1uF*1

Disable HSIC If the USB HSIC is not used, pi n V18 can be co nnected to either +V1P2A or +V1P0A.

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2014/01/03 2014/01/03

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

VLV-M SOC Power

Bay Trail M LA-A821P

0.1

11 40Monday, July 01, 2013

D D

UC1I

A11

VSS_A11

A15

VSS_A15

A19

VSS_A19

A23

VSS_A23

A27

VSS_A27

A31

VSS_A31

A35

VSS_A35

A39

VSS_A39

A43

VSS_A43

A47

VSS_A47

C C

B B

AA1

VSS_AA1

AA16

VSS_AA16

AA19

VSS_AA19

AA21

VSS_AA21

AA3

VSS_AA3

AA32

VSS_AA32

AA35

VSS_AA35

AA38

VSS_AA38

AA53

VSS_AA53

AB10

VSS_AB10

AB4

VSS_AB4

AB41

VSS_AB41

AB45

VSS_AB45

AB47

VSS_AB47

AB48

VSS_AB48

AB50

VSS_AB50

AB51

VSS_AB51

AB6

VSS_AB6

AC16

VSS_AC16

AC18

VSS_AC18

AC19

VSS_AC19

AC21

VSS_AC21

AC25

VSS_AC25

AC33

VSS_AC33

AC35

VSS_AC35

VSS_B2

VSS_A6

A52

VSS_A52

A51

VSS_A51

VSS_A5

A49

VSS_A49

VSS_A3

BH53

VSS_BH53

BH52

VSS_BH52

BH2

VSS_BH2

BH1

VSS_BH1

BG53

VSS_BG53

E53

VSS_E53

U16

USB_VSSA_U16

AN16

VSSA_AN16

VALLEYVIEW-M_FCBGA1170

9 OF 13

VSS_AC36 VSS_AC38 VSS_AD19 VSS_AD21 VSS_AD25 VSS_AD32 VSS_AD33 VSS_AD47

VSS_AD7

VSS_AE1 VSS_AE11 VSS_AE12 VSS_AE14

VSS_AE3

VSS_AE4 VSS_AE40 VSS_AE42 VSS_AE43 VSS_AE45 VSS_AE46 VSS_AE48 VSS_AE50 VSS_AE51 VSS_AE53

VSS_AE6

VSS_AE8

VSS_AE9 VSS_AF10 VSS_AF12 VSS_AF25 VSS_AF32 VSS_AF47 VSS_AG16 VSS_AG25 VSS_AG36

VSS_B52 VSS_B53

VSS_BE1 VSS_BE53

VSS_BG1

VSS_BJ2 VSS_BJ3

VSS_BJ5 VSS_BJ49 VSS_BJ51 VSS_BJ52

VSS_C1

VSS_C53

VSS_E1

AC36 AC38 AD19 AD21 AD25 AD32 AD33 AD47 AD7 AE1 AE11 AE12 AE14 AE3 AE4 AE40 AE42 AE43 AE45 AE46 AE48 AE50 AE51 AE53 AE6 AE8 AE9 AF10 AF12 AF25 AF32 AF47 AG16 AG25 AG36 B52 B53 BE1 BE53 BG1 BJ2 BJ3 BJ5 BJ49 BJ51 BJ52 C1 C53 E1

AG38

AH4 AH41 AH45

AH7

AH9

AJ16 AJ21 AJ25 AJ27 AJ29

AJ30 AJ32 AJ33 AJ35 AJ38

AJ53 AK10 AK14 AK16 AK33 AK41 AK44 AM12 AM19 AM24 AM25 AM29 AM33 AM35 AM36 AM40

M28

AJ1

AJ3

UC1J

VSS_AG38 VSS_AH4 VSS_AH41 VSS_AH45 VSS_AH7 VSS_AH9 VSS_AJ1 VSS_AJ16 VSS_AJ21 VSS_AJ25 VSS_AJ27 VSS_AJ29 VSS_AJ3 VSS_AJ30 VSS_AJ32 VSS_AJ33 VSS_AJ35 VSS_AJ38 VSS_AJ53 VSS_AK10 VSS_AK14 VSS_AK16 VSS_AK33 VSS_AK41 VSS_AK44 VSS_AM12 VSS_AM19 VSS_AM24 VSS_AM25 VSS_AM29 VSS_AM33 VSS_AM35 VSS_AM36 VSS_AM40 VSS_M28

VALLEYVIEW-M_FCBGA1170

10 OF 13

VSS_AH47 VSS_AH48 VSS_AH50 VSS_AH51

VSS_AH6 VSS_AM44 VSS_AM51

VSS_AM7

VSS_AN1

VSS_AN11 VSS_AN12 VSS_AN14 VSS_AN22

VSS_AN3

VSS_AN33 VSS_AN35 VSS_AN36 VSS_AN38 VSS_AN40 VSS_AN42 VSS_AN43 VSS_AN45 VSS_AN46 VSS_AN48 VSS_AN49

VSS_AN5

VSS_AN51 VSS_AN53

VSS_AN6

VSS_AN8

VSS_AN9

VSS_AP40 VSS_AT12 VSS_AT16 VSS_AT19

AH47 AH48 AH50 AH51 AH6 AM44 AM51 AM7 AN1 AN11 AN12 AN14 AN22 AN3 AN33 AN35 AN36 AN38 AN40 AN42 AN43 AN45 AN46 AN48 AN49 AN5 AN51 AN53 AN6 AN8 AN9 AP40 AT12 AT16 AT19

UC1K

AT24

VSS_AT24

AT27

VSS_AT27

AT30

VSS_AT30

AT35

VSS_AT35

AT38

VSS_AT38

AT4

VSS_AT4

AT47

VSS_AT47

AT52

VSS_AT52

AU1

VSS_AU1

AU24

VSS_AU24

AU3

VSS_AU3

AU30

VSS_AU30

AU38

VSS_AU38

AU51

VSS_AU51

AV12

VSS_AV12

AV13

VSS_AV13

AV14

VSS_AV14

AV18

VSS_AV18

AV19

VSS_AV19

AV24

VSS_AV24

AV27

VSS_AV27

AV30

VSS_AV30

AV35

VSS_AV35

AV38

VSS_AV38

AV47

VSS_AV47

AV51

VSS_AV51

AV7

VSS_AV7

AW13

VSS_AW13

AW19

VSS_AW19

AW27

VSS_AW27

AW3

VSS_AW3

AW35

VSS_AW35

AY10

VSS_AY10

AY22

VSS_AY22

AY32

VSS_AY32

VALLEYVIEW-M_FCBGA1170

11 OF 13

VSS_AY36

VSS_AY4

VSS_AY50

VSS_AY9 VSS_BA14 VSS_BA19 VSS_BA22 VSS_BA27 VSS_BA32 VSS_BA35 VSS_BA40 VSS_BA53 VSS_BB19 VSS_BB27 VSS_BB35 VSS_BC20 VSS_BC22 VSS_BC26 VSS_BC28 VSS_BC32 VSS_BC34 VSS_BC42 VSS_BD19 VSS_BD24 VSS_BD27 VSS_BD30 VSS_BD35 VSS_BE19

VSS_BE2 VSS_BE35

VSS_BE8 VSS_BF12 VSS_BF16 VSS_BF24 VSS_BF38

AY36 AY4 AY50 AY9 BA14 BA19 BA22 BA27 BA32 BA35 BA40 BA53 BB19 BB27 BB35 BC20 BC22 BC26 BC28 BC32 BC34 BC42 BD19 BD24 BD27 BD30 BD35 BE19 BE2 BE35 BE8 BF12 BF16 BF24 BF38

UC1L

BF30

VSS_BF30

BF36

VSS_BF36

BF4

VSS_BF4

BG31

VSS_BG31

BG34

VSS_BG34

BG39

VSS_BG39

BG42

VSS_BG42

BG45

VSS_BG45

BG49

VSS_BG49

BJ11

VSS_BJ11

BJ15

VSS_BJ15

BJ19

VSS_BJ19

BJ23

VSS_BJ23

BJ27

VSS_BJ27

BJ31

VSS_BJ31

BJ35

VSS_BJ35

BJ39

VSS_BJ39

BJ43

VSS_BJ43

BJ47

VSS_BJ47

BJ7

VSS_BJ7

C14

VSS_C14

C31

VSS_C31

C34

VSS_C34

C39

VSS_C39

C42

VSS_C42

C45

VSS_C45

C49

VSS_C49

D12

VSS_D12

D16

VSS_D16

D24

VSS_D24

D30

VSS_D30

D36

VSS_D36

D38

VSS_D38

E19

VSS_E19

E35

VSS_E35

VALLEYVIEW-M_FCBGA1170

12 OF 13

VSS_E8

VSS_F19

VSS_F2 VSS_F24 VSS_F27 VSS_F30 VSS_F35

VSS_F5

VSS_F7 VSS_G10 VSS_G20 VSS_G22 VSS_G26 VSS_G28 VSS_G32 VSS_G34 VSS_G42 VSS_H19 VSS_H27 VSS_H35

VSS_J1 VSS_J16 VSS_J19 VSS_J22 VSS_J27 VSS_J32 VSS_J35 VSS_J40 VSS_J53 VSS_K14 VSS_K22 VSS_K32 VSS_K36

VSS_K4

VSS_K50

UC1M

E8 F19 F2 F24 F27 F30 F35 F5 F7 G10 G20 G22 G26 G28 G32 G34 G42 H19 H27 H35 J1 J16 J19 J22 J27 J32 J35 J40 J53 K14 K22 K32 K36 K4 K50

VSS_K9

L13

VSS_L13

L19

VSS_L19

L27

VSS_L27

L35

VSS_L35

M19

VSS_M19

M26

VSS_M26

M27

VSS_M27

M34

VSS_M34

M35

VSS_M35

M38

VSS_M38

M47

VSS_M47

M51

VSS_M51

VSS_N1

N16

VSS_N16

N38

VSS_N38

N51

VSS_N51

P13

VSS_P13

P16

VSS_P16

P19

VSS_P19

P20

VSS_P20

P24

VSS_P24

P32

VSS_P32

P35

VSS_P35

P38

VSS_P38

VSS_P4

P47

VSS_P47

P52

VSS_P52

VSS_P9

T40

VSS_T40

VSS_U1

U11

VSS_U11

U12

VSS_U12

U14

VSS_U14

U21

VSS_U21

13 OF 13

VALLEYVIEW-M_FCBGA1170

VSS_U3 VSS_U30 VSS_U32 VSS_U40 VSS_U42 VSS_U43 VSS_U45 VSS_U46 VSS_U48 VSS_U49

VSS_U5 VSS_U51 VSS_U53

VSS_U6

VSS_U8

VSS_U9 VSS_V12 VSS_V16 VSS_V19 VSS_V21 VSS_V35 VSS_V40 VSS_V44 VSS_V51

VSS_V7

VSS_Y10 VSS_Y14 VSS_Y16 VSS_Y21 VSS_Y25 VSS_Y33 VSS_Y41 VSS_Y44

VSS_Y7

VSS_Y9

U3 U30 U32 U40 U42 U43 U45 U46 U48 U49 U5 U51 U53 U6 U8 U9 V12 V16 V19 V21 V35 V40 V44 V51 V7 Y10 Y14 Y16 Y21 Y25 Y33 Y41 Y44 Y7 Y9

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2014/01/03 2014/01/03

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

VLV-M SOC GND

Bay Trail M LA-A821P

0.1

12 40Monday, July 01, 2013

0.1

D D

+1.8VALW

XDP@

RC61

200_0402_5%

XDP_H_PREQ_BUF#

+1.8VS

+1.8VALW

C C

1 2

RC86

1 2

1K_0402_5%

1K_0402_5% RC62 1K_0402_5%

1K_0402_5%

+1.8VALW

XDP@

1 2

RC63 51_0402_5%

@RC86

@RC62

XDP_RSTBTN#

1 2

CC81

XDP@CC81

XDP@

.1U_0402_16V7K

XDP_H_TDO

TDO Close To XDP Conn >250 mil

B B

XDP_H_TCK<8> XDP_H_TMS<8> XDP_H_TDI<8> XDP_H_TRST#<8>

XDP_H_TDO<8> XDP_RSTBTN#<8> PMC_PLTRST#<8> RTC_TEST#<8>

RC19

0_0804_8P4R_5%

ESD@

RC44

0_0804_8P4R_5%

ESD@

XDP_H_TCK_DB

XDP_H_TMS_DB

XDP_H_TDI_DB

XDP_H_TRST#_DB

XDP_H_TDO_DB

XDP_RSTBTN#_DB

PMC_PLTRST#_DB

RTC_TEST#_DB

+1.8VALW

XDP-SFF-26Pin

CONN@

JDB1

XDP_H_PREQ_BUF#_DB XDP_H_PRDY#_DB

XDP_OBSDATA_A0_DB XDP_OBSDATA_A1_DB

XDP_OBSDATA_A2_DB XDP_OBSDATA_A3_DB

EC_RSMRST#_DB

PMC_CORE_PWROK_D B RTC_TEST#_DB

PMC_PLTRST#_DB XDP_RSTBTN#_DB

XDP_H_TDO_DB XDP_H_TRST#_DB XDP_H_TDI_DB XDP_H_TMS_DB

XDP_H_TCK_DB

XDP_OBSDATA_A1<8> XDP_OBSDATA_A0<8> XDP_H_PRDY#<8> XDP_H_PREQ_BUF#<8>

PMC_CORE_PWROK<25,8> EC_RSMRST#<25,8> XDP_OBSDATA_A3<8> XDP_OBSDATA_A2<8>

25 26

MOLEX_52435-2671_26P_P0.5

PCB Footprint = MOLEX_52435-2671_26P-T

RC46

0_0804_8P4R_5%

ESD@

1 8 2 7 3 6 4 5

RC52 0_0804_8P 4R_5%

ESD@

XDP_OBSDATA_A1_DB

XDP_OBSDATA_A0_DB

XDP_H_PRDY#_DB

XDP_H_PREQ_BUF#_DB

PMC_CORE_PWROK_D B EC_RSMRST#_DB XDP_OBSDATA_A3_DB XDP_OBSDATA_A2_DB

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2014/01/03 2014/01/03

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

VLV-M SOC Debug

Bay Trail M LA-A821P

0.1

13 40Monday, July 01, 2013

+ 28 hidden pages