Compal LA-A551P ZRMAE 10AN, Satellite M50DT, Satellite U50D, LA-A551P ZEMAE Juno 10AN, LA-A551P Iakros 10AN Schematic

A

1 1

B

C

D

E

ZRMAE/ZEMAE

2 2

LA-A551P SchematicREV

3 3

Juno/Iakros 10AN/10ANG

0.1

AMD KABINI Quad Core 25W for UMA+DIS AMD KABINI Quad Core 15W

2013-04-24 Rev 0.1

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/15 2015/09/27

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

LA-A551P

1 40Monday, May 06, 2013

E

0.1

of

A

B

C

D

E

AMD GPU

page 20

PCIe Gen2 X4

5Gbps

DP0 X4

DP1 X4

AMD FT3 APU

Jaguar Core

Integrated Yangtze FCH

AMD Sun Pro M2, 64bit with 1GB DDR3(2Gbit)

1 1

AMD Sun Pro M2, 64bit with 2GB DDR3(4Gbit)

page 12-19

LVDS/eDP Conn

HDMI Conn

Memory BUS(DDRIII)

Single Channel

1.5V DDRIII 1333/1600 MT/s APU SMBUS

USB 2.0 Left

USB port 0

page 25

USB 2.0

5V 480Mbps

USB Right1

USB2.0 port 8

page 24

200pin DDRIII-SO-DIMM X2

BANK 0, 1, 2, 3

TouchScreen

USB port 4

page 20

USB Right2

USB2.0 port 9

page 24

page 10,11

CardReader

USB port 2

page 20

Int. Camera

USB port 3

page 20

PCIeMini Card For BT

USB port 1

page 23

(1.4b & 3D)

page 21

2 2

PCIe Gen1 X1

PCIeMini Card For WLAN

PCIe port 2

page 23

RTL8106E 10/100M

PCIe port 1

3 3

page 25

APU SMBUS

2.5bps

PCIe Gen1 X1

2.5bps

BGA 769-balls

USB 3.0

5V 5Gbps

SATA Gen3 port 0

5V 6Gbps

HD Audio

3.3V 24MHz

USB Right1

USB3.0 port 0

page 24

SATA HDD

SATA port 0

page 23

HDA Codec

ALC259

page 26

USB Right2

USB3.0 port 1

page 24

SPK Conn

page 28

JHP

page 25

SPI BUS

3.3V 33HZ

LPC Bus

RTC CKT.

page 9

SPI ROM (4MB)

page 7

Touch Screen Control/B

page 20

DC/DC Interface CKT.

page 31

4 4

Sub Boards

APU SMBus

ENE KB9012

Touch Pad

3.3V 33 MHz

EC SMBus

Int.KBD

page 28page 28

page 27

CardReader RTS5176(Port 3)

Power Circuit DC/DC

page 29~38

Power On/Off CKT & Power/B

page 28

A

+USB (Port 2)+Audio Combo jack

page 25

Touch pad/LED B

page 28

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/15 2015/09/27

C

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Block Diagram

LA-A551P

2 40Monday, May 06, 2013

E

of

0.1

5

4

3

2

1

DESIGN CURRENT 0.15A

B+

D D

I

peak=12A, Imax=8.4A, Iocp min=14A

SUSP#

N-CHANNEL

TPS22966

ODD_PWR

N-CHANNEL

TPS22966

DESIGN CURRENT 0A

DESIGN CURRENT 4A

DESIGN CURRENT 2A

+3VL +5VL

+5VALW

+5VS

+5VS_ODD

RT8243A

Ipeak=8A, Imax=5.6A, Iocp min=10A

3VALW_APU_PWREN

P-CHANNEL

AO-3413

1.8_0.95VALW_PWREN

C C

SUSP#

N-CHANNEL

TPS22966

SY8032

P-CHANNEL

AO-3413

DGPU_PWR_EN

P-CHANNEL

AO-3413

LCD_ENVDD

DESIGN CURRENT 330mA

DESIGN CURRENT 2.5A

SUSP#

N-CHANNEL

TPS22966

VGA_PWRGD

N-CHANNEL

TPS22966

DESIGN CURRENT 4A

DESIGN CURRENT 1.5A

DESIGN CURRENT 60mA

+3VALW

+3VALW_APU

+3V_LAN

+1.8VALW

+1.8VS

+1.8VGS

+3VS

+LCD_VDD

+3VS_DGPU

B B

SYSON

RT8207M

1.8_0.95VALW_PWREN

Ipeak=12A, Imax=8.4A, Iocp min=13.8A

VGA_PWRGD

N-CHANNEL

TPS22966

SUSP#

DESIGN CURRENT 2A

DESIGN CURRENT 1.5A

Ipeak=2.5A, Imax=1.75A, Iocp min=16A

SY8208D

VR_ON

A A

RT8880A

GPU_DPRSLPVR

0.95VS_PWREN#

N-CHANNEL

FDS6676

Ipeak=15A, Imax=10.5A, Iocp min=30A

Ipeak=13A, Imax=9.1A, Iocp min=30A

DESIGN CURRENT 2A

Ipeak=21A, Imax=14.7A, Iocp min=40A

ISL62881

5

4

+3V_WLAN

+1.5V

+1.5VGS

+0.75VS

+0.95VALW

+0.95VS

APU_CORE

APU_CORE_NB

VGA_CORE

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2013/05/15 2015/09/27

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Power Tree

LA-A551P

of

3 40Monday, May 06, 2013

of

3 40Monday, May 06, 2013

of

1

3 40Monday, May 06, 2013

0.1

A

B

C

D

E

Voltage Rails

State

S0

S1

S3

S5 S4/AC

power plane

1 1

2 2

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

( O MEANS ON X MEANS OFF )

+RTCVCC

O

B+

O

X

+5VL

+3VL

O

X

+5VALW

+3VALW

+1.8VALW

+0.95VALW

+VSB

O

X

+1.5V

+5VS

+3VS

+0.95VS

+1.8VS

+1.5VS

+0.75VS

+APU_CORE

+APU_CORE_NB

O

X X

X

X X

UMA

OO

X

BTO Option Table

Function

PU A4-5000

description

explain

BTO

Function

description

explain

BTO

Function

description

explain

BTO

Function

description

explain

BTO

C

1

5W 4C 25W 4C

A4R1@ A6R1@

GPU

Sun-Pro M2

VGA

VGA@

LAN

8106E

106E@

8

E

MI@ @EMI@ ESD@ @ESD@ @RF@

APU

CPU A6-5200

EC

9012

9012@

S&C

TI solution

TPS2546

2546@

EMI/ESD/RF part

885

w/

885@

TPS2544

2544@

LVDS-eDP

w/ EMI

885_EMI@

LVDS eDP

LVDS@ IEDP@

Size

14" 15" W/O EMI Touch

14@

15@

CAM@

Codec

ALC259

259@

Camera & Mic

CAM@EMI@ @CAM@EMI@

Touch Screen

W/ Touch

Touch_EMI@ @Touch_EMI@

KB Light

KBL@

APU SM Bus Address (SCL0/SDA0)

3 3

+3VS DDR SO-DIMM A A0H 1010 0000 b +3VS DDR SO-DIMM B A2H 1010 0010 b +3VS WLAN

EC SM Bus1 Address

+3VL Smart Battery 16H 0001 0110 b +3VL Charger 12H 0001 0010 b

4 4

Device Address

A

HEX AddressDevicePower

HEX Address

HEX

EC SM Bus2 Address

+3VS VGA thermal 82H 1000 0010 b

DevicePowerPower

+3VS APU thermal 98H 1001 1000 b

B

HEX Address

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

3 LOW LOW

G

Issued Date

SIGNAL

SLP_S3# SLP_S5#

HIGHHIGH

HIGH HIGH

LOW

HIGH

LOW

HIGH

LOWLOW

Compal Secret Data

2013/05/15 2015/09/27

C

Compal Secret Data

Deciphered Date

APU POWER SEQUENCE

G-A

G-B

G-C

G-D

G-E

+RTC

3VALW_APU_PWREN

+3VALW_APU

1.8_0.95VALW_PWREN

+1.8VALW

+0.95VALW

SYSON

+1.5V

SUSP#

+3VS

+1.8VS

+1.5VS

+0.95VS

VR_ON

+APU_CORE

+APU_CORE_NB

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Notes List

LA-A551P

4 40Monday, May 06, 2013

E

of

0.1

5

4

3

2

1

DDR_AB_DQS[0..7]<10,11>

DDR_AB_DQS#[0..7]<10,11>

DDR_AB_MA[0..15]<10,11>

D D

DDR_AB_BS0<10,11> DDR_AB_BS1<10,11> DDR_AB_BS2<10,11> DDR_AB_DM[0..7]<10,11>

C C

DDR_A_CLK0<10> DDR_A_CLK0#<10> DDR_A_CLK1<10> DDR_A_CLK1#<10> DDR_B_CLK0<11> DDR_B_CLK0#<11> DDR_B_CLK1<11> DDR_B_CLK1#<11>

MEM_MAB_RST#<10,11> MEM_MAB_EVENT#<10,11>

DDR_A_CKE0<10> DDR_A_CKE1<10> DDR_B_CKE0<11>

B B

1 2

CC94

DDR_B_CKE1<11>

DDR_A_ODT0<10> DDR_A_ODT1<10> DDR_B_ODT0<11> DDR_B_ODT1<11>

DDR_A_SCS0#<10> DDR_A_SCS1#<10> DDR_B_SCS0#<11> DDR_B_SCS1#<11>

DDR_AB_RAS#<10,11> DDR_AB_CAS#<10,11> DDR_AB_WE#<10,11>

ESD@

180P_0402_50V8J

MEM_MAB_RST#

close to APU

+1.5V

MEMORY Reference Voltage (Cap follower checklist 1.02)

RC6

1K_0402_1%

A A

1K_0402_1%

RC8

1 2

2

CC17

CC17 1U_0402_6.3V6K

1U_0402_6.3V6K

1

1 2

DDR_AB_MA0 DDR_AB_MA1 DDR_AB_MA2 DDR_AB_MA3 DDR_AB_MA4 DDR_AB_MA5 DDR_AB_MA6 DDR_AB_MA7 DDR_AB_MA8 DDR_AB_MA9 DDR_AB_MA10 DDR_AB_MA11 DDR_AB_MA12 DDR_AB_MA13 DDR_AB_MA14 DDR_AB_MA15

DDR_AB_BS0 DDR_AB_BS1 DDR_AB_BS2

DDR_AB_DM0 DDR_AB_DM1 DDR_AB_DM2 DDR_AB_DM3 DDR_AB_DM4 DDR_AB_DM5 DDR_AB_DM6 DDR_AB_DM7

DDR_AB_DQS0 DDR_AB_DQS#0 DDR_AB_DQS1 DDR_AB_DQS#1 DDR_AB_DQS2 DDR_AB_DQS#2 DDR_AB_DQS3 DDR_AB_DQS#3 DDR_AB_DQS4 DDR_AB_DQS#4 DDR_AB_DQS5 DDR_AB_DQS#5 DDR_AB_DQS6 DDR_AB_DQS#6 DDR_AB_DQS7 DDR_AB_DQS#7

DDR_A_CLK0 DDR_A_CLK0# DDR_A_CLK1 DDR_A_CLK1# DDR_B_CLK0 DDR_B_CLK0# DDR_B_CLK1 DDR_B_CLK1#

MEM_MAB_RST# MEM_MAB_EVENT#

DDR_A_CKE0 DDR_A_CKE1 DDR_B_CKE0 DDR_B_CKE1

DDR_A_ODT0 DDR_A_ODT1 DDR_B_ODT0 DDR_B_ODT1

DDR_A_SCS0# DDR_A_SCS1# DDR_B_SCS0# DDR_B_SCS1#

DDR_AB_RAS# DDR_AB_CAS# DDR_AB_WE#

+MEM_VREF

remove from CRB_ver0C Check List 1.02

15mil

+MEM_VREF MEM_MAB_EVENT#

2

CC18

0.1U_0402_16V7K

1

UC1A

AG38

M_ADD0

W35

M_ADD1

W38

M_ADD2

W34

M_ADD3

U38

M_ADD4

U37

M_ADD5

U34

M_ADD6

R35

M_ADD7

R38

M_ADD8

N38

M_ADD9

AG34

M_ADD10

R34

M_ADD11

N37

M_ADD12

AN34

M_ADD13

L38

M_ADD14

L35

M_ADD15

AJ38

M_BANK0

AG35

M_BANK1

N34

M_BANK2

B32

M_DM0

B38

M_DM1

G40

M_DM2

N41

M_DM3

AG40

M_DM4

AN41

M_DM5

AY40

M_DM6

AY34

M_DM7

Y40

M_DM8

B33

M_DQS_H0

A33

M_DQS_L0

B40

M_DQS_H1

A40

M_DQS_L1

H41

M_DQS_H2

H40

M_DQS_L2

P41

M_DQS_H3

P40

M_DQS_L3

AH41

M_DQS_H4

AH40

M_DQS_L4

AP41

M_DQS_H5

AP40

M_DQS_L5

BA40

M_DQS_H6

AY41

M_DQS_L6

AY33

M_DQS_H7

BA34

M_DQS_L7

AA40

M_DQS_H8

Y41

M_DQS_L8

AC35

M_CLK_H0

AC34

M_CLK_L0

AA34

M_CLK_H1

AA32

M_CLK_L1

AE38

M_CLK_H2

AE37

M_CLK_L2

AA37

M_CLK_H3

AA38

M_CLK_L3

G38

M_RESET_L

AE34

M_EVENT_L

L34

M0_CKE0

J38

M0_CKE1

J37

M1_CKE0

J34

M1_CKE1

AN38

M0_ODT0

AU38

M0_ODT1

AN37

M1_ODT0

AR37

M1_ODT1

AJ34

M0_CS_L0

AR38

M0_CS_L1

AL38

M1_CS_L0

AN35

M1_CS_L1

AJ37

M_RAS_L

AL34

M_CAS_L

AL35

M_WE_L

AD40

M_VREF

AC38

M_VREFDQ

FT3_BGA769 @

MEMORY

FT3 REV 0.51

M_DATA0

M_DATA1

M_DATA2

M_DATA3

M_DATA4

M_DATA5

M_DATA6

M_DATA7

M_DATA8

M_DATA9

M_DATA10

M_DATA11

M_DATA12

M_DATA13

M_DATA14

M_DATA15

M_DATA16

M_DATA17

M_DATA18

M_DATA19

M_DATA20

M_DATA21

M_DATA22

M_DATA23

M_DATA24

M_DATA25

M_DATA26

M_DATA27

M_DATA28

M_DATA29

M_DATA30

M_DATA31

M_DATA32

M_DATA33

M_DATA34

M_DATA35

M_DATA36

M_DATA37

M_DATA38

M_DATA39

M_DATA40

M_DATA41

M_DATA42

M_DATA43

M_DATA44

M_DATA45

M_DATA46

M_DATA47

M_DATA48

M_DATA49

M_DATA50

M_DATA51

M_DATA52

M_DATA53

M_DATA54

M_DATA55

M_DATA56

M_DATA57

M_DATA58

M_DATA59

M_DATA60

M_DATA61

M_DATA62

M_DATA63

M_CHECK0

M_CHECK1

M_CHECK2

M_CHECK3

M_CHECK4

M_CHECK5

M_CHECK6

M_CHECK7

M_ZVDDIO_MEM_S

B30 A32 B35 A36 B29 A30 A34 B34

B37 A38 D40 D41 B36 A37 B41 C40

F40 F41 K40 K41 E40 E41 J40 J41

M41 N40 T41 U40 L40 M40 R40 T40

AF40 AF41 AK40 AK41 AE40 AE41 AJ40 AJ41

AM41 AN40 AT41 AU40 AL40 AM40 AR40 AT40

AV41 AW4 0 BA38 AY37 AU41 AV40 AY39 AY38

BA36 AY35 BA32 AY31 BA37 AY36 BA33 AY32

V41 W40 AB40 AC40 U41 V40 AA41 AB41

AD41

DDR_AB_D0 DDR_AB_D1 DDR_AB_D2 DDR_AB_D3 DDR_AB_D4 DDR_AB_D5 DDR_AB_D6 DDR_AB_D7

DDR_AB_D8 DDR_AB_D9 DDR_AB_D10 DDR_AB_D11 DDR_AB_D12 DDR_AB_D13 DDR_AB_D14 DDR_AB_D15

DDR_AB_D16 DDR_AB_D17 DDR_AB_D18 DDR_AB_D19 DDR_AB_D20 DDR_AB_D21 DDR_AB_D22 DDR_AB_D23

DDR_AB_D24 DDR_AB_D25 DDR_AB_D26 DDR_AB_D27 DDR_AB_D28 DDR_AB_D29 DDR_AB_D30 DDR_AB_D31

DDR_AB_D32 DDR_AB_D33 DDR_AB_D34 DDR_AB_D35 DDR_AB_D36 DDR_AB_D37 DDR_AB_D38 DDR_AB_D39

DDR_AB_D40 DDR_AB_D41 DDR_AB_D42 DDR_AB_D43 DDR_AB_D44 DDR_AB_D45 DDR_AB_D46 DDR_AB_D47

DDR_AB_D48 DDR_AB_D49 DDR_AB_D50 DDR_AB_D51 DDR_AB_D52 DDR_AB_D53 DDR_AB_D54 DDR_AB_D55

DDR_AB_D56 DDR_AB_D57 DDR_AB_D58 DDR_AB_D59 DDR_AB_D60 DDR_AB_D61 DDR_AB_D62 DDR_AB_D63

M_ZVDDIO

1 2

VENT# pull high

E

Close to APU AD40

5

4

DDR_AB_D[0..63] <10,11>

LAN

WLAN

PCIE_LANTX_ARX_N1<22>

PCIE_WLANTX_ARX_P2<23> PCIE_WLANTX_ARX_N2<23>

+0.95VS_APU_GFX +0.95VS_APU_GFX

PCIE_GTX_C_ARX_P0<12> PCIE_GTX_C_ARX_N0<12>

PCIE_GTX_C_ARX_P1<12> PCIE_GTX_C_ARX_N1<12>

VGA

PCIE_GTX_C_ARX_P2<12> PCIE_GTX_C_ARX_N2<12>

PCIE_GTX_C_ARX_P3<12> PCIE_GTX_C_ARX_N3<12>

+1.5V

RC439.2_0402_1% RC439.2_0402_1%

+1.5V

1 2

RC7 1K_0402_5%RC7 1K_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

RC1 1.69K_0402_1%RC1 1.69K_0402_1%

3

P_TX_ZVDD P_RX_ZVDD

2013/05/15 2015/09/27

UC1B

R10

P_GPP_RXP0

R8

P_GPP_RXN0

R5

P_GPP_RXP1

R4

P_GPP_RXN1

N5

P_GPP_RXP2

N4

P_GPP_RXN2

N10

P_GPP_RXP3

N8

P_GPP_RXN3

W8

P_TX_ZVDD_095

L5

P_GFX_RXP0

L4

P_GFX_RXN0

J5

P_GFX_RXP1

J4

P_GFX_RXN1

G5

P_GFX_RXP2

G4

P_GFX_RXN2

D7

P_GFX_RXP3

E7

P_GFX_RXN3

FT3_BGA769

Compal Secret Data

PCIE

L2

P_GPP_TXP0

L1

P_GPP_TXN0

K2

PCIE_ATX_LANRX_P1

K1

PCIE_ATX_LANRX_N1

J2

PCIE_ATX_WLANRX_P2

J1

PCIE_ATX_WLANRX_N2

H2 H1

W7

G2

PCIE_ATX_GRX_P0

G1

PCIE_ATX_GRX_N0

F2

PCIE_ATX_GRX_P1

F1

PCIE_ATX_GRX_N1

E2

PCIE_ATX_GRX_P2

E1

PCIE_ATX_GRX_N2

D2

PCIE_ATX_GRX_P3

D1

PCIE_ATX_GRX_N3

@

FT3 REV 0.51

GRAPHICS GPP

P_GPP_TXP1

P_GPP_TXN1

P_GPP_TXP2

P_GPP_TXN2

P_GPP_TXP3

P_GPP_TXN3

P_RX_ZVDD_095

P_GFX_TXP0

P_GFX_TXN0

P_GFX_TXP1

P_GFX_TXN1

P_GFX_TXP2

P_GFX_TXN2

P_GFX_TXP3

P_GFX_TXN3

FAN Control Circuit

+5VS

1 2

R2 0_0603_5%R2 0_0603_5%

1A

DFAN1<27>

Deciphered Date

+FAN1

0mil

1

12

C27

10U_0805_6.3V6M

SA00002XA00 EOL change use SA00003UO00 2

nd source SA00005JO00

2

U4

1

EN

2

VIN

3

VOUT

4

VSET

P2793BB0_SO8

1 2

CC3 0.1U_0402_16V7KCC3 0.1U_0402_16V7K

1 2

CC4 0.1U_0402_16V7KCC4 0.1U_0402_16V7K

1 2

CC1 0.1U_0402_16V7KCC1 0.1U_0402_16V7K

1 2

CC2 0.1U_0402_16V7KCC2 0.1U_0402_16V7K

12

RC2 1K_0402_1%RC2 1K_0402_1%

0.1U_0402_16V7KVGA@

CC5

CC5 CC6

CC6

CC7

CC7 CC8

CC8

CC9

CC9 CC10

CC10

CC11

CC11 CC12

CC12

1 2 1 2

VGA@

0.1U_0402_16V7KVGA@

0.1U_0402_16V7K

0.1U_0402_16V7KVGA@

0.1U_0402_16V7K

0.1U_0402_16V7KVGA@

+FAN1

2

12

C4

@C4

C3

10U_0805_6.3V6M

8

GND

7

GND

6

GND

5

GND

Title

Size Document Number Rev

Date: Sheet

@

1000P_0402_50V7K

1

FT3 DISP/MISC/HDT

LA-A551P

Monday, May 06, 2013

PCIE_ATX_C_LANRX_P1 <22>PCIE_LANTX_ARX_P1<22> PCIE_ATX_C_LANRX_N1 <22>

PCIE_ATX_C_WLANRX_P2 <23> PCIE_ATX_C_WLANRX_N2 <23>

JFAN

1

2

3

4

GND

5

GND

CVILU_CI4403M1HRT-NH

R1 10K_0402_5%R1 10K_0402_5%

12

FAN_SPEED1

1

C1

0.01U_0402_25V7K

@

2

1

PCIE_ATX_C_GRX_P0 <12> PCIE_ATX_C_GRX_N0 <12>

PCIE_ATX_C_GRX_P1 <12> PCIE_ATX_C_GRX_N1 <12>

PCIE_ATX_C_GRX_P2 <12> PCIE_ATX_C_GRX_N2 <12>

PCIE_ATX_C_GRX_P3 <12> PCIE_ATX_C_GRX_N3 <12>

Conn@

+3VS

LAN

WLAN

FAN_SPEED1 <27>

of

5 40

of

5 40

of

5 40

VGA

0.1

5

EDP_LCD_TXOUT0+_R

EDP_LCD_TXOUT0-_R

APU_HDMI_TX2+<21>

D D

HDMI

EDP use 2 Lane for FHD

EDP Cap co-lay

CC107

0.1U_0402_16V7K

SVT,SVC,SVD, APU_PWRGD is 1.8V Output

ROCHOT is 3.3V Input

P

+3VS

C C

CC108

EDP@

RC26 1K_0402_5%RC26 1K_0402_5%

EDP@

0.1U_0402_16V7K

12

+1.8VS

1 2

RC32 300_0402_5%RC32 300_0402_5%

1 2

RC34 300_0402_5%RC34 300_0402_5%

EDP/LVDS

APU_PROCHOT#

APU_RST#

APU_PWRGD

APU_HDMI_TX2-<21>

APU_HDMI_TX1+<21> APU_HDMI_TX1-<21>

APU_HDMI_TX0+<21> APU_HDMI_TX0-<21>

APU_HDMI_CLK+<21> APU_HDMI_CLK-<21>

EDP_LCD_TXOUT2+_R<20>

EDP_LCD_TXOUT2-_R<20>

EDP_LCD_TXOUT1+_R<20>

EDP_LCD_TXOUT1-_R<20>

EDP_LCD_TXOUT0+_R<20>

EDP_LCD_TXOUT0-_R<20>

LCD_TXCLK+<20> LCD_TXCLK-<20>

APU_SVT<36> APU_SVC<36> APU_SVD<36>

EC_SMB_CK2<13,27> EC_SMB_DA2<13,27>

APU_PWRGD<36>

APU_PROCHOT#<27,36>

+1.8VS

RPC2

1 8 2 7

+3VS

3 6 4 5

1K_8P4R_5%

RC28

B B

ESD@

1 2

CC99 1000P_0402_50V7K

ESD@

1 2

CC93

180P_0402_50V8J

DP_STEREOSYNC

APU_ALERT#

12

1K_0402_5%

APU_RST#

APU_PWRGD

APU_TDI APU_TRST#

APU_DBREQ#

APU_VDDNB_SEN_H<36> APU_VDD_SEN_H<36>

APU_VDD_SEN_L<36>

close to APU

DC1

12

APU_PROCHOT#

@ESD@

SCV00001K00

close to APU

4

0.1U_0402_16V7K

1 2

CC109

EDP@CC109

EDP@

0.1U_0402_16V7K

1 2

CC110

EDP@CC110

EDP@

LVDS@

1 2

RC75 0_0402_5%

1 2

RC76 0_0402_5%LVDS@RC76 0_0402_5%LVDS@

1 2

CC107 0_0402_5%LVDS@CC107 0_0402_5%LVDS@

1 2

CC108 0_0402_5%LVDS@CC108 0_0402_5%LVDS@

LVDS@

1 2

RC77 0_0402_5%

1 2

RC78 0_0402_5%LVDS@RC78 0_0402_5%LVDS@

TP@

T28

TP@

T32

TP@

T37

TP@

TP@ TP@

TP@

EDP_LCD_TXOUT2+ EDP_LCD_TXOUT2-

EDP_LCD_TXOUT1+ EDP_LCD_TXOUT1-

EDP_LCD_TXOUT0+ EDP_LCD_TXOUT0-

APU_PROCHOT#

T15

T18

T18 T19

T19

EDP_LCD_TXOUT2+

EDP_LCD_TXOUT2-

LCD_TXCLK+ LCD_TXCLK-

APU_RST#

APU_PWRGD

APU_ALERT#

APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBRDY APU_DBREQ#

VDDMEM_SENSE

VDD095_FB_H VDD095_FB_L

AV33 AU33

3

UC1C

DISPLAY/SVI2/JTAG/TEST

TDP1_TXP0

TDP1_TXN0

TDP1_TXP1

TDP1_TXN1

TDP1_TXP2

TDP1_TXN2

TDP1_TXP3

TDP1_TXN3

LTDP0_TXP0

LTDP0_TXN0

LTDP0_TXP1

LTDP0_TXN1

LTDP0_TXP2

LTDP0_TXN2

LTDP0_TXP3

LTDP0_TXN3

DISP_CLKIN_H

DISP_CLKIN_L

SVT

SVC

SVD

SIC

SID

APU_RST_L

LDT_RST_L

APU_PWROK

LDT_PWROK

PROCHOT_L

ALERT_L

TDI

TDO

TCK

TMS

TRST_L

DBRDY

DBREQ_L

VDDCR_NB_SENSE

VDDCR_CPU_SENSE

VDDIO_MEM_S_SENSE

VSS_SENSE

VDD_095_FB_H

VDD_095_FB_L

DISPLAY/SVI2/JTAG/TEST

DISPLAY

MISC

GIO_TSTDTM0_SERIALCLK

TEST

HDMI_EN/DP_STEREOSYNC

G31

G27

G23

A10 B10

A11 B11

A12 B12

K15 H15

D27 E29

B22 B21

B20 A20

B19 A19

A22 B18

D29 D31 D35 D33

B25 A25

D23

E25 E23

A9 B9

A4 B4

A5 B5

A6 B6

A7 B7

MISC

FT3 REV 0.51

FT3_BGA769 @

FT3 REV 0.51

DP_150_ZVSS

DP_2K_ZVSS

DP_BLON

DP_DIGON

DP_VARY_BL

TDP1_AUXP

TDP1_AUXN

TDP1_HPD

LTDP0_AUXP

LTDP0_AUXN

LTDP0_HPD

DAC_RED

DAC_GREEN

DAC_BLUE

DAC_HSYNC

DAC_VSYNC

DAC_SCL

DAC_SDA

DAC_ZVSS

THERMDA

THERMDC

DIECRACKMON

BP0

BP1

BP2

BP3

PLLTEST1

PLLTEST0

BYPASSCLK_H

BYPASSCLK_L

PLLCHRZ_H

PLLCHRZ_L

M_TEST

FREE_2

GIO_TSTDTM0_CLKINIT

USB_ATEST0

USB_ATEST1

M_ANALOGIN

M_ANALOGOUT

TMON_CAL

2

LCD_ENBKL : APU to EC to LCD

B16

DP_150_ZVSS

A21

DP_2K_ZVSS

B17

LCD_ENBKL

A17

LCD_ENVDD

A18

LCD_INT_PWM

D17

APU_HDMI_CLK

E17

APU_HDMI_DATA

H19

D15

EDP_LVDS_CLK_R

E15

EDP_LVDS_DATA_R

H17

EDP_LVDS_HPD

B14

1 2

RC13 150_0402_1%RC13 150_0402_1%

1 2

RC9 2K_0402_1%RC9 2K_0402_1%

1 2

CC101 0_0402_5%LVDS@CC101 0_0402_5%LVDS@

1 2

CC103 0_0402_5%LVDS@CC103 0_0402_5%LVDS@

LVDS_CLK&LVDS_DATA layout follow EDP AUX route 85 ohm

LCD_ENBKL <20,27> LCD_ENVDD <20> LCD_INT_PWM <20>

APU_HDMI_CLK <21> APU_HDMI_DATA <21>

HDMI_HPD <21>

EDP_LVDS_CLK <20> EDP_LVDS_DATA <20>

EDP_LVDS_HPD <20>

EDP/LVDS

HDMI

EDP/LVDS

A14

B15

G19

APU_CRT_HSYNC

E19

D19 D21

A16

DAC_ZVSS

H27

TEST4

H29

TEST5

D25 A27

TEST14

B27

TEST15

A26

TEST16

B26

TEST17

B28

TEST18

A28

TEST19

B24

TEST25_H

A24

TEST25_L

AV35

TEST28_H

AU35

TEST28_L

E33

TEST31

A29 H21

TEST36

H25

TEST37

AJ10

TEST42

AJ8

TEST43

R32

TEST39

N32

TEST40

AP29

TEST41

E21

DP_STEREOSYNC

DP_STEREOSYNC U

sed to align shutter glasses w ith the interleaved video frame

APU_HSYNC PU FOR INTERNAL(HDM I enable)

1 2

RC21 499_0402_1%RC21 499_0402_1%

TP@T1TP@

T1

TP@T2TP@

T2

TP@T3TP@

T3

TP@T4TP@

T4

TP@T5TP@

T5

TP@T6TP@

T6

TP@

T34

TP@

T35

route TEST25_H/L AND TEST28_H/ L differentially

TP@T7TP@

T7

TP@T8TP@

T8

TP@T9TP@

T9

TP@

T12

TP@

T13

TP@

T14

TP@

T16

TP@

T17

NOTE: DP_STEREOSYNC & APU_HSYN C PU FOR INTERNAL(HDMI enable), DP_STER EOSYNC & APU_HSYNC PD FOR CUSTOMER(HDMI disable)

EDP_LVDS_CLK_R

EDP_LVDS_DATA_R

HDMI DDC PU RES move

HDMI page

to

APU_CRT_HSYNC

EDP_LVDS_HPD

RC14 4.7K_0402_5%LVDS@RC14 4.7K_0402_5%LVDS@

RC15 4.7K_0402_5%LVDS@RC15 4.7K_0402_5%LVDS@

RC18 1K_0402_5%RC18 1K_0402_5%

RC45 100K_0402_5%

EDP Cap co-lay

CC103

CC101

0.1U_0402_16V7K

EDP_LVDS_HPD

LCD_ENBKL

LCD_INT_PWM

TEST25_L TEST36 TEST37

DP_STEREOSYNC

TEST36

TEST37

TEST25_H

APU_TMS

APU_TCK TEST19 TEST18

CC103

EDP@

0.1U_0402_16V7K

RC44 100K_0402_5%

RC19 100K_0402_5%RC19 100K_0402_5%

RC20 100K_0402_5%RC20 100K_0402_5%

RC35 510_0402_1%RC35 510_0402_1% RC37 1K_0402_5%@RC37 1K_0402_5%@ RC39 1K_0402_5%@RC39 1K_0402_5%@

RC36 1K_0402_5%@RC36 1K_0402_5%@

RC41 1K_0402_5%@RC41 1K_0402_5%@ RC46 1K_0402_5%@RC46 1K_0402_5%@

RC43 510_0402_1%RC43 510_0402_1%

1 8 2 7 3 6 4 5

1

1 2

@

EDP@

1 2 1 2 1 2

1 2

1 2 1 2

1 2

RPC4

1K_8P4R_5%

+3VS

12

+1.8VS

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/15 2015/09/27

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

FT3 DISP/MISC/HDT

LA-A551P

Monday, May 06, 2013

0.1

of

6 40

of

6 40

of

6 40

1

5

SATA_ATX_DRX_P0<23>

GA

SATA_ATX_DRX_N0<23>

SATA_DTX_C_ARX_N0<23> SATA_DTX_C_ARX_P0<23>

RC58 1K_0402_1%RC58 1K_0402_1%

+0.95VS

CLK_PCIE_VGA<12>

CLK_PCIE_VGA#<12>

CLK_LAN<22> CLK_LAN#<22>

CLK_WLAN<23> CLK_WLAN#<23>

CLK_PCI_EC<27,8> CLK_PCI_DDR<8>

LPC_AD0<27> LPC_AD1<27> LPC_AD2<27> LPC_AD3<27>

LPC_FRAME#<27,8>

SERIRQ<27>

RC59 1K_0402_1%RC59 1K_0402_1%

SATA HDD

D D

V

LAN WLAN

C C

EC

4

12 12

EMI@

1 2

RC62 22_0402_5%

1 2

RC63 0_0402_5%EMI@RC63 0_0402_5%EMI@

SATA_ZVSS SATA_ZVSS_095

T20

TP@

3

UC1E

BA14

SATA_TX0P

AY14

SATA_TX0N

BA16

SATA_RX0N

AY16

SATA_RX0P

AY19

SATA_TX1P

BA19

SATA_TX1N

AY17

SATA_RX1N

BA17

SATA_RX1P

AR19

SATA_ZVSS

AP19

SATA_ZVDD_095

BA30

SATA_ACT

48M_X1

48M_X2

LPC_CLK0 LPC_CLK1 APU_SPI_CLK

SATA_ACT_L/GPIO67

AY12

SATA_X1

BA12

SATA_X2

U4

GFX_CLKP

U5

GFX_CLKN

AC8

GPP_CLK0P

AC10

GPP_CLK0N

AE4

GPP_CLK1P

AE5

GPP_CLK1N

AC4

GPP_CLK2P

AC5

GPP_CLK2N

AA5

GPP_CLK3P

AA4

GPP_CLK3N

AP13

X14M_25M_48M_OSC

N2

X48M_X1

N1

X48M_X2

AY2

LPCCLK0

AW2

LPCCLK1

AT2

LAD0

AT1

LAD1

AR2

LAD2

AR1

LAD3

AP2

LFRAME_L

AP1

LDRQ0_L

AV29

SERIRQ/GPIO48

AP25

LPC_CLKRUN_L

AV2

LPC_PD_L/GEVENT5_L/SPI_TPM_CS_L

FT3_BGA769 @

CLK/SATA/USB/SPI/LPC

SATACLK

LPC

FT3 REV 0.51

USBCLK/14M_25M_48M_OSC

USB_ZVSS

USB_HSD0P

USB_HSD0N

USB_HSD1P

USB_HSD1N

USB_HSD2P

USB_HSD2N

USB_HSD3P

USB_HSD3N

USB_HSD4P

USB_HSD4N

USB_HSD5P

USB_HSD5N

USB_HSD6P

USB_HSD6N

USBSPI

USB_HSD7P

USB_HSD7N

USB_HSD8P

USB_HSD8N

USB_HSD9P

USB_HSD9N

USB_SS_ZVSS

USB_SS_ZVDD_095_USB3_DUAL

USB_SS_0TXP

USB_SS_0TXN

USB_SS_0RXP

USB_SS_0RXN

USB_SS_1TXP

USB_SS_1TXN

USB_SS_1RXP

USB_SS_1RXN

SPI_CLK/GPIO162

SPI_CS1_L/GPIO165

SPI_CS2_L/GPIO166

SPI_DO/GPIO163

SPI_DI/GPIO164

SPI_HOLD_L/GEVENT9_L

SPI_WP_L/GPIO161

W4

AG4

AL4 AL5

AJ4 AJ5

AG7 AG8

AG1 AG2

AF1 AF2

AE1 AE2

AD1 AD2

AC1 AC2

AB1 AB2

AA1 AA2

AE10 AE8

T2 T1

V2 V1

R1 R2

W1 W2

AU7 AW9 AR4 AR11 AR7 AU11 AU9

USB_ZVSS

USBSS_ZVSS USBSS_ZVDD

APU_SPI_CS1# APU_SPI_CS2# APU_SPI_MOSI APU_SPI_MISO

APU_SPI_WP#

2

1 2

RC57 11.8K_0402_1%RC57 11.8K_0402_1%

1 2

RC60 1K_0402_1%RC60 1K_0402_1%

1 2

RC61 1K_0402_1%RC61 1K_0402_1%

EMI@

1 2

RC130 0_0402_5%

T21

TP@

T22

TP@

USB20_P0 <25> USB20_N0 <25>

USB20_P1 <23> USB20_N1 <23>

USB20_P2 <25> USB20_N2 <25>

USB20_P3 <20> USB20_N3 <20>

USB20_P4 <20> USB20_N4 <20>

USB20_P8 <24> USB20_N8 <24>

USB20_P9 <24> USB20_N9 <24>

USB30_TX0P <24> USB30_TX0N <24>

USB30_RX0P <24> USB30_RX0N <24>

USB30_TX1P <24> USB30_TX1N <24>

USB30_RX1P <24> USB30_RX1N <24>

APU_SPI_CLK_R

RC10

10_0402_5%

@EMI@

CC13

10P_0402_50V8J

@EMI@

1

USB2.0-Left1 (Debug Port)

WLAN (BT) Cardreader Int. Camera

Touch Screen

USB2.0-Right1

USB2.0-Right2

+0.95VALW

USB3.0-Right1

USB3.0-Right2

12

2

1

B B

48KMHz CRYSTAL

48M_X2

1

4

1

4

1

2

48M_X1

CC23

4.7P_0402_50V8J

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/15 2015/09/27

3

RC64 1M_0402_5%RC64 1M_0402_5%

2

3

YC1

YC1 48MHZ_8PF_X3S048000D81H-W

48MHZ_8PF_X3S048000D81H-W

1

CC22

4.7P_0402_50V8J

2

A A

5

SPI ROM

EC_SPIDO<27>

EC_SPIDI<27> EC_SPICLK<27> EC_SPICS#<27>

1 2

RC66 10K_0402_5%RC66 10K_0402_5%

+3VALW_APU

Socket: SP07000F500/SP07000H900 Please place UC5 close to UC1 APU,

4MB ROM P/N: SA00004LI00

Compal Secret Data

Deciphered Date

885@

1 2

RC101 33_0402_5%

885@

1 2

RC102 33_0402_5%

885_EMI@

1 2

RC121 33_0402_5%

885@

1 2

RC124 33_0402_5%

2

4M Byte

UC5

APU_SPI_CLK_R

APU_SPI_CS1#

5

6

1

7

3

8

2

CC25

0.1U_0402_16V4Z

1

UC5

SI

SCLK

CS

HOLD

WP

VCC

MX25L3205DM2I-12G SO8

GND

2

APU_SPI_MISOAPU_SPI_MOSI

SO

4

SW said ROM can change to 4MB

Title

Size Document Number Rev

Date: Sheet

FT3-SATA/CLK/USB/SPI/LPC

LA-A551P

Monday, May 06, 2013

1

of

7 40

of

7 40

of

7 40

0.1

Follow check list & ORB_0C

esign 10 ms RC delay circuit

d on +1.8-V S5 power rail.

EC_RSMRST#<27>

D D

5

DC2

CH751H-40PT_SOD323-2

21

+1.8VALW

2

CC29

ESD@

1 2

CC97

180P_0402_50V8J

RC71

47K_0402_5%

1 2

RSMRST#

1

1U_0402_6.3V6K

SYS_PWRGD

USB_OC#0 USB_OC#2 USB_CHG_OC#

AZ_BITCLK_HD

HDA_BITCLK

AZ_SDIN0_HD

CC30

1 2

CC31

1 2

1U_0402_6.3V6K

SLP_S3# SLP_S5#

10P_0402_50V8J

RC104

20M_0402_5%

10P_0402_50V8J

AZ_BITCLK_HD<26> AZ_SDOUT_HD<26>

AZ_SDIN0_HD<26>

AZ_SYNC_HD<26>

AZ_RST_HD#<26>

YC2

4

12

32.768KHZ_7PF_Q13MC1461000100

3

1

2

+1.8VALW

1 2

RC127 10K_0402_5%RC127 10K_0402_5%

+3VALW_APU

C C

SLP_S3#, SLP_S5# PU reserve

1 2

RC128 2.2K_0402_5%

@

1 2

RC129 2.2K_0402_5%

@

RPC5

1 8 2 7 3 6 4 5

100K_8P4R_5%

10K_0402_5%

RC23

RC23 RC25

RC25

CC15

RC96 10K_0402_5%@RC96 10K_0402_5%@ RC97 10K_0402_5%@RC97 10K_0402_5%@

10K_0402_5%

@EMI@

1 2

1 2 1 2

12

APU_PCIE_WAKE#

12

APU_GPIO174

10P_0402_50V8J

STRAP PINS

B B

PULL HIGH

BOOT FAIL TIMER

CLKGEN ENABLE

DEFAULT DEFAULT

PULL LOW

BOOT FAIL TIMER DISABLED

CLKGEN DISABLED

DEFAULT

12

@

RC107

RC107 10K_0402_5%

10K_0402_5%

CLK_PCI_EC<27,7> CLK_PCI_DDR<7>

A A

LPC_FRAME#<27,7>

GEVENT2 RTC_CLK

12

RC112

RC112 2K_0402_5%

2K_0402_5%

5

SPI ROM 1.8V SPI ROM

LPC ROM

12

RC108

RC108 10K_0402_5%

10K_0402_5%

12

@

RC113

RC113 2K_0402_5%

2K_0402_5%

12

RC106

RC106 10K_0402_5%

10K_0402_5%

@

RC111

RC111 2K_0402_5%

2K_0402_5%

3.3V SPI ROM

EFAULT

D

12

4

SYS_PWRGD

close to APU

PBTN_OUT#<27>

SYS_PWRGD<27>

APU_PCIE_WAKE#<22>

SLP_S3#<27> SLP_S5#<27>

KB_RST#<27> GATEA20<27> EC_SCI#<27> EC_SMI#<27>

SLP_CHG_CB0<24>

SLP_CHG_CB1<24>

LAN_EN<22>

CLKREQ_WLAN#<23>

CLKREQ_LAN#<22>

CLKREQ_PEG#<13>

USB_OC#0<24,27>

USB_CHG_OC#<24,27>

USB_OC#2<25,27>

EMI@

1 2

RC92 33_0402_5%

1 2

RC93 33_0402_5%RC93 33_0402_5%

1 2

RC98 33_0402_5%RC98 33_0402_5%

1 2

RC100 33_0402_5%RC100 33_0402_5%

32K_X1

32K_X2

NORMAL POWR UP/RESET TIMING

FAST POWER UP/RESET TIMING FOR SIMULATION

+3VALW_APU

12

@

RC109

RC109 10K_0402_5%

10K_0402_5%

RC114

RC114 2K_0402_5%

2K_0402_5%

RC110

RC110 10K_0402_5%

10K_0402_5%

12

@

RC115

RC115 2K_0402_5%

2K_0402_5%

4

LPC_RST#_R APU_PCIE_RST#_R

RSMRST#

SYS_PWRGD

APU_PCIE_WAKE#

SLP_S3# SLP_S5#

TEST0

T24TP@T24TP@

TEST1/TMS

T25TP@T25TP@

TEST2

T27TP@T27TP@

USB_OC#0 USB_CHG_OC#

USB_OC#2

HDA_BITCLK HDA_SDOUT AZ_SDIN0_HD

HDA_SYNC HDA_RST#

32K_X1

32K_X2

RTC_CLKCLK_PCI_EC CLK_PCI_DDR LPC_FRAME# GEVENT2

DEFAULT

3

UC1D

AY4

LPC_RST_L

AY9

PCIE_RST_L

AY5

RSMRST_L

BA8

PWR_BTN_L

AM19

PWR_GOOD

AY7

T23TP@T23TP@

SYS_RESET_L/GEVENT19_L

AW1 1

WAKE_L/GEVENT8_L

AY3

SLP_S3_L

BA5

SLP_S5_L

AU13

TEST0

AY10

TEST1/TMS

AY6

TEST2

AR23

KBRST_L

AR31

GA20IN/GEVENT0_L

AN5

LPC_PME_L/GEVENT3_L

AL7

LPC_SMI_L/GEVENT23_L

AP15

AC_PRES/IR_RX0/GEVENT16_L

AV13

IR_TX0/GEVENT21_L

BA9

IR_TX1/GEVENT6_L

BA10

IR_RX1/GEVENT20_L

AV15

IR_LED_L/LLB_L/GPIO184

AU29

CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/GPIO60

AW2 9

CLK_REQ1_L/GPIO61

AR27

CLK_REQ2_L/GPIO62

AV27

CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/GPIO63

AY29

CLK_REQG_L/GPIO65/OSCIN

AY8

USB_OC0_L/SPI_TPM_CS_L/TRST_L/GEVENT12_L

AW1

USB_OC1_L/TDI/GEVENT13_L

AV1

USB_OC2_L/TCK/GEVENT14_L

AY1

USB_OC3_L/TDO/GEVENT15_L

AN2

AZ_BITCLK

AN1

AZ_SDOUT

AK2

AZ_SDIN0/GPIO167

AK1

AZ_SDIN1/GPIO168

AM1

AZ_SDIN2/GPIO169

AL2

AZ_SDIN3/GPIO170

AM2

AZ_SYNC

AL1

AZ_RST_L

AJ2

X32K_X1

AJ1

X32K_X2

FT3_BGA769 @

PANEL_SEL

TOUCH_SEL

PX5 Reserved DIS UMA

ACPI/SD/AZ/GPIO/RTC/MISC

Sequence

IR

RTC CLK

FT3 REV 0.51

H L

eDP panel

H L

Non Touch

Touch

Panel

(turn off EHCI)

Board_ID0

0 0 1 1

LVDS panel

B

oard_ID1Board Conf.

MSICHDA

0 1 0 1

SD

GPIO

BLINK/GEVENT18_L

GENINT1_L/GPIO32

GENINT2_L/GPIO33

PXS_PWREN PXS_EN# Board_ID0 Board_ID1

For DIS

PXS_PWREN

SD_PWR_CTRL

SD_CLK/GPIO73

SD_CMD/GPIO74

SD_CD/GPIO75

SD_WP/GPIO76

SD_DATA0/GPIO77

SD_DATA1/GPIO78

SD_DATA2/GPIO79

SD_DATA3/GPIO80

SD_LED/GPIO45

SCL0/GPIO43

SDA0/GPIO47

SCL1/GPIO227

SDA1/GPIO228

GPIO49

GPIO50

GPIO51

GPIO55

GPIO57

GPIO58

GPIO59

GPIO64

SPKR/GPIO66

GPIO68

GPIO69

GPIO70

GPIO71

GPIO174

GEVENT2_L

GEVENT4_L

GEVENT7_L

GEVENT10_L

GEVENT11_L

GEVENT17_L

GEVENT22_L

FANOUT0/GPIO52

FANIN0/GPIO56

RTCCLK

BA23 AY22

AY23 AY20 BA20

BA22 AY21 AY24 BA24

AY25

AU25

APU_SCLK0

AV25

APU_SDATA0

AY11

APU_SCLK1

BA11

APU_SDATA1

AP27 AY28

PW_CLEAR#

BA28 AV23

PANEL_SEL

AP21 BA26

Board_ID0

AV19

Board_ID1

AY27

PXS_RST#

BA27 AU21

PXS_PWREN

AY26

TOUCH_SEL

AV21 AM21 BA3

APU_GPIO174

AV17

GEVENT2

BA4 AR15 AP17 AP11 AN8 AU17 BA6

EC_LID_OUT#

BA29 AP23

AV31 AU31

AV11

RTC_CLK

RPC6

1 8 2 7 3 6 4 5

10K_8P4R_5%

VGA@

QC3A

2N7002KDWH_SOT363-6

6 1

QC3B

QC3B 2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

PXS_RST#

34

VGA@

EC_PXCONTROL

5

1 2

CC48

2

1 2

JPW SP@JPW SP@

GPIO174 PD CHK1.03

+3VS +3VALW_APU

Place at GPU

VGA@

PXS_EN#

EC_PXCONTROL <27>

@ESD@

180P_0402_50V8J

APU_PCIE_RST#_R

LPC_RST#_R

APU_SCLK0 <10,11,23>

APU_SDATA0 <10,11,23>

APU_SCLK1 <25> APU_SDATA1 <25>

PXS_RST# <12> APU_SPKR <26> PXS_PWREN <14,37>

SW request

EC_LID_OUT# <27>

VGA_PWRGD <15,37>

RTC_CLK <27>

1

PCIE_RST# is for PCIE devices on APU

1 2

RC68 33_0402_5%RC68 33_0402_5%

CC28

150P_0402_50V8J

A_RST# is for LPC devices

1 2

RC73 33_0402_5%RC73 33_0402_5%

150P_0402_50V8J

EC_LID_OUT#

PANEL_SEL

RC72

1

@

100K_0402_5%

2

1 2

1

RC74

CC27

APU SMBus0 for S0 , SMBus1 for S5 I

f APU_SMBUS no use pull high 1 0K

Board_ID0 Board_ID1

PXS_RST#

RC74 100K_0402_5%

100K_0402_5%

@

2

1 2

APU_SDATA0 APU_SCLK0

APU_SCLK1 APU_SDATA1

+3VS

1 8 2 7 3 6 4 5

1 2

RC137 10K_0402_5%UMA@RC137 10K_0402_5%UMA@

1 2

RC138 10K_0402_5%

UMA@

VGA@

RC133

1 2

RC94 10K_0402_5%RC94 10K_0402_5%

RC125

RC125 10K_0402_5%

10K_0402_5%

EDP@

1 2

RC126

RC126 10K_0402_5%

10K_0402_5%

LVDS@

1 2

RPC1

2.2K_8P4R_5%

APU_PCIE_RST# <12,22,23>

LPC_RST# <27>

+3VS

+3VALW_APU

+3VS

1K_0402_5%

+3VALW_APU

+3VS

RC95

RC95 10K_0402_5%

10K_0402_5%

TOUCH@

TOUCH_SEL

TOUCH@

1 2

RC99

RC99 1K_0402_5%

1K_0402_5%

NTOUCH@

1 2

close to APU

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/15 2015/09/27

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

FT3 GPIO/AZ/MISC

LA-A551P

Monday, May 06, 2013

0.1

of

8 40

of

8 40

of

8 40

1

5

1.5V OF APU

AMD CKL v1.01

VDDIO_MEM_S

+1.5V

3A

@

2

1

CC3910U_0603_6.3V6M CC3910U_0603_6.3V6M

D D

2

1

CC4010U_0603_6.3V6M CC4010U_0603_6.3V6M

2

CC330.1U_0402_16V7K CC330.1U_0402_16V7K

CC340.1U_0402_16V7K CC340.1U_0402_16V7K

CC410.1U_0402_16V7K CC410.1U_0402_16V7K

CC350.1U_0402_16V7K CC350.1U_0402_16V7K

1

2

CC420.1U_0402_16V7K CC420.1U_0402_16V7K

1

2

CC360.1U_0402_16V7K CC360.1U_0402_16V7K

CC430.1U_0402_16V7K CC430.1U_0402_16V7K

CC370.1U_0402_16V7K CC370.1U_0402_16V7K

1

2

@

CC14

47U_0805_6.3V6M

AMD CKL v1.01 4.7uF

1.8VALW & 1.8VS OF APU

VDD_18

VDD_18_ALW

+1.8VALW

1 2

RC116 0_0603_5%RC116 0_0603_5%

C C

1

CC494.7U_0603_6.3V6K CC494.7U_0603_6.3V6K

CC501U_0402_6.3V6K CC501U_0402_6.3V6K

2

+1.8VALW_APU

0.5A

1

CC521U_0402_6.3V6K CC521U_0402_6.3V6K

CC511U_0402_6.3V6K CC511U_0402_6.3V6K

2

1

CC531U_0402_6.3V6K CC531U_0402_6.3V6K

CC551U_0402_6.3V6K CC551U_0402_6.3V6K

CC541U_0402_6.3V6K CC541U_0402_6.3V6K

2

+1.8VS

CC5710U_0603_6.3V6M CC5710U_0603_6.3V6M

1

2

3.3VALW & 3.3VS OF APU

1

CC721U_0402_6.3V6K CC721U_0402_6.3V6K

2

+1.5VS

1

2

V

DDIO_33_ALW

VDDIO_33

+RTC_APU

for VDDIO_AZ_ALW 0.1A

1

CC664.7U_0603_6.3V6K CC664.7U_0603_6.3V6K

CC671U_0402_6.3V6K CC671U_0402_6.3V6K

2

Place on TOP

4.7uF 1uF 180pFAMD CKL v1.01

1 3 1

4.5uA

1

CC98

2

0.22U_0402_16V7K

+3VALW_APU

for VDDIO_33_ALW 0.2A

1

B B

CC741U_0402_6.3V6K CC741U_0402_6.3V6K

2

+3VS

RC117 0_0603_5%RC117 0_0603_5%

1 2

+3VS_APU

0.2A

CC711U_0402_6.3V6K CC711U_0402_6.3V6K

1

CC751U_0402_6.3V6K CC751U_0402_6.3V6K

2

RTC OF APU

A A

+3VL +RTC

DC5

2 1

CH751H-40PT_SOD323-2

5

4

10uF 0.1uF 180pF

2 8 4

10uF 1uF 180pF

1 7 1

1 6 1

.5A

1

CC581U_0402_6.3V6K CC581U_0402_6.3V6K

CC591U_0402_6.3V6K CC591U_0402_6.3V6K

2

1

CC691U_0402_6.3V6K CC691U_0402_6.3V6K

2

CC631U_0402_6.3V6K CC631U_0402_6.3V6K

CC621U_0402_6.3V6K CC621U_0402_6.3V6K

CC601U_0402_6.3V6K CC601U_0402_6.3V6K

CC611U_0402_6.3V6K CC611U_0402_6.3V6K

2

1

CC701U_0402_6.3V6K CC701U_0402_6.3V6K

2

2 1

12

RC123

RC123 120_0402_5%

120_0402_5%

route to 20mil

12

SP@

JCMOS

4

1

CC641U_0402_6.3V6K CC641U_0402_6.3V6K

2

RC122

1 2

10K_0402_5%

0.1A

0

+1.8VALW_APU

0.2A

+3VALW_APU

+0.95VALW_APU_USB3

0.5A

+0.95VALW_APU

4.5uA

+RTC_APU

+RTC_APU_R

3

UC1F

+1.5V

+1.5VS

.5A

1A

3A

UC1F

J35

VDDIO_MEM_S_1

L32

VDDIO_MEM_S_2

L37

VDDIO_MEM_S_3

N35

VDDIO_MEM_S_4

R31

VDDIO_MEM_S_5

R37

VDDIO_MEM_S_6

U32

VDDIO_MEM_S_7

U35

VDDIO_MEM_S_8

W31

VDDIO_MEM_S_9

W32

VDDIO_MEM_S_10

W37

VDDIO_MEM_S_11

AA31

VDDIO_MEM_S_12

AA35

VDDIO_MEM_S_13

AC32

VDDIO_MEM_S_14

AC37

VDDIO_MEM_S_15

AE31

VDDIO_MEM_S_16

AE35

VDDIO_MEM_S_17

AG32

VDDIO_MEM_S_18

AG37

VDDIO_MEM_S_19

AJ35

VDDIO_MEM_S_20

AL32

VDDIO_MEM_S_21

AL37

VDDIO_MEM_S_22

AR35

VDDIO_MEM_S_23

AL10

VDDIO_AZ_ALW_1

AL11

VDDIO_AZ_ALW_2

B1

VDD_18_ALW_1

B2

VDD_18_ALW_2

AL13

VDD_33_ALW_1

AM13

VDD_33_ALW_2

AR5

VDD_095_USB3_DUAL_1

AU4

VDD_095_USB3_DUAL_2

AV7

VDD_095_USB3_DUAL_3

AW5

VDD_095_USB3_DUAL_4

AE11

VDD_095_ALW_1

AE13

VDD_095_ALW_2

AJ11

VDD_095_ALW_3

AJ13

VDD_095_ALW_4

AN4

VDDBT_RTC_G

FT3_BGA769 @

POWER

FT3 REV 0.51

VDDCR_CPU_1

VDDCR_CPU_2

VDDCR_CPU_3

VDDCR_CPU_4

VDDCR_CPU_5

VDDCR_CPU_6

VDDCR_CPU_7

VDDCR_CPU_8

VDDCR_CPU_9

VDDCR_CPU_10

VDDCR_CPU_11

VDDCR_CPU_12

VDDCR_CPU_13

VDDCR_CPU_14

VDDCR_CPU_15

VDDCR_CPU_16

VDDCR_CPU_17

VDDCR_CPU_18

VDDCR_CPU_19

VDDCR_CPU_20

VDDCR_CPU_21

VDDCR_CPU_22

VDDCR_CPU_23

VDDCR_CPU_24

VDDCR_CPU_25

VDDCR_CPU_26

VDDCR_NB_1

VDDCR_NB_2

VDDCR_NB_3

VDDCR_NB_4

VDDCR_NB_5

VDDCR_NB_6

VDDCR_NB_7

VDDCR_NB_8

VDDCR_NB_9

VDDCR_NB_10

VDDCR_NB_11

VDDCR_NB_12

VDDCR_NB_13

VDDCR_NB_14

VDDCR_NB_15

VDDCR_NB_16

VDDCR_NB_17

VDDCR_NB_18

VDDCR_NB_19

VDDCR_NB_20

VDDCR_NB_21

VDD_18_1

VDD_18_2

VDD_18_3

VDD_18_4

VDD_33_1

VDD_33_2

VDD_095_1

VDD_095_2

VDD_095_3

VDD_095_4

VDD_095_5

VDD_095_6

VDD_095_7

VDD_095_8

VDD_095_9

VDD_095_GFX_1

VDD_095_GFX_2

VDD_095_GFX_3

L21 L23 L25 L27 L29 N21 N23 N27 R21 R23 R27 U21 U23 U27 W21 W23 W27 AA21 AA23 AA27 AC21 AC23 AC27 AE21 AE23 AE27

L13 L17 N11 N13 N17 R11 R13 R17 U13 U17 W13 W17 AA13 AA17 AC13 AC17 AE15 AE17 AE19 AG17 AG21

A2 A3 B3 C3

AM15 AM17

AG23 AG27 AJ21 AJ27 AL21 AL23 AL27 AM23 AM25

U10 W10 AA10

15A/21A

+APU_CORE

13A/17A

+APU_CORE_NB

1.5A

+1.8VS

0.2A

+3VS_APU

5A

+0.95VS_APU

0.6A

+0.95VS_APU_GFX

0.95VALW & 0.95VS OF APU

+0.95VALW

1 2

RC119 0_0603_5%RC119 0_0603_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+0.95VALW_APU_USB3

1

CC7710U_0603_6.3V6M CC7710U_0603_6.3V6M

2

2013/05/15 2015/09/27

1A

+0.95VALW

1 2

1

CC791U_0402_6.3V6K CC791U_0402_6.3V6K

CC801U_0402_6.3V6K CC801U_0402_6.3V6K

CC781U_0402_6.3V6K CC781U_0402_6.3V6K

2

RC120 0_0603_5%RC120 0_0603_5%

1

2

Compal Secret Data

Deciphered Date

2

A8 A13 A23 A31 A35 A39

B8 B13 B23 B31 B39

C1

C2

C5

C7

C9 C11 C13 C15 C17 C19 C21 C23 C25 C27 C29 C31 C33 C35 C37 C39 C41

D9 D11 D13

E3

E4

E9 E11 E13 E27 E31 E35 E38 E39

G3

G7 G11 G13 G15 G17 G21 G25 G29 G35 G37 G39 G41 H11 H13 H23 H31

+0.95VALW_APU

0.5AVDDIO_AZ_ALW

1

CC821U_0402_6.3V6K CC821U_0402_6.3V6K

CC841U_0402_6.3V6K CC841U_0402_6.3V6K

CC831U_0402_6.3V6K CC831U_0402_6.3V6K

2

UC1G

GND

VSS_1

VSS_2

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9

VSS_10

VSS_11

VSS_12

VSS_13

VSS_14

VSS_15

VSS_16

VSS_17

VSS_18

VSS_19

VSS_20

VSS_21

VSS_22

VSS_23

VSS_24

VSS_25

VSS_26

VSS_27

VSS_28

VSS_29

VSS_30

VSS_31

VSS_32

VSS_33

VSS_34

VSS_35

VSS_36

VSS_37

VSS_38

VSS_39

VSS_40

VSS_41

VSS_42

VSS_43

VSS_44

VSS_45

VSS_46

VSS_47

VSS_48

VSS_49

VSS_50

VSS_51

VSS_52

VSS_53

VSS_54

VSS_55

VSS_56

VSS_57

VSS_58

VSS_59

VSS_60

VSS_61

VSS_62

FT3 REV 0.51

FT3_BGA769 @

+0.95VS

2

PJ2

2

JUMP_43X79

@

1

CC851U_0402_6.3V6K CC851U_0402_6.3V6K

2

5A

1

CC8710U_0603_6.3V6M CC8710U_0603_6.3V6M

CC8610U_0603_6.3V6M CC8610U_0603_6.3V6M

2

1

UC1H

GND

J3

VSS_63

J7

VSS_64

J8

VSS_65

J39

VSS_66

K11

VSS_67

K13

VSS_68

K17

VSS_69

K19

VSS_70

K21

VSS_71

K23

VSS_72

K25

VSS_73

K27

VSS_74

K29

VSS_75

K31

VSS_76

L3

VSS_77

L7

VSS_78

L8

VSS_79

L10

VSS_80

L11

VSS_81

L15

VSS_82

L19

VSS_83

L31

VSS_84

L39

VSS_85

L41

VSS_86

M1

VSS_87

M2

VSS_88

N3

VSS_89

N7

VSS_90

N15

VSS_91

N19

VSS_92

N25

VSS_93

N29

VSS_94

N31

VSS_95

N39

VSS_96

P1

VSS_97

P2

VSS_98

R3

VSS_99

R7

VSS_100

R15

VSS_101

R19

VSS_102

R25

VSS_103

R29

VSS_104

R39

VSS_105

R41

VSS_106

U1

VSS_107

U2

VSS_108

U3

VSS_109

U7

VSS_110

U8

VSS_111

U11

VSS_112

U15

VSS_113

U19

VSS_114

U25

VSS_115

U29

VSS_116

U31

VSS_117

U39

VSS_118

W3

VSS_119

W5

VSS_120

W11

VSS_121

W15

VSS_122

W19

VSS_123

W25

VSS_124

AMD CKL v1.01

VDD_095_USB3_DUAL VDD_095 VDD_095_ALW VDD_095_GFX

W29 W39 W41

Y1

Y2 AA3 AA7 AA8

AA11 AA15 AA19 AA25 AA29 AA39

AC3

AC7 AC11 AC15 AC19 AC25 AC29 AC31 AC39 AC41

AE3

AE7 AE25 AE29 AE32 AE39

AG3

AG5 AG10 AG11 AG13 AG15 AG19 AG25 AG29 AG31 AG39 AG41

AH1

AH2

AJ3

AJ7 AJ15 AJ17 AJ19 AJ23 AJ25 AJ29 AJ31 AJ32 AJ39

AL3

AL8

AL15 AL17 AL19 AL25 AL29

10uF 1uF 180pF

2 3 1 2 5 1

1 1

VSS_125

VSS_126

VSS_127

VSS_128

VSS_129

VSS_130

VSS_131

VSS_132

VSS_133

VSS_134

VSS_135

VSS_136

VSS_137

VSS_138

VSS_139

VSS_140

VSS_141

VSS_142

VSS_143

VSS_144

VSS_145

VSS_146

VSS_147

VSS_148

VSS_149

VSS_150

VSS_151

VSS_152

VSS_153

VSS_154

VSS_155

VSS_156

VSS_157

VSS_158

VSS_159

VSS_160

VSS_161

VSS_162

VSS_163

VSS_164

VSS_165

VSS_166

VSS_167

VSS_168

VSS_169

VSS_170

VSS_171

VSS_172

VSS_173

VSS_174

VSS_175

VSS_176

VSS_177

VSS_178

VSS_179

VSS_180

VSS_181

VSS_182

VSS_183

VSS_184

VSS_185

VSS_186

FT3_BGA769

4

GND

FT3 REV 0.51

VSS_187

VSS_188

VSS_189

VSS_190

VSS_191

VSS_192

VSS_193

VSS_194

VSS_195

VSS_196

VSS_197

VSS_198

VSS_199

VSS_200

VSS_201

VSS_202

VSS_203

VSS_204

VSS_205

VSS_206

VSS_207

VSS_208

VSS_209

VSS_210

VSS_211

VSS_212

VSS_213

VSS_214

VSS_215

VSS_216

VSS_217

VSS_218

VSS_219

VSS_220

VSS_221

VSS_222

VSS_223

VSS_224

VSS_225

VSS_226

VSS_227

VSS_228

VSS_229

VSS_230

VSS_231

VSS_232

VSS_233

VSS_234

VSS_235

VSS_236

VSS_237

VSS_238

VSS_239

VSS_240

VSS_241

VSS_242

VSSBG_DAC

VBURN

PSEN

@

+0.95VS_APU

LC1

1 2

FBMA-L11-201209-300LMA30T

1

CC901U_0402_6.3V6K CC901U_0402_6.3V6K

CC911U_0402_6.3V6K CC911U_0402_6.3V6K

CC921U_0402_6.3V6K CC921U_0402_6.3V6K

2

FT3 PWR/GND

Monday, May 06, 2013

1

2

LA-A551P

CC881U_0402_6.3V6K CC881U_0402_6.3V6K

CC891U_0402_6.3V6K CC891U_0402_6.3V6K

2

Title

Size Document Number Rev

Date: Sheet

FBMA-L11-201209-300LMA30T

9 40

1

AL39 AL41 AM11 AM27 AM31 AN3 AN7 AN39 AP31 AR3 AR13 AR17 AR21 AR25 AR29 AR39 AR41 AU1 AU2 AU3 AU15 AU19 AU23 AU27 AU39 AV9 AW3 AW7 AW1 3 AW1 5 AW1 7 AW1 9 AW2 1 AW2 3 AW2 5 AW2 7 AW3 1 AW3 3 AW3 5 AW3 7 AW3 9 AW4 1 AY13 AY15 AY18 AY30 BA2 BA7 BA13 BA15 BA18 BA21 BA25 BA31 BA35 BA39 A15 AL31 AM29

+0.95VS_APU_GFX

0.6A

1

CC9510U_0603_6.3V6M CC9510U_0603_6.3V6M

2

of

1

CC961U_0402_6.3V6K CC961U_0402_6.3V6K

2

0.1

5

+VREF_DQA

DDR_AB_D0 DDR_AB_D1

DDR_AB_DM0

DDR_AB_D2 DDR_AB_D3

DDR_AB_D8

0.1U_0402_16V4Z

5

2

CD20

1

DDR_AB_D9

DDR_AB_DQS#1 DDR_AB_DQS1

DDR_AB_D10 DDR_AB_D11

DDR_AB_D16 DDR_AB_D17

DDR_AB_DQS#2 DDR_AB_DQS2

DDR_AB_D18 DDR_AB_D19

DDR_AB_D24 DDR_AB_D25

DDR_AB_DM3

DDR_AB_D26 DDR_AB_D27

DDR_A_CKE0

DDR_AB_BS2

DDR_AB_MA9

DDR_AB_MA8 DDR_AB_MA5

DDR_AB_MA3 DDR_AB_MA1

DDR_A_CLK0 DDR_A_CLK0#

DDR_AB_MA10 DDR_AB_BS0

DDR_AB_WE# DDR_AB_CAS#

DDR_AB_MA13 DDR_A_SCS1#

DDR_AB_D32 DDR_AB_D33

DDR_AB_DQS#4 DDR_AB_DQS4

DDR_AB_D34 DDR_AB_D35

DDR_AB_D40 DDR_AB_D41

DDR_AB_DM5

DDR_AB_D42 DDR_AB_D43

DDR_AB_D48 DDR_AB_D49

DDR_AB_DQS#6 DDR_AB_DQS6

DDR_AB_D50 DDR_AB_D51

DDR_AB_D56 DDR_AB_D57

DDR_AB_DM7

DDR_AB_D58 DDR_AB_D59

D D

C C

B B

A A

+3VS

DDR_AB_BS2<11,5>

DDR_A_CLK0<5> DDR_A_CLK0#<5>

DDR_AB_BS0<11,5>

DDR_AB_WE#<11,5>

DDR_AB_CAS#<11,5>

DDR_A_SCS1#<5>

+0.75VS

+1.5V

JDDR3L

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

LCN_DAN06-K4406-0103

Conn@

VSS DQ4 DQ5 VSS

DQS0#

DQS0

VSS DQ6 DQ7 VSS

DQ12 DQ13

VSS DM1

RESET#

VSS

DQ14 DQ15

VSS

DQ20 DQ21

VSS DM2 VSS

DQ22 DQ23

VSS

DQ28 DQ29

VSS

DQS3#

DQS3

VSS

DQ30 DQ31

VSS

CKE1

VDD

A15

A14 VDD

A11

VDD

VDD CK1

CK1#

VDD

BA1

RAS#

VDD

S0#

ODT0

VDD

ODT1

VDD

VREF_CA

VSS

DQ36 DQ37

VSS DM4 VSS

DQ38 DQ39

VSS

DQ44 DQ45

VSS

DQS5#

DQS5

VSS

DQ46 DQ47

VSS

DQ52 DQ53

VSS DM6 VSS

DQ54 DQ55

VSS

DQ60 DQ61

VSS

DQS7#

DQS7

VSS

DQ62 DQ63

VSS

EVENT#

SDA SCL

VTT

GND2

BOSS2

A7

A6 A4

A2 A0

NC

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206 208

4

+1.5V

DDR_AB_D4 DDR_AB_D5

DDR_AB_DQS#0

DDR_AB_DQS0

DDR_AB_D6 DDR_AB_D7

DDR_AB_D12 DDR_AB_D13

DDR_AB_DM1 MEM_MAB_RST#

DDR_AB_D14 DDR_AB_D15

DDR_AB_D20 DDR_AB_D21

DDR_AB_DM2

DDR_AB_D22 DDR_AB_D23

DDR_AB_D28 DDR_AB_D29

DDR_AB_DQS#3

DDR_AB_DQS3

DDR_AB_D30 DDR_AB_D31

DDR_A_CKE1

DDR_AB_MA15 DDR_AB_MA14

DDR_AB_MA11DDR_AB_MA12 DDR_AB_MA7

DDR_AB_MA6 DDR_AB_MA4

DDR_AB_MA2 DDR_AB_MA0

DDR_A_CLK1 DDR_A_CLK1#

DDR_AB_BS1 DDR_AB_RAS#

DDR_A_SCS0# DDR_A_ODT0

DDR_A_ODT1

+VREF_CAA

DDR_AB_D36 DDR_AB_D37

DDR_AB_DM4

DDR_AB_D38 DDR_AB_D39

DDR_AB_D44 DDR_AB_D45

DDR_AB_DQS#5

DDR_AB_DQS5

DDR_AB_D46 DDR_AB_D47

DDR_AB_D52 DDR_AB_D53

DDR_AB_DM6

DDR_AB_D54 DDR_AB_D55

DDR_AB_D60 DDR_AB_D61

DDR_AB_DQS#7

DDR_AB_DQS7

DDR_AB_D62 DDR_AB_D63

MEM_MAB_EVENT# APU_SDATA0 APU_SCLK0

+0.75VS

4

DDR3 SO-DIMM A Reverse Type

MEM_MAB_RST# <11,5>

DDR_A_CKE1 <5>DDR_A_CKE0<5>

DDR_A_CLK1 <5> DDR_A_CLK1# <5>

DDR_AB_BS1 <11,5> DDR_AB_RAS# <11,5>

DDR_A_SCS0# <5> DDR_A_ODT0 <5>

DDR_A_ODT1 <5>

MEM_MAB_EVENT# <11,5> APU_SDATA0 <11,23,8> APU_SCLK0 <11,23,8>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

SO-DIMM VREF

DDR_AB_DQS[0..7] <11,5>

DDR_AB_DQS#[0..7] <11,5>

DDR_AB_D[0..63] <11,5>

DDR_AB_DM[0..7] <11,5>

DDR_AB_MA[0..15] <11,5>

Layout Note: Place near JDDR3L

+1.5V

CD43

CD10 10U_0603_6.3V6MCD10 10U_0603_6.3V6M

CD11 10U_0603_6.3V6MCD11 10U_0603_6.3V6M

CD13 10U_0603_6.3V6MCD13 10U_0603_6.3V6M

CD14 10U_0603_6.3V6MCD14 10U_0603_6.3V6M

CD16 10U_0603_6.3V6MCD16 10U_0603_6.3V6M

CD18 10U_0603_6.3V6MCD18 10U_0603_6.3V6M

2013/05/15 2015/09/27

3

1 2

47U_0805_6.3V6M

Compal Secret Data

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

Deciphered Date

2

+1.5V +1.5V

12

RD1

1K_0402_1%

+VREF_CAA+VREF_DQA

2

CD1

1

0.1U_0402_16V7K

12

1

@

RD3

CD2

2

RD3

1K_0402_1%

2.2U_0402_6.3V6M

Close to JDDR3L.1 Close to JDDR3L.126

Layout Note: Place near JDDR3L.203 and 204

+1.5V

1 2

CD5 0.1U_0402_16V4ZCD5 0.1U_0402_16V4Z

1 2

CD6 0.1U_0402_16V4ZCD6 0.1U_0402_16V4Z

1 2

CD7 0.1U_0402_16V4ZCD7 0.1U_0402_16V4Z

1 2

CD8 0.1U_0402_16V4ZCD8 0.1U_0402_16V4Z

2

+0.75VS

CD9 1U_0402_6.3V6KCD9 1U_0402_6.3V6K

CD12 1U_0402_6.3V6KCD12 1U_0402_6.3V6K

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRIII-SODIMMA

LA-A551P

1

12

RD2

1K_0402_1%

2

CD3

1

0.1U_0402_16V7K

12

1

12

1

@

CD4

2

RD4

1K_0402_1%

2.2U_0402_6.3V6M

0.1

of

10 40Monday, May 06, 2013

of

10 40Monday, May 06, 2013

of

10 40Monday, May 06, 2013

5

+1.5V

+VREF_DQB

DDR_AB_D0 DDR_AB_D1

DDR_AB_DM0

DDR_AB_D2 DDR_AB_D3

D D

C C

B B

A A

+3VS

DDR_AB_BS2<10,5>

DDR_B_CLK0<5> DDR_B_CLK0#<5>

DDR_AB_BS0<10,5>

DDR_AB_WE#<10,5>

DDR_AB_CAS#<10,5>

DDR_B_SCS1#<5>

DDR_AB_D8 DDR_AB_D9

DDR_AB_DQS#1 DDR_AB_DQS1

DDR_AB_D10 DDR_AB_D11

DDR_AB_D16 DDR_AB_D17

DDR_AB_DQS#2 DDR_AB_DQS2

DDR_AB_D18 DDR_AB_D19

DDR_AB_D24 DDR_AB_D25

DDR_AB_DM3

DDR_AB_D26 DDR_AB_D27

DDR_B_CKE0

DDR_AB_BS2

DDR_AB_MA9

DDR_AB_MA8 DDR_AB_MA5

DDR_AB_MA3 DDR_AB_MA1

DDR_B_CLK0 DDR_B_CLK0#

DDR_AB_MA10 DDR_AB_BS0

DDR_AB_WE# DDR_AB_CAS#

DDR_AB_MA13 DDR_B_SCS1#

DDR_AB_D32 DDR_AB_D33

DDR_AB_DQS#4 DDR_AB_DQS4

DDR_AB_D34 DDR_AB_D35

DDR_AB_D40 DDR_AB_D41

DDR_AB_DM5

DDR_AB_D42 DDR_AB_D43

DDR_AB_D48 DDR_AB_D49

DDR_AB_DQS#6 DDR_AB_DQS6

DDR_AB_D50 DDR_AB_D51

DDR_AB_D56 DDR_AB_D57

DDR_AB_DM7

DDR_AB_D58 DDR_AB_D59

1 2

RD9 10K_0402_5%RD9 10K_0402_5%

2

CD40

1

0.1U_0402_16V4Z

5

+0.75VS

JDDR3H

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

LCN_DAN06-K4806-0103

Conn@

VSS DQ4 DQ5

VSS

DQS0#

DQS0

VSS DQ6 DQ7

VSS

DQ12 DQ13

VSS DM1

RESET#

VSS

DQ14 DQ15

VSS

DQ20 DQ21

VSS DM2

VSS

DQ22 DQ23

VSS

DQ28 DQ29

VSS

DQS3#

DQS3

VSS

DQ30 DQ31

VSS

CKE1

VDD

CK1

CK1#

VDD

BA1

RAS#

VDD

ODT0

VDD

ODT1

VDD

VREF_CA

VSS

DQ36 DQ37

VSS DM4

VSS

DQ38 DQ39

VSS

DQ44 DQ45

VSS

DQS5#

DQS5

VSS

DQ46 DQ47

VSS

DQ52 DQ53

VSS DM6

VSS

DQ54 DQ55

VSS

DQ60 DQ61

VSS

DQS7#

DQS7

VSS

DQ62 DQ63

VSS

EVENT#

SDA

SCL

VTT

GND2

BOSS2

A15 A14

A11

S0#

NC

4

+1.5V

2 4

DDR_AB_D4

6

DDR_AB_D5

8 10

DDR_AB_DQS#0

12

DDR_AB_DQS0

14 16

DDR_AB_D6

18

DDR_AB_D7

20 22

DDR_AB_D12

24

DDR_AB_D13

26 28

DDR_AB_DM1

30

MEM_MAB_RST#

32 34

DDR_AB_D14

36

DDR_AB_D15

38 40

DDR_AB_D20

42

DDR_AB_D21

44 46

DDR_AB_DM2

48 50

DDR_AB_D22

52

DDR_AB_D23

54 56

DDR_AB_D28

58

DDR_AB_D29

60 62

DDR_AB_DQS#3

64

DDR_AB_DQS3

66 68

DDR_AB_D30

70

DDR_AB_D31

72

74

DDR_B_CKE1

76 78

DDR_AB_MA15

80

DDR_AB_MA14

82 84

DDR_AB_MA11DDR_AB_MA12

86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206 208

DDR_AB_MA7

DDR_AB_MA6 DDR_AB_MA4

DDR_AB_MA2 DDR_AB_MA0

DDR_B_CLK1 DDR_B_CLK1#

DDR_AB_BS1 DDR_AB_RAS#

DDR_B_SCS0# DDR_B_ODT0

DDR_B_ODT1

+VREF_CAB

DDR_AB_D36 DDR_AB_D37

DDR_AB_DM4

DDR_AB_D38 DDR_AB_D39

DDR_AB_D44 DDR_AB_D45

DDR_AB_DQS#5 DDR_AB_DQS5

DDR_AB_D46 DDR_AB_D47

DDR_AB_D52 DDR_AB_D53

DDR_AB_DM6

DDR_AB_D54 DDR_AB_D55

DDR_AB_D60 DDR_AB_D61

DDR_AB_DQS#7 DDR_AB_DQS7

DDR_AB_D62 DDR_AB_D63

MEM_MAB_EVENT# APU_SDATA0 APU_SCLK0

+0.75VS

4

A7

A6 A4

A2 A0

DDR3 SO-DIMM B Standard Type

MEM_MAB_RST# <10,5>

DDR_B_CKE1 <5>DDR_B_CKE0<5>

DDR_B_CLK1 <5> DDR_B_CLK1# <5>

DDR_AB_BS1 <10,5> DDR_AB_RAS# <10,5>

DDR_B_SCS0# <5> DDR_B_ODT0 <5>

DDR_B_ODT1 <5>

MEM_MAB_EVENT# <10,5> APU_SDATA0 <10,23,8> APU_SCLK0 <10,23,8>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

SO-DIMM VREF

DDR_AB_DQS[0..7] <10,5>

DDR_AB_DQS#[0..7] <10,5>

DDR_AB_D[0..63] <10,5>

DDR_AB_DM[0..7] <10,5>

DDR_AB_MA[0..15] <10,5>

Layout Note: Place near JDDR3H

+1.5V

1 2

CD30 10U_0603_6.3V6MCD30 10U_0603_6.3V6M

1 2

CD31 10U_0603_6.3V6MCD31 10U_0603_6.3V6M

1 2

CD33 10U_0603_6.3V6MCD33 10U_0603_6.3V6M

1 2

CD34 10U_0603_6.3V6MCD34 10U_0603_6.3V6M

1 2

CD36 10U_0603_6.3V6MCD36 10U_0603_6.3V6M

1 2

CD38 10U_0603_6.3V6MCD38 10U_0603_6.3V6M

2013/05/15 2015/09/27

3

Layout Note: Place these 4 Caps near Command and Control signals of DIMMB

+1.5V

CD25 0.1U_0402_16V4ZCD25 0.1U_0402_16V4Z

CD26 0.1U_0402_16V4ZCD26 0.1U_0402_16V4Z

CD27 0.1U_0402_16V4ZCD27 0.1U_0402_16V4Z

CD28 0.1U_0402_16V4ZCD28 0.1U_0402_16V4Z

Compal Secret Data

Deciphered Date

2

CD21

1

0.1U_0402_16V7K

Close to JDDR3H.1

12

2

1

+1.5V

12

RD6

1K_0402_1%

+VREF_CAB+VREF_DQB

12

1

@

RD5

CD22

2

RD5

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M 1K_0402_1%

1K_0402_1%

2

1

CD23

1

@

CD24

2.2U_0402_6.3V6M

2

0.1U_0402_16V7K

Close to JDDR3H.126

Layout Note: Place near JDDRH.203 and 204

+0.75VS

12

CD29 1U_0402_6.3V6KCD29 1U_0402_6.3V6K

12

CD32 1U_0402_6.3V6KCD32 1U_0402_6.3V6K

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRIII-SODIMMB

LA-A551P

1

+1.5V

11 40Monday, May 06, 2013

12

RD8

1K_0402_1%

12

RD7

1K_0402_1%

of

0.1

A

B

C

D

E

PCIE_ATX_C_GRX_P[3..0]<5>

PCIE_ATX_C_GRX_N[3..0]<5>

1 1

2 2

3 3

CLK_PCIE_VGA<7> CLK_PCIE_VGA#<7>

3.3-V tolerant

4 4

PXS_RST#<8>

APU_PCIE_RST#<22,23,8>

A

PCIE_ATX_C_GRX_P[3..0]

PCIE_ATX_C_GRX_N[3..0]

PCIE_ATX_C_GRX_P0 PCIE_ATX_C_GRX_N0

PCIE_ATX_C_GRX_P1 PCIE_ATX_C_GRX_N1

PCIE_ATX_C_GRX_P2 PCIE_ATX_C_GRX_N2

PCIE_ATX_C_GRX_P3 PCIE_ATX_C_GRX_N3

CLK_PCIE_VGA CLK_PCIE_VGA#

12

VGA@

RV2 1K_0402_5%

GPU_RST#

12

+3VS

2

B

1

A

VGA@

RV212

RV212 100K_0402_5%

100K_0402_5%

UV1A

AA38

PCIE_RX0P

Y37

PCIE_RX0N

Y35

PCIE_RX1P

W36

PCIE_RX1N

W38

PCIE_RX2P

V37

PCIE_RX2N

V35

PCIE_RX3P

U36

PCIE_RX3N

U38

PCIE_RX4P

T37

PCIE_RX4N

T35

PCIE_RX5P

R36

PCIE_RX5N

R38

PCIE_RX6P

P37

PCIE_RX6N

P35

PCIE_RX7P

N36

PCIE_RX7N

N38

NC

M37

NC

M35

NC

L36

NC

L38

NC

K37

NC

K35

NC

J36

NC

J38

NC

H37

NC

H35

NC

G36

NC

G38

NC

F37

NC

F35

NC

E37

NC

CLOCK

AB35

PCIE_REFCLKP

AA36

PCIE_REFCLKN

AH16

TEST_PG

AA30

PERSTB

VGA@

5

UV13

P

4

Y

G

3

MC74VHC1G08DFT2G SC70 5P

PART 1 0F 9

PCI EXPRESS INTERFACE

SUN-PRO M2_FCBGA962VGA@

GPU_RST#

B

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

CALIBRATION

PCIE_CALR_TX

PCIE_CALR_RX

PCIE_GTX_C_ARX_P[3..0]

PCIE_GTX_C_ARX_N[3..0]

.1U_0402_16V7K

Y33

PCIE_GTX_ARX_P0 PCIE_GTX_C_ARX_P0

Y32

W33

PCIE_GTX_ARX_P1

W32

PCIE_GTX_ARX_N1

U33

PCIE_GTX_ARX_P2

U32

PCIE_GTX_ARX_N2 PCIE_GTX_C_ARX_N2

U30

PCIE_GTX_ARX_P3

U29

PCIE_GTX_ARX_N3 PCIE_GTX_C_ARX_N3

T33 T32

T30 T29

P33 P32

P30 P29

N33

NC

N32

NC

N30

NC

N29

NC

L33

NC

L32

NC

L30

NC

L29

NC

K33

NC

K32

NC

J33

NC

J32

NC

K30

NC

K29

NC

H33

NC

H32

NC

Y30

VGA_PCIE_CALRP

Y29

VGA_PCIE_CALRN

.1U_0402_16V7K

AC Coupling Cap acitor P

CIeR Gen1 and G en2 only: Recom mended value is 100 nF 10%.

PCIeR Gen3: Rec ommended value is 220 nF 10%.

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

1 2

RV1 1.69K_0402 _1%VGA@RV1 1.69K_0402_1%VGA@

1 2

RV3 1K_0402_1%VGA@RV3 1K_0402_1%VGA@

Issued Date

PCIE_GTX_C_ARX_P[3..0] <5>

PCIE_GTX_C_ARX_N[3..0] <5>

1 2

CV1 CV2

CV3 CV4

CV5 CV6

CV7 CV8

C

VGA@CV1

VGA@

1 2

VGA@CV2

VGA@

1 2

VGA@CV3

VGA@

1 2

VGA@CV4

VGA@

1 2

VGA@CV5

VGA@

1 2

VGA@CV6

VGA@

1 2

VGA@CV7

VGA@

1 2

VGA@CV8

VGA@

2013/05/15 2015 /09/27

PCIE_GTX_C_ARX_N0PCIE_GTX_ARX_N0

PCIE_GTX_C_ARX_P1 PCIE_GTX_C_ARX_N1

PCIE_GTX_C_ARX_P2

PCIE_GTX_C_ARX_P3

For MEMCLK 1GHz Brand

gDDR3-2Gbit

+0.95VGS

For MEMCLK 900MHz Brand

gDDR3-2Gbit

Compal Secret Data

Deciphered Date

skHynix

Samsung

skHynix

Micron

Samsung

LVDS Interface

UV1D

PART 7 0F 9

RSVD/VARY_BL

LVDS CONTROL

LVTMDP

Description

H5TQ2G63DFR-N0C

K4W2G1646E-BC1A

Comment PS_3[3:1] R_pu(ohm) R_pd(ohm)

1.5V/1GHz

Description

H5TQ2G63DFR-11C

MT41K128M16JT-1 07G:K

K4W2G1646E-BC11 1.5V/900MHz 111

D

RSVD/DIGON

TXCBP_DPB3P

TXCBM_DPB3N

TX3P_DPB2P TX3M_DPB2N

TX4P_DPB1P TX4M_DPB1N

TX5P_DPB0P TX5M_DPB0N

NC#AF35

NC#AG36

TXCAP_DPA3P

TXCAM_DPA3N

TX0P_DPA2P TX0M_DPA2N

TX1P_DPA1P TX1M_DPA1N

TX2P_DPA0P TX2M_DPA0N

SUN-PRO M2_FCBGA962VGA@

000

111

Comment PS_3[3:1]R_pu(ohm) R_pd(ohm)

1.5V/900MHz

1.35V/900MHz

1.5V/900MHz

Title

Size Document Number Rev

Custom

Date: Sheet

AK27 AJ27

AK35 AL36

AJ38 AK37

AH35 AJ36

AG38 AH37

AF35 AG36

AP34 AR34

AW37 AU35

AR37 AU39

AP35 AR35

AN36

NC

AP37

NC

4750

000

001

NC

8450 2000

4750

Compal Electronics, Inc.

PCIE/LVDS

LA-A551P

E

4750

NC

4750

NC

0.1

of

12 40Monday, May 06, 2013

of

12 40Monday, May 06, 2013

of

12 40Monday, May 06, 2013

A

+3VGS

1 1

RV12

1 8 2 7 3 6 4 5

10K_8P4R_5%

+3VGS

2 2

+3VGS

3 3

4 4

10K_8P4R_5%

CHECK VR

VR Suport PSI# and DPRSLPVR PU 10K

IF to +3VGS: PSI# :Low load current flag DPRSLPVR : Deeper sleep enable flag

GENERIC_X

ereo-sync signal.

St Indicates left/right frame, or top/bottom field. Can be left unconnected if not used.

Enable JTAG access

RV7

5.11K_0402_5%

@

1 2

Re

served signal, for normal ASIC operation.

RV9

RV9 1K_0402_5%

1K_0402_5%

VGA@

1 2

TSVDD MarsCRB Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

JTAG_TRSTB

JTAG_TDI JTAG_TMS JTAG_TCK

@

RV13

1 8

GPIO_16

2 7

GPIO_28_FDO

3 6

VGA_SMB_CK2

4 5

VGA_SMB_DA2

VGA@

GPU_DPRSLPVR<3 7>

VGA@

1 2

RV11 10K_0402_5%

GPU_DOWN#<27>

GPU_VID5<37>

GPU_VID1<37>

GPU_VID2<37>

CLKREQ_PEG#<8>

VGA@

RV14 10K_0402_5%

1 2

GPU_VID3<37> GPU_VID4<37>

PX_EN :

Hi

gh (3.3 V) switches the regulators off (enter BACO mode). Low (0 V) switches the regulators on. (Default)

TESTEN

GPIO_28_FDO

H

L

LV3

VGA@ LV3

VGA@

1 2

BLM15BD121SN1D_0402

A

MLPS

Disable

Enable

RV8

+TSVDD+1.8VGS

1

CV17

2

VGA@ CV17

VGA@

VGA_SMB_CK2 VGA_SMB_DA2

GPU_DPRSLPVR

GPU_VID5

TV1TP@TV1TP@

GPU_GPIO8

TV2TP@TV2TP@

GPU_GPIO9

TV3TP@TV3TP@

GPU_GPIO10

GPU_VID1

GPIO_16

10K_0402_5%@

1 2

GPU_VID2

TV4TP@TV4TP@

GPU_GPIO21

TV5TP@TV5TP@

GPU_GPIO22 CLKREQ_PEG#

GPU_VID3 GPU_VID4

TV9

TP@

PX_EN

JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS

TV7TP@TV7TP@

JTAG_TDO

GPIO_28_FDO

(1.8V@13mA TSVDD)

+TSVDD

1

CV18

CV19

2

1U_0402_6.3V6K

10U_0603_6.3V6M

VGA@ CV18

VGA@

VGA@ CV19

VGA@

UV1B

PART 2 0F 9

MUTI GFX

AD29

GENLK_CLK

AC29

GENLK_VSYNC

AJ21

SWAPLOCKA

AK21

SWAPLOCKB

AR8

NC

AU8

NC

AP8

DBG_CNTL0

AW8

NC

AR3

NC

AR1

NC

AU1

DBG_DATA0

AU3

DBG_DATA1

AW3

DBG_DATA2

AP6

DBG_DATA3

AW5

DBG_DATA4

AU5

DBG_DATA5

AR6

DBG_DATA6

AW6

DBG_DATA7

AU6

DBG_DATA8

AT7

DBG_DATA9

AV7

DBG_DATA10

AN7

DBG_DATA11

AV9

DBG_DATA12

AT9

DBG_DATA13

AR10

DBG_DATA14

AW10

DBG_DATA15

AU10

DBG_DATA16

AP10

DBG_DATA17

AV11

DBG_DATA18

AT11

DBG_DATA19

AR12

DBG_DATA20

AW12

DBG_DATA21

AU12

DBG_DATA22

AP12

DBG_DATA23

AJ23

SMBCLK

AH23

SMBDATA

AK26

SCL

AJ26

SDA

GENERAL PURPOSE I/O

AH20

GPIO_0

AH18

GPIO_1

AN16

GPIO_2

AH17

GPIO_5_AC_BATT

AJ17

GPIO_6_TACH

AK17

GPIO_7_BLON

AJ13

GPIO_8_ROMSO

AH15

GPIO_9_ROMSI

AJ16

GPIO_10_ROMSCK

AK16

GPIO_11

AL16

GPIO_12

AM16

GPIO_13

AM14

GPIO_14_HPD2

AM13

GPIO_15_PWRCNTL_0

AK14

GPIO_16

AG30

GPIO_17_THERMAL_INT

AN14

GPIO_18_HPD3

AM17

GPIO_19_CTF

AL13

GPIO_20_PWRCNTL_1

AJ14

GPIO_21

AK13

GPIO_22_ROMCSB

AN13

CLKREQB

AG32

GPIO_29

AG33

GPIO_30

AJ19

GENERICA

AK19

GENERICB

AJ20

GENERICC

AK20

GENERICD

AJ24

GENERICE_HPD4

AH26

GENERICF_HPD5

AH24

GENERICG_HPD6

AC30

CEC_1

AK24

HPD1

AH13

DBG_VREFG

AL21

PX_EN

AD28

TESTEN

AM23

JTAG_TRSTB

AN23

JTAG_TDI

AK23

JTAG_TCK

AL24

JTAG_TMS

AM24

JTAG_TDO

THERMAL

AF29

DPLUS

AG29

DMINUS

AK32

GPIO_28_FDO

AL31

TS_A

AJ32

TSVDD

AJ33

TSVSS

0.1U_0402_16V4Z

DEBUG

DPA

DPB

DPC

DPD

SMBus

I2C

DAC1

MLPS

BACO

DDC/AUX

DDCVGACLK

DDCVGADATA

SUN-PRO M2_FCBGA962VGA@

AVSSN

HSYNC VSYNC

AVDD

AVSSQ

VDD1DI

VSS1DI

NC_SVI2 NC_SVI2 NC_SVI2

DDC1CLK

DDC1DATA

AUX1P AUX1N

DDC2CLK

DDC2DATA

AUX2P AUX2N

B

C

D

E

MLPS

AU24

NC

AV23

NC

AT25

NC

AR24

NC

AU26

NC

AV25

NC

AT27

NC

AR26

NC

AR30

NC

AT29

NC

AV31

NC

AU30

NC

AR32

NC

AT31

NC

AT33

NC

AU32

NC

AU14

NC

AV13

NC

AT15

NC

AR14

NC

AU16

NC

AV15

NC

AT17

NC

AR16

NC

AU20

NC

AT19

NC

AT21

NC

AR20

NC

AU22

NC

AV21

NC

AT23

NC

AR22

NC

AD39

R

AD37

AE36

G

AD35

AF37

B

AE38

AC36 AC38

AB34

RSET

AD34 AE34

AC33 AC34

V13

NC

U13

NC

AF33

NC

AF32

NC

AA29

NC

AG21

NC

AC32

NC

AC31 AD30 AD32

AM34

PS_0

AD31

PS_1

AG31

PS_2

AD33

PS_3

AM26 AN26

AM27 AL27

AM19 AL19

AN20 AM20

AL30

NC

AM30

NC

AL29

NC

AM29

NC

AN21

NC

AM21

NC

AK30

NC

AK29

NC

AJ30 AJ31

B

Mars MLPS configuration

Bits[5:1]

xx

000

xx001

xx010

xx011

xx100

xx101

xx110

xx111

00xxx

01xxx

10xxx

11xxx

Pin Name

GPIO_0

GPIO_5_AC_BATT

GPIO_6

GPIO_15_PWRCNTL_0

GPIO_20_PWRCNTL_1

GPIO_29

GPIO_30

GPIO_8_ROMSO

GPIO_9_ROMSI

GPIO_10_ROMSCK

GPIO_22_ROMCSB

GPIO_17_THERMAL_INT

GPIO_19_CTF

GPIO_21

GPIO_28_FDO

CLKREQB

PX_EN

PD(1%) CapPU(1%)

NC 4.75k

8.45k 2.00k

4.53k 2.00k

6.98k 4.99k

4.53k 4.99k

3.24k 5.62k

3.40k 10.0k

4.75k NC

Type PD/PU Description

I/O

3.3 V (VDDR3)

I/O

3.3 V (VDDR3)

I/O

3.3 V (VDDR3)

I

3.3 V (VDDR3)

O

3.3 V (VDDR3)

I/O

3.3 V (VDDR3)

O

3.3 V (VDDR3)

I/O

3.3 V (VDDR3)

I/O

3.3 V (VDDR3)

O

O PD

Primary Memory Aperture Size Requested at PCI Configuration

Size of the Primary

emory Apertures

M

ROM_CONFIG [2:0]

128 MB

256 MB

64 MB

Reserved

512 MB

680nF

82nF

10nF

NC

PD-reset

1 GB

2 GB

4 GB Not supported

Power-state indicator. Permits the voltage regulator to activate power-saving features. IF VR Suport PSI# and DPRSLPVR PU 10K to +3VGS. PSI# :Low load current flag DPRSLPVR : Deeper sleep enable flag

(Optional) An input which allows the system to request a fastpower reduction by setting GPIO_5_AC_BATT to low (0 V). The resulting state transition may disturb the display momentarily. Power reductions that are less time critical should use the standard software methods in order to prevent display disturbances.

Voltage control signals for the core (VDDC and VDDCI). At reset, these signals will be inputs with weak internal pulldown resistors. The VBIOS can define all voltage-control signals to be either 3.3-V or open-drain outputs (all signals must be the same type). The output states (high/low) of these pins are programmable for each AMD PowerPlay state when they are used as voltage control signals. Note: GPIO_29 and GPIO_30 are only available on 28-nm ASICs, and are NC on earlier generation ASICs.

Serial-ROM output from ROM. General purpose I/O or open-drain output.

Design: No use external VGA ROM, so use the test point.

Serial-ROM input to ROM. General purpose I/O or open-drain output.

Serial-ROM clock to ROM. General purpose I/O or open-drain output.

BIOS-ROM chip select. Used to enable the ROM for ROM read and program operations.

Design: No use external VGA ROM, so use the test po

ints.

Thermal monitor interrupt. An input from an external temperature sensor (ALERTb).

Critical temperature fault (CTF) (active high) will output 3.3 V if the on-die temperature sensor exceeds a critical temperature so that the motherboard can protect the ASIC from damage by removing power. The CTF setpoint is 109 by default, and is programmed during ASIC initialization. See the advisory for AMD PowerPlay states for more details.

(Optional) Voltage control signal for the memory-voltage regulator. Note: This signal must be low (0 V) at reset (failure to do so will prevent booting).

Disable MLPS: PU 10K ohm to 3.3V. (Do not install for Mars) Enable MLPS: PD 10K ohm to GND. (Install for Mars)

Supports the CLKREQB feature for saving power to turn on/off the REFCLK clock on the ASIC.

On/off regulator switch in AMD PowerXpress? (switchable graphics) BACO mode. High (3.3 V) switches the regulators off (enter BACO mode). Low (0 V) switches the regulators on. (Default) PX_EN is tri-state before internal TEST_PG is asserted and PERSTb is deasserted.

Not supported

℃℃℃℃

C

000

001

010

011

MLPS Bit Strap Name Description Settings

ROM_CONFIG[0]

PS_0[1]

ROM_CONFIG[1]

PS_0[2]

ROM_CONFIG[2]

PS_0[3]

PS_0[4] N/A

STRAP_BIF_

PS_1[1]

GEN3_EN_A

PS_1[2] STRAP_BIF_

CLK_PM_EN

PS_1[3] N/A Reserved for internal use only. Must be 0 at reset.

PS_1[4] TX_PWRS_ENB

PS_1[5] TX_DEEMPH_EN

PS_2[1]

N/A

PS_2[2]

N/A

PS_2[3] BIOS_ROM_EN

PS_2[4] BIF_VGA_DIS

PS_2[5] N/A Reserved.

PS_3[1]

BOARD_CONFIG[0]

PS_3[2]

BOARD_CONFIG[1]

PS_3[3]

BOARD_CONFIG[2]

PS_0[5]

AUD_PORT_CONN_

PS_3[4]

PINSTRAP[0]

PS_3[5]

AUD_PORT_CONN_ PINSTRAP[1]

AUD_PORT_CONN_ PINSTRAP[2]

MLPS Strap

1 1

PS_0[5:1]

1 1

PS_1[5:1]

0 0

PS_2[5:1]

1 1

PS_3[5:1]

PS_0 PS_1 PS_2 PS_3

@

VGA@

1

CV22

CV20

CV21

2

0.01U_0402_16V7K

0.68U_0402_10V6K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Legacy

GPIO[13:11]

GENLK_VSYNC

GPIO_2

GPIO_8

If BIOS_ROM_EN = 1, ROM_CONFIG[2:0] define the ROM type. If BIOS_ROM_EN = 0, ROM_CONFIG[2:0] define the primary memory-aperture size. Refer to current databooks for details.

Reserved for internal use only. Must be 1 at reset.

Re-defined strap to indicate PCIe GEN3 capability. 1 = PCIe GEN3 supported. 0 = PCIe GEN3 not supported.

Determines whether or not the PCIe reference clock power management capability is reported in the PCI configuration space (otherwise known as CLKREQB). 0 = The CLKREQB power management capability is disabled 1 = The CLKREQB power management capability is enabled

GENLK_CLK

GPIO_0

GPIO_1

N/A

GPIO_22

GPIO_9

Transmitter (Tx) power savings enable. 0 = 50% Tx output swing. 1 = Full Tx output swing.

PCI EXPRESS transmitter, deemphasis enable. 0 = Tx deemphasis disabled. 1 = Tx deemphasis enabled.

Reserved.

To enable the external BIOS ROM device. 0 = Disable the external BIOS ROM device. 1 = Enable the external BIOS ROM device.

VGA disable determines whether or not the card will be recognized as the system's VGA controller. 0 = VGA controller capacity enabled. 1 = The device will not be recognized as the system’s VGA controller.

N/A

CapacitorBits[5:4]

Bits[3:1]

0 0 1

NC

0 0 1

NC

0 0 0

680 nF

X X X

NC

Mapping to VRAM type please refer to page 6

@

RV20

8.45K_0402_1%

@

1

CV23

2K_0402_1%

2

0.01U_0402_16V7K

2013/05/15 2015/09/27

Board configuration related strapping (such as memory ID).

Together with PS_0[5] form the three-bit strap option to indicate the number of audio-capable display outputs. In a given ASIC there are as many endpoints as there are digital display outputs, though not all outputs are audio capable. 111 = No usable endpoints. 110 = One usable endpoint. 101 = Two usable endpoints. 100 = Three usable endpoints. 011 = Four usable endpoints. 010 = Five usable endpoints. 001 = Six usable endpoints. 000 = All endpoints are usable.

R_pu R_pd

8.45K 2K

8.45K

2K

NC

4.75K

X

12

@

RV21

8.45K_0402_1%

12

VGA@

@

RV28

RV27

D

4.75K_0402_1%

Compal Secret Data

Deciphered Date

@

RV22

VGA@

RV68

12

8.45K_0402_1%

12

2K_0402_1%

VGA@

RV23

VGA@

RV30

+1.8VGS

001

1

0

1

0

Base on VRAM ID

111

12

+3VGS

2

VGA@

12

VGA_SMB_CK2

VGA_SMB_DA2

Title

Size Document Numbe r Rev

Custom

Date: Sheet

VGA@

61

QV1A

DMN66D0LDW-7 2N_SOT363-6

4

DMN66D0LDW-7 2N_SOT363-6

Compal Electronics, Inc.

Main_MSIC

LA-A551P

E

VGA@QV1B

VGA@

3

EC_SMB_CK2 <27,6>

EC_SMB_DA2 <27,6>

13 40Monday, May 06, 2013

of

0.1

5

QV1B

A

MPLL_PVDD MarsCRB Design

1 1

2 2

220ohm 1 1

0.1u 1 1 1u 1 1

2.2u 1 1

SPLL_PVDD MarsCRB Design 120ohm 1 1

0.1u 1 1 1u 1 1

2.2u 1 1

SPLL_VDDC MarsCRB Design 120ohm 1 1

0.1u 1 1 1u 1 1

2.2u 1 1

+1.8VGS

LV7

1 2

BLM15BD121SN1D_0402

+1.8VGS

LV8

1 2

BLM15BD121SN1D_0402

+0.95VGS

LV9

1 2

BLM15BD121SN1D_0402

B

VGA@LV7

VGA@

VGA@LV8

VGA@

VGA@LV9

VGA@

+MPV18

(MPLL_PVDD:1.8V@130mA )

1

CV79

CV78

2

1U_0402_6.3V6K

0.1U_0402_16V7K

VGA@ CV79

VGA@

VGA@ CV78

VGA@

2.2U_0402_6.3V6M

+SPV18

SPLL_PVDD:1.8V@75mA )

(

1

CV81

CV82

2

1U_0402_6.3V6K

0.1U_0402_16V7K

VGA@ CV81

VGA@

VGA@ CV82

VGA@

2.2U_0402_6.3V6M

+SPLL_VDDC

(SPLL_VDDC:0.95V@100mA )

1

CV93

CV92

2

1U_0402_6.3V6K

0.1U_0402_16V7K

VGA@ CV92

VGA@

VGA@ CV93

VGA@

2.2U_0402_6.3V6M

C

UV1C

PART 9 0F 9

AV33

XTALIN

1

CV80

2

VGA@ CV80

VGA@

1

CV83

2

VGA@ CV83

VGA@

1

CV94

2

VGA@ CV94

VGA@

+MPV18

+SPV18

+SPLL_VDDC

AM10

AN10

AF30 AF31

AN9

H7 H8

MPLL_PVDD MPLL_PVDD

SPLL_PVDD

SPLL_VDDC

SPLL_PVSS

NC_XTAL_PVDD NC_XTAL_PVSS

PLLS/XTAL

SUN-PRO M2_FCBGA962VGA@

XTALOUT

XO_IN

XO_IN2

CLKTESTA CLKTESTB

AU34

AW34

AW35

AK10 AL10

D

XTALIN

CV24

15P_0402_50V8J

VGA@

XTALOUT

Debug Only, for clock observat ion A

s short as poss ible

VGA@

1 2

RV31 1M_0402_5%

VGA@

YV1

4

NC

OSC

1

2

1

XTALIN

OSC

27MHZ 10PF +-20PPM X3G027000DA1H

NC

E

3

XTALOUT

2

CV25

CV25 15P_0402_50V8J

15P_0402_50V8J

1

VGA@

+0.95VS to +0.95VGS

RV45

VGA@

1 2

RV48

220K_0402_5%

61

VGA@

2

PXS_PWREN#

VGA@

QV8A

2N7002DW-T/R7_SOT363-6

VGA@

470_0805_5%

B+

1 2 3

VGA@

QV8B

5

2N7002DW-T/R7_SOT363-6

4

B

+3VGS

VGA@

RV43

470_0805_5%

1 2 3

VGA@

QV9B

2N7002DW-T/R7_SOT363-6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2013/05/15 2015 /09/27

Compal Secret Data

Deciphered Date

QV9B

4

PXS_PWREN<37,8>

PXS_PWREN

D

100K_0402_5%

5

PXS_PWREN#

VGA@

RV44

VGA@

QV9A

A

+0.95VALW

VGA@

QV3

8

D

7

D

6

D

5

D

FDS6676AS_SO8

3 3

4 4

+0.95VGS

Vgs=10V,Id=14.5 A,Rds=6mohm

1

S

2

S

3

S

4

G

QV3_GATE

1

12

RV49

CV106

2

VGA@ CV106

VGA@

VGA@ RV49

VGA@

820K_0402_5%

0.1U_0402_25V6

+3VS to +3VGS

+3VALW

@

2

CV103

0.1U_0402_16V7K

VGA@

RV46

1 2

47K_0402_5%

1 2

61

2

2N7002DW-T/R7_SOT363-6

Date: Sheet

0.1U_0402_16V7K

1

2

CV104

1

VGA@ CV104

VGA@

0.01U_0402_25V7K

Title

Size Document Number Rev

Custom

+3VS

Vgs=-4.5V,Id=3A ,Rds<97mohm

S

G

2

D

QV4

1 3

VGA@

AO3413_SOT23

Compal Electronics, Inc.

BACO POWER

LA-A551P

E

+3VGS

0.1

of

14 40Monday, May 06, 2013

of

14 40Monday, May 06, 2013

of

14 40Monday, May 06, 2013

A

B

C

D

E

Only for Kabini

+1.8VALW to +1.8VGS +1.5V to +1.5VGS

1 1

+1.5V

CV96

1

@

1U_0402_6.3V6K

2

2 2

VIN 5V and 3.3V (VBIAS=5V),IMA X(per channel)= 6A,Rds=18mohm

1 2

3

4

5

6 7

VGA_PWRGD<37,8>

+1.8VALW

1

@ CV100

@

2

CV100

1U_0402_6.3V6K

+5VALW

VGA_PWRGD

VGA@

UV3

VIN1 VIN1

ON1

VBIAS

ON2

VIN2 VIN2

TPS22966DPUR_SON14_2X3

VOUT1 VOUT1

GND

VOUT2 VOUT2

GPAD

14 13

12

CT1

11

10

CT2

9 8

15

+1.5VGS_LS

CV95 180P_0402_50V8J

1 2

VGA@

CV99 330P_0402_50V7K

1 2

VGA@

+1.8VGS_LS

PJ12

1 2

PAD-OPEN 4x4m

PJ13

@

1 2

PAD-OPEN 4x4m

@

+1.8VGS

@ CV98

@

2

1

+1.5VGS

@ CV97

@

CV98

0.1U_0402_10V7K

2

CV97

0.1U_0402_10V7K

1

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2013/05/15 2015 /09/27

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

BACO POWER

LA-A551P

15 40Monday, May 06, 2013

E

0.1

of

A

B

C

D

E

VDDR1 MarsCRB Design

0.01u 5 0

0.1u 5 0

2.2u 5 5 10u 3 3

VDD_CT MarsCRB Design 120ohm 1 1

1 1

0.1u 1 1 1u 1 1 10u 1 1

VDDR3 Mars ch eck list Desig n 120ohm 1 1 1u 3 2 10u 1 0

0.1u 0 1

+1.8VGS +VDDC_CT

BLM15BD121SN1D_0402

2 2

3 3

+3VGS

BLM15BD121SN1D_0402

LV4

VGA@LV4

VGA@

1 2

LV5

VGA@LV5

VGA@

1 2

+1.5VGS

10U_0603_6.3V6M

1

CV34

CV33

2

10U_0603_6.3V6M

VGA@ CV34

10U_0603_6.3V6M

VGA@

VGA@ CV33

VGA@

CV51

10U_0603_6.3V6M

VGA@ CV51

10U_0603_6.3V6M

VGA@

+VDDR3

CV42

1U_0402_6.3V6K

VGA@ CV42

VGA@

(VDDR1:1.5V@1.5A)

1

CV36

CV35

2

10U_0603_6.3V6M

VGA@ CV35

10U_0603_6.3V6M

VGA@

VGA@ CV36

VGA@

2.2U_0402_6.3V6M

(VDD_CT:1.8V@13mA )

1

CV53

CV52

2

1U_0402_6.3V6K

0.1U_0402_16V7K

VGA@ CV52

VGA@

VGA@ CV53

VGA@

(VDDR3:3.3V@25mA)

1

CV54

CV55

2

1U_0402_6.3V6K

0.1U_0402_16V7K

VGA@ CV55

VGA@

VGA@ CV54

VGA@

+1.5VGS

1

CV38

CV40

CV39

CV37

2

VGA@ CV38

VGA@

VGA@ CV40

VGA@

VGA@ CV39

VGA@

VGA@ CV37

VGA@

2.2U_0402_6.3V6M

+VDDC_CT

+VDDR3

Route as differential pair

VCC_GPU_SENSE<37>

TV44TV44

VSS_GPU_SENSE<37>

AD11

AG10

AF26 AF27 AG26 AG27

AF23 AF24 AG23 AG24

AD12 AF11 AF12 AF13

AF15 AG11 AG13 AG15

AF28

AG28

AH29

AC7

AK8

G11 G14 G17 G20 G23 G26 G29

M11

AF7

AJ7

AL9

H10

J7

J9 K11 K13

K8 L12 L16 L21 L23 L26

L7

N11

P7 R11 U11

U7

Y11

Y7

UV1E

MEM I/O

VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1

LEVEL

TRANSLATION

VDD_CT VDD_CT VDD_CT VDD_CT

I/O

VDDR3 VDDR3 VDDR3 VDDR3

DVP

VDDR4 VDDR4 VDDR4 VDDR4

VOLTAGE

VOLTAGE SENESE

SENESE

FB_VDDC

FB_VDDCI

FB_GND

PART 5 0F 9

(PCIE_PVDD: 1.80V@100mA)

+1.8VGS

AA31

NC

AA32

NC

AA33

NC

AA34

NC

W30

NC

Y31

NC

V28

NC_BIF_VDDC

W29

NC_BIF_VDDC

AB37

PCIE_PVDD

G30

PCIE

PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC

BIF_VDDC

BACO

BIF_VDDC

VDDC

CORE

VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC

VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC

VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI

CORE I/O

ISOLATED

VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI

SUN-PRO M2_FCBGA962VGA@

VDDCI

G31 H29 H30 J29 J30 L28 M28 N28 R28 T28 U28

N27 T27

AA15 AA17 AA20 AA22 AA24 AA27 AB16 AB18 AB21 AB23 AB26 AB28 AC17 AC20 AC22 AC24 AC27 AD18 AD21 AD23 AD26 AF17 AF20 AF22 AG16 AG18

AH22 AH27 AH28 M26 N24 R18 R21 R23 R26 T17 T20 T22 T24 U16 U18 U21 U23 U26 V17 V20 V22 V24 V27 Y16 Y18 Y21 Y23 Y26 Y28

AA13 AB13 AC12 AC15 AD13 AD16 M15 M16 M18 M23 N13 N15 N17 N20 N22 R12 R13 R16 T12 T15 V15 Y13

+0.95VGS

+VGA_CORE

1

CV31

CV30

2

1U_0402_6.3V6K

VGA@ CV31

VGA@

10U_0603_6.3V6M

VGA@ CV30

VGA@

1

CV43

CV44

2

1U_0402_6.3V6K

VGA@ CV43

VGA@

VGA@ CV44

VGA@

(BIF_VDDC: 0.95V@1.4A)

1

CV68

CV67

2

@ CV68

@

@ CV67

@

1U_0402_6.3V6K

10U_0603_6.3V6M

Maximum Current on +1.8VGS:

1

"Sun": ~0.5 A

CV32

2

VGA@ CV32

VGA@

PCIE_VDDC:

0.95 V @ 1.88 A (PCIe Gen 2.0)

0.95 V @ 2.50 A (PCIe Gen 3.0)

1

CV46

CV41

CV45

2

1U_0402_6.3V6K

VGA@ CV46

VGA@

VGA@ CV41

VGA@

VGA@ CV45

VGA@

Maximum Current on +0.95VGS:

1

CV69

"Sun": ~4.0 A for PCIe GEN 3.0 designs (estimated)

2

@ CV69

@

1

CV47

2

VGA@ CV47

VGA@

+0.95VGS

+1.8VGS

+0.95VGS

1

CV48

CV50

CV49

2

1U_0402_6.3V6K

VGA@ CV48

VGA@

10U_0603_6.3V6M

VGA@ CV50

10U_0603_6.3V6M

VGA@

10U_0603_6.3V6M

VGA@ CV49

10U_0603_6.3V6M

VGA@

PCIE_PVDD Mar sCRB Design 1u 2 2 10u 1 1

PCIE_VDDC Mar sCRB Design 1u 7 7 10u 2 2

BIF_VDDC Mar s check list Design 1u 1 1 10u 1 1

+VGA_CORE

Need check all power current and decoupling capacitors a

4 4

A

fter got SUN databook and reference schematic.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

Compal Secret Data

2013/05/15 2015/09/27

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet

Compal Electronics, Inc.

Power

LA-A551P

E

16 40Monday, May 06, 2013

of

0.1

A

UV1H

PART 3 0F 9

GDDR5/DDR3

DQA0_0 DQA0_1 DQA0_2 DQA0_3 DQA0_4 DQA0_5 DQA0_6 DQA0_7 DQA0_8 DQA0_9 DQA0_10 DQA0_11 DQA0_12 DQA0_13 DQA0_14 DQA0_15 DQA0_16 DQA0_17 DQA0_18 DQA0_19 DQA0_20 DQA0_21 DQA0_22 DQA0_23 DQA0_24 DQA0_25 DQA0_26 DQA0_27 DQA0_28 DQA0_29 DQA0_30 DQA0_31 DQA1_0 DQA1_1 DQA1_2 DQA1_3 DQA1_4 DQA1_5 DQA1_6 DQA1_7 DQA1_8 DQA1_9 DQA1_10 DQA1_11 DQA1_12 DQA1_13 DQA1_14 DQA1_15 DQA1_16 DQA1_17 DQA1_18 DQA1_19 DQA1_20 DQA1_21 DQA1_22 DQA1_23 DQA1_24 DQA1_25 DQA1_26 DQA1_27 DQA1_28 DQA1_29 DQA1_30 DQA1_31

MVREFDA MVREFSA

NC NC NC

MEM_CALRP0

NC NC

VGA@

GDDR5/DDR3

MEMORY INTERFACE A

MAA0_0/MAA_0 MAA0_1/MAA_1 MAA0_2/MAA_2 MAA0_3/MAA_3 MAA0_4/MAA_4 MAA0_5/MAA_5 MAA0_6/MAA_6 MAA0_7/MAA_7 MAA1_0/MAA_8

MAA1_1/MAA_9 MAA1_2/MAA_10 MAA1_3/MAA_11 MAA1_4/MAA_12

MAA1_5/MAA_BA2 MAA1_6/MAA_BA0 MAA1_7/MAA_BA1

WCKA0_0/DQMA_0

WCKA0B_0/DQMA_1

WCKA0_1/DQMA_2

WCKA0B_1/DQMA_3

WCKA1_0/DQMA_4

WCKA1B_0/DQMA_5

WCKA1_1/DQMA_6

WCKA1B_1/DQMA_7

EDCA0_0/QSA_0 EDCA0_1/QSA_1 EDCA0_2/QSA_2 EDCA0_3/QSA_3 EDCA1_0/QSA_4 EDCA1_1/QSA_5 EDCA1_2/QSA_6 EDCA1_3/QSA_7

DDBIA0_0/QSA_0B DDBIA0_1/QSA_1B DDBIA0_2/QSA_2B DDBIA0_3/QSA_3B DDBIA1_0/QSA_4B DDBIA1_1/QSA_5B DDBIA1_2/QSA_6B DDBIA1_3/QSA_7B

ADBIA0/ODTA0

ADBIA1/ODTA1

CLKA0B

CLKA1B

RASA0B RASA1B

CASA0B CASA1B

CSA0B_0 CSA0B_1

CSA1B_0 CSA1B_1

CKEA0 CKEA1

WEA0B WEA1B

MAA0_8/MAA_13 MAA1_8/MAA_14 MAA0_9/MAA_15

MAA1_9/RSVD

SUN-PRO M2_FCBGA962

C37 C35

A35

E34 G32 D33

F32

E32 D31

F30 C30

A30

AG12

AH12

F28 C28

A28

E28 D27

F26 C26

A26

F24 C24

A24

E24 C22

A22

F22 D21

A20

F20 D19

E18 C18

A18

F18 D17

A16

F16 D15

E14

F14 D13

F12

A12 D11

F10

A10 C10 G13 H13

J13 H11 G10

G8

K9

K10

G9

A8

C8

E8 A6

C6

E6 A5

L18

L20

L27 N12

M27

M12

1 1

2 2

1 2

RV34 120_0402_1%VGA@RV34 120_0402_1%VGA@

3 3

Memory clock 900MHz

GPU Type

SUN PRO-M2

SUN PRO-M3

SUN PRO-M4

Memory Bus Width

64bit

VRAM Vendor

Samsung

Micron

Samsung

Micron

Samsung

Compal P/N

SA000068U20

SA00005XB00

SA00005SH00

SA000068R20

B

G24 J23 H24 J24 H26 J26 H21 G21 H19 H20 L13 G16 J16 H16 J17 H17

A32 C32 D23 E22 C14 A14 E10 D9

C34 D29 D25 E20 E16 E12 J10 D7

A34 E30 E26 C20 C16 C12 J11 F8

J21 G19

H27

CLKA0

G27

J14

CLKA1

H14

K23 K19

K20 K17

K24 K27

M13 K16

K21 J20

K26 L15

H23 J19 M21 M20

Manufacturer P/N

K4W2G1646E-BC1A

MT41K128M16JT-107G:K

K4W2G1646E-BC11

MT41K256M16HA-107G:ESA000065D30

K4W4G1646B-HC11

Close to pin Y12 and AA12

RV72

40.2_0402_1%

VGA@

RV73

100_0402_1%

VGA@

ZZZ2

X76xxxxxLx1

S1G

S1G@

ZZZ3

H1G@

X76xxxxxLx2

X76 P/N

C

MDB[0..63]

+1.5VGS

H1G

MDB[0..63]<19>

12

15mil

+MVREFDB_SB

12

1

CV159

CV159 1U_0402_6.3V6K

1U_0402_6.3V6K

VGA@

2

ZZZ5

S2G

S2G@

ZZZ5

H2G

H2G@

X76xxxxxLx4

ZZZ4

X76xxxxxLx3

Size per part Configuration Total Memory Size/Qty

2Gbit 128M*16 1GB/4pcs

2Gbit

4Gbit

128M*16

128M*16 1GB/4pcs

128M*16

1GB/4pcs

2GB/4pcs

+MVREFDB_SB

MDB0 MDB1 MDB2 MDB3 MDB4 MDB5 MDB6 MDB7 MDB8 MDB9 MDB10 MDB11 MDB12 MDB13 MDB14 MDB15 MDB16 MDB17 MDB18 MDB19 MDB20 MDB21 MDB22 MDB23 MDB24 MDB25 MDB26 MDB27 MDB28 MDB29 MDB30 MDB31 MDB32 MDB33 MDB34 MDB35 MDB36 MDB37 MDB38 MDB39 MDB40 MDB41 MDB42 MDB43 MDB44 MDB45 MDB46 MDB47 MDB48 MDB49 MDB50 MDB51 MDB52 MDB53 MDB54 MDB55 MDB56 MDB57 MDB58 MDB59 MDB60 MDB61 MDB62 MDB63

UV1I

C5

DQB0_0

C3

DQB0_1

E3

DQB0_2

E1

DQB0_3

F1

DQB0_4

F3

DQB0_5

F5

DQB0_6

G4

DQB0_7

H5

DQB0_8

H6

DQB0_9

J4

DQB0_10

K6

DQB0_11

K5

DQB0_12

L4

DQB0_13

M6

DQB0_14

M1

DQB0_15

M3

DQB0_16

M5

DQB0_17

N4

DQB0_18

P6

DQB0_19

P5

DQB0_20

R4

DQB0_21

T6

DQB0_22

T1

DQB0_23

U4

DQB0_24

V6

DQB0_25

V1

DQB0_26

V3

DQB0_27

Y6

DQB0_28

Y1

DQB0_29

Y3

DQB0_30

Y5

DQB0_31

AA4

DQB1_0

AB6

DQB1_1

AB1

DQB1_2

AB3

DQB1_3

AD6

DQB1_4

AD1

DQB1_5

AD3

DQB1_6

AD5

DQB1_7

AF1

DQB1_8

AF3

DQB1_9

AF6

DQB1_10

AG4

DQB1_11

AH5

DQB1_12

AH6

DQB1_13

AJ4

DQB1_14

AK3

DQB1_15

AF8

DQB1_16

AF9

DQB1_17

AG8

DQB1_18

AG7

DQB1_19

AK9

DQB1_20

AL7

DQB1_21

AM8

DQB1_22

AM7

DQB1_23

AK1

DQB1_24

AL4

DQB1_25

AM6

DQB1_26

AM1

DQB1_27

AN4

DQB1_28

AP3

DQB1_29

AP1

DQB1_30

AP5

DQB1_31

Y12

MVREFDB

AA12

MVREFSB

R_pu & R_pd resistor: 04

02 1% resistors are required.

PS_3[ 1]PS_3[ 2 ]PS_3[ 3 ]

0 0

0

0 1 0

1 1 0

D

PART 4 0F 9

GDDR5/DDR3

MEMORY INTERFACE B

0

1

11 1

MAB0_0/MAB_0 MAB0_1/MAB_1 MAB0_2/MAB_2 MAB0_3/MAB_3 MAB0_4/MAB_4 MAB0_5/MAB_5 MAB0_6/MAB_6 MAB0_7/MAB_7 MAB1_0/MAB_8

MAB1_1/MAB_9 MAB1_2/MAB_10 MAB1_3/MAB_11 MAB1_4/MAB_12

MAB1_5/BA2 MAB1_6/BA0 MAB1_7/BA1

WCKB0_0/DQMB_0

WCKB0B_0/DQMB_1

WCKB0_1/DQMB_2

WCKB0B_1/DQMB_3

WCKB1_0/DQMB_4

WCKB1B_0/DQMB_5

WCKB1_1/DQMB_6

WCKB1B_1/DQMB_7

EDCB0_0/QSB_0 EDCB0_1/QSB_1 EDCB0_2/QSB_2 EDCB0_3/QSB_3 EDCB1_0/QSB_4 EDCB1_1/QSB_5 EDCB1_2/QSB_6 EDCB1_3/QSB_7

DDBIB0_0/QSB_0B DDBIB0_1/QSB_1B DDBIB0_2/QSB_2B DDBIB0_3/QSB_3B DDBIB1_0/QSB_4B DDBIB1_1/QSB_5B DDBIB1_2/QSB_6B DDBIB1_3/QSB_7B

ADBIB0/ODTB0 ADBIB1/ODTB1

MAB0_8/MAB_13 MAB1_8/MAB_14 MAB0_9/MAB_15

MAB1_9/RSVD

DRAM_RST

SUN-PRO M2_FCBGA962VGA@

R_pu R_pd

RV20 RV27

NC 4.75K

RV20

8.45K

RV20 RV27

4.53K

RV20 RV27

3.4K

RV20 RV27

4.75K

CLKB0

CLKB0B

CLKB1

CLKB1B

RASB0B RASB1B

CASB0B CASB1B

CSB0B_0 CSB0B_1

CSB1B_0 CSB1B_1

CKEB0 CKEB1

WEB0B WEB1B

MAB[0..15]

B_BA2 <19> B_BA0 <19> B_BA1 <19>

ODTB0 <19> ODTB1 <19>

CLKB0 <19> CLKB0# <19>

CLKB1 <19> CLKB1# <19>

RASB0# <19> RASB1# <19>

CASB0# <19> CASB1# <19>

CSB0#_0 <19>

CSB1#_0 <19>

CKEB0 <19> CKEB1 <19>

WEB0# <19> WEB1# <19>

RV36

1 2

10_0402_1%

120P_0402_50V9

1 2

DQMB#[0..7]

QSB[0..7]

QSB#[0..7]

VGA@RV36

VGA@

CV158

12

P8

MAB0

T9

MAB1

P9

MAB2

N7

MAB3

N8

MAB4

N9

MAB5

U9

MAB6

U8

MAB7

Y9

MAB8

W9

MAB9

AC8

MAB10

AC9

MAB11

AA7

MAB12

AA8

B_BA2

Y8

B_BA0

AA9

B_BA1

H3

DQMB#0

H1

DQMB#1

T3

DQMB#2

T5

DQMB#3

AE4

DQMB#4

AF5

DQMB#5

AK6

DQMB#6

AK5

DQMB#7

F6

QSB0

K3

QSB1

P3

QSB2

V5

QSB3

AB5

QSB4

AH1

QSB5

AJ9

QSB6

AM5

QSB7

G7

QSB#0

K1

QSB#1

P1

QSB#2

W4

QSB#3

AC4

QSB#4

AH3

QSB#5

AJ8

QSB#6

AM3

QSB#7

T7

ODTB0

W7

ODTB1

L9

CLKB0

L8

CLKB0#

AD8

CLKB1

AD7

CLKB1#

T10

RASB0#

Y10

RASB1#

W10

CASB0#

AA10

CASB1#

P10

CSB0#_0

L10

AD10

CSB1#_0

AC10

U10

CKEB0

AA11

CKEB1

N10

WEB0#

AB11

WEB1#

T8

MAB13

W8

MAB14

U12

MAB15

V12

AH11

DRAM_RST#_R

VGA@

RV71

4.99K_0402_1%

Place all these components close to GPU (Within 25mm) and keep all component close to each other

RV27

2K

10K

NC

RV70

1 2

51.1_0402_1%

E

MAB[0..15] <19>

DQMB#[0..7] <19>

QSB[0..7] <19>

QSB#[0..7] <19>

VGA@RV70

VGA@

DRAM_RST# <19>

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

2013/05/15 2015/09/27

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet

Compal Electronics, Inc.

MEM Interface

LA-A551P

E

17 40Monday, May 06, 2013

of

0.1

A

UV1G

PART 6 0F 9

AB39

GND

E39

GND

F34

GND

F39

GND

G33

GND

G34

GND

H31

GND

H34

GND

H39

GND

J31

W31 W34

M34 M39 N31 N34

R34

U31 U34

M17 M22 M24

GND

J34

GND

K31

GND

K34

GND

K39

GND

L31

GND

L34

GND GND GND GND GND

P31

GND

P34

GND

P39

GND GND

T31

GND

T34

GND

T39

GND GND GND

V34

GND

V39

GND GND GND

Y34

GND

Y39

GND

F15

GND

F17

GND

F19

GND

F21

GND

F23

GND

F25

GND

F27

GND

F29

GND

F31

GND

F33

GND

F7

GND

F9

GND

G2

GND

G6

GND

H9

GND

J2

GND

J27

GND

J6

GND

J8

GND

K14

GND

K7

GND

L11

GND

L17

GND

L2

GND

L22

GND

L24

GND

L6

GND GND GND GND

N16

GND

N18

GND

N2

GND

N21

GND

N23

GND

N26

GND

N6

GND

R15

GND

R17

GND

R2

GND

R20

GND

R22

GND

R24

GND

R27

GND

R6

GND

T11

GND

T13

GND

T16

GND

T18

GND

T21

GND

T23

GND

T26

GND

U15

GND

U17

GND

U2

GND

U20

GND

U22

GND

U24

GND

U27

GND

U6

GND

V11

GND

V16

GND

V18

GND

V21

GND

V23

GND

V26

GND

W2

GND

W6

GND

Y15

GND

Y17

GND

Y20

GND

Y22

GND

Y24

GND

Y27

GND

VSS_MECH VSS_MECH VSS_MECH

SUN-PRO M2_FCBGA962VGA@

1 1

2 2

3 3

4 4

A

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

GND

NC

A3 A37 AA16 AA18 AA2 AA21 AA23 AA26 AA28 AA6 AB12 AB15 AB17 AB20 AB22 AB24 AB27 AC11 AC13 AC16 AC18 AC2 AC21 AC23 AC26 AC28 AC6 AD15 AD17 AD20 AD22 AD24 AD27 AD9 AE2 AE6 AF10 AF16 AF18 AF21 AG17 AG2 AG20

AG6 AG9 AH21 AJ10 AJ11 AJ2 AJ28 AJ6 AK11 AK31 AK7 AL11 AL14 AL17 AL2 AL20

AL23 AL26 AL32 AL6 AL8 AM11 AM31 AM9 AN11 AN2 AN30 AN6 AN8 AP11 AP7 AP9 AR5 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B7 B9 C1 C39 E35 E5 F11 F13

AG22

A39 AW1 AW39

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

+1.8VGS

(DP_VDDR: 1.8V@ 20mA)

C

D

UV1F

AN24

NC

AP24

NC

AP25

NC

AP26

NC

AU28

NC

AV29

NC

AP20

NC

AP21

NC

AP22

NC

AP23

NC

AU18

NC

AV19

NC

AH34

DP_VDDR

AJ34

DP_VDDR

AF34

DP_VDDR

AG34

DP_VDDR

AM37

DP_VDDR

AL38

DP_VDDR

AM32

DP_VDDR

AW28

NC

AW18

NC

AM39

DP_CALR

2013/05/15 2015 /09/27

PART 8 0F 9

DP_VDDR DP_VDDC

DP GND

CALIBRATION

SUN-PRO M2_FCBGA962VGA@

Compal Secret Data

Deciphered Date

DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC

DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR

D

NC NC NC NC

AP31 AP32 AN33 AP33 AL33 AM33 AK33 AK34

(DP_VDDC: 0.95V @20mA)

AN31

AP13 AT13 AP14 AP15

AN27 AP27 AP28 AW24 AW26 AN29 AP29 AP30 AW30 AW32 AN17 AP16 AP17 AW14 AW16 AN19 AP18 AP19 AW20 AW22 AN34 AP39 AR39 AU37 AF39 AH39 AK39 AL34 AV27 AR28 AV17 AR18 AN38 AM35 AN32

E

+0.95VGS

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

PWR_GND

LA-A551P

18 40Monday, May 06, 2013

E

of

0.1

5

4

3

2

1

CHANNEL B: 512MB/1024MB DDR3

UV5

+VREFC_A1_B +VREFC_A2_B +VREFC_A3_B +VREFC_A4_B

D D

MDB[0..63]<17>

MAB[0..15]<17>

DQMB#[0..7]<17>

QSB[0..7]<17>

QSB#[0..7]<17>

C C

CLKB0

RV78 40.2_0402_1%

CLKB0#

RV79 40.2_0402_1%

1 2

CLKB1

RV84 40.2_0402_1%

1 2

CLKB1#

RV85 40.2_0402_1%

VGA@

1 2

VGA@

1 2

VGA@

MDB[0..63]

MAB[0..15]

DQMB#[0..7]

QSB[0..7]

QSB#[0..7]

12

VGA@

CV160

0.01U_0402_16V7K

VGA@

CV161

0.01U_0402_16V7K

CLKB0<17> CLKB0#<17> CKEB0<17>

ODTB0<17> CSB0#_0<17> RASB0#<17> CASB0#<17> WEB0#<17>

DRAM_RST#<17>

243_0402_1%

B_BA0<17> B_BA1<17> B_BA2<17>

RV80

VGA@

M8

VREFCA

H1

VREFDQ

N3

MAB0 MAB0 MAB0 MAB0

A0

P7

MAB1 MAB1 MAB1 MAB1

A1

P3

MAB2 MAB2 MAB2 MAB2

A2

N2

MAB3 MAB3 MAB3 MAB3

A3

P8

MAB4 MAB4 MAB4 MAB4

A4

P2

MAB5 MAB5 MAB5 MAB5

A5

R8

MAB6 MAB6 MAB6 MAB6

A6

R2

MAB7 MAB7 MAB7 MAB7

A7

T8

MAB8 MAB8 MAB8 MAB8

A8

R3

MAB9 MAB9 MAB9 MAB9MDB14

A9

L7

MAB10 MAB10 MAB10 MAB10

A10/AP

R7

MAB11 MAB11 MAB11 MAB11

A11

N7

MAB12 MAB12 MAB12 MAB12

A12

T3

MAB13 MAB13 MAB13 MAB13

A13

T7

MAB14 MAB14 MAB14 MAB14

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

QSB3 QSB2 QSB4 QSB1 QSB0

DQMB#3 DQMB#2 DQMB#4 DQMB#1 DQMB#0

QSB#3 QSB#2 QSB#4 QSB#1 QSB#0

12

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646G-BC11_FBGA96

E3

MDB24

DQL0

F7

MDB26

DQL1

F2

MDB30

DQL2

F8

MDB31

DQL3

H3

MDB25

DQL4

H8

MDB27

DQL5

G2

MDB28

DQL6

H7

MDB29

DQL7

D7

MDB15

DQU0

C3

MDB10

DQU1

C8

DQU2

C2

MDB11

DQU3

A7

MDB13

DQU4

A2

MDB9 MDB5

DQU5

B8

MDB12

DQU6

A3

MDB8

DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VDD VDD VDD VDD VDD VDD VDD VDD VDD

+1.5VGS

B2 D9 G7 K2 K8 N1 N9 R1 R9

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

@

RV81

243_0402_1%

VGA@

UV6

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

B_BA0 B_BA0 B_BA0 B_BA1 B_BA1 B_BA1 B_BA2 B_BA2 B_BA2

CLKB0 CLKB0# CKEB0 CKEB1

ODTB0 ODTB1 CSB0#_0 CSB1#_0 RASB0# RASB1# CASB0# CASB1# WEB0# WEB1#

DRAM_RST# DRAM_RST# DRAM_RST#

12

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646G-BC11_FBGA96

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3

MDB17

F7

MDB19

F2

MDB16

F8

MDB22

H3

MDB20

H8

MDB21

G2

MDB18

H7

MDB23

D7

MDB1

C3

MDB7

C8

MDB2

C2 A7

MDB3

A2 B8

MDB0

A3

MDB6

+1.5VGS

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

@

CLKB1<17> CLKB1#<17> CKEB1<17>

ODTB1<17> CSB1#_0<17> RASB1#<17> CASB1#<17> WEB1#<17>

RV82

243_0402_1%

VGA@

QSB7

DQMB#7

QSB#7

12

UV7

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646G-BC11_FBGA96

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

UV8

CLKB1 CLKB1#

QSB6 QSB5

DQMB#6 DQMB#5

QSB#6 QSB#5

12

M8 H1

N3

N2

R8 R2

R3

R7 N7

M7

MAB15MAB15MAB15MAB15

M2 N8 M3

C7

D3

G3

UV8

VREFCA VREFDQ

A0

P7

A1

P3

A2 A3

P8

A4

P2

A5 A6 A7

T8

A8 A9

L7

A10/AP A11 A12

T3

A13

T7

A14 A15/BA3

BA0 BA1 BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL DQSU

E7

DML DMU

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646G-BC11_FBGA96

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3

MDB49

F7

MDB53

F2

MDB51

F8

MDB55

H3

MDB48

H8

MDB54

G2

MDB50

H7

MDB52

D7

MDB47

C3

MDB43

C8

MDB45

C2

MDB42

A7

MDB44MDB57

A2

MDB40

B8

MDB46

A3

MDB41

+1.5VGS

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

@

E3

MDB33

F7

MDB37

F2

MDB35

F8

MDB39

H3

MDB32

H8

MDB36

G2

MDB34

H7

MDB38

D7

MDB58

C3

MDB60

C8

MDB56

C2

MDB62MDB4

A7 A2

MDB63

B8

MDB59

A3

MDB61

+1.5VGS

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

@

RV83

243_0402_1%

VGA@

Supported Memory Configurations: Up to 4 Gbit/part for DDR3.

B B

+1.5VGS +1.5VGS

0.1U_0402_16V7K

VGA@

1

0.1U_0402_16V7K

VGA@

1

0.1U_0402_16V7K

VGA@

1

CV170

CV171

2

0.1U_0402_16V7K

VGA@

CV169

2

1

CV168

2

1

CV166

CV167

2

A A

0.1U_0402_16V7K

VGA@

0.1U_0402_16V7K

VGA@

2

0.1U_0402_16V7K

VGA@

1

c

CV173

CV172

2

0.1U_0402_16V7K

VGA@

close to UV7 UV 8

5

+1.5VGS +1.5VGS +1.5VGS +1.5VGS

12

VGA@

RV86

4.99K_0402_1%

15mil 15mil 15mil 15mil

+VREFC_A1_B +VREFC_A3_B +VREFC_A4_B

12

VGA@

RV90

VGA@

CV162

lose to UV9 UV1 0

4

1

2

0.1U_0402_16V7K

CV179 22U_0603_6.3V6M

1

2

VGA@

RV87

4.99K_0402_1%

VGA@

RV91

4.99K_0402_1%

12

+VREFC_A2_B

12

1

CV163

2

VGA@

0.1U_0402_16V7K

close to UV7 UV 8

+1.5VGS +1.5VGS

1U_0402_6.3V6K

VGA@

1

CV185

CV184

2

1U_0402_6.3V6K

VGA@

1

CV183

2

1U_0402_6.3V6K

VGA@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

CV187

CV186

2

1U_0402_6.3V6K

VGA@

2013/05/15 2015/09/27

12

VGA@

RV88

4.99K_0402_1%

12

VGA@

RV92

4.99K_0402_1%

1

CV188

2

Compal Secret Data

Deciphered Date

VGA@

2

1

CV164

2

0.1U_0402_16V7K

close to UV9 UV 10

1

CV193

CV194

2

1U_0402_6.3V6K

VGA@

1U_0402_6.3V6K

VGA@

1U_0402_6.3V6K

VGA@

12

VGA@

RV89

4.99K_0402_1%

12

VGA@

RV93

4.99K_0402_1%

1

CV195

CV196

2

1U_0402_6.3V6K

VGA@

Title

Size Document Number Rev

C 0.1

Date: Sheet of

1

CV197

CV198

2

1U_0402_6.3V6K

VGA@

Compal Electronics, Inc.

1

CV165

2

VGA@

0.1U_0402_16V7K

VRAM Channel B

LA-A551P

1

19 40Monday, May 06, 2013

5

4

3

2

1

EDP_LCD_TXOUT0+_R<6>

EDP_LCD_TXOUT0-_R<6>

EDP_LCD_TXOUT1+_R<6>

EDP_LCD_TXOUT1-_R<6>

JLVDS

Conn@

GND GND GND GND GND

EDP_LCD_TXOUT2+_R<6>

EDP_LCD_TXOUT2-_R<6>

LCD_TXCLK+<6>

LCD_TXCLK-<6>

EDP_LVDS_CLK<6>

EDP_LVDS_DATA<6>

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31 32 33 34 35

+5VS_LVDS_TOUCH USB20_N4_R USB20_P4_R

BKOFF# INT_MIC_DATA INT_MIC_CLK

USB20_P3_R USB20_N3_R +3VS_LVDS_CAM +LCD_VDD

+3VS EDP_LVDS_CLK EDP_LVDS_DATA EDP_LCD_TXOUT0-_R EDP_LCD_TXOUT0+_R EDP_LCD_TXOUT1-_R EDP_LCD_TXOUT1+_R EDP_LCD_TXOUT2-_R EDP_LCD_TXOUT2+_R

LCD_TXCLKLCD_TXCLK+

LED_PWM BKOFF#_R

D D

C C

B B

STARC_111H30-000000-G4-R

EDP_LCD_TXOUT0+_R

EDP_LCD_TXOUT0-_R

EDP_LCD_TXOUT1+_R

EDP_LCD_TXOUT1-_R

EDP_LCD_TXOUT2+_R

EDP_LCD_TXOUT2-_R

LCD_TXCLK+

LCD_TXCLK-

EDP_LVDS_CLK

EDP_LVDS_DATA

@

1 2

R389 0_0603_5%

+LCD_VDD

+LCD_INV

pin1-4 Touch function for panel p

in5-10 For Webcam with single or dual MIC

If it's EPD, they're become LCD_TXOUT2+_R = EDP_TX0+ LCD_TXOUT2-_R = EDP_TX0LCD_TXOUT1+_R = EDP_TX1+ LCD_TXOUT1-_R = EDP_TX1LVDS_CLK = EDP_AUXP LVDS_DATA = EDP_AUXN

1 2

@

R390 0_0603_5%

Irush=1.5A

EDP_LVDS_HPD <6>

Irush=1.5A

60mils

INT_MIC_DATA <26> INT_MIC_CLK <26>

60mils

+5VS

+3VS

20mils

pin11-30 For LVDS or EDP panel

LCD_VDD

Need check eDP&LVDS both 3V power rail.

L

CD Control

INT_MIC_CLK

INT_MIC_DATA

+3VS

W=60mils

12

C17

C17 1500P_0402_50V7K

1500P_0402_50V7K

D29

4

5

Vbus

6

SC300001400

.5A

1

+LCD_VDD_SS

@E

SD@

3

GND

1

close to LVDS conn.

U16

5

VIN

4

SS

APL3512ABI-TRG_SOT23-5

LCD_ENVDD<6>

3

USB20_N3_R

2

1

USB20_P3_R

Reserve for power consumption Remove on PVT phase

1

GND

EN

+LCD_VDD_OUT

2

3

1 2

R112

R112 100K_0402_5%

100K_0402_5%

VOUT

1 2

R106 0_0805_5%R106 0_0805_5%

+LCD_INV

1.5A

+LCD_VDD

W=60mils

I rush=1.5A

LCD_INV

L2

FBMA-L11-201209-221LMA30T_0805

12

B+

Carmera & Touch Screen

eserve for eDP panel potential issue

D6

LCD_INT_PWM<6>

CAM_EMI@

USB20_P3<7>

USB20_N3<7>

3

2

WCM-2012-900T_0805

Reserve for EMI request

A A

USB20_N4<7>

USB20_P4<7>

TOUCH_EMI@

3

2

WCM-2012-900T_0805

Reserve for EMI request

5

L3

3

2

@TOUCH_EMI@

R104 0_0402_5%

3

2

@TOUCH_EMI@

R105 0_0402_5%

1 2

4

1

L4

4

1

4

USB20_P3_R

1

USB20_N3_R

4

USB20_N4_R

1

USB20_P4_R

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D6

2013/05/15 2015/09/27

3

12

RB751V40_SC76-2

12

R131

R131 47K_0402_5%

47K_0402_5%

Compal Secret Data

Deciphered Date

LED_PWM

BKOFF#_R

2

R

1 2

EDP@

R103 0_0402_5%

1 2

D15 RB751V40_SC76-2

LVDS@

12

R113

R113 10K_0402_5%

10K_0402_5%

Title

Size Document Number Rev

Date: Sheet

+3VS

5

EDP@

U17

1

P

IN1

4

O

2

BKOFF#

IN2

G

3

SN74AHC1G08DCKR_SC70-5

1 2

R147 0_0402_5%

LVDS@

Compal Electronics, Inc.

LVDS/EDP W/ CAMERA

LA-A551P

1

LCD_ENBKL <27,6>

BKOFF# <27>

of

20 40Monday, May 06, 2013

of

20 40Monday, May 06, 2013

of

20 40Monday, May 06, 2013

0.1

5

4

3

2

1

RPY2

Issued Date

1 8 2 7 3 6 4 5

4.7K_8P4R_5%

2

3 1

SGD

BSH111_SOT23-3

+3VS

+HDMI_5V_OUT

D D

APU_HDMI_CLK<6>

APU_HDMI_DATA<6>

C C

LY1

EMI@LY1

1 2

APU_HDMI_CLK-<6>

APU_HDMI_CLK+<6>

APU_HDMI_TX0-<6>

APU_HDMI_TX0+<6>

B B

APU_HDMI_TX1-<6>

APU_HDMI_TX1+<6>

APU_HDMI_TX2-<6>

APU_HDMI_TX2+<6>

HDMI45@

ZZZ

HDMI Royalty

A A

ZZZ

RO0000003HM

HDMI W/Logo + HDCP

HDMI W/O Logo: RO0000001HM HDMI W/Logo: RO0000002HM HDMI W/Logo + HDCP: RO0000003HM

CY2 0.1U_0402_16V7KCY2 0.1U_0402_16V7K

1 2

CY1 0.1U_0402_16V7KCY1 0.1U_0402_16V7K

1 2

CY5 0.1U_0402_16V7KCY5 0.1U_0402_16V7K

1 2

CY3 0.1U_0402_16V7KCY3 0.1U_0402_16V7K

1 2

CY7 0.1U_0402_16V7KCY7 0.1U_0402_16V7K

1 2

CY6 0.1U_0402_16V7KCY6 0.1U_0402_16V7K

1 2

CY9 0.1U_0402_16V7KCY9 0.1U_0402_16V7K

1 2

CY8 0.1U_0402_16V7KCY8 0.1U_0402_16V7K

HDMI_TXC-

HDMI_TXC+

HDMI_TXD0-

HDMI_TXD0+

HDMI_TXD1-

HDMI_TXD1+

HDMI_TXD2-

HDMI_TXD2+

1

4

KINGCORE WCM-2012HS-900T

1

4

KINGCORE WCM-2012HS-900T

1

4

KINGCORE WCM-2012HS-900T

1

4

KINGCORE WCM-2012HS-900T

EMI@

EMI@LY2

EMI@

EMI@LY3

EMI@

EMI@LY4

EMI@

2

3

2

3

2

3

2

3

1

4

LY2

1

4

LY3

1

4

LY4

1

4

please manually load this virtual material to 45@ BOM

5

4

APU_HDMI_CLK HDMI_SCLK

APU_HDMI_DATA HDMI_SDATA

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

APU_HDMI_CLK APU_HDMI_DATA

HDMI_SCLK HDMI_SDATA

+3VS

2

3 1

SGD

QY1

BSH111_SOT23-3

QY2

Main: SCA00000U10 2nd: SCA00001L00

Close to JHDMI

HDMI_R_CK+ HDMI_R_CKHDMI_R_D0+

HDMI_R_D0-

HDMI_R_D2+

HDMI_R_D2HDMI_R_D1+ HDMI_R_D1-

Compal Secret Data

2013/05/15 2015/09/27

3

Compal Secret Data

Deciphered Date

+HDMI_5V_OUT

HDMI_SDATA HDMI_SCLK

RPY3

1 8 2 7 3 6 4 5

499_8P4R_1%

RPY4

1 8 2 7 3 6 4 5

499_8P4R_1%

+5VS

RY1

1

5

UY1

P

4

OE#

A2Y

G

74AHCT1G125GW_SOT353-5

3

RY1

1 2

1K_0402_5%

HDMI_HPD

+3VS

12

100K_0402_5%

RY3

2.2K_0402_5%

HDMI_HPD

RY2

HDMI_HPD_CHDMI_HPD_U

1 2

2

CY4

0.1U_0402_16V4Z

1

HDMI_HPD <6>

OE# A Y

L

L L

L

H H

H

X Z

HDMI POWER CIRCUIT

VIN = 5V, IOUT = 0.5A , RDS(ON) TYP=95m ; MAX=115m Current Limit: TYP=0.8A ; MAX=1A

0.1U_0402_10V7K

13

D

QY3

2

G

S

2

+HDMI_5V_OUT

1

CY18

2

DY30

@ESD@DY30

@ESD@

2

3

YSLC05CH_SOT23-3

2N7002KW_SOT323-3

UY2

1

OUT

2

GND

3

FLG

AP2151DWG-7_SOT25-5

SA00006H000

1

+HDMI_5V_OUT

Title

Size Document Number Rev

Date: Sheet

5

IN

4

EN

HDMI Connector

JHDMI

HDMI_HPD_C

HDMI_R_CK-

HDMI_R_CK+

HDMI_R_D0-

HDMI_R_D0+

HDMI_R_D1-

HDMI_R_D1+

HDMI_R_D2-

HDMI_R_D2+

Compal Electronics, Inc.

HDMI W/O CEC

LA-A551P

19

HP_DET

18

+5V

17

DDC/CEC_ GND

16

SDA

15

SCL

14

Utility

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

ACON_HMR2J-AK120C

1

+5VS

GND GND GND GND

21 40Monday, May 06, 2013

Conn@JHDMI

Conn@

20 21 22 23

0.1

of

A

B

C

D

E

UL1

LAN_MDI0+ LAN_MDI1+ LAN_MDI0-

+LAN_VDD10> 40 mil

+LAN_VDD10

+3V_LAN > 40 mi l

1 1

2 2

LAN_MDI1-

+3V_LAN

CLK_LAN<7> CLK_LAN#<7> APU_PCIE_WAKE# <8 >

LANCLK_REQ# LAN_X1 LAN_X2

T101 PADTP@T101 PADTP@ T102 PADTP@T102 PADTP@

1 2

1

MDIP0

4

MDIP1

2

MDIN0

5

MDIN1

8

AVDD10

30

AVDD10

32

AVDD33

23

DVDD33

15

REFCLK_P

16

REFCLK_N

12

CLKREQB

28

CKXTAL1

29

CKXTAL2

27

LED0

25

LED1

31

RSET

33

RL12.49K_0402_1% RL12.49K_0402_1 %

GND

RTL8106E-CG_QFN32_4X4

8106E@

LAN_MDI0+

+3V_LAN

LAN_MDI0- LA N_MDI1-

6

5

4

17

HSOP

18

HSON

13

HSIP

14

HSIN

19

PERSTB

20

ISOLATEB

21

LANWAKEB

26

GPO

3

NC

6

NC

7

NC

9

NC

10

NC

11

NC

22

NC

24

NC

DL2

ESD@DL2

ESD@

I/O4

I/O2

VDD

GND

I/O3

AZC099-04S.R7G_SOT23-6

I/O1

PCIE_LANTX_C_ARX_P1 PCIE_LANTX_C_ARX_N1

ISOLATE#

3

LAN_MDI1+

2

1

T103PAD TP@T103PAD TP@

CL18 0.1U_0402_10V7KCL18 0.1U_0402_10V7K

1 2 1 2

CL21 0.1U_0402_10V7KCL21 0.1U_ 0402_10V7K

1

CL15

0.1U_0402_25V6

2

PCIE_LANTX_ARX_P1 <5>

PCIE_LANTX_ARX_N1 <5>

PCIE_ATX_C_LANRX_P1 <5> PCIE_ATX_C_LANRX_N1 <5>

APU_PCIE_RST# <12,23,8>

main: SP050007T00 2nd: SP050007K00 3nd: SP050006H00

UL3

1

TD+

LAN_MDI0- RJ45_MIDI0-

LAN_MDI1+ LAN_MDI1-

2

TD-

3

CT

4

NC

5

NC

6

CT

7

RD+ RD-8RX-

10/100M transformer_NS681612A

8106E@

SP050007T00UL3

SP050007T00

TX+

TX-

CT NC NC CT

RX+

16 15 14 13 12 11 10 9

RJ45_MIDI0+LAN_MDI0+

RJ45_MIDI1+ RJ45_MIDI1-

+LAN_VDD10

CL2,CL4 close to pin 8,30 respectively

L6 close to pin 30

C

1 2

CL2 0.1U_0402_10V7KCL2 0.1U_0402_10V7K

1 2

CL4 0.1U_0402_10V7KCL4 0.1U_0402_10V7K

1 2

CL6 1U_0402_6.3V6KCL6 1U_0402_6.3V6K

PJ77

@PJ77

@

RL5

1 2

RL6

1 2

2

112

JUMP_43X39

75_0603_1%

RJ45_GND LANGND

+3VALW_APU +3V_LAN

Keep de-coupling capacitors close to RTL8106E within 200 mil

RJ45_MIDI0+

RJ45_MIDI0-

RJ45_MIDI1+

RJ45_MIDI1-

CL16 1000 P_1206_2KV7KCL16 1000P_1206_2KV7K

1 2

1

2

3

4

5

6

7

8

EMI@ CL17

EMI@

+3V_LAN

1

2

JRJ45

PR1+

PR1-

PR2+

PR3+

PR3-

PR2-

PR4+

GND GND

PR4-

SANTA_130456-491

Conn@

12

CL17 220P_0603_50V8J

220P_0603_50V8J

CL8 close to Pin32 CL20 close to Pin23

1 2

CL8 0.1U_0402_10V7KCL8 0.1U_0402_10V7K

1 2

CL20 0.1U_0402_10V7KCL20 0.1U_0402_10V7K

YL1 25MHZ _20PF_7V25000016YL1 25MHZ _20PF_7V25000016

1

GND

CL9

CL9 27P_0402_50V8J

27P_0402_50V8J

2

For ESD, keep c lose to RJ45 Co nnector C

hange back to c onnect to LANGN D only

on 20130201

LANGND

9 10

3

GND

4

27P_0402_50V8J

DL1

ESD@DL1

ESD@

2

3

YSLC05CH_SOT23-3

LAN_X2LAN_X1

CL10

1

2

3 3

For LAN function

RL24 10K_0402_5%RL24 10K_0402_5%

+3VS

LAN_EN<8>

CLKREQ_LAN#<8>

4 4

12

A

LANCLK_REQ#

2

1 3

D

QL53

2N7002KW_SOT323-3

G

LANCLK_REQ#

S

+3VS

12

1K_0402_5%

1K_0402_5% RL8

RL8

@

ISOLATE#

RL9

15K_0402_5%

B

1 2

RL433 0_0402_5%Rshort@RL433 0_0402_5%Rshort@

WOL_EN#

Sx Enable Wake up

LOW

WOL_EN# <27>

Sx Disable Wake up

HIGH

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

+3V_LAN rising time (10%~90%) need > 1ms and <100ms.

LAN WOL LAN_EN ISOLATEB S0 Sx S0 Sx

--------------------------------------------- 0 0 0 0 1 1 0 1 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 0*

* S3: after SUSP# assert low over 100ms S4/S5: after SYSON assert low over 100ms

2013/05/15 2015 /09/27

C

2013/5/3 EMI request change CL17 BOM structure to EMI@

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

PCIe-LAN-RTL8106E

LA-A551P

E

0.1

of

22 40Monday, May 06, 2013

of

22 40Monday, May 06, 2013

of

22 40Monday, May 06, 2013

5

Slot 1 Half PCIe Mini Card-WLAN

4

3

2

1

JWLAN

1

3

PJ11

+3V_WLAN

1

2

2 1

JUMP_43X39

@

40 mils

0.1U_0402_10V7K

1

CM2

2

CM3

D D

+3V_WLAN

CM1

0.1U_0402_10V7K

+3VS

1

2

4.7U_0603_6.3V6K

CLKREQ_WLAN#<8>

PCIE_WLANTX_ARX_N2<5>

PCIE_WLANTX_ARX_P2<5>

PCIE_ATX_C_WLANRX_N2<5> PCIE_ATX_C_WLANRX_P2<5>

1 2

CLK_WLAN#<7> CLK_WLAN<7>

E51_TXD<27>

E51_RXD<27>

RM1

+3V_WLAN

0_0402_5%@

E51_TXD E51_RXD

BT_CTRL_RBT_ON

Debug card using

C C

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

GND1

LCN_DAN08-52406-0500

Conn@

GND2

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

+3V_WLAN

WL_OFF# <27> APU_PCIE_RST# <12,22,8>

APU_SCLK0 <10,11,8> APU_SDATA0 <10,11,8>

USB20_N1 <7> USB20_P1 <7>

BT

From EC

WLAN&BT Combo module circuits

BT

n module

o

BT on module

Enable Disable

BT_ON

BT_ON<27>

H L

1 2

RM2

1K_0402_5%

For isolate BT_CTRL and C

ompal Debug Card.

E51_RXDBT_ON

SATA HDD Conn.

ACES_50208-00801-003

Conn@

B B

Conn@

GND GND

JHDD

10 9

8

7

6

5 4 3 2 1

SATA_ATX_C_DRX_P0 SATA_ATX_C_DRX_N0

SATA_DTX_ARX_N0 SATA_DTX_ARX_P0

5 4 3 2 1

+5VS

1 2

C194 0.01U_0402_25V7KC194 0.01U_0402_25V7K

1 2

C195 0.01U_0402_25V7KC195 0.01U_0402_25V7K

1 2

C196 0.01U_0402_25V7KC196 0.01U_0402_25V7K

1 2

C198 0.01U_0402_25V7KC198 0.01U_0402_25V7K

SATA_ATX_DRX_P0 <7> SATA_ATX_DRX_N0 <7>

SATA_DTX_C_ARX_N0 <7>

SATA_DTX_C_ARX_P0 <7>

Close to JHDD

+5VS

12

A A

5

Place closely JHDD SATA CONN.

1.2A

C185

C185 10U_0805_6.3V6M

10U_0805_6.3V6M

1

C186

0.1U_0402_10V7K

2

1

C187

0.1U_0402_10V7K

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/15 2015/09/27

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

WLAN/SATA HDD&ODD

LA-A551P

23 40Monday, May 06, 2013

1

0.1

of

5

4

3

2

1

USB Sleep & Charge

State table for TPS2546RTER

CB1CB0

0

D D

1

0

1

ILIM_SELCB2 STATUS

1 1

1

0

1

ode

M

Auto-detection charger mode for Apple device(2A,1A).

to

Au

Resistor dividers are connected to DP/DM. Including DCP

Forced 1A charger mode for Apple devices. Resistor

Alternate

dividers are connected to DP/DM.

SDP

USB pass-through mode.DP/DM are connected to TDP/TDM

USB pass-through mode with CDP emulation.

CDP

DP/DM are connected to TDP/TDM

SLP_CHG_CB0<8> SLP_CHG_CB1<8>

EC_CHG_CB0<27> EC_CHG_CB1<27> EC_CHG_CB2<27>

Right side USB 3.0 x 1

EMI@

LR1

USB30_RX0N<7>

USB30_RX0P<7>

C C

USB30_TX0N<7>

USB30_TX0P<7>

USB30_RX0N

USB30_RX0P

CR15 0.1U_0402_16V7KCR15 0.1U_0402_16V7K

CR16 0.1U_0402_16V7KCR16 0.1U_0402_16V7K

USB20_N8<7>

USB20_P8<7>

1 2

USB30_TX0N_C

1 2

USB30_TX0P_C

USB20_N8

USB20_P8 USB20_P8_L

4

1

KINGCORE WCM-2012HS-670T

LR3

4

1

KINGCORE WCM-2012HS-670T

LR2

4

1

WCM-2012-900T_0805

3

USB30_RX0N_L

3

2

USB30_RX0P_L

2

EMI@

3

USB30_TX0N_C_L

3

2

USB30_TX0P_C_L

2

EMI@LR2

EMI@

3

USB20_N8_L

3

4

1

2

USB30_RX1N<7>

USB30_RX1P<7>

USB30_TX1N<7>

USB30_TX1P<7>

Right side USB 3.0 x 1 W/ Sleep&Charge

+5VALW +USB_VCCA

0_0402_5%

0_0402_5% 0_0402_5%

0_0402_5%

0_0402_5% 0_0402_5%

0_0402_5%

LR4

4

1

LR6

4

1

RR8

RR9

RR10

USB_CHG_OC#<27,8>

USB_CHG_EN<27>

EMI@

@RR8

@

1 2

@RR9

@

1 2

@RR10

@

3

2

3

2

10K_0402_5%

ILIM_SEL<27>

USB30_RX1N

USB30_RX1P USB30_RX1P_L

1 2

CR17 0.1U_0402_16V7KCR17 0.1U_0402_16V7K

1 2

CR18 0.1U_0402_16V7KCR18 0.1U_0402_16V7K

0_0402_5%

@

RR2

@

RR3

RR7

RR7 RR6

RR6 RR12

RR12

+3VALW_APU

KINGCORE WCM-2012HS-670T

USB30_TX1P_C

KINGCORE WCM-2012HS-670T

RB7

PU

EC_CHG_CB2

EC_CHG_CB0

EC_CHG_CB1

USB30_RX1N_L

USB30_TX1N_C_LUSB30_TX1N_C

USB30_TX1P_C_L

ILIM_SEL_R

CHG_CB0 CHG_CB1

2.5A

UR4

1

IN

9

STATUS#

13

FAULT#

4

ILIM_SEL

5

EN

6

CTL1

7

CTL2

8

CTL3

TPS2546RTER_QFN16_3X3

TPS2546@

UR4

TPS2544RTER_QFN16_3X3

TPS2544@

USB20_DP9 USB20_P9_L

+USB_VCCA

W=100milsW=100mils

12

OUT

10

USB20_DN9

DM_IN

11

USB20_DP9

DP_IN

2

DM_OUT

3

DP_OUT

15

ILIM_HI

GND

T-PAD

ILIM_LO

16

ILIM_HI

14 17

4

1

WCM-2012-900T_0805

LR5

4

1

ILIM_LO

Sleep & Charge Port

W=100mils

USB20_N9_L USB20_P9_L

USB30_RX1N_L USB30_RX1P_L

USB30_TX1N_C_L USB30_TX1P_C_L

USB20_N9 <7> USB20_P9 <7>

RR11

RR11 RR5

RR5

Close to UR4 IN/OUT

+5VALW

@

EMI@LR5

EMI@

3

2

JUSBF

1

VBUS

2

D-

3

D+

4

GND

5

StdA-SSRX-

6

StdA-SSRX+

7

GND-DRAIN

8

StdA-SSTX-

9

StdA-SSTX+

SINGA_2UB3914-000101F

W=100mils

1

CR8

2

0.1U_0402_10V7K

3

2

GND GND GND GND

USB20_N9_LUSB20_DN9

12 12

20K_0402_1%

20K_0402_1% 20K_0402_1%

20K_0402_1%

+USB_VCCA

Conn@JUSBF

Conn@

10 11 12 13

1

CR7

2

0.1U_0402_10V7K

W=100mils

1

CR2

2

47U_0805_6.3V6M

1

CR9

@

2

4.7U_0603_6.3V6K

+USB_VCCB

B B

W=80mils

USB20_N8_L USB20_P8_L

USB30_RX0N_L USB30_RX0P_L

USB30_TX0N_C_L USB30_TX0P_C_L

JUSBR

1

VBUS

2

D-

3

D+

4

GND

5

StdA-SSRX-

6

StdA-SSRX+

7

GND-DRAIN

8

StdA-SSTX-

9

StdA-SSTX+

USB POWER SWITH

6

OUT

7

OUT

8

OUT

5

OCB

W=80mils

1

CR3

2

47U_0805_6.3V6M

W=80mils

+USB_VCCB

1

CR13

@

2

4.7U_0805_10V4Z

+5VALW

2.0A

UR2

2

IN

3

IN

USB_EN#0<27>

A A

4

EN/ENB

1

GND

SY6288DCAC_MSOP8

SA00003TV00 SA00003XM00

+USB_VCCB

1

CR11

2

0.1U_0402_10V7K

5

Conn@JUSBR

Conn@

10

GND

11

GND

12

GND

13

GND

SINGA_2UB3914-000101F

USB_OC#0 <27,8>

DR1

@ESD@

DR1

@ESD@

USB30_TX0P_C_L

USB30_TX0N_C_L

USB30_RX0P_L

USB30_RX0N_L

Change ESD Diode for EMI request

USB30_TX1P_C_L

USB30_TX1N_C_L

USB30_RX1P_L

USB30_RX1N_L

Change ESD Diode for EMI request

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2013/05/15 2015/09/27

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

1

2

4

5

3

8

YSCLAMP0524P_SLP2510P8-10-9

SC300002800

DR3

1

2

4

5

3

8

YSCLAMP0524P_SLP2510P8-10-9

SC300002800

Compal Electronics, Inc.

LUSB/RUSB/S&C

LA-A551P

9

USB30_TX0P_C_L

10

8

USB30_TX0N_C_L

9

7

USB30_RX0P_L

7

6

USB30_RX0N_L

65

@ESD@

9

USB30_TX1P_C_L

10

8

USB30_TX1N_C_L

9

7

USB30_RX1P_L

7

6

USB30_RX1N_L

65

0.1

24 40Monday, May 06, 2013

1

24 40Monday, May 06, 2013

0.1

5

4

3

2

1

Small board Conn

JSB5

Conn@JSB5

JSB4

Conn@JSB4

Conn@

+USB_VCCC

D D

USB20_N0<7> USB20_P0<7>

USB20_N2<7> USB20_P2<7>

USB20_N0 USB20_N0_L_R

LR7

EMI@LR7

4

1

4

1

EMI@

4

1

WCM- 2012-900T_0805

LR8

EMI@LR8

EMI@

4

1

WCM- 2012-900T_0805

3

2

3

2

Close to JSB4

USB20_N0_L USB20_P0_L

USB20_N2_L USB20_P2_L

R44 0_0402_5%14@R44 0_0402_5%14@ R45 0_0402_5%14@R45 0_0402_5%14@

R46 0_0402_5%14@R46 0_0402_5%14@ R47 0_0402_5%14@R47 0_0402_5%14@

Left USB 2.0 x 1

W=80mils

OUT OUT OUT OCB

+USB_VCCC+5VALW

6 7 8 5

USB_OC#2 <27,8>

C C

USB_EN#2<27>

2.0A

UR3

2

IN

3

IN

4

EN/ENB

1

GND

SY6288DCAC_MSOP8

SA00003TV00 SA00003XM00

+5VALW +5VALW

+3VL

+3VS

1 2 1 2

USB20_P0_L_RUSB20_P0

PL<26> PR<26>

EXT_MIC_L<26>

NBA_PLUG<26>

USB20_N2_RUSB20_N2 USB20_P2_RUSB20_P2

LID_SW#<27>

BATT_FULL_LED#<27>

BATT_CHG_LOW _LED#<27>

PWR_SU SP_LED#<27>

WL_BT_LED #<27 >

TP_DATA<27>

TP_CLK<27>

TP_I2CSDA1 TP_I2CSCL1

29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

32

3030GND

31

GND

29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

ACES_51522-03001-P01

TP_I2CSCL1

TP_I2CSDA1

R298

4.7K_0402_5%

+USB_VCCC

Close to JSB5

USB20_N0_L USB20_P0_L

USB20_N2_L USB20_P2_L USB20_P2_L_R5

+3VS

1 2

R49 0_0402_5%15@R49 0_0402_5%15@ R50 0_0402_5%15@R50 0_0402_5%15@

R53 0_0402_5%15@R53 0_0402_5%15@ R51 0_0402_5%15@R51 0_0402_5%15@

R299

4.7K_0402_5%

1 2

DMN66D0LDW -7 2N_SOT363-6

+3VL +3VS

1 2 1 2

2

Q8A

4

DMN66D0LDW -7 2N_SOT363-6

61

+3VS

5

Q8B

PL PR

EXT_MIC_L NBA_PLUG

LID_SW# BATT_FULL_LED# BATT_CHG_LOW _LED# PWR_SU SP_LED# WL_BT_LED #

3

USB20_N0_L_R5 USB20_P0_L_R5

USB20_N2_L_R5

TP_DATA TP_CLK

TP_I2CSDA1 TP_I2CSCL1

Conn@

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

29 3030GND

ACES_51522-03001-P01

APU_SCLK1 <8>

APU_SDATA1 <8>

GND

31 32

SPK Conn.

JSPK

SPK_L1<26> SPK_L2<26> SPK_R1<26 > SPK_R2<26 >

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2013/05/15 2015/09/27

3

Compal Secret Data

Deciphered Date

1

2

3

4

5

G1

6

G2

E&T_3802-F04N-01R

Conn@

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

USB-CardReader Genesys GL834L

LA-A551P

25 40Monday, May 06, 2013

of

1

of

0.1

5

UA1

10 mil

AC_JDREF LDO_CAP AC_VREF

CPVEE

CBN CBP

EC_MUTE#

Hight LOW

22 21

17 16

31 30 29

15 14

20

12

10

11

19 28 27 34 35 36

2 3

13 18

47

4

ALC259-VC2-CG_MQFN48_6X6

259@

Internal AMP

Enable Disable

MIC1_LINE1_R_R MIC1_LINE1_R_L

D D

@ESD@

0.01U_0402_25V7K

1 2

CA65

AZ_RST_HD#<8>

close to pin 28

1 2

CA60 10U_0603_6.3V6MCA60 10U_0603_6.3V6M

1

12

CA25

2.2U_0603_10V6K

C C

INT_MIC_CLK<20>

CA55

0.1U_0402_10V7K

2

close to pin19

RA30 20K_0402_1%RA30 20K_0402_1%

1 2

CA54 2.2U_0402_6.3V6MCA54 2.2U_0402_6.3V6M

1 2

CA53 2.2U_0402_6.3V6MCA53 2.2U_0402_6.3V6M

INT_MIC_DATA<2 0>

12

@

RA34 20K_0402_1%

For EMI reserve

INT_MIC_CLK_R

RA42

FBMA-10-100505-301T

CAM_EMI@

EC_MUTE#<27>

CA584.7U_0603_6.3V6K CA584.7U_0603_6.3V6K CA574.7U_0603_6.3V6K CA574.7U_0603_6.3V6K

+MIC1_VREFO_L

EC_MUTE_INT<27>

AZ_SYNC_HD<8>

12

MIC1_LINE1_R_C_R MIC1_LINE1_R_C_L

MONO_IN

INT_MIC_CLK_R

SENSE_A SENSE_B

COMBO_GPI

4

MIC1_R MIC1_L

MIC2_R MIC2_L

MIC1_VREFO_L MIC1_VREFO_R MIC2_VREFO

LINE2_R LINE2_L

MONO_OUT

PCBEEP

SYNC

RESET#

JDREF LDO_CAP VREF CPVEE CBN CBP

GPIO0/DMIC_DATA GPIO1/DMIC_CLK

SENSE_A SENSE_B

EAPD PD#

DVDD

DVDD_IO

AVDD1 AVDD2

PVDD1 PVDD2

SPK_OUT_R+

SPK_OUT_R-

SPK_OUT_L+

SPK_OUT_L-

HPOUT_R

HPOUT_L

SDATA_OUT

SDATA_IN

BCLK

LINE1_L

LINE1_R

AVSS1 AVSS2 PVSS1 PVSS2

DVSS

Thermal Pad

NC

1 9

25 38

39 46

45 44

40 41

33 32

5 8

AZ_SDIN0_HD_R

6

AZ_BITCLK_HD

23 24 48

26 37 42 43 7

49

DGND

+DVDD +DVDD_IO

+AVDD +AVDD

+PVDD +PVDD

SPKR+ SPKR-

SPKL+ SPKL-

HPOUT_R HPOUT_L

AGND

75_0402_1%

RA19

RA19 RA20

RA20

75_0402_1%

12

RA23 33_0402_5%RA23 33_0402_5%

For EMI reserve close to codec

AZ_BITCLK_HD

3

0.1U_0402_16V4Z

close to pin1

close to pin9

HP_R HP_L

AZ_SDOUT_HD <8>

AZ_SDIN0_HD <8>

AZ_BITCLK_HD <8>

12

@EMI@

RA4110_0402_5%

10P_0402_50V8J

35mA for 3.3V level

+DVDD

1

CA4

2

+DVDD_IO

1

CA45

0.1U_0402_16V4Z

CA51

1 2

@EMI@

2

RA22

0_0402_5%

1

CA3

2.2U_0402_6.3V6M

2

RA1

0_0402_5%

1 2

@

RA45 0_0603_5%

1 2

@

RA46 0_0603_5%

1 2

@

RA43 0_0603_5%

1 2

RA38 0_0603_5%

@EMI@

1 2

RA31

@EMI@

+3VS +5VALW

HDALink is 1.5V

+1.5VS

0_0603_5%

2

mil20 mil

40

close to pin 25 close to pin 38

+AVDD

CA42

10U_0603_6.3V6M

close to pin39

close to pin46

650mA for 5V level

0.1U_0402_10V7K

2

1

CA47

1

0.1U_0402_10V7K

CA33

CA32

2

CA37

10U_0603_6.3V6M

60 mil

+PVDD

1

2

1

2

1

0.1U_0402_10V7K

1

CA50

2

CA35

1

10U_0603_6.3V6M

1

RA18

1 2

0_0603_5%

RA21

1 2

0_0603_5%

RA24

1 2

0_0603_5%

RA25

1 2

0_0603_5%

@RA18

@

+5VS

@RA24

@

+5VALW

+5VS

Beep sound

PCI Beep

APU_SPKR<8>

B B

Sense Pin

Impedance

39.2K

SENSE A

A A

20K

10K

5.1K

39.2K

20

K

10K

5

RA52

1 2

47K_0402_5%

RA49

4.7K_0402_5%

1 2

Codec Signals

PORT-I (PIN 32, 33)

PORT-B (PIN 21, 22)

PORT-C (PIN 23, 24)

(PIN 48)

PORT-E (PIN 14, 15)

PORT-F (PIN 16, 17)SENSE B

PORT-H (PIN 20)

CA70

1 2

0.1U_0402_10V7K

CA27

100P_0402_50V8J

For better sound by

customer request

Function

Headphone out

Ext. MIC

MONO_IN

4

4ohm =40mil For EMI reserve

2W 1W 8ohm =20mil

SPKL+

SPKL-

SPKR+

SPKR-

close to codec

1 2

Rshort@

RA7 0_0603_5%

1 2

Rshort@

RA8 0_0603_5%

1 2

Rshort@

RA9 0_0603_5%

1 2

Rshort@

RA10 0_0603_5%

1000P_0402_50V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

CA31

@EMI@

CA34

@EMI@

1

2

1

2

3

SPK_L1 <25>

1

CA30

CA30 1000P_0402_50V7K

1000P_0402_50V7K

2

@EMI@

1

CA36

CA36 1000P_0402_50V7K

1000P_0402_50V7K

2

@EMI@

SPK_L2 <25>

SPK_R1 <25>

SPK_R2 <25>

2013/05/15 2015 /09/27

SPK

Combo Jack

+MIC1_VREFO_L

MIC1_LINE1_R_R

MIC1_LINE1_R_L

COMBO_GPI

if need EMI material will use SM01000GK00

HP_R

HP_L

Compal Secret Data

Deciphered Date

RA69 2.2K_0402_5%RA69 2.2K_0402_5%

RA35 1K_0402_5%RA35 1K_0402_5%

CA48

10U_0603_6.3V6M

1 2

LA7 0_0402 _5%Rshort@LA7 0_0402_5%Rshort@

1 2

LA6 0_0402 _5%Rshort@LA6 0_0402_5%Rshort@

NBA_PLUG<25>

1 2

1

2

RA71

1 2

22K_0402_5%

CA74

@EMI@

EXT_MIC

1

2

100P_0402_50V8J

12

RA70

CA75

1

2

@EMI@

100P_0402_50V8J

place close to chip

RA61 39.2K_0402_1%RA61 39.2K_0402_1%

2

Change material to SM01000GK00

LA8

EMI@LA8

EMI@

0_0402_5%

1

2

CA69

22K_0402_5%

100P_0402_50V8J

PR <25>

PL <25>

SENSE_A

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

EXT_MIC_L <25>

1

of

26 40Monday, May 06, 2013

of

26 40Monday, May 06, 2013

of

26 40Monday, May 06, 2013

0.1

5

0.1U_0402_10V7K

1

CB2

CB4

2

0.1U_0402_10V7K

SLP_S3#<8> SLP_S5#<8> EC_SMI#<8>

KB_LED<28>

WL_OFF#<23>

E51_TXD<23>

E51_RXD<23>

BT_ON<23>

1 2

Rshort@

1 2

Rshort@

0.1U_0402_10V7K

1

2

EC_MUTE_INT_R

100K_0402_5%

0.1U_0402_10V7K

1

CB1

0.1U_0402_10V7K

For EMI

CLK_PCI_EC

12

RB3

10_0402_5%

@EMI@

22P_0402_50V8J

RB2

47K_0402_5%

1 2

CB12 0.1U_0402_10V7KCB12 0.1U_0402_10V7K

1 8 2 7 3 6 4 5

2.2K_0804_8P4R_5%

ESD@

1 2

CB6 0.1U_0402_10V7K

@ESD@

1 2

CB14 180P_0402_50V8J

@EMI@

CB11

@EMI@

RPB1

1

2

EC_RST#

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

SYS_PWRGD

SUSP#

D D

+3VL

C C

SMBUS1->BATT, S mart Charger

BUS2->G-Sensor, GPU Thermal Sen sor,

SM APU The rmal Sensor

EC SMBus2 for S 0 , SMBus1 for S5

+3VL

+3VS

B B

0.1U_0402_10V7K

KSI[0..7]<28>

KSO[0..17]<28>

EC_MUTE_INT<26>

P.32_SYS_PWRGD OD/L for 1.8V PU APU

2

GATEA20<8> KB_RST#<8> SERIRQ<7>

LPC_FRAME#<7,8>

LPC_AD3<7> LPC_AD2<7> LPC_AD1<7> LPC_AD0<7>

CLK_PCI_EC<7,8>

LPC_RST#<8>

EC_SCI#<8>

0.95VS_PWREN#<29>

KSI[0..7]

KSO[0..17]

EC_SMB_CK1<31,32> EC_SMB_DA1<31,32> EC_SMB_CK2<13,6> EC_SMB_DA2<13,6>

USB_OC#2<25,8> USB_CHG_OC#<24,8> USB_CHG_EN<24>

USB_EN#2<25>

FAN_SPEED1<5>

SYS_PWRGD<8>

EC_CHG_CB2<24>

RB25 0_0402_5%

RTC_CLK<8>

RB25 0_0402_5% RB20 0_0402_5%

RB20 0_0402_5%

Close to EC

RB27

100K_0402_5%

1 2

4.7K_0402_5%

A A

1 2

RB28

E51_TXD

EC_MUTE_INT_R

5

EC_ON_R

885_EC_ON

RB36 0_0402_5%

1 3

1

CB5

2

EC_RST#

KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8

KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17

EC_SMB_CK1

EC_SMB_DA1

EC_SMB_CK2

EC_SMB_DA2

E51_TXD

XCLKO

12

RB22

9012@

1 2

D

QB2

2N7002KW_SOT323-3

885@

G

2

RB24

RB24 10K_0402_5%

10K_0402_5%

885@

1 2

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7

S

4

1 2 3 4 5 7 8

10

12 13 37 20 38

55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82

77 78 79 80

6 14 15 16 17 18 19 25 28 29 30 31 32 34 36

122 123

1

CB16

CB16 20P_0402_50V8

20P_0402_50V8

2

+3VL

UB1

GATEA20/GPIO00 KBRST#/GPIO01 SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1

LPC & MISC

LPC_AD0

CLK_PCI_EC PCIRST#/GPIO05 EC_RST# EC_SCII#/GPIO0E GPIO1D

KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24

Int. K/B

KSO5/GPIO25

Matrix

KSO6/GPIO26 KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49

EC_SMB_CK1/GPIO44 EC_SMB_DA1/GPIO45 EC_SMB_CK2/GPIO46 EC_SMB_DA2/GPIO47

PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 GPIO0A GPIO0B GPIO0C GPIO0D EC_INVT_PWM/GPIO11 FAN_SPEED1/GPIO14 EC_PME#/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 PCH_PWROK/GPIO18 SUSP_LED#/GPIO19 NUM_LED#/GPIO1A

XCLKI/GPIO5D XCLKO/GPIO5E

RB19 330K_0402_5%

1

1U_0402_6.3V6K

1U_0402_6.3V6K CB50

CB50

2

@

9

22

33

EC_VDD/VCC

PWM Output

DA Output

PS2 Interface

SPI Device Interface

SM Bus

GPIO

GND/GND

11

24

885@

12

96

111

EC_VDD/VCC

AD Input

SPI Flash ROM

GPIO

GND/GND

35

94

For KB9012 EC_ON low pulse work around

4

+3VL

CB3

0.1U_0402_10V7K

1 2

125

67

EC_VDD0

EC_VDD/VCC

CPU1.5V_S3_GATE/GPXIOA00

GND/GND

GND0

113

BEEP#/GPIO10

EC_VDD/AVCC

ACOFF/GPIO13

BATT_TEMP/GPIO38

ADP_I/GPIO3A

IMON/GPIO43

DAC_BRIG/GPIO3C

EN_DFAN1/GPIO3D

IREF/GPIO3E

CHGVADJ/GPIO3F

EC_MUTE#/GPIO4A

USB_EN#/GPIO4B

CAP_INT#/GPIO4C

EAPD/GPIO4D

TP_CLK/GPIO4E

TP_DATA/GPIO4F

WOL_EN/GPXIOA01

ME_EN/GPXIOA02

VCIN0_PH/GPXIOD00

SPIDI/GPIO5B SPIDO/GPIO5C SPICLK/GPIO58

SPICS#/GPIO5A

ENBKL/GPIO40

PECI_KB930/GPIO41

FSTCHG/GPIO50

BATT_CHG_LED#/GPIO52

CAPS_LED#/GPIO53

PWR_LED#/GPIO54

BATT_LOW_LED#/GPIO55

SYSON/GPIO56 VR_ON/GPIO57

PM_SLP_S4#/GPIO59

EC_RSMRST#/GPXIOA03 EC_LID_OUT#/GPXIOA04

PROCHOT_IN/GPXIOA05

H_PROCHOT#_EC/GPXIOA06

VCOUT0_PH/GPXIOA07

GPO

BKOFF#/GPXIOA08

PBTN_OUT#/GPXIOA09

PCH_APWROK/GPXIOA10

SA_PGOOD/GPXIOA11

AC_IN/GPXIOD01

EC_ON/GPXIOD02

ON/OFF/GPXIOD03

GPI

LID_SW#/GPXIOD04

SUSP#/GPXIOD05

GPXIOD06

PECI_KB9012/GPXIOD07

AGND/AGND

KB9012QF-A4_LQFP128_14X14

69

+3VL

EC_ON <33>

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

GPIO0F

GPIO12

GPIO39

GPIO3B GPIO42

V18R

Issued Date

3

2

20130417 Note. 2013 ENE EC change version

3 (SA00004OB20) to A4 (SA00004OB30)

A

21 23 26 27

63 64 65 66 75 76

68 70

885_EC_ON

71 72

83 84 85 86 87

TP_CLK

88

TP_DATA

97 98 99 109

119 120 126 128

73 74 89

ILIM_SEL

90 91 92 93 95

SYSON

121

VR_ON

127

1.8_0.95VALW_PWRE N

100 101 102 103

H_PROCHOT_EC

104

VCOUT0_PH_L

105 106 107 108

110 112

EC_ON_R

114 115

LID_SW#

116

SUSP#

117 118

124

+EC_V18R

Voltage Comparator Pins FOR 9012 A3

VCIN0 pin109 VCIN1 pin102

VCOUT0 pin104

VCOUT1 pin103

3

WL_BT_LED# <25> USB_EN#0 <24>

BATT_PRES <31> USB_OC#0 <24,8> ADP_I <31,32> ADP_V <32>

DFAN1 <5>

EC_MUTE# <26>

TP_CLK <25> TP_DATA <25>

VGATE <36> GPU_DOWN# <13> POK <33> VCIN0_PH <31>

LCD_ENBKL <20,6> WOL_EN# <22> ILIM_SEL <24>

PWR_SUSP_LED# <25>

1.8_0.95VALW_PWRE N <35>

EC_RSMRST# <8> EC_LID_OUT# <8>

PROCHOT_IN < 31>

BKOFF# <20>

PBTN_OUT# <8> 3VALW_APU_PW REN <29,33> EC_PXCONTROL <8>

ACIN <32>

ON/OFFBTN# <28> LID_SW# <25> SUSP# <29,34> EC_CHG_CB0 <24> EC_CHG_CB1 <24>

1

CB15

4.7U_0805_10V4Z

2

EC_SPIDI <7>

EC_SPIDO <7> EC_SPICLK <7> EC_SPICS# <7>

BATT_FULL_LED# <25> CAPS_LED# <28>

BATT_CHG_LOW_LED# <25> SYSON <29,34> VR_ON <36>

VCIN0_PH connec t to power portion ( 9012 only)

Nuvoton EC shar e ROM

H_PROCHOT_EC H/L, no PU/PD

PBTN_OUT# H

/L, no PU/PD

>1.2V <1.2V

HIGH

LOW

2013/05/15 2015/09/27

LOW

HIGH

Compal Secret Data

Deciphered Date

2

H_PROCHOT_EC

High Active

1

+3VL

LID_SW#

ILIM_SEL

VCOUT0_PH_L

VCOUT0_PH connect to power portion (9012 only)

1.8_0.95VALW_PWRE N

SUSP#

Title

Size Document Number Rev

Date: Sheet

1 2

RB35 47K_0402_5%RB35 47K_0402_5%

RPB2

VR_ON SYSON TP_DATA TP_CLK

2

1 8 2 7 3 6 4 5

4.7K_0804_8P4R_5%

12

@

RB2310K_0402_5%@RB2310K_0402_5%

1 2

Rshort@

RB34 0_0402_5%

1 2

RB26 10K_0402_5%RB26 10K_0402_5%

1 2

RB21 10K_0402_5%RB21 10K_0402_5%

DB1

12

APU_PROCHOT#

@ESD@

SC

V00001K00

close to APU

APU_PROCHOT#

Low Active (+3. 3V)

13

D

2N7002KW_SOT323-3

G

QB1

S

Compal Electronics, Inc.

LPC-EC-KB9012

LA-A551P

Monday, May 06, 2013

+3VALW_APU

VS_ON <33>

APU_PROCHOT# <36,6>

1

+3VS

of

27 40

of

27 40

of

27 40

0.1

5

Power Button

15@

TJG-533-V-T/R_6P

3

4

D D

TJG-533-V-T/R_6P

3

4

1

2

SW2

5

6

14@

1

2

SW3

5

6

TJG-533-V-T/R_6P

3

4

1

2

SW5

5

6

For NPI phase Only

C24

ESD@

+3VL

R202

R202 100K_0402_5%

100K_0402_5%

1 2

1

2

4

ON/OFFBTN#

0.1U_0402_25V6

ON/OFFBTN# <27>

POWER LED

3

+5VS

R5

15@R5

15@

390_0402_5%

1 2

R7

14@R7

14@

390_0402_5%

1 2

R9

R9 390_0402_5%

390_0402_5%

1 2

HT-F196BP5_WHITE

D9

15@D9

15@

2 1

D7

14@D7

14@

2 1

D8

2 1

2

1

Battery Reset

SW4

SW4 TJG-533-V-T/R_6P

TJG-533-V-T/R_6P

3

ENLDO<33>

4

1

2

5

6

Keyboard LED

JBLG Conn@

1

2

3

Q9

+5VS

AO3413_SOT23

D

S

D

S

13

+5VS_LED

KBL@

C C

KB_LED<27>

CAPS_LED#<27>

+3VS

R4 300_0402_5%R4 300_0402_5%

B B

A A

R204

10K_0402_5%

KBL@

2

G

12

13

12

G

2

D

Q10

Q10 2N7002KW_SOT323-3

2N7002KW_SOT323-3

KBL@

S

+3VS_KB KSI1 KSI6 KSI5 KSI0 KSI4 KSI3 KSI2 KSI7 KSO15 KSO12 KSO11 KSO10 KSO9 KSO8 KSO13 KSO7 KSO6 KSO14 KSO5 KSO3 KSO4 KSO0 KSO1 KSO2

KBL@

JKB4

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

34 GND1 GND2

CVILU_CF17341U0R0-NH

Conn@

+5VS_LED

15" KEYBOARD CONN.14" KEYBOARD CONN.

KSI[0..7]

KSO[0..17]

CAPS_LED#CAPS_LED#

D31

ESD@D31

ESD@

1 2

CK0402101V05_0402-2

D31 close between JKB4&JKB5

35 36

CK0402101V05_0402-2

4 5 6

KSI[0..7] <27>

KSO[0..17] <27>

4 GND GND

ACES_50578-0040N-001

+3VS_KB KSI1 KSI6 KSI5 KSI0 KSI4 KSI3 KSI2 KSI7 KSO15 KSO12 KSO11 KSO10 KSO9 KSO8 KSO13 KSO7 KSO6 KSO14 KSO5 KSO3 KSO4 KSO0 KSO1 KSO2

KSO17

KSO16

JKB5

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

GND1

36

GND2

CVILU_CF17341U0R0-NH

Conn@

Screw Hole

CPU

H1

1

H_4P6

@

H2

H_4P6x4P2

@

1

H7

H6

H_3P0

@

1

H5

1

H_6P5

@

H_3P3

@

WLAN standoff

H29

H_3P3

@

1

PTH

H18

H17

1

H_2P5N

@

1

H19

1

H_3P0x2P5N

@

H_3P5x3P0N

@

H20

H_2P8N

@

1

VGA

H4

H3

H_4P2

@

1

H4

H_3P3

@

1

PTH N

H11

H10

H9

H8

H_3P0

H_5P2

@

1

@

1

H13

H_3P5

@

1

H_4P0

@

H_6P5

@

1

PCB Fedical Mark PAD

FD3@FD3

@

1

FD4@FD4

@

1

APU PR sample

UC1

SA00006R410

CPU A4-5000 15W 4C

UC1

SA00006R310

CPU A6-5200 25W 4C

A4R1@

A6R1@

FD2@FD2

FD1@FD1

@

1

ISPD

ZZZ1

DA60011V000

PCB LA-A551P

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/15 2015/09/27

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

KB/TP/LED/LID/DEBUG/ISPD

LA-A551P

28 40Monday, May 06, 2013

1

0.1

of

5

+5VALW

C6

1

@

1U_0402_6.3V6K

2

D D

VIN 5V and 3.3V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm

U1

+3VALW

@ C10

@

1 2

SUSP#

+5VALW

1

C10

1U_0402_6.3V6K

2

SUSP#

3

4

5

6 7

+5VALW TO +5VS +3VALW TO +3VS

VOUT1

VIN1

VOUT1

VIN1

ON1

VBIAS

ON2

VIN2 VIN2

TPS22966DPUR_SON14_2X3

GND

VOUT2

GPAD

CT1

CT2

14

+5VS_LS

13

12

11

10

9 8

+3VS_LS

15

Load switch

4

C5 180P_0402_50V8JC5 180P_0402_50V8J

1 2

C9 330P_0402_50V7KC9 330P_0402_50V7K

1 2

PJ7

1 2

JUMP_43X118

@

PJ6

1 2

JUMP_43X118

+3VS

@PJ7

@

@ C8

@

3

+1.5V

+5VS

2

C7

@ C7

@

0.1U_0402_10V7K

1

2

C8

0.1U_0402_10V7K

1

C14

1

@

1U_0402_6.3V6K

2

VIN 5V and 3.3V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm

+5VALW

+1.8VALW

1

C13

@ C13

@

1U_0402_6.3V6K

2

U2

SUSP#

U2

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

TPS22966DPUR_SON14_2X3

VOUT1 VOUT1

CT1

GND

CT2

VOUT2 VOUT2

GPAD

14 13

12

11

10

9 8

15

+1.8VALW TO +1.8VS

+1.5VS_LS

C12 180P_0402_50V8JC12 180P_0402_50V8J

1 2

C11 330P_0402_50V7KC11 330P_0402_50V7K

1 2

+1.8VS_LS

PJ8

1 2

JUMP_43X79

PJ9

@PJ9

@

1 2

JUMP_43X79

1

+1.8VS

@ C16

@

+1.5VS

@

2

C15

@ C15

@

0.1U_0402_10V7K

1

2

C16

0.1U_0402_10V7K

1

+1.5V TO +1.5VS Load switch

+0.95VALW to +0.95VS

C C

+0.95VALW

Q11

8

D

7

D

6

D

5

D

FDS6676AS_SO8

B B

S S S G

C250

+0.95VS

Vgs=10V,Id=14.5A,Rds=6mohm

1 2 3 4

Q11_GATE

1

12

R217

R217 820K_0402_5%

2

820K_0402_5%

2N7002DW-T/R7_SOT363-6

0.1U_0402_25V6

0.95VS_PWREN#<27>

1 2

R216

220K_0402_5%

61

Q2A

2

R214

470_0805_5%

B+

1 2 3

Q2B

5

2N7002DW-T/R7_SOT363-6

4

2N7002KDWH_SOT363-6

Q3A

+1.5V

1 2 61

R211

R211 470_0805_5%

470_0805_5%

2

SYSON#

100K_0402_5%

SYSON#

SYSON<27,34>

2N7002KDWH_SOT363-6

R212

5

+5VALW

1 2

34

Q3B

+3VALW_APU

R221

R221 470_0805_5%

470_0805_5%

1 2

61

Q5A

2

2N7002KDWH_SOT363-6

3VALW_APU_PWREN

2N7002KDWH_SOT363-6

5

+5VALW

1 2

34

R219

R219 100K_0402_5%

100K_0402_5%

Q5B

+0.75VS

R213

R213 470_0805_5%

470_0805_5%

1 2

61

Q4A 2N7002KDW H_SOT363-6Q4A 2N7002KDWH_SOT363-6

2

SUSP

SUSP#<27,34>

SUSP

5

SUSP#

2N7002KDWH_SOT363-6

+5VALW

1 2

34

R215

R215 100K_0402_5%

100K_0402_5%

Q4B

+3VALW to +3VALW_FCH

+3VALW

+3VL

R224

10K_0402_5%

885@

1 2

3VALW_APU_PWREN<27,33>

A A

3VALW_APU_PWREN

10K_0402_5%

12

R223

R223 100K_0402_5%

100K_0402_5%

9012@

R218

@

5

1 2

34

QC1B

2N7002KDWH_SOT363-6

+3VALW

@

1 2

R220 47K_0402_5%

2

@

C251

0.1U_0402_10V7K

1

AO3413_SOT23

2

@

C252

0.01U_0402_25V7K

1

Vgs=-4.5V,Id=3A,Rds<97mohm

S

@

PJ4

G

2

1 3

PJ4 JUMP_43X39

JUMP_43X39

@

Q12

D

2 1

+3VALW_APU

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/15 2015/09/27

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

DC TO DC INTERFACE

LA-A551P

29 40Monday, May 06, 2013

1

0.1

of

A

B

C

D

EMI Part (47.1)

Other component (37.1)

PL1

EMI@ PL1

A51 need add fuse

1 1

@

PJP1

1

2

3

4

ACES_50299-00401-001

2 2

PF1

21

7A_32V_S1206-H-7.0A

DC_IN_S1

PBJ101 @

- +

ML1220T13RE

12

EMI@

PC102

PC102 1000P_0603_50V7K

1000P_0603_50V7K

12

For ML1220 RTC (38.2)

560_0603_5%

HCB2012KF-121T50_0805

12

100P_0603_50V8

PR101

1 2

EMI@

1 2

PL3

EMI@ PL3

EMI@

1 2

EMI@

PC103

PR102

560_0603_5%

1 2

+RTC_R

12

PC101

100P_0603_50V8

+RTC

EMI@PC101

EMI@

VIN

12

EMI@

PC104

PC104 1000P_0603_50V7K

1000P_0603_50V7K

For RTC (38.2)

+RTC_APU_R

3

2

AP2138N-1.5TRG1_SOT23-3

12

PC10

1U_0402_6.3V6K

PU1

Vout

GND

1

Vin

12

+RTC

PC9

1U_0402_6.3V6K

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/09/27 2015/09/27

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DCIN/PRECHARGE

ZRMAE

D

30 40

of

0.1

A

B

C

D

@

PJP2

10

GND

9

GND

8

7

1 1

6

5

4

3

2

1

ACES_50458-00801-001

Other component (37.1)

PF2

10A_125V_TR2/6125FF10-R

BATT_S1

BATT_P5 EC_SMDA EC_SMCA

10A_125V_TR2/6125FF10-R

21

12

PR14

PR14 1K_0402_1%

1K_0402_1%

+3VL

12

PR16

6.49K_0402_1%

12

PR19

1K_0402_1%

PR20

100_0402_1%

2 2

100_0402_1%

2 1

PR21

PR21 100_0402_1%

100_0402_1%

2 1

BATT_PRES <27>

EC_SMB_DA1 <27,32>

EC_SMB_CK1 <27,32>

EMI Part (47.1)

VMB

12

EMI@ PC7

EMI@

1000P_0402_50V7K

PL2

EMI@ PL2

EMI@

FBMA-L11-201209-121LMA50T_0805

1 2

PL4

EMI@ PL4

EMI@

FBMA-L11-201209-121LMA50T_0805

PC7

12

PC8

EMI@ PC8

EMI@

0.01U_0402_25V7K

BATT+

OTP (39.7)

ADP_I<27,32>

@PR2

@

0_0402_5%

PROCHOT_IN<27> VCIN0_PH<27>

1 2

PR2

+3VL

12

PR4

PR1

1 2

1K_0402_1%

PR3

1 2

20K_0402_1%

PR5

@PR5

@

0_0402_5%

1 2

12

PC11

@PC11

@

0.1U_0402_10V7K

PR4

12.1K_0402_1%

12

PH1

100K_0402_1%_TSM0B104F4251RZ

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

2012/09/27 2015/09/27

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

BATTERY CONN / OTP

ZRMAE

D

31 40

of

0.1

A

B

C

D

for reverse input protection

Charger controller (40.1), Support component (40.2)

13

D

2

PQ209

G

2N7002FU_SOT23

S

PR225

1 2

1M_0402_5%

1 1

2 2

3 3

1M_0402_5%

TPCA 8057

PQ203

5

12

PC230

2200P_0402_50V7K

1 2

3M_0402_5%

P1

1 2 3

4

BQ24725_ACDRV_1

Vin Dectector

Min. Typ Max. H-->L 17.23V L--> H 17.63V

ILIM and external DPM

3.97A

4 4

PR226

S

SI7716ADN-T1-GE3_POWERPAK8-5

1 2 3

12

PC231

0.1U_0402_25V6

12

PR235

PR234

4.12K_0603_1%

PQ205

EMI Part (47.1)

P2

5

4

PC238

+3VL

PR239 10K_0402_1%PR239 10K_0402_1%

12

0.1U_0402_25V6

PR211

0.01_1206_1%

1

2

1 2

PC236

0.1U_0402_25V6

BQ24725_ACP

BQ24725_CMSRC

BQ24725_ACDRV

1 2

BQ24725_ACN

BQ24725_ACOK

ACIN<27>

VIN

12

PC244

4

3

0.1U_0402_25V6

12

PC235

12

B+VIN

0.1U_0402_25V6

PC239

1 2

1U_0603_25V6K

PU200

21

PAD

1

ACN

2

ACP

3

CMSRC

4

ACDRV

5

ACOK

PR244

422K_0402_1%

PR245

66.5K_0402_1%

66.5K_0402_1% PC245

PC245

100P_0402_50V8J

EMI@

1UH_NRS4018T1R0NDGJ_3.2A_30%

VIN

2

3

PD230

PD230 BAS40CW_SOT323-3

BAS40CW_SOT323-3

0.047U_0402_25V7K

1 12

PC237

1 2

PR228

10_1206_1%

PR229

2.2_0603_5%

BQ24725_VCC

BQ24725_LX

DH_CHG

20

18

19

VCC

HIDRV

PHASE

ACDET6IOUT7SDA8SCL9ILIM

BQ24725_ACDET

PR246

@PR246

@

0_0402_5%

12

0_0402_5%

1 2

PL201

1 2

12

BQ24725_REGN

BQ24725_BST

17

16

BTST

REGN

LODRV

BATDRV

10

12

PC211

10U_0805_25V6K

12

PC213

10U_0805_25V6K

PD231

PD231 RB751V-40_SOD323-2

RB751V-40_SOD323-2

DH_CHG

PC205

1 2

1U_0603_25V6K

15

14

GND

13

SRP

12

SRN

11

BQ24725RGRR_QFN20_3P5X3P5

BQ24725_ILIM

12

PR242

100K_0402_1%

12

PC246

@PC246

@

0.1U_0402_10V7K

PR210

0_0603_5%

1 2

DL_CHG

PR236

10_0603_1%

1 2

SRP

PR237

6.8_0603_5%

1 2

SRN

BQ24725_BATDRV

1 2

PR241

590K_0402_1%

PC243

0.01U_0402_25V7K

EC_SMB_CK1 <27,31>

EC_SMB_DA1 <27,31>

ADP_I <27,31>

Please locate t he RC Near EC chip 2011-02-22

PC214

@EMI@

CSOP1

CSON1

2200P_0402_25V7K

+5VALW

5

4

5

4

12

PC242

0.1U_0603_16V7K

BQ24725_BATDRV

PQ201

PQ201 AON7408L

AON7408L

PL202

123

BQ24725_LX

123

PQ202

AON7406L

PL202

4.7UH_ETQP3W4R7WF N_5.5A_20%

1 2

12

PR206

4.7_1206_5%

@EMI@

12

PC206

680P_0603_50V8J

@EMI@ PC206

@EMI@

E

MI Part (35.33)

309K_0402_1%

PR249

47K_0402_1%

For A51 ADP_V function

1 2

PR233

4.12K_0603_1%

CHG

CSOP1

12

VIN

12

PR247

12

S TR SI7716ADN

S TR SI7716ADN PQ207

PQ207

5

4

BQ24725_BATDRV_1

PR227

0.01_1206_1%

1

2

PC240

0.1U_0402_25V6

12

0.1U_0402_10V7K

4

3

PC247

@PC247

@

1 2 3

12

PC234

0.01U_0402_50V7K

BATT+

CSON1

12

PC241

12

PC222

PC223

10U_0805_25V6K

0.1U_0402_25V6

10U_0805_25V6K

ADP_V <27>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

2012/09/27 2015/09/27

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

CHARGER

ZRMAE

D

32 40

of

0.1

A

B

C

D

3/5VALW controller (35.1), Support component (35.2)

PQ333

S

2N7002FU_SOT23

POK<27>

0_0402_5%

1 2

3/5V_B+

PR333

2N7002FU_SOT23

PR330

14K_0402_1%

1 2

PR331

20K_0402_1%

1 2

+3VL

12

PR335

BST_3V

UG_3V

LX_3V

LG_3V

PR334

499K_0402_1%

1 2

12

PC360

0.1U_0603_25V7K

PR341

@PR341

@

0_0402_5%

1 2

123

3VALW_APU_PWREN<27,29>

5

4

PC335

0.1U_0402_10V7K

1 2

BST1_3V

5

4

AON7406L

AON7406L PQ332

PQ332

1 1

EMI Part (47.1)

B+

EMI@

PL331

HCB2012KF-121T50_0805

1 2

2 2

+3VALWP

3/5V_B+

PC339

@EMI@

12

2200P_0402_50V7K

PC340

10U_0805_25V6K

PL332

4.7UH_ETQP3W4R7W FN_5.5A_20%

1

+

PC354

2

150U_6.3V_20M

12

PQ331

AON7408L

12

PR336

4.7_1206_5%

@EMI@

SNUB_3V

12

PC336

680P_0603_50V8J

@EMI@

EMI Part (35.33)

3 3

3.3V Peak Current 5.78A

EC_ON<27>

VS_ON<27>

OCP current 6.94A Delta I=1.160A ,ripple=1.160 x17m=19.27mV FSW=455kHz ESR 20mohm TYP MAX H/S Rds(on) :27mohm , 34mohm L/S Rds(on) :19mohm , 23.5mohm

G

2

FB_3V

100K_0402_1%

6

7

8

9

10

PR340

2.2K_0402_1%

1 2

S

D

1 3

1 2

4

5

FB2

PGOOD

BOOT2

UGATE2

PHASE2

LGATE2

VIN11ENLDO12SECFB13LDO514LDO3

12

PR338

PC342

100K_0402_1%

1U_0603_10V6K

12

PC343

@

PR339

0_0402_5%

@

PR350

30K_0402_1%

1 2

3/5V_B+

PR351

PR342

PR337

PR357

56K_0402_1%

1 2

121K_0402_1%

150K_0402_1%

2

3

TON

ENTRIP1

ENTRIP2

15

12

4.7U_0603_10V6K

ENLDO<28>

PR351

19.1K_0402_1%

1 2

FB_5V

1

21

FB1

PAD

20

BYP1

19

18

17

16

BST_5V

UG_5V

LX_5V

LG_5V

12

4.7U_0603_10V6K

BOOT1

UGATE1

PHASE1

LGATE1

PU330

PU330 RT8243AZQW_WQFN2 0_3X3

RT8243AZQW_WQFN2 0_3X3

PC344

+3VLP

PC341

PR355

0_0402_5%

1 2

0.1U_0402_10V7K

BST1_5V

12

PC361

10U_0805_25V6K

PC355

1 2

FDMC7692S_MLP8-5

PQ352

PQ351

AON7408L

3 5

241

PL352

2.2UH_MMD-06CZ-2R2M-V1_8A_20%

1 2

E

5

4

12

PR356

4.7_1206_5%

@EMI@ PR356

@EMI@

SNUB_5V

123

12

PC356

680P_0603_50V8J

@EMI@ PC356

@EMI@

MI Part (47.1)

1

+

PC353

2

150U_6.3V_20M

+5VALWP

5V Peak Current 6.8A OCP current 8.16A FSW=390kHz Delta I=2.791A,ripple=2.791*15m=41.865mV ESR 20mohm

PR332

@ PR332

@

1 2

100K_0402_5%

4.7U_0805_25V6-K

PJ332

@ PJ332

@

+3VLP +3VL

(100mA,20mils ,Via NO.= 1)

2

JUMP_43X39

112

TYP MAX H/S Rds(on) ::27mohm , 34mohm L/S Rds(on) :10.8mohm , 13.6mohm

PJ331

@ PJ331

@

+3VALWP +3VALW

+5VALWP +5VALW

JUMP_43X118

(8A,160mils ,Via NO.= 16)

JUMP_43X118

(12A,240mils ,Via NO.= 24)

112

PJ351

@ PJ351

@

112

2

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

2011/06/24 2012/07/12

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

3VALW/5VALW

33 40

D

33 40

of

0.1

DDR controller (35.3), Support component (35.4)

EMI@

PL151

B+

PL151

HCB2012KF-121T50_0805

1 2

1.5V_B+

EMI Part (47.1)

BST_1.5V-1

PR155

0_0603_5%

1 2

A

BST_1.5V

+1.5V

12

@EMI@

PC152

2200P_0402_50V7K

PL152

1UH_PCMB063T-1R0MS_12A _20%

+1.5VP

1

+

PC157

2

1 1

PJ750

@ PJ750

@

+0.75VSP +1.5VP

(0.5A,40mils ,Via NO.= 1)

2

JUMP_43X79

112

PL152

12

220U_D2_2V_Y

SNUB_+1.5VP

12

+0.75VS

12

PC154

10U_0805_25V6K

PQ151

AON7408L

123

@EMI@

PR156

4.7_1206_5%

@EMI@

PC156

680P_0402_50V7K

(12A, 480mils ,Via NO.= 24) OCP=13.8A

PQ152

FDMC7692S_MLP8-5

123

SYSON<27,29>

@

2

JUMP_43X118

@

2

JUMP_43X118

PJ151

PJ152

PC155

5

1 2

0.1U_0603_25V7K

4

+5VALW

PR163

@PR163

@

0_0402_5%

1 2

112

+1.5V

DH_1.5V

PR159

5.1_0603_5%

1 2

PC164

1U_0603_10V6K

12

PC166

@PC166

@

0.1U_0402_10V7K

SW_1.5V

DL_1.5V

12

EN_1.5V

PR158

16.2K_0402_1%

1 2

PC162

1U_0603_10V6K

1 2

VDD_1.5V

+5VALW

SUSP#<27,29>

CS_1.5V

1.5V_B+

15

LGATE

14

PGND

13

CS

12

VDDP

11

VDD

PR161

825K_0402_1%

1 2

16

17

19

18

BOOT

PHASE

UGATE

RT8207MZQW_W QFN20_3X3

S5

PGOOD

TON

8

7

9

10

TON_1.5V

PR164

0_0402_5%

12

EN_0.75VSP

12

20

PU150

VTT

PAD

VLDOIN

VTTGND

VTTSNS

GND

VTTREF

VDDQ

FB

S3

6

FB_1.5V

@

PC167

0.1U_0402_10V7K

21

1

2

3

4

5

VTTREF_1.5V

PR162

PR162 10K_0402_1%

10K_0402_1%

1 2

PR160

10.2K_0402_1%

+1.5VP

12

PC160

PC159

10U_0603_6.3V6M

+1.5VP

12

PC163

0.033U_0402_16V7K

+0.75VSP

1.5V Pe

ak Current 8.35A OCP current 9.66A FSW=500kHz DCR 8.3 ~ 10mohm TYP MAX H/S Rds(on) :27mohm , 34mohm L/S Rds(on) :10.8mohm , 13.6mohm

STATE S3 S5 1.5VP VTT_REFP 0.75VSP

S0

S3

S4/S5

Hi Hi

HiLo

Lo Lo

On

Off (Discharge)

On

Off (Discharge)

On

Off (Hi-Z)

Off (Discharge)

Note: S3 - sleep ; S5 - power off

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

2011/06/24 2012/07/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

1.5VP/0.75VSP/1.8VSP

LA-9869P

34 40

of

0.1

A

B

C

D

1.8V controller (35.15), Support component (35.16)

1 1

+3VALW

12

PC458

22U_0603_6.3V6M

PR452

0_0402_5%

1.8_0.95VALW_PWREN<27>

@

PJ451

2

2 2

+1.8VALWP

112

JUMP_43X79

+1.8VALW

0_0402_5%

@

PC453

0.1U_0402_16V7K

22U_0603_6.3V6M

12

+1.8_EN

12

Need create Symbol.

Note:Iload(max)=3A

PU450

1UH_NRS4018T1R0NDGJ _3.2A_30%

4

5

1UH_NRS4018T1R0NDGJ _3.2A_30%

IN

PG

FB6EN

3

LX

2

GND

1

SY8032ABC_SOT23-6

1 2

FB=0.6V

PL451

PR451

100K_0402_1%

PR453

49.9K_0402_1%

1.8V ak Current 2.5A

Pe OCP current 3.5A FSW=800kHz

H/S Rds(on) :100mohm , L/S Rds(on) :80mohm ,

12

PC451

22U_0603_6.3V6M

+1.8VALWP

12

PC450

22P_0402_50V8J

12

PC452

22U_0603_6.3V6M

(2.5A,100mils ,Via NO.=5)

0.95V controller (35.27), Support component (35.28)

PR404

0_0402_5%

12

1.8_0.95VALW _PWREN

12

PC454

@

3 3

@

0.01U_0402_16V7K

EMI Part (47.1)

@EMI@

4.7_1206_5%

HCB2012KF-121T50_0805

B+

4 4

12

PC404

@EMI@

10U_0805_25V6K

2200P_0402_50V7K

+3VALW

B+_0.95V

12

PC410

PU400

8

IN

EN

9

3

2

BS

LX

GND

FB

BYP

ILMT

PG

LDO

SY8208DQNC_QFN10_3X3

1

PC405

0.1U_0603_25V7K

1 2

6

10

LX_0.953V

4

7

5

12

PC402

4.7U_0603_6.3V6K

EMI@

PL402

HCB2012KF-121T50_0805

4.7_1206_5%

1 2

PL401

1UH_PCMB063T-1R0M S_12A_20%

1 2

+3VALW

12

PC411

2.2U_0603_6.3V6K

PR401

@EMI@

680P_0603_50V7K

SNB_0.95V

FB=0.6V

100K_0402_1%

1 2

PR406

PC403

MI Part (47.1)

E

12

PR402

66.5K_0402_1%

12

PC409

12

4700P_0402_50V7K

PR403

1K_0402_1%

12

PC408

PC407

22U_0603_6.3V6M

12

PC406

PC401

22U_0603_6.3V6M

0.95V Peak Current 11.1A OCP current 16A FSW=800kHz

H/S Rds(on) :22mohm L/S Rds(on) :11mohm

+0.95VALWP

12

PC412

@

22U_0603_6.3V6M

+0.95VALW P +0.95VALW

(11A,440mils ,Via NO.=22) OCP=

PJ1

@ PJ1

@

2

JUMP_43X118

112

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2012/09/27 2015/09/27

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

+1.8VALWP/+0.95VALWP

ZRMAE

D

35 40Monday, May 06, 2013

0.1Custom

A

PC535

330P_0402_50V7K

APU_VDDNB_SEN_H<6>

+APU_CORE_NB

VSUMP_NB

1 1

VSUMN_NB

2 2

+1.8VS

3 3

4 4

12

PR578

12

2.61K_0402_1%

PH501

PR582 27.4K_0402_1%PR582 27.4K_0402_1%

470K_0402_5%_TSM0B474J4702RE

PC544 1000P_0402_50V7KPC544 1000P_0402_50V7K

PR585 133K_0402_1%PR585 133K_0402_1%

1 2

PC545

0.1U_0402_25V6

10K_0402_5%_ERTJ0ER103J

12

PC542

0.1U_0603_50V7K

12

1 2

PR588

0_0402_5%

1 2

PH502

12

1000P_0402_50V7K

PR579

1 2

11K_0402_1%

12

APU_PROCHOT#<27 ,6>

1 2

PC546

0.1U_0402_25V6

PR595

133K_0402_1%

1 2

PC550

1 2

PR572

10_0402_5%

12

PC537

1000P_0402_50V7K

PC539

12

PC543

@

12

PR584 0_0402_5%PR584 0_0402_5%

1 2

PR586 0_0402_5%PR586 0_0402_5%

1 2

PR587 0_0402_5%PR587 0_0402_5%

1 2

PR589 0_0402_5%PR589 0_0402_5%

1 2

PR591 0_0402_5%PR591 0_0402_5%

1 2

PR592 0_0402_5%PR592 0_0402_5%

1 2

PR593 0_0402_5%PR593 0_0402_5%

1 2

PC561

@PC561

@

1000P_0402_50V7K

12

PH503

12

PC537

10.5K_0402_1%

1 2

PH504

10K_0402_5%_ERTJ0ER103J

PR576

0_0402_5%

1 2

0.01U_0402_50V7K

1 2

PC540

PC541

PR580

0.1U_0402_16V7K

301_0402_1%

0.033U_0402_16V7K

PR581

@PR581

@

220P_0402_50V7K

100_0402_1%

10.5K_0402_1%

APU_PWRGD<6>

220P_0402_50V7K

12

PR583

12

APU_SVC<6>

APU_SVD<6>

APU_SVT<6>

VR_ON<27>

PR597 27.4K_0402_1%PR597 27.4K_0402_1%

470K_0402_5%_TSM0B474J4702RE

NTC near CPU_CORE H/S mos

VSUM+

VSUM-

12

PR573

1.5K_0402_1%

12

PR598

+5VS

10K_0402_1%

12

PR506

12

2.61K_0402_1%

1 2

12

PC558

0.1U_0603_50V7K

PR571

2K_0402_1%

12

301_0402_1%

SVC

SVD

VDDIO

SVT

ENABLE

PWROK

PR511

PR505

11K_0402_1%

NTC near phase 1 choke

A

12

PR577

12

PU500

1

NTC_NB

2

IMON_NB

3

SVC

4

VR_HOT_L

5

SVD

6

VDDIO

7

SVT

8

ENABLE

9

PWROK

10

IMON

PR599

1 2

0_0402_5%

12

1 2

PC555

0.033U_0402_16V7K

PR501

@ PR501

@

100_0402_1%

B

PR574

137K_0402_1%

100P_0402_25V8K

40TP41

11

ISEN2

ISEN1

1 2

PC556

0.1U_0402_16V7K

374_0402_1%

12

B

390P_0402_50V7K

PC536

12

PC538

12

37

38

39

FB_NB

VSEN_NB

ISUMP_NB

ISUMN_NB

ISL62771HRTZ-T_TQFN40_5X5

ISEN1

ISUMP

ISEN212NTC

13

14

PR503

12

PC559

@PC559

@

820P_0402_50V7K

12

C

D

CPU controller (36.1),Driver (36.2) Support component (36.3)

PR575

41.2K_0402_1%

12

PR569

2.2_0603_5%

1 2

UGATE1

PHASE1

BOOT1

LGATE1

1 2

PR512

BOOT_NB1-1

0.22U_0603_25V7K

PR533

2.2_0603_5%

1 2

0.22U_0603_25V7K

PC510

1 2

BOOT1-1

PR570

2.2_0603_5%

1 2

PC523

D

4

35

36

COMP_NB

ISUMN

15

16

1 2

33

34

LGATE_NB

PHASE_NB

PGOOD_NB

RTN

FB18PGOOD

VSEN

17

1000P_0402_50V7K

@

PC553

330P_0402_50V7K

1 2

PC560

0.01U_0402_50V7K

LGATE_NB1

PHASE_NB1

UGATE_NB1

BOOT_NB1

31

32

BOOT_NB

UGATE_NB

UGATE2

PHASE2

LGATE2

LGATE1

PHASE1

UGATE1

COMP

19

20

PC551

12

PR508

1.87K_0402_1%

PR502

10_0402_5%

PR522

0_0402_5%

1 2

PR521

0_0402_5%

1 2

PR520

10_0402_5%

UGATE_NB1

BOOT_NB1

PHASE_NB1

LGATE_NB1

30

BOOT2

29

28

27

26

VDDP

25

VDD

24

LGATE1

23

PHASE1

22

UGATE1

21

BOOT1

12

BOOT1

+3VS

1

12

PR596

100K_0402_1%

PR510

301_0402_1%

12

2K_0402_1%

12

+APU_CORE

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

2

PC552

100P_0402_25V8K

12

PR507

137K_0402_1%

12

PC557

PR504

330P_0402_50V7K

12

APU_VDD_SEN_H <6>

APU_VDD_SEN_L <6>

C

+5VS

PR590

12

1_0603_5%

12

PC547

1U_0603_25V6K

PC549

PC549 1000P_0402_50V7K

1000P_0402_50V7K

VGATE <27>

PC554

390P_0402_50V7K

12

2012/09/27

12

PC548

1U_0603_25V6K

PR509

@PR509

@

32.4K_0402_1%

12

Compal Secret Data

Deciphered Date

5

4

5

PQ501

AON7518_DFN8-5

123

5

4

PQ502

123

TPCA8059-H_PPAK56-8-5

123

APU_B+

12

PC534

@EMI@PC534

@EMI@

2200P_0402_50V7K

PQ504

25W@ PQ504

25W@

TPCA8059-H_PPAK56-8-5

PC505

10U_0805_25V6K

12

PR517

EMI@

SNB_APU_NB

12

PC514

EMI@ PC514

EMI@

VSUMP_NB

VSUMN_NB

PC506

10U_0805_25V6K

4.7_1206_5%

680P_0603_50V7K

APU_CORE_NB TDC 13A(A) 12A(B) Peak Current 17A(A) 15A(B) OCP current > 21.39A Load line -4mV/A FSW=400kHz DCR 0.98mohm +/-5% TYP MAX H/S Rds(on) :11.2mohm , 14mohm L/S Rds(on) :3.8mohm , 4.8mohm

5

4

5

4

PQ503

AON7518_DFN8-5

123

5

4

PQ506

123

TPCA8059-H_PPAK56-8-5

123

EMI@

12

PR540

SNB_APU

PQ508

12

25W@ PQ508

25W@

PC527

TPCA8059-H_PPAK56-8-5

EMI@

APU_core TDC 15A(A) 13A(B) Peak Current 21A(A) 18A(B) OCP current > 26.58A Load line -4mV/A FSW=400kHz DCR 0.98mohm +/-5% TYP MAX H/S Rds(on) :11.2mohm , 14mohm L/S Rds(on) :3.8mohm , 4.8mohm

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

+CPU_CORE/VDDNBP

E

EMI Part (47.1)

HCB2012KF-121T50_0805

1 2

HCB2012KF-121T50_0805

1 2

1

12

3.65K_0402_1%

PC519

4.7_1206_5%

680P_0603_50V7K

+

PC508

PC507

2

33U_25V_M

PL502

0.22UH_MMD-06DZNR22EO1L_25A_20 %

4

3

PR516

1 2

PR519

PR519 1_0402_1%

1_0402_1%

1 2

APU_B+

EMI Part (47.1)

12

PC520

10U_0805_25V6K

PL503

0.22UH_MMD-06DZNR22EO1L_25A_20 %

4

3

PR541

3.65K_0402_1%

1 2

VSUM+

PR547

PR547 1_0402_1%

1_0402_1%

1 2

VSUM-

ZRMAE

E

PL501

PL504

PC522

@EMI@

36 40Monday, May 06, 2013

1

2

12

2200P_0402_50V7K

EMI@PL501

EMI@

EMI@PL504

EMI@

+APU_CORE_NB

ISENA1N-1

1

2

+APU_CORE

of

B+

1.0

5

D D

4

3

2

1

VGA controller (43.1),Driver (43.2) Support component (43.3)

EMI Part (47.1)

EMI@

PL801

HCB2012KF-121T50_0805

2.37K_0402_1%

1 2

PC818

VID5

0

1

1 0

1

1 2

PC809

1000P_0402_50V7K

12

PC811

330P_0402_50V7K

PR812

1 2

PR816

715_0402_1%

GPIO30

VID4

1

0

0 0

0

11 000

1

B+

PR804

10_0402_5%

12

C C

B B

VSS_GPU_SENSE<16>

VCC_GPU_SENSE<16>

+VGA_CORE

1 2

PR806

10_0402_5%

1000P_0402_50V7K

GPIO6

A A

GPU_B+

12

PC803

PC802

2200P_0402_50V7K

@EMI@

330P_0402_50V7K

1 2

PR813

226K_0402_1%

1 2

PC814

390P_0402_50V7K

PC819

56P_0402_50V8

1 2

PR835

120K_0402_1%

VGA_PWRGD<15,8>

GPIO29

GPIO20

VID2

VID3

1 1

0

1 0 0

1

0

1

11 0.775V

10U_0805_25V6K

PC812

1000P_0402_50V7K

12

8.06K_0402_1%

0

1

10

0

1

10

0

1

0

PC804

10U_0805_25V6K

PC815

12

147K for CPU 47K for GPU

12

PR817

GPIO15

VID1

0

1

0

101.075V

0

1

110

0

1

0

1

0

10

12

PR802

1_0603_5%

PR801

PR809

47K_0402_1%

12

PR801

1_0603_5%

1 2

12

7

6

5

4

3

2

1

0_0402_5%

VSEN

FB

COMP

VW

RBIAS

PGOOD

CLK_EN#

PR29

12

PR718

1.8K_0402_1%

+5VALW

+3VS

1_0603_5%

12

PC806

1U_0603_6.3V6M

GPU_ISUM+

GPU_ISUM-

10

9

8

29

AGND

ISL62881CHRTZ-T_TQFN28_4X4

11

RTN

VDD

ISUM-

ISUM+

PU801

VID5

25

28

12

+5VALW

12

VIN

12

13

IMON

VID323VID424VID626VR_ON27DPRSLPVR

PC807

0.22U_0603_25V7K

BST_GPU

PR841

PR841 0_0402_1%

0_0402_1%

14

BOOT

UGATE

PHASE

VSSP

LGATE

VCCP

VID0

VID1

VID2

22

2.2_0603_5%

15

16

17

18

19

20

21

DH_GPU

LX_GPU

DL_GPU

PR805

12

1_0603_5%

12

2.2U_0603_6.3V6K

12

PR823

10K_0402_1%

PC810

0.1U_0603_25V7K

12

PR814

PC817

12

PR831

PR830

@ PR830

@

10K_0402_1%

12

+5VALW

+3VGS

12

PR832

PR833

@ PR833

@

10K_0402_1%

4

5

4

123

Rds(on):2.7mΩ~3

10K_0402_1%

5

PQ802

S TR TPCA8059-H 1N PPAK56-8

.3mΩ

123

PQ801

S TR TPCA8065-H 1N PPAK56-8

5

4

123

Layout Note: Place near Choke

PQ803

VDDC

1.15V

1.125V1110

1.100V

1.050V

1.025V

1.000V

0.975V

0.950V

0.925V

0.900V

0.875V

0.850V

0.825V

0.800V

GPU_DPRSLPVR

Default

<13>

12

0.1U_0402_16V7K

0.1U_0402_16V7K PR828

PR828

12

47K_0402_1%

PXS_PWREN

PR824 0_0402_5%@PR824 0_0402_5%

PR826 0_0402_5%@PR826 0_0402_5%

PR825 0_0402_5%@PR825 0_0402_5%

PR827 0_0402_5%@PR827 0_0402_5%

PC822

1 2

@

<13>

<14,8>

GPU_VID2

GPU_VID4

GPU_VID3

GPU_VID5

12

PR836

@ PR836

@

PR821 0_0402_5%@PR821 0_0402_5%

1 2

@

<13>

GPU_VID1

12

PR837

10K_0402_1%

<13>

12

PR838

PR839

PR840

@

@ PR838

@

10K_0402_1%

+VGA_CORE

C 21A

TD EDC 31.5A OCP current ?? A FSW=??kHz DCR 1.4m ohm +- 5% T YP MAX H/S Rds(on) :11 .7mohm , 14mohm L/S Rds(on) :2. 7mohm , 3.3mohm

PL802

0.36UH_PDME064T-R36MS_24A_20%

1

12

1 2

S TR TPCA8059-H 1N PPAK56-8

@EMI@

PR808

4.7_1206_5%

@EMI@

PC816

680P_0603_50V7K

GPU_ISUM+

GPU_ISUM-

12

3.65K_0805_1%

PR815

1 2

2.61K_0402_1%

2

PR810

1 2

10KB_0402_5%_ERTJ1VR103J

1 2

PR818

11K_0402_1%

1 2

PC820

0.047U_0402_16V7K

1 2

PC821

0.1U_0402_16V7K

1.2K_0402_1%

4

3

12

PR811

@ PR811

@

0_0402_5%

PH7

B value:4250K±2%

12

PR822

+VGA_CORE

1

+

PC899

PC900

2

330U_D2_2V_Y

560U_D2_2VM_R4.5M

0.1U_0402_16V7K

PC823

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2012/09/27 2015/09/27

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet

Compal Electronics, Inc.

+VPU_COREP

ZRMAE

1

37 40Monday, May 06, 2013

of

0.1

5

4

CPU_Core output CAP (Including MLCC) 36.4

3

2

1

+APU_CORE

12

PC1000

D D

C C

PC1000

10U_0603_6.3V6M

12

PC1004

1U_0402_6.3V6K

12

PC1014

1U_0402_6.3V6K

12

PC1006

@

0.22U_0402_16V7K

12

PC1019

180P_0402_50V8J

+APU_CORE

PC1001

10U_0603_6.3V6M

PC1010

1U_0402_6.3V6K

PC1015

1U_0402_6.3V6K

+APU_CORE_NB

12

PC1002

10U_0603_6.3V6M

12

PC1011

1U_0402_6.3V6K

12

PC1016

1U_0402_6.3V6K

12

PC1003

1U_0402_6.3V6K

12

PC1012

1U_0402_6.3V6K

12

PC1017

1U_0402_6.3V6K

12

PC1013

1U_0402_6.3V6K

12

PC1018

1U_0402_6.3V6K

+APU_CORE_NB

12

PC1036

180P_0402_50V8J

12

PC1005

10U_0603_6.3V6M

12

PC1007

10U_0603_6.3V6M

12

PC1008

10U_0603_6.3V6M

GFX output CAP (Including MLCC) 36.5

+APU_CORE_NB

1

+

PC1032

2

560U_D2_2VM_R4.5M

PC1009

10U_0603_6.3V6M

560U_D2_2VM_R4.5M

kabini

VDD

1

12

+

PC1033

2

@

330U_D2_2V_Y

12

PC1020

1U_0402_6.3V6K

12

PC1025

1U_0402_6.3V6K

560uF*4.5m

12

PC1021

1U_0402_6.3V6K

12

PC1026

1U_0402_6.3V6K

330uF

1

12

PC1023

PC1022

1U_0402_6.3V6K

PC1027

1U_0402_6.3V6K

1

PC1023

1U_0402_6.3V6K

12

PC1028

1U_0402_6.3V6K

12

10uF (0603)

3

PC1024

1U_0402_6.3V6K

@

PC1029

1U_0402_6.3V6K

1u (0402)

180P (0402)

11 1

+VGA_CORE

VDD_NB

+APU_CORE

1

+

PC1100

2

560U_D2_2VM_R4.5M

B B

1

+

PC1101

2

560U_D2_2VM_R4.5M

+VGA_CORE

12

PC1042

PC1043

10U_0603_6.3V6M

12

PC1077

PC1076

1U_0402_6.3V6K

PC1040

10U_0603_6.3V6M

PC1078

1U_0402_6.3V6K

+VDDC

12

PC1041

12

PC1044

12

VGA_Core output CAP (Including MLCC 43.9)

10U_0603_6.3V6M

12

PC1045

1U_0402_6.3V6K

12

PC1079

1U_0402_6.3V6K

12

PC1047

PC1046

1U_0402_6.3V6K

12

PC1049

PC1048

1U_0402_6.3V6K

1

4 9

1

12

PC1051

PC1050

1U_0402_6.3V6K

12

PC1060

PC1069

1U_0402_6.3V6K

A A

5

4

1U_0402_6.3V6K

12

PC1053

PC1052

1U_0402_6.3V6K

12

PC1061

PC1068

1U_0402_6.3V6K

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

PC1054

PC1055

1U_0402_6.3V6K

12

PC1063

PC1062

1U_0402_6.3V6K

2012/09/ 27

3

12

PC1056

PC1057

1U_0402_6.3V6K

12

PC1064

PC1065

1U_0402_6.3V6K

12

PC1058

PC1059

1U_0402_6.3V6K

12

PC1067

PC1066

1U_0402_6.3V6K

Compal Secret Data

Deciphered Date

12

Compal Electronics, Inc.

Title

Size D ocument Number Rev

A3

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR DECOUPLING

ZRMAE

1

of

38 40Monday, May 06, 2013

of

38 40Monday, May 06, 2013

of

38 40Monday, May 06, 2013

0.1

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 1

for PWR

Reason for change PG# Modify List Date PhaseItem

D D

C C

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2013/05/15 2015/09/27

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PIR (PWR)

ZRMAE

39 40Monday, May 06, 2013

1

0.1

of

5

4

3

2

1

HW PIR (Product Improve Record)

VNKAE LA-A551P SCHEMATIC CHANGE LIST REVISION CHANGE: 0.1 TO 0.2

----------------------------------------------------------------------------------------------------------------------------------Item Page Date Request Solution

-----------------------------------------------------------------------------------------------------------------------------------

D D

C C

B B

A A

Title

HW PIR

Size Docum ent Number Rev

LA-A551P 0 .1

B

LA-A551P 0 .1

B

LA-A551P 0 .1

B

Date: Sheet of

5

4

3

2

Date: Sheet of

40 40Monday, May 06, 2013

1

Compal LA-A551P ZRMAE 10AN, Satellite M50DT, Satellite U50D, LA-A551P ZEMAE Juno 10AN, LA-A551P Iakros 10AN Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual