Compal LA-A551P ZRMAE 10AN, Satellite M50DT, Satellite U50D, LA-A551P ZEMAE Juno 10AN, LA-A551P Iakros 10AN Schematic

A

1 1

B

C

D

E

ZRMAE/ZEMAE

2 2

LA-A551P SchematicREV

3 3

Juno/Iakros 10AN/10ANG

0.1

AMD KABINI Quad Core 25W for UMA+DIS AMD KABINI Quad Core 15W

2013-04-24 Rev 0.1

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/15 2015/09/27

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

LA-A551P

1 40Monday, May 06, 2013

E

0.1

of

A

B

C

D

E

AMD GPU

page 20

PCIe Gen2 X4

5Gbps

DP0 X4

DP1 X4

AMD FT3 APU

Jaguar Core

Integrated Yangtze FCH

AMD Sun Pro M2, 64bit with 1GB DDR3(2Gbit)

1 1

AMD Sun Pro M2, 64bit with 2GB DDR3(4Gbit)

page 12-19

LVDS/eDP Conn

HDMI Conn

Memory BUS(DDRIII)

Single Channel

1.5V DDRIII 1333/1600 MT/s APU SMBUS

USB 2.0 Left

USB port 0

page 25

USB 2.0

5V 480Mbps

USB Right1

USB2.0 port 8

page 24

200pin DDRIII-SO-DIMM X2

BANK 0, 1, 2, 3

TouchScreen

USB port 4

page 20

USB Right2

USB2.0 port 9

page 24

page 10,11

CardReader

USB port 2

page 20

Int. Camera

USB port 3

page 20

PCIeMini Card For BT

USB port 1

page 23

(1.4b & 3D)

page 21

2 2

PCIe Gen1 X1

PCIeMini Card For WLAN

PCIe port 2

page 23

RTL8106E 10/100M

PCIe port 1

3 3

page 25

APU SMBUS

2.5bps

PCIe Gen1 X1

2.5bps

BGA 769-balls

USB 3.0

5V 5Gbps

SATA Gen3 port 0

5V 6Gbps

HD Audio

3.3V 24MHz

USB Right1

USB3.0 port 0

page 24

SATA HDD

SATA port 0

page 23

HDA Codec

ALC259

page 26

USB Right2

USB3.0 port 1

page 24

SPK Conn

page 28

JHP

page 25

SPI BUS

3.3V 33HZ

LPC Bus

RTC CKT.

page 9

SPI ROM (4MB)

page 7

Touch Screen Control/B

page 20

DC/DC Interface CKT.

page 31

4 4

Sub Boards

APU SMBus

ENE KB9012

Touch Pad

3.3V 33 MHz

EC SMBus

Int.KBD

page 28page 28

page 27

CardReader RTS5176(Port 3)

Power Circuit DC/DC

page 29~38

Power On/Off CKT & Power/B

page 28

A

+USB (Port 2)+Audio Combo jack

page 25

Touch pad/LED B

page 28

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/15 2015/09/27

C

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Block Diagram

LA-A551P

2 40Monday, May 06, 2013

E

of

0.1

5

4

3

2

1

DESIGN CURRENT 0.15A

B+

D D

I

peak=12A, Imax=8.4A, Iocp min=14A

SUSP#

N-CHANNEL

TPS22966

ODD_PWR

N-CHANNEL

TPS22966

DESIGN CURRENT 0A

DESIGN CURRENT 4A

DESIGN CURRENT 2A

+3VL +5VL

+5VALW

+5VS

+5VS_ODD

RT8243A

Ipeak=8A, Imax=5.6A, Iocp min=10A

3VALW_APU_PWREN

P-CHANNEL

AO-3413

1.8_0.95VALW_PWREN

C C

SUSP#

N-CHANNEL

TPS22966

SY8032

P-CHANNEL

AO-3413

DGPU_PWR_EN

P-CHANNEL

AO-3413

LCD_ENVDD

DESIGN CURRENT 330mA

DESIGN CURRENT 2.5A

SUSP#

N-CHANNEL

TPS22966

VGA_PWRGD

N-CHANNEL

TPS22966

DESIGN CURRENT 4A

DESIGN CURRENT 1.5A

DESIGN CURRENT 60mA

+3VALW

+3VALW_APU

+3V_LAN

+1.8VALW

+1.8VS

+1.8VGS

+3VS

+LCD_VDD

+3VS_DGPU

B B

SYSON

RT8207M

1.8_0.95VALW_PWREN

Ipeak=12A, Imax=8.4A, Iocp min=13.8A

VGA_PWRGD

N-CHANNEL

TPS22966

SUSP#

DESIGN CURRENT 2A

DESIGN CURRENT 1.5A

Ipeak=2.5A, Imax=1.75A, Iocp min=16A

SY8208D

VR_ON

A A

RT8880A

GPU_DPRSLPVR

0.95VS_PWREN#

N-CHANNEL

FDS6676

Ipeak=15A, Imax=10.5A, Iocp min=30A

Ipeak=13A, Imax=9.1A, Iocp min=30A

DESIGN CURRENT 2A

Ipeak=21A, Imax=14.7A, Iocp min=40A

ISL62881

5

4

+3V_WLAN

+1.5V

+1.5VGS

+0.75VS

+0.95VALW

+0.95VS

APU_CORE

APU_CORE_NB

VGA_CORE

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2013/05/15 2015/09/27

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Power Tree

LA-A551P

of

3 40Monday, May 06, 2013

of

3 40Monday, May 06, 2013

of

1

3 40Monday, May 06, 2013

0.1

A

B

C

D

E

Voltage Rails

State

S0

S1

S3

S5 S4/AC

power plane

1 1

2 2

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

( O MEANS ON X MEANS OFF )

+RTCVCC

O

B+

O

X

+5VL

+3VL

O

X

+5VALW

+3VALW

+1.8VALW

+0.95VALW

+VSB

O

X

+1.5V

+5VS

+3VS

+0.95VS

+1.8VS

+1.5VS

+0.75VS

+APU_CORE

+APU_CORE_NB

O

X X

X

X X

UMA

OO

X

BTO Option Table

Function

PU A4-5000

description

explain

BTO

Function

description

explain

BTO

Function

description

explain

BTO

Function

description

explain

BTO

C

1

5W 4C 25W 4C

A4R1@ A6R1@

GPU

Sun-Pro M2

VGA

VGA@

LAN

8106E

106E@

8

E

MI@ @EMI@ ESD@ @ESD@ @RF@

APU

CPU A6-5200

EC

9012

9012@

S&C

TI solution

TPS2546

2546@

EMI/ESD/RF part

885

w/

885@

TPS2544

2544@

LVDS-eDP

w/ EMI

885_EMI@

LVDS eDP

LVDS@ IEDP@

Size

14" 15" W/O EMI Touch

14@

15@

CAM@

Codec

ALC259

259@

Camera & Mic

CAM@EMI@ @CAM@EMI@

Touch Screen

W/ Touch

Touch_EMI@ @Touch_EMI@

KB Light

KBL@

APU SM Bus Address (SCL0/SDA0)

3 3

+3VS DDR SO-DIMM A A0H 1010 0000 b +3VS DDR SO-DIMM B A2H 1010 0010 b +3VS WLAN

EC SM Bus1 Address

+3VL Smart Battery 16H 0001 0110 b +3VL Charger 12H 0001 0010 b

4 4

Device Address

A

HEX AddressDevicePower

HEX Address

HEX

EC SM Bus2 Address

+3VS VGA thermal 82H 1000 0010 b

DevicePowerPower

+3VS APU thermal 98H 1001 1000 b

B

HEX Address

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

3 LOW LOW

G

Issued Date

SIGNAL

SLP_S3# SLP_S5#

HIGHHIGH

HIGH HIGH

LOW

HIGH

LOW

HIGH

LOWLOW

Compal Secret Data

2013/05/15 2015/09/27

C

Compal Secret Data

Deciphered Date

APU POWER SEQUENCE

G-A

G-B

G-C

G-D

G-E

+RTC

3VALW_APU_PWREN

+3VALW_APU

1.8_0.95VALW_PWREN

+1.8VALW

+0.95VALW

SYSON

+1.5V

SUSP#

+3VS

+1.8VS

+1.5VS

+0.95VS

VR_ON

+APU_CORE

+APU_CORE_NB

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Notes List

LA-A551P

4 40Monday, May 06, 2013

E

of

0.1

5

4

3

2

1

DDR_AB_DQS[0..7]<10,11>

DDR_AB_DQS#[0..7]<10,11>

DDR_AB_MA[0..15]<10,11>

D D

DDR_AB_BS0<10,11> DDR_AB_BS1<10,11> DDR_AB_BS2<10,11> DDR_AB_DM[0..7]<10,11>

C C

DDR_A_CLK0<10> DDR_A_CLK0#<10> DDR_A_CLK1<10> DDR_A_CLK1#<10> DDR_B_CLK0<11> DDR_B_CLK0#<11> DDR_B_CLK1<11> DDR_B_CLK1#<11>

MEM_MAB_RST#<10,11> MEM_MAB_EVENT#<10,11>

DDR_A_CKE0<10> DDR_A_CKE1<10> DDR_B_CKE0<11>

B B

1 2

CC94

DDR_B_CKE1<11>

DDR_A_ODT0<10> DDR_A_ODT1<10> DDR_B_ODT0<11> DDR_B_ODT1<11>

DDR_A_SCS0#<10> DDR_A_SCS1#<10> DDR_B_SCS0#<11> DDR_B_SCS1#<11>

DDR_AB_RAS#<10,11> DDR_AB_CAS#<10,11> DDR_AB_WE#<10,11>

ESD@

180P_0402_50V8J

MEM_MAB_RST#

close to APU

+1.5V

MEMORY Reference Voltage (Cap follower checklist 1.02)

RC6

1K_0402_1%

A A

1K_0402_1%

RC8

1 2

2

CC17

CC17 1U_0402_6.3V6K

1U_0402_6.3V6K

1

1 2

DDR_AB_MA0 DDR_AB_MA1 DDR_AB_MA2 DDR_AB_MA3 DDR_AB_MA4 DDR_AB_MA5 DDR_AB_MA6 DDR_AB_MA7 DDR_AB_MA8 DDR_AB_MA9 DDR_AB_MA10 DDR_AB_MA11 DDR_AB_MA12 DDR_AB_MA13 DDR_AB_MA14 DDR_AB_MA15

DDR_AB_BS0 DDR_AB_BS1 DDR_AB_BS2

DDR_AB_DM0 DDR_AB_DM1 DDR_AB_DM2 DDR_AB_DM3 DDR_AB_DM4 DDR_AB_DM5 DDR_AB_DM6 DDR_AB_DM7

DDR_AB_DQS0 DDR_AB_DQS#0 DDR_AB_DQS1 DDR_AB_DQS#1 DDR_AB_DQS2 DDR_AB_DQS#2 DDR_AB_DQS3 DDR_AB_DQS#3 DDR_AB_DQS4 DDR_AB_DQS#4 DDR_AB_DQS5 DDR_AB_DQS#5 DDR_AB_DQS6 DDR_AB_DQS#6 DDR_AB_DQS7 DDR_AB_DQS#7

DDR_A_CLK0 DDR_A_CLK0# DDR_A_CLK1 DDR_A_CLK1# DDR_B_CLK0 DDR_B_CLK0# DDR_B_CLK1 DDR_B_CLK1#

MEM_MAB_RST# MEM_MAB_EVENT#

DDR_A_CKE0 DDR_A_CKE1 DDR_B_CKE0 DDR_B_CKE1

DDR_A_ODT0 DDR_A_ODT1 DDR_B_ODT0 DDR_B_ODT1

DDR_A_SCS0# DDR_A_SCS1# DDR_B_SCS0# DDR_B_SCS1#

DDR_AB_RAS# DDR_AB_CAS# DDR_AB_WE#

+MEM_VREF

remove from CRB_ver0C Check List 1.02

15mil

+MEM_VREF MEM_MAB_EVENT#

2

CC18

0.1U_0402_16V7K

1

UC1A

AG38

M_ADD0

W35

M_ADD1

W38

M_ADD2

W34

M_ADD3

U38

M_ADD4

U37

M_ADD5

U34

M_ADD6

R35

M_ADD7

R38

M_ADD8

N38

M_ADD9

AG34

M_ADD10

R34

M_ADD11

N37

M_ADD12

AN34

M_ADD13

L38

M_ADD14

L35

M_ADD15

AJ38

M_BANK0

AG35

M_BANK1

N34

M_BANK2

B32

M_DM0

B38

M_DM1

G40

M_DM2

N41

M_DM3

AG40

M_DM4

AN41

M_DM5

AY40

M_DM6

AY34

M_DM7

Y40

M_DM8

B33

M_DQS_H0

A33

M_DQS_L0

B40

M_DQS_H1

A40

M_DQS_L1

H41

M_DQS_H2

H40

M_DQS_L2

P41

M_DQS_H3

P40

M_DQS_L3

AH41

M_DQS_H4

AH40

M_DQS_L4

AP41

M_DQS_H5

AP40

M_DQS_L5

BA40

M_DQS_H6

AY41

M_DQS_L6

AY33

M_DQS_H7

BA34

M_DQS_L7

AA40

M_DQS_H8

Y41

M_DQS_L8

AC35

M_CLK_H0

AC34

M_CLK_L0

AA34

M_CLK_H1

AA32

M_CLK_L1

AE38

M_CLK_H2

AE37

M_CLK_L2

AA37

M_CLK_H3

AA38

M_CLK_L3

G38

M_RESET_L

AE34

M_EVENT_L

L34

M0_CKE0

J38

M0_CKE1

J37

M1_CKE0

J34

M1_CKE1

AN38

M0_ODT0

AU38

M0_ODT1

AN37

M1_ODT0

AR37

M1_ODT1

AJ34

M0_CS_L0

AR38

M0_CS_L1

AL38

M1_CS_L0

AN35

M1_CS_L1

AJ37

M_RAS_L

AL34

M_CAS_L

AL35

M_WE_L

AD40

M_VREF

AC38

M_VREFDQ

FT3_BGA769 @

MEMORY

FT3 REV 0.51

M_DATA0

M_DATA1

M_DATA2

M_DATA3

M_DATA4

M_DATA5

M_DATA6

M_DATA7

M_DATA8

M_DATA9

M_DATA10

M_DATA11

M_DATA12

M_DATA13

M_DATA14

M_DATA15

M_DATA16

M_DATA17

M_DATA18

M_DATA19

M_DATA20

M_DATA21

M_DATA22

M_DATA23

M_DATA24

M_DATA25

M_DATA26

M_DATA27

M_DATA28

M_DATA29

M_DATA30

M_DATA31

M_DATA32

M_DATA33

M_DATA34

M_DATA35

M_DATA36

M_DATA37

M_DATA38

M_DATA39

M_DATA40

M_DATA41

M_DATA42

M_DATA43

M_DATA44

M_DATA45

M_DATA46

M_DATA47

M_DATA48

M_DATA49

M_DATA50

M_DATA51

M_DATA52

M_DATA53

M_DATA54

M_DATA55

M_DATA56

M_DATA57

M_DATA58

M_DATA59

M_DATA60

M_DATA61

M_DATA62

M_DATA63

M_CHECK0

M_CHECK1

M_CHECK2

M_CHECK3

M_CHECK4

M_CHECK5

M_CHECK6

M_CHECK7

M_ZVDDIO_MEM_S

B30 A32 B35 A36 B29 A30 A34 B34

B37 A38 D40 D41 B36 A37 B41 C40

F40 F41 K40 K41 E40 E41 J40 J41

M41 N40 T41 U40 L40 M40 R40 T40

AF40 AF41 AK40 AK41 AE40 AE41 AJ40 AJ41

AM41 AN40 AT41 AU40 AL40 AM40 AR40 AT40

AV41 AW4 0 BA38 AY37 AU41 AV40 AY39 AY38

BA36 AY35 BA32 AY31 BA37 AY36 BA33 AY32

V41 W40 AB40 AC40 U41 V40 AA41 AB41

AD41

DDR_AB_D0 DDR_AB_D1 DDR_AB_D2 DDR_AB_D3 DDR_AB_D4 DDR_AB_D5 DDR_AB_D6 DDR_AB_D7

DDR_AB_D8 DDR_AB_D9 DDR_AB_D10 DDR_AB_D11 DDR_AB_D12 DDR_AB_D13 DDR_AB_D14 DDR_AB_D15

DDR_AB_D16 DDR_AB_D17 DDR_AB_D18 DDR_AB_D19 DDR_AB_D20 DDR_AB_D21 DDR_AB_D22 DDR_AB_D23

DDR_AB_D24 DDR_AB_D25 DDR_AB_D26 DDR_AB_D27 DDR_AB_D28 DDR_AB_D29 DDR_AB_D30 DDR_AB_D31

DDR_AB_D32 DDR_AB_D33 DDR_AB_D34 DDR_AB_D35 DDR_AB_D36 DDR_AB_D37 DDR_AB_D38 DDR_AB_D39

DDR_AB_D40 DDR_AB_D41 DDR_AB_D42 DDR_AB_D43 DDR_AB_D44 DDR_AB_D45 DDR_AB_D46 DDR_AB_D47

DDR_AB_D48 DDR_AB_D49 DDR_AB_D50 DDR_AB_D51 DDR_AB_D52 DDR_AB_D53 DDR_AB_D54 DDR_AB_D55

DDR_AB_D56 DDR_AB_D57 DDR_AB_D58 DDR_AB_D59 DDR_AB_D60 DDR_AB_D61 DDR_AB_D62 DDR_AB_D63

M_ZVDDIO

1 2

VENT# pull high

E

Close to APU AD40

5

4

DDR_AB_D[0..63] <10,11>

LAN

WLAN

PCIE_LANTX_ARX_N1<22>

PCIE_WLANTX_ARX_P2<23> PCIE_WLANTX_ARX_N2<23>

+0.95VS_APU_GFX +0.95VS_APU_GFX

PCIE_GTX_C_ARX_P0<12> PCIE_GTX_C_ARX_N0<12>

PCIE_GTX_C_ARX_P1<12> PCIE_GTX_C_ARX_N1<12>

VGA

PCIE_GTX_C_ARX_P2<12> PCIE_GTX_C_ARX_N2<12>

PCIE_GTX_C_ARX_P3<12> PCIE_GTX_C_ARX_N3<12>

+1.5V

RC439.2_0402_1% RC439.2_0402_1%

+1.5V

1 2

RC7 1K_0402_5%RC7 1K_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

RC1 1.69K_0402_1%RC1 1.69K_0402_1%

3

P_TX_ZVDD P_RX_ZVDD

2013/05/15 2015/09/27

UC1B

R10

P_GPP_RXP0

R8

P_GPP_RXN0

R5

P_GPP_RXP1

R4

P_GPP_RXN1

N5

P_GPP_RXP2

N4

P_GPP_RXN2

N10

P_GPP_RXP3

N8

P_GPP_RXN3

W8

P_TX_ZVDD_095

L5

P_GFX_RXP0

L4

P_GFX_RXN0

J5

P_GFX_RXP1

J4

P_GFX_RXN1

G5

P_GFX_RXP2

G4

P_GFX_RXN2

D7

P_GFX_RXP3

E7

P_GFX_RXN3

FT3_BGA769

Compal Secret Data

PCIE

L2

P_GPP_TXP0

L1

P_GPP_TXN0

K2

PCIE_ATX_LANRX_P1

K1

PCIE_ATX_LANRX_N1

J2

PCIE_ATX_WLANRX_P2

J1

PCIE_ATX_WLANRX_N2

H2 H1

W7

G2

PCIE_ATX_GRX_P0

G1

PCIE_ATX_GRX_N0

F2

PCIE_ATX_GRX_P1

F1

PCIE_ATX_GRX_N1

E2

PCIE_ATX_GRX_P2

E1

PCIE_ATX_GRX_N2

D2

PCIE_ATX_GRX_P3

D1

PCIE_ATX_GRX_N3

@

FT3 REV 0.51

GRAPHICS GPP

P_GPP_TXP1

P_GPP_TXN1

P_GPP_TXP2

P_GPP_TXN2

P_GPP_TXP3

P_GPP_TXN3

P_RX_ZVDD_095

P_GFX_TXP0

P_GFX_TXN0

P_GFX_TXP1

P_GFX_TXN1

P_GFX_TXP2

P_GFX_TXN2

P_GFX_TXP3

P_GFX_TXN3

FAN Control Circuit

+5VS

1 2

R2 0_0603_5%R2 0_0603_5%

1A

DFAN1<27>

Deciphered Date

+FAN1

0mil

1

12

C27

10U_0805_6.3V6M

SA00002XA00 EOL change use SA00003UO00 2

nd source SA00005JO00

2

U4

1

EN

2

VIN

3

VOUT

4

VSET

P2793BB0_SO8

1 2

CC3 0.1U_0402_16V7KCC3 0.1U_0402_16V7K

1 2

CC4 0.1U_0402_16V7KCC4 0.1U_0402_16V7K

1 2

CC1 0.1U_0402_16V7KCC1 0.1U_0402_16V7K

1 2

CC2 0.1U_0402_16V7KCC2 0.1U_0402_16V7K

12

RC2 1K_0402_1%RC2 1K_0402_1%

0.1U_0402_16V7KVGA@

CC5

CC5 CC6

CC6

CC7

CC7 CC8

CC8

CC9

CC9 CC10

CC10

CC11

CC11 CC12

CC12

1 2 1 2

VGA@

0.1U_0402_16V7KVGA@

0.1U_0402_16V7K

0.1U_0402_16V7KVGA@

0.1U_0402_16V7K

0.1U_0402_16V7KVGA@

+FAN1

2

12

C4

@C4

C3

10U_0805_6.3V6M

8

GND

7

GND

6

GND

5

GND

Title

Size Document Number Rev

Date: Sheet

@

1000P_0402_50V7K

1

FT3 DISP/MISC/HDT

LA-A551P

Monday, May 06, 2013

PCIE_ATX_C_LANRX_P1 <22>PCIE_LANTX_ARX_P1<22> PCIE_ATX_C_LANRX_N1 <22>

PCIE_ATX_C_WLANRX_P2 <23> PCIE_ATX_C_WLANRX_N2 <23>

JFAN

1

2

3

4

GND

5

GND

CVILU_CI4403M1HRT-NH

R1 10K_0402_5%R1 10K_0402_5%

12

FAN_SPEED1

1

C1

0.01U_0402_25V7K

@

2

1

PCIE_ATX_C_GRX_P0 <12> PCIE_ATX_C_GRX_N0 <12>

PCIE_ATX_C_GRX_P1 <12> PCIE_ATX_C_GRX_N1 <12>

PCIE_ATX_C_GRX_P2 <12> PCIE_ATX_C_GRX_N2 <12>

PCIE_ATX_C_GRX_P3 <12> PCIE_ATX_C_GRX_N3 <12>

Conn@

+3VS

LAN

WLAN

FAN_SPEED1 <27>

of

5 40

of

5 40

of

5 40

VGA

0.1

5

EDP_LCD_TXOUT0+_R

EDP_LCD_TXOUT0-_R

APU_HDMI_TX2+<21>

D D

HDMI

EDP use 2 Lane for FHD

EDP Cap co-lay

CC107

0.1U_0402_16V7K

SVT,SVC,SVD, APU_PWRGD is 1.8V Output

ROCHOT is 3.3V Input

P

+3VS

C C

CC108

EDP@

RC26 1K_0402_5%RC26 1K_0402_5%

EDP@

0.1U_0402_16V7K

12

+1.8VS

1 2

RC32 300_0402_5%RC32 300_0402_5%

1 2

RC34 300_0402_5%RC34 300_0402_5%

EDP/LVDS

APU_PROCHOT#

APU_RST#

APU_PWRGD

APU_HDMI_TX2-<21>

APU_HDMI_TX1+<21> APU_HDMI_TX1-<21>

APU_HDMI_TX0+<21> APU_HDMI_TX0-<21>

APU_HDMI_CLK+<21> APU_HDMI_CLK-<21>

EDP_LCD_TXOUT2+_R<20>

EDP_LCD_TXOUT2-_R<20>

EDP_LCD_TXOUT1+_R<20>

EDP_LCD_TXOUT1-_R<20>

EDP_LCD_TXOUT0+_R<20>

EDP_LCD_TXOUT0-_R<20>

LCD_TXCLK+<20> LCD_TXCLK-<20>

APU_SVT<36> APU_SVC<36> APU_SVD<36>

EC_SMB_CK2<13,27> EC_SMB_DA2<13,27>

APU_PWRGD<36>

APU_PROCHOT#<27,36>

+1.8VS

RPC2

1 8 2 7

+3VS

3 6 4 5

1K_8P4R_5%

RC28

B B

ESD@

1 2

CC99 1000P_0402_50V7K

ESD@

1 2

CC93

180P_0402_50V8J

DP_STEREOSYNC

APU_ALERT#

12

1K_0402_5%

APU_RST#

APU_PWRGD

APU_TDI APU_TRST#

APU_DBREQ#

APU_VDDNB_SEN_H<36> APU_VDD_SEN_H<36>

APU_VDD_SEN_L<36>

close to APU

DC1

12

APU_PROCHOT#

@ESD@

SCV00001K00

close to APU

4

0.1U_0402_16V7K

1 2

CC109

EDP@CC109

EDP@

0.1U_0402_16V7K

1 2

CC110

EDP@CC110

EDP@

LVDS@

1 2

RC75 0_0402_5%

1 2

RC76 0_0402_5%LVDS@RC76 0_0402_5%LVDS@

1 2

CC107 0_0402_5%LVDS@CC107 0_0402_5%LVDS@

1 2

CC108 0_0402_5%LVDS@CC108 0_0402_5%LVDS@

LVDS@

1 2

RC77 0_0402_5%

1 2

RC78 0_0402_5%LVDS@RC78 0_0402_5%LVDS@

TP@

T28

TP@

T32

TP@

T37

TP@

TP@ TP@

TP@

EDP_LCD_TXOUT2+ EDP_LCD_TXOUT2-

EDP_LCD_TXOUT1+ EDP_LCD_TXOUT1-

EDP_LCD_TXOUT0+ EDP_LCD_TXOUT0-

APU_PROCHOT#

T15

T18

T18 T19

T19

EDP_LCD_TXOUT2+

EDP_LCD_TXOUT2-

LCD_TXCLK+ LCD_TXCLK-

APU_RST#

APU_PWRGD

APU_ALERT#

APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBRDY APU_DBREQ#

VDDMEM_SENSE

VDD095_FB_H VDD095_FB_L

AV33 AU33

3

UC1C

DISPLAY/SVI2/JTAG/TEST

TDP1_TXP0

TDP1_TXN0

TDP1_TXP1

TDP1_TXN1

TDP1_TXP2

TDP1_TXN2

TDP1_TXP3

TDP1_TXN3

LTDP0_TXP0

LTDP0_TXN0

LTDP0_TXP1

LTDP0_TXN1

LTDP0_TXP2

LTDP0_TXN2

LTDP0_TXP3

LTDP0_TXN3

DISP_CLKIN_H

DISP_CLKIN_L

SVT

SVC

SVD

SIC

SID

APU_RST_L

LDT_RST_L

APU_PWROK

LDT_PWROK

PROCHOT_L

ALERT_L

TDI

TDO

TCK

TMS

TRST_L

DBRDY

DBREQ_L

VDDCR_NB_SENSE

VDDCR_CPU_SENSE

VDDIO_MEM_S_SENSE

VSS_SENSE

VDD_095_FB_H

VDD_095_FB_L

DISPLAY/SVI2/JTAG/TEST

DISPLAY

MISC

GIO_TSTDTM0_SERIALCLK

TEST

HDMI_EN/DP_STEREOSYNC

G31

G27

G23

A10 B10

A11 B11

A12 B12

K15 H15

D27 E29

B22 B21

B20 A20

B19 A19

A22 B18

D29 D31 D35 D33

B25 A25

D23

E25 E23

A9 B9

A4 B4

A5 B5

A6 B6

A7 B7

MISC

FT3 REV 0.51

FT3_BGA769 @

FT3 REV 0.51

DP_150_ZVSS

DP_2K_ZVSS

DP_BLON

DP_DIGON

DP_VARY_BL

TDP1_AUXP

TDP1_AUXN

TDP1_HPD

LTDP0_AUXP

LTDP0_AUXN

LTDP0_HPD

DAC_RED

DAC_GREEN

DAC_BLUE

DAC_HSYNC

DAC_VSYNC

DAC_SCL

DAC_SDA

DAC_ZVSS

THERMDA

THERMDC

DIECRACKMON

BP0

BP1

BP2

BP3

PLLTEST1

PLLTEST0

BYPASSCLK_H

BYPASSCLK_L

PLLCHRZ_H

PLLCHRZ_L

M_TEST

FREE_2

GIO_TSTDTM0_CLKINIT

USB_ATEST0

USB_ATEST1

M_ANALOGIN

M_ANALOGOUT

TMON_CAL

2

LCD_ENBKL : APU to EC to LCD

B16

DP_150_ZVSS

A21

DP_2K_ZVSS

B17

LCD_ENBKL

A17

LCD_ENVDD

A18

LCD_INT_PWM

D17

APU_HDMI_CLK

E17

APU_HDMI_DATA

H19

D15

EDP_LVDS_CLK_R

E15

EDP_LVDS_DATA_R

H17

EDP_LVDS_HPD

B14

1 2

RC13 150_0402_1%RC13 150_0402_1%

1 2

RC9 2K_0402_1%RC9 2K_0402_1%

1 2

CC101 0_0402_5%LVDS@CC101 0_0402_5%LVDS@

1 2

CC103 0_0402_5%LVDS@CC103 0_0402_5%LVDS@

LVDS_CLK&LVDS_DATA layout follow EDP AUX route 85 ohm

LCD_ENBKL <20,27> LCD_ENVDD <20> LCD_INT_PWM <20>

APU_HDMI_CLK <21> APU_HDMI_DATA <21>

HDMI_HPD <21>

EDP_LVDS_CLK <20> EDP_LVDS_DATA <20>

EDP_LVDS_HPD <20>

EDP/LVDS

HDMI

EDP/LVDS

A14

B15

G19

APU_CRT_HSYNC

E19

D19 D21

A16

DAC_ZVSS

H27

TEST4

H29

TEST5

D25 A27

TEST14

B27

TEST15

A26

TEST16

B26

TEST17

B28

TEST18

A28

TEST19

B24

TEST25_H

A24

TEST25_L

AV35

TEST28_H

AU35

TEST28_L

E33

TEST31

A29 H21

TEST36

H25

TEST37

AJ10

TEST42

AJ8

TEST43

R32

TEST39

N32

TEST40

AP29

TEST41

E21

DP_STEREOSYNC

DP_STEREOSYNC U

sed to align shutter glasses w ith the interleaved video frame

APU_HSYNC PU FOR INTERNAL(HDM I enable)

1 2

RC21 499_0402_1%RC21 499_0402_1%

TP@T1TP@

T1

TP@T2TP@

T2

TP@T3TP@

T3

TP@T4TP@

T4

TP@T5TP@

T5

TP@T6TP@

T6

TP@

T34

TP@

T35

route TEST25_H/L AND TEST28_H/ L differentially

TP@T7TP@

T7

TP@T8TP@

T8

TP@T9TP@

T9

TP@

T12

TP@

T13

TP@

T14

TP@

T16

TP@

T17

NOTE: DP_STEREOSYNC & APU_HSYN C PU FOR INTERNAL(HDMI enable), DP_STER EOSYNC & APU_HSYNC PD FOR CUSTOMER(HDMI disable)

EDP_LVDS_CLK_R

EDP_LVDS_DATA_R

HDMI DDC PU RES move

HDMI page

to

APU_CRT_HSYNC

EDP_LVDS_HPD

RC14 4.7K_0402_5%LVDS@RC14 4.7K_0402_5%LVDS@

RC15 4.7K_0402_5%LVDS@RC15 4.7K_0402_5%LVDS@

RC18 1K_0402_5%RC18 1K_0402_5%

RC45 100K_0402_5%

EDP Cap co-lay

CC103

CC101

0.1U_0402_16V7K

EDP_LVDS_HPD

LCD_ENBKL

LCD_INT_PWM

TEST25_L TEST36 TEST37

DP_STEREOSYNC

TEST36

TEST37

TEST25_H

APU_TMS

APU_TCK TEST19 TEST18

CC103

EDP@

0.1U_0402_16V7K

RC44 100K_0402_5%

RC19 100K_0402_5%RC19 100K_0402_5%

RC20 100K_0402_5%RC20 100K_0402_5%

RC35 510_0402_1%RC35 510_0402_1% RC37 1K_0402_5%@RC37 1K_0402_5%@ RC39 1K_0402_5%@RC39 1K_0402_5%@

RC36 1K_0402_5%@RC36 1K_0402_5%@

RC41 1K_0402_5%@RC41 1K_0402_5%@ RC46 1K_0402_5%@RC46 1K_0402_5%@

RC43 510_0402_1%RC43 510_0402_1%

1 8 2 7 3 6 4 5

1

1 2

@

EDP@

1 2 1 2 1 2

1 2

1 2 1 2

1 2

RPC4

1K_8P4R_5%

+3VS

12

+1.8VS

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/15 2015/09/27

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

FT3 DISP/MISC/HDT

LA-A551P

Monday, May 06, 2013

0.1

of

6 40

of

6 40

of

6 40

1

5

SATA_ATX_DRX_P0<23>

GA

SATA_ATX_DRX_N0<23>

SATA_DTX_C_ARX_N0<23> SATA_DTX_C_ARX_P0<23>

RC58 1K_0402_1%RC58 1K_0402_1%

+0.95VS

CLK_PCIE_VGA<12>

CLK_PCIE_VGA#<12>

CLK_LAN<22> CLK_LAN#<22>

CLK_WLAN<23> CLK_WLAN#<23>

CLK_PCI_EC<27,8> CLK_PCI_DDR<8>

LPC_AD0<27> LPC_AD1<27> LPC_AD2<27> LPC_AD3<27>

LPC_FRAME#<27,8>

SERIRQ<27>

RC59 1K_0402_1%RC59 1K_0402_1%

SATA HDD

D D

V

LAN WLAN

C C

EC

4

12 12

EMI@

1 2

RC62 22_0402_5%

1 2

RC63 0_0402_5%EMI@RC63 0_0402_5%EMI@

SATA_ZVSS SATA_ZVSS_095

T20

TP@

3

UC1E

BA14

SATA_TX0P

AY14

SATA_TX0N

BA16

SATA_RX0N

AY16

SATA_RX0P

AY19

SATA_TX1P

BA19

SATA_TX1N

AY17

SATA_RX1N

BA17

SATA_RX1P

AR19

SATA_ZVSS

AP19

SATA_ZVDD_095

BA30

SATA_ACT

48M_X1

48M_X2

LPC_CLK0 LPC_CLK1 APU_SPI_CLK

SATA_ACT_L/GPIO67

AY12

SATA_X1

BA12

SATA_X2

U4

GFX_CLKP

U5

GFX_CLKN

AC8

GPP_CLK0P

AC10

GPP_CLK0N

AE4

GPP_CLK1P

AE5

GPP_CLK1N

AC4

GPP_CLK2P

AC5

GPP_CLK2N

AA5

GPP_CLK3P

AA4

GPP_CLK3N

AP13

X14M_25M_48M_OSC

N2

X48M_X1

N1

X48M_X2

AY2

LPCCLK0

AW2

LPCCLK1

AT2

LAD0

AT1

LAD1

AR2

LAD2

AR1

LAD3

AP2

LFRAME_L

AP1

LDRQ0_L

AV29

SERIRQ/GPIO48

AP25

LPC_CLKRUN_L

AV2

LPC_PD_L/GEVENT5_L/SPI_TPM_CS_L

FT3_BGA769 @

CLK/SATA/USB/SPI/LPC

SATACLK

LPC

FT3 REV 0.51

USBCLK/14M_25M_48M_OSC

USB_ZVSS

USB_HSD0P

USB_HSD0N

USB_HSD1P

USB_HSD1N

USB_HSD2P

USB_HSD2N

USB_HSD3P

USB_HSD3N

USB_HSD4P

USB_HSD4N

USB_HSD5P

USB_HSD5N

USB_HSD6P

USB_HSD6N

USBSPI

USB_HSD7P

USB_HSD7N

USB_HSD8P

USB_HSD8N

USB_HSD9P

USB_HSD9N

USB_SS_ZVSS

USB_SS_ZVDD_095_USB3_DUAL

USB_SS_0TXP

USB_SS_0TXN

USB_SS_0RXP

USB_SS_0RXN

USB_SS_1TXP

USB_SS_1TXN

USB_SS_1RXP

USB_SS_1RXN

SPI_CLK/GPIO162

SPI_CS1_L/GPIO165

SPI_CS2_L/GPIO166

SPI_DO/GPIO163

SPI_DI/GPIO164

SPI_HOLD_L/GEVENT9_L

SPI_WP_L/GPIO161

W4

AG4

AL4 AL5

AJ4 AJ5

AG7 AG8

AG1 AG2

AF1 AF2

AE1 AE2

AD1 AD2

AC1 AC2

AB1 AB2

AA1 AA2

AE10 AE8

T2 T1

V2 V1

R1 R2

W1 W2

AU7 AW9 AR4 AR11 AR7 AU11 AU9

USB_ZVSS

USBSS_ZVSS USBSS_ZVDD

APU_SPI_CS1# APU_SPI_CS2# APU_SPI_MOSI APU_SPI_MISO

APU_SPI_WP#

2

1 2

RC57 11.8K_0402_1%RC57 11.8K_0402_1%

1 2

RC60 1K_0402_1%RC60 1K_0402_1%

1 2

RC61 1K_0402_1%RC61 1K_0402_1%

EMI@

1 2

RC130 0_0402_5%

T21

TP@

T22

TP@

USB20_P0 <25> USB20_N0 <25>

USB20_P1 <23> USB20_N1 <23>

USB20_P2 <25> USB20_N2 <25>

USB20_P3 <20> USB20_N3 <20>

USB20_P4 <20> USB20_N4 <20>

USB20_P8 <24> USB20_N8 <24>

USB20_P9 <24> USB20_N9 <24>

USB30_TX0P <24> USB30_TX0N <24>

USB30_RX0P <24> USB30_RX0N <24>

USB30_TX1P <24> USB30_TX1N <24>

USB30_RX1P <24> USB30_RX1N <24>

APU_SPI_CLK_R

RC10

10_0402_5%

@EMI@

CC13

10P_0402_50V8J

@EMI@

1

USB2.0-Left1 (Debug Port)

WLAN (BT) Cardreader Int. Camera

Touch Screen

USB2.0-Right1

USB2.0-Right2

+0.95VALW

USB3.0-Right1

USB3.0-Right2

12

2

1

B B

48KMHz CRYSTAL

48M_X2

1

4

1

4

1

2

48M_X1

CC23

4.7P_0402_50V8J

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/15 2015/09/27

3

RC64 1M_0402_5%RC64 1M_0402_5%

2

3

YC1

YC1 48MHZ_8PF_X3S048000D81H-W

48MHZ_8PF_X3S048000D81H-W

1

CC22

4.7P_0402_50V8J

2

A A

5

SPI ROM

EC_SPIDO<27>

EC_SPIDI<27> EC_SPICLK<27> EC_SPICS#<27>

1 2

RC66 10K_0402_5%RC66 10K_0402_5%

+3VALW_APU

Socket: SP07000F500/SP07000H900 Please place UC5 close to UC1 APU,

4MB ROM P/N: SA00004LI00

Compal Secret Data

Deciphered Date

885@

1 2

RC101 33_0402_5%

885@

1 2

RC102 33_0402_5%

885_EMI@

1 2

RC121 33_0402_5%

885@

1 2

RC124 33_0402_5%

2

4M Byte

UC5

APU_SPI_CLK_R

APU_SPI_CS1#

5

6

1

7

3

8

2

CC25

0.1U_0402_16V4Z

1

UC5

SI

SCLK

CS

HOLD

WP

VCC

MX25L3205DM2I-12G SO8

GND

2

APU_SPI_MISOAPU_SPI_MOSI

SO

4

SW said ROM can change to 4MB

Title

Size Document Number Rev

Date: Sheet

FT3-SATA/CLK/USB/SPI/LPC

LA-A551P

Monday, May 06, 2013

1

of

7 40

of

7 40

of

7 40

0.1

Follow check list & ORB_0C

esign 10 ms RC delay circuit

d on +1.8-V S5 power rail.

EC_RSMRST#<27>

D D

5

DC2

CH751H-40PT_SOD323-2

21

+1.8VALW

2

CC29

ESD@

1 2

CC97

180P_0402_50V8J

RC71

47K_0402_5%

1 2

RSMRST#

1

1U_0402_6.3V6K

SYS_PWRGD

USB_OC#0 USB_OC#2 USB_CHG_OC#

AZ_BITCLK_HD

HDA_BITCLK

AZ_SDIN0_HD

CC30

1 2

CC31

1 2

1U_0402_6.3V6K

SLP_S3# SLP_S5#

10P_0402_50V8J

RC104

20M_0402_5%

10P_0402_50V8J

AZ_BITCLK_HD<26> AZ_SDOUT_HD<26>

AZ_SDIN0_HD<26>

AZ_SYNC_HD<26>

AZ_RST_HD#<26>

YC2

4

12

32.768KHZ_7PF_Q13MC1461000100

3

1

2

+1.8VALW

1 2

RC127 10K_0402_5%RC127 10K_0402_5%

+3VALW_APU

C C

SLP_S3#, SLP_S5# PU reserve

1 2

RC128 2.2K_0402_5%

@

1 2

RC129 2.2K_0402_5%

@

RPC5

1 8 2 7 3 6 4 5

100K_8P4R_5%

10K_0402_5%

RC23

RC23 RC25

RC25

CC15

RC96 10K_0402_5%@RC96 10K_0402_5%@ RC97 10K_0402_5%@RC97 10K_0402_5%@

10K_0402_5%

@EMI@

1 2

1 2 1 2

12

APU_PCIE_WAKE#

12

APU_GPIO174

10P_0402_50V8J

STRAP PINS

B B

PULL HIGH

BOOT FAIL TIMER

CLKGEN ENABLE

DEFAULT DEFAULT

PULL LOW

BOOT FAIL TIMER DISABLED

CLKGEN DISABLED

DEFAULT

12

@

RC107

RC107 10K_0402_5%

10K_0402_5%

CLK_PCI_EC<27,7> CLK_PCI_DDR<7>

A A

LPC_FRAME#<27,7>

GEVENT2 RTC_CLK

12

RC112

RC112 2K_0402_5%

2K_0402_5%

5

SPI ROM 1.8V SPI ROM

LPC ROM

12

RC108

RC108 10K_0402_5%

10K_0402_5%

12

@

RC113

RC113 2K_0402_5%

2K_0402_5%

12

RC106

RC106 10K_0402_5%

10K_0402_5%

@

RC111

RC111 2K_0402_5%

2K_0402_5%

3.3V SPI ROM

EFAULT

D

12

4

SYS_PWRGD

close to APU

PBTN_OUT#<27>

SYS_PWRGD<27>

APU_PCIE_WAKE#<22>

SLP_S3#<27> SLP_S5#<27>

KB_RST#<27> GATEA20<27> EC_SCI#<27> EC_SMI#<27>

SLP_CHG_CB0<24>

SLP_CHG_CB1<24>

LAN_EN<22>

CLKREQ_WLAN#<23>

CLKREQ_LAN#<22>

CLKREQ_PEG#<13>

USB_OC#0<24,27>

USB_CHG_OC#<24,27>

USB_OC#2<25,27>

EMI@

1 2

RC92 33_0402_5%

1 2

RC93 33_0402_5%RC93 33_0402_5%

1 2

RC98 33_0402_5%RC98 33_0402_5%

1 2

RC100 33_0402_5%RC100 33_0402_5%

32K_X1

32K_X2

NORMAL POWR UP/RESET TIMING

FAST POWER UP/RESET TIMING FOR SIMULATION

+3VALW_APU

12

@

RC109

RC109 10K_0402_5%

10K_0402_5%

RC114

RC114 2K_0402_5%

2K_0402_5%

RC110

RC110 10K_0402_5%

10K_0402_5%

12

@

RC115

RC115 2K_0402_5%

2K_0402_5%

4

LPC_RST#_R APU_PCIE_RST#_R

RSMRST#

SYS_PWRGD

APU_PCIE_WAKE#

SLP_S3# SLP_S5#

TEST0

T24TP@T24TP@

TEST1/TMS

T25TP@T25TP@

TEST2

T27TP@T27TP@

USB_OC#0 USB_CHG_OC#

USB_OC#2

HDA_BITCLK HDA_SDOUT AZ_SDIN0_HD

HDA_SYNC HDA_RST#

32K_X1

32K_X2

RTC_CLKCLK_PCI_EC CLK_PCI_DDR LPC_FRAME# GEVENT2

DEFAULT

3

UC1D

AY4

LPC_RST_L

AY9

PCIE_RST_L

AY5

RSMRST_L

BA8

PWR_BTN_L

AM19

PWR_GOOD

AY7

T23TP@T23TP@

SYS_RESET_L/GEVENT19_L

AW1 1

WAKE_L/GEVENT8_L

AY3

SLP_S3_L

BA5

SLP_S5_L

AU13

TEST0

AY10

TEST1/TMS

AY6

TEST2

AR23

KBRST_L

AR31

GA20IN/GEVENT0_L

AN5

LPC_PME_L/GEVENT3_L

AL7

LPC_SMI_L/GEVENT23_L

AP15

AC_PRES/IR_RX0/GEVENT16_L

AV13

IR_TX0/GEVENT21_L

BA9

IR_TX1/GEVENT6_L

BA10

IR_RX1/GEVENT20_L

AV15

IR_LED_L/LLB_L/GPIO184

AU29

CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/GPIO60

AW2 9

CLK_REQ1_L/GPIO61

AR27

CLK_REQ2_L/GPIO62

AV27

CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/GPIO63

AY29

CLK_REQG_L/GPIO65/OSCIN

AY8

USB_OC0_L/SPI_TPM_CS_L/TRST_L/GEVENT12_L

AW1

USB_OC1_L/TDI/GEVENT13_L

AV1

USB_OC2_L/TCK/GEVENT14_L

AY1

USB_OC3_L/TDO/GEVENT15_L

AN2

AZ_BITCLK

AN1

AZ_SDOUT

AK2

AZ_SDIN0/GPIO167

AK1

AZ_SDIN1/GPIO168

AM1

AZ_SDIN2/GPIO169

AL2

AZ_SDIN3/GPIO170

AM2

AZ_SYNC

AL1

AZ_RST_L

AJ2

X32K_X1

AJ1

X32K_X2

FT3_BGA769 @

PANEL_SEL

TOUCH_SEL

PX5 Reserved DIS UMA

ACPI/SD/AZ/GPIO/RTC/MISC

Sequence

IR

RTC CLK

FT3 REV 0.51

H L

eDP panel

H L

Non Touch

Touch

Panel

(turn off EHCI)

Board_ID0

0 0 1 1

LVDS panel

B

oard_ID1Board Conf.

MSICHDA

0 1 0 1

SD

GPIO

BLINK/GEVENT18_L

GENINT1_L/GPIO32

GENINT2_L/GPIO33

PXS_PWREN PXS_EN# Board_ID0 Board_ID1

For DIS

PXS_PWREN

SD_PWR_CTRL

SD_CLK/GPIO73

SD_CMD/GPIO74

SD_CD/GPIO75

SD_WP/GPIO76

SD_DATA0/GPIO77

SD_DATA1/GPIO78

SD_DATA2/GPIO79

SD_DATA3/GPIO80

SD_LED/GPIO45

SCL0/GPIO43

SDA0/GPIO47

SCL1/GPIO227

SDA1/GPIO228

GPIO49

GPIO50

GPIO51

GPIO55

GPIO57

GPIO58

GPIO59

GPIO64

SPKR/GPIO66

GPIO68

GPIO69

GPIO70

GPIO71

GPIO174

GEVENT2_L

GEVENT4_L

GEVENT7_L

GEVENT10_L

GEVENT11_L

GEVENT17_L

GEVENT22_L

FANOUT0/GPIO52

FANIN0/GPIO56

RTCCLK

BA23 AY22

AY23 AY20 BA20

BA22 AY21 AY24 BA24

AY25

AU25

APU_SCLK0

AV25

APU_SDATA0

AY11

APU_SCLK1

BA11

APU_SDATA1

AP27 AY28

PW_CLEAR#

BA28 AV23

PANEL_SEL

AP21 BA26

Board_ID0

AV19

Board_ID1

AY27

PXS_RST#

BA27 AU21

PXS_PWREN

AY26

TOUCH_SEL

AV21 AM21 BA3

APU_GPIO174

AV17

GEVENT2

BA4 AR15 AP17 AP11 AN8 AU17 BA6

EC_LID_OUT#

BA29 AP23

AV31 AU31

AV11

RTC_CLK

RPC6

1 8 2 7 3 6 4 5

10K_8P4R_5%

VGA@

QC3A

2N7002KDWH_SOT363-6

6 1

QC3B

QC3B 2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

PXS_RST#

34

VGA@

EC_PXCONTROL

5

1 2

CC48

2

1 2

JPW SP@JPW SP@

GPIO174 PD CHK1.03

+3VS +3VALW_APU

Place at GPU

VGA@

PXS_EN#

EC_PXCONTROL <27>

@ESD@

180P_0402_50V8J

APU_PCIE_RST#_R

LPC_RST#_R

APU_SCLK0 <10,11,23>

APU_SDATA0 <10,11,23>

APU_SCLK1 <25> APU_SDATA1 <25>

PXS_RST# <12> APU_SPKR <26> PXS_PWREN <14,37>

SW request

EC_LID_OUT# <27>

VGA_PWRGD <15,37>

RTC_CLK <27>

1

PCIE_RST# is for PCIE devices on APU

1 2

RC68 33_0402_5%RC68 33_0402_5%

CC28

150P_0402_50V8J

A_RST# is for LPC devices

1 2

RC73 33_0402_5%RC73 33_0402_5%

150P_0402_50V8J

EC_LID_OUT#

PANEL_SEL

RC72

1

@

100K_0402_5%

2

1 2

1

RC74

CC27

APU SMBus0 for S0 , SMBus1 for S5 I

f APU_SMBUS no use pull high 1 0K

Board_ID0 Board_ID1

PXS_RST#

RC74 100K_0402_5%

100K_0402_5%

@

2

1 2

APU_SDATA0 APU_SCLK0

APU_SCLK1 APU_SDATA1

+3VS

1 8 2 7 3 6 4 5

1 2

RC137 10K_0402_5%UMA@RC137 10K_0402_5%UMA@

1 2

RC138 10K_0402_5%

UMA@

VGA@

RC133

1 2

RC94 10K_0402_5%RC94 10K_0402_5%

RC125

RC125 10K_0402_5%

10K_0402_5%

EDP@

1 2

RC126

RC126 10K_0402_5%

10K_0402_5%

LVDS@

1 2

RPC1

2.2K_8P4R_5%

APU_PCIE_RST# <12,22,23>

LPC_RST# <27>

+3VS

+3VALW_APU

+3VS

1K_0402_5%

+3VALW_APU

+3VS

RC95

RC95 10K_0402_5%

10K_0402_5%

TOUCH@

TOUCH_SEL

TOUCH@

1 2

RC99

RC99 1K_0402_5%

1K_0402_5%

NTOUCH@

1 2

close to APU

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/05/15 2015/09/27

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

FT3 GPIO/AZ/MISC

LA-A551P

Monday, May 06, 2013

0.1

of

8 40

of

8 40

of

8 40

1

5

1.5V OF APU

AMD CKL v1.01

VDDIO_MEM_S

+1.5V

3A

@

2

1

CC3910U_0603_6.3V6M CC3910U_0603_6.3V6M

D D

2

1

CC4010U_0603_6.3V6M CC4010U_0603_6.3V6M

2

CC330.1U_0402_16V7K CC330.1U_0402_16V7K

CC340.1U_0402_16V7K CC340.1U_0402_16V7K

CC410.1U_0402_16V7K CC410.1U_0402_16V7K

CC350.1U_0402_16V7K CC350.1U_0402_16V7K

1

2

CC420.1U_0402_16V7K CC420.1U_0402_16V7K

1

2

CC360.1U_0402_16V7K CC360.1U_0402_16V7K

CC430.1U_0402_16V7K CC430.1U_0402_16V7K

CC370.1U_0402_16V7K CC370.1U_0402_16V7K

1

2

@

CC14

47U_0805_6.3V6M

AMD CKL v1.01 4.7uF

1.8VALW & 1.8VS OF APU

VDD_18

VDD_18_ALW

+1.8VALW

1 2

RC116 0_0603_5%RC116 0_0603_5%

C C

1

CC494.7U_0603_6.3V6K CC494.7U_0603_6.3V6K

CC501U_0402_6.3V6K CC501U_0402_6.3V6K

2

+1.8VALW_APU

0.5A

1

CC521U_0402_6.3V6K CC521U_0402_6.3V6K

CC511U_0402_6.3V6K CC511U_0402_6.3V6K

2

1

CC531U_0402_6.3V6K CC531U_0402_6.3V6K

CC551U_0402_6.3V6K CC551U_0402_6.3V6K

CC541U_0402_6.3V6K CC541U_0402_6.3V6K

2

+1.8VS

CC5710U_0603_6.3V6M CC5710U_0603_6.3V6M

1

2

3.3VALW & 3.3VS OF APU

1

CC721U_0402_6.3V6K CC721U_0402_6.3V6K

2

+1.5VS

1

2

V

DDIO_33_ALW

VDDIO_33

+RTC_APU

for VDDIO_AZ_ALW 0.1A

1

CC664.7U_0603_6.3V6K CC664.7U_0603_6.3V6K

CC671U_0402_6.3V6K CC671U_0402_6.3V6K

2

Place on TOP

4.7uF 1uF 180pFAMD CKL v1.01

1 3 1

4.5uA

1

CC98

2

0.22U_0402_16V7K

+3VALW_APU

for VDDIO_33_ALW 0.2A

1

B B

CC741U_0402_6.3V6K CC741U_0402_6.3V6K

2

+3VS

RC117 0_0603_5%RC117 0_0603_5%

1 2

+3VS_APU

0.2A

CC711U_0402_6.3V6K CC711U_0402_6.3V6K

1

CC751U_0402_6.3V6K CC751U_0402_6.3V6K

2

RTC OF APU

A A

+3VL +RTC

DC5

2 1

CH751H-40PT_SOD323-2

5

4

10uF 0.1uF 180pF

2 8 4

10uF 1uF 180pF

1 7 1

1 6 1

.5A

1

CC581U_0402_6.3V6K CC581U_0402_6.3V6K

CC591U_0402_6.3V6K CC591U_0402_6.3V6K

2

1

CC691U_0402_6.3V6K CC691U_0402_6.3V6K

2

CC631U_0402_6.3V6K CC631U_0402_6.3V6K

CC621U_0402_6.3V6K CC621U_0402_6.3V6K

CC601U_0402_6.3V6K CC601U_0402_6.3V6K

CC611U_0402_6.3V6K CC611U_0402_6.3V6K

2

1

CC701U_0402_6.3V6K CC701U_0402_6.3V6K

2

2 1

12

RC123

RC123 120_0402_5%

120_0402_5%

route to 20mil

12

SP@

JCMOS

4

1

CC641U_0402_6.3V6K CC641U_0402_6.3V6K

2

RC122

1 2

10K_0402_5%

0.1A

0

+1.8VALW_APU

0.2A

+3VALW_APU

+0.95VALW_APU_USB3

0.5A

+0.95VALW_APU

4.5uA

+RTC_APU

+RTC_APU_R

3

UC1F

+1.5V

+1.5VS

.5A

1A

3A

UC1F

J35

VDDIO_MEM_S_1

L32

VDDIO_MEM_S_2

L37

VDDIO_MEM_S_3

N35

VDDIO_MEM_S_4

R31

VDDIO_MEM_S_5

R37

VDDIO_MEM_S_6

U32

VDDIO_MEM_S_7

U35

VDDIO_MEM_S_8

W31

VDDIO_MEM_S_9

W32

VDDIO_MEM_S_10

W37

VDDIO_MEM_S_11

AA31

VDDIO_MEM_S_12

AA35

VDDIO_MEM_S_13

AC32

VDDIO_MEM_S_14

AC37

VDDIO_MEM_S_15

AE31

VDDIO_MEM_S_16

AE35

VDDIO_MEM_S_17

AG32

VDDIO_MEM_S_18

AG37

VDDIO_MEM_S_19

AJ35

VDDIO_MEM_S_20

AL32

VDDIO_MEM_S_21

AL37

VDDIO_MEM_S_22

AR35

VDDIO_MEM_S_23

AL10

VDDIO_AZ_ALW_1

AL11

VDDIO_AZ_ALW_2

B1

VDD_18_ALW_1

B2

VDD_18_ALW_2

AL13

VDD_33_ALW_1

AM13

VDD_33_ALW_2

AR5

VDD_095_USB3_DUAL_1

AU4

VDD_095_USB3_DUAL_2

AV7

VDD_095_USB3_DUAL_3

AW5

VDD_095_USB3_DUAL_4

AE11

VDD_095_ALW_1

AE13

VDD_095_ALW_2

AJ11

VDD_095_ALW_3

AJ13

VDD_095_ALW_4

AN4

VDDBT_RTC_G

FT3_BGA769 @

POWER

FT3 REV 0.51

VDDCR_CPU_1

VDDCR_CPU_2

VDDCR_CPU_3

VDDCR_CPU_4

VDDCR_CPU_5

VDDCR_CPU_6

VDDCR_CPU_7

VDDCR_CPU_8

VDDCR_CPU_9

VDDCR_CPU_10

VDDCR_CPU_11

VDDCR_CPU_12

VDDCR_CPU_13

VDDCR_CPU_14

VDDCR_CPU_15

VDDCR_CPU_16

VDDCR_CPU_17

VDDCR_CPU_18

VDDCR_CPU_19

VDDCR_CPU_20

VDDCR_CPU_21

VDDCR_CPU_22

VDDCR_CPU_23

VDDCR_CPU_24

VDDCR_CPU_25

VDDCR_CPU_26

VDDCR_NB_1

VDDCR_NB_2

VDDCR_NB_3

VDDCR_NB_4

VDDCR_NB_5

VDDCR_NB_6

VDDCR_NB_7

VDDCR_NB_8

VDDCR_NB_9

VDDCR_NB_10

VDDCR_NB_11

VDDCR_NB_12

VDDCR_NB_13

VDDCR_NB_14

VDDCR_NB_15

VDDCR_NB_16

VDDCR_NB_17

VDDCR_NB_18

VDDCR_NB_19

VDDCR_NB_20

VDDCR_NB_21

VDD_18_1

VDD_18_2

VDD_18_3

VDD_18_4

VDD_33_1

VDD_33_2

VDD_095_1

VDD_095_2

VDD_095_3

VDD_095_4

VDD_095_5

VDD_095_6

VDD_095_7

VDD_095_8

VDD_095_9

VDD_095_GFX_1

VDD_095_GFX_2

VDD_095_GFX_3

L21 L23 L25 L27 L29 N21 N23 N27 R21 R23 R27 U21 U23 U27 W21 W23 W27 AA21 AA23 AA27 AC21 AC23 AC27 AE21 AE23 AE27

L13 L17 N11 N13 N17 R11 R13 R17 U13 U17 W13 W17 AA13 AA17 AC13 AC17 AE15 AE17 AE19 AG17 AG21

A2 A3 B3 C3

AM15 AM17

AG23 AG27 AJ21 AJ27 AL21 AL23 AL27 AM23 AM25

U10 W10 AA10

15A/21A

+APU_CORE

13A/17A

+APU_CORE_NB

1.5A

+1.8VS

0.2A

+3VS_APU

5A

+0.95VS_APU

0.6A

+0.95VS_APU_GFX

0.95VALW & 0.95VS OF APU

+0.95VALW

1 2

RC119 0_0603_5%RC119 0_0603_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+0.95VALW_APU_USB3

1

CC7710U_0603_6.3V6M CC7710U_0603_6.3V6M

2

2013/05/15 2015/09/27

1A

+0.95VALW

1 2

1

CC791U_0402_6.3V6K CC791U_0402_6.3V6K

CC801U_0402_6.3V6K CC801U_0402_6.3V6K

CC781U_0402_6.3V6K CC781U_0402_6.3V6K

2

RC120 0_0603_5%RC120 0_0603_5%

1

2

Compal Secret Data

Deciphered Date

2

A8 A13 A23 A31 A35 A39

B8 B13 B23 B31 B39

C1

C2

C5

C7

C9 C11 C13 C15 C17 C19 C21 C23 C25 C27 C29 C31 C33 C35 C37 C39 C41

D9 D11 D13

E3

E4

E9 E11 E13 E27 E31 E35 E38 E39

G3

G7 G11 G13 G15 G17 G21 G25 G29 G35 G37 G39 G41 H11 H13 H23 H31

+0.95VALW_APU

0.5AVDDIO_AZ_ALW

1

CC821U_0402_6.3V6K CC821U_0402_6.3V6K

CC841U_0402_6.3V6K CC841U_0402_6.3V6K

CC831U_0402_6.3V6K CC831U_0402_6.3V6K

2

UC1G

GND

VSS_1

VSS_2

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9

VSS_10

VSS_11

VSS_12

VSS_13

VSS_14

VSS_15

VSS_16

VSS_17

VSS_18

VSS_19

VSS_20

VSS_21

VSS_22

VSS_23

VSS_24

VSS_25

VSS_26

VSS_27

VSS_28

VSS_29

VSS_30

VSS_31

VSS_32

VSS_33

VSS_34

VSS_35

VSS_36

VSS_37

VSS_38

VSS_39

VSS_40

VSS_41

VSS_42

VSS_43

VSS_44

VSS_45

VSS_46

VSS_47

VSS_48

VSS_49

VSS_50

VSS_51

VSS_52

VSS_53

VSS_54

VSS_55

VSS_56

VSS_57

VSS_58

VSS_59

VSS_60

VSS_61

VSS_62

FT3 REV 0.51

FT3_BGA769 @

+0.95VS

2

PJ2

2

JUMP_43X79

@

1

CC851U_0402_6.3V6K CC851U_0402_6.3V6K

2

5A

1

CC8710U_0603_6.3V6M CC8710U_0603_6.3V6M

CC8610U_0603_6.3V6M CC8610U_0603_6.3V6M

2

1

UC1H

GND

J3

VSS_63

J7

VSS_64

J8

VSS_65

J39

VSS_66

K11

VSS_67

K13

VSS_68

K17

VSS_69

K19

VSS_70

K21

VSS_71

K23

VSS_72

K25

VSS_73

K27

VSS_74

K29

VSS_75

K31

VSS_76

L3

VSS_77

L7

VSS_78

L8

VSS_79

L10

VSS_80

L11

VSS_81

L15

VSS_82

L19

VSS_83

L31

VSS_84

L39

VSS_85

L41

VSS_86

M1

VSS_87

M2

VSS_88

N3

VSS_89

N7

VSS_90

N15

VSS_91

N19

VSS_92

N25

VSS_93

N29

VSS_94

N31

VSS_95

N39

VSS_96

P1

VSS_97

P2

VSS_98

R3

VSS_99

R7

VSS_100

R15

VSS_101

R19

VSS_102

R25

VSS_103

R29

VSS_104

R39

VSS_105

R41

VSS_106

U1

VSS_107

U2

VSS_108

U3

VSS_109

U7

VSS_110

U8

VSS_111

U11

VSS_112

U15

VSS_113

U19

VSS_114

U25

VSS_115

U29

VSS_116

U31

VSS_117

U39

VSS_118

W3

VSS_119

W5

VSS_120

W11

VSS_121

W15

VSS_122

W19

VSS_123

W25

VSS_124

AMD CKL v1.01

VDD_095_USB3_DUAL VDD_095 VDD_095_ALW VDD_095_GFX

W29 W39 W41

Y1

Y2 AA3 AA7 AA8

AA11 AA15 AA19 AA25 AA29 AA39

AC3

AC7 AC11 AC15 AC19 AC25 AC29 AC31 AC39 AC41

AE3

AE7 AE25 AE29 AE32 AE39

AG3

AG5 AG10 AG11 AG13 AG15 AG19 AG25 AG29 AG31 AG39 AG41

AH1

AH2

AJ3

AJ7 AJ15 AJ17 AJ19 AJ23 AJ25 AJ29 AJ31 AJ32 AJ39

AL3

AL8

AL15 AL17 AL19 AL25 AL29

10uF 1uF 180pF

2 3 1 2 5 1

1 1

VSS_125

VSS_126

VSS_127

VSS_128

VSS_129

VSS_130

VSS_131

VSS_132

VSS_133

VSS_134

VSS_135

VSS_136

VSS_137

VSS_138

VSS_139

VSS_140

VSS_141

VSS_142

VSS_143

VSS_144

VSS_145

VSS_146

VSS_147

VSS_148

VSS_149

VSS_150

VSS_151

VSS_152

VSS_153

VSS_154

VSS_155

VSS_156

VSS_157

VSS_158

VSS_159

VSS_160

VSS_161

VSS_162

VSS_163

VSS_164

VSS_165

VSS_166

VSS_167

VSS_168

VSS_169

VSS_170

VSS_171

VSS_172

VSS_173

VSS_174

VSS_175

VSS_176

VSS_177

VSS_178

VSS_179

VSS_180

VSS_181

VSS_182

VSS_183

VSS_184

VSS_185

VSS_186

FT3_BGA769

4

GND

FT3 REV 0.51

VSS_187

VSS_188

VSS_189

VSS_190

VSS_191

VSS_192

VSS_193

VSS_194

VSS_195

VSS_196

VSS_197

VSS_198

VSS_199

VSS_200

VSS_201

VSS_202

VSS_203

VSS_204

VSS_205

VSS_206

VSS_207

VSS_208

VSS_209

VSS_210

VSS_211

VSS_212

VSS_213

VSS_214

VSS_215

VSS_216

VSS_217

VSS_218

VSS_219

VSS_220

VSS_221

VSS_222

VSS_223

VSS_224

VSS_225

VSS_226

VSS_227

VSS_228

VSS_229

VSS_230

VSS_231

VSS_232

VSS_233

VSS_234

VSS_235

VSS_236

VSS_237

VSS_238

VSS_239

VSS_240

VSS_241

VSS_242

VSSBG_DAC

VBURN

PSEN

@

+0.95VS_APU

LC1

1 2

FBMA-L11-201209-300LMA30T

1

CC901U_0402_6.3V6K CC901U_0402_6.3V6K

CC911U_0402_6.3V6K CC911U_0402_6.3V6K

CC921U_0402_6.3V6K CC921U_0402_6.3V6K

2

FT3 PWR/GND

Monday, May 06, 2013

1

2

LA-A551P

CC881U_0402_6.3V6K CC881U_0402_6.3V6K

CC891U_0402_6.3V6K CC891U_0402_6.3V6K

2

Title

Size Document Number Rev

Date: Sheet

FBMA-L11-201209-300LMA30T

9 40

1

AL39 AL41 AM11 AM27 AM31 AN3 AN7 AN39 AP31 AR3 AR13 AR17 AR21 AR25 AR29 AR39 AR41 AU1 AU2 AU3 AU15 AU19 AU23 AU27 AU39 AV9 AW3 AW7 AW1 3 AW1 5 AW1 7 AW1 9 AW2 1 AW2 3 AW2 5 AW2 7 AW3 1 AW3 3 AW3 5 AW3 7 AW3 9 AW4 1 AY13 AY15 AY18 AY30 BA2 BA7 BA13 BA15 BA18 BA21 BA25 BA31 BA35 BA39 A15 AL31 AM29

+0.95VS_APU_GFX

0.6A

1

CC9510U_0603_6.3V6M CC9510U_0603_6.3V6M

2

of

1

CC961U_0402_6.3V6K CC961U_0402_6.3V6K

2

0.1

5

+VREF_DQA

DDR_AB_D0 DDR_AB_D1

DDR_AB_DM0

DDR_AB_D2 DDR_AB_D3

DDR_AB_D8

0.1U_0402_16V4Z

5

2

CD20

1

DDR_AB_D9

DDR_AB_DQS#1 DDR_AB_DQS1

DDR_AB_D10 DDR_AB_D11

DDR_AB_D16 DDR_AB_D17

DDR_AB_DQS#2 DDR_AB_DQS2

DDR_AB_D18 DDR_AB_D19

DDR_AB_D24 DDR_AB_D25

DDR_AB_DM3

DDR_AB_D26 DDR_AB_D27

DDR_A_CKE0

DDR_AB_BS2

DDR_AB_MA9

DDR_AB_MA8 DDR_AB_MA5

DDR_AB_MA3 DDR_AB_MA1

DDR_A_CLK0 DDR_A_CLK0#

DDR_AB_MA10 DDR_AB_BS0

DDR_AB_WE# DDR_AB_CAS#

DDR_AB_MA13 DDR_A_SCS1#

DDR_AB_D32 DDR_AB_D33

DDR_AB_DQS#4 DDR_AB_DQS4

DDR_AB_D34 DDR_AB_D35

DDR_AB_D40 DDR_AB_D41

DDR_AB_DM5

DDR_AB_D42 DDR_AB_D43

DDR_AB_D48 DDR_AB_D49

DDR_AB_DQS#6 DDR_AB_DQS6

DDR_AB_D50 DDR_AB_D51

DDR_AB_D56 DDR_AB_D57

DDR_AB_DM7

DDR_AB_D58 DDR_AB_D59

D D

C C

B B

A A

+3VS

DDR_AB_BS2<11,5>

DDR_A_CLK0<5> DDR_A_CLK0#<5>

DDR_AB_BS0<11,5>

DDR_AB_WE#<11,5>

DDR_AB_CAS#<11,5>

DDR_A_SCS1#<5>

+0.75VS

+1.5V

JDDR3L

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

LCN_DAN06-K4406-0103

Conn@

VSS DQ4 DQ5 VSS

DQS0#

DQS0

VSS DQ6 DQ7 VSS

DQ12 DQ13

VSS DM1

RESET#

VSS

DQ14 DQ15

VSS

DQ20 DQ21

VSS DM2 VSS

DQ22 DQ23

VSS

DQ28 DQ29

VSS

DQS3#

DQS3

VSS

DQ30 DQ31

VSS

CKE1

VDD

A15

A14 VDD

A11

VDD

VDD CK1

CK1#

VDD

BA1

RAS#

VDD

S0#

ODT0

VDD

ODT1

VDD

VREF_CA

VSS

DQ36 DQ37

VSS DM4 VSS

DQ38 DQ39

VSS

DQ44 DQ45

VSS

DQS5#

DQS5

VSS

DQ46 DQ47

VSS

DQ52 DQ53

VSS DM6 VSS

DQ54 DQ55

VSS

DQ60 DQ61

VSS

DQS7#

DQS7

VSS

DQ62 DQ63

VSS

EVENT#

SDA SCL

VTT

GND2

BOSS2

A7

A6 A4

A2 A0

NC

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206 208

4

+1.5V

DDR_AB_D4 DDR_AB_D5

DDR_AB_DQS#0

DDR_AB_DQS0

DDR_AB_D6 DDR_AB_D7

DDR_AB_D12 DDR_AB_D13

DDR_AB_DM1 MEM_MAB_RST#

DDR_AB_D14 DDR_AB_D15

DDR_AB_D20 DDR_AB_D21

DDR_AB_DM2

DDR_AB_D22 DDR_AB_D23

DDR_AB_D28 DDR_AB_D29

DDR_AB_DQS#3

DDR_AB_DQS3

DDR_AB_D30 DDR_AB_D31

DDR_A_CKE1

DDR_AB_MA15 DDR_AB_MA14

DDR_AB_MA11DDR_AB_MA12 DDR_AB_MA7

DDR_AB_MA6 DDR_AB_MA4

DDR_AB_MA2 DDR_AB_MA0

DDR_A_CLK1 DDR_A_CLK1#

DDR_AB_BS1 DDR_AB_RAS#

DDR_A_SCS0# DDR_A_ODT0

DDR_A_ODT1

+VREF_CAA

DDR_AB_D36 DDR_AB_D37

DDR_AB_DM4

DDR_AB_D38 DDR_AB_D39

DDR_AB_D44 DDR_AB_D45

DDR_AB_DQS#5

DDR_AB_DQS5

DDR_AB_D46 DDR_AB_D47

DDR_AB_D52 DDR_AB_D53

DDR_AB_DM6

DDR_AB_D54 DDR_AB_D55

DDR_AB_D60 DDR_AB_D61

DDR_AB_DQS#7

DDR_AB_DQS7

DDR_AB_D62 DDR_AB_D63

MEM_MAB_EVENT# APU_SDATA0 APU_SCLK0

+0.75VS

4

DDR3 SO-DIMM A Reverse Type

MEM_MAB_RST# <11,5>

DDR_A_CKE1 <5>DDR_A_CKE0<5>

DDR_A_CLK1 <5> DDR_A_CLK1# <5>

DDR_AB_BS1 <11,5> DDR_AB_RAS# <11,5>

DDR_A_SCS0# <5> DDR_A_ODT0 <5>

DDR_A_ODT1 <5>

MEM_MAB_EVENT# <11,5> APU_SDATA0 <11,23,8> APU_SCLK0 <11,23,8>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

SO-DIMM VREF

DDR_AB_DQS[0..7] <11,5>

DDR_AB_DQS#[0..7] <11,5>

DDR_AB_D[0..63] <11,5>

DDR_AB_DM[0..7] <11,5>

DDR_AB_MA[0..15] <11,5>

Layout Note: Place near JDDR3L

+1.5V

CD43

CD10 10U_0603_6.3V6MCD10 10U_0603_6.3V6M

CD11 10U_0603_6.3V6MCD11 10U_0603_6.3V6M

CD13 10U_0603_6.3V6MCD13 10U_0603_6.3V6M

CD14 10U_0603_6.3V6MCD14 10U_0603_6.3V6M

CD16 10U_0603_6.3V6MCD16 10U_0603_6.3V6M

CD18 10U_0603_6.3V6MCD18 10U_0603_6.3V6M

2013/05/15 2015/09/27

3

1 2

47U_0805_6.3V6M

Compal Secret Data

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

Deciphered Date

2

+1.5V +1.5V

12

RD1

1K_0402_1%

+VREF_CAA+VREF_DQA

2

CD1

1

0.1U_0402_16V7K

12

1

@

RD3

CD2

2

RD3

1K_0402_1%

2.2U_0402_6.3V6M

Close to JDDR3L.1 Close to JDDR3L.126

Layout Note: Place near JDDR3L.203 and 204

+1.5V

1 2

CD5 0.1U_0402_16V4ZCD5 0.1U_0402_16V4Z

1 2

CD6 0.1U_0402_16V4ZCD6 0.1U_0402_16V4Z

1 2

CD7 0.1U_0402_16V4ZCD7 0.1U_0402_16V4Z

1 2

CD8 0.1U_0402_16V4ZCD8 0.1U_0402_16V4Z

2

+0.75VS

CD9 1U_0402_6.3V6KCD9 1U_0402_6.3V6K

CD12 1U_0402_6.3V6KCD12 1U_0402_6.3V6K

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRIII-SODIMMA

LA-A551P

1

12

RD2

1K_0402_1%

2

CD3

1

0.1U_0402_16V7K

12

1

12

1

@

CD4

2

RD4

1K_0402_1%

2.2U_0402_6.3V6M

0.1

of

10 40Monday, May 06, 2013

of

10 40Monday, May 06, 2013

of

10 40Monday, May 06, 2013

5

+1.5V

+VREF_DQB

DDR_AB_D0 DDR_AB_D1

DDR_AB_DM0

DDR_AB_D2 DDR_AB_D3

D D

C C

B B

A A

+3VS

DDR_AB_BS2<10,5>

DDR_B_CLK0<5> DDR_B_CLK0#<5>

DDR_AB_BS0<10,5>

DDR_AB_WE#<10,5>

DDR_AB_CAS#<10,5>

DDR_B_SCS1#<5>

DDR_AB_D8 DDR_AB_D9

DDR_AB_DQS#1 DDR_AB_DQS1

DDR_AB_D10 DDR_AB_D11

DDR_AB_D16 DDR_AB_D17

DDR_AB_DQS#2 DDR_AB_DQS2

DDR_AB_D18 DDR_AB_D19

DDR_AB_D24 DDR_AB_D25

DDR_AB_DM3

DDR_AB_D26 DDR_AB_D27

DDR_B_CKE0

DDR_AB_BS2

DDR_AB_MA9

DDR_AB_MA8 DDR_AB_MA5

DDR_AB_MA3 DDR_AB_MA1

DDR_B_CLK0 DDR_B_CLK0#

DDR_AB_MA10 DDR_AB_BS0

DDR_AB_WE# DDR_AB_CAS#

DDR_AB_MA13 DDR_B_SCS1#

DDR_AB_D32 DDR_AB_D33

DDR_AB_DQS#4 DDR_AB_DQS4

DDR_AB_D34 DDR_AB_D35

DDR_AB_D40 DDR_AB_D41

DDR_AB_DM5

DDR_AB_D42 DDR_AB_D43

DDR_AB_D48 DDR_AB_D49

DDR_AB_DQS#6 DDR_AB_DQS6

DDR_AB_D50 DDR_AB_D51

DDR_AB_D56 DDR_AB_D57

DDR_AB_DM7

DDR_AB_D58 DDR_AB_D59

1 2

RD9 10K_0402_5%RD9 10K_0402_5%

2

CD40

1

0.1U_0402_16V4Z

5

+0.75VS

JDDR3H

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

LCN_DAN06-K4806-0103

Conn@

VSS DQ4 DQ5

VSS

DQS0#

DQS0

VSS DQ6 DQ7

VSS

DQ12 DQ13

VSS DM1

RESET#

VSS

DQ14 DQ15

VSS

DQ20 DQ21

VSS DM2

VSS

DQ22 DQ23

VSS

DQ28 DQ29

VSS

DQS3#

DQS3

VSS

DQ30 DQ31

VSS

CKE1

VDD

CK1

CK1#

VDD

BA1

RAS#

VDD

ODT0

VDD

ODT1

VDD

VREF_CA

VSS

DQ36 DQ37

VSS DM4

VSS

DQ38 DQ39

VSS

DQ44 DQ45

VSS

DQS5#

DQS5

VSS

DQ46 DQ47

VSS

DQ52 DQ53

VSS DM6

VSS

DQ54 DQ55

VSS

DQ60 DQ61

VSS

DQS7#

DQS7

VSS

DQ62 DQ63

VSS

EVENT#

SDA

SCL

VTT

GND2

BOSS2

A15 A14

A11

S0#

NC

4

+1.5V

2 4

DDR_AB_D4

6

DDR_AB_D5

8 10

DDR_AB_DQS#0

12

DDR_AB_DQS0

14 16

DDR_AB_D6

18

DDR_AB_D7

20 22

DDR_AB_D12

24

DDR_AB_D13

26 28

DDR_AB_DM1

30

MEM_MAB_RST#

32 34

DDR_AB_D14

36

DDR_AB_D15

38 40

DDR_AB_D20

42

DDR_AB_D21

44 46

DDR_AB_DM2

48 50

DDR_AB_D22

52

DDR_AB_D23

54 56

DDR_AB_D28

58

DDR_AB_D29

60 62

DDR_AB_DQS#3

64

DDR_AB_DQS3

66 68

DDR_AB_D30

70

DDR_AB_D31

72

74

DDR_B_CKE1

76 78

DDR_AB_MA15

80

DDR_AB_MA14

82 84

DDR_AB_MA11DDR_AB_MA12

86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206 208

DDR_AB_MA7

DDR_AB_MA6 DDR_AB_MA4

DDR_AB_MA2 DDR_AB_MA0

DDR_B_CLK1 DDR_B_CLK1#

DDR_AB_BS1 DDR_AB_RAS#

DDR_B_SCS0# DDR_B_ODT0

DDR_B_ODT1

+VREF_CAB

DDR_AB_D36 DDR_AB_D37

DDR_AB_DM4

DDR_AB_D38 DDR_AB_D39

DDR_AB_D44 DDR_AB_D45

DDR_AB_DQS#5 DDR_AB_DQS5

DDR_AB_D46 DDR_AB_D47

DDR_AB_D52 DDR_AB_D53

DDR_AB_DM6

DDR_AB_D54 DDR_AB_D55

DDR_AB_D60 DDR_AB_D61

DDR_AB_DQS#7 DDR_AB_DQS7

DDR_AB_D62 DDR_AB_D63

MEM_MAB_EVENT# APU_SDATA0 APU_SCLK0

+0.75VS

4

A7

A6 A4

A2 A0

DDR3 SO-DIMM B Standard Type

MEM_MAB_RST# <10,5>

DDR_B_CKE1 <5>DDR_B_CKE0<5>

DDR_B_CLK1 <5> DDR_B_CLK1# <5>

DDR_AB_BS1 <10,5> DDR_AB_RAS# <10,5>

DDR_B_SCS0# <5> DDR_B_ODT0 <5>

DDR_B_ODT1 <5>

MEM_MAB_EVENT# <10,5> APU_SDATA0 <10,23,8> APU_SCLK0 <10,23,8>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

SO-DIMM VREF

DDR_AB_DQS[0..7] <10,5>

DDR_AB_DQS#[0..7] <10,5>

DDR_AB_D[0..63] <10,5>

DDR_AB_DM[0..7] <10,5>

DDR_AB_MA[0..15] <10,5>

Layout Note: Place near JDDR3H

+1.5V

1 2

CD30 10U_0603_6.3V6MCD30 10U_0603_6.3V6M

1 2

CD31 10U_0603_6.3V6MCD31 10U_0603_6.3V6M

1 2

CD33 10U_0603_6.3V6MCD33 10U_0603_6.3V6M

1 2

CD34 10U_0603_6.3V6MCD34 10U_0603_6.3V6M

1 2

CD36 10U_0603_6.3V6MCD36 10U_0603_6.3V6M

1 2

CD38 10U_0603_6.3V6MCD38 10U_0603_6.3V6M

2013/05/15 2015/09/27

3

Layout Note: Place these 4 Caps near Command and Control signals of DIMMB

+1.5V

CD25 0.1U_0402_16V4ZCD25 0.1U_0402_16V4Z

CD26 0.1U_0402_16V4ZCD26 0.1U_0402_16V4Z

CD27 0.1U_0402_16V4ZCD27 0.1U_0402_16V4Z

CD28 0.1U_0402_16V4ZCD28 0.1U_0402_16V4Z

Compal Secret Data

Deciphered Date

2

CD21

1

0.1U_0402_16V7K

Close to JDDR3H.1

12

2

1

+1.5V

12

RD6

1K_0402_1%

+VREF_CAB+VREF_DQB

12

1

@

RD5

CD22

2

RD5

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M 1K_0402_1%

1K_0402_1%

2

1

CD23

1

@

CD24

2.2U_0402_6.3V6M

2

0.1U_0402_16V7K

Close to JDDR3H.126

Layout Note: Place near JDDRH.203 and 204

+0.75VS

12

CD29 1U_0402_6.3V6KCD29 1U_0402_6.3V6K

12

CD32 1U_0402_6.3V6KCD32 1U_0402_6.3V6K

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRIII-SODIMMB

LA-A551P

1

+1.5V

11 40Monday, May 06, 2013

12

RD8

1K_0402_1%

12

RD7

1K_0402_1%

of

0.1

A

B

C

D

E

PCIE_ATX_C_GRX_P[3..0]<5>

PCIE_ATX_C_GRX_N[3..0]<5>

1 1

2 2

3 3

CLK_PCIE_VGA<7> CLK_PCIE_VGA#<7>

3.3-V tolerant

4 4

PXS_RST#<8>

APU_PCIE_RST#<22,23,8>

A

PCIE_ATX_C_GRX_P[3..0]

PCIE_ATX_C_GRX_N[3..0]

PCIE_ATX_C_GRX_P0 PCIE_ATX_C_GRX_N0

PCIE_ATX_C_GRX_P1 PCIE_ATX_C_GRX_N1

PCIE_ATX_C_GRX_P2 PCIE_ATX_C_GRX_N2

PCIE_ATX_C_GRX_P3 PCIE_ATX_C_GRX_N3

CLK_PCIE_VGA CLK_PCIE_VGA#

12

VGA@

RV2 1K_0402_5%

GPU_RST#

12

+3VS

2

B

1

A

VGA@

RV212

RV212 100K_0402_5%

100K_0402_5%

UV1A

AA38

PCIE_RX0P

Y37

PCIE_RX0N

Y35

PCIE_RX1P

W36

PCIE_RX1N

W38

PCIE_RX2P

V37

PCIE_RX2N

V35

PCIE_RX3P

U36

PCIE_RX3N

U38

PCIE_RX4P

T37

PCIE_RX4N

T35

PCIE_RX5P

R36

PCIE_RX5N

R38

PCIE_RX6P

P37

PCIE_RX6N

P35

PCIE_RX7P

N36

PCIE_RX7N

N38

NC

M37

NC

M35

NC

L36

NC

L38

NC

K37

NC

K35

NC

J36

NC

J38

NC

H37

NC

H35

NC

G36

NC

G38

NC

F37

NC

F35

NC

E37

NC

CLOCK

AB35

PCIE_REFCLKP

AA36

PCIE_REFCLKN

AH16

TEST_PG

AA30

PERSTB

VGA@

5

UV13

P

4

Y

G

3

MC74VHC1G08DFT2G SC70 5P

PART 1 0F 9

PCI EXPRESS INTERFACE

SUN-PRO M2_FCBGA962VGA@

GPU_RST#

B

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

CALIBRATION

PCIE_CALR_TX

PCIE_CALR_RX

PCIE_GTX_C_ARX_P[3..0]

PCIE_GTX_C_ARX_N[3..0]

.1U_0402_16V7K

Y33

PCIE_GTX_ARX_P0 PCIE_GTX_C_ARX_P0

Y32

W33

PCIE_GTX_ARX_P1

W32

PCIE_GTX_ARX_N1

U33

PCIE_GTX_ARX_P2

U32

PCIE_GTX_ARX_N2 PCIE_GTX_C_ARX_N2

U30

PCIE_GTX_ARX_P3

U29

PCIE_GTX_ARX_N3 PCIE_GTX_C_ARX_N3

T33 T32

T30 T29

P33 P32

P30 P29

N33

NC

N32

NC

N30

NC

N29

NC

L33

NC

L32

NC

L30

NC

L29

NC

K33

NC

K32

NC

J33

NC

J32

NC

K30

NC

K29

NC

H33

NC

H32

NC

Y30

VGA_PCIE_CALRP

Y29

VGA_PCIE_CALRN

.1U_0402_16V7K

AC Coupling Cap acitor P

CIeR Gen1 and G en2 only: Recom mended value is 100 nF 10%.

PCIeR Gen3: Rec ommended value is 220 nF 10%.

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

1 2

RV1 1.69K_0402 _1%VGA@RV1 1.69K_0402_1%VGA@

1 2

RV3 1K_0402_1%VGA@RV3 1K_0402_1%VGA@

Issued Date

PCIE_GTX_C_ARX_P[3..0] <5>

PCIE_GTX_C_ARX_N[3..0] <5>

1 2

CV1 CV2

CV3 CV4

CV5 CV6

CV7 CV8

C

VGA@CV1

VGA@

1 2

VGA@CV2

VGA@

1 2

VGA@CV3

VGA@

1 2

VGA@CV4

VGA@

1 2

VGA@CV5

VGA@

1 2

VGA@CV6

VGA@

1 2

VGA@CV7

VGA@

1 2

VGA@CV8

VGA@

2013/05/15 2015 /09/27

PCIE_GTX_C_ARX_N0PCIE_GTX_ARX_N0

PCIE_GTX_C_ARX_P1 PCIE_GTX_C_ARX_N1

PCIE_GTX_C_ARX_P2

PCIE_GTX_C_ARX_P3

For MEMCLK 1GHz Brand

gDDR3-2Gbit

+0.95VGS

For MEMCLK 900MHz Brand

gDDR3-2Gbit

Compal Secret Data

Deciphered Date

skHynix

Samsung

skHynix

Micron

Samsung

LVDS Interface

UV1D

PART 7 0F 9

RSVD/VARY_BL

LVDS CONTROL

LVTMDP

Description

H5TQ2G63DFR-N0C

K4W2G1646E-BC1A

Comment PS_3[3:1] R_pu(ohm) R_pd(ohm)

1.5V/1GHz

Description

H5TQ2G63DFR-11C

MT41K128M16JT-1 07G:K

K4W2G1646E-BC11 1.5V/900MHz 111

D

RSVD/DIGON

TXCBP_DPB3P

TXCBM_DPB3N

TX3P_DPB2P TX3M_DPB2N

TX4P_DPB1P TX4M_DPB1N

TX5P_DPB0P TX5M_DPB0N

NC#AF35

NC#AG36

TXCAP_DPA3P

TXCAM_DPA3N

TX0P_DPA2P TX0M_DPA2N

TX1P_DPA1P TX1M_DPA1N

TX2P_DPA0P TX2M_DPA0N

SUN-PRO M2_FCBGA962VGA@

000

111

Comment PS_3[3:1]R_pu(ohm) R_pd(ohm)

1.5V/900MHz

1.35V/900MHz

1.5V/900MHz

Title

Size Document Number Rev

Custom

Date: Sheet

AK27 AJ27

AK35 AL36

AJ38 AK37

AH35 AJ36

AG38 AH37

AF35 AG36

AP34 AR34

AW37 AU35

AR37 AU39

AP35 AR35

AN36

NC

AP37

NC

4750

000

001

NC

8450 2000

4750

Compal Electronics, Inc.

PCIE/LVDS

LA-A551P

E

4750

NC

4750

NC

0.1

of

12 40Monday, May 06, 2013

of

12 40Monday, May 06, 2013

of

12 40Monday, May 06, 2013

A

+3VGS

1 1

RV12

1 8 2 7 3 6 4 5

10K_8P4R_5%

+3VGS

2 2

+3VGS

3 3

4 4

10K_8P4R_5%

CHECK VR

VR Suport PSI# and DPRSLPVR PU 10K

IF to +3VGS: PSI# :Low load current flag DPRSLPVR : Deeper sleep enable flag

GENERIC_X

ereo-sync signal.

St Indicates left/right frame, or top/bottom field. Can be left unconnected if not used.

Enable JTAG access

RV7

5.11K_0402_5%

@

1 2

Re

served signal, for normal ASIC operation.

RV9

RV9 1K_0402_5%

1K_0402_5%

VGA@

1 2

TSVDD MarsCRB Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

JTAG_TRSTB

JTAG_TDI JTAG_TMS JTAG_TCK

@

RV13

1 8

GPIO_16

2 7

GPIO_28_FDO

3 6

VGA_SMB_CK2

4 5

VGA_SMB_DA2

VGA@

GPU_DPRSLPVR<3 7>

VGA@

1 2

RV11 10K_0402_5%

GPU_DOWN#<27>

GPU_VID5<37>

GPU_VID1<37>

GPU_VID2<37>

CLKREQ_PEG#<8>

VGA@

RV14 10K_0402_5%

1 2

GPU_VID3<37> GPU_VID4<37>

PX_EN :

Hi

gh (3.3 V) switches the regulators off (enter BACO mode). Low (0 V) switches the regulators on. (Default)

TESTEN

GPIO_28_FDO

H

L

LV3

VGA@ LV3

VGA@

1 2

BLM15BD121SN1D_0402

A

MLPS

Disable

Enable

RV8

+TSVDD+1.8VGS

1

CV17

2

VGA@ CV17

VGA@

VGA_SMB_CK2 VGA_SMB_DA2

GPU_DPRSLPVR

GPU_VID5

TV1TP@TV1TP@

GPU_GPIO8

TV2TP@TV2TP@

GPU_GPIO9

TV3TP@TV3TP@

GPU_GPIO10

GPU_VID1

GPIO_16

10K_0402_5%@

1 2

GPU_VID2

TV4TP@TV4TP@

GPU_GPIO21

TV5TP@TV5TP@

GPU_GPIO22 CLKREQ_PEG#

GPU_VID3 GPU_VID4

TV9

TP@

PX_EN

JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS

TV7TP@TV7TP@

JTAG_TDO

GPIO_28_FDO

(1.8V@13mA TSVDD)

+TSVDD

1

CV18

CV19

2

1U_0402_6.3V6K

10U_0603_6.3V6M

VGA@ CV18

VGA@

VGA@ CV19

VGA@

UV1B

PART 2 0F 9

MUTI GFX

AD29

GENLK_CLK

AC29

GENLK_VSYNC

AJ21

SWAPLOCKA

AK21

SWAPLOCKB

AR8

NC

AU8

NC

AP8

DBG_CNTL0

AW8

NC

AR3

NC

AR1

NC

AU1

DBG_DATA0

AU3

DBG_DATA1

AW3

DBG_DATA2

AP6

DBG_DATA3

AW5

DBG_DATA4

AU5

DBG_DATA5

AR6

DBG_DATA6

AW6

DBG_DATA7

AU6

DBG_DATA8

AT7

DBG_DATA9

AV7

DBG_DATA10

AN7

DBG_DATA11

AV9

DBG_DATA12

AT9

DBG_DATA13

AR10

DBG_DATA14

AW10

DBG_DATA15

AU10

DBG_DATA16

AP10

DBG_DATA17

AV11

DBG_DATA18

AT11

DBG_DATA19

AR12

DBG_DATA20

AW12

DBG_DATA21

AU12

DBG_DATA22

AP12

DBG_DATA23

AJ23

SMBCLK

AH23

SMBDATA

AK26

SCL

AJ26

SDA

GENERAL PURPOSE I/O

AH20

GPIO_0

AH18

GPIO_1

AN16

GPIO_2

AH17

GPIO_5_AC_BATT

AJ17

GPIO_6_TACH

AK17

GPIO_7_BLON

AJ13

GPIO_8_ROMSO

AH15

GPIO_9_ROMSI

AJ16

GPIO_10_ROMSCK

AK16

GPIO_11

AL16

GPIO_12

AM16

GPIO_13

AM14

GPIO_14_HPD2

AM13

GPIO_15_PWRCNTL_0

AK14

GPIO_16

AG30

GPIO_17_THERMAL_INT

AN14

GPIO_18_HPD3

AM17

GPIO_19_CTF

AL13

GPIO_20_PWRCNTL_1

AJ14

GPIO_21

AK13

GPIO_22_ROMCSB

AN13

CLKREQB

AG32

GPIO_29

AG33

GPIO_30

AJ19

GENERICA

AK19

GENERICB

AJ20

GENERICC

AK20

GENERICD

AJ24

GENERICE_HPD4

AH26

GENERICF_HPD5

AH24

GENERICG_HPD6

AC30

CEC_1

AK24

HPD1

AH13

DBG_VREFG

AL21

PX_EN

AD28

TESTEN

AM23

JTAG_TRSTB

AN23

JTAG_TDI

AK23

JTAG_TCK

AL24

JTAG_TMS

AM24

JTAG_TDO

THERMAL

AF29

DPLUS

AG29

DMINUS

AK32

GPIO_28_FDO

AL31

TS_A

AJ32

TSVDD

AJ33

TSVSS

0.1U_0402_16V4Z

DEBUG

DPA

DPB

DPC

DPD

SMBus

I2C

DAC1

MLPS

BACO

DDC/AUX

DDCVGACLK

DDCVGADATA

SUN-PRO M2_FCBGA962VGA@

AVSSN

HSYNC VSYNC

AVDD

AVSSQ

VDD1DI

VSS1DI

NC_SVI2 NC_SVI2 NC_SVI2

DDC1CLK

DDC1DATA

AUX1P AUX1N

DDC2CLK

DDC2DATA

AUX2P AUX2N

B

C

D

E

MLPS

AU24

NC

AV23

NC

AT25

NC

AR24

NC

AU26

NC

AV25

NC

AT27

NC

AR26

NC

AR30

NC

AT29

NC

AV31

NC

AU30

NC

AR32

NC

AT31

NC

AT33

NC

AU32

NC

AU14

NC

AV13

NC

AT15

NC

AR14

NC

AU16

NC

AV15

NC

AT17

NC

AR16

NC

AU20

NC

AT19

NC

AT21

NC

AR20

NC

AU22

NC

AV21

NC

AT23

NC

AR22

NC

AD39

R

AD37

AE36

G

AD35

AF37

B

AE38

AC36 AC38

AB34

RSET

AD34 AE34

AC33 AC34

V13

NC

U13

NC

AF33

NC

AF32

NC

AA29

NC

AG21

NC

AC32

NC

AC31 AD30 AD32

AM34

PS_0

AD31

PS_1

AG31

PS_2

AD33

PS_3

AM26 AN26

AM27 AL27

AM19 AL19

AN20 AM20

AL30

NC

AM30

NC

AL29

NC

AM29

NC

AN21

NC

AM21

NC

AK30

NC

AK29

NC

AJ30 AJ31

B

Mars MLPS configuration

Bits[5:1]

xx

000

xx001

xx010

xx011

xx100

xx101

xx110

xx111

00xxx

01xxx

10xxx

11xxx

Pin Name

GPIO_0

GPIO_5_AC_BATT

GPIO_6

GPIO_15_PWRCNTL_0

GPIO_20_PWRCNTL_1

GPIO_29

GPIO_30

GPIO_8_ROMSO

GPIO_9_ROMSI

GPIO_10_ROMSCK

GPIO_22_ROMCSB

GPIO_17_THERMAL_INT

GPIO_19_CTF

GPIO_21

GPIO_28_FDO

CLKREQB

PX_EN

PD(1%) CapPU(1%)

NC 4.75k

8.45k 2.00k

4.53k 2.00k

6.98k 4.99k

4.53k 4.99k

3.24k 5.62k

3.40k 10.0k

4.75k NC

Type PD/PU Description

I/O

3.3 V (VDDR3)

I/O

3.3 V (VDDR3)

I/O

3.3 V (VDDR3)

I

3.3 V (VDDR3)

O

3.3 V (VDDR3)

I/O

3.3 V (VDDR3)

O

3.3 V (VDDR3)

I/O

3.3 V (VDDR3)

I/O

3.3 V (VDDR3)

O

O PD

Primary Memory Aperture Size Requested at PCI Configuration

Size of the Primary

emory Apertures

M

ROM_CONFIG [2:0]

128 MB

256 MB

64 MB

Reserved

512 MB

680nF

82nF

10nF

NC

PD-reset

1 GB

2 GB

4 GB Not supported

Power-state indicator. Permits the voltage regulator to activate power-saving features. IF VR Suport PSI# and DPRSLPVR PU 10K to +3VGS. PSI# :Low load current flag DPRSLPVR : Deeper sleep enable flag

(Optional) An input which allows the system to request a fastpower reduction by setting GPIO_5_AC_BATT to low (0 V). The resulting state transition may disturb the display momentarily. Power reductions that are less time critical should use the standard software methods in order to prevent display disturbances.

Voltage control signals for the core (VDDC and VDDCI). At reset, these signals will be inputs with weak internal pulldown resistors. The VBIOS can define all voltage-control signals to be either 3.3-V or open-drain outputs (all signals must be the same type). The output states (high/low) of these pins are programmable for each AMD PowerPlay state when they are used as voltage control signals. Note: GPIO_29 and GPIO_30 are only available on 28-nm ASICs, and are NC on earlier generation ASICs.

Serial-ROM output from ROM. General purpose I/O or open-drain output.

Design: No use external VGA ROM, so use the test point.

Serial-ROM input to ROM. General purpose I/O or open-drain output.

Serial-ROM clock to ROM. General purpose I/O or open-drain output.

BIOS-ROM chip select. Used to enable the ROM for ROM read and program operations.

Design: No use external VGA ROM, so use the test po

ints.

Thermal monitor interrupt. An input from an external temperature sensor (ALERTb).

Critical temperature fault (CTF) (active high) will output 3.3 V if the on-die temperature sensor exceeds a critical temperature so that the motherboard can protect the ASIC from damage by removing power. The CTF setpoint is 109 by default, and is programmed during ASIC initialization. See the advisory for AMD PowerPlay states for more details.

(Optional) Voltage control signal for the memory-voltage regulator. Note: This signal must be low (0 V) at reset (failure to do so will prevent booting).

Disable MLPS: PU 10K ohm to 3.3V. (Do not install for Mars) Enable MLPS: PD 10K ohm to GND. (Install for Mars)

Supports the CLKREQB feature for saving power to turn on/off the REFCLK clock on the ASIC.

On/off regulator switch in AMD PowerXpress? (switchable graphics) BACO mode. High (3.3 V) switches the regulators off (enter BACO mode). Low (0 V) switches the regulators on. (Default) PX_EN is tri-state before internal TEST_PG is asserted and PERSTb is deasserted.

Not supported

℃℃℃℃

C

000

001

010

011

MLPS Bit Strap Name Description Settings

ROM_CONFIG[0]

PS_0[1]

ROM_CONFIG[1]

PS_0[2]

ROM_CONFIG[2]

PS_0[3]

PS_0[4] N/A

STRAP_BIF_

PS_1[1]

GEN3_EN_A

PS_1[2] STRAP_BIF_

CLK_PM_EN

PS_1[3] N/A Reserved for internal use only. Must be 0 at reset.

PS_1[4] TX_PWRS_ENB

PS_1[5] TX_DEEMPH_EN

PS_2[1]

N/A

PS_2[2]

N/A

PS_2[3] BIOS_ROM_EN

PS_2[4] BIF_VGA_DIS

PS_2[5] N/A Reserved.

PS_3[1]

BOARD_CONFIG[0]

PS_3[2]

BOARD_CONFIG[1]

PS_3[3]

BOARD_CONFIG[2]

PS_0[5]

AUD_PORT_CONN_

PS_3[4]

PINSTRAP[0]

PS_3[5]

AUD_PORT_CONN_ PINSTRAP[1]

AUD_PORT_CONN_ PINSTRAP[2]

MLPS Strap

1 1

PS_0[5:1]

1 1

PS_1[5:1]

0 0

PS_2[5:1]

1 1

PS_3[5:1]

PS_0 PS_1 PS_2 PS_3

@

VGA@

1

CV22

CV20

CV21

2

0.01U_0402_16V7K

0.68U_0402_10V6K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Legacy

GPIO[13:11]

GENLK_VSYNC

GPIO_2

GPIO_8

If BIOS_ROM_EN = 1, ROM_CONFIG[2:0] define the ROM type. If BIOS_ROM_EN = 0, ROM_CONFIG[2:0] define the primary memory-aperture size. Refer to current databooks for details.

Reserved for internal use only. Must be 1 at reset.

Re-defined strap to indicate PCIe GEN3 capability. 1 = PCIe GEN3 supported. 0 = PCIe GEN3 not supported.

Determines whether or not the PCIe reference clock power management capability is reported in the PCI configuration space (otherwise known as CLKREQB). 0 = The CLKREQB power management capability is disabled 1 = The CLKREQB power management capability is enabled

GENLK_CLK

GPIO_0

GPIO_1

N/A

GPIO_22

GPIO_9

Transmitter (Tx) power savings enable. 0 = 50% Tx output swing. 1 = Full Tx output swing.

PCI EXPRESS transmitter, deemphasis enable. 0 = Tx deemphasis disabled. 1 = Tx deemphasis enabled.

Reserved.

To enable the external BIOS ROM device. 0 = Disable the external BIOS ROM device. 1 = Enable the external BIOS ROM device.

VGA disable determines whether or not the card will be recognized as the system's VGA controller. 0 = VGA controller capacity enabled. 1 = The device will not be recognized as the system’s VGA controller.

N/A

CapacitorBits[5:4]

Bits[3:1]

0 0 1

NC

0 0 1

NC

0 0 0

680 nF

X X X

NC

Mapping to VRAM type please refer to page 6

@

RV20

8.45K_0402_1%

@

1

CV23

2K_0402_1%

2

0.01U_0402_16V7K

2013/05/15 2015/09/27

Board configuration related strapping (such as memory ID).

Together with PS_0[5] form the three-bit strap option to indicate the number of audio-capable display outputs. In a given ASIC there are as many endpoints as there are digital display outputs, though not all outputs are audio capable. 111 = No usable endpoints. 110 = One usable endpoint. 101 = Two usable endpoints. 100 = Three usable endpoints. 011 = Four usable endpoints. 010 = Five usable endpoints. 001 = Six usable endpoints. 000 = All endpoints are usable.

R_pu R_pd

8.45K 2K

8.45K

2K

NC

4.75K

X

12

@

RV21

8.45K_0402_1%

12

VGA@

@

RV28

RV27

D

4.75K_0402_1%

Compal Secret Data

Deciphered Date

@

RV22

VGA@

RV68

12

8.45K_0402_1%

12

2K_0402_1%

VGA@

RV23

VGA@

RV30

+1.8VGS

001

1

0

1

0

Base on VRAM ID

111

12

+3VGS

2

VGA@

12

VGA_SMB_CK2

VGA_SMB_DA2

Title

Size Document Numbe r Rev

Custom

Date: Sheet

VGA@

61

QV1A

DMN66D0LDW-7 2N_SOT363-6

4

DMN66D0LDW-7 2N_SOT363-6

Compal Electronics, Inc.

Main_MSIC

LA-A551P

E

VGA@QV1B

VGA@

3

EC_SMB_CK2 <27,6>

EC_SMB_DA2 <27,6>

13 40Monday, May 06, 2013

of

0.1

5

QV1B