Compal LA-A481P ZRMAA, Satellite E55, LA-A481P ZEMAA Schematic

A

1 1

B

C

D

E

Compal Confidential

ZRMAA/ZEMAA Schematics Document

2 2

Haswell ULT with DDR3L

nVIDIA N14P-GV2 (Dual Rank) nVIDIA N14M-GL

LA-A481P REV 0.1 Schematic

3 3

Intel Processor (Haswell)

2013-02-22 Rev 0.1

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

ZRMAA/ZEMAA

1 49Sunday, April 07, 2013

E

0.1

A

B

C

D

E

VGA (DDR3)

nVIDIA N14P-GV2 & N14M-GL

1 1

page 18~26

PCI-Express 4X Gen3 8GT/s

eDP 1X 5.4GT/s

Intel Haswell ULT

Memory BUS(DDR3L)

Dual Channel

1.35V DDR3L 1333/1600 MT/s

204pin DDR3-SO-DIMM X2

BANK 0, 1, 2

page 16,17

LVDS Conn. Colay eDP

page 28

LVDS Translator RTD2132S (Single)

page 27

HDMI Conn.

page 30

2 2

PCIeMini Card W

LAN

PCIe port 4

page 34

PCIeMini Card WIMAX

SATA HDD

Sub Boards

CardReader RTS5176(Port 3) +USB (Port 2)+Audio Combo jack

page 35

3 3

Touch pad/LED B

page 41

SATA SSD

USB20 port 4

page 34

SATA port 0

page 33

SATA port 1

page 33

PCIe Gen1 1x

1.5V 5GT/s

USB20 1x

5V 480MHz

SATA Gen3 port 0

5V 6GHz(600MB/s)

SATA Gen3 port 1

5V 6GHz(600MB/s)

LPC BUS

3.3V 33 MHz

Haswell ULT

Processor

OPI

Lynx Point - LP

PCH

1168pin BGA

page 05~15

HD Audio

3.3V 24MHz

USB30 2x

5V 5GT/s

USB20 2x

5V 480MHz

USB20 1x

5V 480MHz

USB20 1x

5V 480MHz

USB20 1x

5V 480MHz

SLG3NB282VTR page 34

USB3.0 x2 Right

USB20 port 0,1 USB30 port 1,2

page 37

CardReader Connector

USB20 port 3

page 36

Touch Screen

USB20 port 5

page 28

Int. Camera

USB20 port 7

page 28

GCLK

RTC CKT.

page 7

SPI ROM (8MB)

page 8

KB9012

page 40

HDA Codec

ALC282 (w/ S&M)

page 38

DC/DC Interface CKT.

page 42

Power Circuit DC/DC

4 4

page 43~51

Touch Pad

Int.KBD

page 41page 41

G-Sensor

page 33

SPK Conn

page 39

JHP

page 39

Power On/Off CKT.

page 41

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

ZRMAA/ZEMAA

2 49Sunday, April 07, 2013

E

0.1

A

B+

1 1

SUSP#

RT8243AZQW

TPS22966DPUR

SUSP#

SY8208DQNC

2 2

SUSP#

TPS22966DPUR

PCH_PWR_EN#

P-CHANNEL

-3413

AO

WOWL_EN#

P-CHANNEL

SUSP#

AO-3413

TPS51362RVER

3 3

PCH_PWR_EN

TPS51212DSCR

VR_ON

TPS51622RSM

SYSON

RT8207MZQW

4 4

+3VS_DGPU

NCP81172MNTWG

B

USB_EN#0

SY6288DCAC

USB_CHG_EN#

G547N2P81U

USB_EN#2

SY6288DCAC

+5VS

AP2151DWG-7

KB_LED

A03413-SOT23

VGA_PWROK

2N7002

LCD_ENVDD

APL3512ABI-TRG

DGPU_PWR_EN

P-CHANNEL

AO-3413

1.5V_PWR_EN

FDS6676AS

SUSP

P-

CHANNEL

AO-3413

DESIGN CURRENT 26mA

DESIGN CURRENT 12.47A

DESIGN CURRENT 2A

DESIGN CURRENT 5.61A

DESIGN CURRENT 2A

DESIGN CURRENT 50mA

DESIGN CURRENT 10.5A

DESIGN CURRENT 5.13A

DESIGN CURRENT 5.824A

DESIGN CURRENT 4.873A

DESIGN CURRENT 2.0A

DESIGN CURRENT 1.02A

DESIGN CURRENT 451mA

DESIGN CURRENT 500mA

DESIGN CURRENT 27.821A

DESIGN CURRENT 11A

DESIGN CURRENT 15.9A

DESIGN CURRENT A

DESIGN CURRENT 32A

DESIGN CURRENT 6A

DESIGN CURRENT 1.5A

DESIGN CURRENT 55.2A

C

+3VL +5VALW

+USB_VCCB

+USB_VCCA

+USB_VCCC

+5VS

+HDMI_5V_OUT

+5VS_LED

+1.05VS_VTT

+1.05VS_DGPU

+3VALW

+3VS

+LCD_VDD

+3VS_DGPU

+3VS_RT +3VALW_PCH +3V_LAN

+3V_WLAN

+1.5VS

+1.5VSDGPU

+VRAM_1.5VS

+1.5VS

+CPU_CORE

+1.35V

+0.675VS

+VGA_CORE

D

E

+LCD_INV

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/10/25 2013/10/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Power Map

ZRMAA/ZEMAA

E

0.1

3 49Sunday, April 07, 2013

0.1

A

Voltage Rails

power plane

1 1

State

( O MEANS ON X MEANS OFF )

+RTCVCC

B+

+5VL +3VL

B

+5VALW +3VALW +1.5VALW +VSB

+1.35V

+5VS +3VS +1.8VS_CRT +1.5VS +CPU_CORE +VGA_CORE +VRAM_1.5VS +3VS_DGPU +1.05VS_DGPU +1.05VS_VTT

C

Platform

BTO Option Table

Function

description

SKU

D

SKU CPU PCH VGA

nVIDIA N13P-GL (N13PGL@)

MIC

LAN

E

explain

BTO

S0

S1

S3

2 2

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

O O O O O O

O O O O O

X

O O O O O

X

O O O O

X X

O

X X X X X

OO OO

X

Function

description

X

explain

BTO

Function

PCH SM Bus Address

Power

+3VS +3VS

Device

DDR SO-DIMM 0 DDR SO-DIMM 1

HEX

Address

1010 0000 bA0 H 1010 0100 bA4 H

description

explain

BTO

Function

3 3

description

explain

BTO

EC SM Bus1 Address

Device Address Address

+3VL

4 4

HEX HEX

6 H

1

0001 0110 bSmart Battery

12 HSmart Charger 0001 0010 b+3VL

Pow

+3VS +3VS

HEXDevice AddressPower

EC SM Bus2 Address

Device

erPower

96 H

NVIDIA GPU 1001 1010 b

9E H

STATE

Full ON

1001 0110 bPCH

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

G3 LO

SIGNAL

SLP_S3# SLP_S4# SLP_S5#

HIGH HIGHHIGH

LOW

LOW LOW

W LOWLOW

HIGH HIGHHIGH

HIGH

LOW LOWLOW

HIGH

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/07/10 2013/07/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Notes List

ZRMAA/ZEMAA

0.1

4 49Sunday, April 07, 2013

E

0.1

5

4

3

U1A

HASWELL_MCP_E

2

1

C54

DDI1_TXN0

C55

DDI1_TXP0

B58

DDI1_TXN1

C58

DDI1_TXP1

B55

DDI1_TXN2

A55

DDI1_TXP2

A57

DDI1_TXN3

B57

D D

HDMI

H_PECI<36>

ESD@

H_CPUPW RGD

C C

+1.35V

12

R184 470_0603_5%

CH11100P_0402_50V8J

+1.05VS_VTT

H_PROCHOT#<36>

H_HDMI_TX2-<29> H_HDMI_TX2+<29> H_HDMI_TX1-<29> H_HDMI_TX1+<29> H_HDMI_TX0-<29> H_HDMI_TX0+<29> H_HDMI_TXC-<29> H_HDMI_TXC+<29>

12

R68

62_0402_5%

1 2

R6 10K_0402_5%

1 2

R11 200_0402_1%

1 2

R13 120_0402_1%

1 2

R41 100_0402_1%

DIMM_DRAMRST#<16,17>

DDR_PG_CTRL<16>

R8 56_0402_5%

1 2

T20 @ T97 @

H_PROCHOT#_R

H_CPUPW RGD

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 DIMM_DRAMRST#

C51 C50 C53 B54 C49 B50 A53 B53

D61 K61 N62

K63

C61

AU60 AV60 AU61 AV15 AV61

DDI1_TXP3 DDI2_TXN0

DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3

U1B

PROC_DETECT CATERR PECI

PROCHOT

PROCPWRGD

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_DRAMRST SM_PG_CNTL1

DDR3 Compensation Signals

ESD@

DIMM_DRAMRST#

12

DIMM_DRAMRST#

CH70.1U_0402_10V7K

DDI EDP

1 OF 19

HASWELL_MCP_E

MISC

JTAG

THERMAL

PWR

DDR3

2 OF 19

EDP_AUXN EDP_AUXP

EDP_RCOMP

EDP_DISP_UTIL

EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1

EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3

Rev1p2

PRDY

PREQ PROC_TCK PROC_TMS

PROC_TRST

PROC_TDI

PROC_TDO

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

Rev1p2

C45 B46 A47 B47

C47 C46 A49 B49

A45 B45

D20 A43

H_EDP_TXN0 <27> H_EDP_TXP0 <27> H_EDP_TXN1 <27> H_EDP_TXP1 <27>

H_EDP_AUXN <27> H_EDP_AUXP <27>

1 2

R1 24.9_0402_1%

Trace width=20 mils,Spacing=25mil,Max length=100mils

T154@

T155@ T156@ T148@ T149@ T150@ T151@ T152@ T153@

J62 K62 E60 E61 E59 F63 F62

J60 H60 H61 H62 K59 H63 K60 J61

EDP_COMP

XDP_PRDY# XDP_PREQ# XDP_TCK XDP_TMS XDP_TRST# XDP_TDI XDP_TDO

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

PU/PD for JTAG signals

+VCCIOA_OUT

+1.05VS_VTT

B B

A A

Security Classification

2012/07/10 2013/07/10

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/07/10 2013/07/10

3

Compal Secret Data

Deciphered Date

2

XDP_TMS XDP_TDI XDP_PREQ# XDP_TDO

XDP_TCK XDP_TRST#

Title

Size Document Number Rev

Custom

Date: Sheet of

HSW MCP(1/11) DDI,MSIC,XDP

ZRMAA/ZEMAA

1 2

R86 51_0402_5%@

1 2

R87 51_0402_5%XDP@

1 2

R88 51_0402_5%@

1 2

R89 51_0402_5%XDP@

1 2

R90 51_0402_5%XDP@

1 2

R91 51_0402_5%@

Compal Electronics, Inc.

1

0.1

5 49Sunday, April 07, 2013

5

4

3

2

1

U1C

AH63

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4

D D

C C

B B

DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

AH62 AK63 AK62 AH61 AH60 AK61 AK60 AM63 AM62 AP63 AP62 AM61 AM60 AP61 AP60 AP58 AR58 AM57 AK57

AL58 AK58 AR57 AN57 AP55 AR55 AM54 AK54

AL55 AK55 AR54 AN54 AY58

AW58

AY56

AW56

AV58 AU58 AV56 AU56 AY54

AW54

AY52

AW52

AV54 AU54 AV52 AU52 AK40 AK42 AM43 AM45 AK45 AK43 AM40 AM42 AM46 AK46 AM49 AK49 AM48 AK48 AM51 AK51

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

HASWELL_MCP_E

DDR CHANNEL A

SA_CLK#0

SA_CLK0

SA_CLK#1

SA_CLK1

SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3

SA_CS#0 SA_CS#1

SA_ODT0

SA_RAS

SA_WE

SA_CAS SA_BA0

SA_BA1 SA_BA2

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7

SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7

SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1

AU37 AV37 AW36 AY36

AU43 AW43 AY42 AY43

AP33 AR32

AP32 AY34

AW34 AU34

AU35 AV35 AY41

AU36 AY37 AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40 AP35 AW41 AU41 AR35 AV42 AU42

AJ61 AN62 AM58 AM55 AV57 AV53 AL43 AL48

AJ62 AN61 AN58 AN55 AW57 AW53 AL42 AL49

AP49 AR51 AP51

DDRA_ODT0

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

SA_CLK_DDR#0 <16> SA_CLK_DDR0 <16> SA_CLK_DDR#1 <16> SA_CLK_DDR1 <16>

DDRA_CKE0_DIMMA <16> DDRA_CKE1_DIMMA <16>

DDRA_CS0_DIMMA# <16> DDRA_CS1_DIMMA# <16>

T4@

DDR_A_RAS# <16>

DDR_A_WE# <16>

DDR_A_CAS# <16>

DDR_A_BS0 <16> DDR_A_BS1 <16> DDR_A_BS2 <16>

DDR_A_D[0..63]<16>

DDR_A_MA[0..15]<16>

DDR_A_DQS#[0..7]<16>

DDR_A_DQS[0..7]<16>

SM_DIMM_VREFCA <16> SA_DIMM_VREFDQ <16> SB_DIMM_VREFDQ <17>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AY31

AW31

AY29

AW29

AV31

AU31

AV29

AU29

AY27

AW27

AY25

AW25

AV27

AU27

AV25 AU25 AM29

AK29

AL28

AK28 AR29 AN29 AR28

AP28 AN26 AR26 AR25

AP25

AK26 AM26

AK25

AL25

AY23 AW23

AY21 AW21

AV23 AU23

AV21 AU21

AY19 AW19

AY17 AW17

AV19 AU19

AV17 AU17 AR21 AR22

AL21 AM22 AN22

AP21

AK21

AK22 AN20 AR20

AK18

AL18

AK20 AM20 AR18

AP18

U1D

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

HASWELL_MCP_E

DDR CHANNEL B

SB_CK#0

SB_CK0

SB_CK#1

SB_CK1

SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3

SB_CS#0 SB_CS#1

SB_ODT0

SB_RAS

SB_WE

SB_CAS SB_BA0

SB_BA1 SB_BA2

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7

SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7

AM38 AN38 AK38 AL38

AY49 AU50 AW49 AV50

AM32 AK32

AL32 AM35

AK35 AM33

AL35 AM36 AU49

AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46

AW30 AV26

DDR_B_DQS#1

AN28

DDR_B_DQS#2

AN25

DDR_B_DQS#3

AW22

DDR_B_DQS#4

AV18

DDR_B_DQS#5

AN21

DDR_B_DQS#6

AN18

DDR_B_DQS#7

AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18

DDRB_ODT0

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

DDR_B_DQS#0

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_D[0..63]<17>

DDR_B_MA[0..15]<17>

DDR_B_DQS#[0..7]<17>

DDR_B_DQS[0..7]<17>

SB_CLK_DDR#0 <17> SB_CLK_DDR0 <17> SB_CLK_DDR#1 <17> SB_CLK_DDR1 <17>

DDRB_CKE0_DIMMB <17> DDRB_CKE1_DIMMB <17>

DDRB_CS0_DIMMB# <17> DDRB_CS1_DIMMB# <17>

T5@

DDR_B_RAS# <17> DDR_B_WE# <17> DDR_B_CAS# <17>

DDR_B_BS0 <17> DDR_B_BS1 <17> DDR_B_BS2 <17>

3 OF 19

A A

5

Rev1p2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/07/10 2013/07/10

Compal Secret Data

Deciphered Date

4 OF 19

2

Rev1p2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

HSW MCP(2/11) DDRIII

ZRMAA/ZEMAA

1

6 49Sunday, April 07, 2013

0.1

5

4

3

2

1

PCH_RTCX1_R<31>

D D

+RTCVCC

1 2

RH26 0_0402_5%

CMOS Setting, near DDR Door

1 2

RH23 20K_0402_5%

iME Setting.

1 2

RH24 20K_0402_5%

PCH_INTVRMEN

INTVRMEN

H：Integrated VRM enable

*

C C

L

：

1 2

R73 330K_0402_5%

Integrated VRM disable

GCLK@

PCH_SRTCRST#

PCH_RTCX1

PCH_RTCRST#

1U_0402_6.3V6K

CH4

CH5

+RTCVCC

JCMOS @

1 2 1 2

JME @

1 2 1 2

+RTCVCC

1 2

R72 1M_0402_5%

AZ_SDIN0_HD<35>

1 2

R9851_0402_5% @

T138 @

T6 @ T7 @

T8 @ T9 @

T95 @ T21 @

T19 @ T15 @ T10 @ T11 @ T22 @ T12 @

PCH_RTCX1 PCH_RTCX2 SM_INTRUDER# PCH_INTVRMEN PCH_SRTCRST# PCH_RTCRST#

HDA_BIT_CLK HDA_SYNC HDA_RST#

HDA_SDOUT

PCH_JTAG_RST# PCH_JTAG_TDI

PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TCK_JTAGX

U1E

AW5

RTCX1

AY5

RTCX2

AU6

INTRUDER

AV7

INTVRMEN

AV6

SRTCRST

AU7

RTCRST

AW8

HDA_BCLK/I2S0_SCLK

AV11

HDA_SYNC/I2S0_SFRM

AU8

HDA_RST/I2S_MCLK

AY10

HDA_SDI0/I2S0_RXD

AU12

HDA_SDI1/I2S1_RXD

AU11

HDA_SDO/I2S0_TXD

AW10

HDA_DOCK_EN/I2S1_TXD

AV10

HDA_DOCK_RST/I2S1_SFRM

AY8

I2S1_SCLK

AU62

PCH_TRST

AE62

PCH_TCK

AD61

PCH_TDI

AE61

PCH_TDO

AD62

PCH_TMS

AL11

RSVD

AC4

RSVD

AE63

JTAGX

AV2

RSVD

HASWELL_MCP_E

RTC

JTAG

5 OF 19

SATA_IREF

RSVD RSVD

SATALED

Rev1p2

J5 H5 B15 A15

J8 H8 A17 B17

J6 H6 B14 C15

F5 E5 C17 D17

V1 U1 V6 AC1

A12 L11 K10 C12 U3

PU at Page09

EC_SMI# ODD_DETECT#

T159@ T165@

SATA_IREFPCH_JTAG_TCK

T13@ T14@

SATA_RCOMP

SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3

SATA_TN0/PETN6_L3 SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2

SATA_TN1/PETN6_L2 SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1

SATA_TN2/PETN6_L1

SATAAUDIO

SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0 SATA_RP3/PERP6_L0

SATA_TN3/PETN6_L0 SATA_TP3/PETP6_L0

SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37

SATA_RCOMP

SATA_PRX_C_DTX_N0 <30> SATA_PRX_C_DTX_P0 <30> SATA_PTX_DRX_N0 <30> SATA_PTX_DRX_P0 <30>

SATA_PRX_C_DTX_N1 <33> SATA_PRX_C_DTX_P1 <33> SATA_PTX_DRX_N1 <33> SATA_PTX_DRX_P1 <33>

EC_SMI# <36>

ODD_DETECT# <10>

@

1 2

R75 0_0603_5%

within 500 mils

1 2

R2 3.01K_0402_1%

HDD

SSD

+1.05VS_ASATA3PLL

HDA for AUDIO

RP14

AZ_RST_HD#<35> AZ_BITCLK_HD<35> AZ_SDOUT_HD<35> AZ_SYNC_HD<35>

PWRME_CTRL<36>

1 8 2 7 3 6 4 5

33_0804_8P4R_5%

1 2

R163 0_0402_5%

HDA_RST# HDA_BIT_CLK HDA_SDOUT HDA_SYNC

ME Debug

B B

+RTCBATT

1

+RTCVCC

3

1

CH8

0.1U_0402_10V7K

2

A A

5

4

DH1 BAS40-04_SOT23-3

2

+3VL

Security Classification

2012/07/10 2013/07/10

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/07/10 2013/07/10

3

Compal Secret Data

Deciphered Date

FAN Control Circuit

+3VS

12

R33 10K_0402_5%

+5VS

FAN_SPEED1<36>

1A

1 2

R32 0_0603_5%

2

+FAN1

1

C4

0.01U_0402_25V7K

@

2

JFAN

6

G2

5

G1

4

1

2

C5

3

2

1

E&T_3802-F04N-01R

@

7 49Sunday, April 07, 2013

1

FANPWM<36>

+FAN1

12

D1

BAS16_SOT23-3

Title

Size Document Number Rev

Custom

ZRMAA/ZEMAA

Date: Sheet of

10U_0603_6.3V6M

Compal Electronics, Inc.

HSW MCP(3/11) RTC,SATA,XDP

0.1

5

4

3

2

1

RH42

PCH_X1_R<31>

12

D D

C C

B B

NOGCLK@

24MHZ_12PF_7A24000134

1

C2 12P_0402_50V8J

2

NOGCLK@

+3VALW _PCH

RH5 1K_0402_5% RH16 1K_0402_5%

R481M_0402_5%

Y2

1 2

NOGCLK@

+3VS

12 12

EC_CS0#<36>

EC_SDIO<36>

PCH_X1 PCH_X1 PCH_X2

1

C3 12P_0402_50V8J

2

NOGCLK@

PCH_SPIDO1 PCH_SPIDO2

1 2

PCH_SPIDO2 PCH_SPIDO3

1 2

RH61 15_0402_5%885@

1 2

RH68 15_0402_5%

1 2

RH69 15_0402_5%

1 2

RH72 15_0402_5%885@

PCIE LAN

CLK_REQ_VGA#

RH8910K_0402_5%

SPI ROM for BIOS & ME & Win8 (8MByte )

1 2

0_0402_5%

GCLK@

Placement near to YH2

WLAN

PCH_SPICS0# PCH_SPI0_DO1 PCH_SPI0_DO2

PCH_X1

CLK_LAN#<32> CLK_LAN<32>

+3VS CLKREQ_LAN#<32> CLK_WLAN#<31> CLK_WLAN<31> CLKREQ_WLAN#<10,31>

CLK_PCIE_VGA#<18> CLK_PCIE_VGA<18> CLK_REQ_VGA#<18>

UH3

1

CS#

2

SO

3

WP#

4

GND

64M EN25QH64-104HIP SOP 8P

VCC

HOLD#

SCLK

8 7 6 5

SI

T158 @

PCH_GPIO19

1 2

R52 10K_0402_5%

CLK_REQ_VGA#

T160 @

1 2 1 2 1 2

1 2 1 2

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME#

PCH_SPICLK PCH_SPICS0#

PCH_SPIDI PCH_SPIDO1 PCH_SPIDO2 PCH_SPIDO3

LPC_AD0<36> LPC_AD1<36> LPC_AD2<36> LPC_AD3<36>

LPC_FRAME#<36>

+3VALW _PCH

CH9 0.1U_0402_10V7K

1 2

PCH_SPI0_DO3 PCH_SPIDO3 PCH_SPI0_CLK PCH_SPI0_DI

RH65 15_0402_5% RH66 0_0402_5%@ RH67 15_0402_5%

RH74 15_0402_5%885@ RH78 15_0402_5%885@

U1F

C43

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

U2

PCIECLKRQ0/GPIO18

B41

CLKOUT_PCIE_N1

A41

CLKOUT_PCIE_P1

Y5

PCIECLKRQ1/GPIO19

C41

CLKOUT_PCIE_N2

B42

CLKOUT_PCIE_P2

AD1

PCIECLKRQ2/GPIO20

B38

CLKOUT_PCIE_N3

C37

CLKOUT_PCIE_P3

N1

PCIECLKRQ3/GPIO21

A39

CLKOUT_PCIE_N4

B39

CLKOUT_PCIE_P4

U5

PCIECLKRQ4/GPIO22

B37

CLKOUT_PCIE_N5

A37

CLKOUT_PCIE_P5

T2

PCIECLKRQ5/GPIO23

U1G

AU14

LAD0

AW12

LAD1

AY12

LAD2

AW11

LAD3

AV12

LFRAME

AA3

SPI_CLK

Y7

SPI_CS0

Y4

SPI_CS1

AC2

SPI_CS2

AA2

SPI_MOSI

AA4

SPI_MISO

Y6

SPI_IO2

AF1

SPI_IO3

PCH_SPICLK PCH_SPIDI

EC_SCK <36> EC_SDI <36>

HASWELL_MCP_E

CLOCK

SIGNALS

6 OF 19

HASWELL_MCP_E

LPC

SMBUS

SPI C-LINK

7 OF 19

XTAL24_IN

XTAL24_OUT

RSVD RSVD

DIFFCLK_BIASREF

TESTLOW_C35 TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8

CLKOUT_LPC_0 CLKOUT_LPC_1

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

Rev1p2

SMBALERT/GPIO11

SMBCLK

SMBDATA

SML0ALERT/GPIO60

SML0CLK

SML1ALERT/PCHHOT/GPIO73

SML0DATA

SML1CLK/GPIO75

SML1DATA/GPIO74

CL_CLK

CL_DATA

CL_RST

Rev1p2

DMN66D0LDW-7_SOT363-6

PCH_SMBDATA

PCH_SMBCLK

DMN66D0LDW-7_SOT363-6

A25 B25

K21 M21 C26

C35 C34 AK8 AL8

AN15 AP15

B35 A35

AN2 AP2 AH1 AL2 AN1 AK1 AU4 AU3 AH3

AF2 AD2 AF4

PCH_X2

T16@ T17@

XCLK_BIASREF

1 2

R140 10K_0402_5%

1 2

R141 10K_0402_5%

1 2

R142 10K_0402_5%

1 2

R148 10K_0402_5%

CLKOUT_LPC0

CLK_BCLK_ITP# CLK_BCLK_ITP

PCH_SMBCLK PCH_SMBDATA

PCH_SMLCLK1 PCH_SMLDATA1

SUSWARN#<9>

SLP_CHG_CB0<11,34>

USB_CHG_OC#<11,34,36>

+3VS

Q7A

2

6 1

3 4

Q7B

1 2

R78 3.01K_0402_1%

R390 22_0402_5%

T170@

T23@ T24@ T25@

4.7K_0402_5%

5

12

EMI@

T18@ T130@

SMB_ALERT# <10>

PCH_SMBDATA <10> LAN_EN <10,32> SML0CLK <10> SML0DATA <10>

PU 2.2K at EC side (+3VS)

PCH_SMBCLK

PCH_SMLCLK1 PCH_SMLDATA1

+3VS

R116

1 2

+1.05VS_AXCK_LCPLL

CLK_PCI_EC <36>

RP8

1 8 2 7 3 6 4 5

RH73 2.2K_0402_5% RH77 2.2K_0402_5%

R119

4.7K_0402_5%

PM_SMBDATA <16,17,31,33>

2.2K_0804_8P4R_5%

12 12

PM_SMBCLK <16,17,31,33>

+3VALW _PCH

Socket: SP07000F500/SP07000H900 Please place UH3 close to U1 CPU, Please place RH66, RH67, RH68 near UH3

PCH_SMLDATA1

PCH_SMLCLK1

A A

6 1

QH4A

2N7002DW-T/R7_SOT363-6

5

3

2

QH4B

2N7002DW-T/R7_SOT363-6

4

+3VS

EC_SMB_DA2 <18,36>

EC_SMB_CK2 <18,36>

Security Classification

2012/07/10 2013/07/10

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/07/10 2013/07/10

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HSW MCP(4/11) CLK,SPI,SMBUS

ZRMAA/ZEMAA

8 49Sunday, April 07, 2013

1

0.1

5

+3VS

12

R227 10K_0402_5%

SYS_RESET#

D D

PCH_PW ROK<36> VCCST_PG_EC<12,36>

12

PCH_RSMRST#

R11710K_0402_5%

+3VALW_PCH

12

R245

100K_0402_5%

D21

ACIN<36,41>

C C

B B

1 2

RB751V40_SC76-2

PCH_ACIN

PCH_RSMRST#<36>

ote for PCH_ACIN: Deep Sx need use

N EC

GPIO for ACPRESENT function

Need to Check

4

PCH_PW ROK

POK<36,42>

PLT_RST#<36>

SUSWARN#<8>

PBTN_OUT#<36>

1 2 1 2 1 2

R206 0_0402_5%@

0_0402_5%@

1 2

R63 0_0402_5%@

PCH_RSMRST# PCH_RSMRST#_R

+3VALW _PCH

PCH_PW M_TL<27> PCH_PW M_EDP<28>

EC_ENBKL<27,28,36>

1 2

R79

1 2

R156 8.2K_0402_5%

RH17 0_0402_5%LVDS@ RH18 0_0402_5%IEDP@ RH19 0_0402_5%IEDP@

LCD_ENVDD<28>

VGA_PW ROK<22,47>

DGPU_PW R_EN<10,22>

DGPU_HOLD_RST#<10>

TP_INTR#<10,33>

DH2

2

3

BAS40-04_SOT23-3

SUSACK#SUSWARN# SYS_RESET# SYS_PWROK PCH_PW ROK PM_APW ROK PLT_RST#

SUSWARN# PCH_ACIN

PCH_BATLOW#

PCH_PW M

EC_ENBKL_R

DGPU_HOLD_RST#

PCH_GPIO55

T157 @

PCH_GPIO54 PCH_GPIO51 PCH_GPIO53

1

T31 @

T26 @

3

PCH_RSMRST#

U1H

AK2

SUSACK

AC3

SYS_RESET

AG2

SYS_PWROK

AY7

PCH_PWROK

AB5

APWROK

AG7

PLTRST

AW6

RSMRST

AV4

SUSWARN/SUSPWRDNACK/GPIO30

AL7

PWRBTN

AJ8

ACPRESENT/GPIO31

AN4

BATLOW/GPIO72

AF3

SLP_S0

AM5

SLP_WLAN/GPIO29

U1I

B8

EDP_BKLCTL

A9

EDP_BKLEN

C6

EDP_VDDEN

U6

PIRQA/GPIO77

P4

PIRQB/GPIO78

N4

PIRQC/GPIO79

N2

PIRQD/GPIO80

AD4

PME

U7

GPIO55

L1

GPIO52

L3

GPIO54

R5

GPIO51

L4

GPIO53

HASWELL_MCP_E

SYSTEM POWER MANAGEMENT

HASWELL_MCP_E

eDP SIDEBAND

GPIO

8 OF 19

DISPLAY

EC_SWI#

CLKRUN/GPIO32

SUS_STAT/GPIO61

SUSCLK/GPIO62

SLP_S5/GPIO63

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPB_AUXN DDPC_AUXN DDPB_AUXP DDPC_AUXP

DDPB_HPD DDPC_HPD

RH171

DSWVRMEN

DPWROK

WAKE

SLP_S4 SLP_S3

SLP_A

SLP_SUS

SLP_LAN

Rev1p2

EDP_HPD

2

12

1K_0402_5%

AW7

DSWODVREN

AV5

PCH_RSMRST#_R

AJ5

EC_SWI#

V5

CLKRUN#

AG4 AE6 AP5

PM_SLP_S5#

AJ6

PM_SLP_S4#

AT4

PM_SLP_S3#

AL5 AP4 AJ7

PM_SLP_LAN#

B9 C9 D9 D11

C5 B6 B5 A6

C8 A8 D6

1 2

R271 2.2K_0402_5%

H_EDP_HPD

+3VALW _PCH

DSWODVREN - On Die DSW VR Enable

H：Enable(DEFAULT)

*

L：Disable

1 2

R124 330K_0402_5%

EC_SWI# <32,36>

1 2

R157 8.2K_0402_5%

T104@

T27@ T28@

T30@ T96@

1 2

R118

@

10K_0402_5%

not support Deep S4,S5 can NC

DDPB_CTRLDATA: Port B Detected DDPC_CTRLDATA: Port C Detected

1: Port B or C is detected

*

0: Port B or C is not detected

(Have internal PD)

+3VS

UMA_HDMI_CLK <29>

UMA_HDMI_DATA <29>

HDMI_HPD <10,29> H_EDP_HPD <27,28>

+3VS

+RTCVCC

CLK_EC <31> PM_SLP_S5# <36>

T29@

PM_SLP_S4# <36> PM_SLP_S3# <36>

+3VALW _PCH

1

9 OF 19

PCH_PW ROK

10K_0402_5%

A A

R65 0_0402_5%

12

R208

5

12

SYS_PWROK

+3VS

5

PLT_RST# DGPU_HOLD_RST#

4

1

IN1

VCC

IN2

GND

U37 MC74VHC1G08DFT2G_SC70-5

OPT@

3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

R391 100K_0402_5%

OPT@

3

4

OUT

2

PLTRST_VGA# <18>

Compal Secret Data

2012/07/10 2013/07/10

Compal Secret Data

Deciphered Date

Rev1p2

PLT_RST#

2

R403

0_0402_5%

@

+3VS

5

1

IN1

VCC

OUT

2

IN2

GND

U30 MC74VHC1G08DFT2G_SC70-5

3

12

4

Title

Size Document Number Rev

Custom

Date: Sheet of

H_EDP_HPD

12

R417 100K_0402_5%

12

ZRMAA/ZEMAA

PLT_RST_BUF# <31,32>

R416

100K_0402_5%

Compal Electronics, Inc.

HSW MCP(5/11) PM,GPIO,DDI

1

0.1

9 49Sunday, April 07, 2013

5

+3VS

D D

+3VALW _PCH

C C

+3VS

Note: need check all GPIO PU need or not after BIOS post

1 8

RP34

RP23

RP27

RP35

RP28

2 7 3 6 4 5

1 8 2 7 3 6 4 5

SERIRQ ODD_EN#

10K_0804_8P4R_5%

DEVSLP1

ODD_DA#

10K_0804_8P4R_5%

18 27

SLP_CHG_CB1

36 45

10K_0804_8P4R_5%

PCH_GPIO27 PASSWORD_CLEAR#

10K_0804_8P4R_5%

TP_INTR# <33,9>

DGPU_HOLD_RST# <9> CLKREQ_WLAN# <31,8>

LAN_EN <32,8> USB_OC#0 <11,34,36> SMB_ALERT# <8> SML0CLK <8>

SML0DATA <8> PCH_SMBDATA <8>

USB_OC#2 <11,33,36>

ODD_DETECT# <7> DGPU_PW R_EN <22,9>

4

T162 @ T167 @

EC_LID_OUT#<36>

PASSWORD_CLEAR#

12

JPW

@

SLP_CHG_CB1<34>

EC_SCI#<36>

DEVSLP1<33>

PCH_SPKR<35>

T166 @

T163 @ T139 @

T168 @ T169 @

T136 @

EC_LID_OUT# ODD_EN# ODD_DA# PCH_GPIO24 PCH_GPIO27 PCH_GPIO28 PCH_GPIO26

PCH_GPIO58 PCH_GPIO59 SLP_CHG_CB1 PCH_GPIO47

PCH_GPIO71 PCH_GPIO14 PCH_GPIO45

PCH_GPIO46 PCH_GPIO9

EC_SCI#

DEVSLP1 PCH_SPKR

3

U1J

P1

BMBUSY/GPIO76

AU2

GPIO8

AM7

LAN_PHY_PWR_CTRL/GPIO12

AD6

GPIO15

Y1

GPIO16

T3

GPIO17

AD5

GPIO24

AN5

GPIO27

AD7

GPIO28

AN3

GPIO26

AG6

GPIO56

AP1

GPIO57

AL4

GPIO58

AT5

GPIO59

AK4

GPIO44

AB6

GPIO47

U4

GPIO48

Y3

GPIO49

P3

GPIO50

Y2

HSIOPC/GPIO71

AT3

GPIO13

AH4

GPIO14

AM4

GPIO25

AG5

GPIO45

AG3

GPIO46

AM3

GPIO9

AM2

GPIO10

P2

DEVSLP0/GPIO33

C4

SDIO_POWER_EN/GPIO70

L2

DEVSLP1/GPIO38

N5

DEVSLP2/GPIO39

V2

SPKR/GPIO81

HASWELL_MCP_E

GPIO

10 OF 19

CPU/ MISC

LPIO

2

THERMTRIP

RCIN/GPIO82

SERIRQ

PCH_OPI_RCOMP

RSVD RSVD

GSPI0_CS/GPIO83

GSPI0_CLK/GPIO84 GSPI0_MISO/GPIO85 GSPI0_MOSI/GPIO86

GSPI1_CS/GPIO87

GSPI1_CLK/GPIO88 GSPI1_MISO/GPIO89

GSPI_MOSI/GPIO90

UART0_RXD/GPIO91

UART0_TXD/GPIO92 UART0_RTS/GPIO93 UART0_CTS/GPIO94

UART1_RXD/GPIO0 UART1_TXD/GPIO1 UART1_RST/GPIO2 UART1_CTS/GPIO3

I2C0_SDA/GPIO4

I2C0_SCL/GPIO5

I2C1_SDA/GPIO6

I2C1_SCL/GPIO7

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

SDIO_D0/GPIO66 SDIO_D1/GPIO67 SDIO_D2/GPIO68 SDIO_D3/GPIO69

Rev1p2

D60 V4 T4 AW15 AF20 AB21

R6

PCH_GPIO83

L6

PCH_GPIO84

N6

PCH_GPIO85

L8

PCH_GPIO86

R7

DGPU_PRSNT#

L5

PCH_GPIO88

N7

PCH_GPIO89

K2 J1 K3

PCH_GPIO92

J2

PCH_GPIO93

G1 K4 G2 J3 J4

PCH_GPIO3

F2 F3

PCH_GPIO5

G4

PM_I2CSDA1

F1

PM_I2CSCL1

E3

PCH_GPIO64

F4

PCH_GPIO65

D3

PCH_GPIO66

E4

PCH_GPIO67

C3

PCH_GPIO68

E2

SSD_Detect

H_THERMTRIP# KB_RST# SERIRQ PCH_OPIRCOMP

T106@ T32@

T135@ T134@

T114@ T111@

T133@ T132@

1 2

HDMI_HPD <29,9>

PM_I2CSDA1 PM_I2CSCL1

R145

49.9_0402_1%

PM_I2CSDA1 <33> PM_I2CSCL1 <33>

R274 1K_0402_5%@ R272 1K_0603_5%@

1

H_THERMTRIP#

ODD_DA#

CH6 180P_0402_50V8J

1 2 1 2

KB_RST# <36>

SERIRQ <36>

+1.05VS_VTT

ESD@

1 2

12

2

1

+3VS

R144 1K_0402_5%

ESD@

CH12

0.1U_0402_10V7K

+3VS

B B

10K_0402_5%

DGPU_PRSNT#

10K_0402_5%

R306

UMA@

R219

OPT@

12

GPIO87

DGPU_PRSNT#

DIS,Optimus

1 2

UMA

0 1

+3VALW _PCH

1 2

R247 10K_0402_5%

10K_0402_5%

GPIO15 : TLS Confidentiality

1: Intel ME TLS with confidentiality

A A

5

4

0: Intel ME TLS with no confidentiality

*

(Have internal PD)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

R215

SSD_Detect

R30 0_0402_5%

@

1 2

EC_LID_OUT#

SSD_Detect <33>

PCH_GPIO86

U

ltra

Non-Ultra

1 2

R273 1K_0402_5%@

GSPI0_MOSI / GPIO86 : Boot BIOS Strap

1: ENABLED 0: SPI ROM

*

Compal Secret Data

2012/07/10 2013/07/10

3

Compal Secret Data

Deciphered Date

(Have internal PD)

GPIO69

PROJECT_ID

0 1

2

Need to check the resistors value

+3VS

1 2

R269 1K_0402_1%@

PCH_SPKR

SPKR / GPIO81 : NO REBOOT

1: ENABLED 0: DISABLED

*

(Have internal PD)

PCH_GPIO66

R270 1K_0402_1%@

1 2

SDIO_D0 / GPIO66 : Top-Block Swap Override

1: ENABLED

*

0

: DISABLED

Title

Size Document Number Rev

Custom

Date: Sheet of

HSW MCP(6/11) GPIO,LPIO

ZRMAA/ZEMAA

(Have internal PU)

Compal Electronics, Inc.

1

10 49Sunday, April 07, 2013

0.1

5

PCIE_CTX_C_GRX_N0 PEG_HTX_GRX_N0

PCIE_GTX_C_CRX_N[0..3] <18>

PCIE_GTX_C_CRX_P[0..3] <18>

D D

PCIE_CTX_C_GRX_N[0..3] <18> PCIE_CTX_C_GRX_P[0..3] <18>

PCIE LAN

WLAN

C C

PCIE_CTX_C_GRX_N1 PEG_HTX_GRX_N1

PCIE_CTX_C_GRX_P2 PEG_HTX_GRX_P2

PCIE_CTX_C_GRX_N3 PEG_HTX_GRX_N3

PCIE_PRX_C_LANTX_N3<32> PCIE_PRX_C_LANTX_P3<32>

PCIE_PTX_C_LANRX_N3<32> PCIE_PTX_C_LANRX_P3<32>

PCIE_PRX_WLANTX_N4<31> PCIE_PRX_WLANTX_P4<31>

PCIE_PTX_C_WLANRX_N4<31> PCIE_PTX_C_WLANRX_P4<31>

+1.05VS_AUSB3PLL

C78 0.22U_0402_16V7KOPT@ C79 0.22U_0402_16V7KOPT@

C82 0.22U_0402_16V7KOPT@ C83 0.22U_0402_16V7KOPT@

C86 0.22U_0402_16V7KOPT@ C87 0.22U_0402_16V7KOPT@

C90 0.22U_0402_16V7KOPT@ C91 0.22U_0402_16V7KOPT@

R232 3.01K_0402_1%

4

1 2 1 2

1 2

C155 0.1U_0402_16V7K

1 2

C160 0.1U_0402_16V7K

1 2

C156 0.1U_0402_16V7K

1 2

C157 0.1U_0402_16V7K

1 2

PCIE_GTX_C_CRX_N0 PCIE_GTX_C_CRX_P0

PEG_HTX_GRX_P0PCIE_CTX_C_GRX_P0

PCIE_GTX_C_CRX_N1 PCIE_GTX_C_CRX_P1

PEG_HTX_GRX_P1PCIE_CTX_C_GRX_P1

PCIE_GTX_C_CRX_N2 PCIE_GTX_C_CRX_P2

PEG_HTX_GRX_N2PCIE_CTX_C_GRX_N2

PCIE_GTX_C_CRX_N3 PCIE_GTX_C_CRX_P3

PEG_HTX_GRX_P3PCIE_CTX_C_GRX_P3

PCIE_PTX_LANRX_N3 PCIE_PTX_LANRX_P3

PCIE_PTX_WLANRX_N4 PCIE_PTX_WLANRX_P4

T33 @

T34 @

PCIE_RCOMP PCIE_IREF

F10

PERN5_L0

E10

PERP5_L0

C23

PETN5_L0

C22

PETP5_L0

F8

PERN5_L1

E8

PERP5_L1

B23

PETN5_L1

A23

PETP5_L1

H10

PERN5_L2

G10

PERP5_L2

B21

PETN5_L2

C21

PETP5_L2

E6

PERN5_L3

F6

PERP5_L3

B22

PETN5_L3

A21

PETP5_L3

G11

PERN3

F11

PERP3

C29

PETN3

B30

PETP3

F13

PERN4

G13

PERP4

B29

PETN4

A29

PETP4

G17

PERN1/USB3RN3

F17

PERP1/USB3RP3

C30

PETN1/USB3TN3

C31

PETP1/USB3TP3

F15

PERN2/USB3RN4

G15

PERP2/USB3RP4

B31

PETN2/USB3TN4

A31

PETP2/USB3TP4

E15

RSVD

E13

RSVD

A27

PCIE_RCOMP

B27

PCIE_IREF

U1K

3

HASWELL_MCP_E

PCIe

USB3.0 P3 / PCIE P1

USB3.0 P4 / PCIE P2

11 OF 19

USB

USB3.0 P1

USB3.0 P2

USB2N0 USB2P0

USB2N1 USB2P1

USB2N2 USB2P2

USB2N3 USB2P3

USB2N4 USB2P4

USB2N5 USB2P5

USB2N6 USB2P6

USB2N7 USB2P7

USB3RN1 USB3RP1

USB3TN1 USB3TP1

USB3RN2 USB3RP2

USB3TN2 USB3TP2

USBRBIAS USBRBIAS

RSVD RSVD

OC0/GPIO40 OC1/GPIO41 OC2/GPIO42 OC3/GPIO43

Rev1p2

AN8 AM8

AR7 AT7

AR8 AP8

AR10 AT10

AM15 AL15

AM13 AN13

AP11 AN11

AR13 AP13

G20 H20

C33 B34

E18 F18

B33 A33

AJ10 AJ11 AN10 AM10

AL3 AT1 AH2 AV3

2

USBRBIAS

R154 22.6_0402_1%

T35@ T36@

1 2

USB20_N0 <34> USB20_P0 <34>

USB20_N1 <34> USB20_P1 <34>

USB20_N2 <33> USB20_P2 <33>

USB20_N3 <33> USB20_P3 <33>

USB20_N4 <31> USB20_P4 <31>

USB20_N5 <28> USB20_P5 <28>

USB20_N7 <28> USB20_P7 <28>

U3RXDN1 <34> U3RXDP1 <34>

U3TXDN1 <34> U3TXDP1 <34>

U3RXDN2 <34> U3RXDP2 <34>

U3TXDN2 <34> U3TXDP2 <34>

CAD note: Route single-end 50-ohms and max 450-mils length. Avoid routing next to clock pins or under stitching capacitors. Recommended minimum spacing to other signal traces is 15 mils

USB_OC#0 <10,34,36> USB_CHG_OC# <34,36,8> USB_OC#2 <10,33,36>

SLP_CHG_CB0 <34,8>

USB-Right1 USB-Right2 USB-Left1 CardReader WiMAX / BT Touch Screen

Camera

USB-Right Rear USB-Right Front USB-Left

1

B B

A A

Security Classification

2012/07/10 2013/07/10

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/07/10 2013/07/10

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HSW MCP(7/11) PCIE,USB

ZRMAA/ZEMAA

1

0.1

11 49Sunday, April 07, 2013

5

D D

+3VS

12

R422

100K_0402_5%

C C

VCCST_PG_EC<36,9>

VID ALERT

S

VR_SVID_ALRT#<46>

@

U16

NC1VCC

2

A

3

GND

74AUP1G07GW_TSSOP5

+1.05VS_VTT

Place the PU

12

resistors close to CPU

R171 75_0402_1%

R172 43_0402_1%

+3VALW _PCH

5

4

Y

12

H_CPU_SVIDALRT#

R309

10K_0402_5%

VCCST_PG_EC_R

+1.05VS_VTT

12

R166 0_0402_5%

1 2

4

@

VCCST_PWRGD <36,44>

VR_SVID_CLK<46>

3

+VCCIOA_OUT

VR_ON<46>

VGATE<46>

Reserved Only

C167

1 2

0.1U_0402_16V7K

@

T131 @

+CPU_CORE

T107 @

+1.05VS_VTT

+1.35V

R1670_0402_5% @

CPU_PW R_DEBUG

T37 @ T38 @

T39 @ T40 @

VCC_SENSE_R

T41 @

+VCCIO_OUT

T42 @ T43 @

T44 @

H_CPU_SVIDALRT# VIDSOUT

VCCST_PG_EC_R PCH_VR_EN

T45 @ T46 @ T47 @ T48 @ T98 @ T142 @ T143 @ T144 @ T141 @ T140 @ T147 @ T145 @ T146 @

2

AH26

AJ31 AJ33

AJ37 AN33 AP43 AR48 AY35 AY40 AY44 AY50

N58

AC58

E63

AB23

A59

E20 AD23 AA23 AE59

N63

B59

C59

D63

H59

P62

P60

P61

N59

N61 AD60

AD59 AA59 AE60 AC59

AG58

U59

V59 AC22

AE22 AE23

AB57 AD57

AG57

C24

C28

C32

L59 J58

F59

L62 L63 F60

T59

U1L

RSVD RSVD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VCC RSVD RSVD

VCC_SENSE RSVD VCCIO_OUT VCCIOA_OUT RSVD RSVD RSVD

VIDALERT VIDSCLK VIDSOUT VCCST_PWRGD VR_EN VR_READY

VSS PWR_DEBUG VSS RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

VCCST VCCST VCCST

VCC VCC VCC VCC VCC VCC

HASWELL_MCP_E

HSW ULT POWER

12 OF 19

1

+CPU_CORE

C36

VCC

C40

VCC

C44

VCC

C48

VCC

C52

VCC

C56

VCC

E23

VCC

E25

VCC

E27

VCC

E29

VCC

E31

VCC

E33

VCC

E35

VCC

E37

VCC

E39

VCC

E41

VCC

E43

VCC

E45

VCC

E47

VCC

E49

VCC

E51

VCC

E53

VCC

E55

VCC

E57

VCC

F24

VCC

F28

VCC

F32

VCC

F36

VCC

F40

VCC

F44

VCC

F48

VCC

F52

VCC

F56

VCC

G23

VCC

G25

VCC

G27

VCC

G29

VCC

G31

VCC

G33

VCC

G35

VCC

G37

VCC

G39

VCC

G41

VCC

G43

VCC

G45

VCC

G47

VCC

G49

VCC

G51

VCC

G53

VCC

G55

VCC

G57

VCC

H23

VCC

J23

VCC

K23

VCC

K57

VCC

L22

VCC

M23

VCC

M57

VCC

P57

VCC

U57

VCC

W57

VCC

Rev1p2

B B

A A

SVID DATA

VR_SVID_DAT<46>

100_0402_1%

VCC_SENSE_R

VSS_SENSE_R<14>

100_0402_1%

R177

R233

+1.05VS_VTT

R174 0_0402_5%

12

@

+CPU_CORE

12

Note: 0 ohm PLACED CLOSE TO CPU

12

R178

@

0_0402_5%

12

R235

12

5

0_0402_5%@

Place the PU resistors close to CPU

12

R173 130_0402_1%

VIDSOUT

VCC_SENSE <46>

VSS_SENSE <46>

4

+1.35V

12

CC53

47U_0805_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/07/10 2013/07/10

3

+1.35V

VDDQ DECOUPLING

2.2U_0402_6.3V6M

C8

1

@

2

Compal Secret Data

Deciphered Date

2.2U_0402_6.3V6M

C9

C10

1

2

10U_0603_6.3V6M

C11

1

2

1

@

C12

2

10U_0603_6.3V6M

1

@

C13

2

10U_0603_6.3V6M

1

C14

C15

2

+1.35V : 470UF/2V/7343 *2

Title

Size Document Number Rev

Custom

ZRMAA/ZEMAA

Date: Sheet of

10U_0603_6.3V6M

1

C17

C16

2

10UF/6.3V/0603 * 6

2.2UF/6.3V/0402 * 4

Compal Electronics, Inc.

HSW MCP(8/11) Power

1

0.1

12 49Sunday, April 07, 2013

5

+1.05VS_VTT

1

C21

2

D D

+1.05VS_VTT +1.05VS_AUSB3PLL

1 2

L1

2.2UH_LQM2MPN2R2NG0L_30%

Idc 1.2A Rdc 0.11ohm +/-30%

L2

2.2UH_LQM2MPN2R2NG0L_30%

Idc 1.2A Rdc 0.11ohm +/-30%

L3

2.2UH_LQM2MPN2R2NG0L_30%

Idc 1.2A Rdc 0.11ohm +/-30%

C C

+1.05VS_VTT +1.05VS_AXCK_DCB

L4

2.2UH_LQM2MPN2R2NG0L_30%

Idc 1.2A Rdc 0.11ohm +/-30%

L5

2.2UH_LQM2MPN2R2NG0L_30%

Idc 1.2A Rdc 0.11ohm +/-30%

1 2

R210 0_0805_5%

1 2

@

1 2

+1.05VS_ASATA3PLL

+1.05VS_APLLOPI

+1.05VS_AXCK_LCPLL

1U_0402_6.3V6K

Near K9 Near L10 Near M9

Near B18

1 2

C42 1U_0402_6.3V6K

1 2

C64 22U_0805_6.3V6M

Near B11

1 2

C46 1U_0402_6.3V6K

1 2

C65 22U_0805_6.3V6M

Near AA21

1 2

C47 1U_0402_6.3V6K

1 2

C66 22U_0805_6.3V6M@

Near J18

1 2

C48 1U_0402_6.3V6K

1 2

C67 22U_0805_6.3V6M

Near A20

1 2

C49 1U_0402_6.3V6K

1 2

C68 22U_0805_6.3V6M

@

1

C20

C31

2

1U_0402_6.3V6K

ESD@

C35

1U_0402_6.3V6K

100P_0402_50V8J

Close to CPU

+1.05VS_VTT

Near J17 Near R21

4

ESD@

C39

C60

100P_0402_50V8J

HDA --> 3.3V or 1.5V I2C --> 1.8V

12

Near AC9 Near AH10 Near V8

C57

12

1U_0402_6.3V6K C56

12

1U_0402_6.3V6K

+1.05VS_AUSB3PLL

+1.05VS_ASATA3PLL

+1.05VS_APLLOPI

+3VALW _PCH

C38 1U_0402_6.3V6K

C28

12

22U_0805_6.3V6M C59

@

12

0.1U_0402_16V7K C29

12

22U_0805_6.3V6M

+3VS

+1.05VS_AXCK_DCB

+1.05VS_AXCK_LCPLL

+3VALW _PCH

T99 @

T105 @

T116 @

+3VALW _PCH

T100 @ T101 @ T102 @

B18 B11

Y20

AA21

W21

AH14

AH13

AC9 AA9

AH10

K19 A20

R21 T21 K18

M20

V21 AE20 AE21

K9

L10

M9 N8 P9

J13

V8

W9

J18

J17

U1M

VCCHSIO VCCHSIO VCCHSIO VCC1_05 VCC1_05 VCCUSB3PLL VCCSATA3PLL

RSVD VCCAPLL VCCAPLL

DCPSUS3

VCCHDA

DCPSUS2

VCCSUS3_3 VCCSUS3_3 VCCDSW3_3 VCC3_3 VCC3_3

VCCCLK VCCCLK VCCACLKPLL VCCCLK VCCCLK VCCCLK RSVD RSVD RSVD VCCSUS3_3 VCCSUS3_3

3

mPHY

OPI

USB3

AXALIA/HDA

VRM/USB2/AZALIA

GPIO/LCC

LPT LP POWER

HASWELL_MCP_E

13 OF 19

RTC

SPI

CORE

THERMAL SENSOR

SDIO/PLSS

SUS OSCILLATOR

USB2

VCCSUS3_3

VCCRTC DCPRTC

VCCSPI

VCCASW VCCASW

VCC1_05 VCC1_05 VCC1_05 VCC1_05

VCC1_05 DCPSUSBYP DCPSUSBYP

VCCASW VCCASW

VCCASW DCPSUS1 DCPSUS1

VCCTS1_5

VCC3_3 VCC3_3

VCCSDIO

DCPSUS4

RSVD VCC1_05 VCC1_05

Rev1p2

+3VALW _PCH

AH11 AG10 AE7

Y8

AG14 AG13

J11 H11 H15 AE8 AF22 AG19 AG20 AE9 AF9 AG8 AD10 AD8

J15 K14 K16

U8 T9

AB8

AC20 AG16 AG17

C30 1U_0402_6.3V6K

+VCCRTCEXT

C54 0.1U_0402_16V7K

+3VALW _PCH

C58 0.1U_0402_16V7K

C27 10U_0603_6.3V6M C33 1U_0402_6.3V6K C40 1U_0402_6.3V6K

+PCH_VCCDSW

C36 22U_0805_6.3V6M C37 1U_0402_6.3V6K

1 2

C55 0.1U_0402_16V7K

1 2

C44 1U_0402_6.3V6K

T137@

T103@

+1.05VS_VTT

1 2

C45 1U_0402_6.3V6K

2

1 2

@

1 2 1 2 1 2

1 2 1 2

T108@

12

+RTCVCC

+1.05VS_VTT +1.05VS_VTT

+1.05VS_VTT

+1.5VS +3VS

+3VS

C41 1U_0402_6.3V6K

1 2

+RTCVCC

C52

1U_0402_6.3V6K

1

@

C51

2

0.1U_0402_16V7K

1

@

C50

2

0.1U_0402_16V7K

+3VALW to +3VALW_PCH

B B

PCH_PW R_EN#<38>

A A

5

PCH_PW R_EN#

+3VALW

12

RH3 47K_0402_5%

4

Q10 AO3413_SOT23

S

G

1

CH1110.1U_0402_25V6

2

+3VALW _PCH

D

13

2

1

CH1130.1U_0402_10V7K

CH1120.01U_0402_25V7K

2

Security Classification

2012/07/10 2013/07/10

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/07/10 2013/07/10

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

HSW MCP(9/11) Power

ZRMAA/ZEMAA

13 49Sunday, April 07, 2013

1

0.1

5

4

3

2

1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

U1O

HASWELL_MCP_E

15 OF 19

Rev1p2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AV59 AV8 AW16 AW24 AW33 AW35 AW37 AW4 AW40 AW42 AW44 AW47 AW50 AW51 AW59 AW60 AY11 AY16 AY18 AY22 AY24 AY26 AY30 AY33 AY4 AY51 AY53 AY57 AY59 AY6 B20 B24 B26 B28 B32 B36 B4 B40 B44 B48 B52 B56 B60 C11 C14 C18 C20 C25 C27 C38 C39 C57 D12 D14 D18 D2 D21 D23 D25 D26 D27 D29 D30 D31

G18 G22

D33 D34 D35 D37 D38 D39 D41 D42 D43 D45 D46 D47 D49

D50 D51 D53 D54 D55 D57 D59 D62

E11 E17 F20 F26 F30 F34 F38 F42 F46 F50 F54 F58 F61

H13

U1P

HASWELL_MCP_E

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

D5

VSS VSS VSS VSS VSS VSS VSS VSS VSS

D8

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

G3

VSS

G5

VSS

G6

VSS

G8

VSS VSS

16 OF 19

VSS_SENSE

Rev1p2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS

VSS

H17 H57 J10 J22 J59 J63 K1 K12 L13 L15 L17 L18 L20 L58 L61 L7 M22 N10 N3 P59 P63 R10 R22 R8 T1 T58 U20 U22 U61 U9 V10 V3 V7 W20 W22 Y10 Y59 Y63

V58 AH46 V23 E62 AH16

VSS_SENSE_R <12>

HASWELL_MCP_E

D D

C C

B B

A11 A14 A18 A24 A28 A32 A36 A40 A44 A48 A52 A56

AA1 AA58 AB10 AB20 AB22

AB7 AC61 AD21

AD3 AD63 AE10

AE5 AE58

AF11 AF12 AF14 AF15 AF17 AF18

AG1 AG11 AG21 AG23 AG60 AG61 AG62 AG63 AH17 AH19 AH20 AH22 AH24 AH28 AH30 AH32 AH34 AH36 AH38 AH40 AH42 AH44 AH49 AH51 AH53 AH55 AH57

AJ13 AJ14 AJ23 AJ25 AJ27 AJ29

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

U1N

14 OF 19

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

Rev1p2

AJ35 AJ39 AJ41 AJ43 AJ45 AJ47 AJ50 AJ52 AJ54 AJ56 AJ58 AJ60 AJ63 AK23 AK3 AK52 AL10 AL13 AL17 AL20 AL22 AL23 AL26 AL29 AL31 AL33 AL36 AL39 AL40 AL45 AL46 AL51 AL52 AL54 AL57 AL60 AL61 AM1 AM17 AM23 AM31 AM52 AN17 AN23 AN31 AN32 AN35 AN36 AN39 AN40 AN42 AN43 AN45 AN46 AN48 AN49 AN51 AN52 AN60 AN63 AN7 AP10 AP17 AP20

AP22 AP23 AP26 AP29

AP3 AP31 AP38 AP39 AP48 AP52 AP54 AP57 AR11 AR15 AR17 AR23 AR31 AR33 AR39 AR43 AR49

AR5 AR52

AT13 AT35 AT37 AT40 AT42 AT43 AT46 AT49 AT61 AT62 AT63

AU1 AU16 AU18 AU20 AU22 AU24 AU26 AU28 AU30 AU33 AU51 AU53 AU55 AU57 AU59 AV14 AV16 AV20 AV24 AV28 AV33 AV34 AV36 AV39 AV41 AV43 AV46 AV49 AV51 AV55

A A

Security Classification

2012/07/10 2013/07/10

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/07/10 2013/07/10

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HSW MCP(10/11) GND

ZRMAA/ZEMAA

0.1

14 49Sunday, April 07, 2013

1

5

4

3

2

1

U1Q

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG18 CFG17 CFG19

AY2

DAISY_CHAIN_NCTF_AY2

AY3

DAISY_CHAIN_NCTF_AY3

AY60

DAISY_CHAIN_NCTF_AY60

AY61

DAISY_CHAIN_NCTF_AY61

AY62

DAISY_CHAIN_NCTF_AY62

B2

DAISY_CHAIN_NCTF_B2

B3

DAISY_CHAIN_NCTF_B3

B61

DAISY_CHAIN_NCTF_B61

B62

DAISY_CHAIN_NCTF_B62

B63

DAISY_CHAIN_NCTF_B63

C1

DAISY_CHAIN_NCTF_C1

C2

DAISY_CHAIN_NCTF_C2

U1S

AC60

CFG0

AC62

CFG1

AC63

CFG2

AA63

CFG3

AA60

CFG4

Y62

CFG5

Y61

CFG6

Y60

CFG7

V62

CFG8

V61

CFG9

V60

CFG10

U60

CFG11

T63

CFG12

T62

CFG13

T61

CFG14

T60

CFG15

AA62

CFG16

U63

CFG18

AA61

CFG17

U62

CFG19

V63

CFG_RCOMP

A5

RSVD

E1

RSVD

D1

RSVD

J20

RSVD

H18

RSVD

B12

TD_IREF

DC_TEST_AY2_AW2 DC_TEST_AY3_AW3

T49 @

DC_TEST_AY61_AW 61 DC_TEST_AY62_AW 62

D D

C C

B B

T50 @

T110 @ T109 @ T112 @

T113 @ T117 @ T115 @ T119 @ T118 @ T121 @ T120 @ T124 @ T122 @ T125 @ T123 @

T128 @ T127 @ T129 @ T126 @

DC_TEST_A3_B3 DC_TEST_A61_B61 DC_TEST_B62_B63

DC_TEST_C1_C2

CFG_RCOMP

T90 @ T91 @

T92 @ T93 @ T94 @

TD_IREF

HASWELL_MCP_E

17 OF 19

HASWELL_MCP_E

RESERVED

19 OF 19

DAISY_CHAIN_NCTF_A3 DAISY_CHAIN_NCTF_A4

DAISY_CHAIN_NCTF_A60 DAISY_CHAIN_NCTF_A61 DAISY_CHAIN_NCTF_A62

DAISY_CHAIN_NCTF_AV1 DAISY_CHAIN_NCTF_AW1 DAISY_CHAIN_NCTF_AW2 DAISY_CHAIN_NCTF_AW3

DAISY_CHAIN_NCTF_AW61 DAISY_CHAIN_NCTF_AW62 DAISY_CHAIN_NCTF_AW63

Rev1p2

PROC_OPI_RCOMP

RSVD_TP RSVD_TP

RSVD

RSVD_TP RSVD_TP

RSVD_TP

RSVD RSVD

RSVD

RSVD RSVD

VSS VSS

RSVD RSVD

Rev1p2

A3 A4

A60 A61 A62 AV1 AW1 AW2

DC_TEST_AY2_AW2

AW3

DC_TEST_AY3_AW3

AW61

DC_TEST_AY61_AW 61

AW62

DC_TEST_AY62_AW 62

AW63

AV63 AU63

C63 C62 B43

A51 B51

L60 N60 W23

Y22 AY15

AV62 D58

P22 N21

P20 R20

DC_TEST_A3_B3

DC_TEST_A61_B61

T75@ T76@

T77@ T78@ T79@

T80@ T81@

T82@ T83@ T84@

T85@

OPI_COMP

T86@ T87@

T88@ T89@

T58@ T59@ T60@

T61@ T62@

T63@

T51 @ T52 @ T53 @ T54 @

T55 @ T56 @ T57 @

U1R

AT2

RSVD

AU44

RSVD

AV44

RSVD

D15

RSVD

F22

RSVD

H22

RSVD

J21

RSVD

CFG Straps for Processor

Physical Debug Enable (DFX Privacy)

CFG3

HASWELL_MCP_E

18 OF 19

CFG3

12

R224 1K_0402_1%

@

1: DISABLED 0: ENABLED; SET DFX ENABLED BIT

I

N DEBUG INTERFACE MSR

CFG4

12

R225 1K_0402_5%

RSVD RSVD RSVD RSVD

RSVD RSVD RSVD RSVD RSVD RSVD RSVD

Rev1p2

N23 R23 T23 U10

AL1 AM11 AP7 AU10 AU15 AW14 AY14

T64@ T65@ T66@ T67@

T68@ T69@ T70@ T71@ T72@ T73@ T74@

12

R222 49.9_0402_1% R223 49.9_0402_1% R226 8.2K_0402_5%

A A

5

CFG_RCOMP

12 12

OPI_COMP

TD_IREF

Display Port Presence Strap

1 : Disabled; No Physical Display Port

CFG4

attached to Embedded Display Port

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

Security Classification

2012/07/10 2013/07/10

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/07/10 2013/07/10

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HSW MCP(11/11) RSVD

ZRMAA/ZEMAA

0.1

15 49Sunday, April 07, 2013

1