A
1 1
B
C
D
E
Compal Confidential
ZRMAA/ZEMAA Schematics Document
2 2
Haswell ULT with DDR3L
nVIDIA N14P-GV2 (Dual Rank)
nVIDIA N14M-GL
LA-A481P REV 1.0 Schematic
3 3
Intel Processor (Haswell)
2013-06-21 Rev 1.0
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2012/04/19 2015/04/19
2012/04/19 2015/04/19
2012/04/19 2015/04/19
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
D
Date: Sheet
Compal Electronics, Inc.
Cover Page
Cover Page
Cover Page
ZRMAA/ZEMAA
ZRMAA/ZEMAA
ZRMAA/ZEMAA
1 55Friday, June 21, 2013
1 55Friday, June 21, 2013
1 55Friday, June 21, 2013
E
0.4
0.4
0.4
of
of
A
GA (DDR3)
V
n
VIDIA N14P-GV2
1 1
p
age 18~26
B
CI-Express 4X Gen3 8GT/s
P
eDP 1X 5.4GT/s
C
Intel Haswell ULT
D
M
emory BUS(DDR3L)
D
ual Channel
1
.35V DDR3L 1333/1600 MT/s
E
04pin DDR3-SO-DIMM X2
2
B
ANK 0, 1, 2
p
age 16,17
LVDS Conn.
Colay eDP
page 28
LVDS Translator
RTD2132R-CG
page 27
Haswell ULT
Processor
USB30 2x
5V 5GT/s
USB20 2x
5V 480MHz
USB3.0 x2 Right
USB20 port 0,1
USB30 port 1,2
page 34
OPI
HDMI Conn.
page 29
2 2
RJ45
page 32
RTL8106E-CG 10/100M
RTL8111G-CG 1G
PCIe port 3
page 32
PCIeMini Card
WLAN
PCIe port 4
USB20 port 4
page 31
PCIe Gen1 1x
1.5V 5GT/s
PCIe Gen1 1x
1.5V 5GT/s
USB20 1x
5V 480MHz
Lynx Point - LP
PCH
USB20 1x
5V 480MHz
USB20 1x
5V 480MHz
SATA Gen3 port 0
5V 6GHz(600MB/s)
SATA Gen3 port 1
5V 6GHz(600MB/s)
Touch Screen
USB20 port 5
page 28
Int. Camera
USB20 port 7
page 28
SATA HDD
SATA port 0
page 30
SATA SSD
NGFF B TYPE
SATA port 1
page 33
NGFF E TYPE
WLAN
3 3
PCIe port 4
USB20 port 4
page 31
LPC BUS
3.3V 33 MHz
1168pin BGA
page 05~15
HD Audio
3.3V 24MHz
RTC CKT.
page 7
Sub Boards
LS-A481P
CardReader GL834L(Port 3)
+USB (Port 2)+
Audio Combo jack
4 4
page 33
DC/DC Interface CKT.
page 38
Power Circuit DC/DC
page 39~47
SPI ROM
(8MB)
page 8
KB9012QF A4
page 36
Int.KBD
page 37
HDA Codec
ALC282 (w/o S&M)
page 35
SPK Conn
page 33
Power On/Off CKT.
LS-A482P
Touch pad/LED B
page 33
GCLK
SLG3NB282VTR page 31
A
page 37
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2012/04/19 2015/04/19
2012/04/19 2015/04/19
2012/04/19 2015/04/19
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
D
Date: Sheet
Compal Electronics, Inc.
Block Diagram
Block Diagram
Block Diagram
ZRMAA/ZEMAA
ZRMAA/ZEMAA
ZRMAA/ZEMAA
2 55Friday, June 21, 2013
2 55Friday, June 21, 2013
2 55Friday, June 21, 2013
E
0.4
0.4
0.4
of
of
A
B
+
1 1
RT8243AZQW
I
peak=9.8A, Imax=6.8A, Iocp min=11.8A
S
USP#
TPS22966DPUR
SY8208DQNC
Ipeak=10.63A, Imax=7.44A, Iocp min=12.3A
SUSP#
Ipeak=10.63A, Imax=7.44A, Iocp min=12.3A
B
D
ESIGN CURRENT 2 2mA
D
ESIGN CURRENT 9 .8A
SB_EN#0
U
S
Y6288DCAC
SB_CHG_EN#
U
G
547N2P81U
SB_EN#2
U
SY6288DCAC
+5VS
AP2151DWG-7
KB_LED
D
ESIGN CURRENT 2 A
D
ESIGN CURRENT 2 .5A
ESIGN CURRENT 2 A
D
DESIGN CURRENT 4.19A
DESIGN CURRENT 1A
DESIGN CURRENT 150mA
A03413-SOT23
DESIGN CURRENT 10.17A
VGA_PWROK
DESIGN CURRENT 3.2A
2N7002
2 2
Ipeak=9A, Imax=6.3A, Iocp min=10.5A
TPS22966DPUR
SUSP#
LCD_ENVDD
APL3512ABI-TRG
DGPU_PWR_EN
P-CHANNEL
PCH_PWR_EN#
P-CHANNEL
AO-3413
WOWL_EN#
P-CHANNEL
AO-3413
AO-3413
DESIGN CURRENT 9A
DESIGN CURRENT 4.433A
DESIGN CURRENT 1.5A
DESIGN CURRENT 1.02A
DESIGN CURRENT 2.5A
DESIGN CURRENT 451mA
DESIGN CURRENT 370mA
DESIGN CURRENT 1.5A
C
+
3VL
+
5VALW
+
USB_VCCB
+
USB_VCCA
USB_VCCC
+
+5VS
+HDMI_5V_OUT
+5VS_LED
+1.05VS_VTT
+1.05VS_DGPU
+3VALW
+3VS
+LCD_VDD
+3VS_DGPU
+3VS_RT
+3VALW_PCH
+3V_LAN
+3V_WLAN
D
E
3 3
PCH_PWR_EN
TPS51212DSCR
Ipeak=12.8A, Imax=9A, Iocp min=13.5A
1.5V_PWR_EN
FDS6676AS
SUSP
VR_ON
TPS51622RSM
SYSON
Ipeak=10.63A, Imax=7.44A, Iocp min=12.3A
P-CHANNEL
AO-3413
Ipeak=8.9A, Imax=6.3A, Iocp min=11A
RT8207MZQW
4 4
+3VS_DGPU
NCP81172MNTWG
A
Ipeak=55A, Imax=32A, Iocp min=60A
B
DESIGN CURRENT1 2.8A
DESIGN CURRENT 7.8A
DESIGN CURRENT 8mA
DESIGN CURRENT 32A
DESIGN CURRENT 8.9A
DESIGN CURRENT 1.5A
DESIGN CURRENT 55A
DESIGN CURRENT 650mA
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Issued Date
Issued Date
+1.5VALW
+VRAM_1.5VS
+1.5VS
+CPU_CORE
+1.35V
+0.675VS
+VGA_CORE
+LCD_INV
Compal Secret Data
Compal Secret Data
2012/10/25 2013/10/05
2012/10/25 2013/10/05
2012/10/25 2013/10/05
C
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Power Map
Power Map
Power Map
ZRMAA/ZEMAA
ZRMAA/ZEMAA
ZRMAA/ZEMAA
E
of
3 55Friday, June 21, 2013
of
3 55Friday, June 21, 2013
of
3 55Friday, June 21, 2013
0.4
0.4
0.4
A
(
oltage Rails
V
p
ower
1 1
plane
State
O MEANS O N X MEANS O FF )
+RTCVCC
+
B
+5VL
+3VL
B
+5VALW
3VALW
+
+1.5VALW
+
VSB
+1.35V
+5VS
+3VS
+
1.8VS_CRT
+1.5VS
+
CPU_CORE
+VGA_CORE
+
VRAM_1.5VS
+3VS_DGPU
+1.05VS_DG PU
+1.05VS_VT T
P
TO Option Table
B
description
latform
Function
C
D
SKU CPU PCH VGA
SKU
MIC
LAN
n
VIDIA N13P-GL
(N13PGL@)
E
explain
BTO
S0
S1
S3
2 2
S5 S4/AC
S5 S4/ Bat tery only
S5 S4/AC & Battery
don't exis t
O
O
O
O
O
O
O
O
O
O
O
X
O
O
O
O
O
X
O
O
O
O
X
X
O
X X
X
X X
OO
OO
X
Function
description
X
explain
BTO
Function
PCH SM Bus Address
Power
+3VS
+3VS
Device
DDR SO-DIMM 0
DDR SO-DIMM 1
HEX
Address
1010 0000 bA0 H
1010 0100 bA4 H
description
explain
BTO
Function
3 3
description
explain
BTO
EC SM Bus1 Address
Device Address Address
+3VL
4 4
HEX HEX
16 H
0001 0110 bSmart Battery
12 HSmart Charger 0001 0010 b+3VL
PowerPower
+3VS
+3VS
HEXDevice AddressPower
EC SM Bus2 Address
Device
96 H
1001 0110 bPCH
NVIDIA GPU 1001 1010 b
9E H
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
G3 LOW LOWLOW
SIGNAL
SLP_S3# SLP_S4# SLP_S5#
HIGH HIGHHIGH
LOW
LOW LOW
HIGH HIGHHIGH
HIGH
LOW LOWLOW
HIGH
HIGH
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2012/07/10 2013/07/10
2012/07/10 2013/07/10
2012/07/10 2013/07/10
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
D
Date: Sheet
Compal Electronics, Inc.
Notes List
Notes List
Notes List
ZRMAA/ZEMAA
ZRMAA/ZEMAA
ZRMAA/ZEMAA
0.4
0.4
0.4
of
4 55Friday, June 21, 2013
of
4 55Friday, June 21, 2013
4 55Friday, June 21, 2013
E
5
4
3
U1A
U1A
ASWELL_MCP_E
ASWELL_MCP_E
H
H
2
1
C54
DI1_TXN0
D
C55
D
DI1_TXP0
B58
DI1_TXN1
D
C58
D
DI1_TXP1
B55
DI1_TXN2
D
A55
D
DI1_TXP2
A57
DI1_TXN3
D
B57
D D
HDMI
H_PECI<36>
ESD@
ESD@
H_CPUPW RGD
CH11100P_04 02_50V8J
C C
+1.35V
12
R184
R184
470_060 3_5%
470_060 3_5%
CH11100P_04 02_50V8J
+1.05VS_ VTT
H_PROCH OT#<36>
_HDMI_TX2 -<29>
H
H
_HDMI_TX2 +<29>
_HDMI_TX1 -<29>
H
H_HDMI_TX 1+<29>
H_HDMI_TX 0-<29>
H_HDMI_TX 0+<29>
H_HDMI_TX C-<2 9>
H_HDMI_TX C+<29>
12
R68
R68
R8
62_0402 _5%
62_0402 _5%
1 2
R6 10K _0402_5%R6 10K_ 0402_5%
1 2
R11 200_040 2_1%R11 200_040 2_1%
1 2
R13 120_040 2_1%R13 120_040 2_1%
1 2
R41 100_040 2_1%R41 100_040 2_1%
DIMM_DRAM RST#<16,17>
DDR_PG_ CTRL<16>
R8
56_0402 _5%
56_0402 _5%
1 2
T20 @T20 @
T97 @T97 @
H_PROCH OT#_R
H_CPUPW RGD
SM_RCOM P0
SM_RCOM P1
SM_RCOM P2
DIMM_DRAMR ST#
C51
C50
C53
B54
C49
B50
A53
B53
D61
K61
N62
K63
C61
AU60
AV60
AU61
AV15
AV61
DDI1_TXP3
DI2_TXN0
D
D
DI2_TXP0
DI2_TXN1
D
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3
U1B
U1B
PROC_DETECT
CATERR
PECI
PROCHOT
PROCPWRGD
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_DRAMRST
SM_PG_CNTL1
DDR3 Compensation Signals
ESD@
ESD@
DIMM_DRAM RST#
12
DIMM_DRAM RST#
CH70.1U_0402_10V7 K
CH70.1U_0402_10V7 K
DDI EDP
DDI EDP
1 OF 19
1 OF 19
HASWELL_MCP_E
HASWELL_MCP_E
MISC
MISC
JTAG
JTAG
THERMAL
THERMAL
PWR
PWR
DDR3
DDR3
2 OF 19
2 OF 19
E
E
EDP_RCOMP
EDP_DISP_UTIL
DP_TXN0
E
E
DP_TXP0
DP_TXN1
E
E
DP_TXP1
E
DP_TXN2
DP_TXP2
E
EDP_TXN3
E
DP_TXP3
DP_AUXN
DP_AUXP
Rev1p2
Rev1p2
PRDY
PREQ
PROC_TCK
PROC_TMS
PROC_TRST
PROC_TDI
PROC_TDO
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
Rev1p2
Rev1p2
C45
B46
A47
B47
C47
C46
A49
B49
A45
B45
D20
A43
_EDP_TX N0 <27>
H
H
_EDP_TX P0 <27>
_EDP_TX N1 <27>
H
H
_EDP_TX P1 <27>
H
_EDP_AU XN <27 >
_EDP_AU XP <27>
H
1 2
R1 24.9_0402 _1%R1 24.9_0402 _1%
EDP_COM P
dƌĂĐĞǁŝĚƚŚсϮϬŵŝůƐ^ƉĂĐŝŶŐсϮϱŵŝůDĂdžůĞŶŐƚŚсϭϬϬŵŝůƐ
J62
K62
E60
E61
E59
F63
F62
J60
H60
H61
H62
K59
H63
K60
J61
XDP_PRD Y#
XDP_PRE Q#
XDP_TCK
XDP_TMS
XDP_TRS T#
XDP_TDI
XDP_TDO
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
T154@ T154@
T155@ T155@
T156@ T156@
T148@ T148@
T149@ T149@
T150@ T150@
T151@ T151@
T152@ T152@
T153@ T153@
PU/PD for JTAG signals
+VCCIOA_OU T
+1.05VS_ VTT
B B
A A
Security Class ification
Security Class ification
Security Class ification
2012/07/ 10 2013/07/ 10
2012/07/ 10 2013/07/ 10
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2012/07/ 10 2013/07/ 10
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
XDP_TMS
XDP_TDI
XDP_PRE Q#
XDP_TDO
XDP_TCK
XDP_TRS T#
Title
Title
Title
Size Docum ent Number Rev
Size Docum ent Number Rev
Size Docum ent Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
HSW MCP(1/11) DDI,MSIC,XDP
HSW MCP(1/11) DDI,MSIC,XDP
HSW MCP(1/11) DDI,MSIC,XDP
ZRMAA/ZEMAA
ZRMAA/ZEMAA
ZRMAA/ZEMAA
1 2
R86 51_0402 _5%@R86 51_0402 _5%@
1 2
R87 51_0402 _5%XDP@R87 51_0402 _5%XDP@
1 2
R88 51_0402 _5%@R88 51_0402 _5%@
1 2
R89 51_0402 _5%XDP@R89 51_0402 _5%XDP@
1 2
R90 51_0402 _5%XDP@R90 51_0402 _5%XDP@
1 2
R91 51_0402 _5%@R91 51_0402 _5%@
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
1
0.4
0.4
0.4
5 55Friday, June 21, 201 3
5 55Friday, June 21, 201 3
5 55Friday, June 21, 201 3
5
HASWELL_MCP_E
U1C
U1C
AH63
DR_A_D0
D
D
DR_A_D1
DR_A_D2
D
D
DR_A_D3
D
DR_A_D4
D D
C C
B B
DDR_A_D5
D
DR_A_D6
DR_A_D7
D
D
DR_A_D8
DR_A_D9
D
D
DR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51
S
A_DQ0
A_DQ1
S
S
A_DQ2
A_DQ3
S
SA_DQ4
A_DQ5
S
A_DQ6
S
S
A_DQ7
S
A_DQ8
A_DQ9
S
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
HASWELL_MCP_E
DDR CHANNEL A
DDR CHANNEL A
4
S
A_CLK#0
A_CLK0
S
S
A_CLK#1
A_CLK1
S
A_CKE0
S
A_CKE1
S
S
A_CKE2
S
A_CKE3
SA_CS#0
SA_CS#1
SA_ODT0
SA_RAS
SA_WE
SA_CAS
SA_BA0
SA_BA1
SA_BA2
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7
SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1
AU37
AV37
AW36
AY36
AU43
AW43
AY42
AY43
AP33
AR32
AP32
AY34
AW34
AU34
AU35
AV35
AY41
AU36
AY37
AR38
AP36
AU39
AR36
AV40
AW39
AY39
AU40
AP35
AW41
AU41
AR35
AV42
AU42
AJ61
AN62
AM58
AM55
AV57
AV53
AL43
AL48
AJ62
AN61
AN58
AN55
AW57
AW53
AL42
AL49
AP49
AR51
AP51
DDRA_ODT0
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
S
A_CLK_DDR#0 <16>
A_CLK_DDR0 <16>
S
S
A_CLK_DDR#1 <16>
A_CLK_DDR1 <16>
S
DRA_CKE0_DIMMA < 16>
D
DRA_CKE1_DIMMA < 16>
D
DDRA_CS0_DIMMA# <16>
DDRA_CS1_DIMMA# <16>
T4@ T4@
DDR_A_RAS# <16>
DDR_A_WE# <16>
DDR_A_CAS# <16>
DDR_A_BS0 <16>
DDR_A_BS1 <16>
DDR_A_BS2 <16>
DDR_A_D[0..63]<16>
DDR_A_MA[0..15]<16>
DDR_A_DQS#[0..7]<16>
DDR_A_DQS[0..7]<16>
SM_DIMM_VREFCA <16>
SA_DIMM_VREFDQ <16>
SB_DIMM_VREFDQ <17>
3
U1D
U1D
AY31
DR_B_D0
D
D
DR_B_D1
D
DR_B_D2
DDR_B_D3
D
DR_B_D4
DR_B_D5
D
D
DR_B_D6
DR_B_D7
D
D
DR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18
S
B_DQ0
B_DQ1
S
SB_DQ2
B_DQ3
S
B_DQ4
S
S
B_DQ5
S
B_DQ6
B_DQ7
S
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
2
HASWELL_MCP_E
HASWELL_MCP_E
DDR CHANNEL B
DDR CHANNEL B
S
B_CK#0
B_CK0
S
SB_CK#1
B_CK1
S
S
B_CKE0
S
B_CKE1
B_CKE2
S
SB_CKE3
SB_CS#0
SB_CS#1
SB_ODT0
SB_RAS
SB_WE
SB_CAS
SB_BA0
SB_BA1
SB_BA2
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7
AM38
AN38
AK38
AL38
AY49
AU50
AW49
AV50
AM32
AK32
AL32
DDRB_ODT0
AM35
AK35
AM33
AL35
AM36
AU49
AP40
DDR_B_MA0
AR40
DDR_B_MA1
AP42
DDR_B_MA2
AR42
DDR_B_MA3
AR45
DDR_B_MA4
AP45
DDR_B_MA5
AW46
DDR_B_MA6
AY46
DDR_B_MA7
AY47
DDR_B_MA8
AU46
DDR_B_MA9
AK36
DDR_B_MA10
AV47
DDR_B_MA11
AU47
DDR_B_MA12
AK33
DDR_B_MA13
AR46
DDR_B_MA14
AP46
DDR_B_MA15
AW30
DDR_B_DQS#0
AV26
DDR_B_DQS#1
AN28
DDR_B_DQS#2
AN25
DDR_B_DQS#3
AW22
DDR_B_DQS#4
AV18
DDR_B_DQS#5
AN21
DDR_B_DQS#6
AN18
DDR_B_DQS#7
AV30
DDR_B_DQS0
AW26
DDR_B_DQS1
AM28
DDR_B_DQS2
AM25
DDR_B_DQS3
AV22
DDR_B_DQS4
AW18
DDR_B_DQS5
AM21
DDR_B_DQS6
AM18
DDR_B_DQS7
1
S
B_CLK_DDR#0 <17>
B_CLK_DDR0 <17>
S
SB_CLK_DDR#1 <17 >
B_CLK_DDR1 <17>
S
DRB_CKE0_DIMMB <17>
D
D
DRB_CKE1_DIMMB <17>
DDRB_CS0_DIMMB# <17>
DDRB_CS1_DIMMB# <17>
T5@ T5@
DDR_B_RAS# <17>
DDR_B_WE# <17>
DDR_B_CAS# <17>
DDR_B_BS0 <17>
DDR_B_BS1 <17>
DDR_B_BS2 <17>
DDR_B_D[0..63]<17>
DDR_B_MA[0..15]<17>
DDR_B_DQS#[0..7]<17>
DDR_B_DQS[0..7]<17>
Rev1p2
3 OF 19
3 OF 19
A A
5
Rev1p2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2012/07/10 2013/07/10
2012/07/10 2013/07/10
2012/07/10 2013/07/10
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4 OF 19
4 OF 19
2
Rev1p2
Rev1p2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
Date: Sheet
Compal Electronics, Inc.
HSW MCP(2/11) DDRIII
HSW MCP(2/11) DDRIII
HSW MCP(2/11) DDRIII
ZRMAA/ZEMAA
ZRMAA/ZEMAA
ZRMAA/ZEMAA
1
of
6 55Friday, June 21, 2013
of
6 55Friday, June 21, 2013
6 55Friday, June 21, 2013
0.4
0.4
0.4
5
1 2
@
@
CH_RTCX 1
CH_RTCR ST#
P
P
CH4
CH4
1U_0402 _6.3V6K
1U_0402 _6.3V6K
CH5
CH5
1U_0402 _6.3V6K
1U_0402 _6.3V6K
+RTCVCC
J
J
CMOS @
CMOS @
1 2
1 2
JME @
JME @
1 2
1 2
CH_RTCX 1_R<31 >
P
D D
RTCVCC
+
MOS Setting, near DDR Door
C
H23
H23
R
R
20K_040 2_5%
20K_040 2_5%
1 2
R
R
H26 0_0402_5%
H26 0_0402_5%
iME Setting.
1 2
RH24
RH24
20K_040 2_5%
20K_040 2_5%
PCH_INTVR MEN
INTVRMEN
*
C C
R73 330K_04 02_5%R73 330K_04 02_5%
Integrated VRM enable
H
L Integrated VRM disable
PCH_SRT CRST#
1 2
4
RTCVCC
+
1 2
R
R
72 1M_0402_ 5%
72 1M_0402_ 5%
AZ_SDIN0_HD<3 5>
1 2
R9851_0402 _5% @ R9 851_0402 _5% @
138 @
138 @
T
T
T6 @T6 @
T7 @T7 @
T8 @T8 @
T9 @T9 @
T95 @T95 @
T21 @T21 @
T19 @T19 @
T15 @T15 @
T10 @T10 @
T11 @T11 @
T22 @T22 @
T12 @T12 @
P
CH_RTCX 1
CH_RTCX 2
P
S
M_INTRUDE R#
CH_INTVRM EN
P
P
CH_SRTC RST#
CH_RTCR ST#
P
HDA_BIT_C LK
HDA_SYNC
HDA_RST #
HDA_SDO UT
PCH_JTA G_RST#
PCH_JTA G_TDI
PCH_JTA G_TDO
PCH_JTA G_TMS
PCH_TCK _JTAGX
3
U1E
U1E
AW5
R
TCX1
AY5
TCX2
R
A
U6
I
NTRUDER
AV7
NTVRMEN
I
A
V6
S
RTCRST
A
U7
TCRST
R
AW8
HDA_BCLK/I2S0_SCLK
AV11
HDA_SYNC/I2S0_SFRM
AU8
HDA_RST/I2S_MCLK
AY10
HDA_SDI0/I2S0_RXD
AU12
HDA_SDI1/I2S1_RXD
AU11
HDA_SDO/I2S0_TXD
AW10
HDA_DOCK_EN/I2S1_TXD
AV10
HDA_DOCK_RST/I2S1_SFRM
AY8
I2S1_SCLK
AU62
PCH_TRST
AE62
PCH_TCK
AD61
PCH_TDI
AE61
PCH_TDO
AD62
PCH_TMS
AL11
RSVD
AC4
RSVD
AE63
JTAGX
AV2
RSVD
HASWELL_MCP_E
HASWELL_MCP_E
RTC
RTC
JTAG
JTAG
5 OF 19
5 OF 19
2
SATA_IREF
RSVD
RSVD
SATALED
Rev1p2
Rev1p2
J5
H5
B15
A15
J8
H8
A17
B17
J6
H6
B14
C15
F5
E5
C17
D17
V1
U1
V6
AC1
A12
L11
K10
C12
U3
PU at Page09
EC_SMI#
ODD_DET ECT#
T159@ T159@
T165@ T165@
SATA_IREFPCH_JTA G_TCK
T13@ T13@
T14@ T14@
SATA_RC OMP
S
ATA_RN0/PERN6_L3
ATA_RP0/PERP6_L3
S
S
ATA_TN0/PETN6_L3
ATA_TP0/PETP6_L3
S
S
ATA_RN1/PERN6_L2
ATA_RP1/PERP6_L2
S
S
ATA_TN1/PETN6_L2
ATA_TP1/PETP6_L2
S
SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1
SATA_TN2/PETN6_L1
SATAAUDIO
SATAAUDIO
SATA_TP2/PETP6_L1
SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0
SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0
SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37
SATA_RCOMP
S
ATA_PRX _C_DTX_N0 <30>
ATA_PRX _C_DTX_P0 <30>
S
S
ATA_PTX _DRX_N0 <30>
S
ATA_PTX _DRX_P0 <30>
ATA_PRX _C_DTX_N1 <33>
S
ATA_PRX _C_DTX_P1 <33>
S
S
ATA_PTX _DRX_N1 <33>
ATA_PTX _DRX_P1 <33>
S
EC_SMI# <36 >
ODD_DET ECT# < 10>
@
@
1 2
R75 0_0603_ 5%
R75 0_0603_ 5%
ǁŝƚŚŝŶϱϬϬŵŝůƐ
1 2
R2 3.01 K_0402_1%R2 3.01 K_0402_1%
1
+1.05VS_ ASATA3PLL
HDD
S
SD
HDA for AUDIO
RP14
RP14
AZ_RST_ HD#<35>
AZ_BITCLK _HD<35>
AZ_SDOU T_HD<35>
AZ_SYNC_H D<35>
PWRME_CTRL<36>
1 8
2 7
3 6
4 5
33_0804 _8P4R_5%
33_0804 _8P4R_5%
1 2
@
@
R163 0_0402_ 5%
R163 0_0402_ 5%
ME Debug
B B
+RTCBAT T
1
DH1
+RTCVCC
3
1
CH8
CH8
0.1U_040 2_10V7K
0.1U_040 2_10V7K
2
A A
5
DH1
BAS40-04 _SOT23-3
BAS40-04 _SOT23-3
2
+3VL
HDA_RST #
HDA_BIT_C LK
HDA_SDO UT
HDA_SYNC
FAN Control Circuit
@
@
JFAN
+5VS
1A
C32
C32
10U_080 5_6.3V6M
10U_080 5_6.3V6M
U4
U4
1
EN
2
VIN
DFAN1<36>
Security Class ification
Security Class ification
Security Class ification
2012/07/ 10 2013/07/ 10
2012/07/ 10 2013/07/ 10
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2012/07/ 10 2013/07/ 10
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
+FAN2
10mil
SA00002XA00 EOL , SA00003UO00 X1
Main source SA00005CA00
2nd source SA00005JO00
2
3
4
12
C26
C26
10U_080 5_6.3V6M
10U_080 5_6.3V6M
VOUT
VSET
P2793BB 0_SO8
P2793BB 0_SO8
8
GND
7
GND
6
GND
5
GND
Title
Title
Title
Size Docum ent Number Rev
Size Docum ent Number Rev
Size Docum ent Number Rev
Custom
Custom
Custom
ZRMAA/ZEMAA
ZRMAA/ZEMAA
ZRMAA/ZEMAA
Date: Sheet of
Date: Sheet of
Date: Sheet of
+FAN2
@
@
2
12
C25
C25
1000P_0 402_50V7K
1000P_0 402_50V7K
1
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
HSW MCP(3/11) RTC,SATA,XDP
HSW MCP(3/11) RTC,SATA,XDP
HSW MCP(3/11) RTC,SATA,XDP
JFAN
1
2
3
4
5
CVILU_CI4403 M1HRT-NH
CVILU_CI4403 M1HRT-NH
R25 10K_040 2_5%R25 10K_0402 _5%
FAN_SPE ED1
1
C24
C24
0.01U_04 02_25V7K
0.01U_04 02_25V7K
@
@
2
1
2
3
GND
GND
12
1
+3VS
FAN_SPE ED1 <36>
7 55Friday, June 21, 201 3
7 55Friday, June 21, 201 3
7 55Friday, June 21, 201 3
0.4
0.4
0.4
5
P
CH_X1_R< 31>
4
H42
H42
R
R
12
22_0402 _5%GCLK@
22_0402 _5%GCLK@
P
CH_X1
Placement near to YH2
D D
LK_LAN#<32>
PCIE LAN
WLAN
+3VS
1 2
C C
RH8910K _0402_5% RH8910K _0402_5%
CLK_REQ _VGA#
C
CLK_LAN<32>
+3VS
CLKREQ_ LAN#<32>
CLK_WLAN#<31>
CLK_WLAN<31>
CLKREQ_WL AN#<10,31>
CLK_PCIE_VGA#<18>
CLK_PCIE_VGA<18>
CLK_REQ_VGA#<18>
1 2
R52 10K_040 2_5%R52 10K_0402_5%
LPC_AD0<36>
LPC_AD1<36>
LPC_AD2<36>
LPC_AD3<36>
LPC_FRA ME#<36>
CH_GPIO19
P
CLK_REQ _VGA#
T
T
158 @
158 @
T160 @T160 @
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRA ME#
PCH_SPICL K
PCH_SPICS 0#
PCH_SPIDI
PCH_SPIDO 1
PCH_SPIDO 2
PCH_SPIDO 3
3
C43
C42
U
2
B41
A41
5
Y
C41
B42
AD1
B38
C37
N1
A39
B39
U5
B37
A37
T2
AU14
AW12
AY12
AW11
AV12
AA3
Y7
Y4
AC2
AA2
AA4
Y6
AF1
U1F
U1F
C
LKOUT_PCIE_N0
LKOUT_PCIE_P0
C
P
CIECLKRQ0/GPIO18
CLKOUT_PCIE_N1
C
LKOUT_PCIE_P1
CIECLKRQ1/GPIO19
P
LKOUT_PCIE_N2
C
CLKOUT_PCIE_P2
PCIECLKRQ2/GPIO20
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
PCIECLKRQ3/GPIO21
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
PCIECLKRQ4/GPIO22
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
PCIECLKRQ5/GPIO23
U1G
U1G
LAD0
LAD1
LAD2
LAD3
LFRAME
SPI_CLK
SPI_CS0
SPI_CS1
SPI_CS2
SPI_MOSI
SPI_MISO
SPI_IO2
SPI_IO3
H
H
ASWELL_MCP_E
ASWELL_MCP_E
CLOCK
CLOCK
SIGNALS
SIGNALS
6 OF 19
6 OF 19
HASWELL_MCP_E
HASWELL_MCP_E
LPC
LPC
SMBUS
SMBUS
SPI C-LINK
SPI C-LINK
7 OF 19
7 OF 19
2
X
TAL24_IN
TAL24_OUT
X
SVD
R
RSVD
D
IFFCLK_BIASREF
T
ESTLOW_C35
ESTLOW_C34
T
TESTLOW_AK8
TESTLOW_AL8
CLKOUT_LPC_0
CLKOUT_LPC_1
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
Rev1p2
Rev1p2
SMBALERT/GPIO11
SMBCLK
SMBDATA
SML0ALERT/GPIO60
SML0CLK
SML1ALERT/PCHHOT/GPIO73
SML0DATA
SML1CLK/GPIO75
SML1DATA/GPIO74
CL_CLK
CL_DATA
CL_RST
Rev1p2
Rev1p2
A25
B25
K21
M21
C26
C35
C34
AK8
AL8
AN15
AP15
B35
A35
AN2
AP2
AH1
AL2
AN1
AK1
AU4
AU3
AH3
AF2
AD2
AF4
P
CH_X1
CH_X2
P
16@T16@
T
T17@ T17@
X
CLK_BIASR EF
1 2
R
R
140 1 0K_0402_5%
140 1 0K_0402_5%
1 2
141 1 0K_0402_5%
141 1 0K_0402_5%
R
R
1 2
R
R
142 1 0K_0402_5%
142 1 0K_0402_5%
1 2
R148 10K_04 02_5%R148 10K_ 0402_5%
CLKOUT_ LPC0
CLK_BCL K_ITP#
CLK_BCL K_ITP
PCH_SMB CLK
PCH_SMB DATA
PCH_SML CLK1
SUSW ARN#<9>
USB_CHG _OC#<11,34,36 >
1
2
1 2
R
R
78 3.01K_040 2_1%
78 3.01K_040 2_1%
R390 2 2_0402_5%
R390 2 2_0402_5%
T170@ T170@
T23@ T23@
T24@ T24@
T25@ T25@
12
EMI@
EMI@
T18@ T18@
T130@ T130@
SMB_ALE RT# <10>
PCH_SMB DATA <10 >
LAN_EN <1 0,32>
SML0CLK <10>
SML0DAT A <10>
PCH_SML DATA1 <1 0>
PU 2.2K at EC s ide (+3VS)
PCH_SML CLK1
PCH_SMB CLK
1
F
or HDD cannot d etect issue
P
CH_X1
C
C
71
71
12P_040 2_50V8J
12P_040 2_50V8J
@
@
1.05VS_A XCK_LCPLL
+
CLK_PCI_E C <36>
+3VALW _PCH
RP8
RP8
1 8
2 7
3 6
4 5
2.2K_080 4_8P4R_5%
2.2K_080 4_8P4R_5%
+3VALW _PCH
R116
R116
4.7K_040 2_5%
4.7K_040 2_5%
+3VS
1 2
R119
R119
4.7K_040 2_5%
4.7K_040 2_5%
1 2
PM_SMBD ATA <16,17,31,33>
PM_SMBC LK <16,17,31,33>
RH5 1K_0402 _5%RH5 1K_0402_5%
B B
RH16 1K_0402 _5%RH16 1K_0402_5%
12
12
EC_CS0#<36>
EC_SDIO<36>
PCH_SPIDO 1
PCH_SPIDO 2
PCH_SPIDO 2
PCH_SPIDO 3
RH61 15_0402 _5%885@RH61 15_040 2_5%885@
RH68 15_0402 _5%RH68 15_0402 _5%
RH69 15_0402 _5%RH69 15_0402 _5%
RH72 15_0402 _5%885@RH72 15_040 2_5%885@
SPI ROM for BIOS & ME & Win8 (8MByte )
1 2
1 2
1 2
1 2
PCH_SPICS 0#
PCH_SPI0_ DO1
PCH_SPI0_ DO2
UH3
UH3
1
CS#
2
SO
3
WP#
4
GND
64M EN25 QH64-104HIP SOP 8P
64M EN25 QH64-104HIP SOP 8P
VCC
HOLD#
SCLK
8
7
6
5
SI
+3VALW _PCH
CH9 0.1U_ 0402_10V7K
CH9 0.1U_ 0402_10V7K
1 2
1 2
PCH_SPI0_ DO3 PCH_SPIDO 3
PCH_SPI0_ CLK
PCH_SPI0_ DI
RH65 15_0402 _5%RH65 15_0402 _5%
1 2
RH66 15_0402 _5%RH66 15_0402 _5%
1 2
RH67 15_0402 _5%RH67 15_0402 _5%
1 2
RH74 15_0402 _5%885@RH74 15_040 2_5%885@
1 2
RH78 15_0402 _5%885@RH78 15_040 2_5%885@
PCH_SPICL K
PCH_SPIDI
EC_SCK <3 6>
EC_SDI < 36>
Q7A
DMN66D0 LDW-7_SOT3 63-6
DMN66D0 LDW-7_SOT3 63-6
PCH_SMB DATA
PCH_SMB CLK
DMN66D0 LDW-7_SOT3 63-6
DMN66D0 LDW-7_SOT3 63-6
Q7A
6 1
+3VS
2
5
3 4
Q7B
Q7B
Socket: SP07000F500/SP07000H900
Please place UH3 close to U1 CPU,
Please place RH66, RH67, RH68 near UH3
PCH_SPICL K
A A
Security Class ification
Security Class ification
Security Class ification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C70
C70
10P_040 2_50V8J
10P_040 2_50V8J
1 2
Compal Secret Data
Compal Secret Data
2012/07/ 10 2013/07/ 10
2012/07/ 10 2013/07/ 10
2012/07/ 10 2013/07/ 10
3
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
PCH_SML DATA1
PCH_SML CLK1
2
6 1
QH4A
QH4A
2N7002D W-T/R7_SOT3 63-6
2N7002D W-T/R7_SOT3 63-6
Title
Title
Title
Size Docum ent Number Rev
Size Docum ent Number Rev
Size Docum ent Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
3
2
QH4B
QH4B
2N7002D W-T/R7_SOT3 63-6
2N7002D W-T/R7_SOT3 63-6
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
HSW MCP(4/11) CLK,SPI,SMBUS
HSW MCP(4/11) CLK,SPI,SMBUS
HSW MCP(4/11) CLK,SPI,SMBUS
ZRMAA/ZEMAA
ZRMAA/ZEMAA
ZRMAA/ZEMAA
4
+3VS
EC_SMB_ DA2 <18,3 6>
EC_SMB_ CK2 <18,3 6>
1
0.4
0.4
0.4
8 55Friday, June 21, 201 3
8 55Friday, June 21, 201 3
8 55Friday, June 21, 201 3
5
+
3VS
12
227
227
R
R
10K_040 2_5%
10K_040 2_5%
YS_RESET#
S
D D
PCH_PW ROK< 36>
VCCST_P G_EC<12,36>
12
PCH_RSM RST#
R11710K_04 02_5% R11710K _0402_5%
+3VALW_P CH
12
R245
R245
100K_04 02_5%
100K_04 02_5%
D21
D21
ACIN<36,41>
C C
B B
1 2
RB751V4 0_SC76-2
RB751V4 0_SC76-2
PCH_ACIN
PCH_RSM RST#<36>
Note for PCH_AC IN: Deep Sx nee d use
EC GPIO for AC PRESENT functio n
Need to Check
4
P
CH_PW ROK
P
OK<36,42>
R
R
206
PLT_RST#<3 6>
SUSW ARN#<8>
PBTN_OU T#<36>
1 2
1 2
206
0_0402_ 5%@
0_0402_ 5%@
0_0402_ 5%@
0_0402_ 5%@
1 2
USWA RN#
S
1 2
R63 0_0402_ 5%@R63 0_ 0402_5%@
PCH_RSM RST# PCH_RSM RST#_R
+3VALW _PCH
PCH_PW M_TL<27>
PCH_PW M_EDP<28>
EC_ENBK L_R<28>
1 2
R79
R79
1 2
R156 8.2K_04 02_5%R156 8.2K_04 02_5%
RH17 0_0402_5 %LVDS@RH17 0_0402_5 %LVDS@
RH18 0_0402_5 %IEDP@RH18 0_0402_5%IEDP @
LCD_ENV DD<28>
VGA_PW ROK<22,47>
DGPU_PW R_EN<10,22>
DGPU_HO LD_RST#<10>
TP_INTR#< 10,33>
H2
H2
D
D
2
3
BAS40-04 _SOT23-3
BAS40-04 _SOT23-3
S
S
SYS_PW ROK
PCH_PW ROK
PLT_RST #
SUSW ARN#
PCH_ACIN
PCH_BAT LOW#
PCH_PW M
DGPU_HOLD_RST#
PCH_GPIO5 5
T157 @T 157 @
PCH_GPIO5 4
PCH_GPIO5 1
PCH_GPIO5 3
1
USACK#
YS_RESET#
T31 @T31 @
T26 @T26 @
3
P
CH_RSMR ST#
U1H
U1H
K2
A
USACK
S
A
C3
SYS_RESET
AG2
SYS_PWROK
AY7
PCH_PWROK
AB5
APWROK
AG7
PLTRST
AW6
RSMRST
AV4
SUSWARN/SUSPWRDNACK/GPIO30
AL7
PWRBTN
AJ8
ACPRESENT/GPIO31
AN4
BATLOW/GPIO72
AF3
SLP_S0
AM5
SLP_WLAN/GPIO29
U1I
U1I
B8
EDP_BKLCTL
A9
EDP_BKLEN
C6
EDP_VDDEN
U6
PIRQA/GPIO77
P4
PIRQB/GPIO78
N4
PIRQC/GPIO79
N2
PIRQD/GPIO80
AD4
PME
U7
GPIO55
L1
GPIO52
L3
GPIO54
R5
GPIO51
L4
GPIO53
HASWELL_MCP_E
HASWELL_MCP_E
S
S
YSTEM POWER MANAGEMENT
YSTEM POWER MANAGEMENT
HASWELL_MCP_E
HASWELL_MCP_E
eDP SIDEBAND
eDP SIDEBAND
GPIO
GPIO
8 OF 19
8 OF 19
DISPLAY
DISPLAY
C_SW I#
E
CLKRUN/GPIO32
SUS_STAT/GPIO61
SUSCLK/GPIO62
SLP_S5/GPIO63
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP
DDPB_HPD
DDPC_HPD
H171
H171
R
R
SWVRMEN
D
DPWROK
SLP_S4
SLP_S3
SLP_SUS
SLP_LAN
EDP_HPD
2
1K_0402 _5%
1K_0402 _5%
WAKE
SLP_A
Rev1p2
Rev1p2
3VALW _PCH
+
12
AW7
SWOD VREN
D
AV5
P
CH_RSMR ST#_R
AJ5
EC_SW I#
V5
CLKRUN#
AG4
AE6
AP5
PM_SLP_ S5#
AJ6
PM_SLP_ S4#
AT4
PM_SLP_ S3#
AL5
AP4
AJ7
PM_SLP_ LAN#
B9
C9
D9
D11
C5
B6
B5
A6
C8
A8
D6
1 2
R271 2.2K_04 02_5%R271 2.2K_04 02_5%
CPU_DP_ HPD
H_EDP_H PD
DSWODVREN - On Die DSW VR Enab le
H E
nable(DEFAULT)
*
isable
D
L
1 2
R
R
124 3 30K_0402_5%
124 3 30K_0402_5%
EC_SW I# <3 2,36>
1 2
R157 8.2K_040 2_5%R157 8.2K_040 2_5%
T104@ T104@
T27@ T27@
T28@ T28@
T30@ T30@
T96@ T96@
1 2
R118
@R118
@
10K_040 2_5%
10K_040 2_5%
+3VS
+
RTCVCC
CLK_EC <3 1>
PM_SLP_ S5# <36>
T29@ T29@
PM_SLP_ S4# <36>
PM_SLP_ S3# <36>
+3VALW _PCH
not support Dee p S4,S5 can NC
DDPB_CTRLDATA: Port B Detected
DDPC_CTRLDATA: Port C Detected
1: Port B or C is detected
*
0: Port B or C is not detected
(Have internal PD)
+3VS
UMA_HDM I_CLK <29>
UMA_HDM I_DATA <29>
CPU_DP_ HPD
HDMI_HPD <10,29 >
H_EDP_H PD <27,28 >
1
12
R418
R418
100K_04 02_5%
100K_04 02_5%
Rev1p2
9 OF 19
9 OF 19
PCH_PW ROK
R208
R208
10K_040 2_5%
10K_040 2_5%
A A
5
R65 0_0402_ 5%@R65 0_0 402_5%@
12
1 2
SYS_PW ROK
+3VS
5
PLT_RST#
DGPU_HOLD_RST#
4
1
IN1
VCC
IN2
GND
U37
U37
MC74VHC1G08DFT2G_ SC70-5
MC74VHC1G08DFT2G_ SC70-5
OPT@
OPT@
3
Security Class ification
Security Class ification
Security Class ification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
12
R391
R391
100K_04 02_5%
100K_04 02_5%
OPT@
OPT@
2012/07/ 10 2013/07/ 10
2012/07/ 10 2013/07/ 10
2012/07/ 10 2013/07/ 10
3
4
OUT
2
PLTRST_VGA# <18>
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Rev1p2
PLT_RST#
2
R403
R403
0_0402_ 5%
0_0402_ 5%
@
@
+3VS
5
1
IN1
VCC
OUT
2
IN2
GND
U30
U30
MC74VHC1G08DFT2G_ SC70-5
MC74VHC1G08DFT2G_ SC70-5
3
12
4
Title
Title
Title
Size Docum ent Number Rev
Size Docum ent Number Rev
Size Docum ent Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
H_EDP_H PD
12
R417
R417
100K_04 02_5%
100K_04 02_5%
12
R416
R416
100K_04 02_5%
100K_04 02_5%
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
HSW MCP(5/11) PM,GPIO,DDI
HSW MCP(5/11) PM,GPIO,DDI
HSW MCP(5/11) PM,GPIO,DDI
ZRMAA/ZEMAA
ZRMAA/ZEMAA
ZRMAA/ZEMAA
2
@ESD@
@ESD@
C489
C489
0.1U_040 2_10V7K
0.1U_040 2_10V7K
1
PLT_RST_BUF# <31,32,35>
1
0.4
0.4
0.4
9 55Friday, June 21, 201 3
9 55Friday, June 21, 201 3
9 55Friday, June 21, 201 3
5
+
3VS
D D
+3VALW _PCH
C C
+3VS
Note: need chec k all GPIO PU n eed or not after BIOS post
1 8
R
R
P23
RP34
RP34
P23
P27
P27
R
R
RP28
RP28
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
RP35
RP35
1 8
2 7
3 6
4 5
S
ERIRQ
DD_EN#
O
10K_080 4_8P4R_5%
10K_080 4_8P4R_5%
EVSLP1
D
O
DD_DA#
10K_080 4_8P4R_5%
10K_080 4_8P4R_5%
10K_080 4_8P4R_5%
10K_080 4_8P4R_5%
18
27
36
45
2.2K_080 4_8P4R_5%
2.2K_080 4_8P4R_5%
PCH_GPIO2 7
PASSW ORD_CLEAR#
10K_080 4_8P4R_5%
10K_080 4_8P4R_5%
T
P_INTR# <33 ,9>
DGPU_HO LD_RST# <9>
CLKREQ_ WLAN# < 31,8>
LAN_EN < 32,8>
USB_OC# 0 <11,34 ,36>
SMB_ALE RT# <8>
USB_OC# 2 <11,33 ,36>
SML0CLK <8>
SML0DAT A <8>
PCH_SMB DATA <8>
PCH_SML DATA1 <8 >
ODD_DET ECT# < 7>
DGPU_PW R_EN <22,9>
4
T
T
162 @
162 @
167 @
167 @
T
T
EC_LID_OU T#<3 6>
PASSW ORD_CLEAR#
12
JPW
JPW
@
@
EC_SCI#<3 6>
DEVSLP1<33>
PCH_SPK R<35>
T166 @T166 @
T163 @T163 @
T139 @T139 @
T168 @T168 @
T169 @T169 @
T136 @T136 @
EC_LID_OU T#
ODD_EN#
ODD_DA#
PCH_GPIO2 4
PCH_GPIO2 7
PCH_GPIO2 8
PCH_GPIO2 6
PCH_GPIO5 8
PCH_GPIO5 9
PCH_GPIO4 7
PCH_GPIO7 1
PCH_GPIO1 4
PCH_GPIO4 5
PCH_GPIO4 6
PCH_GPIO9
EC_SCI#
DEVSLP1
PCH_SPK R
3
U1J
U1J
P
1
B
MBUSY/GPIO76
AU2
PIO8
G
AM7
LAN_PHY_PWR_CTRL/GPIO12
AD6
GPIO15
Y1
GPIO16
T3
GPIO17
AD5
GPIO24
AN5
GPIO27
AD7
GPIO28
AN3
GPIO26
AG6
GPIO56
AP1
GPIO57
AL4
GPIO58
AT5
GPIO59
AK4
GPIO44
AB6
GPIO47
U4
GPIO48
Y3
GPIO49
P3
GPIO50
Y2
HSIOPC/GPIO71
AT3
GPIO13
AH4
GPIO14
AM4
GPIO25
AG5
GPIO45
AG3
GPIO46
AM3
GPIO9
AM2
GPIO10
P2
DEVSLP0/GPIO33
C4
SDIO_POWER_EN/GPIO70
L2
DEVSLP1/GPIO38
N5
DEVSLP2/GPIO39
V2
SPKR/GPIO81
HASWELL_MCP_E
HASWELL_MCP_E
GPIO
GPIO
10 OF 19
10 OF 19
CPU/
CPU/
MISC
MISC
LPIO
LPIO
2
T
HERMTRIP
CIN/GPIO82
R
SERIRQ
PCH_OPI_RCOMP
RSVD
RSVD
GSPI0_CS/GPIO83
GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86
GSPI1_CS/GPIO87
GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89
GSPI_MOSI/GPIO90
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART0_RTS/GPIO93
UART0_CTS/GPIO94
UART1_RXD/GPIO0
UART1_TXD/GPIO1
UART1_RST/GPIO2
UART1_CTS/GPIO3
I2C0_SDA/GPIO4
I2C0_SCL/GPIO5
I2C1_SDA/GPIO6
I2C1_SCL/GPIO7
SDIO_CLK/GPIO64
SDIO_CMD/GPIO65
SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69
Rev1p2
Rev1p2
D
60
4
V
T4
AW15
AF20
AB21
R6
PCH_GPIO83
L6
PCH_GPIO84
N6
PCH_GPIO85
L8
PCH_GPIO86
R7
DGPU_PR SNT#
L5
PCH_GPIO88
N7
PCH_GPIO89
K2
J1
K3
PCH_GPIO92
J2
PCH_GPIO93
G1
K4
G2
J3
J4
PCH_GPIO3
F2
F3
PCH_GPIO5
G4
PM_I2CSDA1
F1
PM_I2CSCL 1
E3
PCH_GPIO64
F4
PCH_GPIO65
D3
PCH_GPIO66
E4
PCH_GPIO67
C3
PCH_GPIO68
E2
SSD_DET ECT#
H
_THERMT RIP#
B_RST#
K
S
ERIRQ
PCH_OPIRCO MP
T106@ T106@
T135@ T135@
T134@ T134@
T114@ T114@
T111@ T111@
T133@ T133@
T132@ T132@
1 2
HDMI_HPD <29 ,9>
PM_I2CSDA1
PM_I2CSCL 1
R145
R145
49.9_040 2_1%
49.9_040 2_1%
PM_I2CSDA1 <33>
PM_I2CSCL 1 <3 3>
R274 1K_040 2_5%@R274 1K_0 402_5%@
R272 1K_040 2_5%@R272 1K_0 402_5%@
1
H_THERM TRIP#
ODD_DA#
CH6 180P _0402_50V8J
CH6 180P _0402_50V8J
1 2
1 2
B_RST# <36>
K
SERIRQ <36>
ESD@
ESD@
1 2
+1.05VS_ VTT
12
R144
R144
1K_0402 _5%
1K_0402 _5%
2
ESD@
ESD@
1
CH12
CH12
+3VS
0.1U_0402_10V7K
0.1U_0402_10V7K
+3VS
+3VS
B B
10K_040 2_5%
10K_040 2_5%
DGPU_PR SNT#
10K_040 2_5%
10K_040 2_5%
R306
R306
UMA@
UMA@
R219
R219
OPT@
OPT@
12
GPIO87
DGPU_PRSNT#
DIS,Optimus
1 2
UMA
0
1
+3VALW _PCH
1 2
R247 10K_04 02_5%R247 10K_ 0402_5%
10K_040 2_5%
10K_040 2_5%
GPIO15 : TLS Confidentiality
1: Intel ME TLS with confidentiality
A A
5
4
0: Intel ME TLS with no confidentiality
*
(Have internal PD)
Security Class ification
Security Class ification
Security Class ification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
12
R215
R215
SSD_DET ECT#
R30
R30
0_0402_ 5%
0_0402_ 5%
@
@
1 2
EC_LID_OU T#
SSD_DET ECT# <33 >
PCH_GPIO86
Ultra
Non-Ultra
1 2
R273 1K_040 2_5%@R273 1K_ 0402_5%@
GSPI0_MOSI / GPIO86 : Boot BIOS Strap
1: ENABLED
0: SPI ROM
*
Compal Secret Data
Compal Secret Data
2012/07/ 10 2013/07/ 10
2012/07/ 10 2013/07/ 10
2012/07/ 10 2013/07/ 10
3
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
(Have internal PD)
GPIO69
PROJECT_ID
0
1
2
Need to check the resistors value
+3VS
1 2
R269 1K_040 2_1%@R269 1K_0 402_1%@
PCH_SPK R
SPKR / GPIO81 : NO REBOOT
1: ENABLED
0: DISABLED
*
(Have internal PD)
PCH_GPIO66
R270 1K_040 2_1%@R270 1K_0 402_1%@
1 2
SDIO_D0 / GPIO66 : Top-Block Swap Override
1: ENABLED
*
0: DISABLED
Title
Title
Title
Size Docum ent Number Rev
Size Docum ent Number Rev
Size Docum ent Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
HSW MCP(6/11) GPIO,LPIO
HSW MCP(6/11) GPIO,LPIO
HSW MCP(6/11) GPIO,LPIO
ZRMAA/ZEMAA
ZRMAA/ZEMAA
ZRMAA/ZEMAA
(Have internal PU)
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
1
10 55Friday, June 21, 2 013
10 55Friday, June 21, 2 013
10 55Friday, June 21, 2 013
0.4
0.4
0.4
5
CIE_CTX_C _GRX_N0
P
P
CIE_GTX_C _CRX_N[0..3] < 18>
P
P
CIE_GTX_C _CRX_P[0..3] <18>
D D
PCIE_CTX_ C_GRX_N[0..3] < 18>
P
CIE_CTX_C _GRX_P[0..3] <18>
PCIE LAN
WLAN NGFF type
C C
WLAN min PCIE type
CIE_CTX_C _GRX_P0
P
CIE_CTX_C _GRX_N1
CIE_CTX_C _GRX_P1
P
PCIE_CTX_ C_GRX_P2 PEG_HTX_G RX_P2
PCIE_CTX_ C_GRX_N3 PEG_HTX_GRX_ N3
PCIE_PRX_ C_LANTX_N3<32>
PCIE_PRX_ C_LANTX_P3<32>
PCIE_PTX_ C_LANRX_N3<32>
PCIE_PTX_ C_LANRX_P3<32>
PCIE_PRX_ WLANTX_N4<31>
PCIE_PRX_ WLANTX_P4<31>
PCIE_PTX_ C_WLANRX_ N4<31>
PCIE_PTX_ C_WLANRX_ P4<3 1>
PCIE_PTX_ C_WLANRX_ N4_M<31>
PCIE_PTX_ C_WLANRX_ P4_M<31>
+1.05VS_ AUSB3PLL
C
C
C
C
C
C
C
C
C86 0.22U_0402_1 6V7KOPT@
C86 0.22U_0402_1 6V7KOPT@
C87 0.22U_0402_1 6V7KOPT@
C87 0.22U_0402_1 6V7KOPT@
C90 0.22U_0402_1 6V7KOPT@C90 0.22U_0402_ 16V7KOPT@
C91 0.22U_0402_1 6V7KOPT@C91 0.22U_0402_ 16V7KOPT@
R232 3 .01K_0402_1%R232 3 .01K_0402_1%
4
1 2
78 0.22U_0402_16 V7KOPT@
78 0.22U_0402_16 V7KOPT@
1 2
79 0.22U_0402_16 V7KOPT@
79 0.22U_0402_16 V7KOPT@
1 2
82 0.22U_0402_16 V7KOPT@
82 0.22U_0402_16 V7KOPT@
1 2
83 0.22U_0402_16 V7KOPT@
83 0.22U_0402_16 V7KOPT@
1 2
1 2
1 2
1 2
1 2
C155 0.1U_040 2_16V7K
C155 0.1U_040 2_16V7K
1 2
C160 0.1U_040 2_16V7KC160 0.1U_040 2_16V7K
NWL AN@
NWL AN@
1 2
C156 0.1U_040 2_16V7K
C156 0.1U_040 2_16V7K
1 2
C157 0.1U_040 2_16V7K
C157 0.1U_040 2_16V7K
NWL AN@
NWL AN@
MWLA N@
MWLA N@
1 2
C161 0.1U_040 2_16V7K
C161 0.1U_040 2_16V7K
1 2
C163 0.1U_040 2_16V7K
C163 0.1U_040 2_16V7K
MWLA N@
MWLA N@
1 2
P
CIE_GTX_C _CRX_N0
CIE_GTX_C _CRX_P0
P
EG_HTX_ GRX_N0
P
P
EG_HTX_ GRX_P0
P
CIE_GTX_C _CRX_N1
CIE_GTX_C _CRX_P1
P
P
EG_HTX_ GRX_N1
EG_HTX_ GRX_P1
P
CIE_GTX_C _CRX_N2
P
P
CIE_GTX_C _CRX_P2
PEG_HTX _GRX_N2PCIE_CTX_ C_GRX_N2
PCIE_GTX_ C_CRX_N3
PCIE_GTX_ C_CRX_P3
PEG_HTX _GRX_P3PCIE_CT X_C_GRX_P3
PCIE_PTX_ LANRX_N3
PCIE_PTX_ LANRX_P3
PCIE_PTX_ WLANRX_N4
PCIE_PTX_ WLANRX_P4
T33 @T33 @
T34 @T34 @
PCIE_RCOM P
F10
P
E10
P
C23
P
C22
P
F8
P
E8
P
B23
P
A23
P
H10
P
G10
PERP5_L2
B21
PETN5_L2
C21
PETP5_L2
E6
PERN5_L3
F6
PERP5_L3
B22
PETN5_L3
A21
PETP5_L3
G11
PERN3
F11
PERP3
C29
PETN3
B30
PETP3
F13
PERN4
G13
PERP4
B29
PETN4
A29
PETP4
G17
PERN1/USB3RN3
F17
PERP1/USB3RP3
C30
PETN1/USB3TN3
C31
PETP1/USB3TP3
F15
PERN2/USB3RN4
G15
PERP2/USB3RP4
B31
PETN2/USB3TN4
A31
PETP2/USB3TP4
E15
RSVD
E13
RSVD
A27
PCIE_RCOMP
B27
PCIE_IREF
U1K
U1K
ERN5_L0
ERP5_L0
ETN5_L0
ETP5_L0
ERN5_L1
ERP5_L1
ETN5_L1
ETP5_L1
ERN5_L2
3
HASWELL_MCP_E
HASWELL_MCP_E
PCIe
PCIe
USB3.0 P3 / PCIE P1
USB3.0 P4 / PCIE P2
11 OF 19
11 OF 19
USB
USB
USB3.0 P1
USB3.0 P2
U
SB2N0
SB2P0
U
SB2N1
U
U
SB2P1
U
SB2N2
SB2P2
U
U
SB2N3
SB2P3
U
SB2N4
U
USB2P4
USB2N5
USB2P5
USB2N6
USB2P6
USB2N7
USB2P7
USB3RN1
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USBRBIAS
USBRBIAS
RSVD
RSVD
OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43
Rev1p2
Rev1p2
AN8
AM8
AR7
AT7
AR8
AP8
AR10
AT10
AM15
AL15
AM13
AN13
AP11
AN11
AR13
AP13
G20
H20
C33
B34
E18
F18
B33
A33
AJ10
AJ11
AN10
AM10
AL3
AT1
AH2
AV3
2
R154 22.6_04 02_1%R1 54 22.6_040 2_1%
USBRBIAS
T35@ T35@
T36@ T36@
R234
R234
2.2K_040 2_5%
2.2K_040 2_5%
1 2
12
1
U
SB20_N0 <34>
SB20_P0 <34 >
U
SB20_N1 <34>
U
U
SB20_P1 <34 >
U
SB20_N2 <33>
U
SB20_P2 <33 >
U
SB20_N3 <33>
SB20_P3 <33 >
U
SB20_N4 <31>
U
USB20_P 4 <31>
USB20_N 5 <28>
USB20_P 5 <28>
USB20_N 7 <28>
USB20_P 7 <28>
U3RXDN1 <34>
U3RXDP1 <3 4>
U3TXDN1 <34>
U3TXDP1 < 34>
U3RXDN2 <34>
U3RXDP2 <3 4>
U3TXDN2 <34>
U3TXDP2 < 34>
ŶŽƚĞ
ZŽƵƚĞƐŝŶŐůĞͲĞŶĚϱϬͲŽŚŵƐĂŶĚŵĂdžϰϱϬͲŵŝůƐůĞŶŐƚŚ
ǀŽŝĚƌŽƵƚŝŶŐŶĞdžƚƚŽĐůŽĐŬƉŝŶƐŽƌƵŶĚĞƌƐƚŝƚĐŚŝŶŐĐĂƉĂĐŝƚŽƌƐ
ZĞĐŽŵŵĞŶĚĞĚŵŝŶŝŵƵŵƐƉĂĐŝŶŐƚŽŽƚŚĞƌƐŝŐŶĂůƚƌĂĐĞƐŝƐϭϱŵŝůƐ
USB_OC# 0 <10,34 ,36>
USB_CHG _OC# <34 ,36,8>
USB_OC# 2 <10,33 ,36>
+3VALW _PCH
USB-Right1
USB-Right2
USB-Left1
CardReader
WiMAX / BT
Touch Screen
Camera
USB-Right Rear
USB-Right Front
USB-Left
B B
A A
Security Class ification
Security Class ification
Security Class ification
2012/07/ 10 2013/07/ 10
2012/07/ 10 2013/07/ 10
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2012/07/ 10 2013/07/ 10
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Docum ent Number Rev
Size Docum ent Number Rev
Size Docum ent Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
HSW MCP(7/11) PCIE,USB
HSW MCP(7/11) PCIE,USB
HSW MCP(7/11) PCIE,USB
ZRMAA/ZEMAA
ZRMAA/ZEMAA
ZRMAA/ZEMAA
1
0.4
0.4
0.4
11 55Friday, June 21, 2 013
11 55Friday, June 21, 2 013
11 55Friday, June 21, 2 013
+1.05VS_ VTT
12
1 2
4
R166
R166
0_0402_ 5%
0_0402_ 5%
@
@
VCCST_PWRG D <36,44>
5
D D
+3VS
12
R422
R422
100K_04 02_5%
100K_04 02_5%
@
C C
VCCST_P G_EC<36,9>
@
U16
U16
NC1VCC
2
A
3
GND
74AUP1G 07GW_TSSO P5
74AUP1G 07GW_TSSO P5
+3VALW _PCH
5
4
Y
R309
R309
10K_040 2_5%
10K_040 2_5%
VCCST_P G_EC_R
SVID ALERT
+1.05VS_ VTT
Place the PU
12
resistors close to CPU
R171
R171
75_0402 _1%
75_0402 _1%
R172
R172
43_0402 _1%
43_0402 _1%
12
VR_SVID_A LRT#<46>
B B
SVID DATA
VR_SVID_D AT<46>
+CPU_CO RE
R174
R174
0_0402_ 5%
0_0402_ 5%
@
@
H_CPU_S VIDALRT#
+1.05VS_ VTT
Place the PU
resistors close to CPU
12
R173
R173
130_040 2_1%
130_040 2_1%
12
VIDSOUT
+1.35V
CC53
CC53
1
2
VR_SVID_C LK<46>
CC54
CC54
22U_0603_6.3V6M
22U_0603_6.3V6M
3
+VCCIOA_OU T
VR_ON<46>
VGATE<46>
Reserved Only
1
2
22U_0603_6.3V6M
22U_0603_6.3V6M
C167
C167
1 2
1 2
0.1U_040 2_16V7K
0.1U_040 2_16V7K
@
@
T131 @T131 @
+CPU_CO RE
+1.35V
+
1.35V
+
CPU_COR E
T107 @T1 07 @
R1670_0402_ 5% @ R1670_040 2_5% @
CPU_PW R_DEBUG
+1.05VS_ VTT
sYKhW>/E'
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
C8
C8
1
1
@
@
2
2
VCC_SEN SE_R
+VCCIO_OUT
H_CPU_S VIDALRT#
VIDSOUT
VCCST_P G_EC_R
PCH_VR_ EN
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6MC92.2U_0402_6.3V6M
C9
1
2
T
T
37 @
37 @
38 @
38 @
T
T
T39 @T39 @
T40 @T40 @
T41 @T41 @
T42 @T42 @
T44 @T44 @
T45 @T45 @
T46 @T46 @
T47 @T47 @
T48 @T48 @
T98 @T98 @
T142 @T142 @
T143 @T143 @
T144 @T144 @
T141 @T141 @
T140 @T140 @
T147 @T147 @
T145 @T145 @
T146 @T146 @
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
C10
C10
1
2
2
HASWELL_MCP_E
U1L
U1L
L59
R
SVD
J58
SVD
R
AH26
DDQ
V
AJ31
V
DDQ
AJ33
DDQ
V
AJ37
V
DDQ
AN33
DDQ
V
AP43
VDDQ
AR48
V
DDQ
AY35
DDQ
V
AY40
V
DDQ
AY44
DDQ
V
AY50
VDDQ
F59
VCC
N58
RSVD
AC58
RSVD
E63
VCC_SENSE
AB23
RSVD
A59
VCCIO_OUT
E20
VCCIOA_OUT
AD23
RSVD
AA23
RSVD
AE59
RSVD
L62
VIDALERT
N63
VIDSCLK
L63
VIDSOUT
B59
VCCST_PWRGD
F60
VR_EN
C59
VR_READY
D63
VSS
H59
PWR_DEBUG
P62
VSS
P60
RSVD_TP
P61
RSVD_TP
N59
RSVD_TP
N61
RSVD_TP
T59
RSVD
AD60
RSVD
AD59
RSVD
AA59
RSVD
AE60
RSVD
AC59
RSVD
AG58
RSVD
U59
RSVD
V59
RSVD
AC22
VCCST
AE22
VCCST
AE23
VCCST
AB57
VCC
AD57
VCC
AG57
VCC
C24
VCC
C28
VCC
C32
VCC
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
C11
C11
1
@
@
C12
C12
2
1
1
@
@
C13
C13
2
2
HASWELL_MCP_E
HSW ULT POWER
HSW ULT POWER
12 OF 19
12 OF 19
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C14
C14
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C15
C15
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C16
C16
C17
C17
2
1
+
CPU_COR E
C36
V
CC
C40
CC
V
C44
V
CC
C48
CC
V
C52
V
CC
C56
CC
V
E23
V
CC
E25
CC
V
E27
VCC
E29
V
CC
E31
CC
V
E33
V
CC
E35
CC
V
E37
VCC
E39
VCC
E41
VCC
E43
VCC
E45
VCC
E47
VCC
E49
VCC
E51
VCC
E53
VCC
E55
VCC
E57
VCC
F24
VCC
F28
VCC
F32
VCC
F36
VCC
F40
VCC
F44
VCC
F48
VCC
F52
VCC
F56
VCC
G23
VCC
G25
VCC
G27
VCC
G29
VCC
G31
VCC
G33
VCC
G35
VCC
G37
VCC
G39
VCC
G41
VCC
G43
VCC
G45
VCC
G47
VCC
G49
VCC
G51
VCC
G53
VCC
G55
VCC
G57
VCC
H23
VCC
J23
VCC
K23
VCC
K57
VCC
L22
VCC
M23
VCC
M57
VCC
P57
VCC
U57
VCC
W57
VCC
Rev1p2
Rev1p2
12
R177
R177
100_040 2_1%
100_040 2_1%
VCC_SEN SE_R
A A
VSS_SEN SE_R<1 4>
R233
R233
100_040 2_1%
100_040 2_1%
EŽƚĞϬŽŚŵW>>K^dKWh
12
R178
@ R1 78
@
0_0402_ 5%
0_0402_ 5%
12
R235
R235
0_0402_ 5%@
12
5
0_0402_ 5%@
VCC_SEN SE <46>
VSS_SEN SE <46>
+1.35V : 470UF/2V/7343 *2
10UF/6.3V/0603 * 6
2.2UF/6.3V/0402 * 4
Security Class ification
Security Class ification
Security Class ification
2012/07/ 10 2013/07/ 10
2012/07/ 10 2013/07/ 10
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2012/07/ 10 2013/07/ 10
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Docum ent Number Rev
Size Docum ent Number Rev
Size Docum ent Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
HSW MCP(8/11) Power
HSW MCP(8/11) Power
HSW MCP(8/11) Power
ZRMAA/ZEMAA
ZRMAA/ZEMAA
ZRMAA/ZEMAA
0.4
0.4
0.4
12 55Friday, June 21, 2 013
12 55Friday, June 21, 2 013
12 55Friday, June 21, 2 013
1
5
+
1.05VS_V TT
@
1
1
C21
C21
2
2
1U_0402_6.3V6K
D D
1 2
1 2
R210
@R210
@
0_0805_ 5%
0_0805_ 5%
1 2
1 2
1 2
1 2
+1.05VS_ AUSB3PLL
+1.05VS_ ASATA3PLL
+1.05VS_ APLLOPI
+1.05VS_ AXCK_DCB
+1.05VS_ AXCK_LCPLL
+1.05VS_ VTT
L1
L1
2.2UH_LQ M2MPN2R2NG0L _30%
2.2UH_LQ M2MPN2R2NG0L _30%
Idc 1.2A Rdc 0.11ohm +/-30%
L2
L2
2.2UH_LQ M2MPN2R2NG0L _30%
2.2UH_LQ M2MPN2R2NG0L _30%
Idc 1.2A Rdc 0.11ohm +/-30%
L3
L3
2.2UH_LQ M2MPN2R2NG0L _30%
2.2UH_LQ M2MPN2R2NG0L _30%
Idc 1.2A Rdc 0.11ohm +/-30%
C C
+1.05VS_ VTT
L4
L4
2.2UH_LQ M2MPN2R2NG0L _30%
2.2UH_LQ M2MPN2R2NG0L _30%
Idc 1.2A Rdc 0.11ohm +/-30%
L5
L5
2.2UH_LQ M2MPN2R2NG0L _30%
2.2UH_LQ M2MPN2R2NG0L _30%
Idc 1.2A Rdc 0.11ohm +/-30%
1U_0402_6.3V6K
ear K9 Near L 10 Near M9
N
Near B18
1 2
C42 1U_0402 _6.3V6KC42 1U_ 0402_6.3V6K
1 2
C64 22U_080 5_6.3V6MC64 22U_080 5_6.3V6M
Near B11
1 2
C46 1U_0402 _6.3V6KC46 1U_ 0402_6.3V6K
1 2
C65 22U_080 5_6.3V6MC65 22U_080 5_6.3V6M
Near AA21
1 2
C47 1U_0402 _6.3V6KC47 1U_ 0402_6.3V6K
1 2
C66 22U_080 5_6.3V6MC66 22U_080 5_6.3V6M
Near J18
1 2
C48 1U_0402 _6.3V6K
C48 1U_0402 _6.3V6K
1 2
C67 22U_060 3_6.3V6M
C67 22U_060 3_6.3V6M
Near A20
1 2
C49 1U_0402 _6.3V6KC49 1U_040 2_6.3V6K
1 2
C68 22U_080 5_6.3V6MC68 2 2U_0805_6.3V6 M
@
1
C20
C20
C31
C31
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
ESD@
ESD@
C35
C35
100P_0402_50V8J
100P_0402_50V8J
lose to CPU
C
+1.05VS_ VTT
Near J17
Near R21
4
ESD@
ESD@C60
ESD@
ESD@
C60
C39
C39
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
HDA --> 3.3V or 1.5V
I2C --> 1.8V
12
Near AC9
Near AH10
Near V8
C57
C57
12
1U_0402 _6.3V6K
1U_0402 _6.3V6K
C56
C56
12
1U_0402 _6.3V6K
1U_0402 _6.3V6K
+
1.05VS_A USB3PLL
1.05VS_A SATA3PLL
+
1.05VS_A PLLOPI
+
+
3VALW _PCH
C38
C38
1U_0402 _6.3V6K
1U_0402 _6.3V6K
C28
C28
12
22U_060 3_6.3V6M
22U_060 3_6.3V6M
C59
@C59
@
12
0.1U_040 2_16V7K
0.1U_040 2_16V7K
C29
C29
12
22U_060 3_6.3V6M
22U_060 3_6.3V6M
+3VS
+1.05VS_ AXCK_DCB
+1.05VS_ AXCK_LCPLL
+3VALW _PCH
T99 @T99 @
T105 @T105 @
T116 @T116 @
+3VALW _PCH
T100 @T100 @
T101 @T101 @
B18
B11
Y20
AA21
W21
AH14
AH13
AC9
AA9
AH10
K19
A20
R21
T21
K18
M20
V21
AE20
AE21
L10
J13
W9
J18
J17
K9
M9
N8
P9
V8
U1M
U1M
CCHSIO
V
V
CCHSIO
CCHSIO
V
V
CC1_05
CC1_05
V
V
CCUSB3PLL
CCSATA3PLL
V
RSVD
V
CCAPLL
CCAPLL
V
DCPSUS3
VCCHDA
DCPSUS2
VCCSUS3_3
VCCSUS3_3
VCCDSW3_3
VCC3_3
VCC3_3
VCCCLK
VCCCLK
VCCACLKPLL
VCCCLK
VCCCLK
VCCCLK
RSVD
RSVD
RSVD
VCCSUS3_3
VCCSUS3_3
3
mPHY
mPHY
OPI
OPI
USB3
USB3
AXALIA/HDA
AXALIA/HDA
VRM/USB2/AZALIA
VRM/USB2/AZALIA
GPIO/LCC
GPIO/LCC
LPT LP POWER
LPT LP POWER
HASWELL_MCP_E
HASWELL_MCP_E
13 OF 19
13 OF 19
RTC
RTC
SPI
SPI
CORE
CORE
THERMAL SENSOR
THERMAL SENSOR
SDIO/PLSS
SDIO/PLSS
SUS OSCILLATOR
SUS OSCILLATOR
USB2
USB2
V
CCSUS3_3
CCRTC
V
D
CPRTC
VCCSPI
V
CCASW
CCASW
V
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
DCPSUSBYP
DCPSUSBYP
VCCASW
VCCASW
VCCASW
DCPSUS1
DCPSUS1
VCCTS1_5
VCC3_3
VCC3_3
VCCSDIO
VCCSDIO
DCPSUS4
RSVD
VCC1_05
VCC1_05
Rev1p2
Rev1p2
+
3VALW _PCH
30 1U_0402_ 6.3V6K
30 1U_0402_ 6.3V6K
C
AH11
AG10
AE7
Y8
AG14
AG13
J11
H11
H15
AE8
AF22
AG19
AG20
AE9
AF9
AG8
AD10
AD8
J15
K14
K16
U8
T9
AB8
AC20
AG16
AG17
C
+
VCCRTCE XT
54 0.1U_0402 _16V7K
54 0.1U_0402 _16V7K
C
C
+
3VALW _PCH
C58 0.1U_040 2_16V7K
C58 0.1U_040 2_16V7K
C27 10U_060 3_6.3V6M
C27 10U_060 3_6.3V6M
C33 1U_0402 _6.3V6K
C33 1U_0402 _6.3V6K
C40 1U_0402 _6.3V6KC40 1U_040 2_6.3V6K
+PCH_VC CDSW
C36 22U_080 5_6.3V6MC36 2 2U_0805_6.3V6 M
C37 1U_0402 _6.3V6KC37 1U_040 2_6.3V6K
1 2
C55 0.1U_040 2_16V7K
C55 0.1U_040 2_16V7K
1 2
C44 1U_0402_ 6.3V6K
C44 1U_0402_ 6.3V6K
T137@ T137@
T103@ T103@
+1.05VS_ VTT
1 2
C45 1U_0402_ 6.3V6KC45 1U_0402_ 6.3V6K
2
1 2
1 2
@
@
1 2
1 2
1 2
1 2
1 2
T108@ T108@
12
RTCVCC
+
+
1.05VS_V TT
+1.05VS_ VTT
+1.05VS_ VTT
+1.5VS
+3VS
+3VS
+
1U_0402_6.3V6K
1U_0402_6.3V6K
C41
C41
1U_0402 _6.3V6K
1U_0402 _6.3V6K
1 2
C69
C69
1 2
Near AG19
1
RTCVCC
1
@
@
C51
C51
C52
C52
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.47U_04 02_16V4Z
0.47U_04 02_16V4Z
1
2
1
@
@
C50
C50
2
0.1U_0402_16V7K
0.1U_0402_16V7K
+3VALW _PCH
+3VALW to +3VALW_PCH
B B
PCH_PW R_EN#< 38>
A A
5
PCH_PW R_EN#
+3VALW
12
RH3 47K_ 0402_5%RH3 47K_0 402_5%
4
Q10
Q10
AO3413_ SOT23
AO3413_ SOT23
S
S
G
G
1
CH1110.1U_0402_25V6
CH1110.1U_0402_25V6
2
+3VALW _PCH
D
D
13
2
1
CH1130.1U_0402_10V7K
CH1130.1U_0402_10V7K
CH1120.01U_0402_25V7K CH1120.01U_0402_25V7K
2
Security Class ification
Security Class ification
Security Class ification
2012/07/ 10 2013/07/ 10
2012/07/ 10 2013/07/ 10
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2012/07/ 10 2013/07/ 10
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Docum ent Number Rev
Size Docum ent Number Rev
Size Docum ent Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet
Compal Electronics, Inc.
HSW MCP(9/11) Power
HSW MCP(9/11) Power
HSW MCP(9/11) Power
ZRMAA/ZEMAA
ZRMAA/ZEMAA
ZRMAA/ZEMAA
13 55Friday, June 21, 2 013
13 55Friday, June 21, 2 013
13 55Friday, June 21, 2 013
1
of
0.4
0.4
0.4
5
H
H
ASWELL_MCP_E
ASWELL_MCP_E
U1N
D D
C C
B B
A11
A14
A18
A24
A28
A32
A36
A40
A44
A48
A52
A56
AA1
AA58
AB10
AB20
AB22
AB7
AC61
AD21
AD3
AD63
AE10
AE5
AE58
AF11
AF12
AF14
AF15
AF17
AF18
AG1
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
AJ13
AJ14
AJ23
AJ25
AJ27
AJ29
V
V
V
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U1N
SS
SS
SS
14 OF 19
14 OF 19
SS
V
V
SS
SS
V
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Rev1p2
Rev1p2
AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20
4
H
H
ASWELL_MCP_E
ASWELL_MCP_E
U1O
U1O
AP22
AP23
AP26
AP29
AP3
AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49
AR5
AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63
AU1
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55
V
V
V
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SS
SS
SS
15 OF 19
15 OF 19
Rev1p2
Rev1p2
V
V
V
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SS
SS
SS
AV59
AV8
AW16
AW24
AW33
AW35
AW37
AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31
3
U1P
U1P
HASWELL_MCP_E
V
V
V
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SS
SS
SS
HASWELL_MCP_E
16 OF 19
16 OF 19
G18
G22
D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49
D50
D51
D53
D54
D55
D57
D59
D62
E11
E17
F20
F26
F30
F34
F38
F42
F46
F50
F54
F58
F61
H13
D5
D8
G3
G5
G6
G8
VSS_SENSE
Rev1p2
Rev1p2
V
V
V
V
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
2
H17
SS
H57
SS
J10
SS
J22
SS
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63
V58
AH46
V23
E62
AH16
VSS_SEN SE_R <12>
1
A A
Security Class ification
Security Class ification
Security Class ification
2012/07/ 10 2013/07/ 10
2012/07/ 10 2013/07/ 10
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2012/07/ 10 2013/07/ 10
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Docum ent Number Rev
Size Docum ent Number Rev
Size Docum ent Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
HSW MCP(10/11) GND
HSW MCP(10/11) GND
HSW MCP(10/11) GND
ZRMAA/ZEMAA
ZRMAA/ZEMAA
ZRMAA/ZEMAA
0.4
0.4
0.4
14 55Friday, June 21, 2 013
14 55Friday, June 21, 2 013
14 55Friday, June 21, 2 013
1
5
H
H
ASWELL_MCP_E
U1Q
U1Q
D
C_TEST_ AY2_AW2
C_TEST_ AY3_AW3
D
T
T
49 @
49 @
C_TEST_ AY61_AW61
D
DC_TEST _AY62_AW62
T
T
50 @
D D
50 @
C_TEST_ A3_B3
D
D
C_TEST_ A61_B61
C_TEST_ B62_B63
D
DC_TEST _C1_C2
AY2
D
AISY_CHAIN_NCTF_AY2
AY3
AISY_CHAIN_NCTF_AY3
D
AY60
D
AISY_CHAIN_NCTF_AY60
AY61
AISY_CHAIN_NCTF_AY61
D
AY62
DAISY_CHAIN_NCTF_AY62
B2
D
AISY_CHAIN_NCTF_B2
B3
AISY_CHAIN_NCTF_B3
D
B61
D
AISY_CHAIN_NCTF_B61
B62
AISY_CHAIN_NCTF_B62
D
B63
DAISY_CHAIN_NCTF_B63
C1
DAISY_CHAIN_NCTF_C1
C2
DAISY_CHAIN_NCTF_C2
U1S
U1S
ASWELL_MCP_E
17 OF 19
17 OF 19
HASWELL_MCP_E
HASWELL_MCP_E
4
D
AISY_CHAIN_NCTF_A3
AISY_CHAIN_NCTF_A4
D
AISY_CHAIN_NCTF_A60
D
DAISY_CHAIN_NCTF_A61
D
AISY_CHAIN_NCTF_A62
AISY_CHAIN_NCTF_AV1
D
D
AISY_CHAIN_NCTF_AW1
AISY_CHAIN_NCTF_AW2
D
DAISY_CHAIN_NCTF_AW3
DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63
Rev1p2
Rev1p2
A3
A4
A60
A61
A62
AV1
AW1
AW2
D
AW3
D
AW61
DC_TEST _AY61_AW61
AW62
DC_TEST _AY62_AW62
AW63
D
C_TEST_ A3_B3
DC_TEST _A61_B61
C_TEST_ AY2_AW2
C_TEST_ AY3_AW3
3
U1R
U1R
T
T
51 @
58@T58@
T
59@T59@
T
T
60@T60@
61@T61@
T
T
62@T62@
T63@ T63@
51 @
52 @
52 @
T
T
T
T
53 @
53 @
54 @
54 @
T
T
55 @
55 @
T
T
T
T
56 @
56 @
57 @
57 @
T
T
AT2
AU44
AV44
D15
F22
H22
R
SVD
SVD
R
R
SVD
SVD
R
SVD
R
R
SVD
J21
SVD
R
2
H
H
ASWELL_MCP_E
ASWELL_MCP_E
R
SVD
SVD
R
R
SVD
SVD
R
SVD
R
R
SVD
SVD
R
RSVD
RSVD
RSVD
RSVD
Rev1p2
18 OF 19
18 OF 19
Rev1p2
N23
R23
T23
U10
AL1
AM11
AP7
AU10
AU15
AW14
AY14
1
T
64@T64@
65@T65@
T
T
66@T66@
67@T67@
T
68@T68@
T
T
69@T69@
70@T70@
T
T
71@T71@
T72@ T72@
T73@ T73@
T74@ T74@
AC60
CFG_RCO MP
T90 @T90 @
T91 @T91 @
T92 @T92 @
T93 @T93 @
T94 @T94 @
TD_IREF
12
12
12
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG18
CFG17
CFG19
CFG0
AC62
CFG1
AC63
CFG2
AA63
CFG3
AA60
CFG4
Y62
CFG5
Y61
CFG6
Y60
CFG7
V62
CFG8
V61
CFG9
V60
CFG10
U60
CFG11
T63
CFG12
T62
CFG13
T61
CFG14
T60
CFG15
AA62
CFG16
U63
CFG18
AA61
CFG17
U62
CFG19
V63
CFG_RCOMP
A5
RSVD
E1
RSVD
D1
RSVD
J20
RSVD
H18
RSVD
B12
TD_IREF
CFG_RCO MP
OPI_COMP
TD_IREF
RESERVED
RESERVED
19 OF 19
19 OF 19
PROC_OPI_RCOMP
T110 @T110 @
T109 @T109 @
T112 @T112 @
C C
B B
T113 @T113 @
T117 @T117 @
T115 @T115 @
T119 @T119 @
T118 @T118 @
T121 @T121 @
T120 @T120 @
T124 @T124 @
T122 @T122 @
T125 @T125 @
T123 @T123 @ T84@ T84@
T128 @T128 @
T127 @T127 @
T129 @T129 @ T86@ T86@
T126 @T126 @
R222 4 9.9_0402_1%R222 49 .9_0402_1%
R223 4 9.9_0402_1%R223 49 .9_0402_1%
R226 8 .2K_0402_5%R226 8.2K_04 02_5%
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
VSS
VSS
RSVD
RSVD
Rev1p2
Rev1p2
AV63
AU63
C63
C62
B43
A51
B51
L60
N60
W23
Y22
AY15
AV62
D58
P22
N21
P20
R20
T75@ T75@
T76@ T76@
T77@ T77@
T78@ T78@
T79@ T79@
T80@ T80@
T81@ T81@
T82@ T82@
T83@ T83@
T85@ T85@
OPI_COMP
T87@ T87@
T88@ T88@
T89@ T89@
CFG Straps for Processor
CFG3
Physical Debug Enable (DFX Privacy)
CFG3
1: DISABLED
0: ENABLED; SET DFX ENABLED BIT
IN DEBUG INTERFACE MSR
Display Port Presence Strap
CFG4
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
CFG4
12
12
R224
R224
1K_0402 _1%
1K_0402 _1%
@
@
R225
R225
1K_0402 _5%
1K_0402 _5%
A A
Security Class ification
Security Class ification
Security Class ification
2012/07/ 10 2013/07/ 10
2012/07/ 10 2013/07/ 10
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2012/07/ 10 2013/07/ 10
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Docum ent Number Rev
Size Docum ent Number Rev
Size Docum ent Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
HSW MCP(11/11) RSVD
HSW MCP(11/11) RSVD
HSW MCP(11/11) RSVD
ZRMAA/ZEMAA
ZRMAA/ZEMAA
ZRMAA/ZEMAA
0.4
0.4
0.4
15 55Friday, June 21, 2 013
15 55Friday, June 21, 2 013
15 55Friday, June 21, 2 013
1
D
DR_A_D4
D
DR_A_D5
D
DR_A_D3
DR_A_D7
D
D
DR_A_D8
DDR_A_D13
D
DR_A_DQS#1
DR_A_DQS1
D
DR_A_D15
D
DDR_A_D11
DDR_A_D21
DDR_A_D18
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D23
DDR_A_D17
DDR_A_D33
DDR_A_D36
DDR_A_D35
DDR_A_D39
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
SA_CLK_DDR0
SA_CLK_DDR#0
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_A_D45
DDR_A_D40
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D43
DDR_A_D42
DDR_A_D25
DDR_A_D24
DDR_A_D26
DDR_A_D31
DDR_A_D59
DDR_A_D58
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D57
DDR_A_D56
DDR_A_D52
DDR_A_D53
DDR_A_D49
DDR_A_D48
R211
R211
0_0402_5%
0_0402_5%
@
@
1 2
B
+
1.35V
R212
R212
0_0402_5%
0_0402_5%
DDR3L
DDR3L
J
J
1
V
REF_DQ
3
SS
V
5
D
Q0
7
Q1
D
9
V
SS
11
M0
D
13
V
SS
15
Q2
D
17
Q3
D
19
V
SS
21
Q8
D
23
DQ9
25
V
SS
27
QS1#
D
29
D
QS1
31
SS
V
33
D
Q10
35
DQ11
37
VSS
39
DQ16
41
DQ17
43
VSS
45
DQS2#
47
DQS2
49
VSS
51
DQ18
53
DQ19
55
VSS
57
DQ24
59
DQ25
61
VSS
63
DM3
65
VSS
67
DQ26
69
DQ27
71
VSS
73
CKE0
75
VDD
77
NC
79
BA2
81
VDD
83
A12/BC#
85
A9
87
VDD
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VDD
101
CK0
103
CK0#
105
VDD
107
A10/AP
109
BA0
111
VDD
113
WE#
115
CAS#
117
VDD
119
A13
121
S1#
123
VDD
125
TEST
127
VSS
129
DQ32
131
DQ33
133
VSS
135
DQS4#
137
DQS4
139
VSS
141
DQ34
143
DQ35
145
VSS
147
DQ40
149
DQ41
151
VSS
153
DM5
155
VSS
157
DQ42
159
DQ43
161
VSS
163
DQ48
165
DQ49
167
VSS
169
DQS6#
171
DQS6
173
VSS
175
DQ50
177
DQ51
179
VSS
181
DQ56
183
DQ57
185
VSS
187
DM7
189
VSS
191
DQ58
193
DQ59
195
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
207
BOSS1
LCN_DAN06-K4406-0103
LCN_DAN06-K4406-0103
@
@
D
QS0#
D
D
DQ13
R
ESET#
D
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQS3#
DQS3
DQ30
DQ31
CKE1
VDD
VDD
VDD
VDD
VDD
CK1#
VDD
RAS#
VDD
ODT0
VDD
ODT1
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
GND2
BOSS2
V
D
D
V
QS0
V
D
D
V
Q12
V
D
V
Q14
VSS
VSS
DM2
VSS
VSS
VSS
VSS
VSS
CK1
BA1
SCL
VTT
+
1.35V
2
SS
4
DR_A_D0
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
D
D
DR_A_D1
DR_A_DQS#0
D
D
DR_A_DQS0
D
DR_A_D6
DR_A_D2
D
D
DR_A_D9
DDR_A_D12
IMM_DRAMRST#
D
DR_A_D14
D
DDR_A_D10
DDR_A_D19
DDR_A_D20
DDR_A_D22
DDR_A_D16
DDR_A_D37
DDR_A_D32
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D38
DDRA_CKE1_DIMMA
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
SA_CLK_DDR1
SA_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
DDRA_CS0_DIMMA#
SA_ODT0
SA_ODT1
+VREF_CA
DDR_A_D44
DDR_A_D41
DDR_A_D47
DDR_A_D46
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D27
DDR_A_D62
DDR_A_D63
DDR_A_D61
DDR_A_D60
DDR_A_D50
DDR_A_D51
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D55
DDR_A_D54
+0.675VS
Q4
Q5
SS
SS
Q6
Q7
SS
SS
M1
SS
A15
A14
A11
A7
A6
A4
A2
A0
S0#
NC
Channel A
A
A_DIMM_VREFDQ<6>
S
158
158
C
C
0.022U_0402_25V7K
0.022U_0402_25V7K
1 1
R
R
24.9_0402_1%
24.9_0402_1%
176
176
1 2
1
@
@
2
12
@
@
R
R
293
293
2_0402_1%
2_0402_1%
1.35V
+
12
12
R
R
54
54
1.8K_0402_1%
1.8K_0402_1%
R
R
185
185
1.8K_0402_1%
1.8K_0402_1%
+
V_DDR_REFA
C106
C106
0.1U_0402_16V7K
0.1U_0402_16V7K
1
2
Note: Depend on Project
Layout Note:
Place near JDIMM1
+1.35V
C
C
C
C
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
107
107
108
1
@
@
2
2 2
+1.35V
1
2
+1.35V
1
2
3 3
+0.675VS
1
@
@
2
Layout Note:
Place near JDIMM1.203,204
4 4
108
1
1
@
@
2
2
C
C
10U_0603_6.3V6M
10U_0603_6.3V6M
111
111
C
C
10U_0603_6.3V6M
10U_0603_6.3V6M
115
115
C
C
1U_0402_6.3V6K
1U_0402_6.3V6K
121
121
C
C
C
C
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
113
113
112
112
1
1
2
2
C
C
C
C
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
116
116
117
117
1
1
@
@
2
2
C
C
1U_0402_6.3V6K
1U_0402_6.3V6K
122
122
1
1
@
@
2
2
C
C
C
C
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
110
109
110
109
1
2
C
C
10U_0603_6.3V6M
10U_0603_6.3V6M
114
114
1
2
C
C
C
C
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
124
124
123
123
1
2
All VREF traces should
have 10 mil trace width
DDRA_CKE0_DIMMA<6>
DDR_A_BS2<6 >
SA_CLK_DDR0<6>
SA_CLK_DDR#0<6>
DDR_A_BS0<6>
DDR_A_WE#<6>
DDR_A_CAS#<6>
DDRA_CS1_DIMMA#<6>
+3VS
+0.675VS
C125
C125
0.1U_0402_16V7K
0.1U_0402_16V7K
1
2
DDRA_CKE0_DIMMA
DDR_A_BS2
DDRA_CS1_DIMMA#
@
@
1 2
C
DDR3 SO-DIMM A
everse Type
R
H=4.0mm
D
D
IMM_DRAMRST# <17,5>
SA_CLK_DDR1 <6>
SA_CLK_DDR#1 <6>
DDR_A_BS1 <6>
DDR_A_RAS# <6>
PM_SMBDATA <17,31,33 ,8>
PM_SMBCLK <17,31 ,33,8>
DR_PG_CTRL<5>
DDRA_CKE1_DIMMA <6>
DDRA_CS0_DIMMA# <6>
0.1U_0402_16V7K
0.1U_0402_16V7K
C120
C120
1
2
Note: Depend on Project
DDR_A_DQS#[0..7] <6>
DDR_A_DQS[0..7] <6>
DDR_A_D[0..63] <6>
DDR_A_MA[0..15] <6>
+1.35V
12
R56
R56
1.8K_0402_1%
1.8K_0402_1%
R296
R296
1 2
2_0402_1%
2_0402_1%
12
R295
R295
1.8K_0402_1%
1.8K_0402_1%
+VREF_CA <17>
0.1U_0402_16V7K
0.1U_0402_16V7K
U
U
45
45
1
C
N
2
3
V
A
G
ND
74AUP1G07GW_TSSOP5
74AUP1G07GW_TSSOP5
1
@
@
2
12
@ R294
@
+
1.35V
C34
C34
1
@
@
2
5
CC
4
Y
C162
C162
0.022U_0402_25V7K
0.022U_0402_25V7K
R294
24.9_0402_1%
24.9_0402_1%
D
+
SM_DIMM_VREFCA <6>
5VS
+
191
191
R
R
100K_0402_5%
100K_0402_5%
1 2
2
G
G
DDR_VTT_PG_CTRL <43>
1.35V
Q
Q
18
18
LBSS138LT1G_SOT-23-3
LBSS138LT1G_SOT-23-3
13
D
D
S
S
_A_B_DIMM_ODT
M
1 2
187
187
R
R
66.5_0402_1%
66.5_0402_1%
188
188
R
R
1 2
66.5_0402_1%
66.5_0402_1%
1 2
R189
R189
66.5_0402_1%
66.5_0402_1%
190
190
R
R
1 2
66.5_0402_1%
66.5_0402_1%
E
A_ODT0
S
A_ODT1
S
SB_ODT0
B_ODT1
S
S
B_ODT0 <17>
S
B_ODT1 <17>
<Address: SA1:SA0=00>
Note: Depend on Project
A
DIMM_1 STD H:4mm
B
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2012/07/10 2013/07/10
2012/07/10 2013/07/10
2012/07/10 2013/07/10
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDRIII DIMMA
DDRIII DIMMA
DDRIII DIMMA
ZRMAA/ZEMAA
ZRMAA/ZEMAA
ZRMAA/ZEMAA
16 55Friday, June 21, 2013
16 55Friday, June 21, 2013
E
16 55Friday, June 21, 2013
0.4
0.4
0.4
D
DR_B_D19
D
DR_B_D17
D
DR_B_D21
DR_B_D20
D
D
DR_B_D5
DDR_B_D4
D
DR_B_DQS#0
DR_B_DQS0
D
DR_B_D3
D
DDR_B_D2
DDR_B_D24
DDR_B_D25
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D31
DDR_B_D27
DDR_B_D12
DDR_B_D13
DDR_B_D10
DDR_B_D14
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_B_D36
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D38
DDR_B_D34
DDR_B_D44
DDR_B_D41
DDR_B_D47
DDR_B_D43
DDR_B_D52
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D54
DDR_B_D63
DDR_B_D62
DDR_B_D60
DDR_B_D58
R231
R231
0_0402_5%
0_0402_5%
+
B
1.35V
DDR3H
DDR3H
J
J
1
V
REF_DQ
3
SS2
V
5
D
Q0
7
Q1
D
9
V
SS4
11
M0
D
13
V
SS5
15
Q2
D
17
Q3
D
19
V
SS7
21
Q8
D
23
DQ9
25
V
SS9
27
QS#1
D
29
D
QS1
31
SS11
V
33
D
Q10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
LCN_DAN06-K4406-0102
LCN_DAN06-K4406-0102
@
@
V
D
D
V
D
QS#0
QS0
D
V
D
D
V
D
DQ13
V
SS10
D
R
ESET#
SS12
V
D
DQ15
DQ20
DQ21
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
VTT2
+
1.35V
2
SS1
4
DR_B_D16
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
D
D
DR_B_D18
DR_B_DQS#2
D
D
DR_B_DQS2
D
DR_B_D22
DR_B_D23
D
D
DR_B_D1
DDR_B_D0
IMM_DRAMRST#
D
DR_B_D6
D
DDR_B_D7
DDR_B_D29
DDR_B_D26
DDR_B_D30
DDR_B_D28
DDR_B_D9
DDR_B_D8
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D11
DDR_B_D15
DDRB_CKE1_DIMMB
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
SB_CLK_DDR1
SB_CLK_DDR#1
DDR_B_BS1
DDR_B_RAS#
DDRB_CS0_DIMMB#
SB_ODT0
SB_ODT1
+VREF_CA
DDR_B_D37
DDR_B_D32
DDR_B_D39
DDR_B_D35
DDR_B_D45
DDR_B_D40
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D42
DDR_B_D46
DDR_B_D51
DDR_B_D55
DDR_B_D53
DDR_B_D48
DDR_B_D56
DDR_B_D57
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D61
DDR_B_D59
+0.675VS
Q4
Q5
SS3
SS6
Q6
Q7
SS8
Q12
M1
Q14
A15
A14
A11
A7
A6
A4
A2
A0
CK1
BA1
S0#
SCL
G2
Channel B
A
B_DIMM_VREFDQ<6>
S
159
159
C
C
0.022U_0402_25V7K
0.022U_0402_25V7K
1 1
R
R
24.9_0402_1%
24.9_0402_1%
179
179
1 2
1
@
@
2
12
@
@
R
R
297
297
2_0402_1%
2_0402_1%
1.35V
+
12
12
R
R
57
57
1.8K_0402_1%
1.8K_0402_1%
R
R
213
213
1.8K_0402_1%
1.8K_0402_1%
+
V_DDR_REFB
C128
C128
0.1U_0402_16V7K
0.1U_0402_16V7K
1
2
Note: Depend on Project
Layout Note:
Place near JDIMM1
+1.35V
C
C
C
C
1U_0402_6.3V6K
1U_0402_6.3V6K
129
129
1
1
@
@
2
2
2 2
+1.35V
C
C
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
133
133
1
1
2
2
+1.35V
C
C
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
137
137
1
1
2
2
3 3
<BOM Structure>
<BOM Structure>
<BOM Structure>
<BOM Structure>
+0.675VS
C
C
1U_0402_6.3V6K
1U_0402_6.3V6K
143
143
1
1
@
@
2
2
<BOM Structure>
<BOM Structure>
Layout Note:
Place near JDIMM1.203,204
4 4
1U_0402_6.3V6K
1U_0402_6.3V6K
130
130
C
C
134
134
1
2
C
C
138
138
1
@
@
2
C
C
1U_0402_6.3V6K
1U_0402_6.3V6K
144
144
C
C
1U_0402_6.3V6K
1U_0402_6.3V6K
131
131
1
@
@
2
C
C
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
135
135
1
2
C
C
10U_0603_6.3V6M
10U_0603_6.3V6M
139
139
C
C
1U_0402_6.3V6K
1U_0402_6.3V6K
145
145
1
@
@
2
<BOM Structure>
<BOM Structure>
C
C
1U_0402_6.3V6K
1U_0402_6.3V6K
132
132
1
2
C
C
136
136
C
C
1U_0402_6.3V6K
1U_0402_6.3V6K
146
146
1
2
All VREF traces should
have 10 mil trace width
DDRB_CKE0_DIMMB<6>
DDR_B_BS2<6>
SB_CLK_DDR0<6>
SB_CLK_DDR#0<6>
DDR_B_BS0<6>
DDR_B_WE#<6>
DDR_B_CAS#<6>
DDRB_CS1_DIMMB#<6>
+3VS
R229
R229
10K_0402_5%
10K_0402_5%
+3VS
+0.675VS
1 2
C147
C147
0.1U_0402_16V7K
0.1U_0402_16V7K
1
2
DDRB_CKE0_DIMMB
DDR_B_BS2
SB_CLK_DDR0
SB_CLK_DDR#0
DDRB_CS1_DIMMB#
@
@
1 2
C
D
IMM_DRAMRST# <16,5>
DDRB_CKE1_DIMMB <6>
SB_CLK_DDR1 <6>
SB_CLK_DDR#1 <6>
DDR_B_BS1 <6>
DDR_B_RAS# <6>
DDRB_CS0_DIMMB# <6>
SB_ODT0 <16>
SB_ODT1 <16>
0.1U_0402_16V7K
0.1U_0402_16V7K
1
2
Note: Depend on Project
PM_SMBDATA <16,31,33 ,8>
PM_SMBCLK <16,31 ,33,8>
C142
C142
DR_B_DQS#[0..7] <6>
D
DR_B_DQS[0..7] <6>
D
DR_B_D[0..63] <6>
D
DR_B_MA[0..15] <6>
D
DDR3 SO-DIMM B
everse Type
R
H=9.0mm
+VREF_CA <16>
D
E
<Address: SA1:SA0=10>
Note: Depend on Project
A
DIMM_2 STD H:4mm
B
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2012/07/10 2013/07/10
2012/07/10 2013/07/10
2012/07/10 2013/07/10
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDRIII DIMMB
DDRIII DIMMB
DDRIII DIMMB
ZRMAA/ZEMAA
ZRMAA/ZEMAA
ZRMAA/ZEMAA
of
17 55Friday, June 21, 2013
17 55Friday, June 21, 2013
E
17 55Friday, June 21, 2013
0.4
0.4
0.4
A
CIE_GTX_C_CRX_P[0..3]
CIE_GTX_C_CRX_P[0..3]<11>
P
P
CIE_GTX_C_CRX_N[0..3]<11>
CIE_CTX_C_GRX_P[0..3]<11>
P
PCIE_CTX_C_GRX_N[0..3]<11>
1 1
PCIE_GTX_C_CRX_P0
PCIE_GTX_C_CRX_N0
PCIE_GTX_C_CRX_P1
PCIE_GTX_C_CRX_N1
PCIE_GTX_C_CRX_P2
PCIE_GTX_C_CRX_N2
PCIE_GTX_C_CRX_P3
PCIE_GTX_C_CRX_N3
2 2
3 3
CLK_REQ_VGA#<8>
4 4
P
P
CIE_GTX_C_CRX_N[0..3]
P
CIE_CTX_C_GRX_P[0..3]
P
CIE_CTX_C_GRX_N[0..3]
1 2
CV1 0.22U_0402_16V7KOPT@CV1 0.22U_0402_16V7KOPT@
1 2
CV2 0.22U_0402_16V7KOPT@CV2 0.22U_0402_16V7KOPT@
1 2
CV3 0.22U_0402_16V7KOPT@CV3 0.22U_0402_16V7KOPT@
1 2
CV4 0.22U_0402_16V7KOPT@CV4 0.22U_0402_16V7KOPT@
1 2
CV5 0.22U_0402_16V7KOPT@CV5 0.22U_0402_16V7KOPT@
1 2
CV6 0.22U_0402_16V7KOPT@CV6 0.22U_0402_16V7KOPT@
1 2
CV7 0.22U_0402_16V7KOPT@CV7 0.22U_0402_16V7KOPT@
1 2
CV8 0.22U_0402_16V7KOPT@CV8 0.22U_0402_16V7KOPT@
CLK_PCIE_VGA<8 >
CLK_PCIE_VGA#<8>
PLTRST_VGA#<9>
61
QV2A
QV2A
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
OPT@
OPT@
2
1 2
@
@
RV4 200_0402_1%
RV4 200_0402_1%
+3VS_DGPU
CIE_CTX_C_GRX_P0
P
P
CIE_CTX_C_GRX_N0
CIE_CTX_C_GRX_P1
P
P
CIE_CTX_C_GRX_N1
CIE_CTX_C_GRX_P2
P
CIE_CTX_C_GRX_N2
P
P
CIE_CTX_C_GRX_P3
CIE_CTX_C_GRX_N3
P
PCIE_GTX_CRX_P0
PCIE_GTX_CRX_N0
PCIE_GTX_CRX_P1
PCIE_GTX_CRX_N1
PCIE_GTX_CRX_P2
PCIE_GTX_CRX_N2
PCIE_GTX_CRX_P3
PCIE_GTX_CRX_N3
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_REQ_GPU#
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT#
RV5
RV5
2.49K_0402_1%
2.49K_0402_1%
OPT@
OPT@
1 2
B
U
U
V1A
V1A
AG6
EX_RX0
P
AG7
P
EX_RX0_N
AF7
EX_RX1
P
AE7
P
EX_RX1_N
AE9
EX_RX2
P
AF9
P
EX_RX2_N
AG9
EX_RX3
P
AG10
P
EX_RX3_N
AF10
EX_RX4
P
AE10
PEX_RX4_N
AE12
EX_RX5
P
AF12
EX_RX5_N
P
AG12
P
EX_RX6
AG13
P
EX_RX6_N
AF13
EX_RX7
P
AE13
PEX_RX7_N
AE15
NC
AF15
NC
AG15
NC
AG16
NC
AF16
NC
AE16
NC
AE18
NC
AF18
NC
AG18
NC
AG19
NC
AF19
NC
AE19
NC
AE21
NC
AF21
NC
AG21
NC
AG22
NC
AC9
PEX_TX0
AB9
PEX_TX0_N
AB10
PEX_TX1
AC10
PEX_TX1_N
AD11
PEX_TX2
AC11
PEX_TX2_N
AC12
PEX_TX3
AB12
PEX_TX3_N
AB13
PEX_TX4
AC13
PEX_TX4_N
AD14
PEX_TX5
AC14
PEX_TX5_N
AC15
PEX_TX6
AB15
PEX_TX6_N
AB16
PEX_TX7
AC16
PEX_TX7_N
AD17
NC
AC17
NC
AC18
NC
AB18
NC
AB19
NC
AC19
NC
AD20
NC
AC20
NC
AC21
NC
AB21
NC
AD23
NC
AE23
NC
AF24
NC
AE24
NC
AG24
NC
AG25
NC
AE8
PEX_REFCLK
AD8
PEX_REFCLK_N
AC6
PEX_CLKREQ_N
AF22
PEX_TSTCLK_OUT
AE22
PEX_TSTCLK_OUT_N
AC7
PEX_RST_N
AF25
PEX_TERMP
N14P-GV2-S-A2_FCBGA595
N14P-GV2-S-A2_FCBGA595
N14PGV2@
N14PGV2@
1
CV17
CV17
18P_0402_50V8J
18P_0402_50V8J
NOGCLK@
NOGCLK@
2
P
P
1
art 1 of 6
art 1 of 6
PCI EXPRESS
PCI EXPRESS
YV1
YV1
1
DACs
DACs
120mA
I2C GPIO
I2C GPIO
52mA
71mA
41mA
CLK
CLK
NOGCLK@
NOGCLK@
27MHZ_16PF
27MHZ_16PF
GND
2
PIO0
G
G
PIO1
PIO2
G
G
PIO3
PIO4
G
G
PIO5
PIO6
G
G
PIO7
PIO8
G
GPIO9
PIO10
G
PIO11
G
G
PIO12
G
PIO13
PIO14
G
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
DACA_RED
DACA_GREEN
DACA_BLUE
DACA_HSYNC
DACA_VSYNC
DACA_VDD
DACA_VREF
DACA_RSET
I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA
I2CS_SCL
I2CS_SDA
CORE_PLLVDD
SP_PLLVDD
VID_PLLVDD
XTAL_IN
XTAL_OUT
XTAL_SSIN
XTAL_OUTBUFF
3
GND
4
18P_0402_50V8J
18P_0402_50V8J
NC
3
NOGCLK@
NOGCLK@
XTAL_OUTXTALIN
C6
B2
D6
C7
F9
A3
A4
B6
A6
F8
C5
E7
D7
B4
B3
C3
D5
D4
C2
F7
E6
C4
AB6
AG3
AF4
AF3
AE3
AE4
W5
AE2
AF2
B7
A7
C9
C8
A9
B9
D9
D8
L6
M6
N6
C11
B10
A10
C10
CV18
CV18
B_CLAMP_MON
F
F
B_CLAMP_REQ#
O
VERT#_VGA
G
PU_EVENT
D
GPU_VID
PS_DOWN#
G
P
SI
VGA_CRT_CLK
VGA_CRT_DATA
HDCP_SCL
HDCP_SDA
VGA_EDID_CLK
VGA_EDID_DATA
SMB_CLK_GPU
SMB_DATA_GPU
+PLLVDD
+GPU_PLLVDD
XTALIN
XTAL_OUT
XTAL_SSIN
XTAL_OUTBUFF
1
2
C
+
3VS_DGPU
G
G
2
V8
V8
Q
Q
N14PGV2@
N14PGV2@
13
D
D
S
S
2N7002KW_SOT323-3
2N7002KW_SOT323-3
GPU_VID <47>
D
PS_DOWN# <36>
G
P
SI <47>
1
1
CV9
CV9
CV10
2
RV7
CV113
CV113
CV10
2
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
OPT@
OPT@
12
@EMI@RV7
@EMI@
1
@EMI@
@EMI@
2
OPT@
OPT@
CV42, CV43 under GPU
close to ball : AE8,AD7
VGA_X1<31>
10_0402_5%
10_0402_5%
10P_0402_50V8J
10P_0402_50V8J
for EMI
D
D
V1
V1
12
RB751V40_SC76-2
RB751V40_SC76-2
OPT@
OPT@
LK_REQ_GC6# <36>
C
E
C GPS_DOWN# must be OD\Low
to avoid leakage
OPT@ LV1
OPT@
BLM18PG181SN1D_2P
BLM18PG181SN1D_2P
1
CV11
CV11
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
OPT@
OPT@
OPT@
OPT@
1 2
RV8 0_0402_5%
RV8 0_0402_5%
DGCLK@
DGCLK@
1 2
1
CV12
CV12
2
B_CLAMP <19,22,36>
F
LV1
22U_0603_6.3V6M
22U_0603_6.3V6M
XTALIN
+1.05VS_DGPU
OPT@
OPT@
F
or GC6
1
CV13
CV13
2
10U_0603_6.3V6M
10U_0603_6.3V6M
D
Internal Thermal Sensor
SMB_CLK_GPU
SMB_DATA_GPU
+PLLVDD
under GPU
close to AD8
JTAG_TRST<20>
TESTMODE<20>
+3VS_DGPU
5
4
2
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
OPT@
OPT@
QV1A
QV1A
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
61
1
CV14
2
OPT@ CV14
OPT@
0.1U_0402_10V7K
0.1U_0402_10V7K
G
PS_DOWN#
PU_EVENT
G
TAL_OUTBUFF
X
X
TAL_SSIN
C
LK_REQ_GPU#
B_CLAMP_REQ#
F
F
B_CLAMP_MON
VERT#_VGA
O
VGA_EDID_CLK
VGA_EDID_DATA
SMB_CLK_GPU
SMB_DATA_GPU
VGA_CRT_CLK
VGA_CRT_DATA
HDCP_SDA
HDCP_SCL
CLK_REQ_GC6#
FB_CLAMP
OPT@
OPT@
QV1B
QV1B
1
CV15
2
OPT@ CV15
OPT@
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
3
LV2
1 2
FBMA-L11-160808300LMA25T_2P
FBMA-L11-160808300LMA25T_2P
22U_0603_6.3V6M
22U_0603_6.3V6M
E
PV1
PV1
R
R
10K_8P4R_5%
10K_8P4R_5%
OPT@
OPT@
RPV12
RPV12
10K_8P4R_5%
10K_8P4R_5%
OPT@
OPT@
RPV2
RPV2
2.2K_8P4R_5%
2.2K_8P4R_5%
OPT@
OPT@
RPV3
RPV3
2.2K_8P4R_5%
2.2K_8P4R_5%
OPT@
OPT@
RPV13
RPV13
10K_8P4R_5%
10K_8P4R_5%
OPT@
OPT@
EC_SMB_CK2 <36,8>
EC_SMB_DA2 <36,8>
OPT@LV2
OPT@
3VS_DGPU
+
+1.05VS_DGPU
1
2
+3VS
CV16
OPT@
OPT@ CV16
10U_0603_6.3V6M
10U_0603_6.3V6M
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2012/09/28 2013/09/28
2012/09/28 2013/09/28
2012/09/28 2013/09/28
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
D
Date: Sheet
Compal Electronics, Inc.
VGA_N14x PEG & DAC
VGA_N14x PEG & DAC
VGA_N14x PEG & DAC
18 55Friday, June 21, 2013
18 55Friday, June 21, 2013
E
18 55Friday, June 21, 2013
0.4
0.4
0.4
of
of
A
V
RAM Interface
DA[15..0]
+FB_PLLAVDD
22U_0805_6.3V6M
22U_0805_6.3V6M
C
C
V20
V20
1
OPT@
OPT@
2
M
DA[31..16]
M
M
DA[47..32]
M
DA[63..48]
Close to H22
0.1U_0402_10V7K
0.1U_0402_10V7K
CV21
2
OPT@CV21
OPT@
1
CV22
OPT@CV22
OPT@
0.1U_0402_10V7K
0.1U_0402_10V7K
1
2
Close to P22
0.1U_0402_10V7K
0.1U_0402_10V7K
CV114
1
OPT@CV114
OPT@
2
U
U
V1B
V1B
art 2 of 6
art 2 of 6
P
M
DA0
M
DA1
MDA2
M
DA3
DA4
M
DA5
M
M
DA6
DA7
M
M
DA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
+FB_PLLAVDD
FB_CLAMP<18,22,36>
TV1 PAD@TV1 PAD
TV2 PAD@TV2 PAD
E18
F18
E16
F17
D20
D21
F20
E21
E15
D15
F15
F13
C13
B13
E13
D13
B15
C16
A13
A15
B18
A18
A19
C19
B24
C23
A25
A24
A21
B21
C20
C21
R22
R24
T22
R23
N25
N26
N23
N24
V23
V22
T23
U22
Y24
AA24
Y22
AA23
AD27
AB25
AD26
AC25
AA27
AA26
W26
Y25
R26
T25
N27
R27
V26
V27
W27
W25
F16
P22
D23
H22
F3
@
F22
J22
@
P
BA_D00
F
FBA_D01
F
BA_D02
F
BA_D03
BA_D04
F
F
BA_D05
BA_D06
F
BA_D07
F
FBA_D08
FBA_D09
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
62mA
FB_PLLAVDD_1
62mA
FB_PLLAVDD_2
FB_VREF_PROBE
35mA
FB_DLLAVDD
FB_CLAMP
FBA_DEBUG0
FBA_DEBUG1
N14P-GV2-S-A2_FCBGA595
N14P-GV2-S-A2_FCBGA595
N14PGV2@
N14PGV2@
INTERFACE A
INTERFACE A
MEMORY
MEMORY
BA_CMD0
F
FBA_CMD1
F
BA_CMD2
F
BA_CMD3
BA_CMD4
F
F
BA_CMD5
BA_CMD6
F
BA_CMD7
F
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N
FBA_WCK01
FBA_WCK01_N
FBA_WCK23
FBA_WCK23_N
FBA_WCK45
FBA_WCK45_N
FBA_WCK67
FBA_WCK67_N
C27
C
MDA0
C26
C
MDA1
E24
CMDA2
F24
C
MDA3
D27
MDA4
C
D26
MDA5
C
F25
C
MDA6
F26
MDA7
C
F23
C
MDA8
G22
CMDA9
G23
CMDA10
G24
CMDA11
F27
CMDA12
G25
CMDA13
G27
CMDA14
G26
CMDA15
M24
CMDA16
M23
CMDA17
K24
CMDA18
K23
CMDA19
M27
CMDA20
M26
CMDA21
M25
CMDA22
K26
CMDA23
K22
CMDA24
J23
CMDA25
J25
CMDA26
J24
CMDA27
K27
CMDA28
K25
CMDA29
J27
CMDA30
J26
D19
D14
C17
C22
P24
W24
AA25
U25
F19
C14
A16
A22
P25
W22
AB27
T27
E19
C15
B16
B22
R25
W23
AB26
T26
D24
D25
N22
M22
D18
C18
D17
D16
T24
U24
V24
V25
DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7
DQSA#0
DQSA#1
DQSA#2
DQSA#3
DQSA#4
DQSA#5
DQSA#6
DQSA#7
DQSA0
DQSA1
DQSA2
DQSA3
DQSA4
DQSA5
DQSA6
DQSA7
C
MDA[30..0] <23,24,25,26>
CLKA0 <23,25>
CLKA0# <23,25>
CLKA1 <24,26>
CLKA1# <24,26>
DQMA[3..0] <23,25>
DQMA[7..4] <24,26>
DQSA#[3..0] <23,25>
DQSA#[7..4] <24,26>
DQSA[3..0] <23,25>
DQSA[7..4] <24,26>
M
DA[15..0]<23,25>
DA[31..16]<23,25>
M
DA[47..32]<24,26>
M
M
DA[63..48]<24,26>
1 1
30ohms (ESR=0.01)
+1.05VS_DGPU
LV3
OPT@LV3
OPT@
1 2
FBMA-L11-160808300LMA25T_2P
FBMA-L11-160808300LMA25T_2P
Near GPU Close to F16
P
lace close to the first T poin t
placement request
VRAM_1.5VS
+
12
C
RV14 100_0402_5%
RV14 100_0402_5%
V67 100_0402_5%
V67 100_0402_5%
R
R
R
R
V69 100_0402_5%
V69 100_0402_5%
R
R
V73 100_0402_5%
V73 100_0402_5%
RV76 100_0402_5%
RV76 100_0402_5%
RV82 100_0402_5%
RV82 100_0402_5%
RV84 100_0402_5%
RV84 100_0402_5%
RV86 100_0402_5%
RV86 100_0402_5%
+VRAM_1.5VS
+VRAM_1.5VS
DDR3
CMDA16
CMDA19
CMDA3
CMDA0
CMDA20
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
RV88 100_0402_5%
RV88 100_0402_5%
OPT@
OPT@
RV90 100_0402_5%
RV90 100_0402_5%
OPT@
OPT@
RV92 100_0402_5%
RV92 100_0402_5%
OPT@
OPT@
RV93 100_0402_5%
RV93 100_0402_5%
OPT@
OPT@
RV96 100_0402_5%
RV96 100_0402_5%
OPT@
OPT@
RV98 100_0402_5%
RV98 100_0402_5%
OPT@
OPT@
RV100 100_0402_5%
RV100 100_0402_5%
OPT@
OPT@
RV102 100_0402_5%
RV102 100_0402_5%
OPT@
OPT@
RPV8
RPV8
100_0804_8P4R_5%
100_0804_8P4R_5%
OPT@
OPT@
RV10 100_0402_5%
RV10 100_0402_5%
OPT@
OPT@
RV12 100_0402_5%
RV12 100_0402_5%
OPT@
OPT@
MDA12
12
C
MDA14
12
MDA15
C
12
MDA7
C
12
CMDA11
12
CMDA4
12
CMDA5
12
CMDA6
12
12
12
12
12
12
12
12
18
CMDA26
27
CMDA25
36
CMDA27
45
CMDA28
12
12
Command Bit Default Pull-down
ODTx
CKEx
RST
CS* No Termination
1 2
RV36 10K_0402_5%OPT@RV36 10K_0402_5%OPT@
1 2
RV37 10K_0402_5%OPT@RV37 10K_0402_5%OPT@
1 2
RV38 10K_0402_5%OPT@RV38 10K_0402_5%OPT@
1 2
RV40 10K_0402_5%OPT@RV40 10K_0402_5%OPT@
1 2
RV15 10K_0402_5%OPT@RV15 10K_0402_5%OPT@
RV66 100_0402_5%
RV66 100_0402_5%
V68 100_0402_5%
V68 100_0402_5%
R
R
R
R
V70 100_0402_5%
V70 100_0402_5%
R
R
V75 100_0402_5%
V75 100_0402_5%
RV81 100_0402_5%
RV81 100_0402_5%
RV83 100_0402_5%
RV83 100_0402_5%
RV85 100_0402_5%
RV85 100_0402_5%
RV87 100_0402_5%
RV87 100_0402_5%
CMDA22
RV89 100_0402_5%
RV89 100_0402_5%
CMDA9
RV91 100_0402_5%
RV91 100_0402_5%
CMDA21
RV94 100_0402_5%
RV94 100_0402_5%
CMDA24
RV95 100_0402_5%
RV95 100_0402_5%
CMDA23
RV97 100_0402_5%
RV97 100_0402_5%
CMDA13
RV99 100_0402_5%
RV99 100_0402_5%
CMDA8
RV101 100_0402_5%
RV101 100_0402_5%
CMDA10
RV103 100_0402_5%
RV103 100_0402_5%
CMDA28
CMDA27
CMDA25
CMDA26
CMDA29
CMDA30
10k
10k
10k
12
12
OPT@
OPT@
12
OPT@
OPT@
12
OPT@
OPT@
12
OPT@
OPT@
12
OPT@
OPT@
12
OPT@
OPT@
12
OPT@
OPT@
OPT@
OPT@
12
12
OPT@
OPT@
12
OPT@
OPT@
12
OPT@
OPT@
12
OPT@
OPT@
12
OPT@
OPT@
12
OPT@
OPT@
12
OPT@
OPT@
OPT@
OPT@
RPV9
RPV9
1 8
2 7
3 6
4 5
100_0804_8P4R_5%
100_0804_8P4R_5%
OPT@
OPT@
RV11 100_0402_5%
RV11 100_0402_5%
OPT@
OPT@
RV13 100_0402_5%
RV13 100_0402_5%
OPT@
OPT@
12
12
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
2012/09/28 2013/09/28
2012/09/28 2013/09/28
2012/09/28 2013/09/28
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
A
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet
Date: Sheet
Title
Title
Title
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
N14x VRAM Interface
N14x VRAM Interface
N14x VRAM Interface
0.4
0.4
0.4
of
of
19 55Friday, June 21, 2013
19 55Friday, June 21, 2013
19 55Friday, June 21, 2013
5
U
U
V1C
V1C
AC3
FPA_TXC
I
AC4
I
FPA_TXC_N
Y4
FPA_TXD0
I
Y3
I
FPA_TXD0_N
AA3
FPA_TXD1
I
AA2
I
FPA_TXD1_N
AB1
FPA_TXD2
I
AA1
IFPA_TXD2_N
AA4
FPA_TXD3
D D
C C
B B
A A
I
AA5
FPA_TXD3_N
I
AB5
FPB_TXC
I
AB4
IFPB_TXC_N
AB3
IFPB_TXD4
AB2
IFPB_TXD4_N
AD3
IFPB_TXD5
AD2
IFPB_TXD5_N
AE1
IFPB_TXD6
AD1
IFPB_TXD6_N
AD4
IFPB_TXD7
AD5
IFPB_TXD7_N
T2
IFPC_L0
T3
IFPC_L0_N
T1
IFPC_L1
R1
IFPC_L1_N
R2
IFPC_L2
R3
IFPC_L2_N
N2
IFPC_L3
N3
IFPC_L3_N
V3
IFPD_L0
V4
IFPD_L0_N
U3
IFPD_L1
U4
IFPD_L1_N
T4
IFPD_L2
T5
IFPD_L2_N
R4
IFPD_L3
R5
IFPD_L3_N
N1
NC
M1
NC
M2
NC
M3
NC
K2
NC
K3
NC
K1
NC
J1
NC
M4
NC
M5
NC
L3
NC
L4
NC
K4
NC
K5
NC
J4
NC
J5
NC
N4
IFPC_AUX_I2CW_SCL
N5
IFPC_AUX_I2CW_SDA_N
P3
IFPD_AUX_I2CX_SCL
P4
IFPD_AUX_I2CX_SDA_N
J2
IFPE_AUX_I2CY_SCL
J3
IFPE_AUX_I2CY_SDA_N
H3
IFPF_AUX_I2CZ_SCL
H4
IFPF_AUX_I2CZ_SDA_N
N14P-GV2-S-A2_FCBGA595
N14P-GV2-S-A2_FCBGA595
N14PGV2@
N14PGV2@
P
P
art 3 of 6
art 3 of 6
NC
NC
GENERAL
GENERAL
MULTI_STRAP_REF0_GND
LVDS/TMDS
LVDS/TMDS
VDD_SENSE
GND_SENSE
TEST
TEST
JTAG_TRST_N
SERIAL
SERIAL
BUFRST_N
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
THERMDP
THERMDN
TESTMODE
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
ROM_CS_N
ROM_SI
ROM_SO
ROM_SCLK
F11
N
C
AD10
C
N
AD7
N
C
B19
C
N
V5
N
C
V6
C
N
G1
N
C
G2
C
N
G3
NC
G4
C
N
G5
C
N
G6
N
C
G7
N
C
V1
C
N
V2
NC
W1
NC
W2
NC
W3
NC
W4
NC
D11
D10
NC
E9
NC
E10
NC
F10
NC
D1
D2
E4
E3
D3
C1
NC
F6
F4
NC
F5
NC
F12
E12
F2
F1
AD9
AE5
AE6
AF6
AD6
AG4
D12
B12
A12
C12
4
OPT@
OPT@
1 2
RV16 10K_0402_5%
RV16 10K_0402_5%
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
MULTI_STRAP_REF0_GND
VGA_VCC_SENSE
trace width: 16mils
differential voltage sensing.
VGA_VSS_SENSE
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
ROM_SI
ROM_SO
ROM_SCLK
differential signal routing.
PAD
PAD
PAD
PAD
PAD @
PAD @
PAD
PAD
N14PGV2@
N14PGV2@
1 2
RV17 40.2K_0402_1%
RV17 40.2K_0402_1%
+VGA_CORE
RV26
RV26
100_0402_1%
100_0402_1%
OPT@
OPT@
1 2
OPT@
OPT@
12
RV35
RV35
100_0402_1%
100_0402_1%
TESTMODE <18>
@
@
TV3
TV3
@
@
TV4
TV4
TV5
TV5
TV6
@TV6
@
JTAG_TRST <18>
VGA_VCC_SENSE <47>
VGA_VSS_SENSE <47>
3
Physical
Strapping pin
OM_SO
R
OM_SCLK
R
ROM_SI
TRAP0
S
S
TRAP1
S
TRAP2
STRAP3
STRAP4
SKU
Power Rail
+3VS_DGPU
+3VS_DGPU
+3VS_DGPU
+3VS_DGPU
+
+
+3VS_DGPU SOR0_EXPOSEDSOR2_EXPOSED SOR1_EXPOSED
+3VS_DGPU DP_PLL_VDD33V
Device ID biit5 to bit0
N14P-GV2
N14M-GL
MULTI LEVEL STRAPS
12
N14PGV2@
N14PGV2@
RV18
RV18
45.3K_0402_1%
STRAP0
STRAP1 STRAP3
STRAP2
45.3K_0402_1%
12
@
@
RV27
RV27
4.99K_0402_1%
4.99K_0402_1%
+3VS_DGPU
12
@
@
10K_0402_1%
10K_0402_1%
RV19
RV19
12
N14PGV2@
N14PGV2@
RV28
RV28
45.3K_0402_1%
45.3K_0402_1%
0x1140 000000
12
@
@
10K_0402_1%
10K_0402_1%
RV20
RV20
12
N14PGV2@
N14PGV2@
N14PGV2@
N14PGV2@
RV29
RV29
15K_0402_1%
15K_0402_1%
For X76 (N14M-GL)
FB Memory gDDR3
900MHz
1
2
8
M
x
1
6
Samsung
Micron
K4W2G1646E-BC11
K4W2G1646E-BC1A
1GHz
MT41K128M16JT-107G:K
900MHz
N14P-GV2
K4W4G1646B-HC11Samsung
2
5
6
M
x
1
6
Micron
900MHz
MT41K256M16HA-107G:E
900MHz 0100
2
ogical
L
Strapping Bit3
B[1]
F
CI_DEVID[4]
P
Logical
Strapping Bit2
FB[0]
SUB_VENDOR
USER[3]
3VS_DGPU 3GIO_PADCFG[0]3GIO_PADCFG[1]3GIO_PADCFG[2]
3VS_DGPU
GIO_PADCFG[3]
3
P
CI_DEVID[3]
SOR3_EXPOSED
RESERVED
PCIE_SPEED_CHANGE_GEN3
Resistor Values
010010TBD
12
12
@
@
@
@
10K_0402_1%
10K_0402_1%
RV22
RV22
RV21
RV21
4.99K_0402_1%
4.99K_0402_1%
STRAP4
12
12
N14PGV2@
N14PGV2@
RV30
RV30
RV31
RV31
4.99K_0402_1%
4.99K_0402_1%
45.3K_0402_1%
45.3K_0402_1%
For X76 (N14P-GV2)
ROM_SIGPU
PD 45K
PD 30K
1
2
8
M
x
1
6
Samsung
Hynix
Micron
N14M-GL
PD 20K
PD 10K
Samsung K4W4G1646B-HC11
2
5
6
M
Hynix
x
1
6
Micron
Logical
Strapping Bit1
SMB_ALT_ADDR
P
CI_DEVID[5]
AMCFG[1]RAMCFG[3] RAMCFG[2]
R
PCIE_MAX_SPEED
5K
10K
15K
20K
25K
30K
35K
45K
ROM_SI
ROM_SO
ROM_SCLK
FB Memory gDDR3
1GHz
1GHz
900MHz
900MHz
900MHz
900MHz
1
ogical
L
Strapping Bit0
GA_DEVICE
V
PEX_PLLEN_TERM
RAMCFG[0]
SER[0]USER[1]USER[2]
U
PCI_DEVID[0]PCI_DEVID[1]PCI_DEVID[2]
Pull-up to +3VS
_DGPU
1000
1001
1010
1011
1100
1101
1110
1111
12
12
@
@
N14PGV2@
N14PGV2@
RV24
RV24
RV23
RV23
12
@
@
RV32
RV32
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
10K_0402_1%
10K_0402_1%
K4W2G1646E-BC11900MHz
K4W2G1646E-BC1A
H5TQ2G63DFR-11C900MHz
H5TQ2G63DFR-N0C
MT41K128M16JT-107G
H5TC4G63AFR-11C
MT41K256M16HA-107G
Pull-down to Gnd
0000
0001
0010
0011
0100
0101
0110
0111
+3VS_DGPU
12
N14PGV2@
N14PGV2@
RV25
RV25
4.99K_0402_1%
4.99K_0402_1%
STRAP[3:0]GPU
0101
0110
0001
1011
1101
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2012/09/28 2013/09/28
2012/09/28 2013/09/28
2012/09/28 2013/09/28
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
2
Date: Sheet
Compal Electronics, Inc.
VGA_N14x LVDS&TMDS
VGA_N14x LVDS&TMDS
VGA_N14x LVDS&TMDS
20 55Friday, June 21, 2013
20 55Friday, June 21, 2013
1
20 55Friday, June 21, 2013
0.4
0.4
0.4
of
of
5
4
3
2
1
nder GPU
U
VRAM_1.5VS
+
D D
1
1
V116
V116
CV117
C
C
2
2
OPT@
OPT@ CV117
OPT@
OPT@
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
For ME request replace CV32
C C
B B
CV24
Under GPU
1
CV32
2
ME@
ME@ CV32
1
1
CV24
2
ME@
ME@ CV24
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
CV33
2
2
OPT@
OPT@ CV33
1U_0402_6.3V6K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
1
CV35
CV25
CV34
2
2
OPT@
OPT@ CV35
OPT@
OPT@ CV25
OPT@
OPT@ CV34
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
Near GPU
1
1
CV44
CV43
2
2
OPT@
OPT@ CV44
OPT@
OPT@ CV43
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
V1D
V1D
U
U
B26
C25
E23
E26
F14
F21
G13
G14
G15
G16
G18
G19
G20
G21
H24
H26
J21
K21
L22
L24
L26
M21
N21
R21
T21
V21
W21
V7
W7
AA6
W6
Y6
M7
N7
T6
P6
T7
R7
U6
R6
J7
K7
K6
H6
J6
N14P-GV2-S-A2_FCBGA595
N14P-GV2-S-A2_FCBGA595
N14PGV2@
N14PGV2@
Part 4 of 6
Part 4 of 6
3500 mA 2000 mA
BVDDQ_01
F
BVDDQ_02
F
F
BVDDQ_03
F
BVDDQ_04
BVDDQ_05
F
FBVDDQ_06
FBVDDQ_07
FBVDDQ_08
FBVDDQ_09
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
IFPAB_PLLVDD_1
IFPAB_PLLVDD_2
IFPAB_RSET
IFPA_IOVDD
IFPB_IOVDD
IFPC_PLLVDD_1
IFPC_PLLVDD_2
IFPC_RSET
IFPC_IOVDD
IFPD_PLLVDD_2
IFPD_PLLVDD_1
IFPD_RSET
IFPD_IOVDD
NC
NC
NC
NC
NC
EX_IOVDDQ_1
P
EX_IOVDDQ_2
P
P
EX_IOVDDQ_3
P
EX_IOVDDQ_4
EX_IOVDDQ_5
P
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
PEX_IOVDD_6
VDD33_1
VDD33_2
VDD33_3
VDD33_4
POWER
POWER
FB_CAL_PD_VDDQ
FB_CAL_PU_GND
FB_CAL_TERM_GND
PEX_PLL_HVDD_1
PEX_PLL_HVDD_2
PEX_SVDD_3V3
120mA
PEX_PLLVDD_1
PEX_PLLVDD_2
AA10
AA12
AA13
AA16
AA18
AA19
AA20
AA21
AB22
AC23
AD24
AE25
AF26
AF27
AA22
AB23
AC24
AD25
AE26
AE27
G10
G12
G8
G9
D22
+FB_CAL_PD_VDDQ
C24
FB_CAL_PU_GND
B25
FB_CAL_TERM_GND
AA8
AA9
AB8
AA14
AA15
+PEX_PLLVDD
Near Ball
Under GPU
1
CV54
2
OPT@ CV54
OPT@
0.1U_0402_10V7K
0.1U_0402_10V7K
1 2
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
Near GPU
1
CV55
2
OPT@ CV55
OPT@
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
1
2
N
1
CV26
CV26
CV23
2
OPT@
OPT@
OPT@
OPT@ CV23
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CV36
CV36
CV37
2
OPT@
OPT@
OPT@ CV37
OPT@
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
+VRAM_1.5VS
RV3940.2_0402_1%
RV3940.2_0402_1%
12
RV4142.2_0402_1%
RV4142.2_0402_1%
12
RV4251.1_0402_1%
RV4251.1_0402_1%
1
1
CV56
2
2
ME@ CV56
ME@
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
ear GPU
1
CV27
2
ME@
ME@ CV27
1
CV38
2
OPT@ CV38
OPT@
Under GPU
1
CV45
2
OPT@
OPT@ CV45
CV115
OPT@ CV115
OPT@
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
BLM18PG181SN1D_2P
BLM18PG181SN1D_2P
midway between GPU
and Power suppl y
1
1
2
1
2
CV29
CV28
CV28
2
ME@
ME@
OPT@
OPT@ CV29
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CV40
CV39
CV39
2
OPT@ CV40
OPT@
OPT@
OPT@
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
Near GPU
1
1
2
0_0603_5%
0_0603_5%
N14PGV2@
N14PGV2@
1 2
CV47
CV46
CV46
2
OPT@
OPT@ CV47
OPT@
OPT@
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
+1.05VS_DGPU
RV1
RV1
12
LV4
@LV4
@
+
1.05VS_DGPU
1
1
CV31
CV30
2
2
OPT@
OPT@ CV31
OPT@
OPT@ CV30
22U_0805_6.3V6M
22U_0805_6.3V6M
+1.05VS_DGPU
1
1
CV42
CV41
2
2
OPT@ CV42
OPT@
OPT@ CV41
OPT@
22U_0805_6.3V6M
22U_0805_6.3V6M
+3VS_DGPU
1
1
CV48
CV49
2
2
OPT@
OPT@ CV48
OPT@
OPT@ CV49
1U_0402_6.3V6K
1U_0402_6.3V6K
Under GPU
Close to AH12/A G12
1
CV119
2
OPT@
22U_0805_6.3V6M
22U_0805_6.3V6M
OPT@ CV119
For ME request replace CV28
1
CV121
2
OPT@ CV121
22U_0805_6.3V6M
22U_0805_6.3V6M
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
OPT@
10U_0603_6.3V6M
10U_0603_6.3V6M
For ME request replace CV40
Near GPU
1
1
CV50
2
OPT@
OPT@ CV50
0.1U_0402_10V7K
0.1U_0402_10V7K
1
CV51
CV52
2
2
OPT@
OPT@
OPT@ CV51
OPT@ CV52
0.1U_0402_10V7K
0.1U_0402_10V7K
1
CV118
2
OPT@
OPT@ CV118
10U_0603_6.3V6M
10U_0603_6.3V6M
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
+3VS_DGPU
1
CV53
CV53
2
OPT@
OPT@
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
CV27 CV29
For ME request replace CV56
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2012/09/28 2013/09/28
2012/09/28 2013/09/28
2012/09/28 2013/09/28
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
VGA_N14x POWER
VGA_N14x POWER
VGA_N14x POWER
1
0.4
0.4
0.4
of
21 55Friday, June 21, 2013
of
21 55Friday, June 21, 2013
of
21 55Friday, June 21, 2013
5
V1E
V1E
U
U
A2
G
A26
G
AB11
G
AB14
G
AB17
G
AB20
GND_006
AB24
D D
C C
B B
G
AC2
G
AC22
G
AC26
G
AC5
G
AC8
GND_012
AD12
GND_013
AD13
GND_014
AD15
GND_015
AD16
GND_016
AD18
GND_017
AD19
GND_018
AD21
GND_019
AD22
GND_020
AE11
GND_021
AE14
GND_022
AE17
GND_023
AE20
GND_024
AF1
GND_025
AF11
GND_026
AF14
GND_027
AF17
GND_028
AF20
GND_029
AF23
GND_030
AF5
GND_031
AF8
GND_032
AG2
GND_033
AG26
GND_034
B1
GND_035
B11
GND_036
B14
GND_037
B17
GND_038
B20
GND_039
B23
GND_040
B27
GND_041
B5
GND_042
B8
GND_043
E11
GND_044
E14
GND_045
E17
GND_046
E2
GND_047
E20
GND_048
E22
GND_049
E25
GND_050
E5
GND_051
E8
GND_052
H2
GND_053
H23
GND_054
H25
GND_055
H5
GND_056
N14P-GV2-S-A2_FCBGA595
N14P-GV2-S-A2_FCBGA595
N14PGV2@
N14PGV2@
ND_001
ND_002
ND_003
ND_004
ND_005
ND_007
ND_008
ND_009
ND_010
ND_011
art 5 of 6
art 5 of 6
P
P
GND
GND
ND_057
G
G
ND_058
ND_059
G
G
ND_060
ND_061
G
GND_062
ND_063
G
ND_064
G
G
ND_065
G
ND_066
ND_067
G
GND_068
GND_069
GND_070
GND_071
GND_072
GND_073
GND_074
GND_075
GND_076
GND_077
GND_078
GND_079
GND_080
GND_081
GND_082
GND_083
GND_084
GND_085
GND_086
GND_087
GND_088
GND_089
GND_090
GND_091
GND_092
GND_093
GND_094
GND_095
GND_096
GND_097
GND_098
GND_099
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND
GND
K11
K13
K15
K17
L10
L12
L14
L16
L18
L2
L23
L25
L5
M11
M13
M15
M17
N10
N12
N14
N16
N18
P11
P13
P15
P17
P2
P23
P26
P5
R10
R12
R14
R16
R18
T11
T13
T15
T17
U10
U12
U14
U16
U18
U2
U23
U26
U5
V11
V13
V15
V17
Y2
Y23
Y26
Y5
AA7
AB7
4
VGA_CORE
+
For GC6
VGA_PWROK<47,9>
UV1F
UV1F
K10
DD_001
V
K12
V
DD_002
K14
DD_003
V
K16
VDD_004
K18
DD_005
V
L11
DD_006
V
L13
V
DD_007
L15
V
DD_008
L17
DD_009
V
M10
VDD_010
M12
VDD_011
M14
VDD_012
M16
VDD_013
M18
VDD_014
N11
VDD_015
N13
VDD_016
N15
VDD_017
N17
VDD_018
P10
VDD_019
P12
VDD_020
N14P-GV2-S-A2_FCBGA595
N14P-GV2-S-A2_FCBGA595
N14PGV2@
N14PGV2@
FB_CLAMP<18,19,36>
art 6 of 6
art 6 of 6
P
P
POWER
POWER
0.1U_0402_10V7K
0.1U_0402_10V7K
DD_041
V
V
DD_040
DD_039
V
VDD_038
DD_037
V
DD_036
V
V
DD_035
V
DD_034
DD_033
V
VDD_032
VDD_031
VDD_030
VDD_029
VDD_028
VDD_027
VDD_026
VDD_025
VDD_024
VDD_023
VDD_022
VDD_021
@
@
CV58
CV58
V18
V16
V14
V12
V10
U17
U15
U13
U11
T18
T16
T14
T12
T10
R17
R15
R13
R11
P18
P16
P14
+3VS
1
2
5
2
B
1
A
3
3
VGA_CORE
+
UV2
UV2
N14PGV2@
N14PGV2@
4
Vcc
Y
G
NC7SZ32P5X_SC70-5
NC7SZ32P5X_SC70-5
1.5V_PWR_EN
2
1.05VS_VTT to +1.05VS_DGPU
+
+
5VALW
12
RV43
RV43
270K_0402_5%
270K_0402_5%
OPT@
OPT@
61
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
0.01U_0402_25V7K
0.01U_0402_25V7K
VGA_PWROK
OPT@
OPT@
QV4A
QV4A
AO3416_SOT23-3
AO3416_SOT23-3
+1.05VS_DGPU
+
1.05VS_VTT
gs=4.5V,Id=6.5A ,Rds<22mohm
V
V3
OPT@
V3
OPT@
Q
Q
13
D
D
2
G
G
S
S
CV57
CV57
OPT@
OPT@
1
2
+1.5VALW to +VRAM_1.5VS
CV59
CV59
OPT@
OPT@
+1.5VALW
1
2
QV6
OPT@QV6
OPT@
8
S
D
7
S
D
6
S
D
5
G
D
FDS6676AS_SO8
FDS6676AS_SO8
CV60
CV60
OPT@
OPT@
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
+VRAM_1.5VS
Vgs=10V,Id=14.5 A,Rds=6mohm
1
2
3
4
VRAM_1.5VS_GATE
12
1
2
OPT@
OPT@
0.01U_0402_25V7K
0.01U_0402_25V7K
RV48
RV48
820K_0402_5%
820K_0402_5%
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
1.5V_PWR_EN
1 2
180K_0402_5%
180K_0402_5%
61
QV7A
QV7A
OPT@
OPT@
5
OPT@
OPT@
OPT@
OPT@
RV47
RV47
2
1.5V_PWR_EN#
QV5B
QV5B
G
G
2
VGA_PWROK#
61
D
D
QV5A
QV5A
2
G
G
S
S
OPT@
OPT@
B+
5
1 2
34
D
D
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
S
S
+
1.05VS_DGPU
1 2
3
5
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
4
1 2
RV45100K_0402_5%
RV45100K_0402_5%
OPT@
OPT@
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
RV46
RV46
470_0805_5%
470_0805_5%
OPT@
OPT@
1 2
3
QV7B
QV7B
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
OPT@
OPT@
4
+5VALW
RV49100K_0402_5%
RV49100K_0402_5%
OPT@
OPT@
1
V44
V44
R
R
22_0805_5%OPT@
22_0805_5%OPT@
OPT@
OPT@
QV4B
QV4B
+5VALW
+3VS to +3VS_DGPU
+VGA_CORE
RV52
RV51
RV51
470_0805_5%
470_0805_5%
OPT@
OPT@
1 2
3
QV9B
QV9B
5
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
A A
5
4
OPT@
OPT@
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
DGPU_PWR_EN#
4
3
RV52
470_0805_5%
470_0805_5%
OPT@
OPT@
1 2
3
QV2B
QV2B
5
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
OPT@
OPT@
4
Compal Secret Data
Compal Secret Data
2012/09/28 2013/09/28
2012/09/28 2013/09/28
2012/09/28 2013/09/28
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
DGPU_PWR_EN<10,9>
2
DGPU_PWR_EN#
+3VS+3VS_DGPU
RV53
RV53
10K_0402_5%OPT@
10K_0402_5%OPT@
1 2
RV54
RV54
1 2
4.7K_0402_5%
4.7K_0402_5%
OPT@
OPT@
61
QV9A
QV9A
2
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
OPT@
OPT@
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
2
CV61
CV61
0.1U_0402_10V7K
0.1U_0402_10V7K
OPT@
OPT@
1
AO3413_SOT23
AO3413_SOT23
2
CV62
CV62
OPT@
OPT@
0.01U_0402_25V7K
0.01U_0402_25V7K
1
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
VGA_N14x POWER & GND
VGA_N14x POWER & GND
VGA_N14x POWER & GND
+3VS
Vgs=-4.5V,Id=3A ,Rds<97mohm
S
S
QV11
QV11
G
G
2
OPT@
OPT@
D
D
1 3
+3VS_DGPU
22 55Friday, June 21, 2013
22 55Friday, June 21, 2013
1
22 55Friday, June 21, 2013
0.4
0.4
0.4
of
of
of
+
MEM_VREF_CA0
+MEM_VREF_DQ0
CMDA7
CMDA10
CMDA24
CMDA6
CMDA22
CMDA26
CMDA5
CMDA21
CMDA8
CMDA4
CMDA25
CMDA23
CMDA9
CMDA12
CMDA14
CMDA29
CMDA13
CMDA27
CLKA0
CLKA0#
CMDA3
CMDA0
CMDA2
CMDA11
CMDA15
CMDA28
DQSA1
DQSA2
DQMA1
DQMA2
DQSA#1
DQSA#2
CMDA20
12
OPT@
OPT@
RV60
RV60
4
M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M2
N8
M3
J7
K7
K9
K1
L2
J3
K3
L3
F3
C7
E7
D3
G3
B7
T2
L8
J1
L1
J9
L9
U
U
V3
@
V3
@
VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
BA0
BA1
BA2
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU
RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
K4B1G1646E-HC12_FBGA96
K4B1G1646E-HC12_FBGA96
310mA
96-BALL
96-BALL
SDRAM DDR3
SDRAM DDR3
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
M
DA9
MDA12
MDA8
MDA15
MDA13
MDA11
MDA10
MDA14
MDA18
MDA22
MDA16
MDA23
MDA17
MDA20
MDA19
MDA21
+VRAM_1.5VS
+VRAM_1.5VS
5
R
ANK 0 [31...0]
V
RAM DDR3 Chips
D
D D
1K_0402_1%
1K_0402_1%
1K_0402_1%
1K_0402_1%
C C
1K_0402_1%
1K_0402_1%
1K_0402_1%
1K_0402_1%
B B
D
CMDA[30..0]<19,24,25,26>
+VRAM_1.5VS
RV55
RV55
OPT@
OPT@
RV56
RV56
OPT@
OPT@
+VRAM_1.5VS
RV57
RV57
OPT@
OPT@
RV58
RV58
OPT@
OPT@
DQSA[3..0]<19,25>
QSA#[3..0]<19,25>
D
QMA[3..0]<19,25>
MDA[31..0]<19,25>
12
+MEM_VREF_CA0
12
12
+MEM_VREF_DQ0
12
D
D
QMA[3..0]
M
CMDA[30..0]
1
CV63
CV63
0.01U_0402_25V7K
0.01U_0402_25V7K
OPT@
OPT@
2
1
CV64
CV64
0.01U_0402_25V7K
0.01U_0402_25V7K
OPT@
OPT@
2
QSA[3..0]
QSA#[3..0]
DA[31..0]
+MEM_VREF_CA0
+MEM_VREF_DQ0
243_0402_1%
243_0402_1%
Group1
Group2
3
OPT@
OPT@
RV61
RV61
243_0402_1%
243_0402_1%
+
MEM_VREF_CA0
+MEM_VREF_DQ0
CMDA7
CMDA10
CMDA24
CMDA6
CMDA22
CMDA26
CMDA5
CMDA21
CMDA8
CMDA4
CMDA25
CMDA23
CMDA9
CMDA12
CMDA14
CMDA29
CMDA13
CMDA27
CLKA0
CLKA0#
CMDA3
CMDA0
CMDA2
CMDA11
CMDA15
CMDA28
DQSA0
DQSA3
DQMA0
DQMA3
DQSA#0
DQSA#3
CMDA20
ZQ1ZQ0
12
U
U
V4
@
V4
M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M2
N8
M3
J7
K7
K9
K1
L2
J3
K3
L3
F3
C7
E7
D3
G3
B7
T2
L8
J1
L1
J9
L9
@
VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
BA0
BA1
BA2
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
310mA
DQSL
DQSU
DML
DMU
DQSL
DQSU
RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
96-BALL
96-BALL
SDRAM DDR3
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
K4B1G1646E-HC12_FBGA96
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
M
DA6
MDA1
MDA5
MDA0
MDA4
MDA2
MDA7
MDA3
MDA30
MDA26
MDA29
MDA24
MDA28
MDA27
MDA31
MDA25
+VRAM_1.5VS
+VRAM_1.5VS
2
M
ode E
Address
CMD0
Rank 0 Rank 1
0..31
ODT
CMD1
CS0#
CKE
A9
A6
A3
A0
A8
A12
A1
RAS#
A13
BA1
A14
CAS#
Group0
Group3
CMD2
CMD3
CMD4
CMD5
CMD6
CMD7
CMD8
CMD9
CMD10
CMD11
CMD12
CMD13
CMD14
CMD15
CMD16
CMD17
CMD18
CMD19
CMD20
CMD21 A7
CMD22
CMD23
CMD24
CMD25
CMD26
CMD27
CMD28
CMD29
RST
A7
A4
A11
A2
A10
A5
BA2
WE#
BA0
CMD30
1
0..31 32..63
2..63
3
ODT
CS1#
CKE
A11
A6
A3
A0
A8
A12 A0
A1
A7 A7
BA1 BA1
A12 A12
A8 A8
A0
A2 A2
RAS# RAS# RAS#
A13
A14
A3
A14
CAS#
A13 A13
CAS# CAS#
ODT
CS0#
CKE
RST RST RST
A6
A4
A11
A2
A10
A5
A5 A5
A9 A9
A1 A1
WE# WE#
A4 A4
BA2
WE#
BA0
A10 A10
BA0 BA0
BA2
A11A9
A14
A3BA1
ODT
CS1#
CKE
A6
BA2
Place close to the first T poi nt
CLKA0<19,25>
CLKA0#<19,25>
12
OPT@
OPT@
RV63
RV63
160_0402_1%
160_0402_1%
Place close to RANK0 VRAM
+VRAM_1.5VS +VRAM_1.5VS
1
1
1
2
A A
5
1
CV68
CV67
2
2
OPT@
OPT@ CV68
OPT@
OPT@ CV67
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
4
1
1
CV69
CV70
2
2
OPT@
OPT@ CV69
OPT@
OPT@ CV70
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
CV71
2
OPT@
OPT@ CV71
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CV73
CV72
2
2
OPT@
OPT@ CV73
OPT@
OPT@ CV72
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1
CV75
CV74
OPT@
OPT@ CV74
0.1U_0402_10V7K
0.1U_0402_10V7K
CV76
2
2
OPT@
OPT@ CV75
OPT@
OPT@ CV76
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
1
2
2012/09/28 2013/09/28
2012/09/28 2013/09/28
2012/09/28 2013/09/28
1
CV77
CV78
CV78
2
OPT@
OPT@ CV77
OPT@
OPT@
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
Compal Secret Data
Compal Secret Data
Compal Secret Data
1
2
1
CV79
CV80
2
OPT@
OPT@ CV79
OPT@
OPT@ CV80
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
Deciphered Date
Deciphered Date
Deciphered Date
1
2
1
1
CV81
CV82
CV82
2
2
OPT@
OPT@ CV81
OPT@
OPT@
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
2
1
1
CV83
2
OPT@
OPT@ CV83
0.1U_0402_10V7K
0.1U_0402_10V7K
1
CV85
CV84
2
2
OPT@
OPT@ CV85
OPT@
OPT@ CV84
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
+VRAM_1.5VS
Custom
Custom
Custom
1
CV87
2
OPT@
OPT@ CV87
22U_0805_6.3V6M
22U_0805_6.3V6M
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
VGA_N14x VRAM RANK 0L
VGA_N14x VRAM RANK 0L
VGA_N14x VRAM RANK 0L
of
23 55Friday, June 21, 2013
of
23 55Friday, June 21, 2013
1
23 55Friday, June 21, 2013
CV86
OPT@
OPT@ CV86
0.1U_0402_10V7K
0.1U_0402_10V7K
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
Date: Sheet
0.4
0.4
0.4
MEM_VREF_CA1
MEM_VREF_DQ1
CMDA7
CMDA10
CMDA24
CMDA6
CMDA22
CMDA26
CMDA5
CMDA21
CMDA8
CMDA4
CMDA25
CMDA23
CMDA9
CMDA12
CMDA14
CMDA29
CMDA13
CMDA27
CLKA1
CLKA1#
CMDA19
CMDA16
CMDA18
CMDA11
CMDA15
CMDA28
DQSA4
DQSA7
DQMA4
DQMA7
DQSA#4
DQSA#7
CMDA20
ZQ2
12
OPT@
OPT@
RV71
RV71
4
V5
V5
U
U
M8
REFCA
V
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12
T3
A13
T7
A14
M7
A15/BA3
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE/CKE0
K1
ODT/ODT0
L2
CS/CS0
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
NC/ODT1
L1
NC/CS1
J9
NC/CE1
L9
NCZQ1
96-BALL
96-BALL
SDRAM DDR3
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
K4B1G1646E-HC12_FBGA96
@
@
310mA 310mA
D
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
QL0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
DA35
M
M
DA37
MDA32
MDA36
MDA33
MDA38
MDA34
MDA39
MDA58
MDA62
MDA56
MDA63
MDA57
MDA61
MDA59
MDA60
+VRAM_1.5VS
+VRAM_1.5VS
5
R
ANK 0 [63...32]
V
RAM DDR3 Chips
D
QSA[7..4]<19,26>
D
QSA#[7..4]<19,26>
+VRAM_1.5VS
RV59
RV59
OPT@
OPT@
RV62
RV62
OPT@
OPT@
+VRAM_1.5VS
RV64
RV64
OPT@
OPT@
RV65
RV65
OPT@
OPT@
D
QMA[7..4]<19,26>
D
DA[63..32]<19,26>
M
CMDA[30..0]<19,23,25,26>
12
+MEM_VREF_CA1
12
12
+MEM_VREF_DQ1
12
1
CV65
CV65
0.01U_0402_25V7K
0.01U_0402_25V7K
OPT@
OPT@
2
1
CV66
CV66
0.01U_0402_25V7K
0.01U_0402_25V7K
OPT@
OPT@
2
D D
1K_0402_1%
1K_0402_1%
1K_0402_1%
1K_0402_1%
C C
1K_0402_1%
1K_0402_1%
1K_0402_1%
1K_0402_1%
B B
QSA[7..4]
DQSA#[7..4]
QMA[7..4]
D
DA[63..32]
M
CMDA[30..0]
+MEM_VREF_CA1
+MEM_VREF_DQ1
+
+
243_0402_1%
243_0402_1%
Group4
3
MEM_VREF_CA1
+
+
MEM_VREF_DQ1
OPT@
OPT@
RV72
RV72
243_0402_1%
243_0402_1%
CMDA7
CMDA10
CMDA24
CMDA6
CMDA22
CMDA26
CMDA5
CMDA21
CMDA8
CMDA4
CMDA25
CMDA23
CMDA9
CMDA12
CMDA14
CMDA29
CMDA13
CMDA27
CLKA1
CLKA1#
CMDA19
CMDA16
CMDA18
CMDA11
CMDA15
CMDA28
DQSA5
DQSA6
DQMA5
DQMA6
DQSA#5
DQSA#6
CMDA20
ZQ3
12
V6
@
V6
@
U
U
M8
REFCA
V
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12
T3
A13
T7
A14
M7
A15/BA3
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE/CKE0
K1
ODT/ODT0
L2
CS/CS0
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
NC/ODT1
L1
NC/CS1
J9
NC/CE1
L9
NCZQ1
96-BALL
96-BALL
SDRAM DDR3
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
K4B1G1646E-HC12_FBGA96
D
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
QL0
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
DA45
M
M
DA41
MDA46
MDA40
MDA44
MDA43
MDA47
MDA42
MDA54
MDA50
MDA55
MDA48
MDA53
MDA51
MDA52
MDA49
+VRAM_1.5VS
+VRAM_1.5VS
2
M
ode E
Address
CMD0
R
0..31
ODT
CMD1
CS0#
CKE
A9
A6
A3
A0
A8
A12
A1
RAS#
A13
BA1
A14
CAS#
Group5
Group6Group7
CMD2
CMD3
CMD4
CMD5
CMD6
CMD7
CMD8
CMD9
CMD10
CMD11
CMD12
CMD13
CMD14
CMD15
CMD16
CMD17
CMD18
CMD19
CMD20
CMD21 A7
CMD22
CMD23
CMD24
CMD25
CMD26
CMD27
CMD28
CMD29
RST
A7
A4
A11
A2
A10
A5
BA2
WE#
BA0
CMD30
1
ank 0 Rank 1
2..63
3
0..31 32..63
ODT
CS1#
CKE
A11
A6
A3
A0
A8
A12 A0
A1
A7 A7
BA1 BA1
A12 A12
A8 A8
A0
A2 A2
RAS# RAS# RAS#
A13
A14
A3
A14
CAS#
A13 A13
CAS# CAS#
ODT
CS0#
CKE
RST RST RST
A6
A4
A11
A2
A10
A5
A5 A5
A9 A9
A1 A1
WE# WE#
A4 A4
BA2
WE#
BA0
A10 A10
BA0 BA0
BA2
A11A9
A14
A3BA1
ODT
CS1#
CKE
A6
BA2
Place close to the first T poi nt
CLKA1<19,26>
CLKA1#<19,26>
12
OPT@
OPT@
RV74
RV74
160_0402_1%
160_0402_1%
Place close to RANK1 VRAM
+VRAM_1.5VS +VRAM_1.5VS +VRAM_1.5VS
1
CV92
2
2
OPT@
OPT@ CV92
1U_0402_6.3V6K
1U_0402_6.3V6K
A A
5
4
1
CV94
CV93
2
2
OPT@
OPT@ CV94
OPT@
OPT@ CV93
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
CV95
CV96
2
2
OPT@
OPT@ CV95
OPT@
OPT@ CV96
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
1
1
CV97
2
OPT@
OPT@ CV97
0.1U_0402_10V7K
0.1U_0402_10V7K
1
CV98
OPT@
OPT@ CV98
0.1U_0402_10V7K
0.1U_0402_10V7K
CV100
2
OPT@
OPT@ CV99
0.1U_0402_10V7K
0.1U_0402_10V7K
CV101
2
2
OPT@
OPT@ CV100
OPT@
OPT@ CV101
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
1
CV99
1
1
CV102
2
2
OPT@
OPT@ CV102
1U_0402_6.3V6K
1U_0402_6.3V6K
Compal Secret Data
Compal Secret Data
2012/09/28 2013/09/28
2012/09/28 2013/09/28
2012/09/28 2013/09/28
Compal Secret Data
1
CV103
2
OPT@
OPT@ CV103
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CV104
2
OPT@
OPT@ CV104
1U_0402_6.3V6K
1U_0402_6.3V6K
Deciphered Date
Deciphered Date
Deciphered Date
1
1
CV105
CV106
2
2
OPT@
OPT@ CV105
OPT@
OPT@ CV106
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
2
1
1
CV107
CV108
CV108
2
2
OPT@
OPT@ CV107
OPT@
OPT@
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1
1
CV109
OPT@
OPT@ CV109
0.1U_0402_10V7K
0.1U_0402_10V7K
CV111
CV110
2
2
OPT@
OPT@ CV111
OPT@
OPT@ CV110
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
1
CV112
2
22U_0805_6.3V6M
22U_0805_6.3V6M
DRANK@
DRANK@ CV112
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
VGA_N14x VRAM RANK 0H
VGA_N14x VRAM RANK 0H
VGA_N14x VRAM RANK 0H
of
24 55Friday, June 21, 2013
of
24 55Friday, June 21, 2013
of
1
24 55Friday, June 21, 2013
0.4
0.4
0.4
5
4
RANK 1 [31...0]
V
RAM DDR3 Chips
D
D D
C C
B B
DQSA[3..0]<19,23>
QSA#[3..0]<19,23>
D
D
QMA[3..0]<19,23>
MDA[31..0]<19,23>
CMDA[30..0]<19,23,24,26>
QSA[3..0]
D
QSA#[3..0]
D
QMA[3..0]
M
DA[31..0]
CMDA[30..0]
+MEM_VREF_CA0
+MEM_VREF_DQ0
CLKA0<19,23>
CLKA0#<19,23>
RV77
RV77
243_0402_1%
243_0402_1%
DRANK@
DRANK@
DRANK@
DRANK@
0.01U_0402_25V7K
0.01U_0402_25V7K
12
CV88
CV88
CMDA9
CMDA24
CMDA10
CMDA13
CMDA26
CMDA22
CMDA21
CMDA5
CMDA8
CMDA23
CMDA28
CMDA4
CMDA7
CMDA14
CMDA12
CMDA29
CMDA6
CMDA30
CMDA3
CMDA0
CMDA1
CMDA11
CMDA15
CMDA25
DQSA1
DQSA2
DQMA1
DQMA2
DQSA#1
DQSA#2
ZQ4
12
UV7
@
UV7
@
M8
VREFCA
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12
T3
A13
T7
A14
M7
A15/BA3
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE/CKE0
K1
ODT/ODT0
L2
CS/CS0
J3
RAS
K3
CAS
L3
WE
310mA 310mA
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
NC/ODT1
L1
NC/CS1
J9
NC/CE1
L9
NCZQ1
96-BALL
96-BALL
SDRAM DDR3
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
K4B1G1646E-HC12_FBGA96
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
MDA12
MDA9
MDA15
MDA8
MDA14
MDA10
MDA11
MDA13
MDA22
MDA18
MDA23
MDA16
MDA21
MDA19
MDA20
MDA17
+VRAM_1.5VS
+VRAM_1.5VS
Group1
Group2
+MEM_VREF_CA0
+MEM_VREF_DQ0
3
CV89
CV89
0.01U_0402_25V7K
0.01U_0402_25V7K
DRANK@
DRANK@
1
2
243_0402_1%
243_0402_1%
RV78
RV78
DRANK@
DRANK@
CMDA9
CMDA24
CMDA10
CMDA13
CMDA26
CMDA22
CMDA21
CMDA5
CMDA8
CMDA23
CMDA28
CMDA4
CMDA7
CMDA14
CMDA12
CMDA29
CMDA6
CMDA30
CLKA0
CLKA0#
CMDA3
CMDA0
CMDA1
CMDA11
CMDA15
CMDA25
DQSA0
DQSA3
DQMA0
DQMA3
DQSA#0
DQSA#3
CMDA20CMDA20
12
UV8
UV8
M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M2
N8
M3
J7
K7
K9
K1
L2
J3
K3
L3
F3
C7
E7
D3
G3
B7
T2
L8
ZQ5
J1
L1
J9
L9
K4B1G1646E-HC12_FBGA96
K4B1G1646E-HC12_FBGA96
VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
BA0
BA1
BA2
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU
RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
96-BALL
96-BALL
SDRAM DDR3
SDRAM DDR3
2
M
ode E
Address
CMD0
Rank 0
0..31
ODT
CMD1
CMD2
CMD3
CMD4
CMD5
CMD6
CMD7
@
@
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
MDA1
MDA6
MDA0
MDA5
MDA3
MDA7
MDA2
MDA4
MDA26
MDA30
MDA24
MDA29
MDA25
MDA31
MDA27
MDA28
+VRAM_1.5VS
+VRAM_1.5VS
Group0
Group3
CMD8
CMD9
CMD10
CMD11
CMD12
CMD13
CMD14
CMD15
CMD16
CMD17
CMD18
CMD19
CMD20
CMD22
CMD23
CMD24
CMD25
CMD26
CMD27
CMD28
CMD29
CMD30
CS0#
CKE
A9
A6
A3
A0
A8
A12
A1
RAS#
A13
BA1
A14
CAS#
RST
A7
A4
A11
A2
A10
A5
BA2
WE#
BA0
1
Rank 1
32..63
ODT
CS1#
CKE
A9
A11
A6
A3
BA1
A0
A8
A8
A0
A1
RAS#RAS#
A13
BA1 A3
A14
A3
A14
CAS#
ODT
CS0#
CKE
RST
A7CMD21
A4
A6
A5
A11
A2
A1
A10
A5
A4
BA2
WE#
BA0
BA0
BA2
32..630..31
A11
A7A7
BA1
A12A12
A8
A0A12
A2A2
RAS#
A14
A13A13
CAS#CAS#
ODT
CS1#
CKE
RSTRST
A6
A5
A9A9
A1
WE#WE#
A4
A10A10
BA0
BA2
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2012/09/28 2013/09/28
2012/09/28 2013/09/28
2012/09/28 2013/09/28
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
VGA_N14x VRAM RANK 1L
VGA_N14x VRAM RANK 1L
VGA_N14x VRAM RANK 1L
of
25 55Friday, June 21, 2013
of
25 55Friday, June 21, 2013
of
1
25 55Friday, June 21, 2013
0.4
0.4
0.4
5
ANK 1[63...32]
R
RAM DDR3 Chips
V
D
QSA[7..4]<19,24>
D
QSA#[7..4]<19,24>
D D
C C
B B
D
QMA[7..4]<19,24>
D
DA[63..32]<19,24>
M
CMDA[30..0]<19,23,24,25>
QSA[7..4]
DQSA#[7..4]
QMA[7..4]
D
DA[63..32]
M
CMDA[30..0]
+MEM_VREF_CA1
+MEM_VREF_DQ1
CLKA1<19,24>
CLKA1#<19,24>
RV79
RV79
243_0402_1%
243_0402_1%
DRANK@
DRANK@
DRANK@
DRANK@
0.01U_0402_25V7K
0.01U_0402_25V7K
12
CV90
CV90
CMDA9
CMDA24
CMDA10
CMDA13
CMDA26
CMDA22
CMDA21
CMDA5
CMDA8
CMDA23
CMDA28
CMDA4
CMDA7
CMDA14
CMDA12
CMDA29
CMDA6
CMDA30
CMDA19
CMDA16
CMDA17
CMDA11
CMDA15
CMDA25
DQSA4
DQSA7
DQMA4
DQMA7
DQSA#4
DQSA#7
CMDA20
ZQ6 ZQ7
12
4
UV9
@
UV9
@
M8
VREFCA
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12
T3
A13
T7
A14
M7
A15/BA3
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE/CKE0
K1
ODT/ODT0
L2
CS/CS0
J3
RAS
K3
CAS
L3
WE
310mA
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
NC/ODT1
L1
NC/CS1
J9
NC/CE1
L9
NCZQ1
96-BALL
96-BALL
SDRAM DDR3
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
K4B1G1646E-HC12_FBGA96
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
MDA37
MDA35
MDA36
MDA32
MDA39
MDA34
MDA38
MDA33
MDA62
MDA58
MDA63
MDA56
MDA60
MDA59
MDA61
MDA57
+VRAM_1.5VS
+VRAM_1.5VS
Group7
+MEM_VREF_CA1
+MEM_VREF_DQ1
3
CV91
CV91
0.01U_0402_25V7K
0.01U_0402_25V7K
DRANK@
DRANK@
1
2
RV80
RV80
243_0402_1%
243_0402_1%
DRANK@
DRANK@
CMDA9
CMDA24
CMDA10
CMDA13
CMDA26
CMDA22
CMDA21
CMDA5
CMDA8
CMDA23
CMDA28
CMDA4
CMDA7
CMDA14
CMDA12
CMDA29
CMDA6
CMDA30
CLKA1
CLKA1#
CMDA19
CMDA16
CMDA17
CMDA11
CMDA15
CMDA25
DQSA5
DQSA6
DQMA5
DQMA6
DQSA#5
DQSA#6
CMDA20
12
UV10
@
UV10
M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M2
N8
M3
J7
K7
K9
K1
L2
J3
K3
L3
F3
C7
E7
D3
G3
B7
T2
L8
J1
L1
J9
L9
@
VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
BA0
BA1
BA2
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
310mA
DQSL
DQSU
DML
DMU
DQSL
DQSU
RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
96-BALL
96-BALL
SDRAM DDR3
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
K4B1G1646E-HC12_FBGA96
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
MDA41
MDA45
MDA40
MDA46
MDA42
MDA47
MDA43
MDA44
MDA50
MDA54
MDA48
MDA55
MDA49
MDA52
MDA51
MDA53
+VRAM_1.5VS
+VRAM_1.5VS
2
ode E
M
Address
CMD0
Rank 0
0..31
ODT
CMD1
Group5Group4
Group6
CMD2
CMD3
CMD4
CMD5
CMD6
CMD7
CMD8
CMD9
CMD10
CMD11
CMD12
CMD13
CMD14
CMD15
CMD16
CMD17
CS0#
CKE
A9
A6
A3
A0
A8
A12
A1
RAS#
A13
BA1
A14
CAS#
CMD18
CMD19
CMD20
RST
A7
CMD22
CMD23
CMD24
CMD25
CMD26
CMD27
CMD28
CMD29
A4
A11
A2
A10
A5
BA2
WE#
BA0
CMD30
1
Rank 1
32..63
ODT
CS1#
CKE
A9
A11
A6
A3
A
A8
BA1
0
A8
A0
A1
RAS#RAS#
A13
BA1 A3
A14
A3
A14
CAS#
ODT
CS0#
CKE
RST
A7CMD21
A4
A6
A5
A11
A2
A1
A10
A5
A4
BA2
WE#
BA0
BA0
BA2
32..630..31
A11
A7A7
BA1
A12A12
A8
A0A12
A2A2
RAS#
A14
A13A13
CAS#CAS#
ODT
CS1#
CKE
RSTRST
A6
A5
A9A9
A1
WE#WE#
A4
A10A10
BA0
BA2
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2012/09/28 2013/09/28
2012/09/28 2013/09/28
2012/09/28 2013/09/28
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
2
Date: Sheet
Compal Electronics, Inc.
VGA_N14x VRAM RANK 1H
VGA_N14x VRAM RANK 1H
VGA_N14x VRAM RANK 1H
of
26 55Friday, June 21, 2013
of
26 55Friday, June 21, 2013
1
26 55Friday, June 21, 2013
0.4
0.4
0.4
5
+
3VS
1
00mil 100mil
C
lose to Pin3
10U_0603_6.3V6M
10U_0603_6.3V6M
D D
LVDS@
LVDS@
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CT1
CT1
LVDS@
LVDS@
1 2
@
@
R
R
T1 0_0603_5%
T1 0_0603_5%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C
C
T2
T2
2
2
LVDS@
LVDS@
+
3VS_RT
+
DP_V33
C
C
T3
T3
Close to LT2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CT4
CT4
2
L
L
L
L
VDS@
VDS@
VDS@
VDS@
1
CT5
CT5
2
+3VS_RT
SWR / LDO Mode select
LDO mode is adopted as default power regulator mode.
Also can implement SWR mode by add inductor.
C C
IEDP@
IEDP@
1 2
C476 0.1U_04 02_10V6K
C476 0.1U_04 02_10V6K
IEDP@
IEDP@
1 2
C477 0.1U_04 02_10V6K
C477 0.1U_04 02_10V6K
LVDS@
LVDS@
1 2
C478 0.1U_04 02_10V6K
H_EDP_AUXP<5>
H_EDP_AUXN<5>
B B
H_EDP_TXP0<5>
H_EDP_TXN0<5>
C478 0.1U_04 02_10V6K
LVDS@
LVDS@
1 2
C479 0.1U_04 02_10V6K
C479 0.1U_04 02_10V6K
LVDS@
LVDS@
1 2
C480 0.1U_04 02_10V6K
C480 0.1U_04 02_10V6K
LVDS@
LVDS@
1 2
C481 0.1U_04 02_10V6K
C481 0.1U_04 02_10V6K
IEDP@
IEDP@
1 2
C482 0.1U_04 02_10V6K
C482 0.1U_04 02_10V6K
IEDP@
IEDP@
1 2
C483 0.1U_04 02_10V6K
C483 0.1U_04 02_10V6K
4
Close to Pin18
SWR_VDD
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
CT8
CT8
2
L
L
VDS@
VDS@
12
+DP_V33
12
+SWR_VDD
+SWR_V12
H_EDP_AUXP_C_TL
H_EDP_AUXN_C_TL
H_EDP_TXP0_C_TL
H_EDP_TXN0_C_TL
RT8
RT8
12K_0402_1%
12K_0402_1%
LVDS@
LVDS@
+
1 2
LCD_EDID_CLK_TL
LCD_EDID_DATA_TL
LCD_TL_TXOUT0LCD_TL_TXOUT0+
H_EDP_AUXP_C_R
H_EDP_AUXN_C_R
H_EDP_TXN0_C_R
H_EDP_TXP0_C_R
0mil
22U_0603_6.3V6M
22U_0603_6.3V6M
L
L
VDS@
VDS@
Close to Pin13
8
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
CT6
CT6
CT7
CT7
2
2
L
L
VDS@
VDS@
LVDS@
LVDS@
LT1
LT1
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
LVDS@
LVDS@
LT2
LT2
100mil 40mil
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
EC_SMB_CK3<36>
EC_SMB_DA3<36>
H_EDP_HPD<28,9>
Close to Pin8
H_EDP_AUXP_C_R
H_EDP_AUXN_C_R
H_EDP_AUXP_C_TL
H_EDP_AUXN_C_TL
H_EDP_TXP0_C_TL
H_EDP_TXN0_C_TL
H_EDP_TXP0_C_R
H_EDP_TXN0_C_R
40mil
100mil
40mil
40mil
40mil
40mil
UT2
UT2
3
DP_V33
13
SWR_VDD
18
PVCC
12
SWR_LX
11
SWR_VCCK
27
VCCK
7
DP_V12
2
AUX_P
1
AUX_N
5
LANE0P
6
LANE0N
9
CIICSCL1
10
CIICSDA1
32
HPD
8
DP_REXT
4
DP_GND
RTD2132R-CG QFN32
RTD2132R-CG QFN32
LVDS@
LVDS@
1 8
2 7
3 6
4 5
0_0804_8P4R_5%
0_0804_8P4R_5%
1 8
2 7
3 6
4 5
0_0804_8P4R_5%
0_0804_8P4R_5%
Close to LT3
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CT9
CT9
2
L
L
VDS@
VDS@
RTD2132S
RTD2132S
DP-IN
DP-IN
Other
Other
RP4
RP4
RP5
RP5
Place co-lay Resistor back to back on TOP and BOT
L
L
Power
Power
LVDS@
LVDS@
IEDP@
IEDP@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
VDS@
VDS@
GPIO
GPIO
LVDS
LVDS
EDID
EDID
ROM
ROM
3
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
CT10
CT10
2
L
L
VDS@
VDS@
C
Pin27
TXEC+
TXEC-
TXE2+
TXE2-
TXE1+
LVDS
LVDS
TXE1-
TXE0+
TXE0-
GPIO(PWM OUT)
GPIO(Panel_VCC)
GPIO(PWM IN)
GPIO(BL_EN)
MIICSCL1
MIICDA1
MIICSCL0
MIICSDA0
GND
1
2
lose to
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CT11
CT11
Close to Pin7
19
20
21
22
23
LCD_TL_TXOUT1+
24
LCD_TL_TXOUT1-
25
LCD_TL_TXOUT0+
26
LCD_TL_TXOUT0-
14
TL_INVT_PWM
15
80mil
16
17
29
LCD_EDID_CLK_TL
28
LCD_EDID_DATA_TL
31
MIIC_SCL
30
MIIC_SDA
33
1
2
CT12
CT12
LVDS@
LVDS@
SWR_V12
+
LCD_TXCLK+ <28>
LCD_TXCLK- <28>
LCD_TXOUT2+ <28>
LCD_TXOUT2- <28>
LCD_EDID_CLK <28>
LCD_EDID_DATA <28>
LCD_TXOUT0- <28>
LCD_TXOUT0+ <28>
TL_INVT_PWM <28>
PCH_PWM_TL <9>
EC_ENBKL <28,36>
+LCD_VDD
2
M
ode Configure
OM only mode : PIN 30 4.7k pull low, Pin 31 4.7k pull high.
R
EP mode : PIN 30 4.7k pull high, Pin 31 4.7k pull low.
!
E
EPROM : PIN 30 4.7k pull high, Pin 31 4.7k pull high.
"
D
efault mode
MIIC_SDA MIIC_SCL
PIN30 PIN31
+LCD_VDD
LCD_EDID_DATA_TL
LCD_EDID_CLK_TL
#
3VS_RT
+
T4
T4
R
R
@
@
4.7K_0402_5%
4.7K_0402_5%
1 2
RT6
RT6
LVDS@
LVDS@
4.7K_0402_5%
4.7K_0402_5%
1 2
RT9 4.7K_0402_5%
RT9 4.7K_0402_5%
RT10 4.7K_0402_5%
RT10 4.7K_0402_5%
+LCD_VDD
LVDS@
LVDS@
1 2
LVDS@
LVDS@
1 2
+3VS_RT
1
LVDS@
LVDS@
3VS_RT
+
1 2
@
@
1 2
R
R
T12
T12
4.7K_0402_5%
4.7K_0402_5%
RT7
RT7
4.7K_0402_5%
4.7K_0402_5%
80mil
12
2
RT113
CT13
CT13
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
LVDS@
LVDS@
RT113
100K_0402_5%
100K_0402_5%
LVDS@
LVDS@
1
Close to Panel conn.
PIN15
2132S
2132R
* Version R internal Power Switch, can
output 1A, Rds(on)=0.2 ohm
TL_ENVDD
+LCD_VDD *
PIN16
Accept voltage input (high level)
2132S
2132R
* Version R has internal level shifter, remove
level shifter circuit on AMD platform
3.3V
1.5~3.3V
Different between 2132S and 2132R
IEDP@
IEDP@
1 2
C62 0.1U_0402_10V7K
H_EDP_TXP1<5>
A A
LCD_TL_TXOUT1+
LCD_TL_TXOUT1-
5
C62 0.1U_0402_10V7K
IEDP@
IEDP@
1 2
C63 0.1U_0402_10V7K
C63 0.1U_0402_10V7K
LVDS@
LVDS@
1 2
R42 0_0402_5%
R42 0_0402_5%
LVDS@
LVDS@
1 2
R43 0_0402_5%
R43 0_0402_5%
4
LCD_TXOUT1+ <28>
LCD_TXOUT1- <28>H_EDP_TXN1<5>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2011/06/30 2013/06/30
2011/06/30 2013/06/30
2011/06/30 2013/06/30
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2132S 2132R
1. Support SWR mode
1. Support LDO mode and SWR mode
2. Internal ROM
3. Support LCD_VDD(internal Power switch)
4. Integrates Level shifter
Title
Title
Title
LVDS Translator - RTD2132S
LVDS Translator - RTD2132S
LVDS Translator - RTD2132S
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
ZRMAA/ZEMAA
ZRMAA/ZEMAA
ZRMAA/ZEMAA
1
27 55Friday, June 21, 2013
27 55Friday, June 21, 2013
27 55Friday, June 21, 2013
0.4
0.4
0.4
of
of
of
A
TOUCH_EMI@
TOUCH_EMI@
SB20_P5_R
U
BTO : TOUCH_EMI@
1 1
U
SB20_N5_R
1 2
R
R
4280 0_0402_5%
4280 0_0402_5%
61 D LW21HN900SQ2L_4P
61 D LW21HN900SQ2L_4P
L
L
4
4
1
1
@TOUCH_EMI@
@TOUCH_EMI@
1 2
4281 0_0402_5%
4281 0_0402_5%
R
R
TOUCH_EMI@
TOUCH_EMI@
B
SB20_P5 <1 1>
U
3
3
2
2
SB20_N5 <11>
U
EMI reques t - Close to JEDP co nnector
L62 D LW21HN900SQ2L_4P
L62 D LW21HN900SQ2L_4P
USB20_N7_R
USB20_P7_R
4
1
4
1
CAM_EMI@
CAM_EMI@
3
3
2
2
USB20_N7 <11>
USB20_P7 <11>
C
L
CD POWER CIRCUIT (For EDP panel only)
3VS
+
W=80mils
+LCD_VDD_SS
12
C475
C475
1500P_0402_50V7K
1500P_0402_50V7K
IEDP@
IEDP@
D
U18
U18
5
4
VOUT
VIN
GND
SS
APL3512ABI-TRG_SOT23-5
APL3512ABI-TRG_SOT23-5
IEDP@
IEDP@
EN
1
W=80mils
2
3
100K_0402_5%
100K_0402_5%
IEDP@
IEDP@
R430
R430
1 2
LCD_VDD
+
E
LCD_ENVDD <9>
LVDS colay eDP cable
2 2
3 3
Pin define will be change after ME ready
JLVDS@JLVDS
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
GND
32
GND
33
GND
34
GND
35
GND
@
+5VS_LVDS_TOUCH
USB20_N5_R
USB20_P5_R
BKOFF#
USB20_P7_R
USB20_N7_R
+3VS_LVDS_CAM
LED_PWM
BKOFF#_R
Irush=1.5A
1 2
@
@
R432 0_0603_5%
R432 0_0603_5%
LCD_EDID_CLK <27>
LCD_EDID_DATA <27>
LCD_TXOUT0- <27>
LCD_TXOUT0+ <27>
LCD_TXOUT1- <27>
LCD_TXOUT1+ <27>
LCD_TXOUT2- <27>
LCD_TXOUT2+ <27>
LCD_TXCLK- <27>
LCD_TXCLK+ <27>
H_EDP_HPD <27,9>
60mils
+LCD_INV
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
+LCD_VDD
+LCD_INV
L63
L63
EMI@
EMI@
R431 0_0603_5%
R431 0_0603_5%
Irush=1.5A
Irush=1.5A
12
1 2
@
@
60mils
B+
INT_MIC_DATA <35>
INT_MIC_CLK <35>
60mils
+5VS
+3VS
20mils
+3VS
20mils
Touch
Camera
INT_MIC_DATA
INT_MIC_CLK
USB20_P7_R
USB20_N7_R
2
3
D97
D97
YSLC05CH_SOT23-3
ESD@DA8
ESD@
DA8
ESD@
ESD@
1 2
1 2
DA9
DA9
CK0402101V05_0402-2
CK0402101V05_0402-2
CK0402101V05_0402-2
CK0402101V05_0402-2
YSLC05CH_SOT23-3
@ESD@
@ESD@
1
+3VS +3VS
Reserve for eDP panel
5
U50
U50
BKOFF#_R
4 4
1 2
R433 0_0402_5%R 433 0_0402_5%
12
R434
R434
10K_0402_5%
10K_0402_5%
4
OUT
1 2
R436 0_0402_5%
R436 0_0402_5%
Reserve for LVDS panel
A
1
IN1
VCC
2
IN2
GND
3
MC74VHC1G08DFT2G_SC70-5
MC74VHC1G08DFT2G_SC70-5
@
@
ENBKL
BKOFF#
BKOFF# <36>
B
5
U51
U51
4
OUT
1
IN1
VCC
2
IN2
GND
3
MC74VHC1G08DFT2G_SC70-5
MC74VHC1G08DFT2G_SC70-5
EC_ENBKL <27,36>
EC_ENBKL_R <9>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
47K_0402_5%
47K_0402_5%
C
LED_PWM
R435
R435
2012/04/19 2015/04/19
2012/04/19 2015/04/19
2012/04/19 2015/04/19
12
IEDP@
IEDP@
1 2
D90 RB751V40_SC76-2
D90 RB751V40_SC76-2
1 2
D91 RB751V40_SC76-2
D91 RB751V40_SC76-2
LVDS@
LVDS@
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
PCH_PWM_EDP <9>
TL_INVT_PWM <27>
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
LVDS
LVDS
LVDS
ZRMAA/ZEMAA
ZRMAA/ZEMAA
ZRMAA/ZEMAA
28 55Friday, June 21, 2013
28 55Friday, June 21, 2013
28 55Friday, June 21, 2013
E
of
of
of
0.4
0.4
0.4
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
B
MA_HDMI_CLK<9>
U
MA_HDMI_DATA<9>
U
UMA_HDMI_CLK
MA_HDMI_DATA
U
H_DVI_TXC-
H_DVI_TXC+
H_DVI_TXD0- HDMI_R_D0-
H_DVI_TXD0+ HDMI_R_D0+
H_DVI_TXD1-
H_DVI_TXD1+
H_DVI_TXD2- HDMI_R_D2-
H_DVI_TXD2+ HDMI_R_D2+
Common CHOKE use 67ohm
3 1
BSH111_SOT23-3
BSH111_SOT23-3
DLW21HN900SQ2L_4P
DLW21HN900SQ2L_4P
4
4
1
1
L64
EMI@
L64
EMI@
DLW21HN900SQ2L_4P
DLW21HN900SQ2L_4P
1
1
4
4
L65
EMI@L65
EMI@
DLW21HN900SQ2L_4P
DLW21HN900SQ2L_4P
4
4
1
1
L66
EMI@
L66
EMI@
DLW21HN900SQ2L_4P
DLW21HN900SQ2L_4P
1
1
4
4
L67
EMI@
L67
EMI@
A
HDMI_5V_OUT
+
P3
P3
R
3VS
1 1
2 2
+
R
1 8
2 7
3 6
4 5
2.2K_0804_8P4R_5%
2.2K_0804_8P4R_5%
H_HDMI_TXC-<5>
H_HDMI_TXC+<5>
H_HDMI_TX0-< 5>
H_HDMI_TX0+<5>
H_HDMI_TX1-< 5>
H_HDMI_TX1+<5>
H_HDMI_TX2-< 5>
H_HDMI_TX2+<5>
H
DMI_SCLK
HDMI_SDATA
U
MA_HDMI_CLK
MA_HDMI_DATA
U
C486 0.1U_0402_10V7KC486 0.1U_0402_10V7K
C484 0.1U_0402_10V7KC484 0.1U_0402_10V7K
C490 0.1U_0402_10V7KC490 0.1U_0402_10V7K
C488 0.1U_0402_10V7KC488 0.1U_0402_10V7K
C494 0.1U_0402_10V7KC494 0.1U_0402_10V7K
C492 0.1U_0402_10V7KC492 0.1U_0402_10V7K
C498 0.1U_0402_10V7KC498 0.1U_0402_10V7K
C496 0.1U_0402_10V7KC496 0.1U_0402_10V7K
3VS
+
2
SGD
SGD
3
2
2
3
3
2
2
3
C
3 1
BSH111_SOT23-3
BSH111_SOT23-3
Q191
Q191
3
2
2
3
3
2
2
3
3VS
+
2
SGD
SGD
HDMI_R_CK-
HDMI_R_CK+
HDMI_R_D1-
HDMI_R_D1+
D
HDMI_5V_OUT
+
H
2
500
500
C
C
0.1U_0402_10V7K
0.1U_0402_10V7K
HDMI_SCLK
190
190
Q
Q
DMI_SDATA
H
2
@ESD@
@ESD@
C487
C487
0.1U_0402_10V7K
0.1U_0402_10V7K
1
+HDMI_5V_OUT
HDMI Connector
JHDMI
HDMI_HPD_C
HDMI_SDATA
HDMI_SCLK
HDMI_R_CK-
HDMI_R_CK+
HDMI_R_D0-
HDMI_R_D0+
HDMI_R_D1-
HDMI_R_D1+
HDMI_R_D2-
HDMI_R_D2+
19
HP_DET
18
+5V
17
DDC/CEC_GND
16
SDA
15
SCL
14
Utility
13
CEC
12
CK-
11
CK_shield
10
CK+
9
D0-
8
D0_shield
7
D0+
6
D1-
5
D1_shield
4
D1+
3
D2-
2
D2_shield
1
D2+
ACON_HMR2J-AK120C
ACON_HMR2J-AK120C
1
5
1
P
A2Y
G
74AHCT1G125GW_SOT353-5
74AHCT1G125GW_SOT353-5
3
HDMI_HPD
@JHDMI
@
20
GND
21
GND
22
GND
23
GND
DMI_HPD_U
9
9
U
U
4
OE#
1 2
1K_0402_5%
1K_0402_5%
H
DMI_HPD
R438
R438
2.2K_0402_5%
2.2K_0402_5%
R
R
437
437
100K_0402_5%
100K_0402_5%
12
+3VS
E
R
R
439
439
DMI_HPD_C
H
2
C
C
501
501
0.1U_0402_10V7K
0.1U_0402_10V7K
1
1 2
HDMI_HPD < 10,9>
RP1
RP1
HDMI_R_D2-
3 3
ZZZ1
HDMI45@ZZZ1
HDMI Royalty
HDMI45@
RO0000003HM
HDMI W/Logo + HDCP
HDMI W/Logo + HDCP
,D/tK>ŽŐŽZKϬϬϬϬϬϬϭ,D
,D/t>ŽŐŽZKϬϬϬϬϬϬϮ,D
,D/t>ŽŐŽн,WZKϬϬϬϬϬϬϯ,D
HDMI_R_D2+
HDMI_R_D1+
HDMI_R_D1-
HDMI_R_CK+
HDMI_R_CKHDMI_R_D0HDMI_R_D0+
virtual material to 45@ BOM
4 4
A
B
1 8
2 7
3 6
4 5
680_8P4R_5%
680_8P4R_5%
RP2
RP2
1 8
2 7
3 6
4 5
680_8P4R_5%
680_8P4R_5%
+5VS
HDMI POWER CIRCUIT
VIN = 5V, IOUT = 0.5A , RDS(ON) TYP=95m ; MAX=115m
Current Limit: TYP=0.8A ; MAX=1A
+HDMI_5V_OUT
1
CY18
13
D
D
Q192
Q192
2
G
G
S
S
2N7002KW_SOT323-3
2N7002KW_SOT323-3
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2012/04/19 2015/04/19
2012/04/19 2015/04/19
2012/04/19 2015/04/19
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
CY18
0.1U_0402_10V7K
0.1U_0402_10V7K
D
2
Date: Sheet
Date: Sheet
Date: Sheet
UY2
UY2
1
2
3
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
5
IN
OUT
GND
4
EN
FLG
AP2151DWG-7_SOT25-5
AP2151DWG-7_SOT25-5
SA00006H00 0
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
HDMI Conn.
HDMI Conn.
HDMI Conn.
ZRMAA/ZEMAA
ZRMAA/ZEMAA
ZRMAA/ZEMAA
E
+5VS
of
29 55Friday, June 21, 2013
of
29 55Friday, June 21, 2013
of
29 55Friday, June 21, 2013
0.4
0.4
0.4
A
S
ATA HDD Conn.
ACES_50208-00801-003
ACES_50208-00801-003
1 1
G
G
JHDD
@JHDD
@
10
ND
9
ND
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
S
ATA_PTX_C_DRX_P0
ATA_PTX_C_DRX_N0
S
ATA_PRX_DTX_N0
S
S
ATA_PRX_DTX_P0
+5VS
1 2
C
C
511 0.01U_0402_25V7K
511 0.01U_0402_25V7K
1 2
512 0.01U_0402_25V7K
512 0.01U_0402_25V7K
C
C
1 2
513 0.01U_0402_25V7K
513 0.01U_0402_25V7K
C
C
1 2
C
C
514 0.01U_0402_25V7K
514 0.01U_0402_25V7K
Close to JHDD
B
ATA_PTX_DRX_P0 <7>
S
ATA_PTX_DRX_N0 <7>
S
ATA_PRX_C_DTX_N0 <7>
S
SATA_PRX_C_DTX_P0 <7>
C
D
E
+5VS
2 2
3 3
Place closely JHDD SATA CONN.
1.2A
12
C515
C515
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C516
C516
0.1U_0402_10V7K
0.1U_0402_10V7K
2
1
C517
C517
0.1U_0402_10V7K
0.1U_0402_10V7K
2
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2012/04/19 2015/04/19
2012/04/19 2015/04/19
2012/04/19 2015/04/19
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
HDD/Gsensor
HDD/Gsensor
HDD/Gsensor
ZRMAA/ZEMAA
ZRMAA/ZEMAA
ZRMAA/ZEMAA
E
0.4
0.4
0.4
of
30 55Friday, June 21, 2013
of
30 55Friday, June 21, 2013
of
30 55Friday, June 21, 2013
A
B
Slot 1 Half PCIe Mini Card-WLAN
U
LAN&BT Combo mo dule circuits
W
B
T
on module
nable Disable
E
1 1
BT_ON
BT
on module
H L
W
1 2
RM26
RM26
From EC
BT_ON< 36>
For isolate BT_CTRL and
Compal Debug Card.
1K_0402_5%
1K_0402_5%
E51_RXDBT_ON
WLAN_WAKE#<36>
WiMax/ BT
LAN/ WiFi
RC285 0_0 402_5%
RC285 0_0 402_5%
1 2
@
@
CIE_PTX_C_WLANRX_P4<11>
P
PCIE_PTX_C_WLANRX_N4<11>
PCIE_PRX_WLANTX_P4<11>
PCIE_PRX_WLANTX_N4< 11>
Mini PCIE type for Non-Ultra
JWLAN1
@JWLAN1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
GND1
GND2
@
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
WLAN_WAKE#_R
@
@
12
RM25
RM25
BT_ON
0_0402_5%
0_0402_5%
CLK_WLAN#_RM
CLK_WLAN_RM
PCIE_PRX_WLANTX_N4_R
PCIE_PRX_WLANTX_P4_R
E51_TXD
E51_RXD
PCIE_PRX_WLANTX_N4
PCIE_PRX_WLANTX_P4
PCIE_PTX_C_WLANRX_N4_M<11>
PCIE_PTX_C_WLANRX_P4_M<11>
CLKREQ_WLAN#
CLK_WLAN#
CLK_WLAN
RC298 & RC299 need to close to NGFF J WLAN for layout concern
1 2
RC288 0_0 402_5%MWL AN@ RC2 88 0_0402_5%MWLAN@
1 2
RC289 0_0 402_5%MWL AN@ RC2 89 0_0402_5%MWLAN@
1 2
RC298 0_0402_5%MWLAN@ RC298 0_0402_5%MWLAN@
1 2
RC299 0_0402_5%MWLAN@ RC299 0_0402_5%MWLAN@
2 2
WLAN/ WiFi
BT_CTRL_R
+3V_WLAN
Debug card using
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
LCN_DAN08-52406-050 0
LCN_DAN08-52406-050 0
U
CLK_WLAN<8>
CLK_WLAN#<8>
CLKREQ_WLAN#<10,8>
WLAN_WAKE#_R
+3V_WLAN
SB20_P4<11>
SB20_N4<11>
WL_OFF#
PLT_RST_BUF#
PM_SMBCLK
PM_SMBDATA
USB20_N4_RM
USB20_P4_RM
MWLAN@
MWLAN@
0.1U_0402_10V7K
0.1U_0402_10V7K
C
+3V_WLAN
0.1U_0402_10V7K
0.1U_0402_10V7K
1
CM1
CM1
CM2
CM2
MWLAN@
MWLAN@
2
Close to JWLAN1
1 2
C296 0_0402_5%NWLAN@RC296 0_0402_5%NWLAN@
R
1 2
R
C297 0_0402_5%NWLAN@RC297 0_0402_5%NWLAN@
1 2
RC300 0_0 402_5%NWLAN@ RC300 0_0402_5%NWLAN@
1 2
RC301 0_0 402_5%NWLAN@ RC301 0_0402_5%NWLAN@
1
CM3
CM3
MWLAN@
MWLAN@
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
WLAN/ WiFi
1
2
1 2
RC294 0_0 402_5%MWL AN@ RC2 94 0_0402_5%MWLAN@
1 2
RC295 0_0 402_5%MWL AN@ RC2 95 0_0402_5%MWLAN@
SB20_P4_R
U
U
SB20_N4_R
CLK_WLAN_R
CLK_WLAN#_R
USB20_N4
USB20_P4
WiMax/ BT
D
NGFF E TYPE for Ultra
J
J
WLAN
WLAN
1
ND
G
3
U
SB_D+
5
SB_D-
U
7
G
ND
9
DIO_CLK
S
11
DIO_CMD
S
13
S
DIO_DAT0
15
DIO_DAT1
S
17
S
DIO_DAT2
19
S
DIO_DAT3
21
SDIO_WAKE#
23
S
DIO_RST#
25
G
ND
27
ET_P0
P
29
PET_N0
31
GND
33
PER_P0
35
PER_N0
37
GND
39
REFCLK_P0
41
REFCLK_N0
43
GND
45
CLKREQ0#
47
PEWAKE0#
49
GND
51
RSVD/PET_P1
53
RSVD/PET_N1
55
GND
57
RSVD/PER_P1
59
RSVD/PER_N1
61
GND
63
RSVD
65
RSVD
67
GND
68
GND1
LOTES_APCI0019-P002A
LOTES_APCI0019-P002A
.3VAUX
3
3
.3VAUX
ED1#
L
P
CM_CLK
CM_SYNC
P
CM_IN
P
P
CM_OUT
ED2#
L
G
U
ART_WAKE#
UART_RX
U
ART_TX
U
ART_CTS
ART_RTS
U
RSVD
RSVD
RSVD
COEX3
COEX2
COEX1
SUSCLK
PERST0#
W_DISABLE2#
W_DISABLE1#
I2C_DAT
I2C_CLK
ALERT
RSVD
RSVD
RSVD
RSVD
3.3VAUX
3.3VAUX
GND2
E
+
3V_WLAN
2
4
6
8
10
12
14
16
18
ND
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
69
@
@
E
E51_RXD
BT_ON
51_TXD
+
3V_WLAN
0.1U_0402_10V7K
0.1U_0402_10V7K
1
C
C
C
C
M6
M6
M8
M8
NWLAN@
NWLAN@
NWLAN@
NWLAN@
2
0.1U_0402_10V7K
0.1U_0402_10V7K
C
lose to JWLAN
E51_TXD <36>
E51_RXD <36>
Debug card using
WL_OFF# <3 6>
PM_SMBCLK < 16,17,33,8>
PM_SMBDATA <16 ,17,33,8>
Need Change to use I2C
1
1
C
C
M7
M7
NWLAN@
NWLAN@
2
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
CLK_EC <9>
PLT_RST_BUF# <32,35, 9>
1
CCL6
3 3
Green Clock
UCL1 GCLK@
UCL1 GCLK@
+3VL
+3VALW
DIS only
+3VL +1 .05VS_VTT+3V_LAN +3VS_DGPU +3VALW
1
CCL5
CCL5
GCLK@
GCLK@
2
0.1U_0402_10V7K
0.1U_0402_10V7K
B
GND
1
CCL2
CCL2
GCLK@
GCLK@
2
.1U_0402_10V7K
.1U_0402_10V7K
0
0
GCLK@
GCLK@
3
GND
2
4
A
1
CCL1
CCL1
GCLK@
GCLK@
2
.1U_0402_10V7K
.1U_0402_10V7K
0
0
YCL1 25MHZ 12PF X3G025000DK1H-X
4 4
YCL1 25MHZ 12PF X3G025000DK1H-X
1
1
1
CCL7
CCL7
18P_0402_50V8J
18P_0402_50V8J
GCLK@
GCLK@
2
1
CCL3
CCL3
GCLK@
GCLK@
2
0.1U_0402_10V7K
0.1U_0402_10V7K
3
CLK_X2CLK_X1
1
CCL8
CCL8
18P_0402_50V8J
18P_0402_50V8J
GCLK@
GCLK@
2
1
CCL4
CCL4
DGCLK@
DGCLK@
2
0.1U_0402_10V7K
0.1U_0402_10V7K
+3V_LAN
+1.05VS_VTT
+3VS_DGPU
DIS only
1 2
RCL5 0_0402_5%@RCL5 0_0402_5%@
+3V_LAN_R PCH_X1_R_R
CLK_X2
CLK_X1
Security Classif ication
Security Classif ication
Security Classif ication
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
18
V3.3A
3
VDD
14
VIO_32k_B
9
VIO_25M
4
VIOE_24M
VIOE_27M1227M
1
X2
2
X1
5
GND
8
GND
15
GND
19
THERMAL_PAD
SLG3NB282VTR_TQFN18_2X3P5
SLG3NB282VTR_TQFN18_2X3P5
VBAT
32.768k_A
32.768k_B
24M
25M
VOUT
2012/04/19 2015/0 4/19
2012/04/19 2015/0 4/19
2012/04/19 2015/0 4/19
CCL6
22U_0805_6.3V6M
22U_0805_6.3V6M
GCLK@
GCLK@
2
11
+RTCGCLK
10
16
6
7
LAN_X1_R_R
13
17
LAN_X1_R_R
PCH_X1_R_R
1
CCL10
CCL10
12P_0402_50V8J
12P_0402_50V8J
2
@
@
Compal Secret Data
Compal Secret Data
Compal Secret Data
1 2
VGA_X1_R
RCL3 22_0402_5%
RCL3 22_0402_5%
22 ohm for NV chip
2
GCLK@
GCLK@
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
CCL9
CCL9
1
1 2
RCL1 0_0402_5%
RCL1 0_0402_5%
For HDD cannot detect issue
Deciphered D ate
Deciphered D ate
Deciphered D ate
For safety request
RCL4
RCL4
120_0603_5%
120_0603_5%
DGCLK@
DGCLK@
RCL2 33_0402_5%RCL2 33_0402_5%
@
@
D
1 2
GCLK@
GCLK@
12
+RTC
VGA_X1 <18>
PCH_RTCX1_R <7>
DIS only
LAN_X2 <32>
PCH_X1_R <8>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCIe-WLAN/mSATA/GCLK
PCIe-WLAN/mSATA/GCLK
PCIe-WLAN/mSATA/GCLK
ZRMAA/ZEMAA
ZRMAA/ZEMAA
ZRMAA/ZEMAA
Friday, June 21, 2013
Friday, June 21, 2013
Friday, June 21, 2013
E
31 55
31 55
31 55
0.4
0.4
0.4
1 2
1 2
L21 0.1U_0402_10V7K
L21 0.1U_0402_10V7K
L
AN_X2 <31>
R
R
L1 2.49K_0402_1%
L1 2.49K_0402_1%
1
CL15
CL15
0.1U_0402_25V6
0.1U_0402_25V6
2
B
12
LAN_MDI3LAN_MDI3+
LAN_MDI2LAN_MDI2+
LAN_MDI1LAN_MDI1+
LAN_MDI0-
CIE_PRX_C_LANTX_P3 <11>
P
CIE_PRX_C_LANTX_N3 <11>
P
P
LT_RST_BUF# <31,35,9>
SP050006B10
SP050006B10
UL2
UL2
1
TCT1
MCT1
2
TD1+
MX1+
3
TD1-
MX1-
4
TCT2
MCT2
5
TD2+
MX2+
TD2-6MX2-
7
MCT3
TCT3
8
MX3+
TD3+
9
MX3-
TD3-
10
MCT4
TCT4
11
MX4+
TD4+
12
MX4-
TD4-
SUPERWORLD_SWG150401
SUPERWORLD_SWG150401
8111G@
8111G@
LAN_VDD10
+
L1, CL2,CL3,CL4 close to pin 3,8,22,30 respectively
C
CL5 close to pin 22, CL6 close to pin 30
CL 19 close to Pin 24
1 2
L1 0.1U_0402_10V7K8111G@
L1 0.1U_0402_10V7K8111G@
C
C
1 2
C
C
L2 0.1U_0402_10V7K
L2 0.1U_0402_10V7K
1 2
L3 0.1U_0402_10V7K8111G@
L3 0.1U_0402_10V7K8111G@
C
C
1 2
L4 0.1U_0402_10V7K
L4 0.1U_0402_10V7K
C
C
1 2
C
C
L5 1U_0402_6.3V6K8111G@
L5 1U_0402_6.3V6K8111G@
1 2
C
L6 1U_0402_6.3V6K8106E@CL6 1U_0402_6.3V6K8106E@
1 2
L19 0.1U_0402_10V7K8111G@
L19 0.1U_0402_10V7K8111G@
C
C
PJ7
8111G@
8111G@
8111G@
8111G@
RL3
RL3
1 2
RL4
RL4
1 2
RL5
RL5
1 2
RL6
RL6
1 2
2
JUMP_43X39
JUMP_43X39
75_0603_1%
75_0603_1%
75_0603_1%
75_0603_1%
75_0603_1%
75_0603_1%
75_0603_1%
75_0603_1%
+3VALW_PCH +3V_LAN
24
23
RJ45_MIDI3-
22
RJ45_MIDI3+
21
20
RJ45_MIDI2-
19
RJ45_MIDI2+
18
17
RJ45_MIDI1-
16
RJ45_MIDI1+
15
14
RJ45_MIDI0-
13
RJ45_MIDI0+LAN_MDI0+
A
A00005V700
A00005V700
S
S
U
U
L1
L1
AN_MDI0+
L
AN_MDI0-
L
+
LAN_VDD10
AN_MDI1+
L
AN_MDI1-
L
L
LAN_VDD10
+
+3V_LAN
P
CIE_PTX_C_LANRX_P3<11>
CIE_PTX_C_LANRX_N3<11>
P
LANCLK_REQ#
2
@ESD@
@ESD@
CL22
CL22
0.1U_0402_10V7K
0.1U_0402_10V7K
1
AN_MDI2+
AN_MDI2-
L
L
AN_MDI3+
L
AN_MDI3-
LANCLK_REQ#
LK_LAN<8>
C
C
LK_LAN#<8>
1 1
2 2
For 10/100 LAN SKU
SA000065Y00
SA000065Y00
UL1
UL1
8106E 10/100M
8106E 10/100M
8106E@
8106E@
SP050007700
SP050007700
UL2
UL2
10/100M transformer
10/100M transformer
8106E@
8106E@
3 3
1
M
2
M
3
A
4
M
5
M
6
M
7
M
8
A
9
M
10
M
11
AVDD33
12
CLKREQB
13
H
14
H
15
R
16
R
LAN_WAKE#
DIP0
DIN0
VDD10
DIP1
DIN1
DIP2
DIN2
VDD10
DIP3
DIN3
SIP
SIN
EFCLK_P
EFCLK_N
LAN_MDI0-
+3V_LAN
LAN_MDI0+
LAN_MDI2-
+3V_LAN
LAN_MDI2+
RTL8111G-CG_QFN32_4X48111G@
RTL8111G-CG_QFN32_4X48111G@
DL2
6
I/O4
5
VDD
4
I/O3
AZC099-04S.R7G_SOT23-6
AZC099-04S.R7G_SOT23-6
DL3
DL3
6
I/O4
5
VDD
4
I/O3
AZC099-04S.R7G_SOT23-6
AZC099-04S.R7G_SOT23-6
Power trace VDDREG > 40 mil, REGOUT trace > 60 mil
C
C
L18 0.1U_0402_10V7K
P
ERSTB
SOLATEB
I
L
ANWAKEB
D
VDD10
DDREG
V
R
EGOUT
ED1/GPIO
L
CKXTAL1
C
KXTAL2
VDD10
A
A
VDD33
R42790_0402_5% R42790_0402_5%
12
8111G@ESD@
8111G@ESD@
H
H
ESD@DL2
ESD@
SOP
SON
L
ED2
LED0
SET
R
ND
G
I/O2
GND
I/O1
I/O2
GND
I/O1
17
CIE_PRX_LANTX_P3
P
18
CIE_PRX_LANTX_N3
P
19
P
LT_RST_BUF#
20
21
22
23
24
25
26
27
28
29
30
31
32
33
EC_SWI# <36,9>
LAN_WAKE# <36>
3
LAN_MDI1-
2
1
LAN_MDI1+
3
LAN_MDI3-
2
1
LAN_MDI3+
SOLATE#
I
AN_WAKE#
L
LAN_X1
L
AN_X2
T
1PADT1PAD
2PADT2PAD
T
T
3PADT3PAD
L18 0.1U_0402_10V7K
+
LAN_VDD10
3V_LAN
+
LAN_VDD10
+
LAN_VDD10
+
+
3V_LAN
C
C
@PJ7
@
112
C
CL16 1000P_1206_2KV7KCL16 1000P_1206_2KV7K
1 2
RJ45_GND
+
3V_LAN
C
L7 close to Pin 11, CL8 close to Pin32
CL20 close to Pin23
1 2
L7 0.1U_0402_10V7K8111G@
L7 0.1U_0402_10V7K8111G@
C
C
1 2
C
C
L8 0.1U_0402_10V7K
L8 0.1U_0402_10V7K
1 2
L20 0.1U_0402_10V7K8106E@
L20 0.1U_0402_10V7K8106E@
C
C
K
eep de-coupling capacitors clo se to
RTL8111G/8106E within 200 mil
Y
Y
L1 25MHZ_20PF_7V25000016
12
CL17
CL17
220P_0603_50V8J
220P_0603_50V8J
L
AN_X1
1
CL9
CL9
27P_0402_50V8J
27P_0402_50V8J
NOGCLK@
NOGCLK@
2
RJ45_MIDI0+
RJ45_MIDI0-
RJ45_MIDI1+
RJ45_MIDI2+
RJ45_MIDI2-
RJ45_MIDI1-
RJ45_MIDI3+
RJ45_MIDI3-
L1 25MHZ_20PF_7V25000016
1
1
LANGND
GND
GND
2
4
JRJ45
JRJ45
1
PR1+
2
PR1-
3
PR2+
4
PR3+
5
PR3-
6
PR2-
7
PR4+
8
PR4-
SANTA_130456-491
SANTA_130456-491
@
@
@ESD@
@ESD@
DL4
DL4
CK0402101V05_0402-2
CK0402101V05_0402-2
1 2
3
3
NOGCLK@
NOGCLK@
27P_0402_50V8J
27P_0402_50V8J
NOGCLK@
NOGCLK@
GND
GND
D
L
AN_X2
1
CL10
CL10
2
9
10
2
3
2
3
1
1
DL5 @ESD@
DL5 @ESD@
L03ESDL5V0CG3-2_SOT-523-3
L03ESDL5V0CG3-2_SOT-523-3
E
For LAN function
12
1 3
D
D
2N7002KW_SOT323-3
2N7002KW_SOT323-3
A
LANCLK_REQ#
2
G
G
S
S
QL53
QL53
LANCLK_REQ#
RL24 10K_0402_5%RL24 10K_0402_5%
+3VS
LAN_EN<10,8>
CLKREQ_LAN#<8>
4 4
+3VS
12
1K_0402_5%
1K_0402_5%
RL8
RL8
@
@
ISOLATE#
RL9
RL9
15K_0402_5%
15K_0402_5%
1 2
RL433 0_0402_5%@RL433 0_0402_5%@
WOL_EN#
Sx Enable
Wake up
LOW
Sx Disable
Wake up
HIGH
B
WOL_EN# <36>
Compal Electronics, Inc.
+3V_LAN rising time (10%~90%) need > 1ms and <100ms.
LAN WOL LAN_EN ISOLATEB
S0 Sx S0 Sx
--------------------------------------------- 0 0 0 0 1 1
0 1 0 0 1 1
1 0 1 1 1 1
1 1 1 1 1 0*
*
S3: after SUSP# assert low over 100ms
S4/S5: after SYSON assert low over 100ms
C
For ESD, keep close to RJ45 Connector
Change back to connect to LANGND only
on 20130201
DL1
ESD@DL1
ESD@
2
LANGND
LANGND
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
3
YSLC05CH_SOT23-3
YSLC05CH_SOT23-3
1
Compal Secret Data
Compal Secret Data
D
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2012/04/19 2015/04/19
2012/04/19 2015/04/19
2012/04/19 2015/04/19
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
PCIe-LAN-RTL8105E
PCIe-LAN-RTL8105E
PCIe-LAN-RTL8105E
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
ZRMAA/ZEMAA
ZRMAA/ZEMAA
ZRMAA/ZEMAA
Date: Sheet of
Date: Sheet of
Date: Sheet of
E
32 55Friday, June 21, 2013
32 55Friday, June 21, 2013
32 55Friday, June 21, 2013
0.4
0.4
0.4
+
USB_VCCC
+
5VALW
BATT_CHG_LOW _LED#<36>
+3VL
+
4
SB4
@JSB4
@
J
30
29
28
27
26
TP_I2CSDA1
TP_I2CSCL1
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
3VS
PL<35>
PR<35>
RING2_L<35>
EXT_MIC_L<35>
NBA_PLUG#<35>
LID_SW#<36>
BATT_FULL_LED#<36>
PWR_SU SP_LED#<36>
WL_BT_LED #<36>
TP_DATA<36>
TP_CLK<36>
TP_INTR#<10,9>
32
3
G
0
ND
31
ND
9
G
2
2
8
2
7
26
2
5
4
2
2
3
2
2
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
ACES_51522-03001-P01
ACES_51522-03001-P01
5
lose to JSB4
C
1 2
R
R
44 0_0402_5%@EMI@
44 0_0402_5%@EMI@
R9
14@EMI@
R9
14@EMI@
L
D D
U
SB20_N2<11>
SB20_P2<11>
U
USB20_N3<11>
USB20_P3<11>
SB20_N2
U
U
SB20_P2
USB20_N3
USB20_P3
L
1
1
4
4
WCM- 2012-900T_0805
WCM- 2012-900T_0805
1 2
R45 0_0402_5%@EMI@R45 0_0402_5%@EMI@
1 2
R46 0_0402_5%@EMI@R46 0_0402_5%@EMI@
LR10
14@EMI@LR10
14@EMI@
1
1
4
4
WCM- 2012-900T_0805
WCM- 2012-900T_0805
1 2
R47 0_0402_5%@EMI@R47 0_0402_5%@EMI@
2
2
3
2
3
SB20_N2_L
U
U
SB20_P2_L
3
2
USB20_N3_L
USB20_P3_L
3
3
mall board Conn
S
C
lose to JSB5
1 2
R49 0_0402_5%@R 49 0_0402_5%@
R11
R11
L
L
4
U
SB20_N2
SB20_P2
U
USB20_N3
USB20_P3
4
1
1
WCM- 2012-900T_0805
WCM- 2012-900T_0805
1 2
R50 0_0402_5%@R 50 0_0402_5%@
1 2
R53 0_0402_5%@R 53 0_0402_5%@
LR12
4
4
1
1
WCM- 2012-900T_0805
WCM- 2012-900T_0805
1 2
R51 0_0402_5%@R 51 0_0402_5%@
15@EMI@
15@EMI@
15@EMI@LR12
15@EMI@
2
USB_VCCC
+
+5VALW
+
3VL
3VS
3
3
2
2
3
3
2
2
U
U
USB20_N3_L5
USB20_P3_L5
SB20_N2_L5
SB20_P2_L5
+
PL
PR
RING2_L
EXT_MIC_L
NBA_PLUG#
LID_SW#
BATT_FULL_LED#
BATT_CHG_LOW _LED#
PWR_S USP_LED#
WL_BT_LE D#
TP_DATA
TP_CLK
TP_INTR#
TP_I2CSDA1
TP_I2CSCL1
1
J
SB5
@JSB5
@
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
GND
3030GND
ACES_51522-03001-P01
ACES_51522-03001-P01
31
32
C C
USB_EN#2<36>
B B
SPK Conn.
A A
Left USB 2.0 x 1
2.0A
U13
U13
2
IN
3
IN
4
EN/ENB
1
GND
G547I2P81U_MSOP8
G547I2P81U_MSOP8
SA00003TV00
SA00003XM00
JSPK
JSPK
SPK_L1<35>
SPK_L2<35>
SPK_R1<35>
SPK_R2<35>
5
1
2
3
4
5
6
E&T_3802-F04N-01R
E&T_3802-F04N-01R
@
@
1 2
R471 0_0402_5%@R471 0_0402_5%@
1 2
R472 0_0402_5%@R472 0_0402_5%@
1 2
R473 0_0402_5%@R473 0_0402_5%@
1 2
R474 0_0402_5%@R474 0_0402_5%@
PM_SMBDATA <16,17,31,8>
PM_SMBCLK <16,17, 31,8>
PM_I2CSDA1 <10>
PM_I2CSCL1 <10>
NGFF SSD B Type connector
OUT
OUT
OUT
OCB
W=80mils
+USB_VCCC+5VALW
6
7
8
5
USB_OC#2 <10,11,36>
TP_I2CSDA1
TP_I2CSCL1
P/N:SP071212280
R29
R29
0_0402_5%
0_0402_5%
@
@
+3VS
2
DEVSLP1 <10>
0.4
0.4
33 55Friday, June 21, 2013
33 55Friday, June 21, 2013
33 55Friday, June 21, 2013
1
0.4
PJ8 @
PJ8 @
JUMP_43X79
JNGFF
JNGFF
T161 @T161 @
+3VS_NGFF
0.1U_0402_10V7K
0.1U_0402_10V7K
1
1
C5
C5
C4
C4
2
0.1U_0402_10V7K
0.1U_0402_10V7K
1
2
3
4
G1
G2
C6
C6
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4
1
2
SSD_DETECT#<10>
Close to JNGFF
1 2
SATA_PRX_C_DTX_P1<7>
SATA_PRX_C_DTX_N1<7>
SATA_PTX_DRX_N1<7>
SATA_PTX_DRX_P1<7>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
C546 0.01U_0402_25V7KC546 0.01U_0402_25V7K
1 2
C548 0.01U_0402_25V7KC548 0.01U_0402_25V7K
1 2
C545 0.01U_0402_25V7KC545 0.01U_0402_25V7K
1 2
C547 0.01U_0402_25V7KC547 0.01U_0402_25V7K
2012/04/19 2015/04/19
2012/04/19 2015/04/19
2012/04/19 2015/04/19
3
SATA_PRX_DTX_P1
SATA_PRX_DTX_N1
SATA_PTX_C_DRX_N1
SATA_PTX_C_DRX_P1
T164 @T164 @
T171 @T171 @
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
1
PRESENCE#
3
GND
5
GND
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
2
FULL_CARD_POWER_OFF#
USB_D+
USB_DGND
WWAN_DETECT#
WAKE_ON_WWAN#
DPR
GND
USB3.0-TXUSB3.0-TX+
GND
USB3.0-RXUSB3.0-RX+
GND
SATA-B+
SATA-BGND
SATA-ASATA-A+
GND
RESERVED1
RESERVED2
GND
ANTCTRL0
ANTCTRL1
ANTCTRL2
ANTCTRL3
RESET#
PCIE_DETECT
GND
GND
USB3_DETECT
PEG2
CONCR_213BAAA32FA @
CONCR_213BAAA32FA @
W_DISABLE1#
W_DISABLE2#
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
SIM_DETECT
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
2
+3VS_NGFF
3.3VAUX1
4
3.3VAUX2
6
8
10
LED#
12
GPIO_5
14
GPIO_6
16
GPIO_7
18
20
UIM_RFU
22
UIM-RESET
24
UIM-CLK
26
UIM-DATA
28
UIM-PWR
30
DEVSLP
32
GPIO_0
34
GPIO_1
36
GPIO_2
38
GPIO_3
40
GPIO_4
42
44
46
48
50
52
COEX3
54
COEX2
56
COEX1
58
60
SUSCLK
62
3.3VAUX3
64
3.3VAUX4
66
3.3VAUX5
68
PEG1
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size D ocument Number Rev
Size D ocument Number Rev
Size D ocument Number Rev
Compal Electronics, Inc.
NGFF SATA/S_B conn/SPK
NGFF SATA/S_B conn/SPK
NGFF SATA/S_B conn/SPK
JUMP_43X79
112
1 2
ZRMAA/ZEMAA
ZRMAA/ZEMAA
ZRMAA/ZEMAA
5
4
3
ight side USB 3.0 x 1 W/ Sleep&Charge
R
2
1
USB Sleep & Charge
5VALW
+
USB_VCCA
State table for TPS2546RTER
D D
CB1CB0
ILIM_SEL
1 110
1
1
C C
B B
1
1
!"#$%&'(&%)*+,-.%/011-
!"#$%&'(&%)*+,-.%/011-
!"#$%&'(&%)*+,-.%/011- !"#$%&'(&%)*+,-.%/011-
U3TXDP1<11>
U3TXDN1<11>
USB_EN#0<36>
1
1
USB20_P0<11>
USB20_N0<11>
U3RXDP1<11>
U3RXDN1<11>
1 2
C527 0.1U_0402_10V7KC527 0.1U_0402_10V7K
1 2
C529 0.1U_0402_10V7KC529 0.1U_0402_10V7K
2.0A
U15
U15
2
IN
3
IN
4
EN/ENB
1
GND
G547I2P81U_MSOP8
G547I2P81U_MSOP8
SA00003TV00
SA00003XM00
OCB
OUT
OUT
OUT
0
1
U3TXDP1_C
U3TXDN1_C
W=80mils
+USB_VCCB+5VALW
6
7
8
5
Mode
A
uto/Alternate
SDP
CDP
STATUSCB2
Auto-detection charger mode for Apple device(2A,1A).
Resistor dividers are connected to DP/DM. Including DCP
USB pass-through mode.DP/DM are connected to TDP/TDM
USB pass-through mode with CDP emulation.
DP/DM are connected to TDP/TDM
LR7
EMI@LR7
EMI@
3
3
2
2
DLW21HN900SQ2L_4P
DLW21HN900SQ2L_4P
L56
L56
1 2
DLW21SN670HQ2L_4P
DLW21SN670HQ2L_4P
L60
L60
1 2
DLW21SN670HQ2L_4P
DLW21SN670HQ2L_4P
USB_OC#0 <10,11,36>
4
1
EMI@
EMI@
EMI@
EMI@
22U_0603_6.3V6M
22U_0603_6.3V6M
4
1
34
34
USB20_P0_R
USB20_N0_R
U3RXDP1_L
U3RXDN1_L
U3TXDP1_C_L
U3TXDN1_C_L
+USB_VCCB
1
C532
C532
2
W=80mils
1
C535
C535
2
22U_0603_6.3V6M
22U_0603_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
1
2
1
C533
C533
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C534
C534
@
@
U
ILIM_SEL<36>
USB_CHG_EN<36>
EC_CB0<36>
EC_CB1<36>
EC_CB2<36>
Internal PU @ EC for ILIM_SEL, EC_CHG_CB[0..2]
U3RXDP2<11>
U3RXDN2<11>
U3TXDP2<11>
U3TXDN2<11>
U3TXDP2
U3TXDN2
1
@
@
0.1U_0402_10V7K
0.1U_0402_10V7K
2
SB_CHG_OC#<11,36,8>
1 2
C526 0.1U_0402_10V7KC526 0.1U_0402_10V7K
1 2
C528 0.1U_0402_10V7K
C528 0.1U_0402_10V7K
C
C
R8
R8
U3TXDP2_C
U3TXDN2_C
U3TXDP2_C_L
U3TXDN2_C_L
U3RXDP2_L
U3RXDN2_L
2
.5A
R2
R2
U
U
1
I
N
9
TATUS#
S
13
F
AULT#
4
ILIM_SEL
5
EN
6
CTL1
7
CTL2
8
CTL3
TPS2546RTER_QFN16_3X3
TPS2546RTER_QFN16_3X3
UR3
UR3
TPS2544RTER_QFN16_3X3
TPS2544RTER_QFN16_3X3
2544@
2544@
L71
EMI@L71
EMI@
1 2
EMI@
EMI@
@ESD@
@ESD@
34
34
6
7
8
9
DLW21SN670HQ2L_4P
DLW21SN670HQ2L_4P
L72
L72
1 2
DLW21SN670HQ2L_4P
DLW21SN670HQ2L_4P
D88
D88
8
8
3
5
4
2
1
TVWDF1004AD0_SLP2510P8-10-9
TVWDF1004AD0_SLP2510P8-10-9
2546R@
2546R@
O
UT
P_IN
D
D
M_IN
DM_OUT
DP_OUT
ILIM_LO
ILIM_HI
GND
T-PAD
U3RXDP2_L
U3RXDN2_L
U3TXDP2_C_L
U3TXDN2_C_L
U3TXDP2_C_L
U3TXDN2_C_L
U3RXDP2_L
U3RXDN2_L
W
=100milsW=100mils
12
10
U
SB20_P1_S
11
SB20_N1_S
U
2
3
15
ILIM_LO
16
ILIM_HI
14
17
+
lose to UR2 IN/OUT
C
USB20_N1 <11>
USB20_P1 <11>
12
RR16
RR16
12
RR14
RR14
20K_0402_1%
20K_0402_1%
20K_0402_1%
20K_0402_1%
LR8
EMI@LR8
EMI@
USB20_N1_S
USB20_P1_S USB20_P1_R
2
2
3
3
DLW21HN900SQ2L_4P
DLW21HN900SQ2L_4P
Sleep & Charge Port
W=100mils
+USB_VCCA
USB20_N1_R
USB20_P1_R
U3RXDN2_L
U3RXDP2_L
U3TXDN2_C_L
U3TXDP2_C_L
+
USB_VCCA
1
C
C
2
1
USB20_N1_R
1
4
4
JUSBF
1
VBUS
2
D-
3
D+
4
GND
5
StdA-SSRX-
6
StdA-SSRX+
7
GND-DRAIN
8
StdA-SSTX-
9
StdA-SSTX+
SINGA_2UB3914-000101F
SINGA_2UB3914-000101F
W
=100mils
C
C
C
C
R3
R3
R2
R2
1
1
R7
R7
2
22U_0603_6.3V6M
22U_0603_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
@JUSBF
@
10
GND
11
GND
12
GND
13
GND
1
R10
R10
C
C
@
@
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
JUSBR
+USB_VCCB
D87
@ESD@
D87
@ESD@
8
8
3
5
U3TXDP1_C_L
4
U3TXDN1_C_L
A A
U3RXDP1_L
U3RXDN1_L
2
1
TVWDF1004AD0_SLP2510P8-10-9
TVWDF1004AD0_SLP2510P8-10-9
5
6
7
8
9
U3TXDP1_C_L
U3TXDN1_C_L
U3RXDP1_L
U3RXDN1_L
USB20_N0_R
USB20_P0_R
U3RXDN1_L
U3RXDP1_L
U3TXDN1_C_L
U3TXDP1_C_L
1
VBUS
2
D-
3
D+
4
GND
5
StdA-SSRX-
6
StdA-SSRX+
7
GND-DRAIN
8
StdA-SSTX-
9
StdA-SSTX+
SINGA_2UB3914-000101F
SINGA_2UB3914-000101F
4
GND
GND
GND
GND
@JUSBR
@
10
11
12
13
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2012/04/19 2015/04/19
2012/04/19 2015/04/19
2012/04/19 2015/04/19
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
RUSB/S&C
RUSB/S&C
RUSB/S&C
ZRMAA/ZEMAA
ZRMAA/ZEMAA
ZRMAA/ZEMAA
1
34 55Friday, June 21, 2013
34 55Friday, June 21, 2013
34 55Friday, June 21, 2013
0.4
0.4
0.4
of
of
of
1
9
26
40
41
46
36
2
3
8
5
6
10
12
13
14
19
20
17
18
22
21
24
23
11
47
4
+
DVDD
+
DVDD
+
AVDD1
AVDD2
+
+
PVDD
PVDD
+
+
DVDD
F
or EMI reserve
NT_MIC_CLK_R
I
Z_SDIN0_HD_R
A
A
Z_BITCLK_HD
MONO_IN
SENSE_A
CA49
CA49
MIC2_R_C_L
MIC2_R_C_R
1 2
1 2
4.7K_0402_5%
4.7K_0402_5%
@
@
R
R
FBMA-10-100505-301T
FBMA-10-100505-301T
R
R
A67 33_0402_5%
A67 33_0402_5%
10U_0603_6.3V6M283@
10U_0603_6.3V6M283@
EC_MUTE# <36>
RA50
RA50
Reserve for solve noise issue
Internal AMP
EC_MUTE#
Hight
LOW
For EMI reserve
close to codec
Z_BITCLK_HD
A
A66
CAM_EMI@
A66
CAM_EMI@
12
CA49
CA49
10U_0603_6.3V6M
10U_0603_6.3V6M
233@
233@
Enable
Disable
A41
A41
R
R
10_0402_5% EMI@
10_0402_5% EMI@
INT_MIC_DATA <28>
Z_SDIN0_HD <7>
A
A
Z_SDOUT_HD <7>
AZ_BITCLK_HD <7>
AZ_SYNC_HD <7>
2
CA65
CA65
0.01U_0402_25V7K
0.01U_0402_25V7K
1
@ESD@
@ESD@
12
C
C
10P_0402_50V8J EMI@
10P_0402_50V8J EMI@
close to pin3
0_0402_5%283@
0_0402_5%283@
RA4
RA4
282@
282@
1 2
CA51 4.7U_0603_6.3V6K
CA51 4.7U_0603_6.3V6K
1 2
CA52 4.7U_0603_6.3V6K
CA52 4.7U_0603_6.3V6K
282@
282@
0_0402_5%283@
0_0402_5%283@
RA5
RA5
AZ_RST_HD# <7>
5
A1
A1
U
BN
BP
PVEE
J
A
H
DREF
C_VREF
POUT_L
16
29
30
31
15
28
32
33
35
37
34
27
39
43
42
44
45
48
21
25
38
49
U
M
ONO-OUT
IC2-VREFO
M
M
IC1-VREFO-R
IC1-VREFO-L
M
J
DREF
V
REF
POUT-L(PORT- I-L)
H
HPOUT-R(PORT -I-R)
BN
C
C
BP
PVEE
C
LDO1-CAP
LDO2-CAP
7
LDO3-CAP
SPK-OUT-LSPK-OUT-L+
SPK-OUT-RSPK-OUT-R+
SPDIF-OUT/GPIO2
4
DVSS
AVSS1
AVSS2
Thermal Pad
ALC282-CG_MQFN48_6X6
ALC282-CG_MQFN48_6X6
282@
282@
UA1
UA1
ALC233-CG MQFN 48P
ALC233-CG MQFN 48P
233@
233@
UA1
UA1
ALC283-CG MQFN 48P
ALC283-CG MQFN 48P
283@
283@
D
VDD
VDD-IO
D
VDD1
A
VDD2
A
VDD1
P
P
VDD2
C
PVDD
GPIO0/DMIC-DATA
PIO1/DMIC-CLK
G
S
DATA-IN
S
DATA-OUT
BCLK
SYNC
PCBEEP
Sense A
Sense B
MIC1-L(PORT-B-L)
MIC1-R(PORT-B-R)
MIC2-L(PORT-F-L)
MIC2-R(PORT-F-R)
LINE1-L(PORT-C-L )
LINE1-R(PORT-C- R)
LINE2-L(PORT-E-L )
LINE2-R(PORT-E-R )
RESETB
PDB
eserve for solv e bobo noise
R
C_MUTE_INT<36>
E
D D
C
C
CA20 10U_0603_6.3V6M
CA20 10U_0603_6.3V6M
CA21 10U_0603_6.3V6MCA21 10U_0603_6.3V6M
CA22 10U_0603_6.3V6MCA22 10U_0603_6.3V6M
close to pin, 1 0mil
1
12
CA12
CA12
0.1U_0402_10V7K
0.1U_0402_10V7K
2
MIC2_VREFO
+
A3
A3
R
R
21
E
C_MUTE_INT_R
@
@
0_0402_5%
0_0402_5%
R
R
H
P_L
HP_R HPOUT_R
A24 2.2U_0603_10V6K
A24 2.2U_0603_10V6K
C
C
A23 2.2U_0603_10V6K
A23 2.2U_0603_10V6K
AC_VREF
CA25
CA25
2.2U_0603_10V6K
2.2U_0603_10V6K
12
A38 20K_0402_1%
A38 20K_0402_1%
R
R
A20 75_0402_1%
A20 75_0402_1%
RA21 75_0402_1%RA21 75_0402_1%
12
12
12
12
12
RA2
RA2
0_0402_5%
0_0402_5%
283@
283@
RA2
0_0402_5%
0_0402_5%
DGND
282@RA2
282@
C
C
C
LDO1-CAP
LDO2-CAP
LDO3-CAP
SPKLSPKL+
SPKRSPKR+
COMBO_GPI
AGND
C C
3
R
R
A27
A27
1
2
2
A39
A39
C
C
10U_0603_6.3V6M
10U_0603_6.3V6M
1
+AVDD2
1
CA41
CA41
10U_0603_6.3V6M
10U_0603_6.3V6M
2
1
CA43
CA43
10U_0603_6.3V6M
10U_0603_6.3V6M
2
1
2
1 2
0_0603_5%
0_0603_5%
2
C
C
A36
A36
1
10U_0603_6.3V6M
10U_0603_6.3V6M
R
R
A28
A28
1 2
0_0603_5%
0_0603_5%
RA65
RA65
1 2
0_0603_5%
0_0603_5%
RA68
RA68
1 2
0_0603_5%
0_0603_5%
+
PVDD
1
C
C
A34
A34
0.1U_0402_10V7K
0.1U_0402_10V7K
RA4
RA4
0_0402_5%
0_0402_5%
233@
233@
RING2
MIC2_LINE1_R_L
MIC2_LINE1_R_R
EXT_MIC
0.1U_0402_16V4Z
0.1U_0402_16V4Z
close to pin1
close to pin41
0.1U_0402_10V7K
0.1U_0402_10V7K
close to pin26
CA8
CA8
10U_0603_6.3V6M
10U_0603_6.3V6M
1 2
A53
A53
I
NT_MIC_CLK <28>
EMI@CA 61
EMI@
CA61
220P_0402_50V7K
220P_0402_50V7K
RA5
RA5
0_0402_5%
0_0402_5%
233@
233@
close to pin36
0.1U_0402_10V7K
0.1U_0402_10V7K
lose to pin46
c
A40
A40
C
C
+DVDD
1
2
CA7
CA7
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CA11
CA11
1
2
2
A38
A38
C
C
+AVDD1
1
2
close to pin9
2
5VS
+
+5VS
+1.5VS
+3VS
1 2
RA45 0_0603_5%
RA45 0_0603_5%
1 2
RA46 0_0603_5%
RA46 0_0603_5%
1 2
RA42 0_0603_5%
RA42 0_0603_5%
1 2
RA32 0_0603_5%
RA32 0_0603_5%
1 2
RA31 0_0603_5%
RA31 0_0603_5%
@
@
@
@
@
@
@EMI@
@EMI@
@EMI@
@EMI@
1
3VL
+
R
R
A8
A8
100K_0402_5%
100K_0402_5%
233@
233@
R
R
A8
A8
100K_0402_5%
100K_0402_5%
283@
A9
A9
R
R
10K_0402_5%
10K_0402_5%
233@
233@
283@
283@
1 2
Z_RST_HD#
A
LT_RST_BUF#<31,32,9>
P
R
R
A9
A9
10K_0402_5%
10K_0402_5%
@
@
1 2
A7
A7
R
R
10K_0402_5%
10K_0402_5%
RA7
RA7
10K_0402_5%
10K_0402_5%
@
@
283@
1 2
3
Q
Q
5539B
5539B
5
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
4
Near small board connector
Q
Q
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
61
233@
233@
A1A
A1A
Q
Q
2
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
283@
283@
3
QA1B
QA1B
5
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
283@
283@
4
QA1B
QA1B
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
233@
233@
A1A
A1A
E
XT_MIC
RING2
CA76
CA76
1
2
283@
283@
100P_0402_50V8J
100P_0402_50V8J
Combo Jack
+MIC2_VREFO
MIC2_LINE1_R_R
MIC2_LINE1_R_L
COMBO_GPI
10U_0603_6.3V6M
10U_0603_6.3V6M
HP_R
HP_L
RA6
RA6
0_0402_5%
0_0402_5%
282@
282@
CA48
CA48
RING2_L <33>
RA69 2.2K_0402_5%RA69 2.2K_0402_5%
1 2
1 2
282@
282@
RA35 1K_0402_5%
RA35 1K_0402_5%
RA71
RA71
1 2
1
22K_0402_5%
22K_0402_5%
282@
282@
2
282@
282@
Change material
to SM01000GK00
EMI@
EMI@
EXT_MIC
282@
282@
if need EMI material
will use SM01000GK00
1 2
@
@
1 2
@
@
1 2
LA8
LA8
SBY100505T-470Y-N_2P
SBY100505T-470Y-N_2P
12
RA70
RA70
22K_0402_5%
22K_0402_5%
LA7
LA7
0_0402_5%
0_0402_5%
LA6
LA6
0_0402_5%
0_0402_5%
1
CA74
CA74
2
@EMI@
@EMI@
100P_0402_50V8J
100P_0402_50V8J
EXT_MIC
EXT_MIC_L
RING2
EXT_MIC_L <33>
1
2
CA69
CA69
100P_0402_50V8J
100P_0402_50V8J
PR <33>
1
CA75
CA75
2
@EMI@
@EMI@
100P_0402_50V8J
100P_0402_50V8J
PL <33>
need 40mil
RA5
RA4
LA8
Near small board connector
CA69
RING2_L
LA9
CA76
RA6
Beep sound
PCI Beep
PCH_SPKR<10>
B B
IF need cost down and don't care common design
RA63 change to 1K
RA62 change to reserve
CA71
CA71
1 2
0.1U_0402_10V7K
0.1U_0402_10V7K
CA27
CA27
100P_0402_50V8J
100P_0402_50V8J
1 2
Codec Signals
PORT-I (PIN 32, 33)
PORT-B (PIN 21, 22)
PORT-C (PIN 23, 24)
(PIN 48)
For better sound
by customer request
Sense Pin
SENSE A
RA63
RA63
1 2
47K_0402_5%
47K_0402_5%
RA62
RA62
4.7K_0402_5%
4.7K_0402_5%
Impedance
39.2K
20K
10K
5.1K
@
@
MONO_IN
Function
Headphone out
Ext. MIC
39.2K PORT-E (PIN 14, 15)
SENSE B PORT-F (PIN 16, 17)
20K
10K
PORT-H (PIN 20)
Need connector list,
check normal close or open
apple or nokia
A A
SPK
SPKL+
SPKL-
SPKR+
SPKR-
+MIC2_VREFO
30mil
For EMI reserve
close to codec
1 2
@
@
RA11 0_0603_5%
RA11 0_0603_5%
1 2
@
@
RA12 0_0603_5%
RA12 0_0603_5%
1000P_0402_50V7K
1000P_0402_50V7K
1 2
@
@
RA13 0_0603_5%
RA13 0_0603_5%
1 2
@
@
RA14 0_0603_5%
RA14 0_0603_5%
@EMI@
@EMI@
1000P_0402_50V7K
1000P_0402_50V7K
RA72
RA72
2.2K_0402_5%
2.2K_0402_5%
233@
233@
RA72 2.2K_0402_5%283@RA72 2.2K_0402_5%283@
1 2
RING2
CA47
CA47
@EMI@
@EMI@
CA42
CA42
1
2
1
2
1
CA46
CA46
1000P_0402_50V7K
1000P_0402_50V7K
2
@EMI@
@EMI@
1
@EMI@
@EMI@
CA45
CA45
1000P_0402_50V7K
1000P_0402_50V7K
2
LA9
LA9
233/283 only
233@EMI@
233@EMI@
1 2
SBY100505T-470Y-N_2P
SBY100505T-470Y-N_2P
CA76
CA76
100P_0402_50V8J
100P_0402_50V8J
233@
233@
SPK_L1 <33>
SPK_L2 <33>
SPK_R1 <33>
SPK_R2 <33>
place close to chip
NBA_PLUG#<33>
RA61 39.2K_0402_1%RA61 39.2K_0402_1%
for Combo Jack normal Open
5
4
SENSE_A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2012/04/19 2015/04/19
2012/04/19 2015/04/19
2012/04/19 2015/04/19
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
ALC282_233_283
ALC282_233_283
ALC282_233_283
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
ZRMAA/ZEMAA
ZRMAA/ZEMAA
ZRMAA/ZEMAA
1
of
35 55Fri day, June 21, 2013
of
35 55Fri day, June 21, 2013
of
35 55Fri day, June 21, 2013
0.4
0.4
0.4
0.1U_0402_10V7K
0.1U_0402_10V7K
1
@
@
2
CLK_PCI_EC
PLT_RST#
EC_RST#
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
E51_TXD
E51_RXD
12
@
@
RB22
RB22
B
1
B5
B5
C
C
2
1
2
3
4
5
7
8
10
12
13
37
20
38
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
77
78
79
80
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
122
123
1
CB16
CB16
20P_0402_50V8
20P_0402_50V8
@
@
2
3VL
+
U
U
B1
B1
ATEA20/GPIO00
G
BRST#/GPIO01
K
S
ERIRQ
L
PC_FRAME#
PC_AD3
L
LPC_AD2
LPC_AD1
LPC & MISC
LPC & MISC
LPC_AD0
CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25
KSO6/GPIO26
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A
XCLKI/GPIO5D
XCLKO/GPIO5E
Int. K/B
Int. K/B
Matrix
Matrix
9
EC_VDD/VCC
PS2 Interface
PS2 Interface
SM Bus
SM Bus
Voltage Comparator Pins FOR 9012 A3
VCIN0 pin109
VCIN1 pin102
VCOUT0 pin104
VCOUT1 pin103
B
>1.2V <1.2V
HIGH
(default)
HIGH
LOW
(default)
+
111
33
22
96
125
EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
PWM Output
PWM Output
AD Input
AD Input
DA Output
DA Output
CPU1.5V_S3_GATE/GPXIOA00
SPI Device Interface
SPI Device Interface
SPI Flash ROM
SPI Flash ROM
BATT_CHG_LED#/GPIO52
GPIO
GPIO
BATT_LOW_LED#/GPIO55
H_PROCHOT#_EC/GPXIOA06
GPO
GPO
GPIO
GPIO
PCH_APWROK/GPXIOA10
GPI
GPI
GND/GND
GND/GND
GND/GND
GND/GND
GND0
11
24
35
94
113
LOW
3VL
B3
B3
C
C
0.1U_0402_10V7K
0.1U_0402_10V7K
1 2
67
EEP#/GPIO10
B
EC_VDD/AVCC
A
COFF/GPIO13
BATT_TEMP/GPIO38
ADP_I/GPIO3A
IMON/GPIO43
DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F
EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F
WOL_EN/GPXIOA01
ME_EN/GPXIOA02
VCIN0_PH/GPXIOD00
SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A
ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59
EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
VCOUT0_PH/GPXIOA07
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
SA_PGOOD/GPXIOA11
AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
PECI_KB9012/GPXIOD07
AGND/AGND
KB9012QF-A4_LQFP128_14X14
KB9012QF-A4_LQFP128_14X14
69
9012@
9012@
A
0.1U_0402_10V7K
0.1U_0402_10V7K
1
1
B2
2
B_RST#<10>
K
L
PC_FRAME#<8 >
CLK_PCI_EC<8>
WOWL_EN#<38>
EC_SMB_CK1<40,41>
EC_SMB_DA1<40,41>
EC_SMB_CK2<18,8>
EC_SMB_DA2<18,8>
PM_SLP_S3#<9>
PM_SLP_S5#<9>
USB_OC#2<10,11,33>
USB_CHG_OC#<11,34,8>
USB_CHG_EN<34>
USB_EN#2<33>
FAN_SPEED1<7>
PCH_PWROK<9>
NUM_LED#<37>
EC_MUTE_INT<35>
E51_TXD
E51_RXD
ERIRQ<10>
S
PC_AD3<8>
L
LPC_AD2<8>
LPC_AD1<8>
LPC_AD0<8>
PLT_RST#<9>
EC_SCI#<10>
EC_SMI#<7>
KB_LED<37>
WL_OFF#<31>
E51_TXD<31>
E51_RXD<31>
BT_ON<31>
B2
C
C
@
@
B4
B4
C
C
2
0.1U_0402_10V7K
0.1U_0402_10V7K
CLK_EC_R
100K_0402_5%
100K_0402_5%
+3VS
B1
B1
C
or EMI
F
LK_PCI_EC
C
12
R
R
B4
B4
10_0402_5%
10_0402_5%
@EMI@
1 1
2 2
+3VL
+3VS
3 3
Signal pull high is default status (ROM only mode).
If signal pull low, EC will send translator code to chip.(EP mode)
4 4
@EMI@
C
C
22P_0402_50V8J
22P_0402_50V8J
@EMI@
@EMI@
+3VL
RB2
RB2
47K_0402_5%
47K_0402_5%
1 2
1 2
CB12 0.1U_0402_10V7KCB12 0.1U_0402_10V7K
+3VALW_PCH
1 2
@
@
RB12 10K_0402_5%
RB12 10K_0402_5%
RPB1
RPB1
1 8
2 7
3 6
4 5
2.2K_8P4R_5%
2.2K_8P4R_5%
RB27
RB27
100K_0402_5%
100K_0402_5%
1 2
EC_MUTE_INT
RB28
RB28
4.7K_0402_5%
4.7K_0402_5%
1 2
LVDS@
LVDS@
TRANS_SEL
@
@
B11
B11
+3VL
1
2
ILIM_SEL
RB26
RB26
10K_0402_5%
10K_0402_5%
1 2
RB25
RB25
10K_0402_5%
10K_0402_5%
1 2
EC_RST#
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
E51_TXD
CB13 0.1U_0402_10V7K
CB13 0.1U_0402_10V7K
KSI[0..7]<37>
KSO[0..17]<37>
POK<42,9>
For Translator select
A
C
0.1U_0402_10V7K
0.1U_0402_10V7K
ESD@
ESD@
1 2
PLT_RST#
KSI[0..7]
KSO[0..17]
1 2
RB7 0_0402_5%@RB7 0_0402_5%@
EC DEBUG port
@
@
JDB
JDB
1
1
2
2
3
3
4
4
5
G1
6
G2
E&T_3802-F04N-01R
E&T_3802-F04N-01R
C
21
PIO0F
G
23
26
G
PIO12
27
63
BATT_PRES
64
GPIO39
65
66
GPIO3B
75
GPIO42
76
68
70
885_EC_ON
71
CB0_WAKE#
72
83
84
85
EC_SMB_CK3
86
EC_SMB_DA3
87
TP_CLK
88
TP_DATA
97
98
GPS_DOWN#
99
109
119
120
126
128
73
WLAN_WAKE #
74
89
ILIM_SELKSO17
90
91
92
93
95
SYSON
121
127
100
101
102
103
H_PROCHOT#_EC
104
VCOUT0_PH_L
105
106
107
108
110
ACIN
112
EC_ON_R
114
115
LID_SW#
116
SUSP#
117
GPXIOD06
V18R
UB1
UB1
NPCE885NB0DX LQFP 128P
NPCE885NB0DX LQFP 128P
885@
885@
EC_ON_R
885_EC_ON
+VTT_EC
118
EC_PECI
124
+EC_V18R
9012@
9012@
1 2
RB36 0_0402_5%
RB36 0_0402_5%
1 3
D
D
TRANS_SEL
1
2
S
S
QB2
QB2
2N7002K_SOT23-3
2N7002K_SOT23-3
G
G
2
L_BT_LED# <33>
W
SB_EN#0 <34>
U
C_CB2 <34>
E
C
LK_REQ_GC6# <18>
BATT_PRES <40>
USB_OC#0 <10,11,34>
ADP_I <40,41>
ADP_V < 41>
EC_ENBKL <27,28>
DFAN1 <7>
VCCST_PWRGD < 12,44>
EC_MUTE# <35>
PM_SLP_S4# <9>
EC_SMB_CK3 <27>
EC_SMB_DA3 <27>
TP_CLK <33>
TP_DATA <33>
ACIN <41,9>
ON/OFFBTN# <37>
LID_SW# <33>
SUSP# < 38,44,45>
CB15
CB15
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
2
885@
885@
Reserve this signal to EC by SW demand
2011/10/18a
EC_CB1 <34>
GPS_DOWN# <18>
PWRME_CTRL <7>
VCIN0_PH <40>
EC_SDIO <8>
EC_SDI <8>
EC_SCK <8>
EC_CS0# <8>
WLAN_WAKE # <31>
WOL_EN# <32>
ILIM_SEL <34>
BATT_FULL_LED# <33>
CAPS_LED# <37>
PWR_SUSP_LED# <3 3>
BATT_CHG_LOW_LED# <33>
SYSON <43>
VCCST_PG_EC <12,9>
FB_CLAMP < 18,19,22>
PCH_RSMRST# <9>
EC_LID_OUT# <10>
PROCHOT_IN <40>
BKOFF# <28>
PBTN_OUT# <9>
PCH_PWR_EN <38,45>
EC_SWI# <32,9>
RB3 0_0402_5%
RB3 0_0402_5%
RB19 43_0402_5%RB19 43_0402_5%
885@
885@
12
RB20 330K_0402_5%
RB20 330K_0402_5%
1U_0402_6.3V6K
1U_0402_6.3V6K
CB50
CB50
@
@
RB24
885@RB2 4
885@
12
10K_0402_5%
10K_0402_5%
CB0_WAKE#
PROCHOT_IN connect
to power portion (9012 only)
1 2
885@
885@
1 2
EC_ON <42>
D
V
R_HOT#<46>
RR8 0_0402 _5%
RR8 0_0402 _5%
12
@
@
12
@
@
RR9 0_0402_5%
RR9 0_0402_5%
VCIN0_PH connec t to
power portion ( 9012 only)
+1.05VS_VTT
H_PECI <5>
+3VL
1 2
R
B1 0_0402_5%@RB1 0_0402_5%@
_PROCHOT#_EC
H
LAN_WAKE# <32>
EC_CB0 <34>
TP_CLK
TP_DATA
EC_SMB_CK3
EC_SMB_DA3
SYSON
SUSP#
VCOUT0_PH_L
VCOUT0_PH connect to power portion (9012 only)
For KB9012 EC_ON low pulse work around
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2012/04/19 2015/04/19
2012/04/19 2015/04/19
2012/04/19 2015/04/19
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Date: Sheet
Date: Sheet
D
Date: Sheet
E
H
13
D
D
2
G
G
S
S
ATT_PRES
B
A
CIN
H_PROCHOT#_EC
LID_SW#
WLAN_WAKE #
RB34 0_0402_5%
RB34 0_0402_5%
Q
Q
2N7002K_SOT23-3
2N7002K_SOT23-3
RB8 4.7K_0402_5%RB8 4.7K_0402_5%
RB9 4.7K_0402_5%RB9 4.7K_0402_5%
RB15 2.2K_0402_5%RB15 2.2K_0402_5%
RB16 2.2K_0402_5%RB16 2.2K_0402_5%
RB10 4.7K_0402_5%RB10 4.7K_0402_5%
RB21 10K_0402_5%RB21 10K_0402_5%
1 2
1
B1
B1
2
1 2
C
B9 10 0P_0402_50V8J@CB9 10 0P_0402_50V8J@
1 2
CB10 100P_0402_50V8JCB10 100 P_0402_50V8J
1 2
@
@
RB6 10K_0402_5%
RB6 10K_0402_5%
1 2
RB35 47K_0402_5%RB35 47K_0402_5%
1 2
RB37 47K_0402_5%RB37 47K_0402_5%
1 2
1 2
1 2
1 2
1 2
1 2
@
@
C
C
B8
B8
47P_0402_50V8J
47P_0402_50V8J
+3VS
+3VL
+3VS
_PROCHOT# <5>
VS_ON <42>
Close to EC
ESD@
ESD@
1 2
SUSP#
CB14 180P_0402_50V8J
CB14 180P_0402_50V8J
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Compal Electronics, Inc.
LPC-EC-KB9012&930
LPC-EC-KB9012&930
LPC-EC-KB9012&930
Friday, June 21, 2013
Friday, June 21, 2013
Friday, June 21, 2013
E
of
36 55
of
36 55
of
36 55
0.4
0.4
0.4
5
Power Button
15@
15@
TJG-533-V-T/R_6 P
TJG-533-V-T/R_6 P
3
1
2
D D
4
5
14@
14@
TJG-533-V-T/R_6 P
TJG-533-V-T/R_6 P
3
4
SW3
SW3
5
6
W2
W2
S
S
6
1
2
3VL
+
R
R
100K_04 02_5%
100K_04 02_5%
1 2
2
1
469
469
O
N/OFFBTN#
ESD@CH 13
ESD@
CH13
0.1U_0402_10V7K
0.1U_0402_10V7K
O
N/OFFBTN# <3 6>
4
P
OWER LED
5VS
+
5
15@R5
15@
R
390_040 2_5%
390_040 2_5%
1 2
7
14@R7
14@
R
390_040 2_5%
390_040 2_5%
1 2
R9
R9
390_040 2_5%
390_040 2_5%
1 2
3
6
6
D
D
2 1
HT-F196BP5_ WHITE
HT-F196BP5_ WHITE
7
D
2 1
HT-F196BP5_ WHITE
HT-F196BP5_ WHITE
D8
D8
2 1
HT-F196BP5_ WHITE
HT-F196BP5_ WHITE
2
attery Reset
B
15@
15@
14@D7
14@
1
W4
W4
S
S
TJG-533-V-T/R_6 P
TJG-533-V-T/R_6 P
3
1
2
NLDO<42>
E
4
5
6
Keyboard LED
Q193
Q193
KBL@
AO3413_ SOT23
AO3413_ SOT23
S
S
12
G
G
13
D
D
Q194
Q194
2N7002K W_SOT323-3
2N7002K W_SOT323-3
KBL@
KBL@
S
S
12
KBL@
D
D
13
+5VS_LE D
2
CAPS_LE D#
+3VS_CAP
KSI1
KSI6
KSI5
KSI0
KSI4
10
KSI3
11
KSI2
12
KSI7
13
KSO15
14
KSO12
15
KSO11
16
KSO10
17
KSO9
18
KSO8
19
KSO13
20
KSO7
21
KSO6
22
KSO14
23
KSO5
24
KSO3
25
KSO4
26
KSO0
27
KSO1
28
KSO2
29
30
31
KSO17
32
33
KSO16
34
+3VS_NUM
CVILU_CF1 7341U0R0-NH
CVILU_CF1 7341U0R0-NH
+5VS
R475
R475
10K_040 2_5%
10K_040 2_5%
KBL@
+3VS
KSI[0..7]
KBL@
2
G
G
NUM_LED#<36>
R480 3 00_0402_5 %R480 300_040 2_5%
KSI[0..7 ] <36>
KSO[0..1 7] <36>
C C
KB_LED<36 >
14 " KEYBOARD CONN.
JKB4
JKB4
1
1
2
2
CAPS_LE D#<36>
+3VS
B B
R479 300 _0402_5%R479 300_0402_ 5%
12
+3VS_CAP
KSI1
KSI6
KSI5
KSI0
KSI4
KSI3
KSI2
KSI7
KSO15
KSO12
KSO11
KSO10
KSO9
KSO8
KSO13
KSO7
KSO6
KSO14
KSO5
KSO3
KSO4
KSO0
KSO1
KSO2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
GND1
36
GND2
CVILU_CF1 7341U0R0-NH
CVILU_CF1 7341U0R0-NH
@
@
15" KEYBOARD CONN.
KSO[0..1 7]
ACES_50 578-0040N-0 01
ACES_50 578-0040N-0 01
JKB5
JKB5
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
GND1
36
GND2
@
@
JBLG@
JBLG@
1
1
2
2
3
3
4
4
GND
GND
+5VS_LE D
5
6
Screw Hole
H1
H1
H_4P6
H_4P6
@
@
1
H6
H6
H_3P0
H_3P0
@
@
1
ISPD
ZZZ
ZZZ
PCB LA-A4 81P
PCB LA-A4 81P
H2
H2
H_4P6x4P2
H_4P6x4P2
@
@
1
H3
H_4P2
H_4P2
@
@
1
H4
H4
1
H3
PTH
H8
H8
H_5P2
H_5P2
@
@
1
H13
H13
H7
H7
H_3P5
H_3P5
@
@
1
H10
H9
H10
H9
H_3P0
H_3P0
@
@
1
H_6P5
H_4P1
H_6P5
H_4P1
@
@
@
@
1
1
PCB Fedical Mark PAD
FD3@FD3
FD2@FD2
FD1@FD1
@
@
1
FD4@FD4
@
@
1
1
1
VGACPU WLAN standoff
H5
H_3P2
H_3P2
@
@
H5
H_3P2
H_3P2
@
@
1
H29
H29
1
NPTH
H18
H11
H11
H_6P5
H_6P5
@
@
1
H18
H17
H17
H_3P0x2P5 N
H_3P0x2P5 N
H_2P5N
H_2P5N
@
@
@
@
1
1
H19
H19
H_3P5x3P0 N
H_3P5x3P0 N
@
@
1
GPU
H_3P3
H_3P3
@
@
H30
H30
H_3P2
H_3P2
@
@
1
H20
H20
H_2P8N
H_2P8N
@
@
1
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
2012/04/19 2015/04/19
2012/04/19 2015/04/19
2012/04/19 2015/04/19
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Title
Title
Title
Size Documen t Number Rev
Size Documen t Number Rev
Size Documen t Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
TP/ISPD/KB/Screw
TP/ISPD/KB/Screw
TP/ISPD/KB/Screw
ZRMAA/ZEMAA
ZRMAA/ZEMAA
ZRMAA/ZEMAA
Friday, June 21, 2013
Friday, June 21, 2013
Friday, June 21, 2013
1
of
37 55
of
37 55
of
37 55
0.4
0.4
0.4
A
V
3VALW TO +3VS
+
5VALW
+
IN 5V and 3.3V (VBIAS=5V),IMAX (per channel)=6A,Rds=18mohm
+5VALW TO +5VS
537
537
C
C
Load Switch
1 1
1U_0402_6.3V6K
1U_0402_6.3V6K
1
@
@
2
+
3VALW
@C542
@
1
2
+
5VALW
542
C
1U_0402_6.3V6K
1U_0402_6.3V6K
S
S
USP#
USP#
B
U
U
3
3
1
V
V
OUT1
IN1
2
3
4
5
6
7
OUT1
IN1
V
V
C
O
N1
G
V
ND
BIAS
O
C
N2
VIN2
VOUT2
VIN2
VOUT2
PAD
G
TPS22966DPUR_SON14_2X3
TPS22966DPUR_SON14_2X3
P
P
J3
J3
@
14
5VS_LS
+
13
12
T1
11
10
T2
9
8
15
538 180P_0402_50V8J
538 180P_0402_50V8J
C
C
1 2
C
C
540 330P_0402_50V7K
540 330P_0402_50V7K
1 2
+3VS_LS
1 2
1 2
PAD-OPEN 4x4m
PAD-OPEN 4x4m
J5
J5
P
P
@
@
PAD-OPEN 4x4m
PAD-OPEN 4x4m
@
+
3VS
1
C
C
541
541
@
@
2
0.1U_0402_10V7K
0.1U_0402_10V7K
C
5VS
+
1
539
539
C
C
0.1U_0402_10V7K
0.1U_0402_10V7K
@
@
2
+3VALW TO +3V_WLAN
for WOWL
W
OWL_EN#<36>
100K_0402_5%
100K_0402_5%
D
WOWL@
WOWL@
R
R
E
+
3VALW
+
12
M4
M4
R
R
10K_0402_5%
10K_0402_5%
M3
M3
R
R
1 2
47K_0402_5%
47K_0402_5%
WOWL@
WOWL@
12
M2
M2
WOWL@
WOWL@
2
M4
M4
C
C
0.1U_0402_10V7K
0.1U_0402_10V7K
1
2
WOWL@
WOWL@
M5
M5
C
C
0.01U_0402_25V7K
0.01U_0402_25V7K
1
3VALW
Vgs=-4.5V,Id=3A,Rds<97mohm
S
S
G
G
2
AO3413_SOT23
AO3413_SOT23
Q
Q
M1
M1
D
D
1 3
WOWL@
WOWL@
Need mount RM1 if system
don't support WOWL
+
3V_WLAN
M1
M1
R
R
1 2
0_0603_5%
0_0603_5%
NOWOWL@
NOWOWL@
+
3VS
+1.5VALW to +1.5VS
+3VL
+1.5VALW +1.5VS
V_GS(th) : -0.55 V
PJ333
@ PJ333
Avoid leakage
2 2
C43
C43
0.1U_0402_16V7K
0.1U_0402_16V7K
R153
1K_0402_5%
1K_0402_5%
SUSP
@
1
221
JUMP_43X39
JUMP_43X39
D
S
D
S
13
@
@
Q8
Q8
1
G
G
AO3413_SOT23
AO3413_SOT23
@
@
2
2
@R153
@
12
@
@
C53
C53
0.01U_0402_25V7K
0.01U_0402_25V7K
PCH_PWR_EN<36,45>
+5VALW
1 2
SUSP
61
SUSP#<36,44,45>
2
12
R483
885@
R483
885@
100K_0402_5%
100K_0402_5%
R485
R485
100K_0402_5%
100K_0402_5%
Q5539A
Q5539A
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
+5VALW
12
R482
R482
100K_0402_5%
100K_0402_5%
PCH_PWR_EN#
61
Q195A
Q195A
2
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
+0.675VS +1.05VS_VTT
R486
R486
22_0805_5%
22_0805_5%
1 2
13
D
D
Q189
Q189
2
SUSP
G
G
S
2N7002KW_SOT323-3
S
2N7002KW_SOT323-3
2N7002KW_SOT323-3
2N7002KW_SOT323-3
Q60
Q60
2
G
G
PCH_PWR_EN# <13>
1 2
13
D
D
R487
R487
470_0805_5%
470_0805_5%
S
S
3 3
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2012/04/19 2015/04/19
2012/04/19 2015/04/19
2012/04/19 2015/04/19
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
DC-DC INTERFACE
DC-DC INTERFACE
DC-DC INTERFACE
ZRMAA/ZEMAA
ZRMAA/ZEMAA
ZRMAA/ZEMAA
Friday, June 21, 2013
Friday, June 21, 2013
Friday, June 21, 2013
E
of
38 55
of
38 55
of
38 55
0.4
0.4
0.4
L101
P
PL102
B
V
IN
12
EMI@ PC101
EMI@
100P_0603_50V8
100P_0603_50V8
PC101
12
PC104
EMI@ PC104
EMI@
1000P_0603_50V7K
1000P_0603_50V7K
A
O
ther component (37.1)
C_IN
D
A51 need add fuse
P
P
F1
F1
7A_32V_S1206-H-7.0A
7A_32V_S1206-H-7.0A
21
1 1
JP1
@PJP1
@
P
ACES_50299-00401-001
ACES_50299-00401-001
1
1
2
2
3
3
4
4
C_IN_S1
D
E
MI Part (47.1)
12
PC102
EMI@ PC102
EMI@
1000P_0603_50V7K
1000P_0603_50V7K
EMI@PL101
EMI@
FBMA-L11-201209-121LMA50T_0805
FBMA-L11-201209-121LMA50T_0805
1 2
1 2
EMI@ PL102
EMI@
FBMA-L11-201209-121LMA50T_0805
FBMA-L11-201209-121LMA50T_0805
12
PC103
EMI@ PC103
EMI@
100P_0603_50V8
100P_0603_50V8
C
D
2 2
12
+
For ML1220 RTC (38.2)
PR101
PR101
560_0603_5%
560_0603_5%
1 2
PBJ101
PBJ101
ML1220T13RE
ML1220T13RE
@
@
+RTC
+RTC_R
PR102
PR102
560_0603_5%
560_0603_5%
1 2
+RTCBATT
-
3 3
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
C
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DCIN
DCIN
DCIN
ZRMAA
D
39 55
39 55
39 55
0.4
0.4
0.4
A
B
C
D
@
1 1
@
JP2
JP2
P
P
10
ND
G
9
G
ND
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
ACES_50458-00801-001
ACES_50458-00801-001
Other component (37.1)
F2
F2
P
P
10A_125V_TR2/6125FF10-R
ATT_S1
B
BATT_P5
EC_SMDA
EC_SMCA
10A_125V_TR2/6125FF10-R
21
12
PR14
PR14
1K_0402_1%
1K_0402_1%
EMI Part (47.1)
MB
V
FBMA-L11-201209-121LMA50T_0805
FBMA-L11-201209-121LMA50T_0805
FBMA-L11-201209-121LMA50T_0805
FBMA-L11-201209-121LMA50T_0805
12
EMI@
EMI@
1000P_0402_50V7K
1000P_0402_50V7K
PC7
PC7
EMI@PL2
EMI@
P
1 2
1 2
PL3
EMI@ PL3
EMI@
L2
ATT+
B
12
PC8
EMI@
PC8
EMI@
0.01U_0402_25V7K
0.01U_0402_25V7K
+3VL
12
PR16
PR16
6.49K_0402_1%
6.49K_0402_1%
12
PR19
PR21
PR21
100_0402_1%
100_0402_1%
PR19
1K_0402_1%
1K_0402_1%
BATT_PRES <36>
EC_SMB_DA1 <36,41>
EC_SMB_CK1 <36,41>
2 2
PR20
PR20
100_0402_1%
100_0402_1%
2 1
2 1
O
TP (39.7)
ADP_I<36,41>
PROCHOT_IN<36>
45W
UMA
75W
N14P-GV2
21
PR1
PR1
1K_0402_1%
PR2
@PR2
@
0_0402_5%
0_0402_5%
1 2
1K_0402_1%
21
PR3
PR3
20K_0402_1%
20K_0402_1%
VCIN0_PH<36>
Initial Recovery
0.55V
0.90V
0.43V
0.72V
PR5
@PR5
@
0_0402_5%
0_0402_5%
1 2
12
PC11
@
PC11
@
0.1U_0402_10V7K
0.1U_0402_10V7K
+
3VL
12
PR4
PR4
12.1K_0402_1%
12.1K_0402_1%
12
PH1
PH1
100K_0402_1%_TSM0B104F4251RZ
100K_0402_1%_TSM0B104F4251RZ
Initial Recovery
CPU
3 3
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
OTP
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
C
90 C
70 C
Title
Title
Title
BATTERY CONN / OTP
BATTERY CONN / OTP
BATTERY CONN / OTP
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: S heet
Date: S heet
Date: S heet
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
ZRMAA
D
40 55
40 55
40 55
0.4
0.4
0.4
of
of
of
A
or reverse input protection
f
13
D
D
2
Q209
Q209
P
P
G
G
SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
S
R225
R225
P
P
1 2
1M_0402_5%
1 1
2 2
3 3
1M_0402_5%
V
IN
Q203
Q203
P
P
TPCA8057-H_PPAK56-8-5
TPCA8057-H_PPAK56-8-5
5
12
C230
C230
P
P
2200P_0402_50V7K
2200P_0402_50V7K
1
2
3
4
BQ24735_ACDRV_1
1 2
3M_0402_5%
3M_0402_5%
S
R226
R226
P
P
P
1
12
PC231
PC231
0.1U_0402_25V6
0.1U_0402_25V6
12
PR234
PR234
4.12K_0603_1%
4.12K_0603_1%
P
P
Q205
SI7716ADN-T1-GE3_POWERPAK8-5
SI7716ADN-T1-GE3_POWERPAK8-5
12
Q205
1
2
3
4
PR235
PR235
4.12K_0603_1%
4.12K_0603_1%
P
2
5
PC238
PC238
0.1U_0603_25V7K
0.1U_0603_25V7K
+3VL
PR239 10K_0402_1%PR239 10K_0402_1%
0.01_1206_1%
0.01_1206_1%
1
2
0.1U_0402_25V6
0.1U_0402_25V6
12
BQ24735_ACP
BQ24735_CMSRC
BQ24735_ACDRV
1 2
P
P
1 2
PC236
PC236
ACIN<36,9>
VIN
B
C
harger controller (40.1), Support component (40.2)
MI Part (47.1)
E
EMI@PL201
EMI@
1UH_NRS4018T1R0NDGJ_3.2A_30%
1UH_NRS4018T1R0NDGJ_3.2A_30%
1 2
2
3
PD230
PD230
BAS40CW_SOT323-3
BAS40CW_SOT323-3
0.047U_0402_25V7K
0.047U_0402_25V7K
1
12
PC237
PC237
1 2
PR228
PR228
BQ24735_VCC
20
VCC
BQ24735RGRR_QFN20_3P5X3P5
BQ24735RGRR_QFN20_3P5X3P5
ACDET6IOUT7SDA8SCL9ILIM
BQ24735_ACDET
12
10_1206_1%
10_1206_1%
PR229
PR229
2.2_0603_5%
2.2_0603_5%
DH_CHG
BQ24735_BST
BQ24735_LX
17
18
19
BTST
HIDRV
PHASE
P
L201
12
12
PD231
PD231
RB751V-40_SOD323-2
RB751V-40_SOD323-2
DH_CHG
PC205
PC205
1 2
BQ24735_REGN
1U_0603_25V6K
1U_0603_25V6K
16
REGN
15
LODRV
14
GND
13
SRP
12
SRN
11
BATDRV
10
BQ24735_ILIM
12
12
PR242
PR242
100K_0402_1%
100K_0402_1%
12
PC214
@EMI@ PC214
@EMI@
2200P_0402_25V7K
2200P_0402_25V7K
PR210
PR210
0_0603_5%
0_0603_5%
1 2
DL_CHG
PR236
PR236
10_0603_1%
10_0603_1%
1 2
SRP
PR237
PR237
6.8_0603_5%
6.8_0603_5%
1 2
SRN
BQ24735_BATDRV
1 2
PR241
PR241
357K_0402_1%
357K_0402_1%
PC243
PC243
0.01U_0402_25V7K
0.01U_0402_25V7K
12
PC211
PC211
10U_0805_25V6K
10U_0805_25V6K
CSOP1
CSON1
+3VALW
R211
R211
B
+
4
3
VIN
12
PC235
PC235
0.1U_0402_25V6
0.1U_0402_25V6
PC239
PC239
BQ24735_ACN
1 2
1U_0603_25V6K
1U_0603_25V6K
21
1
2
3
4
5
BQ24735_ACOK
12
PR244
PR244
422K_0402_1%
422K_0402_1%
PU200
PU200
PAD
ACN
ACP
CMSRC
ACDRV
ACOK
Vin Dectector
12
Min. Typ Max.
H-->L 17.23V
L-->H 17.63V
ILIM and external DPM
3.61A
4 4
12
PR245
PR245
PC244
PC244
66.5K_0402_1%
66.5K_0402_1%
0.1U_0402_25V6
0.1U_0402_25V6
PC245
PC245
12
100P_0402_50V8J
100P_0402_50V8J
PR246
@PR246
@
0_0402_5%
0_0402_5%
1 2
PC246
@PC246
@
0.1U_0402_10V7K
0.1U_0402_10V7K
EC_SMB_CK1 <36,40>
EC_SMB_DA1 <36,40>
ADP_I <36,40>
12
Please locate t he RC
Near EC chip
C
PC213
PC213
10U_0805_25V6K
10U_0805_25V6K
5
4
123
5
4
12
PC242
PC242
0.1U_0603_16V7K
0.1U_0603_16V7K
PL202
PL202
1 2
PR206
PR206
@EMI@
@EMI@
4.7_1206_5%
4.7_1206_5%
PC206
@EMI@ PC206
@EMI@
680P_0603_50V8J
680P_0603_50V8J
1 2
4.12K_0603_1%
4.12K_0603_1%
BQ24735_BATDRV
PQ201
PQ201
AON7408L
AON7408L
4.7UH_ETQP3W4R7WF N_5.5A_20%
4.7UH_ETQP3W4R7WF N_5.5A_20%
BQ24735_LX
12
PQ202
PQ202
AON7406L
AON7406L
123
12
EMI Part (47.1)
PR247
PR247
309K_0402_1%
309K_0402_1%
PR249
PR249
47K_0402_1%
47K_0402_1%
For A51 ADP_V function
P
P
Q207
Q207
SI7716ADN-T1-GE3_POWERPAK8-5
SI7716ADN-T1-GE3_POWERPAK8-5
5
BQ24735_BATDRV_1
PR233
PR233
PR227
PR227
0.01_1206_1%
0.01_1206_1%
1
CHG
2
CSOP1
12
PC240
PC240
0.1U_0402_25V6
0.1U_0402_25V6
VIN
12
12
4
4
3
CSON1
12
12
PC247
@PC247
@
0.1U_0402_10V7K
0.1U_0402_10V7K
D
1
2
3
12
PC234
PC234
0.01U_0402_50V7K
0.01U_0402_50V7K
BATT+
12
12
PC222
PC222
PC223
PC241
PC241
0.1U_0402_25V6
0.1U_0402_25V6
10U_0805_25V6K
10U_0805_25V6K
ADP_V <36>
PC223
10U_0805_25V6K
10U_0805_25V6K
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
C
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: S heet
Date: S heet
Date: S heet
Compal Electronics, Inc.
CHARGER
CHARGER
CHARGER
ZRMAA
D
41 55
41 55
41 55
of
of
of
0.4
0.4
0.4
PC335
PC335
1 2
+3VL
POK<36,9>
BST1_3V
EC_ON<36>
VS_ON<36>
B
3/5V_B+
100P_0402_50V8J
100P_0402_50V8J
14K_0402_1%
14K_0402_1%
PR335
PR335
100K_0402_1%
100K_0402_1%
1 2
PR333
PR333
0_0402_5%
0_0402_5%
1 2
PC345@
PC345@
1 2
PR330
PR330
1 2
PR331
PR331
20K_0402_1%
20K_0402_1%
1 2
BST_3V
UG_3V
LX_3V
LG_3V
499K_0402_1%
499K_0402_1%
1 2
12
PC360
PC360
2.2K_0402_1%
2.2K_0402_1%
1 2
@PR341
@
0_0402_5%
0_0402_5%
1 2
VFB=2V
PR334
PR334
0.1U_0603_25V7K
0.1U_0603_25V7K
PR340
PR340
PR341
FB_3V
6
7
8
9
10
PGOOD
BOOT2
UGATE2
PHASE2
LGATE2
PR338
PR338
100K_0402_1%
100K_0402_1%
5
12
PR342
PR342
PR337
PR337
PR357
PR357
56K_0402_1%
56K_0402_1%
2 1
2 1
2 1
143K_0402_1%
143K_0402_1%
TON_35V
ENTRIP_5V
ENTRIP_3V
2
3
4
FB2
TON
ENTRIP1
ENTRIP2
VIN11ENLDO12SECFB13LDO514LDO3
12
PC342
PC342
1U_0603_10V6K
1U_0603_10V6K
12
PC343
PC343
PR332
@ PR332
@
2 1
100K_0402_5%
100K_0402_5%
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
30K_0402_1%
30K_0402_1%
1 2
160K_0402_1%
160K_0402_1%
PR351
PR351
19.1K_0402_1%
19.1K_0402_1%
1 2
FB_5V
VFB=2V
1
21
FB1
PAD
20
BYP1
19
BOOT1
18
UGATE1
17
PHASE1
16
LGATE1
PU330
PU330
15
RT8243AZQW_WQFN20 _3X3
RT8243AZQW_WQFN20 _3X3
12
PC344
PC344
4.7U_0603_10V6K
4.7U_0603_10V6K
ENLDO <37>
A
/5VALW controller (35.1), Support component (35.2)
3
1 1
B+
EMI Part (47.1)
1 2
PL331
EMI@ PL3 31
EMI@
HCB2012KF-121T50_0805
HCB2012KF-121T50_0805
2 2
+3VALWP
3VALW
Ipeak : 9 A
Imax : 6.3 A
Iocp : 10.5 A
FSW : 455 kHz
3/5V_B+
P
2200P_0402_50V7K
2200P_0402_50V7K
@EMI@
@EMI@
PC340
PC340
10U_0603_25V6M
10U_0603_25V6M
2.2UH_ETQP3W2R2W FN_8.5A_20%
2.2UH_ETQP3W2R2W FN_8.5A_20%
1
+
+
PC331
PC331
2
100U_D_6.3VM_R15M
100U_D_6.3VM_R15M
PL332
PL332
1 2
12
PR336
4.7_1206_5%
4.7_1206_5%
@EMI@ PR336
@EMI@
SNUB_3V
12
PC336
@EMI@ PC336
@EMI@
680P_0603_50V8J
680P_0603_50V8J
12
12
C339
C339
P
5
PQ331
PQ331
AON7408L
AON7408L
123
5
123
4
0.1U_0402_10V7K
0.1U_0402_10V7K
4
FDMC7692S_MLP8-5
FDMC7692S_MLP8-5
PQ332
PQ332
Rds=10.8mȍ(Typ)
13.6mȍ(Max)
EMI Part (47.1)
3 3
PR350
PR350
BST_5V
UG_5V
LX_5V
LG_5V
C
PR355
PR355
0_0402_5%
0_0402_5%
1 2
+3VLP
12
PC341
PC341
4.7U_0603_10V6K
4.7U_0603_10V6K
3/5V_B+
PC355
PC355
0.1U_0402_10V7K
0.1U_0402_10V7K
1 2
BST1_5V
Rds=10.8mȍ(Typ)
13.6mȍ(Max)
12
PC361
PC361
10U_0603_25V6M
10U_0603_25V6M
PQ352
PQ352
FDMC7692S_MLP8-5
FDMC7692S_MLP8-5
PQ351
PQ351
AON7408L_DFN8-5
3 5
2
5
AON7408L_DFN8-5
1
123
4
4
EMI Part (47.1)
PL352
PL352
2.2UH_ETQP3W2R2W FN_8.5A_20%
2.2UH_ETQP3W2R2W FN_8.5A_20%
1 2
12
PR356
4.7_1206_5%
4.7_1206_5%
@EMI@ PR356
@EMI@
SNUB_5V
12
PC356
@EMI@ PC356
@EMI@
680P_0603_50V8J
680P_0603_50V8J
D
1
+
+
2
5VALW
Ipeak : 9.8 A
Imax : 6.8 A
Iocp : 11.8 A
FSW : 390 kHz
PC351
PC351
150U_D_6.3VM_R18M
150U_D_6.3VM_R18M
+5VALWP
PJ332
@ PJ332
@
+3VLP +3VL
1
JUMP_43X39
JUMP_43X39
221
+3VALWP +3VALW
+5VALWP +5VALW
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
PJ331
@ PJ331
@
112
JUMP_43X118
JUMP_43X118
@ PJ351
@
112
JUMP_43X118
JUMP_43X118
PJ351
2
2
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
C
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: S heet
Date: S heet
Date: S heet
Compal Electronics, Inc.
3VALW/5VALW
3VALW/5VALW
3VALW/5VALW
ZRMAA
D
42 55
42 55
42 55
of
of
of
0.4
0.4
0.4
A
DDR controller (35.3), Support component (35.4)
E
MI Part (47.1)
P
L151
EMI@PL151
EMI@
HCB1608KF-121T30_0603
HCB1608KF-121T30_0603
B
+
1 2
PL152
PL152
1UH_PCMB063T-1R0MS_12A _20%
1UH_PCMB063T-1R0MS_12A _20%
+1.35VP
DDR 1.35 V
Ipeak : 8.9 A
Imax : 6.3 A
Iocp : 11 A
FSW : 306 kHz
1
+
+
C157
C157
P
P
2
220U_D2_2V_17m
220U_D2_2V_17m
EMI Part (47.1)
1 1
1
.35V_B+
PR156
@EMI@ PR156
@EMI@
4.7_1206_5%
4.7_1206_5%
PC156
@EMI@
PC156
@EMI@
680P_0402_50V7K
680P_0402_50V7K
12
PC154
PC154
10U_0603_25V6M
10U_0603_25V6M
PQ151
PQ151
AON7408L
AON7408L
123
PQ152
PQ152
FDMC7692S_MLP8-5
FDMC7692S_MLP8-5
123
SYSON<36>
PC155
PC155
5
5
2 1
0.1U_0603_25V7K
0.1U_0603_25V7K
4
4
Rds=10.8mȍ(Typ)
13.6mȍ(Max)
PR163
@PR163
@
0_0402_5%
0_0402_5%
1 2
+5VALW
12
PC152
2200P_0402_50V7K
2200P_0402_50V7K
@EMI@
@EMI@ PC152
12
12
SNUB_+1.35VP
12
BST_1.35V-1
PR159
PR159
5.1_0603_5%
5.1_0603_5%
1 2
1U_0603_10V6K
1U_0603_10V6K
PC164
PC164
P
P
R155
R155
0_0603_5%
0_0603_5%
1 2
SW_1.35V
DL_1.35V
15K_0402_1%
15K_0402_1%
1U_0603_10V6K
1U_0603_10V6K
12
EN_1.35V
PR158
PR158
1 2
PC162
PC162
1 2
VDD_1.35V
BST_1.35V
H_1.35V
D
CS_1.35V
+5VALW
1.35V_B+
15
LGATE
14
PGND
13
CS
12
VDDP
11
VDD
PR161
PR161
825K_0402_1%
825K_0402_1%
1 2
18
17
16
PHASE
RT8207MZQW_W QFN20_3X3
RT8207MZQW_W QFN20_3X3
PGOOD
10
19
BOOT
UGATE
VLDOIN
S5
S3
TON
8
7
9
TON_1.35V
20
PU150
PU150
21
VTT
PAD
1
VTTGND
2
VTTSNS
3
GND
4
VTTREF
5
VDDQ
FB
6
FB_1.35V
VFB=0.75V
VTTREF_1.35V
PR162
PR162
10K_0402_1%
10K_0402_1%
2 1
+1.35V
+1.35VP
+1.35VP
12
PR160
PR160
8.06K_0402_1%
8.06K_0402_1%
2 1
0.675VSP
+
12
PC159
PC159
PC160
PC160
10U_0805_6.3V6K
10U_0805_6.3V6K
10U_0805_6.3V6K
10U_0805_6.3V6K
12
PC163
PC163
0.033U_0402_16V7K
0.033U_0402_16V7K
PJ675
@ PJ675
@
+0.675VSP
+1.35VP
1
JUMP_43X39
JUMP_43X39
@
@
PJ1351
PJ1351
1
JUMP_43X118
JUMP_43X118
221
221
+0.675VS
+1.35V
STATE S3 S5 1.5VP VTT_REFP 0.75VSP
S0
S3
S4/S5
Hi Hi
HiLo
Lo Lo
On
On
Off
(Discharge)
On
On
Off
(Discharge)
On
Off
(Hi-Z)
Off
(Discharge)
Note: S3 - sleep ; S5 - power off
12
PC166
@PC166
@
0.1U_0402_10V7K
0.1U_0402_10V7K
PR164
PR164
0_0402_5%
0_0402_5%
21
DDR_VTT_PG_CTRL<16>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
EN_0.675VSP
12
PC167
PC167
0.1U_0402_10V7K
0.1U_0402_10V7K
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: S heet
Date: S heet
Date: S heet
Compal Electronics, Inc.
1.35VP/0.675VSP
1.35VP/0.675VSP
1.35VP/0.675VSP
ZRMAA
43 55
43 55
43 55
of
of
of
0.4
0.4
0.4
5
4
3
2
1
D D
.05VCCP controller (35.5), Support component (35.6)
1
PR402
PR402
0_0402_5%
0_0402_5%
12
12
PC402
@
PC402
@
0.1U_0402_16V7K
0.1U_0402_16V7K
SUSP# <36,38,45>
EMI Part (47.1)
EMI Part (47.1)
PL401
EMI@ PL40 1
EMI@
HCB2012KF-121T50_0805
н
HCB2012KF-121T50_0805
C C
12
12
PC404
PC404
2200P_0402_50V7K
2200P_0402_50V7K
@EMI@
@EMI@
нϯs^
VCCST_PWRGD<12,36>
12
PC401
PC401
10U_0805_25V6K
10U_0805_25V6K
1 2
100K_0402_5%
100K_0402_5%
PR401
PR401
нϯs^
PU400
PU400
SY8208DQNC_QFN10_3X3
SY8208DQNC_QFN10_3X3
8
IN
EN
GND
ILMT
PG
BS
LX
FB
BYP
LDO
9
3
2
1
6
PC406
PC406
10
0.1U_0603_25V7K
0.1U_0603_25V7K
4
7
5
1 2
12
SW_+1.05VSP
12
PC412
PC412
PC413
PC413
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
PR403
@EMI@ PR403
@EMI@
4.7_1206_5%
4.7_1206_5%
1 2
1UH_PCMB063T-1R0MS_12A _20%
1UH_PCMB063T-1R0MS_12A _20%
1 2
+3VALW
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
SNUB_+1.05VSP
PL402
PL402
@EMI@ PC403
@EMI@
680P_0603_50V7K
680P_0603_50V7K
12
PR404
PR404
75K_0402_1%
75K_0402_1%
12
PR405
PR405
100K_0402_1%
100K_0402_1%
1 2
12
12
PC403
PC407
PC407
PR406
PR406
нϭϬϱs^ͺsddW
12
4700P_0402_25V7K
4700P_0402_25V7K
1K_0402_1%
1K_0402_1%
12
PC408
PC408
PC409
PC409
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
PC411
PC411
PC410
PC410
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
+1.05VS_VTTP
PJ401
@PJ401
@
112
JUMP_43X118
JUMP_43X118
2
+1.05VS_VTT
Ipeak : 10.2 A
Imax : 7.2 A
Iocp : 16 A
FSW : 800 kHz
B B
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: S heet
Date: S heet
2
Date: S heet
Compal Electronics, Inc.
+1.05VS_VCCP
+1.05VS_VCCP
+1.05VS_VCCP
ZRMAA
ZRMAA
ZRMAA
1
44 55
44 55
44 55
0.4
0.4
0.4
of
of
of
PR605
PR605
4
PU600
PU600
1
PGOOD
2
TRIP
3
EN
4
VFB
5
TST
TPS5121 2DSCR_SON10_ 3X3
TPS5121 2DSCR_SON10_ 3X3
VBST
DRVH
V5IN
DRVL
10
BST_1.5V SG
9
DH_1.5VS G
8
SW
TP
SW_1 .5VSGEN_1.5VS G
7
6
DL_1.5VS G
11
12
1U_0603 _10V6K
1U_0603 _10V6K
5
1
.5VS controller (35.31), Support component (35.32)
D D
PR608
PR608
1K_0402 _1%
1K_0402 _1%
SUSP#<36,38,44>
PCH_PW R_EN<3 6,38>
1 2
PR601
@P R601
@
1K_0402 _1%
1K_0402 _1%
1 2
PC605
PC605
0.1U_040 2_16V7K
0.1U_040 2_16V7K
12
PR602
PR602
127K_04 02_1%
127K_04 02_1%
21
TRIP_1.5VS G
FB_1.5VS G
RF_1.5VS G
12
470K_04 02_1%
470K_04 02_1%
1 2
+5VALW
PC606
PC606
3
PR603
PR603
2.2_0603 _5%
2.2_0603 _5%
PC604
PC604
0.1U_060 3_25V7K
0.1U_060 3_25V7K
1 2
Rds=13.5mȍ(Typ)
16.5mȍ(Max)
2
MI Part (47.1)
E
EMI@PL601
EMI@
HCB2012 KF-121T50_080 5
1
.5VSG_B+
5
4
4
PQ601
PQ601
AON7408L
AON7408L
123
2.2UH_ET QP3W2R2W FN_8.5A_20 %
2.2UH_ET QP3W2R2W FN_8.5A_20 %
5
12
PQ602
PQ602
123
12
12
PL602
PL602
1 2
PR604
EMI@
PR604
EMI@
4.7_1206 _5%
4.7_1206 _5%
PC608
EMI@ PC608
EMI@
680P_04 02_50V7K
680P_04 02_50V7K
PC601
PC601
10U_0603_25V6M
10U_0603_25V6M
HCB2012 KF-121T50_080 5
12
PC602
PC602
2200P_0402_50V7K
2200P_0402_50V7K
@EMI@
@EMI@
P
L601
21
1
+
+
PC607
PC607
220U_D2 _2V_17m
220U_D2 _2V_17m
2
1
+
B
+1.5VALWP
SI7716ADN-T1-GE3_POWERPAK8-5
C C
B B
VFB=0.704V
12
PR607
PR607
10K_040 2_1%
10K_040 2_1%
PR606
PR606
11.5K_04 02_1%
11.5K_04 02_1%
21
SI7716ADN-T1-GE3_POWERPAK8-5
+1.5VALW P
EMI Part (47.1)
PJ150
@P J150
@
1
221
JUMP_43 X118
JUMP_43 X118
+1.5VALW
1.5V
Ipeak : 7.8 A
Imax : 5.5 A
Iocp : 9.5 A
FSW : 290 kHz
A A
Security Class ification
Security Class ification
Security Class ification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Docum ent Number Rev
Size Docum ent Number Rev
Size Docum ent Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
+1.5VS
ZRMAA
1
45 55
45 55
45 55
0.4
0.4
0.4
of
of
of
5
4
3
2
1
+VCC_CORE controller (36.1), Support component (36.3)
driver(36.2), decoupling cap(36.4)
5
4700P_0402 _25V7K
4700P_0402 _25V7K
PR509
PR509
309K_0402_ 1%
309K_0402_ 1%
1 2
13
12
IMON
THERM
V5A
VREF
28
29
12
PC519
PC519
1U_0402_1 0V6K
1U_0402_1 0V6K
PC502
PC502
1 2
OCP-I
GND
V5A
1622_VREF
11
10
F-IMAX
B-RAMP
VCLK
VR_HOT#
31
30
1 2
PR529
PR529
10_0603_1 %
10_0603_1 %
56K_0402_1 %
56K_0402_1 %
1 2
B-RAMP
9
O-USR
PGOOD
ALERT#
32
PR510
PR510
F-IMAX
VR_ON
SKIP#
PWM1
PWM2
VDIO
PR502
@
@ PR502
100K_0402_1%
100K_0402_1%
PR506
PR506
150K_0402_1%
150K_0402_1%
O-USR
8
7
6
5
4
N/C
3
2
VDD
VDD
1
PAD
33
+5VALW
12
H501
H501
P
100K_0402_ 1%_TSM0B104F42 51RZ
100K_0402_ 1%_TSM0B104F42 51RZ
D D
PC505
PC505
10K_0402_1 %
10K_0402_1 %
PR520
PR520
PC517
PC517
1500P_0402 _50V7K
1500P_0402 _50V7K
1 2
CSP1
CSN1
CSP2
GFB
VFB
PC516
@ PC516
@
100P_0402_ 50V8J
100P_0402_ 50V8J
10K_0402_1 %
10K_0402_1 %
21
CPU_B+
0_0402_5%
0_0402_5%
C C
VSS_SENSE<12>
VCC_SENSE<1 2>
B B
+3VS
1 2
PR521
@PR5 21
@
0_0402_5%
0_0402_5%
1 2
1 2
PR522
@PR52 2
@
0_0402_5%
0_0402_5%
P
B value:4250K
12
12
1000P_0402_50V7K
1000P_0402_50V7K
1 2
PR511
@PR511
@
10K_0402_1 %
10K_0402_1 %
PR514
PR514
VBAT
17
18
19
20
21
22
23
24
DROOP
21
PR526
PR526
21
PR528
PR528
0.33U_0402 _10V6K
0.33U_0402 _10V6K
4.87K_0402_ 1%
4.87K_0402_ 1%
1 2
HERM
T
PR505
PR505
9.09K_0402_1%
9.09K_0402_1%
SLEWA OCP-I
12
PR513
PR513
39K_0402_1 %
39K_0402_1 %
15
16
14
VBAT
SLEWA
CSP1
CSN1
CSN2
PU500
PU500
CSP2
TPS51622R SM_QFN32_4X4~D
TPS51622R SM_QFN32_4X4~D
PU3
N/C
GFB
VFB
COMP
DROOP
26
25
27
COMP
PR527
PR527
PC518
PC518
51622_VREF
21
12
2.7K_0402_1 %
2.7K_0402_1 %
12
12
PR530
PR530
0_0402_5%
0_0402_5%
1 2
SKIP#
PWM1
12
PC501
PC501
1U_0402_6.3V6K
1U_0402_6.3V6K
VR_SVID_DAT
VR_SVID_ALRT#
VR_SVID_CLK
VR_HOT#
12
12
PR503
PR503
PR504
PR504
1M_0402_1%
1M_0402_1%
9.31K_0402_1%
9.31K_0402_1%
12
12
PR507
PR507
PR508
PR508
150K_0402_1%
150K_0402_1%
150K_0402_1%
150K_0402_1%
VR_ON <12>
+1.05VS_VTT
12
PR523
PR523
10K_0402_1 %
10K_0402_1 %
PR531
PR531
0_0402_5%
0_0402_5%
1 2
PR501
PR501
12
1_0402_1%
1_0402_1%
PD501
@
PD501
@
RB751V-40_SOD323-2
RB751V-40_SOD323-2
+3VS
VR_SVID_CLK<12>
VR_SVID_ALRT#<12>
VR_SVID_DAT<12>
EMI Part (47.1)
FBMA-L11-20120 9-121LMA50T_0805
FBMA-L11-20120 9-121LMA50T_0805
B
+
FBMA-L11-20120 9-121LMA50T_0805
FBMA-L11-20120 9-121LMA50T_0805
CPU_B+
12
PC509
PC509
PC508
PC508
10U_0805_25V6K
10U_0805_25V6K
PR518 2.2_0 402_1%PR518 2.2_0 402_1%
PC511 .1U _0402_16V7K
PC511 .1U _0402_16V7K
PWM1
12
.1U_0402_1 6V7K
.1U_0402_1 6V7K
VR_HOT#<36>
@PC5 20
@
47P_0402_5 0V8J
47P_0402_5 0V8J
EMI@PL501
EMI@
1 2
1 2
EMI@PL504
EMI@
12
10U_0805_25V6K
10U_0805_25V6K
1 2
VGATE <12>
PC520
21
PC515
PC515
P
L501
L504
P
12
12
1
+
+
C503
C503
P
P
33U_25V_M
33U_25V_M
33U_25V_M
33U_25V_M
2
EMI Part (47.1)
PC510
2200P_0402_50V7K
2200P_0402_50V7K
@EMI@ PC510
@EMI@
9
5
PGND2
VSW
VIN
6
PGND1
BOOT_R
7
BOOT
VDD
8
PWM
SKIP#
PU501
PU501
CSD97374C Q4M_SON8_3P5X4P5
CSD97374C Q4M_SON8_3P5X4P5
+1.05VS_VTT
12
12
PR524
PR524
PR525
PR525
130_0402_1%
130_0402_1%
54.9_0402_1%
54.9_0402_1%
C504
C504
P
P
@EMI@ PC507
@EMI@
680P_0402_ 50V7K
680P_0402_ 50V7K
4
3
2
1
12
1
+
+
2
1 2
PC507
@EMI@ PR516
@EMI@
4.7_1206_5%
4.7_1206_5%
1 2
PR519
@PR519
@
0_0402_5%
0_0402_5%
C
PU_B+
12
PR516
21
SKIP#
PC514
PC514
1U_0402_1 0V6K
1U_0402_1 0V6K
PR512
PR512
1 2
2.37K_0402_ 1%
2.37K_0402_ 1%
PL502
PL502
0.15UH_ETQP 4LR15AFM_29A_20%
0.15UH_ETQP 4LR15AFM_29A_20%
1 2
+5VS
12
12
PH502
PH502
12
12
PR515
PR515
16.5K_0402_1%
16.5K_0402_1%
PR517
PR517
10K_0402_1%_TSM0A103F34D1RZ
10K_0402_1%_TSM0A103F34D1RZ
3.01K_0402_1%
3.01K_0402_1%
Maximum current: 32A
VIN
MAX current
Thermal current
Dynamic current
OCP
Switching frequency
Boot voltage
DC Load- line
PC506
PC506
0.1U_0402_10V7K
0.1U_0402_10V7K
12
PC512
@ PC512
@
0.1U_0402_10V7K
0.1U_0402_10V7K
+CPU_CORE
19V
32A
10A
27A
45A
1MHz
1.7V
2m Ohm
CSP1
CSN1
For BOT side
+CPU_CORE
+CPU_CORE
A A
22U_0603_6.3V6M
22U_0603_6.3V6M
P
P
12
C521
C521
22U_0603_6.3V6M
22U_0603_6.3V6M
12
P
P
C529
C529
For TOP side
22U_0603_6.3V6M
22U_0603_6.3V6M
1
P
P
C537
C537
2
22U_0603_6.3V6M
22U_0603_6.3V6M
P
P
1
C545
C545
2
5
22u*26
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PC522
PC522
12
12
22U_0603_6.3V6M
22U_0603_6.3V6M
PC530
PC530
12
12
22U_0603_6.3V6M
22U_0603_6.3V6M
PC538
PC538
1
2
22U_0603_6.3V6M
22U_0603_6.3V6M
PC546
PC546
1
2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PC524
PC524
PC523
PC523
12
12
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PC532
PC532
12
PC531
PC531
22U_0603_6.3V6M
22U_0603_6.3V6M
PC539
PC539
1
2
12
22U_0603_6.3V6M
22U_0603_6.3V6M
PC540
PC540
1
2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PC526
PC526
PC525
PC525
12
12
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PC533
PC533
22U_0603_6.3V6M
22U_0603_6.3V6M
PC541
PC541
1
2
12
12
PC534
PC534
22U_0603_6.3V6M
22U_0603_6.3V6M
PC542
PC542
1
2
4
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PC528
PC528
PC527
PC527
12
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
12
PC535
PC535
PC536
PC536
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PC544
PC544
PC543
PC543
1
1
2
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
CPU_CORE
ZRMAA
46 55
46 55
46 55
1
0.4
0.4
0.4
of
of
of
A
VGA_CORE
+
1 1
+VGA_CORE
1
2
2 2
Under VGA Core
12
12
12
12
C903
C903
C904
C904
P
P
P
P
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
12
C918
C918
C919
C919
P
P
P
P
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
Near VGA Core
12
C924
C924
P
P
PC923
PC923
47U_0805_6.3V6M
47U_0805_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
12
C905
C905
P
P
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
C920
C920
P
P
0.1U_0402_10V7K
0.1U_0402_10V7K
12
C925
C925
P
P
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
12
C909
C909
P
P
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
C921
C921
P
P
0.1U_0402_10V7K
0.1U_0402_10V7K
12
PC926
PC926
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
PC908
PC908
PC907
PC907
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
12
PC928
PC928
PC927
PC927
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
PRV11 = 71.5K ==>Fsw = 450KHz
PR917
@PR917
@
0_0402_5%
0_0402_5%
VGA_VSS_SENSE<20>
VGA_VCC_SENSE<20>
3 3
1 2
PR920
@PR920
@
0_0402_5%
0_0402_5%
1 2
12
PC936
PC936
1000P_0402_50V7K
1000P_0402_50V7K
PC937
PC937
47P_0402_50V8J
47P_0402_50V8J
1 2
B4-128 package
G
12
12
12
PC913
PC913
PC912
PC912
PC911
PC911
PC958
PC958
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
PC952
PC929
PC929
@ PC952
@
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
1 2
PC934
PC934
.01U_0603_16V7K
.01U_0603_16V7K
PR919
PR919
51_0402_1%
51_0402_1%
1 2
PR921
PR921
12
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
PC953
@ PC953
@
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
20K_0402_1%
20K_0402_1%
VREF
1500P_0402_50V7K
1500P_0402_50V7K
PR914
PR914
18K_0402_1%
18K_0402_1%
PC939
PC939
100P_0402_50V8J
100P_0402_50V8J
PC955
@ PC955
@
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
PR915
PR915
21
1 2
12
10K_0402_1%
10K_0402_1%
1 2
12
12
PC954
@ PC954
@
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
21
12
PC933
@
PC933
@
21
PC940
PC940
2700P_0402_50V7K
2700P_0402_50V7K
21
PR931
PR931
34K_0402_1%
34K_0402_1%
1 2
PC938
PC938
10P_0402_50V8J
10P_0402_50V8J
1 2
FB2_VGA
82K_0402_1%
82K_0402_1%
PC956
@ PC956
@
PR922
PR922
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
COMP_VGAFB1_VGA
PR913
PR913
20K_0402_1%
20K_0402_1%
PR930
PR930
2K_0402_1%
2K_0402_1%
REFIN
VREF
FS
FB_VGA
B
GA_CORE controller (43.1), Support component (43.2)
V
PR908
PR908
0_0603_5%
PSI
<18>
<18>
+3VS_DGPU
12
10K_0402_5%
10K_0402_5%
VIDBUF
TSNS13TALERT#
2 1
PR932
@
@ PR932
0_0402_5%
0_0402_5%
PSI_VGA
4
5
VID
14
VCC_VGA
12
+3VS_DGPU
12
PC930
PC930
.1U_0402_16V7K
.1U_0402_16V7K
1 2
PR912 10K _0402_5%PR912 10K _0402_5%
UGATE1_VGA
EN_VGA
2EN3
PSI
HG1
VCC15PGOOD16HG217BST2
1 2
PR925
PR925
10K_0402_5%
10K_0402_5%
1 2
PR927
PR927
2.2_0402_5%
2.2_0402_5%
PC946
PC946
1U_0402_10V6K
1U_0402_10V6K
1
BST1
PH1
LG1
PGND
PVCC
LG2
PH2
18
NCP81172MNTWG_QFN24_4X 4
NCP81172MNTWG_QFN24_4X 4
BOOT2_VGA
UGATE2_VGA
DGPU_VID
PR909
0_0402_5%
0_0402_5%
PR929
PR929
@ PR909
@
2 1
GPU_VID
21
VIDBUF
6
PU900
PU900
7
REFIN
8
VREF
9
FS
10
FBRTN
11
FB
12
COMP
GND
25
12
PR926
PR926
5.9K_0402_1%
5.9K_0402_1%
VREF
PR907
PR907
2.2_0603_5%
2.2_0603_5%
1 2
BOOT1_VGA
PHASE1_VGA
24
23
22
21
PVCC_VGA
20
19
VGA_PWROK <22,9>
+3VS
+5VS
BOOT1_2_VGA
1 2
@
@
PR901
PR901
0_0402_5%
0_0402_5%
0.22U_0603_10V7K
0.22U_0603_10V7K
LGATE1_VGA
LGATE2_VGA
0_0603_5%
1 2
PC922
PC922
1 2
PC935 4.7U_0603_10V6KPC935 4.7U_0603_10V6K
1 2
1 2
1 2
PR924
PR924
2.2_0603_5%
2.2_0603_5%
PHASE2_VGA
UGATE1_2_VGA
12
PR911
PR911
35.7K_0402_1%
35.7K_0402_1%
PR923
PR923
0_0603_5%
0_0603_5%
0.22U_0603_10V7K
0.22U_0603_10V7K
BOOT2_2_VGA
C
AON7518
AON7518
TPCA8059
TPCA8059
+5VS
UGATE2_2_VGA
PC944
PC944
1 2
PQ901
PQ901
PQ902
PQ902
PQ903
PQ903
AON7518
AON7518
PQ904
PQ904
TPCA8059
TPCA8059
D
MI Part (47.1)
E
+
VGA_B+
SUPPRE_ FBMA-L11-453215-800LMA90T_ 1812
SUPPRE_ FBMA-L11-453215-800LMA90T_ 1812
12
12
PC910
PC910
10U_0805_25V6K
10U_0805_25V6K
PL903
PL903
1 2
PC917
PC917
10U_0805_25V6K
10U_0805_25V6K
PR906
4.7_1206_5%
4.7_1206_5%
PC906
PC906
12
PC915
2200P_0402_50V7K
2200P_0402_50V7K
@EMI@
@EMI@ PC915
0.22UH_MMD-06DZNR22MEO1L_25 A_20%
0.22UH_MMD-06DZNR22MEO1L_25 A_20%
12
SNUB1_VGA
12
5
4
123
5
@EMI@ PR906
123
@EMI@
@EMI@
@EMI@
680P_0402_50V7K
680P_0402_50V7K
4
L901
EMI@PL901
EMI@
P
1
+
+
2
PC931
PC931
21
560U_D2_2VM_R4.5M
560U_D2_2VM_R4.5M
+VGA_CORE
B
+
EMI Part (47.1)
+VGA_B+
Product
EDP-Peak 55A
EDP-Continue
5
4
123
5
4
123
12
PR916
@EMI@ PR916
@EMI@
4.7_1206_5%
4.7_1206_5%
PC916
@EMI@ PC916
@EMI@
680P_0402_50V7K
680P_0402_50V7K
12
PC942
PC942
10U_0805_25V6K
10U_0805_25V6K
0.22UH_MMD-06DZNR22MEO1L_25 A_20%
0.22UH_MMD-06DZNR22MEO1L_25 A_20%
12
SNUB2_VGA
12
Max-Current 28A
VID range 0.7125~1.15V
PC943
PC943
OCP
Switching frequency
10U_0805_25V6K
10U_0805_25V6K
PL904
PL904
1 2
1
+
+
PC932
PC932
2
330U_D2_2V_Y
330U_D2_2V_Y
N14P-GV2
32A
60A
1MHz
+VGA_CORE
EMI Part (47.1)
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
B
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
C
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: S heet of
Date: S heet of
Date: S heet of
Compal Electronics, Inc.
VGA_CORE
VGA_CORE
VGA_CORE
ZRMAA
D
47 55
47 55
47 55
0.4
0.4
0.4
5
W
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/
4
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C C
ϭϯ
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A A
ϯϯ
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5
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size D ocument Number Rev
Size D ocument Number Rev
Size D ocument Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PIR (PWR)
PIR (PWR)
PIR (PWR)
ZRMAA
48 55Friday, June 21, 2013
48 55Friday, June 21, 2013
48 55Friday, June 21, 2013
1
0.4
0.4
0.4
A
H
W PIR (Product Improve Record)
RMAA LA-A481P SCHEMATIC CHANGE LIST
Z
REVISION CHANGE: 0.0 TO 0.1
GERBER-OUT DATE: 2013/04/01
NO DATE PAGE MODIFICATION LIST PURPOSE
--------------------------------------------------------------------------------------------------------------------1 03/04 36 Add EC_SMB_CK3
2 03/04 27 Add EC_SMB_CK3
1 1
3 03/04 31 Change JWLAN connector For WLAN
4 03/04 31 Change JHDMI connector For HDMI
5 03/04b 30 Change JHDD pin define For HDD
6 03/04b 33 Delete DEVSLP0 For HDD
7 03/04b 37 ADD R5
8 03/05A 07 Change FAN connector For FAN
9 03/05A 16
10 03/05A 33 Change JHP connector For Small board
11 03/05B 19 Change RV4
12 03/06A 19 Delete RV108
13 03/06A 19 ADD RPV8
14 03/06A 06 Update DDR pin for DDR interleave routing For DDR
15 03/06B 33 Change JHP to JSB4 and Add JSB5 For Small board
16 03/06B 33 ADD R44
17 03/06B 33 Change JKB to JKB4
18 03/07A 16
19 03/11A 33 Change JNGFF connector For NGFF SSD
20 03/11A 34 Change JUSBR
21 03/11A 37 Modify Hole For Dummy
2 2
22 03/11B 35 ADD RA5
23 03/11B 07 Change JSPK For Speaker
24 03/12A 30 Swap JHDD pin define For HDD
25 03/12A 29 Swap L64
26 03/12A 37 Change D6
27 03/12A 37 Add SW3 for 14" For Power Button
28 03/12B 37 Add H18
29 03/12C 37 Change CCL2 and RCL5 @ to GCLK@ For Green clock
30 03/12C 37 Delete E51_TXD(RB27)
31 03/12D 31 Change JWLAN to NGFF E type For WLAN
32 03/13A 37 ADD KSO17
33 03/13A 36 Change TRANS_SEL to pin75
34 03/13A 36 ADD KSO17
35 03/13A 36 Delete BT_ON Pin34 For WLAN
36 03/13A 17
37 03/13B 36 Change LAN_WAKE# from UB1.108 to UB1.71 For EC
38 03/13B 36 Change WAKE# to EC_SWI# and connect to UB1.108 For EC
39 03/13B 34 Swap L60
40 03/13B 37 Delete Q196 For WLAN LED
3 3
41 03/13B 35 Delete CA54
42 03/13B 35 Swap JSPK For Audio
43 03/14A 34 Swap LR7
44 03/14A 16
45 03/14B 33 Swap R44
46 03/14B 36 ADD JDB for EC debug For Debug
47 03/14B 18 Change XTAL_OUTBUFF
50 03/14B 18 Change SMB_CLK_GPU
51 03/14B 16
52 03/14B 31
53 03/14B 36 EC_SMB_CK3
54 03/14B 10 Delete R307
55 03/15A 5
56 03/15A 36 Change CB14 BOM config from @ to ESD@ for ESD's request. For ESD
57 03/15A 35 Delete RA50 for sleep & Music For Audio
58 03/15A 35 Swap JSB5 and modify JSB4
59 03/18A 05 Change CH11 from 180PF to 100PF for ESD's request. For ESD
60 03/18A 36 Change CB13 from 100PF to 0.1UF for ESD's request. For ESD
4 4
17 Change DDR net order For DDR
17 Change JDDR3S
6 Change DDR to no interleave routing For DDR
17 Swap JDDR3R
17 JDDR3R
36 ADD BT_ON For WLAN
10
37 Change CH7,D98,D99 BOM config from @ESD@ to ESD@ For ESD's request.
D6 R7
E
C_SMB_DA3
EC_SMB_DA3 Vendor request for LVDS Translator
D7 For Power LED
RV5
RV6
RV109
RPV9 For Layout placement
R45
R46
JUSBF connector For NGFF SSD
Q5539B for Combo Jack Normal Close For Audio
L65
D7 material and Add D8
H19 Delete H7
KSO16 for 15" keyboard For keyboard
KSO16 for 15" keyboard For keyboard
L56
CA56 For Audio
LR8 For USB
JDDR3S For DDR
R45
JDDR3S to JDDR3H
EC_SMB_DA3 change use 2.2K For LVDS SM Bus
R220 For Audio sleep & music
RV7
RV110
R47 For Small board
ADD JKB5 For Keyboard
JDDR3R For DDR
L66
L67 For HDMI
E51_RXD For WLAN
L71
L72 For DDR3
R46
R47 For Small board
XTAL_SSIN to RPV1.3
SMB_DATA_GPU to RPV2.3
B
R
R
B135
B136 Vendor request for LVDS Translator
RV8
RV9 For Layout placement
RV111
RV104
RV105
RV106
RV107 For Layout placement
R19 For 14" 15" LED
H14
H15 For Hole
!!!!
CHG_PWR_GATE# to pin89 For keyboard
RPV1.4 For VGA
JDDR3L For DDR
JSB5 pin define For Small board
RPV2.4 For VGA
C
D
E
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2012/04/19 2015/04/19
2012/04/19 2015/04/19
2012/04/19 2015/04/19
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
D
Date: Sheet
Compal Electronics, Inc.
HW-PIR
HW-PIR
HW-PIR
49 55Friday, June 21, 2013
49 55Friday, June 21, 2013
49 55Friday, June 21, 2013
E
0.4
0.4
0.4
of
of
A
H
W PIR (Product Improve Record)
RMAA LA-A481P SCHEMATIC CHANGE LIST
Z
REVISION CHANGE: 0.0 TO 0.1
GERBER-OUT DATE: 2013/04/01
NO DATE PAGE MODIFICATION LIST PURPOSE
--------------------------------------------------------------------------------------------------------------------61 03/18A 10 Change CH7, CB14 from 180PF to 0.1UF for ESD's request. For ESD
62 03/18A 37 Change D98,D99 to CH12, CH13 for ESD's request. For ESD
1 1
63 03/19A 31 Modify JWLAN For WLAN
64 03/19A 31 Modify JSB4
65 03/19B 33 Change JNGFF connector For SSD
66 03/19B 29
67 03/20A 37 R480 +5VS change to +5VALW For WLAN
68 03/20A 33 Delete LR5(USB20_P2_L
69 03/20B 33 JNGFF pin1
70 03/20B 21 Delete LV4
71 03/20C 28 Swap D97 For Layout
72 03/20D 31 Delete LED_WIMAX#
73 03/20D 37 Delete Q157
74 03/21A 28 Change U50 BOM config from IEDP@ to always mount. For LVDS issue
75 03/21A 28 Change R436 BOM config from LVDS@ to @. For LVDS issue
76 03/21A 28 Change R436 BOM config from LVDS@ to @. For LVDS issue
77 03/21A 38 Change Q6(SB570020110) to Q5539A(SB00000EO10) For Layout placement
78 03/21A 36 Add RR8
79 03/21A 36 Add EC_CB1 at pin97 For LAN_WAKE#
80 03/21A 33 Change U13,U15 from SA00004KB00 to SA00003TV00. For power switch issue on Rosetta
81 03/21A 34 Add RR6
2 2
82 03/21A 36 Add RR6 then connected to CHG_CB0 and EC_CB0 For USB Sleep and Charge
83 03/21A 34 Add RB11
84 03/21A 33 Modify JNGFF Config pin define and add SSD_Detect pin For SSD
85 03/21A 10 R215 change to 10K pull high 3.3V,PROJECT_ID change to SSD_Detect For SSD
86 03/25A 35 EC_MUTE_INT change to COMBO_GPI and add CA48(10u) For Audio Combo jack
87 03/25A 36 Delete EC_MUTE_INT
88 03/25A 33 Add test point For SSD
89 03/25A 35 Add RA71
90 03/25A 35 Swap Q5539.3(NBA_PLUG) and Q5539.5(NBA_PLUG#) For Audio
91 03/25A 35 change +MIC_VREFO to UA1.31 For Audio
92 03/25A 37 change ZZZ part number to DA8000Y0000 For Mother board location
93 03/25A 35 Add RA50 Reserve for solve noise issue For Audio
94 03/25A 36 Add RB38
95 03/25A 31 JWLAN.42(CLK_EC) connect to U1H.AE6 for WLAN NGFF type use For WLAN
96 03/25A 31 Delete pin64
97 03/25A 34 Change RB11,RB13 from un-mount to mount. For Sleep & Charge
98 03/26A 10 ADD R30 for SSD detect For SSD
99 03/26A 10 ADD RV32 for VRAM Strap pin For VRAM
100 03/26A 32 Change JRJ45 footprint For JRJ45
3 3
101 03/26A 37 H19 change to H_3P5x3P0N
102 03/26A 36 Delete RB5 For WLAN
103 03/26B 34 ADD RB5 Reserve for Seligo wake function For USB switch
104 03/27A 34 Swap LR7 For Layout
105 03/27B 38 Change Q195 SB570020110 to SB00000DH00 For layout
106 03/27B 36 Delete RB38(EC_MUTE_INT_R) For Audio
107 03/27B 38
108 03/27B 18
109 03/27B 29 Change Q190
110 03/27B 32 Change JRJ45 connector For LAN
111 03/29A 37 H29
113 03/29A 36 Delete RB39 For Audio
114 04/01A 35 ADD RA2
115 04/01A 35 Change +MIC1_VREFO(UA1.31) to +MIC2_VREFO(UA1.29) For Audio
28 Swap RP1
35
34Change Q195
8 Change QV1
H30 change to H_3P2
SB5 pin define & Add R49
J
RP2
D97
L61
pin13
RV32
R480 (didn't support WIMAX) For WLAN
RR9 then connected to CB0_WAKE# and LAN_WAKE# For LAN_WAKE#
RR7,change RR2
RB13 on EC_CB0
change Combo jack GND to AGND
RB39 fo Reserve solve S3
Q5539
QV2
Q191 SB501110010 to SB00000PF00 For X1 code
MIC2_R_C_L
pin61
RV33
RM6 (didn't support WIMAX) For WLAN
RB38
66 net For WLAN
QR1
QV4
QV5
MIC2_R_C_R
B
50
53
R
L62 For Layout
USB20_N2_L), change to small board For EMI
pin67 connect to GND For SSD
RV34
RV50 (N14MGL@) For VGA
RR3 14641@ to @ For USB Sleep and Charge
EC_CB1 then pull-high to +3VALW_PCH For USB Sleep and Charge
RB39 For Audio Combo jack
!!!!
Change NBA_PLUG to NBA_PLUG# For Audio
S4
S5 bo bo issue For Audio
H20 change to H_2P8N For ME hole
Q5540
SB00000EO10 to SB00000DH00 For X1 code
QV7
QV9
QH4 SB00000EO10 to SB00000DH00 For X1 code
""""
ADD H7 H_3P0
""""
H13 change to H_3P5 For ME
MIC2_LINE1_R_L
51 For Small board
R
R
MIC2_LINE1_R_R For Audio 282 colay with 233
C
D
E
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2012/04/19 2015/04/19
2012/04/19 2015/04/19
2012/04/19 2015/04/19
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
D
Date: Sheet
Compal Electronics, Inc.
HW-PIR
HW-PIR
HW-PIR
50 55Friday, June 21, 2013
50 55Friday, June 21, 2013
50 55Friday, June 21, 2013
E
0.4
0.4
0.4
of
of
A
H
W PIR (Product Improve Record)
RMAA LA-A481P SCHEMATIC CHANGE LIST
Z
REVISION CHANGE: 0.1 TO 0.2
GERBER-OUT DATE: 2013/04/28
NO DATE PAGE MODIFICATION LIST PURPOSE
--------------------------------------------------------------------------------------------------------------------1 04/02A 29 ZZZ change to ZZZ1 For HDMI
2 04/02A All Delete Footprint *NEW and *–NEW word For Layout footprint
1 1
3 04/02A 35 ADD UA1 233@ For Audio
4 04/02A 21 ADD RV2
5 04/02A 21 ADD CV118
6 04/03A 19 ADD LV4 and change LV3 to ME@ For ME request
7 04/03A 35
8 04/03A 35 RA62 change to @ For vendor request
9 04/03A 35 Delete RV2
10 04/03A 35 Change JRJ45 SANTA_130456-311 to SANTA_130456-491 For ME request
11 04/09A 36 Change UB1 Material SA00004OB20(A3) to SA00004OB30(A4) For EC
12 04/09A 36 Change QB1 Material SB570020020 to SB00000EN00 For PUR cost request
13 04/09A 28 Change U50 Material SA007080100 to SA00000OH00 For Main source common
14 04/09A 35 Delete Q5539
15 04/09A 33 Change NBA_PLUG to NBA_PLUG# For Audio combo jack normal open
16 04/15A 22 Change RV54 33K to 4.7K For +3VS_DGPU sequence faster
17 04/15A 35 Change LA8 KC_FBMA-10-100505-300T_2P to CHILI_SBY100505N-221Y-N_2P For Layout
18 04/15A 37 Delete H12 and change H9 to H_4P0 For ME request
19 04/16A 31 ADD RC287
20 04/16A 31 ADD JWLAN1 For mini PCIE WLAN
21 04/16A 36 Delete UB1.26 FANPWM
2 2
22 04/16A 07 ADD U4
23 04/16A 07 Delete R32
24 04/16B 07 Delete RC292
25 04/16B 07 ADD RC301
26 04/16B 07 Change H8 H_5P0 to H_5P2 For ME hole
27 04/16C 07 Delete RC287
28 04/18A 19 Delete LV4
29 04/18A- 35 Change LA8 Footprint to CHILI_SBY100505T-470Y-N_2P For Audio
30 04/22A 31 JWLAN pin64
31 04/22A 36 UB1.89 CHG_PWR_GATE# change to ILIM_SEL For USB sleep & charge
32 04/22A 34 Change USB sleep & charge chip to TPS2546RTER (Delete U5
33 04/22A 34 Swap D87
34 04/23A 34 Swap L56
35 04/23B 35 ADD RA4
36 04/23B 34 Swap LR7 For Layout
37 04/23B 07 U4 SA00002XA00 EOL change use SA00003UO00 For FAN
38 04/24A 37 H29 change to H_3P3
39 04/24B 31 ADD WLAN net name
40 04/24B 34 UR4.5 USB_CHG_EN# change to USB_CHG_EN For USB sleep & charge
3 3
41 04/24B 36 UB1.18 USB_CHG_EN# change to USB_CHG_EN For USB sleep & charge
42 04/24B 36 CR10 4.7U_0805 change to 4.7U_0603
43 04/24D 34 ADD CR8
44 04/24D 35 Add CA49
45 04/24D 35 Delete CA44
46 04/25A 35
47 04/25A 35 Add CA54
48 04/26A 33 Add LR9
49 04/26B 35 +LINE1_VREFO-R
50 04/26C 33 Swap LR9
51 04/26C 35 Delete +LINE1_VREFO_R
52 04/26C 35 Delete RA74 For no support Line-in
53 04/26D 19 Delete LV4 For Layout
54 04/26D 02 Modify Block Diagram For Schematic
55 04/26E 32 Change UL2 material For Cost request
56 04/26F 32 Delete R4283
57 04/26F 33 change SSD_Detect to SSD_DETECT#
58 04/27G 32 Change UL2 material For ME request
59 04/28A 35 Change Q5539B AGND to GND
4 4
60 04/28A 33 Change title USB-CardReader Genesys GL834L to NGFF SATA/S_B conn/SPK For Title
61 04/28B 08 RH66 0ohm change to 15ohm For SPI EA report
62 04/29A 34 RR3
36 ADD RA3
36 Delete EC_MUTE_INT
V115
C
EC_MUTE_INT connect to EC UB1.122 For Audio bobo noise issue
C26
RA5 75ohm For Audio
ILIM_SEL_R
LR10 For EMI request
RR4 change config to @
V116
C
CV119
CV120
RC288
R25
C4
RC302
""""
LV3 config change to OPT@ For mini PCIE WLAN
66 conntect to +3V_WLAN For WLAN
D88 For USB3.0 Layout
L60
CA76
Change CA7 For co-lay Audio 233/282/283
CA55
LR10 For Layout
CV120
CV121 and change to N14PGV2@ For Layout
RA5 For Audio combo jack normal open
RC289
!!!!
C24
R33
D1
RC293
""""
ADD C161
""""
For mini PCIE WLAN
RC302 For mini PCIE WLAN
L71
L72 For USB3.0 Layout
""""H4
C161
CHG_CB0
CR8
QA1
RA3
RA36
RA37
+LINE1_VREFO-L change to +LINE1_VREFO_R
change PCIE_WAKE# to LAN_WAKE# For LAN
B
V117 and change RV1
C
CV121 and change CV28
RC290
RC291
ADD UB1.68 DFAN1 For FAN Control Circuit
C25
C32
""""
C5 For FAN Control Circuit
H5 change to H_3P2 For ME modify
C163 change to page 11 For WLAN
EC_MUTE_INT_R For co-lay Audio 233/282/283 Line-in
+LINE1_VREFO_L
!!!!
Change JFAN For FAN Control Circuit
C163
RC296
""""
ADD RR16 20K_0402_1% For USB sleep & charge
CHG_CB1
RA7
RA72
RA74 For co-lay Audio 233/282/283 Line-in
RA6
RA73
""""
ADD C4
Change title For Audio
""""
Change UR4 to UR2
V56
V32
C
CV27
RC292
RC293
RC297
EC_CHG_CB2 For USB sleep & charge
RA8
LA9 For co-lay Audio 233/282/283
RA73
RA36
C5
C6 For SSD
""""
Delete CR9 For USB sleep & charge
V24 to ME@ For ME request
C
C
CV29
CV40 to ME@ For ME request
RC294
RC295 For mini PCIE WLAN
RC298
RC299
U14
!!!!
+LINE1_VREFO_L For Audio
RA37
CA54
C
RC300 For mini PCIE WLAN
ADD UR4) For USB sleep & charge
CA55 For no support Line-in
D
E
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2012/04/19 2015/04/19
2012/04/19 2015/04/19
2012/04/19 2015/04/19
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
D
Date: Sheet
Compal Electronics, Inc.
HW-PIR
HW-PIR
HW-PIR
51 55Friday, June 21, 2013
51 55Friday, June 21, 2013
51 55Friday, June 21, 2013
E
0.4
0.4
0.4
of
of
A
H
W PIR (Product Improve Record)
RMAA LA-A481P SCHEMATIC CHANGE LIST
Z
REVISION CHANGE: 0.1 TO 0.2
GERBER-OUT DATE: 2013/04/28
NO DATE PAGE MODIFICATION LIST PURPOSE
--------------------------------------------------------------------------------------------------------------------63 04/29B 10 Change R272 0603 to 0402 For EC
1 1
2 2
B
C
D
E
3 3
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2012/04/19 2015/04/19
2012/04/19 2015/04/19
2012/04/19 2015/04/19
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
D
Date: Sheet
Compal Electronics, Inc.
HW-PIR
HW-PIR
HW-PIR
52 55Friday, June 21, 2013
52 55Friday, June 21, 2013
52 55Friday, June 21, 2013
E
0.4
0.4
0.4
of
of
A
H
W PIR (Product Improve Record)
RMAA LA-A481P SCHEMATIC CHANGE LIST
Z
REVISION CHANGE: 0.2 TO 0.3
GERBER-OUT DATE: 2013/05/30
NO DATE PAGE MODIFICATION LIST PURPOSE
--------------------------------------------------------------------------------------------------------------------01 05/02A 08 Delete R48
02 05/02A 31 ADD CM6
1 1
03 05/03A 13 ADD C61
04 05/03A 34 ADD RR17
05 05/03A 36 ADD EC_CB2 to UB1.36 For USB Sleep & charge
06 05/03A 36 RB12 change config to @ For USB Sleep & charge
07 05/03A 35 Delete QA1B
08 05/10A 08 ADD 10p at PCH_SPICLK for EA measure fail For SPI ROM
09 05/10A 20 RV32 change N14PGV2@ to @ For Load BOM
10 05/16A 13 Delete C61 For Layout
11 05/16A 34 Update UR2 symbol For USB sleep & charge
12 05/16B 31 Delete RC290
13 05/16B 34 Swap LR8 For Layout
14 05/16C 34 RC298.1
15 05/16C 34 JWLAN1.23 change net to PCIE_PRX_WLANTX_N4_R For Layout
16 05/16C 34 JWLAN1.23 change net to PCIE_PRX_WLANTX_P4_R For Layout
17 05/17A 33 Modify R46
18 05/17B 34 Delete RR15
19 05/17B 10 Delete SLP_CHG_CB1, CPU didn't need use For USB sleep & charge
20 05/17C 33 Swap LR9
21 05/17E 34 Modify USB Sleep & charge table For USB sleep & charge
2 2
22 05/20A 33 Swap LR9
23 05/21A 07 Change JDB smybol For Debug
24 05/21B 10 Change RP35 10K to 2.2K For APU
26 05/23A 28 D16 LVDS@ config change to @
27 05/27A 34 C532
28 05/27B 12 CC53 47U_0805 change to CC53
29 05/27B 18
30 05/27B 36
31 05/29A 10
32 05/29A 10 change SML0CLK to RP35.1
33 05/29A 37 add R480 & +3VS_NUM net For Keyboard Number lock LED power
34 05/29A 31 change RCL2 from short pad to 33 Ohm For 25M_LAN_LCK perormace
35 05/29B 9
36 05/29b 32 add DL4 & DL5 , delete CL23 & CL24 For LAN ESD
37 05/30A 35 add RA9 For Audio 283 & 233
38 05/30b 38 add PJ333 For Cost down +1.5VALW to +1.5VS
40 05/31A 13 change R210 config to @ , remove L3 config @ For +1.05VS_APLLOPI Power rail
41 05/31A 38 charnge R482
3 3
13 CV15
37 EC_CB2(GPIO1A) move to GPIO12
8 delete RH77, PCH_SMLDATA1 combine to RP35.4 For SMBUS
32
29 add C489
Y
C
C
2
2
CM8
69 For Customer request
C
hange RR@ config to @ For USB Sleep & charge
!!!!
C
""""
Modify QA1A to QA1 For Audio
RC298.1 net name swap
R47
RR10
LR10 For JSB4
LR10
CR2 47U_0805 change to C535
CV12
CV28
C487 For ESD
3 For Layout
CM7 For WLAN
RC291 For Layout
R44
R45
RR12
LR11
LR12 For Layout
CV29
R483 from 10k to 100k For reduce power consumption
B
!!!!
RC299.2
RC298.2 net name swap For Layout
!!!!
ADD LR11
RR11
CV67 22U_0805 change to 22U_0603 For ME layout request
SML0DATA to RP35.2
""""
LR12 For USB layout
RR13
RR17
RR2
RR3
RR4 For USB sleep & charge
R433 Delete IEDP@ config For LVDS
C532
CR2
CC54 22u_0603 For ME layout request
CR3 22u_0603 For ME layout request
ADD NUM_LED#(JKB5.1 to JUB1.36) For Keyboard Number lock
USB_OC#2 to RP34.5 For PU high resistor design
C
D
E
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2012/04/19 2015/04/19
2012/04/19 2015/04/19
2012/04/19 2015/04/19
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
D
Date: Sheet
Compal Electronics, Inc.
HW-PIR
HW-PIR
HW-PIR
53 55Friday, June 21, 2013
53 55Friday, June 21, 2013
53 55Friday, June 21, 2013
E
0.4
0.4
0.4
of
of
5
H
W PIR (Product Improve Record)
RMAA LA-A481P SCHEMATIC CHANGE LIST
Z
REVISION CHANGE: 0.3 TO 0.4
GERBER-OUT DATE: 2013/06/07
NO DATE PAGE MODIFICATION LIST PURPOSE
--------------------------------------------------------------------------------------------------------------------01 06/06 08 Delete RH73 , PCH_SMLCLK1 combine to RP8 For part count reduce
02 06/06 08 add C71 For HDD cannot detect issue
D D
03 06/06 11
04 06/06 31 JWLAN.46 direct connect to BT_ON For BT cannot turn off issue
05 06/06 31 move RM25 to JWLAN1.5 For BT cannot turn off issue
06 06/06A 31 add CCL10 For HDD cannot detect issue
07 06/07A add R234 For OC# pull hing
C C
1 FKDQJH%201RQ8OWUD#WR0:/$1#8OWUD#WR1:$/1#)RUPRGLI\FRUUHFW%20QDPH
3
4
3
2
1
B B
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2012/04/19 2015/04/19
2012/04/19 2015/04/19
2012/04/19 2015/04/19
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
2
Date: Sheet
Compal Electronics, Inc.
HW-PIR
HW-PIR
HW-PIR
54 55Friday, June 21, 2013
54 55Friday, June 21, 2013
54 55Friday, June 21, 2013
1
0.4
0.4
0.4
of
of
R163
4
R471
R472
RB7
RC285
RCL5
5
H
W PIR (Product Improve Record)
Z
RMAA LA-A481P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.4 TO 1.0
GERBER-OUT DATE: 2013/06/21
NO DATE PAGE MODIFICATION LIST PURPOSE
---------------------------------------------------------------------------------------------------------------------------------------------------------01 06/14 08 RH42 0 ohm change to 22 ohm For HDD cannot detect issue
D D
02 06/14 35 RA45,RA46,RA42 short pad change to 0 ohm For high frequency headphone zi zi noise when system idle.
03 06/14 31 RC298,RC299 change BOM , NWLN@ to MWLAN@ For SSD cannot detect issue
04 06/18 36 Add RB28 For audio EC_MUTE_INT common design
05 06/18 35 Change LA9 BOM config from EMI@ to 233@EMI@ For modify BOM config
06 06/20 34 Update USB3.0 conn footprint For ME request
07 06/20 12
08 06/20 9 add R418 For DP portB pull down
09 06/20 9
10 06/21 7
11 06/21 28 delete D16 For layout space concern
12 06/21 21 add LV4 For +PEX_PLLVDD Power ripple
C C
10
13 Delete T43, T32, T102
28 delete RH19 , add U51 For DOS mode garbage issue
9 31 33
36 change R65
3
2
RH26 footprint to short pad For cost down
1
B B
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2012/04/19 2015/04/19
2012/04/19 2015/04/19
2012/04/19 2015/04/19
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
2
Date: Sheet
Compal Electronics, Inc.
HW-PIR
HW-PIR
HW-PIR
55 55Friday, June 21, 2013
55 55Friday, June 21, 2013
55 55Friday, June 21, 2013
1
0.4
0.4
0.4
of
of
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