Compal LA-A321P ZIUS6, IdeaPad S410, M30-70, LA-A321P ZIUS7 Schematic

A

B

C

D

E

Compal Confidential

Model Name : ZIUS6/S7

1 1

File Name : LA-A321PR01 BOM P/N:4319OP38L5x -- ZIUS7

4319OP38L0x -- ZIUS6

Compal Confidential

2 2

ZIUS6/S7 M/B Schematics Document

Intel SharyBay ULT Processor + AMD SUN Pro

3 3

2013-03-14

REV:0.2

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFE RED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2011/06/24 2012/07/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

LA-A321PR02

E

1 46Thursday, March 14, 2013

0.2

of

1 46Thursday, March 14, 2013

A

B

C

D

E

Compal confidential

File Name :ZIUS6/ZIUS7

AMD SUN Pro

VRAM 256X16,

1 1

128X16 DDR3 x 4

page 16~22

PCIE x4

Memory BUS

1.35V DDR3L 1333/1600

204pin DDR3L-SO-DIMM X1

page 15

LVDS Conn

2 2

RJ45 Conn

page 29

page 24

Realtek RTD2132R

HDMI Conn.

LAN( 10/100/GbE)

Realtek RTL8111GUS /RTL8106 EUS

page 29

page 30

page 24

2.97GT/s HDMI x 4 lanes

port 3

PCIe 2.0 5GT/s

2Channel Speaker

eDP to LVDS translator

Combo Jack(HP, MIC)

IO/B

Single Digital MIC

IO/B

3 3

AUDIO CODEC

Realtek ALC233

page 23

SYS BIOS ROM 8M

WINBOND W25Q64FVSSIQ

page 7

HD Audio

SPI

eDP x1

DDI x1

PCIE x1

Intel Haswell ULT

1168pin BGA

page 04~14

SATA 3.0

USB 3.0

USB 2.0x8

PCIE x1

SATA3.0 HDD CONN

page 27

SATA3.0 HDD (SSD)

USB 3.0 conn x1

port (Left)

page 28 page 29

WLAN+BT (Mini Card)

port

page 28

USB 2.0 conn x2

port (Right)

IO/B

Card Reader

GENESYS GL834L

Card Reader Conn.

page 27

CMOS Camera

port

port IO/B

IO/B

LPC BUS

CLK=24MHz

KBC

ENE KB9012 A4

Issued Date

PS/2

page 31 page 31

C

Sub-borad

4 4

POWER BOARD

LED BOARD

IO Board

A

B

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

page 25

Int.KBDTouch Pad

Compal Secret Data

2011/07/21 2012/12/31

Compal Secret Data

Thermal Sensor

EMC1403-2-AIZL-TR

Deciphered Date

page 31

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

MB Block Diagram

2 46Thursday, March 14, 2013

E

0.2

1

Voltage Rails

+5VS

power plane

A A

State

S0

S3

S5 S4/AC

S5 S4/ Battery only

B B

S5 S4/AC & Battery don't exist

+5VALW

B+

O

X

+1.35V

+3VALW

O

X

X X X

EC SM Bus1 address

Device

Smart Battery Charger

Address Address

CPU SM Bus address

Device Address

DDR DIMM0 WALN

C C

Touch Pad

0XA0

+3VS

+1.5VS

+1.05VS_VTT

+CPU_CORE

+0.675VS

+VGA_CORE(PX)

+0.95VS_VGA(PX)

+3.3VS_VGA(PX)

+1.8VS_VGA(PX)

+1.5VS_VGA(PX)

OO

O

X

X X

X

EC SM Bus2 address

Device

Thermal Sensor EMC1403-2-AIZL-TR Panel - eDP to LVDS translator SharkBay ULT AMD SUN Pro

CPU SML0 Bus address

X

2

3

4

5

BOM Structure Table

1001_101xb

AddressDevice

STATE

Full ON

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

BOARD ID Table

Board ID

0 1 2 3 4 5 6 7

PCB Revision

USB 2.0 Port Table

USB 2.0 Port

SLP_S0# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS

ON

ON ON ON

ON

OFF

OFFLOW LOW LOW LOW

HIGH HIGH HIGH HIGH

LOW LOW

HIGH

LOWLOWLOW

HIGH

0.2

0.1

USB 3.0 Port Table

3 External

0 1 2 3 4 5 6 7

USB Port

USB 2.0 Port (I/O Board) USB 3.0/2.0 Port (MB) USB 2.0 Port (I/O Board) Card Reader Touch Screen (reserve) Camera Mini Card (WLAN/BT)

Port

1 2

USB 3.0 Port (MB)

3 4

SATA Port Table

Port

3 2 1

mSATA SSD

0

HDD

Clock

OFF

BTO Item BOM Structure

Connector ME@ 45 LEVEL 45@ Unpop CPU OPTION CPU1@

LAN RTL8111GUS LAN RTL8106EUS USB3.0 USB3@ EMI PART EMI@ ESD PART

PCIE Port Table

Port

Lane

1 2 3 4

5

6

LAN WLAN

0 1

GPU

2 3 0 1 2 3

*

@

UMA@INTEL UMA PX@AMD SUN Pro

S1G@VRAM Option

M1G@ H1G@ S2G@ M2G@ 8111@ 8106@

ESD@

*

SWR@ SWR@

CPU part

U1

CPU3@

U1

CPU3@

U1

CPU4@

U1

CPU1@

U1

CPU1@

U1

CPU2@

U1

CPU2@

CPU4@

U1

CPU5@

U1

CPU5@

SMBUS Control Table

PANEL

HOST

VGA BATT KB9012 SODIMM

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 SMBCLK SMBDATA SML0CLK SML0DATA

D D

SML1CLK SML1DATA

KB9012

+3VLP

KB9012

+3VS

CPU

+3VALW

CPU

+3VALW

KB9012

+3VS

1

X V

V

+3VS

X X

+3VLP

X X

X

X X

+3VS

X X

V

+3VS

X

sensor

WLAN

ADM1032

X

V

X X

+3VSV+3VS

V

+3VS

X XX XX V

X

2

VGA

Thermal

sensor

ADM1032

EMC1403

X X X

X

V

+3VS

X X X X X X X

CPU Sensor

X

V

+3VALW

X X

V

+3VALW

Touch Pad

X

+3VS

X

Security ROM

VV

+3VS

X X

NFC

X X

V

+3VS

X X

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

I5_3317U 1.7G

SA00006FY20

U1

I7-4550U 1.5G

SA00006SJ30

PCB part

ZZZ5

PCB 0R LA-A321P REV0 M/B

DA600104000

Issued Date

I3-4010U 1.7G

SA00006SX20

CPU6@

U1

I7-4500U 1.8G

SA00006SL20

2011/07/12 2012/07/01

CPU7@

VRAM

I3-4100U 1.8G

SA00006SU20

V0.2

ZZZ3

X7641338L34

K4W4G1646B-HC11

Compal Secret Data

Samsung

S2G@

Deciphered Date

I5-4250U 1.3G

SA00006NM40

4

I5-4200U 1.6G

SA00006SM20

ZZZ8

ZZZ6

ZZZ7

MICRON

M2G@

X7641338L35

MT41K256M16HA-107G:E K4W2G1646E-BC1A MT41J128M16JT-093G:K Hynix 128x16 Vram H5TC2G63FFR-11C

ZZZ6

Samsung

S1G@

X7641338L31

ZZZ4

MICRON

M1G@

X7641338L32

Title

Notes List

Size Document Number Rev

Custom

Date: Sheet of

ZZZ8

Hunix

H1G@

X7641338L33

Compal Electronics, Inc.

LA-A321PR02

5

3 46Thursday, March 14, 2013

0.2

5

D D

4

U1A

HASWELL_MCP_E

3

2

1

C54

DDI1_TXN0

C55

DDI1_TXP0

B58

DDI1_TXN1

H_PROCHOT#_R

H_CPUPWRGD

C58 B55 A55 A57 B57

C51 C50 C53 B54 C49 B50 A53 B53

D61 K61 N62

K63

C61

DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3

DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3

@

U1B

PROC_DETECT CATERR PECI

PROCHOT

PROCPWRGD

DDI EDP

1 OF 19

HASWELL_MCP_E

MISC

JTAG

THERMAL

PWR

EDP_RCOMP

EDP_DISP_UTIL

CRT

1 2

HDMI_TX2-_CK<30>

HDMI

C C

HDMI_TX2+_CK<30> HDMI_TX1-_CK<30> HDMI_TX1+_CK<30> HDMI_TX0-_CK<30> HDMI_TX0+_CK<30> HDMI_CLK-_CK<30> HDMI_CLK+_CK<30>

+1.05VS_VTT

H_PROCHOT#<25,33>

C46 0.1U_0402_16V7KC46 0.1U_0402_16V7K C47 0.1U_0402_16V7KC47 0.1U_0402_16V7K C48 0.1U_0402_16V7KC48 0.1U_0402_16V7K C55 0.1U_0402_16V7KC55 0.1U_0402_16V7K C56 0.1U_0402_16V7KC56 0.1U_0402_16V7K C68 0.1U_0402_16V7KC68 0.1U_0402_16V7K C72 0.1U_0402_16V7KC72 0.1U_0402_16V7K C74 0.1U_0402_16V7KC74 0.1U_0402_16V7K

H_PECI<25>

1 2

R2

62_0402_5%

1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2

R6 10K_0402_5%R6 10K_0402_5%

T111 @T111 @

R3

R3 56_0402_5%

56_0402_5%

1 2

CPU_DP2_N0 CPU_DP2_P0 CPU_DP2_N1 CPU_DP2_P1 CPU_DP2_N2 CPU_DP2_P2 CPU_DP2_N3 CPU_DP2_P3

T2 @T2 @

DDR3 Compensation Signals

B B

DDR3 Compensation Signals: 20mils to comp signals 25mils to non-comp signals 500mil for Max trace length

1 2

R9 200_0402_1%R9 200_0402_1%

1 2

R10 120_0402_1%R10 120_0402_1%

1 2

R11 100_0402_1%R11 100_0402_1%

DDR_PG_CTRL<15>

Chklist 1.0 SM_RCOMP1 -->120 ohm 1%

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 DIMM_DRAMRST# DDR_PG_CTRL

AU60 AV60 AU61 AV15 AV61

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_DRAMRST SM_PG_CNTL1

DDR3

2 OF 19

EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1

EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3

EDP_AUXN EDP_AUXP

Rev1p2

PROC_TCK PROC_TMS

PROC_TRST

PROC_TDI

PROC_TDO

PRDY PREQ

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

Rev1p2

C45 B46 A47 B47

C47 C46 A49 B49

A45 B45

D20 A43

J62 K62 E60 E61 E59 F63 F62

J60 H60 H61 H62 K59 H63 K60 J61

EDP_TXN0 <29> EDP_TXP0 <29>

EDP_AUXN <29> EDP_AUXP <29>

EDP_COMP CPU_INV_PWM

1 2

R1 24.9_0402_1%R1 24.9_0402_1%

1 2

R31 0_0402_5%@R31 0_0402_5%@

EDP_COMP: Trace width=20 mils,Spacing=25mil,Max length=100mils

XDP_TCK XDP_TMS XDP_TRST# XDP_TDI XDP_TDO

eDP

+VCCIOA_OUT

INVPWM <29,8>

T16@ T16@ T17@ T17@ T22@ T22@ T23@ T23@ T24@ T24@

+1.35V

12

R29

R29 470_0402_5%

470_0402_5%

DIMM_DRAMRST#

A A

5

DIMM_DRAMRST# <15>

4

ESD

H_CPUPWRGD

1

C2222

ESD@ C2222

ESD@

100P_0402_50V8J

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2011/12/13 2012/12/13

Compal Secret Data

Deciphered Date

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Title

Size Document Number Rev

Compal Electronics, Inc.

HSW MCP(1/11) DDI,MSIC,XDP

LA-A321PR02

1

4 46Thursday, March 14, 2013

0.2

5

D D

HASWELL_MCP_E

U1C

AH63

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23

C C

B B

DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

AH62 AK63 AK62 AH61 AH60 AK61 AK60 AM63 AM62 AP63 AP62 AM61 AM60 AP61 AP60 AP58 AR58 AM57 AK57

AL58 AK58 AR57 AN57 AP55 AR55 AM54 AK54

AL55 AK55 AR54 AN54 AY58

AW58

AY56

AW56

AV58 AU58 AV56 AU56 AY54

AW54

AY52

AW52

AV54 AU54 AV52 AU52 AK40 AK42

AM43 AM45

AK45 AK43

AM40 AM42 AM46

AK46

AM49

AK49

AM48

AK48

AM51

AK51

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

HASWELL_MCP_E

3 OF 19

DDR CHANNEL A

4

AU37

SA_CLK#0

AV37

SA_CLK0

AW36

SA_CLK#1

AY36

SA_CLK1

AU43

SA_CKE0

AW43

SA_CKE1

AY42

SA_CKE2

AY43

SA_CKE3

AP33

SA_CS#0

AR32

SA_CS#1

AP32

AY34 AW34 AU34

AU35 AV35 AY41

AU36 AY37 AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40 AP35 AW41 AU41 AR35 AV42 AU42

AJ61 AN62 AM58 AM55 AV57 AV53 AL43 AL48

AJ62 AN61 AN58 AN55 AW57 AW53 AL42 AL49

AP49 AR51 AP51

DDRA_ODT0

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

SM_DIMM_VREFCA <15> SA_DIMM_VREFDQ <15>

SA_ODT0

SA_RAS

SA_WE

SA_CAS

SA_BA0 SA_BA1 SA_BA2

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7

SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7

SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1

3

SA_CLK_DDR#0 <15> SA_CLK_DDR0 <15> SA_CLK_DDR#1 <15> SA_CLK_DDR1 <15>

DDRA_CKE0_DIMMA <15> DDRA_CKE1_DIMMA <15>

DDRA_CS0_DIMMA# <15> DDRA_CS1_DIMMA# <15>

T4@ T4@

DDR_A_RAS# <15>

DDR_A_WE# <15>

DDR_A_CAS# <15>

DDR_A_BS0 <15> DDR_A_BS1 <15> DDR_A_BS2 <15>

DDR_A_D[0..63]<15>

DDR_A_MA[0..15]<15>

DDR_A_DQS#[0..7]<15>

DDR_A_DQS[0..7]<15>

AY31

AW31

AY29

AW29

AV31 AU31 AV29 AU29

AY27

AW27

AY25

AW25

AV27 AU27 AV25 AU25

AM29

AK29

AL28 AK28 AR29 AN29 AR28 AP28 AN26 AR26 AR25 AP25 AK26

AM26

AK25

AL25

AY23

AW23

AY21

AW21

AV23 AU23 AV21 AU21

AY19

AW19

AY17

AW17

AV19 AU19 AV17 AU17 AR21 AR22

AL21 AM22 AN22 AP21 AK21 AK22 AN20 AR20 AK18

AL18 AK20 AM20 AR18 AP18

U1D

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

2

HASWELL_MCP_E

DDR CHANNEL B

4 OF 19

SB_CK#0

SB_CK0

SB_CK#1

SB_CK1

SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3

SB_CS#0 SB_CS#1

SB_ODT0

SB_RAS

SB_WE

SB_CAS

SB_BA0 SB_BA1 SB_BA2

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7

SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7

AM38 AN38 AK38 AL38

AY49 AU50 AW49 AV50

AM32 AK32

AL32

AM35 AK35 AM33

AL35 AM36 AU49

AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46

AW30 AV26 AN28 AN25 AW22 AV18 AN21 AN18

AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18

1

Rev1p2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2011/12/13 2012/12/13

Compal Secret Data

Deciphered Date

2

Rev1p2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

HSW MCP(2/11) DDRIII

LA-A321PR02

1

5 46Thursday, March 14, 2013

0.2

5

4

3

2

1

1 2

R33 10M_0402_5%R33 10M_0402_5%

Y1

D D

C C

1 2

32.768KHZ 12.5PF 9H03200031

1

C3

15P_0402_50V8J

2

PCH_INTVRMEN

INTVRMEN (+1.05 VA)

H：Integrated VRM enable

*

L：Integrated VRM disable

PCH_RTCX1

PCH_RTCX2

V0.2

1

C4

15P_0402_50V8J

2

1 2

R39 330K_0402_5%R39 330K_0402_5%

1 2

R40 330K_0402_5%@R40 330K_0402_5%@

+RTCVCC

RTC Battery

W=20mils W=20mils

+RTCVCC +RTCBATT

1 2

R107 0_0402_5%@R107 0_0402_5%@

1

C179

C179 1U_0402_6.3V6K

1U_0402_6.3V6K

2

2/4

Safty suggestion remove EE side ,Keep PWR side

JME2 Short PAD placement to Bottom side.

ME CMOS

+RTCVCC

R36 20K_0402_1%R36 20K_0402_1%

R37 20K_0402_1%R37 20K_0402_1%

1U_0603_10V6K

1 2 1 2

1U_0603_10V6K

1

C2

2

1

C5

2

JME1

JME1 SHORT PADS

SHORT PADS

1 2

@

JME2

JME2 SHORT PADS

SHORT PADS

1 2

@

2/4

CMOS

+RTCVCC

1 2

R35 1M_0402_5%R35 1M_0402_5%

HDA_SDIN0<23>

HASWELL_MCP_E

U1E

PCH_RTCX1 PCH_RTCX2 SM_INTRUDER# PCH_INTVRMEN PCH_SRTCRST# PCH_RTCRST#

HDA_BIT_CLK HDA_SYNC HDA_RST# HDA_SDIN0

HDA_SDOUT

PCH_JTAG_RST#

T108@T108@

PCH_JTAG_TCK PCH_JTAG_TDI

T118@T118@

PCH_JTAG_TDO

T113@T113@

PCH_JTAG_TMS

T119@T119@

PCH_TCK_JTAGX

T106@T106@

SMT

AW5

RTCX1

AY5

RTCX2

AU6

INTRUDER

AV7

INTVRMEN

AV6

SRTCRST

AU7

RTCRST

AW8

HDA_BCLK/I2S0_SCLK

AV11

HDA_SYNC/I2S0_SFRM

AU8

HDA_RST/I2S_MCLK

AY10

HDA_SDI0/I2S0_RXD

AU12

HDA_SDI1/I2S1_RXD

AU11

HDA_SDO/I2S0_TXD

AW10

HDA_DOCK_EN/I2S1_TXD

AV10

HDA_DOCK_RST/I2S1_SFRM

AY8

I2S1_SCLK

AU62

PCH_TRST

AE62

PCH_TCK

AD61

PCH_TDI

AE61

PCH_TDO

AD62

PCH_TMS

AL11

RSVD

AC4

RSVD

AE63

JTAGX

AV2

RSVD

HASWELL_MCP_E

RTC

5 OF 19

JTAG

SATA_IREF

RSVD RSVD

SATALED

Rev1p2

J5 H5 B15 A15

J8 H8 A17 B17

J6 H6 B14 C15

F5 E5 C17 D17

V1 U1 V6 AC1

A12 L11 K10 C12 U3

EC_SMI# PCH_GPIO35 PCH_GPIO36 PCH_GPIO37

SATA_RCOMP PCH_SATALED#

SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3

SATA_TN0/PETN6_L3 SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2

SATA_TN1/PETN6_L2 SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1

SATA_TN2/PETN6_L1

SATAAUDIO

SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0 SATA_RP3/PERP6_L0

SATA_TN3/PETN6_L0 SATA_TP3/PETP6_L0

SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37

SATA_RCOMP

SATA_PRX_DTX_N0 <27> SATA_PRX_DTX_P0 <27> SATA_PTX_DRX_N0 <27> SATA_PTX_DRX_P0 <27>

SATA_PRX_DTX_N1 <27> SATA_PRX_DTX_P1 <27> SATA_PTX_DRX_N1 <27> SATA_PTX_DRX_P1 <27>

EC_SMI# <25> PCH_GPIO35 <9> PCH_GPIO36 <9> PCH_GPIO37 <9>

within 500 mils

1 2

R43 3.01K_0402_1%R43 3.01K_0402_1%

PCH_SATALED# <9>

HDD

mSATA

+1.05VS_ASATA3PLL

+3VALW_PCH

B B

HDA_SDOUT

ME debug mode,t his signal has a weak internal PD * Low = Disable d (Default) High = Enabled [Flash Descript or Security Ove ride]

A A

R1239 1K_0402_5%@R1239 1K_0402_5%@

R86 51_0402_5%@R86 51_0402_5%@

1 2

HDA_SDOUT

HDA_SDOUT_AUDIO<23>

HDA_SYNC_AUDIO<23> HDA_RST_AUDIO#<23>

9/28

PCH_JTAG_TCK

SMT

5

4

HDA_BITCLK_AUDIO<23>

C5205 68P_0402_50V8J

68P_0402_50V8J

RF

ME_FLASH<25>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

EMI

RP14

EMI@RP14

EMI@ 1 8 2 7 3 6 4 5

33_8P4R_5%

1

@C5205

@

2

1 2

R53 0_0402_5%@R53 0_0402_5%@

2011/12/13 2012/12/13

3

HDA_SDOUT HDA_SYNC HDA_RST# HDA_BIT_CLK

Compal Secret Data

Deciphered Date

2

+3VS

1 2

R99 10K_0402_5%R99 10K_0402_5%

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

HSW MCP(3/11) RTC,SATA,XDP

LA-A321PR02

EC_SMI#

1

0.2

6 46Thursday, March 14, 2013

0.2

5

4

3

2

1

HASWELL_MCP_E

U1F

C43

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

U2

PCIECLKRQ0/GPIO18

B41

CLKOUT_PCIE_N1

A41

CLKOUT_PCIE_P1

Y5

PCIECLKRQ1/GPIO19

C41

CLKOUT_PCIE_N2

B42

CLKOUT_PCIE_P2

AD1

PCIECLKRQ2/GPIO20

B38

CLKOUT_PCIE_N3

C37

CLKOUT_PCIE_P3

N1

PCIECLKRQ3/GPIO21

A39

CLKOUT_PCIE_N4

B39

CLKOUT_PCIE_P4

U5

PCIECLKRQ4/GPIO22

B37

CLKOUT_PCIE_N5

A37

CLKOUT_PCIE_P5

T2

PCIECLKRQ5/GPIO23

U1G

AU14

LAD0

AW12

LAD1

AY12

LAD2

AW11

LAD3

AV12

LFRAME

AA3

SPI_CLK

Y7

SPI_CS0

Y4

SPI_CS1

AC2

SPI_CS2

AA2

SPI_MOSI

AA4

SPI_MISO

Y6

SPI_IO2

AF1

SPI_IO3

+3VS

EMI@

1 2

+3VALW_PCH

PCH_GPIO18

CLK_PCIE_LAN# CLK_PCIE_LAN

CLK_PCIE_WLAN# CLK_PCIE_WLAN

PCH_GPIO21

CLK_PEG_VGA# CLK_PEG_VGA

1 2

R184 0_0402_5%@R184 0_0402_5%@

PCH_GPIO23

RP3

1 8 2 7 3 6 4 5

10K_8P4R_5%

LPC_FRAME#<25>

15_0402_5%

PCH_SPI_MOSI PCH_SPI_WP#

PCH_SPI_HOLD#

LPC_AD0<25> LPC_AD1<25> LPC_AD2<25> LPC_AD3<25>

PCH_SPI_CLKPCH_SPI_CLK_R0

R127

R128

1K_0402_1%

1 2

1K_0402_1%

VGA_CLKREQ#_R

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME#

PCH_SPI_CS0#

PCH_SPI_MOSI PCH_SPI_MISO

PCH_SPI_WP#

PCH_SPI_HOLD#

PCH_GPIO18<9>

GLAN

D D

WLAN

dGPU

+3VS

12

R101

R101 10K_0402_5%

10K_0402_5%

UMA@

R1443

R1443 10K_0402_5%

C C

10K_0402_5%

PX@

1 2

CLK_PCIE_LAN#<24> CLK_PCIE_LAN<24> LAN_CLKREQ#<24>

CLK_PCIE_WLAN#<28> CLK_PCIE_WLAN<28> WLAN_CLKREQ#<28>

CLK_PEG_VGA#<16> CLK_PEG_VGA<16> VGA_CLKREQ#<17>

PCH_GPIO23<9>

VGA_CLKREQ#_R

EMI

R106

1

C5206

C5206 68P_0402_50V8J

68P_0402_50V8J

@

RF

2

CHKLIST1.0

B B

PCH_SPI_MOSI_0 PCH_SPI_WP0#

PCH_SPI_HOLD0#

2 SPI Device = 33 ohm 1 SPI Device = 15 ohm

RP4

1 8 2 7 3 6 4 5

15_8P4R_5%

HASWELL_MCP_E

CLOCK

SIGNALS

6 OF 19

HASWELL_MCP_E

LPC

SPI C-LINK

7 OF 19

SMBUS

XTAL24_IN

XTAL24_OUT

RSVD RSVD

DIFFCLK_BIASREF

TESTLOW_C35 TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8

CLKOUT_LPC_0 CLKOUT_LPC_1

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

Rev1p2

SMBALERT/GPIO11

SMBCLK

SMBDATA

SML0ALERT/GPIO60

SML0CLK

SML1ALERT/PCHHOT/GPIO73

SML0DATA

SML1CLK/GPIO75

SML1DATA/GPIO74

CL_CLK

CL_DATA

CL_RST

Rev1p2

A25 B25

K21 M21 C26

C35 C34 AK8 AL8

AN15 AP15

B35 A35

AN2 AP2 AH1 AL2 AN1 AK1 AU4 AU3 AH3

AF2 AD2 AF4

XTAL24_IN XTAL24_OUT

XCLK_BIASREF

CLKOUT_LPC0

CLK_BCLK_ITP# CLK_BCLK_ITP

SMBCLK SMBDATA PCH_GPIO60 SML0CLK SML0DATA PCH_GPIO73 SML1CLK SML1DATA

1 2

R91 3.01K_0402_1%R91 3.01K_0402_1%

1 2

R92 10K_0402_5%R92 10K_0402_5%

1 2

R93 10K_0402_5%R93 10K_0402_5%

1 2

R100 10K_0402_5%R100 10K_0402_5%

1 2

R95 10K_0402_5%R95 10K_0402_5%

R96 22_0402_5%R96 22_0402_5%

SMT

T18@ T18@ T19@ T19@ T20@ T20@

12

T21@ T21@ T26@ T26@

RF

PCH_GPIO11 <9>

PCH_GPIO60 <9>

PCH_GPIO73 <9>

V0.2

+1.05VS_AXCK_LCPLL

1

C5207

@C5207

@

68P_0402_50V8J

2

SMBus :SPD/PCIe/Security/TP

FootPrint :DMN66D0LDW-7_SOT363-6

SMBDATA

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6 Q3A

Q3A

SMBCLK

V0.2

SMBDATA PCH_SMB_DATA

SMBCLK PCH_SMB_CLK

SML1 Bus :EC/Sensors

FootPrint :DMN66D0LDW-7_SOT363-6

SML1CLK

SML1DATA

+3VS

2

@

6 1

@

3 4

Q3B 2N 7002KDWH_SOT363-6

1 2

@

R157 0_0402_5%

1 2

@

R158 0_0402_5%

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6 Q2417A

Q2417A

Q2417B 2N7002KDWH_SOT363-6

SML1CLK

SML1DATA

1

2

R132 2.2K_0402_5%R132 2.2K_0402_5%

1 2

R133 2.2K_0402_5%R133 2.2K_0402_5%

5

1 2

+3VS

2

@

6 1

@

3 4

1 2

@

R160 0_0402_5%

1 2

@

R161 0_0402_5%

V0.2

12

R871M_0402_5% R871M_0402_5%

Y2

24MHZ_12PF_7V24000020

1

GND

C6

15P_0402_50V8J

GND

2

CK_LPC_KBC <25>

+3VS

PU 2.2K at EC s ide (+3VS)

5

EC_SMB_CK2

EC_SMB_DA2

4

XTAL24_IN

XTAL24_OUT

3

1

C7

15P_0402_50V8J

2

PCH_SMB_DATA <15,28,31>

PCH_SMB_CLK <15,28,31>

EC_SMB_CK2 <17,25,29,31>

EC_SMB_DA2 <17,25,29,31>

@

RP13

SPI1 ROM ( 8MByte )

U10

PCH_SPI_CS0# PCH_SPI_MISO_0 PCH_SPI_WP0#

PCH_SPI_MISO PCH_SPI_MOSI_0 PCH_SPI_CLK_R0 PCH_SPI_CS0#

5

R108

1 2

15_0402_5%

PCH_SPI_MISO

A A

PCH_SPI_MISO<25> PCH_SPI_MOSI_0<25> PCH_SPI_CLK_R0<25> PCH_SPI_CS0#<25>

1

CS#

2

DO(IO1)

3

WP#(IO2)

4

GND

W25Q64FVSSIQ_SO8

SPI ROM 8MB 1st: SA000039A30 - Winbond

W25Q64FVSSIQ_SO8

VCC

HOLD#(IO3)

CLK

DI(IO0)

8 7 6 5

4

PCH_SPI_HOLD0#

PCH_SPI_CLK_R0

PCH_SPI_MOSI_0

RA39

CA80

CA80 22P_0402_50V8J

22P_0402_50V8J

@

@RA39

@

EMI

12

33_0402_5%

+3VALW_PCH

1

C8

0.1U_0402_16V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2011/12/13 2012/12/13

Compal Secret Data

Deciphered Date

2

SMBCLK SMBDATA SML1DATA SML1CLK

SML0CLK SML0DATA

1 8 2 7 3 6 4 5

2.2K_0804_8P4R_5%

1 2

R122 2.2K_0402_5%R122 2.2K_0402_5%

1 2

R123 2.2K_0402_5%R123 2.2K_0402_5%

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

HSW MCP(4/11) CLK,SPI,SMBUS

LA-A321PR02

+3VALW_PCH

1

7 46Thursday, March 14, 2013

0.2

5

D D

C C

PCH_PWROK APWROK_R

ACIN<17,25,33,35>

1 2

@

R146 0_0402_5%

D2

1 2

RB751V-40_SOD323-2

V0.2

+3VALW_PCH

12

R643

R643 200K_0402_5%

200K_0402_5%

AC_PRESENT_R

BIOS

4

Note: SUSACK# a nd SUSWARN# can be tied togeth er if EC does not wan t to involve in the handshake mechanism for the Deep Sl eep state entry and exit

CAN be NC ,if n ot support Deep Sx

T117@T117

@

1 2

PCH_GPIO30<9> SYS_RESET#<9> SYS_PWROK<25> PCH_PWROK<25>

EC_RSMRST#<25>

PBTN_OUT#<25>

PCH_GPIO72<9>

PCH_GPIO29<9>

ESD

R135 0_0402_5%@R 135 0_0402_5%@

ESD@

12

C2223 100P_0402_50V8J

1 2

R149 10K_0402_5%R149 10K_0402_5%

PCH_BATLOW# Nee d pull high to VCCDSW3_3 (If no deep Sx , connect to VC CSUS3_3)

R150

INVPWM<29,4> PCH_ENBKL<25> PCH_ENVDD<29>

WLBT_OFF_5#<2 8,9>

DGPU_PWR_EN<18,25,40,41>

DGPU_HOLD_RST#<16>

WLBT_OFF_51#<28,9>

TS_ON<29,9> PCH_GPIO52<9> PCH_GPIO54<9>

PCH_GPIO51<9> PCH_GPIO53<9>

R150

TS_ON PCH_GPIO52 PCH_GPIO54

PCH_GPIO53

T109@T109@

0_0402_5%

1 2

SYS_RESET# SYS_PWROK PCH_PWROK APWROK_R PLT_RST#

EC_RSMRST# PCH_GPIO30 PBTN_OUT# AC_PRESENT_R PCH_GPIO72

PCH_GPIO29

T27 @T27 @

EDP_BKCTL

3

U1H

AK2

SUSACK

AC3

SYS_RESET

AG2

SYS_PWROK

AY7

PCH_PWROK

AB5

APWROK

AG7

PLTRST

AW6

RSMRST

AV4

SUSWARN/SUSPW RDNACK/GPIO30

AL7

PWRBTN

AJ8

ACPRESENT/GPIO31

AN4

BATLOW/GPIO72

AF3

SLP_S0

AM5

SLP_WLAN/GPIO29

U1I

B8

EDP_BKLCTL

A9

EDP_BKLEN

C6

EDP_VDDEN

U6

PIRQA/GPIO77

P4

PIRQB/GPIO78

N4

PIRQC/GPIO79

N2

PIRQD/GPIO80

AD4

PME

U7

GPIO55

L1

GPIO52

L3

GPIO54

R5

GPIO51

L4

GPIO53

HASWELL_MCP_E

SYSTEM POWER MANAGEMENT

HASWELL_MCP_E

eDP SIDEBAND

GPIO

DPWROK: Tired t oghter with RSM RST# that do not sup port Deep Sx

DSWVRMEN

DPWROK

WAKE

CLKRUN/GPIO32

SUS_STAT/GPIO61

SUSCLK/GPIO62

SLP_S5/GPIO63

SLP_S4 SLP_S3

SLP_A SLP_SUS SLP_LAN

Rev1p2

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPB_AUXN

DDPC_AUXN

DDPB_AUXP DDPC_AUXP

DDPB_HPD DDPC_HPD

EDP_HPD

Rev1p2

8 OF 19

DISPLAY

2

AW7 AV5 AJ5

V5 AG4 AE6 AP5

AJ6 AT4 AL5 AP4 AJ7

B9 C9 D9

DDI2_CTRL_CK

D11

DDI2_CTRL_DATA

C5 B6 B5 A6

C8 A8 D6

DSWODVRENSUSACK#_R DPWROK PCH_PCIE_WAKE#

PCH_GPIO32

SUSCLK PM_SLP_S5#

PM_SLP_S4# PM_SLP_S3# PM_SLP_A#

DSWODVREN - On Die DSW VR Enab le

H：Enable(DEFAULT)

*

L：Disable

1 2

R134 330K_0402_5%R134 330K_0402_5%

1 2

R139 330K_0402_5%@R139 330K_0402_5%@

1 2

R148 0_0402_5%@R 148 0_0402_5%@

T114@T114

T115@T115

@

T120@ T120@ T110@ T110@ T112@ T1 12@

DDI2_CTRL_CK <30>

DDI2_CTRL_DATA <30>

DDI2_HDMI_HPD <30> EDP_HPD <29>

T116@T116

@

+RTCVCC

EC_RSMRST#

PCH_PCIE_WAKE# <28,9>

PCH_GPIO32 <9> PCH_GPIO61 <9> SUSCLK <25> PM_SLP_S5# <25>

PM_SLP_S4# <25> PM_SLP_S3# <25>

DDI1_CTRL_DATADDI1_CTRL_DATA

1

@

1 2

R310 2.2K_0402_5%

DDPB_CTRLDATA: Port B Detected DDPC_CTRLDATA: Port C Detected

1: Port B or C is detected

*

0: Port B or C is not detected (Have internal PD)

+3VS

9 OF 19

B B

R155 0_0402_5%@R155 0_0402_5%@

V0.2

U5

PLT_RST#

U74AHC1G08G-AL5-R_SOT353-5

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

U5

3

12

+3VS

5

2

P

B

4

Y

1

A

2011/12/13 2012/12/13

12

G

3

R159

100K_0402_5%

Compal Secret Data

PLT_RST_BUF# <16,24,25,28>

Deciphered Date

Rev1p2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HSW MCP(5/11) PM,GPIO,DDI

LA-A321PR02

1

8 46Thursday, March 14, 2013

0.2

5

D D

+3VS

1 8 2 7 3 6 4 5

1 8

R105 10K_0402_5%@R105 10K_0402_5%@

+3VALW_PCH

2 7 3 6 4 5

1 8 2 7 3 6 4 5

1 2

C C

V0.2

B B

A A

PCH_GPIO39

PCH_GPIO83

RP21 10K_8P4R_5%RP21 10K_8P4R_5%

PCH_GPIO76

RP22 10K_8P4R_5%RP22 10K_8P4R_5%

PCH_GPIO71

RP23 10K_8P4R_5%RP23 10K_8P4R_5%

PCH_GPIO48 PCH_GPIO16 PCH_GPIO49

RP24 10K_8P4R_5%RP24 10K_8P4R_5%

PCH_GPIO67

RP25 10K_8P4R_5%RP25 10K_8P4R_5%

PCH_GPIO33

RP26 10K_8P4R_5%RP26 10K_8P4R_5%

1 8 2 7 3 6 4 5

RP29 10K_8P4R_5%RP29 10K_8P4R_5%

1 8 2 7 3 6 4 5

RP32 10K_8P4R_5%RP32 10K_8P4R_5%

1 8 2 7 3 6 4 5

RP27 10K_8P4R_5%RP27 10K_8P4R_5%

1 8 2 7 3 6 4 5

RP30 10K_8P4R_5%RP30 10K_8P4R_5%

V0.2

SERIRQ

KB_RST#

PCH_GPIO59

PCH_GPIO46 EC_SCI#

PCH_GPIO14

PCH_GPIO57

PCH_GPIO13 PCH_GPIO8

PCH_GPIO9 PCH_GPIO47

PCH_GPIO51 <8>

PCH_GPIO32 <8>

WLBT_OFF_51# <28,8>

PCH_GPIO23 <7>

PCH_GPIO53 <8> PCH_GPIO36 <6>

PCH_GPIO35 <6>

PCH_GPIO18 <7>

TS_ON <29,8> WLBT_OFF_5# <28,8>

PCH_GPIO52 <8> PCH_SATALED# <6>

PCH_GPIO54 <8>

PCH_GPIO30 <8> PCH_GPIO43 <10> PCH_GPIO73 <7>

PCH_GPIO42 <10>

PCH_GPIO41 <10>

USB_OC0# <10,26,28> PCH_GPIO60 <7>

4

PCH_GPIO76 PCH_GPIO8

@

1 2

R295

EC_LID_OUT#<25 >

DGPU_PWROK<41>

+3VALW_PCH

R98 10K_0402_5%R98 10K_0402_5%

R295

0_0402_5%

1 8 2 7 3 6 4 5

RP37 10K_8P4R_5%RP37 10K_8P4R_5%

1 2

PCH_GPIO27<24>

EC_SCI#<25>

SPKR<23>

PCH_GPIO28 PCH_GPIO26

PCH_GPIO45

PCH_GPIO12 PCH_GPIO15 PCH_GPIO16 DGPU_PWROK PCH_GPIO24 PCH_GPIO27 PCH_GPIO28 PCH_GPIO26

PCH_GPIO56 PCH_GPIO57 PCH_GPIO58 PCH_GPIO59 PCH_GPIO44 PCH_GPIO47 PCH_GPIO48 PCH_GPIO49

PCH_GPIO71 PCH_GPIO13 PCH_GPIO14 PCH_GPIO25 PCH_GPIO45 PCH_GPIO46

PCH_GPIO9 EC_SCI# PCH_GPIO33

PCH_GPIO38 PCH_GPIO39 SPKR

3

PCH_GPIO61 <8>

PCH_GPIO11 <7>

U1J

P1

BMBUSY/GPIO76

AU2

GPIO8

AM7

LAN_PHY_PWR_CTRL/GPIO12

AD6

GPIO15

Y1

GPIO16

T3

GPIO17

AD5

GPIO24

AN5

GPIO27

AD7

GPIO28

AN3

GPIO26

AG6

GPIO56

AP1

GPIO57

AL4

GPIO58

AT5

GPIO59

AK4

GPIO44

AB6

GPIO47

U4

GPIO48

Y3

GPIO49

P3

GPIO50

Y2

HSIOPC/GPIO71

AT3

GPIO13

AH4

GPIO14

AM4

GPIO25

AG5

GPIO45

AG3

GPIO46

AM3

GPIO9

AM2

GPIO10

P2

DEVSLP0/GPIO33

C4

SDIO_POWER_EN/GPIO70

L2

DEVSLP1/GPIO38

N5

DEVSLP2/GPIO39

V2

SPKR/GPIO81

HASWELL_MCP_E

GPIO

2

D60

THERMTRIP

SERIRQ

RSVD RSVD

Rev1p2

PCH_GPIO6

PCH_GPIO7

PCH_GPIO65

V4 T4 AW15 AF20 AB21

R6 L6 N6 L8 R7 L5 N7 K2 J1 K3 J2 G1 K4 G2 J3 J4 F2 F3 G4 F1 E3 F4 D3 E4 C3 E2

PCH_OPI_RCOMP

GSPI0_CS/GPIO83

GSPI0_CLK/GPIO84 GSPI0_MISO/GPIO85 GSPI0_MOSI/GPIO86

GSPI1_CS/GPIO87

GSPI1_CLK/GPIO88 GSPI1_MISO/GPIO89

GSPI_MOSI/GPIO90 UART0_RXD/GPIO91

UART0_TXD/GPIO92 UART0_RTS/GPIO93 UART0_CTS/GPIO94

UART1_RXD/GPIO0 UART1_TXD/GPIO1 UART1_RST/GPIO2 UART1_CTS/GPIO3

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

SDIO_D0/GPIO66 SDIO_D1/GPIO67 SDIO_D2/GPIO68 SDIO_D3/GPIO69

1 2

RCIN/GPIO82

I2C0_SDA/GPIO4 I2C0_SCL/GPIO5 I2C1_SDA/GPIO6 I2C1_SCL/GPIO7

CPU/

CPU/ MISC

MISC

LPIO

10 OF 19

LPIO

10 OF 19

Need confirm PU value when sup port I2C TS.

+3VS

R114 10K_0402_5%R114 10K_0402_5%

R115 10K_0402_5%R115 10K_0402_5%

R116 10K_0402_5%R116 10K_0402_5%

+1.05VS_VTT

12

R179

1K_0402_1%

H_THERMTRIP#

SERIRQ PCH_OPIRCOMP

PCH_GPIO83

PCH_GPIO86 DGPU_PRSNT#

PCH_GPIO6 PCH_GPIO7

PCH_GPIO65 PCH_GPIO66 PCH_GPIO67

1 2

R185

PCH_GPIO86

49.9_0402_1%

H_THERMTRIP#

1 2

R710 1K_0402_1%@R710 1K_0402_1%@

1 2

R711 1K_0402_1%R711 1K_0402_1%

GSPI0_MOSI / GPIO86 : Boot BIOS Strap

1

KB_RST# <25>

SERIRQ <25>

V0.2

ESD

ESD@

1 2

C1313 100P_0402_50V8J

+3VS

1: LPC BUS

(Have internal PD)

1 2

R189 1K_0402_1%@R189 1K_0402_1%@

1 2

R712 1K_0402_1%

1K_0402_1%

PCH_GPIO15

@R712

@

+3VALW_PCH

+3VS +3VALW _PCH

1 8 2 7 3 6 4 5

RP33 10K_8P4R_5%RP33 10K_8P4R_5%

1 8 2 7 3 6 4 5

RP15 10K_8P4R_5%RP15 10K_8P4R_5%

1 8 2 7 3 6 4 5

RP31 10K_8P4R_5%RP31 10K_8P4R_5%

PCH_GPIO24

PCH_GPIO27 PCH_GPIO25 PCH_GPIO12

PCH_GPIO56 PCH_GPIO58 PCH_GPIO44

PCH_GPIO29 <8> PCH_GPIO37 <6> SYS_RESET# <8>

PCH_GPIO72 <8>

PCH_PCIE_WAKE# <28,8>

+3VS

DGPU_PRSNT#

VRAM ( X76 BOM ) 1GHz -> stuff 900 Hz -> un-stuff

1 2

R193 10K_0402_5%@R193 10K_0402_5%@

+3VS

1 2

1 UMA 0

R707

R707 10K_0402_5%

10K_0402_5%

UMA@

R708

R708 10K_0402_5%

10K_0402_5%

PX@

PCH_GPIO38

DIS

0: SPI BUS

*

PCH_GPIO66

SDIO_D0 / GPIO66 : Top-Block Swap Override

1: DISABLED

0: ENABLED*(Have internal PD)

+3VALW_PCH

GPIO15 : TLS Confidentiality

1: Intel ME TLS with confidentiality

0: Intel ME TLS with no confidentiality

*

(Have internal PD)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2011/12/13 2012/12/13

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HSW MCP(6/11) GPIO,LPIO

LA-A321PR02

1

0.2

9 46Thursday, March 14, 2013

0.2

5

D D

PCIE_CRX_GTX_N0<16> PCIE_CRX_GTX_P0<16>

PCIE_CTX_GRX_N0<16> PCIE_CTX_GRX_P0<16>

PCIE_CRX_GTX_N1<16> PCIE_CRX_GTX_P1<16>

dGPU

C C

WLAN

LAN

B B

PCIE_CTX_GRX_N1<16> PCIE_CTX_GRX_P1<16>

PCIE_CRX_GTX_N2<16> PCIE_CRX_GTX_P2<16>

PCIE_CTX_GRX_N2<16> PCIE_CTX_GRX_P2<16>

PCIE_CRX_GTX_N3<16> PCIE_CRX_GTX_P3<16>

PCIE_CTX_GRX_N3<16> PCIE_CTX_GRX_P3<16>

PCIE_PRX_DTX_N3<28> PCIE_PRX_DTX_P3<28>

PCIE_PTX_C_DRX_N3<28> PCIE_PTX_C_DRX_P3<28>

PCIE_PRX_DTX_N2<24> PCIE_PRX_DTX_P2<24>

PCIE_PTX_C_DRX_N2<24> PCIE_PTX_C_DRX_P2<24>

+1.05VS_AUSB3PLL

R235 3.01K_0402_1%R235 3.01K_0402_1%

4

0.1U_0402_16V7K

CC250 CC243 0.1U_0402_16V7KPX@CC243 0.1U_0402_16V7KPX@

CC245 0.1U_0402_16V7KPX@CC245 0.1U_0402_16V7KPX@ CC247 0.1U_0402_16V7KPX@CC247 0.1U_0402_16V7KPX@

CC249 0.1U_0402_16V7KPX@CC249 0.1U_0402_16V7KPX@ CC244

CC244

CC246

CC246 CC248

CC248

0.1U_0402_16V7K

PX@CC250

PX@1 2

1 2

1 2 1 2

1 2

0.1U_0402_16V7KPX@

1 2

0.1U_0402_16V7KPX@

1 2

0.1U_0402_16V7KPX@

0.1U_0402_16V7KPX@1 2

1 2

C29 0.1U_0402_16V7KC29 0.1U_0402_16V7K

1 2

C30 0.1U_0402_16V7KC30 0.1U_0402_16V7K

1 2

C856 0.1U_0402_16V7KC856 0.1U_0402_16V7K

1 2

C857 0.1U_0402_16V7KC857 0.1U_0402_16V7K

1 2

PCIE_CRX_GTX_N0 PCIE_CRX_GTX_P0

PCIE_PTX_DRX_N5_L0

PCIE_PTX_DRX_P5_L0

PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P1

PCIE_PTX_DRX_N5_L1 PCIE_PTX_DRX_P5_L1

PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P2

PCIE_PTX_DRX_N5_L2 PCIE_PTX_DRX_P5_L2

PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P3

PCIE_PTX_DRX_N5_L3 PCIE_PTX_DRX_P5_L3

PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3

PCIE_PTX_DRX_N3 PCIE_PTX_DRX_P3

PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2

PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2

PCIE_RCOMP

F10

PERN5_L0

E10

PERP5_L0

C23

PETN5_L0

C22

PETP5_L0

F8

PERN5_L1

E8

PERP5_L1

B23

PETN5_L1

A23

PETP5_L1

H10

PERN5_L2

G10

PERP5_L2

B21

PETN5_L2

C21

PETP5_L2

E6

PERN5_L3

F6

PERP5_L3

B22

PETN5_L3

A21

PETP5_L3

G11

PERN3

F11

PERP3

C29

PETN3

B30

PETP3

F13

PERN4

G13

PERP4

B29

PETN4

A29

PETP4

G17

PERN1/USB3RN3

F17

PERP1/USB3RP3

C30

PETN1/USB3TN3

C31

PETP1/USB3TP3

F15

PERN2/USB3RN4

G15

PERP2/USB3RP4

B31

PETN2/USB3TN4

A31

PETP2/USB3TP4

E15

RSVD

E13

RSVD

A27

PCIE_RCOMP

B27

PCIE_IREF

3

HASWELL_MCP_E

U1K

HASWELL_MCP_E

11 OF 19

PCIe

USB3.0 P3 / PCIE P1

USB3.0 P4 / PCIE P2

USB

USB3.0 P1

USB3.0 P2

USB2N0 USB2P0

USB2N1 USB2P1

USB2N2 USB2P2

USB2N3 USB2P3

USB2N4 USB2P4

USB2N5 USB2P5

USB2N6 USB2P6

USB2N7 USB2P7

USB3RN1 USB3RP1

USB3TN1 USB3TP1

USB3RN2 USB3RP2

USB3TN2 USB3TP2

USBRBIAS USBRBIAS

RSVD RSVD

OC0/GPIO40 OC1/GPIO41 OC2/GPIO42 OC3/GPIO43

Rev1p2

AN8 AM8

AR7 AT7

AR8 AP8

AR10 AT10

AM15 AL15

AM13 AN13

AP11 AN11

AR13 AP13

G20 H20

C33 B34

E18 F18

B33 A33

AJ10 AJ11 AN10 AM10

AL3 AT1 AH2 AV3

USBRBIAS

USB_OC0# PCH_GPIO41 PCH_GPIO42 PCH_GPIO43

2

USB20_N0 USB20_P0

USB20_N1 USB20_P1

USB20_N2 USB20_P2

USB20_N3 USB20_P3

USB20_N4 USB20_P4

USB20_N5 USB20_P5

USB20_N6 USB20_P6

1 2

R233 22.6_0402_1%R233 22.6_0402_1%

USB20_N0 <26> USB20_P0 <26>

USB20_N1 <28> USB20_P1 <28>

USB20_N2 <26> USB20_P2 <26>

USB20_N3 <26> USB20_P3 <26>

USB20_N4 <29> USB20_P4 <29>

USB20_N5 <29> USB20_P5 <29>

USB20_N6 <28> USB20_P6 <28>

USB3_RX2_N <28>

USB3_RX2_P <28>

USB3_TX2_N <28> USB3_TX2_P <28>

1

USB2 IO (Sub Board)

USB2/3 IO (Main Board)

USB2 IO (Sub Board)

Card Reader

Touch Screen

Camera

Mini Card(WLAN+BT)

USB2/3 (Main Board)

CAD note: Route single-end 50-ohms and max 450-mils length. Avoid routing next to clock pins or under stitching capacitors. Recommended minimum spacing to other signal traces is 15 mils

USB_OC0# <26,28,9> PCH_GPIO41 <9> PCH_GPIO42 <9> PCH_GPIO43 <9>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2011/12/13 2012/12/13

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HSW MCP(7/11) PCIE,USB

LA-A321PR02

1

0.2

10 46Thursday, March 14, 2013

0.2

5

D D

VCCST_PG_EC<25>

VCCST_PG_EC

Define EC OD pin, need double confirm.

V0.2

ESD

1 2

C1314 100P_0402_50V8J

C C

SVID ALERT

+1.05VS_VTT

12

VR_SVID_ALRT#<42>

Place the PU resistors close to CPU

R252

R252 75_0402_5%

75_0402_5%

R254

R254 43_0402_1%

43_0402_1%

12

H_CPU_SVIDALRT#

SVID DATA

+1.05VS_VTT

Place the PU resistors close to CPU

12

R256

R256 110_0402_5%

B B

R257

VR_SVID_DAT<42>

VCCSENSE<42>

A A

VSSSENSE<13,42>

5

R257

0_0402_5%@

+CPU_CORE

12

110_0402_5%

12

H_CPU_SVIDDATA

R256: CRB r0.7 changed from 130 Ohms to 110 Ohms

R12

R12 100_0402_1%

100_0402_1%

VCCSENSE

VSSSENSE

R13

R13 100_0402_1%

100_0402_1%

CAD Note: PU resistor should be close to CPU

CAD Note: PD resistor should be close to CPU

+1.05VS_VTT

ESD@

12

R286

R286 10K_0402_5%

10K_0402_5%

4

VR_SVID_CLK<42>

VR_ON<42>

VGATE<42>

RF

C5212

@C5212

@

68P_0402_50V8J

+1.05VS_VTT

R253

@

150_0402_1%

1 2

R255 10K_0402_5%

10K_0402_5%

1 2

4

R253: CPU_PWR_DEBUG CRB mount Check list ,XDP use only

CPU_PWR_DEBU G

@R255

@

3

10U_0603_6.3V6M

1

C40

2

Deciphered Date

AH26

AJ31 AJ33

AJ37 AN33 AP43 AR48 AY35 AY40 AY44 AY50

AC58

AB23

AD23 AA23 AE59

AD60 AD59 AA59 AE60 AC59 AG58

AC22 AE22 AE23

AB57 AD57 AG57

1

2

L59

J58

F59 N58

E63

A59 E20

L62 N63 L63 B59 F60 C59

D63 H59 P62 P60 P61 N59 N61 T59

U59 V59

C24 C28 C32

10U_0603_6.3V6M

+1.35V

+CPU_CORE

T87@T87

@

+VCCIOA_OUT

VR_SVID_CLK

1

2

+CPU_CORE

+1.35V

VDDQ DECOUPLING

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M C36

C36

C35

1

2

CRB: +1.35V : 470UF/2V/7343 *2 (Un-mount) 10UF/6.3V/0603 * 6

2.2UF/6.3V/0402 * 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

VCCSENSE

+VCCIO_OUT_R

+1.05VS_VTT

2.2U_0402_6.3V6M

C37

1

2

2011/12/13 2012/12/13

T38 @T38 @

H_CPU_SVIDALRT# VR_SVID_CLK H_CPU_SVIDDATA VCCST_PG_EC

CPU_PWR_DEBU G

T39 @T39 @ T40 @T40 @ T41 @T41 @ T42 @T42 @ T43 @T43 @ T44 @T44 @ T45 @T45 @ T46 @T46 @ T47 @T47 @ T48 @T48 @ T49 @T49 @ T50 @T50 @ T51 @T51 @

10U_0603_6.3V6M

C38

1

C39

2

Compal Secret Data

U1L

RSVD RSVD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VCC RSVD RSVD

VCC_SENSE RSVD VCCIO_OUT VCCIOA_OUT RSVD RSVD RSVD

VIDALERT VIDSCLK VIDSOUT VCCST_PWRGD VR_EN VR_READY

VSS PWR_DEBUG VSS RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

VCCST VCCST VCCST

VCC VCC VCC VCC VCC VCC

10U_0603_6.3V6M

1

C41

2

HASWELL_MCP_E

12 OF 19

HSW ULT POWER

10U_0603_6.3V6M

1

C42

2

C45

C43

2

Custom

Date: Sheet of

1

+CPU_CORE

C36

VCC

C40

VCC

C44

VCC

C48

VCC

C52

VCC

C56

VCC

E23

VCC

E25

VCC

E27

VCC

E29

VCC

E31

VCC

E33

VCC

E35

VCC

E37

VCC

E39

VCC

E41

VCC

E43

VCC

E45

VCC

E47

VCC

E49

VCC

E51

VCC

E53

VCC

E55

VCC

E57

VCC

F24

VCC

F28

VCC

F32

VCC

F36

VCC

F40

VCC

F44

VCC

F48

VCC

F52

VCC

F56

VCC

G23

VCC

G25

VCC

G27

VCC

G29

VCC

G31

VCC

G33

VCC

G35

VCC

G37

VCC

G39

VCC

G41

VCC

G43

VCC

G45

VCC

G47

VCC

G49

VCC

G51

VCC

G53

VCC

G55

VCC

G57

VCC

H23

VCC

J23

VCC

K23

VCC

K57

VCC

L22

VCC

M23

VCC

M57

VCC

P57

VCC

U57

VCC

W57

VCC

Rev1p2

V0.2

ESD

+1.05VS_VTT

1

C84

@ C84

@

C91

@ C91

@

+CPU_CORE

+3VS

Title

Size Document Number Rev

LA-A321PR02

22U_0603_6.3V6M

2

1 2

C80 22U_0603_6.3V6M

1 2

C83 22U_0603_6.3V6M

1 2

C119 22U_0603_6.3V6M

1 2

C118 22U_0603_6.3V6M

Compal Electronics, Inc.

HSW MCP(8/11) Power

V0.2

ESD

+CPU_CORE

TOPBOT

1

C77

C79

22U_0603_6.3V6M

2

ESD@

V0.2

ESD

@

ESDV0.2

@

+1.05VS_VTT

11 46Thursday, March 14, 2013

1

11 46Thursday, March 14, 2013

0.2

5

D D

4

3

2

1

Check Power Source

+1.05VS_VTT +1.05VS_AUSB3PLL

2.2UH_LQM2MPN2R2NG0L_30%

1 2

L3

C C

B B

A A

L3

2.2UH_LQM2MPN2R2NG0L_30%

L4

2.2UH_LQM2MPN2R2NG0L_30%

+1.05VS_VTT

1 2

L1

1 2

L2

1 2

L5

+3VALW_PCH

+1.05VS_VTT

+3VALW_PCH

+1.05VS_VTT

+1.05VS_ASATA3PLL

+1.05VS_APLLOPI

+1.05VS_AXCK_DCB

+1.05VS_AXCK_LCPLL

C49 1U_0402_6.3V6KC49 1U_0402_6.3V6K C50 1U_0402_6.3V6KC50 1U_0402_6.3V6K

C81 1U_0402_6.3V6K

C78 22U_0603_6.3V6MC 78 22U_0603_6.3V6M

C82 22U_0603_6.3V6MC82 22U_0603_6.3V6M

+3VS

C87 1U_0402_6.3V6KC87 1U_0402_6.3V6K

C88 1U_0402_6.3V6KC88 1U_0402_6.3V6K

C75 1U_0402_6.3V4ZC75 1U_0402_6.3V4Z

5

Close to N8

1 2

C53 1U_0402_6.3V6K@C 53 1U_040 2_6.3V6K@

1 2

C58 1U_0402_6.3V6KC58 1U_0402_6.3V6K

1 2

C59 100U_1206_6.3V6MC59 100U_1206_6.3V6M

1 2

C63 1U_0402_6.3V6KC63 1U_0402_6.3V6K

1 2

C65 100U_1206_6.3V6MC65 100U_1206_6.3V6M

1 2

C69 1U_0402_6.3V6KC69 1U_0402_6.3V6K

1 2

C70 100U_1206_6.3V6M@C70 100U_1206_6.3V6M@

1 2

C116 1U_0402_6.3V6KC116 1U_0402_6.3V6K

1 2

C117 100U_1206_6.3V6MC117 100U_1206_6.3V6M

1 2

C85 1U_0402_6.3V6KC85 1U_0402_6.3V6K

1 2

C86 100U_1206_6.3V6MC86 100U_1206_6.3V6M

Close to K9,M9

1 2 1 2

Close to AH10

1 2

@

Close to AC9/AA9/AE20/AE21

1 2

Close to V8

1 2

Close to J17

1 2

Close to R21

1 2

Close to AH14

12

+1.05VS_VTT

+1.05VS_AUSB3PLL

+1.05VS_ASATA3PLL

+1.05VS_APLLOPI

T91 @T91 @

+3VALW_PCH

T94 @T94 @

+3VALW_PCH

+3VS

+1.05VS_AXCK_DCB

+1.05VS_AXCK_LCPLL

+1.05VS_VTT +1.05VS_VTT

+3VALW_PCH

4

AA21

W21

AH14

AH13

AC9

AH10

M20

AE20 AE21

K9

L10

M9 N8

P9 B18 B11

Y20

J13

AA9

V8

W9

J18 K19 A20

J17 R21 T21 K18

V21

U1M

VCCHSIO VCCHSIO VCCHSIO VCC1_05 VCC1_05 VCCUSB3PLL VCCSATA3PLL

RSVD VCCAPLL VCCAPLL

DCPSUS3

VCCHDA

DCPSUS2

VCCSUS3_3 VCCSUS3_3 VCCDSW3_3 VCC3_3 VCC3_3

VCCCLK VCCCLK VCCACLKPLL VCCCLK VCCCLK VCCCLK RSVD RSVD RSVD VCCSUS3_3 VCCSUS3_3

HASWELL_MCP_E

mPHY

OPI

USB3

AXALIA/HDA

VRM/USB2/AZALIA

13 OF 19

GPIO/LCC

LPT LP POWER

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

THERMAL SENSOR

Issued Date

RTC

SPI

CORE

SDIO/PLSS

SUS OSCILLATOR

USB2

3

DCPSUSBYP DCPSUSBYP

AH11

VCCSUS3_3

AG10

VCCRTC

AE7

DCPRTC

Y8

VCCSPI

AG14

VCCASW

AG13

VCCASW

J11

VCC1_05

H11

VCC1_05

H15

VCC1_05

AE8

VCC1_05

AF22

VCC1_05

AG19 AG20 AE9

VCCASW

AF9

VCCASW

AG8

VCCASW

AD10

DCPSUS1

AD8

DCPSUS1

J15

VCCTS1_5

K14

VCC3_3

K16

VCC3_3

U8

VCCSDIO

T9

VCCSDIO

AB8

DCPSUS4

AC20

RSVD

AG16

VCC1_05

AG17

VCC1_05

Rev1p2

2011/12/13 2012/12/13

1 2

C51 1U_0402_6.3V6KC51 1U_0402_6.3V6K

+VCCRTCEXT

+PCH_VCCDSW

C71 0.1U_0402_16V4ZC71 0.1U_0402_16V4Z

C73 1U_0402_6.3V6KC73 1U_0402_6.3V6K

T89 @T89 @

C76 1U_0402_6.3V6KC76 1U_0402_6.3V6K

1 2

C52 0.1U_0402_16V4ZC52 0.1U_0402_16V4Z

1 2

C57 0.1U_0402_16V4Z

@

1 2

C60 10U_0603_6.3V6MC 60 10U_0 603_6.3V6M

1 2

C61 1U_0402_6.3V6KC61 1U_0402_6.3V6K

1 2

C62 1U_0402_6.3V6KC62 1U_0402_6.3V6K

1 2

C66 22U_0603_6.3V6M@C66 22U_0603_6.3V6M@

1 2

C67 1U_0402_6.3V6KC67 1U_0402_6.3V6K

T95 @T95 @ T90 @T90 @

1 2

+1.05VS_VTT

1 2

Compal Secret Data

Deciphered Date

+1.05VS_VTT

+RTCVCC

+3VALW_PCH

+1.5VS +3VS

+3VS

2

+3VALW_PCH

C64

C64 1U_0402_6.3V6K

1U_0402_6.3V6K

1 2

18mA

Share ROM

+1.05VS_VTT

658mA

+1.05VS_VTT

+RTCVCC

1

C54

2

1U_0402_6.3V6K

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

HSW MCP(9/11) Power

LA-A321PR02

1

0.2

12 46Thursday, March 14, 2013

0.2

5

D D

HASWELL_MCP_E

U1N

A11

VSS

A14

VSS

A18

VSS

A24

VSS

A28

VSS

A32

VSS

A36

VSS

A40

VSS

A44

VSS

A48

VSS

A52

VSS

A56

VSS

AA1

VSS

AA58

VSS

AB10

VSS

AB20

VSS

AB22

VSS

AB7

C C

B B

AC61 AD21

AD63

AE10

AE58 AF11 AF12 AF14 AF15 AF17 AF18

AG11 AG21 AG23 AG60 AG61 AG62 AG63 AH17 AH19 AH20 AH22 AH24 AH28 AH30 AH32 AH34 AH36 AH38 AH40 AH42 AH44 AH49 AH51 AH53 AH55 AH57

AJ13 AJ14 AJ23 AJ25 AJ27 AJ29

AD3

AE5

AG1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

14 OF 19

4

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

Rev1p2

AJ35 AJ39 AJ41 AJ43 AJ45 AJ47 AJ50 AJ52 AJ54 AJ56 AJ58 AJ60 AJ63 AK23 AK3 AK52 AL10 AL13 AL17 AL20 AL22 AL23 AL26 AL29 AL31 AL33 AL36 AL39 AL40 AL45 AL46 AL51 AL52 AL54 AL57 AL60 AL61 AM1 AM17 AM23 AM31 AM52 AN17 AN23 AN31 AN32 AN35 AN36 AN39 AN40 AN42 AN43 AN45 AN46 AN48 AN49 AN51 AN52 AN60 AN63 AN7 AP10 AP17 AP20

AP22 AP23 AP26 AP29

AP31 AP38 AP39 AP48 AP52 AP54

AP57 AR11 AR15 AR17 AR23 AR31 AR33 AR39 AR43 AR49

AR52

AT13

AT35

AT37

AT40

AT42

AT43

AT46

AT49

AT61

AT62

AT63

AU16 AU18 AU20 AU22 AU24 AU26 AU28 AU30 AU33 AU51 AU53 AU55 AU57 AU59

AV14

AV16

AV20

AV24

AV28

AV33

AV34

AV36

AV39

AV41

AV43

AV46

AV49

AV51

AV55

AP3

AR5

AU1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

U1O

3

HASWELL_MCP_E

15 OF 19

Rev1p2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AV59 AV8 AW16 AW24 AW33 AW35 AW37 AW4 AW40 AW42 AW44 AW47 AW50 AW51 AW59 AW60 AY11 AY16 AY18 AY22 AY24 AY26 AY30 AY33 AY4 AY51 AY53 AY57 AY59 AY6 B20 B24 B26 B28 B32 B36 B4 B40 B44 B48 B52 B56 B60 C11 C14 C18 C20 C25 C27 C38 C39 C57 D12 D14 D18 D2 D21 D23 D25 D26 D27 D29 D30 D31

2

U1P

HASWELL_MCP_E

D33 D34 D35 D37 D38 D39 D41 D42 D43 D45 D46 D47 D49

D50 D51 D53 D54 D55 D57 D59 D62

E11 E17

G18 G22

H13

HASWELL_MCP_E

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

D5

VSS VSS VSS VSS VSS VSS VSS VSS VSS

D8

VSS VSS VSS

F20

VSS

F26

VSS

F30

VSS

F34

VSS

F38

VSS

F42

VSS

F46

VSS

F50

VSS

F54

VSS

F58

VSS

F61

VSS VSS VSS

G3

VSS

G5

VSS

G6

VSS

G8

VSS VSS

16 OF 19

VSS_SENSE

Rev1p2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS

VSS

H17 H57 J10 J22 J59 J63 K1 K12 L13 L15 L17 L18 L20 L58 L61 L7 M22 N10 N3 P59 P63 R10 R22 R8 T1 T58 U20 U22 U61 U9 V10 V3 V7 W20 W22 Y10 Y59 Y63

V58 AH46 V23 E62 AH16

1

VSSSENSE <11,42>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2011/12/13 2012/12/13

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HSW MCP(10/11) GND

LA-A321PR02

1

0.2

13 46Thursday, March 14, 2013

0.2

T105 @T105 @

T61 @T61 @

DC_TEST_AY2_AW2 DC_TEST_AY3_AW3

DC_TEST_AY61_AW61 DC_TEST_AY62_AW62

DC_TEST_A3_B3 DC_TEST_A61_B61 DC_TEST_B62_B63

DC_TEST_C1_C2

U1Q

AY2

DAISY_CHAIN_NCTF_AY2

AY3

DAISY_CHAIN_NCTF_AY3

AY60

DAISY_CHAIN_NCTF_AY60

AY61

DAISY_CHAIN_NCTF_AY61

AY62

DAISY_CHAIN_NCTF_AY62

B2

DAISY_CHAIN_NCTF_B2

B3

DAISY_CHAIN_NCTF_B3

B61

DAISY_CHAIN_NCTF_B61

B62

DAISY_CHAIN_NCTF_B62

B63

DAISY_CHAIN_NCTF_B63

C1

DAISY_CHAIN_NCTF_C1

C2

DAISY_CHAIN_NCTF_C2

U1S

HASWELL_MCP_E

17 OF 19

HASWELL_MCP_E

DAISY_CHAIN_NCTF_A3 DAISY_CHAIN_NCTF_A4

DAISY_CHAIN_NCTF_A60 DAISY_CHAIN_NCTF_A61

DAISY_CHAIN_NCTF_A62

DAISY_CHAIN_NCTF_AV1 DAISY_CHAIN_NCTF_AW1 DAISY_CHAIN_NCTF_AW2 DAISY_CHAIN_NCTF_AW3

DAISY_CHAIN_NCTF_AW61 DAISY_CHAIN_NCTF_AW62 DAISY_CHAIN_NCTF_AW63

Rev1p2

A3 A4

A60 A61 A62 AV1 AW1 AW2

DC_TEST_AY2_AW2

AW3

DC_TEST_AY3_AW3

AW61

DC_TEST_AY61_AW61

AW62

DC_TEST_AY62_AW62

AW63

DC_TEST_A3_B3

DC_TEST_A61_B61

1

HASWELL_MCP_E

U1R

T52@ T52@

T96@ T96@

T62@ T62@ T93@ T93@ T66@ T66@

T75@ T75@

AU44 AV44

AT2

RSVD RSVD RSVD

D15

RSVD

F22

RSVD

H22

RSVD

J21

RSVD

HASWELL_MCP_E

18 OF 19

RSVD RSVD RSVD RSVD

RSVD RSVD RSVD RSVD RSVD RSVD RSVD

Rev1p2

N23 R23 T23 U10

AL1 AM11 AP7 AU10 AU15 AW14 AY14

T92 @T92 @ T104 @T104 @ T67 @T67 @ T68 @T68 @ T69 @T69 @ T103 @T103 @ T86 @T86 @ T88 @T88 @ T73 @T73 @ T74 @T74 @

A A

T76 @T76 @ T77 @T77 @ T78 @T78 @ T79 @T79 @ T80 @T80 @ T81 @T81 @

T82 @T82 @ T83 @T83 @ T84 @T84 @ T85 @T85 @

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG18 CFG17 CFG19

CFG_RCOMP

TD_IREF

R275 49.9_0402_1%R275 49.9_0402_1%

R276 49.9_0402_1%R276 49.9_0402_1%

R277 8.2K_0402_5%R277 8.2K_0402_5%

AC60

CFG0

AC62

CFG1

AC63

CFG2

AA63

CFG3

AA60

CFG4

Y62

CFG5

Y61

CFG6

Y60

CFG7

V62

CFG8

V61

CFG9

V60

CFG10

U60

CFG11

T63

CFG12

T62

CFG13

T61

CFG14

T60

CFG15

AA62

CFG16

U63

CFG18

AA61

CFG17

U62

CFG19

V63

CFG_RCOMP

A5

RSVD

E1

RSVD

D1

RSVD

J20

RSVD

H18

RSVD

B12

TD_IREF

12

CFG_RCOMP

12

OPI_COMP

12

TD_IREF

RESERVED

19 OF 19

PROC_OPI_RCOMP

RSVD_TP RSVD_TP

RSVD

RSVD_TP RSVD_TP

RSVD_TP

RSVD

RSVD RSVD

VSS VSS

RSVD RSVD

Rev1p2

AV63 AU63

C63 C62 B43

A51 B51

L60

N60

W23 Y22 AY15

AV62 D58

P22 N21

P20 R20

OPI_COMP

CFG Straps for Processor

CFG3

12

R273

R273 1K_0402_1%

1K_0402_1%

@

Physical Debug Enable (DFX Privacy)

1: DISABLED

CFG3

0: ENABLED; SET DFX ENABLED BIT IN DEBUG INTERFACE MSR

CFG4

Display Port Presence Strap

1 : Disabled; No Physical Display Port

CFG4

attached to Embedded Display Port

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

12

R274

R274 1K_0402_1%

1K_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

2011/12/13 2012/12/13

Compal Secret Data

Deciphered Date

Custom

Date: Sheet of

Compal Electronics, Inc.

Title

Size Document Number Rev

Compal Electronics, Inc.

HSW MCP(11/11) RSVD

LA-A321PR02

14 46Thursday, March 14, 2013

0.2

A

SA_DIMM_VREFDQ<5>

1 1

V0.2

C107

0.022U_0402_16V7K

C107

0.022U_0402_16V7K

12

Follow PDG1.0

+1.35V

C95

1U_0402_6.3V6K

C95

1U_0402_6.3V6K

C94

1U_0402_6.3V6K

C94

1U_0402_6.3V6K

C93

1U_0402_6.3V6K

C93

1U_0402_6.3V6K

1

2

+1.35V

C123

1U_0402_6.3V6K

C123

1U_0402_6.3V6K

2 2

3 3

1

2

V0.2

+1.35V

C97

10U_0603_6.3V6M

C97

10U_0603_6.3V6M

1

2

+1.35V

C101

10U_0603_6.3V6M

C101

10U_0603_6.3V6M

1

2

Layout Note: Place near JDIMM1 Everage by each side

1

2

C121

1U_0402_6.3V6K

C121

1U_0402_6.3V6K

C125

1U_0402_6.3V6K

C125

1U_0402_6.3V6K

1

2

C98

10U_0603_6.3V6M

C98

10U_0603_6.3V6M

C99

10U_0603_6.3V6M

C99

10U_0603_6.3V6M

1

2

1

2

1

2

C103

10U_0603_6.3V6M@C103

10U_0603_6.3V6M

C102

10U_0603_6.3V6M

C102

10U_0603_6.3V6M

1

+

@

2

R279

1 2

2_0402_1%

R4

24.9_0402_1%

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

2

C100

10U_0603_6.3V6M

C100

10U_0603_6.3V6M

C104 100U_B2_6.3VM_R45M

@

+1.35V

12

R278

1.8K_0402_1%

12

R282

1.8K_0402_1%

CRB1.0 0.1uF *1 /2.2uF *1

2.2uF (reserved)

C96

DDRA_CKE0_DIMMA<5>

C124

DDRA_CS1_DIMMA#<5 >

+V_DDR_REFA

C89

0.1U_0402_16V4Z

C89

C92

2.2U_0402_6.3V6M@C92

2.2U_0402_6.3V6M

@

DDR_A_BS2<5>

SA_CLK_DDR0<5> SA_CLK_DDR#0<5>

DDR_A_BS0<5>

DDR_A_WE#<5> DDR_A_CAS#<5>

0.1U_0402_16V4Z

1

2

DDRA_CKE0_DIMMA

DDR_A_BS2

DDRA_CS1_DIMMA#

CRB1.0 10uF *8 /1uF *8

+0.675VS

C109

1U_0402_6.3V6K

C109

1U_0402_6.3V6K

C108

1U_0402_6.3V6K

C108

1U_0402_6.3V6K

C120

10U_0603_6.3V6M

C120

10U_0603_6.3V6M

1

2

4 4

V0.2

1

2

Layout Note: Place near JDIMM1.203,204

C110

1U_0402_6.3V6K

C110

1U_0402_6.3V6K

1

2

+3VS

+0.675VS

C111

1U_0402_6.3V6K

C111

1U_0402_6.3V6K

CRB1.0 0.1uF *1 /2.2uF *1

C113

2.2U_0402_6.3V6M

C113

C112

2.2U_0402_6.3V6M

0.1U_0402_16V4Z

1

2

R259

0_0402_5%

12

@

CRB1.0 10uF *1 /1uF *4

A

DDR_A_D13 DDR_A_D8

DDR_A_D14 DDR_A_D10

DDR_A_D29 DDR_A_D28

DDR_A_DQS#3 DDR_A_DQS3

DDR_A_D30 DDR_A_D31

DDR_A_D44 DDR_A_D41

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D43 DDR_A_D47

DDR_A_D51 DDR_A_D50

DDR_A_D49 DDR_A_D48

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

SA_CLK_DDR0 SA_CLK_DDR#0

DDR_A_MA10 DDR_A_BS0

DDR_A_WE# DDR_A_CAS#

DDR_A_MA13

DDR_A_D0 DDR_A_D1

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D2 DDR_A_D6

DDR_A_D21 DDR_A_D20

DDR_A_D17 DDR_A_D16

DDR_A_D36 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D38

DDR_A_D62 DDR_A_D58

DDR_A_D60 DDR_A_D61

12

R258

R258 0_0402_5%

0_0402_5%

@

B

JDIMM1

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

LCN_DAN06-K4406-0103

ME@

DQS0#

DQS0

RESET#

DQS3#

DQS3

ODT0

ODT1

VREF_CA

DQS5#

DQS5

DQS7#

DQS7

EVENT#

GND2

BOSS2

VSS DQ4 DQ5 VSS

VSS DQ6 DQ7

VSS DQ12 DQ13

VSS

DM1

VSS DQ14 DQ15

VSS DQ20 DQ21

VSS

DM2

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS

VSS DQ30 DQ31

VSS

CKE1

VDD

CK1#

VDD

RAS#

VDD

VSS DQ36 DQ37

VSS

DM4

VSS DQ38 DQ39

VSS DQ44 DQ45

VSS

VSS DQ46 DQ47

VSS DQ52 DQ53

VSS

DM6

VSS DQ54 DQ55

VSS DQ60 DQ61

VSS

VSS DQ62 DQ63

VSS

SDA

+1.35V+1.35V

2 4

DDR_A_D9

6

DDR_A_D12

8 10

DDR_A_DQS#1

12

DDR_A_DQS1

14 16

DDR_A_D15

18

DDR_A_D11

20 22

DDR_A_D25

24

DDR_A_D24

26 28 30

DIMM_DRAMRST#

32 34

DDR_A_D27

36

DDR_A_D26

38 40

DDR_A_D45

42

DDR_A_D40

44 46 48 50

DDR_A_D42

52

DDR_A_D46

54 56

DDR_A_D52

58

DDR_A_D53

60 62

DDR_A_DQS#6

64

DDR_A_DQS6

66 68

DDR_A_D54

70

DDR_A_D55

72

74

DDRA_CKE1_DIMMA

76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206 208

DDR_A_MA15 DDR_A_MA14

DDR_A_MA11 DDR_A_MA7

DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

SA_CLK_DDR1 SA_CLK_DDR#1

DDR_A_BS1 DDR_A_RAS#

DDRA_CS0_DIMMA# SA_ODT0

SA_ODT1

+VREF_CA

DDR_A_D5 DDR_A_D4

DDR_A_D3 DDR_A_D7

DDR_A_D18 DDR_A_D19

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D22 DDR_A_D23

DDR_A_D37 DDR_A_D32

DDR_A_D35 DDR_A_D39

DDR_A_D63 DDR_A_D59

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D56 DDR_A_D57

PCH_SMB_DATA PCH_SMB_CLK

+0.675VS

A15 A14

A11

A7

A6 A4

A2 A0

CK1

BA1

S0#

NC

SCL VTT

All VREF traces should have 10 mil trace width

C115 0.1U_0402_16 V4Z

1 2

@

DDRA_CKE1_DIMMA <5 >

SA_CLK_DDR1 <5> SA_CLK_DDR#1 <5>

DDR_A_BS1 <5 > DDR_A_RAS# <5>

DDRA_CS0_DIMMA# < 5>

1

@

2

CRB1.0 0.1uF *1 /2.2uF *1

2.2uF (reserved)

CHANNEL A /TYPE :Reverse / H:4mm

CHA SPD ADDRESS IS OxA0 CHA TS ADDRESS IS Ox30

PN:SP07000LT00

B

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

DIMM_DRAMRST# <4>

2.2U_0402_6.3V6M

C106

0.1U_0402_16V4Z

C106

0.1U_0402_16V4Z

C105

1

2

PCH_SMB_DATA <28 ,31,7> PCH_SMB_CLK < 28,31,7>

Issued Date

C

DDR_A_DQS#[0..7] <5>

DDR_A_DQS[0..7] <5>

DDR_A_D[0..63] <5>

DDR_A_MA[0..15] <5>

DDR_PG_CTRL<4>

+1.35V

12

R287

1.8K_0402_1%

R288

1 2

2_0402_1%

12

R289

1.8K_0402_1%

2011/12/13 2012/12/13

C114

0.022U_0402_16V7K

C114

0.022U_0402_16V7K

12

R5

24.9_0402_1%

V0.2

Compal Secret Data

Deciphered Date

2

3

SM_DIMM_VREFCA <5>

D

0.1U_0402_16V4Z

C90

U7

NC1VCC

A

Y

GND

74AUP1G07GW_TSSOP5

D

E

+1.35V

+5VALW

1

2

5

4

+5VS

R290220K_040 2_5% R290220K_0402_5%

R291220K_040 2_5%@R291220K_040 2_5%

12

V0.2

@

Custom

+1.35V

Q9

13

D

LBSS138LT1G_SOT-23-3

2

G

S

M_A_B_DIMM_ODT

DDR_VTT_PG_CTRL <37>

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

DDRIII DIMMA

LA-A321PR02

1 2

R281 66.5_0402_1%R281 66 .5_0402_1%

1 2

R285 66.5_0402_1%R285 66 .5_0402_1%

E

SA_ODT0

SA_ODT1

0.2

15 46Thursday, March 14, 2013

0.2