Compal LA-A091P VALGC, G505s, G505, LA-A091P VALGD Schematic

A

1 1

B

C

D

E

Compal Confidential

2 2

VALGC_GD M/B Schematics Document

AMD Fs1r2 Richland Processor with DDRIII + Bolton-M3 FCH

AMD Mars XT M2

LA-A091P

3 3

2013-04-16

REV:1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/11/13 2013/11/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

VALGD MB L

0.1

1 57Friday, April 12, 2013

E

0.1

A

Compal confidential

File Name :LA-A091P

B

C

D

E

AMD MARS XT M2 128 bi

1 1

LVDS Conn.

HDMI Conn.

Sun Pro M2 64bit

VRAM: DDR3 type, 1GB/ 2GB

page 27

page 29

page 16~25

LVDS translator

RTD2132S

ts

page 26

PCIEx8 Gen2

DP Port0

DP Port2

AMD FS1r2 APU

Richland uPGA 722 pin

DP0

35mm x 35mm

DP2

DP1

page 5,6,7,8

Memory BUS(DDRIII)

Dual Channel

DDR3 / DDR3L 1600MHz

204pin DDRIII-SO-DIMM X2

BANK

0, 1, 2

page 9,10

x4 UMI Gen. 1

GPP0GPP1

PCIe Mini Card

WLAN+BT4.0 Combo

2 2

3 3

PCIe Port 1

USB20 Port 2

RJ45 Conn.

CRT Conn.

Thermal Sensor

Touch Pad

Int. KBD

page 32

page 28

page 33

page 37

page 30

LAN

PCIe Port 0

Atheros AR8162 QCA8172(10/100)

page 31

FCH CRT (VGA DAC)

EC

ENE KB9012

SPI ROM

4MB

USB20 x1

page 36

page 12

2.5GT/s per lane

Bolton M3

uFCBGA-656

24.5mm x 24.5mm

page 11~15

USB30 x2

USB20 x6

SATA Gen3

SATA

AZALIA

Audio Codec

CONEXANT CX20757

page 35

Left USB3.0 x2

USB30 Port 0,1

page 39

Touch Screen

USB20 Port 4

page 39

Right USB2.0

USB20 Port 0

page 39

Int. Camera

USB20 Port 3

Card Reader

Realtek RTS5170

USB20 Port 6

page 27

page 37

HDD Conn.

SATA Port 0

page 34

ODD Conn.

SATA Port 1

page 34

Int. MIC Conn.

page 35

Int. Speaker Conn.

page 35

Audio Combo Jacks

HP & MIC

page 37

Sub-borad

15" 14"

4 4

Power/B

LS9902P

IO/B

LS9901P LS9904P

LED/B

LS9903P

ODD/B

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/11/13 2013/11/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

MB Block Diagram

VALGD MB L

E

0.1

2 57Friday, April 12, 2013

0.1

A

Voltage Rails

power plane

1 1

+B

State

S0

S3

2 2

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery do

n't exist

O

X

+5VALW

+3VALW

+1.1VALW

O

X

X X X

+1.5V

+1.5V_APU

O

X X

X

SMBUS Control Table

SOURCE

SMB_EC_CK1 SMB_EC_DA1

SMB_EC_CK2_SUS SMB_EC_DA2_SUS

FCH_SCLK0 FCH_SDATA0

3 3

SMB_EC_CK2 SMB_EC_DA2

KB9012

+3VALW

KB9012

+3VALW

FCH

+3VS

KB9012

+3VS (LV shifter)

EC SM Bus1 address

Device

Smart Battery

PCH SM Bus address

4 4

Device Address

DDR DIMM0

DDR DIMM2

Address Address

0001 011X b

1001 000Xb

1001 010Xb

VGA BATT KB9012 SODIMM

X V

+3VALW

X

V V V

A

X

X X

X

X X

EC SM Bus2 address

Device

Thermal Sen sor

SB-TSI(default)

VGA(int. thermal)

RTD2132S

VGA(ext. thermal)

WLAN WWAN

X X

V

+3VS +3VS

X XX

V

1001_101xb

1001_100xb

1000_001xb

1010_1000b

0100_1101b

B

+5VS

+3VS

+2.5VS

+1.5VS

+1.2VS

+1.1VS

+0.75VS

+APU_CORE

+APU_CORE_NB

+VGA_CORE

+3.3VGS

+1.8VGS

+1.5VGS

+0.95VGS

Thermal Sensor

X

B

C

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S3# SLP_S5# +VALW +V +VS Clock

HIGHHIGH

HIGH

ON

HIGH HIGH

HIGH

LOW

LOW LOW

D

ONONON ON

ON

OFF

E

LOW

OFF

Board ID / SKU ID Table for AD channelBOARD ID Table

Board ID

0 1 2 3

OO

4 5 6

X

7

PCB Revision

0.2

ID BRD ID Ra Rb Vab

x

0

0V

0.25V

0.5V

0.82VR01 EVT

1

2

3

R10 MP0

R03 PVT

R02 DVT

100K

8.2K

18K

33K

Ra = R310 R

b = R311

BOM Structure Table

USB Port Table

X

USB 3.0USB 2.0 Port

0

4 External USB Port

USB Port 2.0 (Right Side)

1 2

Mini Card(WLAN)

3

Camera /

4

Touch Screen

FCH

X

XX XX

X

APU RTD2132

X X

V

+1.5V

X X

X

XHCI

5 6

Card Reader

7 8 9

10

0 1 2 3

USB 2.0 Port (Left Side)

11

USB 2.0 Port (Left Side)

12 13

USB OC MAPPING

OC# USB Port

USB20 port10,port11

0

USB20 port0

1 2 3

APU PCIE PORT LIST

Port Device

1

LAN

2

WLAN

FCH PCIE PORT LIST

Port Device

3 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/11/13 2013/11/12

USB30 port0,port1

1 2 3 4

Compal Secret Data

Deciphered Date

D

PX@ 14@ 15@ 45@ CMOS@ 8162@ 8172@ CMOS@ TS@ X76@ GCLK@ NOGCLK@ GCLK302@ GCLK238@ LVDS@ PXNOGCLK@ LDO@ SWR@

DEBUG@

ME@ MIC@ 885N@ JUMP@ TEST POINT@ SHORT PAD@ EMI@ @ESD@ @EMI@ @ MARS@ 2132S@ 2132R@ ShareROM@ Strap@

Date: Sheet of

BTO ItemBOM Structure

VGA circuit

For 14"

For 15"

HDMI LOGO

CMOS Camera part

AR8162 LAN part

AR8172 LAN part

For CMOS circuit

For Touch Screen circuit

X76 Level part for VRAM

Ues GCLK circuit

No use GCLK circuit

302 part for DIS

238 part for UMA

LVDS circuit

No use GCLK circuit in GPU

LDO mode for LAN

SWR mode for LAN

For debug

ME part

MIC part

Unpop in KBC page

JUMP

TSET POINT

SHORT PAD

EMI part

Reserve for ESD

Reserve for EMI

Unpop

VRAM CHB parts for MARS

Panel PWM part for RTD2132S

Panel PWM part for RTD2132R

Reserve for ShareROM

Reserve for Strap pin

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Compal Electronics, Inc.

Notes List

VALGD MB L

E

3 57Friday, April 12, 2013

0.1

5

Mars XT VRAM STRAP

Vendor

UV5,UV6,UV7,UV8, UV9,UV10,UV11,UV12

Samsung 2048Mbits SA000068U00

MS2G

D D

MM2G

MH2G 0 1 1 6.98K 4.99K

128M16 K4W2G1646E-BC1A FBGA

Micron 2048Mbits SA000067500 128Mx16 MT41J128M16JT-093G:k

Hynix 2048Mbits SA000065300 128M16 H5TQ2G63DFR-N0C FBGA

PS_3[3] PS_3[2] PS_3[1] R_pu R_pd

0 0 0 NC 4.75K

0 0 1 8.45K 2K

4

X76@X76@

RV20 RV27

4.53K 2K0 1 0

3

Sun PRO VRAM STRAP

X76@ X76@

Vendor

UV9,UV10,UV11,UV12

Samsung 2048Mbits

SS2G

SM2G

SS1G

SM1G

SH1G

SA000068R00 256M16 K4W4G1646B-HC11 FBGA

Micron 2048Mbits SA000065D00 256M16 MT41K256M16HA-107G

Samsung 1024Mbits SA000068U00 128M16 K4W2G1646E-BC1A FBGA

Micron 1024Mbits SA000067500 128Mx16 MT41J128M16JT-093G:k

Hynix 1024Mbits SA000065300 128M16 H5TQ2G63DFR-N0C FBGA

2

PS_3[2]PS_3[3] R_pdR_puPS_3[1]

0

1 1 1

00

100

01 1

1

RV27RV20

4.75KNC

2K8.45K

10K3.4K

4.75K NC

Power-Up/Down Sequence

C C

"Mars" has the following requirements with regards to power-supply sequencing to avoid damaging the ASIC:

All the ASIC supplies must reach their respective nominal voltages within 20ms

‧

of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred. The maximum slew rate on all rails is 50mV/us.

The external pull ups on the DDC/AUX signals (if applicable) should ramp up

‧

before or after both VDDC and VDD_CT have ramped up.

VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC should

‧

reach 90% before VDD_CT starts to ramp up (or vice versa).

For power down, reversing the ramp-up sequence is recommended.

‧

VDDR3(+3VGS)

PCIE_VDDC(+0.95VGS)

B B

VDDR1(+1.5VGS)

VDDC/VDDCI(+VGA_CORE)

VDD_CT(+1.8VGS)

PERSTb

REFCLK

Straps Reset

Straps Valid

A A

Global ASIC Reset

T4+16clock

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2012/11/13 2013/11/12

3

Compal Secret Data

Deciphered Date

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Compal Electronics, Inc.

VGA Notes List

VALGD MB L

1

4 57Friday, April 12, 2013

0.1

A

B

C

D

E

1 2

PCIE_CTX_GRX_P[0..7]

PCIE_CTX_GRX_N[0..7]

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2

C35 0.1U_0402_16V7KC35 0.1U_0402_16V7K

1 2

C36 0.1U_0402_16V7KC36 0.1U_0402_16V7K

1 2

C82 0.1U_0402_16V7KC82 0.1U_0402_16V7K

1 2

C103 0.1U_0402_16V7KC103 0.1U_0402_16V7K

1 2

C37 0.1U_0402_16V7KC37 0.1U_0402_16V7K

1 2

C38 0.1U_0402_16V7KC38 0.1U_0402_16V7K

1 2

C39 0.1U_0402_16V7KC39 0.1U_0402_16V7K

1 2

C40 0.1U_0402_16V7KC40 0.1U_0402_16V7K

1 2

C41 0.1U_0402_16V7KC41 0.1U_0402_16V7K

1 2

C42 0.1U_0402_16V7KC42 0.1U_0402_16V7K

1 2

C43 0.1U_0402_16V7KC43 0.1U_0402_16V7K

1 2

C44 0.1U_0402_16V7KC44 0.1U_0402_16V7K

PCIE_CTX_GRX_P[0..7] <16>

PCIE_CTX_GRX_N[0..7] <16>PCIE_CRX_GTX_N[0..7]<16>

CV2090.1U_0402_16V7K PX@CV2090.1U_0402_16V7K PX@ CV2150.1U_0402_16V7K PX@CV2150.1U_0402_16V7K PX@ CV2050.1U_0402_16V7K PX@CV2050.1U_0402_16V7K PX@ CV2030.1U_0402_16V7K PX@CV2030.1U_0402_16V7K PX@ CV2040.1U_0402_16V7K PX@CV2040.1U_0402_16V7K PX@ CV2120.1U_0402_16V7K PX@CV2120.1U_0402_16V7K PX@ CV2110.1U_0402_16V7K PX@CV2110.1U_0402_16V7K PX@ CV2130.1U_0402_16V7K PX@CV2130.1U_0402_16V7K PX@ CV2100.1U_0402_16V7K PX@CV2100.1U_0402_16V7K PX@ CV2060.1U_0402_16V7K PX@CV2060.1U_0402_16V7K PX@ CV2070.1U_0402_16V7K PX@CV2070.1U_0402_16V7K PX@ CV250.1U_0402_16V7K PX@CV250.1U_0402_16V7K PX@ CV510.1U_0402_16V7K PX@CV510.1U_0402_16V7K PX@ CV240.1U_0402_16V7K PX@CV240.1U_0402_16V7K PX@ CV2140.1U_0402_16V7K PX@CV2140.1U_0402_16V7K PX@ CV2080.1U_0402_16V7K PX@CV2080.1U_0402_16V7K PX@

PCIE_CTX_GRX_P0 PCIE_CTX_GRX_N0 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_P7 PCIE_CTX_GRX_N7

PCIE_PTX_C_DRX_P0 <31> PCIE_PTX_C_DRX_N0 <31> PCIE_PTX_C_DRX_P1 <30> PCIE_PTX_C_DRX_N1 <30>

UMI_TXP0 <11> UMI_TXN0 <11> UMI_TXP1 <11> UMI_TXN1 <11> UMI_TXP2 <11> UMI_TXN2 <11> UMI_TXP3 <11> UMI_TXN3 <11>

LAN

W

LAN

PCIE_CRX_GTX_P[0..7]<16>

1 1

PCIE_PRX_DTX_P0<31> PCIE_PRX_DTX_N0<31> PCIE_PRX_DTX_P1<30>

2 2

PCIE_PRX_DTX_N1<30>

UMI_RXP0<11> UMI_RXN0<11> UMI_RXP1<11> UMI_RXN1<11> UMI_RXP2<11> UMI_RXN2<11> UMI_RXP3<11> UMI_RXN3<11>

+1.2VS

PCIE_CRX_GTX_P[0..7]

PCIE_CRX_GTX_N[0..7]

PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_N7

1 2

R1 196_0402_1%R1 196_0402_1%

P_ZVDDP

AG11

AB8 AB7 AA9 AA8 AA5 AA6

AE5 AE6 AD8 AD7 AC9 AC8 AC5 AC6

AG8 AG9 AG6 AG5 AF7 AF8 AE8 AE9

Y8

Y7 W9 W8 W5 W6

V8

V7

U9

U8

U5

U6

T8

T7

R9

R8

R5

R6

P8

P7

N9

N8

N5

N6 M8 M7

JCPU1A

P_GFX_RXP0 P_GFX_RXN0 P_GFX_RXP1 P_GFX_RXN1 P_GFX_RXP2 P_GFX_RXN2 P_GFX_RXP3 P_GFX_RXN3 P_GFX_RXP4 P_GFX_RXN4 P_GFX_RXP5 P_GFX_RXN5 P_GFX_RXP6 P_GFX_RXN6 P_GFX_RXP7 P_GFX_RXN7 P_GFX_RXP8 P_GFX_RXN8 P_GFX_RXP9 P_GFX_RXN9 P_GFX_RXP10 P_GFX_RXN10 P_GFX_RXP11 P_GFX_RXN11 P_GFX_RXP12 P_GFX_RXN12 P_GFX_RXP13 P_GFX_RXN13 P_GFX_RXP14 P_GFX_RXN14 P_GFX_RXP15 P_GFX_RXN15

P_GPP_RXP0 P_GPP_RXN0 P_GPP_RXP1 P_GPP_RXN1 P_GPP_RXP2 P_GPP_RXN2 P_GPP_RXP3 P_GPP_RXN3

P_UMI_RXP0 P_UMI_RXN0 P_UMI_RXP1 P_UMI_RXN1 P_UMI_RXP2 P_UMI_RXN2 P_UMI_RXP3 P_UMI_RXN3

P_ZVDDP

ME@

PCI EXPRESS

LOTES_ACA-ZIF-109-P12-A_FS1R2

GPP GRAPHICS

UMI

P_GFX_TXP0 P_GFX_TXN0 P_GFX_TXP1 P_GFX_TXN1 P_GFX_TXP2 P_GFX_TXN2 P_GFX_TXP3 P_GFX_TXN3 P_GFX_TXP4 P_GFX_TXN4 P_GFX_TXP5 P_GFX_TXN5 P_GFX_TXP6 P_GFX_TXN6 P_GFX_TXP7 P_GFX_TXN7 P_GFX_TXP8 P_GFX_TXN8 P_GFX_TXP9

P_GFX_TXN9 P_GFX_TXP10 P_GFX_TXN10 P_GFX_TXP11 P_GFX_TXN11 P_GFX_TXP12 P_GFX_TXN12 P_GFX_TXP13 P_GFX_TXN13 P_GFX_TXP14 P_GFX_TXN14 P_GFX_TXP15 P_GFX_TXN15

P_GPP_TXP0

P_GPP_TXN0

P_GPP_TXP1

P_GPP_TXN1

P_GPP_TXP2

P_GPP_TXN2

P_GPP_TXP3

P_GPP_TXN3

P_UMI_TXP0 P_UMI_TXN0 P_UMI_TXP1 P_UMI_TXN1 P_UMI_TXP2 P_UMI_TXN2 P_UMI_TXP3 P_UMI_TXN3

P_ZVSS

AB2

PCIE_CTX_C_GRX_P0

AB1

PCIE_CTX_C_GRX_N0

AA3

PCIE_CTX_C_GRX_P1

AA2

PCIE_CTX_C_GRX_N1

Y5

PCIE_CTX_C_GRX_P2

Y4

PCIE_CTX_C_GRX_N2

Y2

PCIE_CTX_C_GRX_P3

Y1

PCIE_CTX_C_GRX_N3

W3

PCIE_CTX_C_GRX_P4

W2

PCIE_CTX_C_GRX_N4

V5

PCIE_CTX_C_GRX_P5

V4

PCIE_CTX_C_GRX_N5

V2

PCIE_CTX_C_GRX_P6

V1

PCIE_CTX_C_GRX_N6

U3

PCIE_CTX_C_GRX_P7

U2

PCIE_CTX_C_GRX_N7

T5 T4 T2 T1 R3 R2 P5 P4 P2 P1 N3 N2 M5 M4 M2 M1

AD5

PCIE_PTX_DRX_P0

AD4

PCIE_PTX_DRX_N0

AD2

PCIE_PTX_DRX_P1

AD1

PCIE_PTX_DRX_N1

AC3 AC2 AB5 AB4

AG2

UMI_TXP0_C

AG3

UMI_TXN0_C

AF4

UMI_TXP1_C

AF5

UMI_TXN1_C

AF1

UMI_TXP2_C

AF2

UMI_TXN2_C

AE2

UMI_TXP3_C

AE3

UMI_TXN3_C

AH11

P_ZVSS

R2 196_0402_1%R2 196_0402_1%

3 3

Power Sequence of APU

+1.5V

+2.5VS

+1.5VS

+APU_CORE

4 4

+APU_CORE_NB

+1.2VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/11/13 2013/11/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

FS1r2 PCIE/UMI

VALGD MB L

E

5 57Friday, April 12, 2013

Group A

Group B

0.1

A

1 1

JCPU1B

MEMORY CHANNEL A

DDRA_SMA[15..0]<9>

DDRA_SBS0#<9> DDRA_SBS1#<9> DDRA_SBS2#<9> DDRA_SDM[7..0]<9>

2 2

DDRA_SDQS0<9> DDRA_SDQS0#<9> DDRA_SDQS1<9> DDRA_SDQS1#<9> DDRA_SDQS2<9> DDRA_SDQS2#<9> DDRA_SDQS3<9> DDRA_SDQS3#<9> DDRA_SDQS4<9> DDRA_SDQS4#<9> DDRA_SDQS5<9> DDRA_SDQS5#<9> DDRA_SDQS6<9> DDRA_SDQS6#<9> DDRA_SDQS7<9> DDRA_SDQS7#<9>

DDRA_CLK0<9> DDRA_CLK0#<9> DDRA_CLK1<9> DDRA_CLK1#<9>

DDRA_CKE0<9> DDRA_CKE1<9>

DDRA_ODT0<9> DDRA_ODT1<9>

3 3

DDRA_SCS0#<9> DDRA_SCS1#<9>

DDRA_SRAS#<9> DDRA_SCAS#<9> DDRA_SWE#<9>

MEM_MA_RST#<9> MEM_MA_EVENT#<9>

+MEM_VREF

+1.5V_APU

Place them close to APU within 1"

Place them close to APU within 1"Place them close to APU within 1"

15mil

DDRA_SMA0 DDRA_SMA1 DDRA_SMA2 DDRA_SMA3 DDRA_SMA4 DDRA_SMA5 DDRA_SMA6 DDRA_SMA7 DDRA_SMA8 DDRA_SMA9 DDRA_SMA10 DDRA_SMA11 DDRA_SMA12 DDRA_SMA13 DDRA_SMA14 DDRA_SMA15

DDRA_SBS0# DDRA_SBS1# DDRA_SBS2#

DDRA_SDM0 DDRA_SDM1 DDRA_SDM2 DDRA_SDM3 DDRA_SDM4 DDRA_SDM5 DDRA_SDM6 DDRA_SDM7

DDRA_SDQS0 DDRA_SDQS0# DDRA_SDQS1 DDRA_SDQS1# DDRA_SDQS2 DDRA_SDQS2# DDRA_SDQS3 DDRA_SDQS3# DDRA_SDQS4 DDRA_SDQS4# DDRA_SDQS5 DDRA_SDQS5# DDRA_SDQS6 DDRA_SDQS6# DDRA_SDQS7 DDRA_SDQS7#

DDRA_CLK0 DDRA_CLK0# DDRA_CLK1 DDRA_CLK1#

DDRA_CKE0 DDRA_CKE1

DDRA_ODT0 DDRA_ODT1

DDRA_SCS0# DDRA_SCS1#

DDRA_SRAS# DDRA_SCAS# DDRA_SWE#

MEM_MA_RST#

MEM_MA_EVENT#

1 2

R3 39.2_0402_1%R3 39.2_0402_1%

M_ZVDDIO

M21

M22

AA25

AD27 AC23 AD19 AC15

AE26 AD26 AB22 AA22 AB18 AA18 AA14 AA15

AA27

AA26

W24 W23

W20

W21

U20 R20 R21 P22 P21 N24 N23 N20 N21

U23

L24

L21 L20

U24 U21

L23

E14

J17 E21 F25

G14 H14 G18 H18

J21 H21 E27 E26

T21 T22 R23 R24

H28 H27

Y25

V22

V21

H25 T24

MA_ADD0 MA_ADD1 MA_ADD2 MA_ADD3 MA_ADD4 MA_ADD5 MA_ADD6 MA_ADD7 MA_ADD8 MA_ADD9 MA_ADD10 MA_ADD11 MA_ADD12 MA_ADD13 MA_ADD14 MA_ADD15

MA_BANK0 MA_BANK1 MA_BANK2

MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7

MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7

MA_CLK_H0 MA_CLK_L0 MA_CLK_H1 MA_CLK_L1

MA_CKE0 MA_CKE1

MA_ODT0 MA_ODT1

MA_CS_L0 MA_CS_L1

MA_RAS_L MA_CAS_L MA_WE_L

MA_RESET_L MA_EVENT_L

M_VREF

M_ZVDDIO

ME@

MEMORY CHANNEL A

LOTES_ACA-ZIF-109-P12-A_FS1R2

B

MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7

MA_DATA8

MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15

MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23

MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31

MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39

MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47

MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55

MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63

E13 J13 H15 J15 H13 F13 F15 E15

H17 F17 E19 J19 G16 H16 H19 F19

H20 F21 J23 H23 G20 E20 G22 H22

G24 E25 G27 G26 F23 H24 E28 F27

AB28 AC27 AD25 AA24 AE28 AD28 AB26 AC25

Y23 AA23 Y21 AA20 AB24 AD24 AA21 AC21

AA19 AC19 AC17 AA17 AB20 Y19 AD18 AD17

AA16 Y15 AA13 AC13 Y17 AB16 AB14 Y13

DDRA_SDQ0 DDRA_SDQ1 DDRA_SDQ2 DDRA_SDQ3 DDRA_SDQ4 DDRA_SDQ5 DDRA_SDQ6 DDRA_SDQ7

DDRA_SDQ8 DDRA_SDQ9 DDRA_SDQ10 DDRA_SDQ11 DDRA_SDQ12 DDRA_SDQ13 DDRA_SDQ14 DDRA_SDQ15

DDRA_SDQ16 DDRA_SDQ17 DDRA_SDQ18 DDRA_SDQ19 DDRA_SDQ20 DDRA_SDQ21 DDRA_SDQ22 DDRA_SDQ23

DDRA_SDQ24 DDRA_SDQ25 DDRA_SDQ26 DDRA_SDQ27 DDRA_SDQ28 DDRA_SDQ29 DDRA_SDQ30 DDRA_SDQ31

DDRA_SDQ32 DDRA_SDQ33 DDRA_SDQ34 DDRA_SDQ35 DDRA_SDQ36 DDRA_SDQ37 DDRA_SDQ38 DDRA_SDQ39

DDRA_SDQ40 DDRA_SDQ41 DDRA_SDQ42 DDRA_SDQ43 DDRA_SDQ44 DDRA_SDQ45 DDRA_SDQ46 DDRA_SDQ47

DDRA_SDQ48 DDRA_SDQ49 DDRA_SDQ50 DDRA_SDQ51 DDRA_SDQ52 DDRA_SDQ53 DDRA_SDQ54 DDRA_SDQ55

DDRA_SDQ56 DDRA_SDQ57 DDRA_SDQ58 DDRA_SDQ59 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDQ62 DDRA_SDQ63

DDRA_SDQ[63..0] <9>

C

DDRB_SMA[15..0]<10>

DDRB_SBS0#<10> DDRB_SBS1#<10> DDRB_SBS2#<10> DDRB_SDM[7..0]<10>

DDRB_SDQS0<10> DDRB_SDQS0#<10> DDRB_SDQS1<10> DDRB_SDQS1#<10> DDRB_SDQS2<10> DDRB_SDQS2#<10> DDRB_SDQS3<10> DDRB_SDQS3#<10> DDRB_SDQS4<10> DDRB_SDQS4#<10> DDRB_SDQS5<10> DDRB_SDQS5#<10> DDRB_SDQS6<10> DDRB_SDQS6#<10> DDRB_SDQS7<10> DDRB_SDQS7#<10>

DDRB_CLK0<10> DDRB_CLK0#<10> DDRB_CLK1<10> DDRB_CLK1#<10>

DDRB_CKE0<10> DDRB_CKE1<10>

DDRB_ODT0<10> DDRB_ODT1<10>

DDRB_SCS0#<10> DDRB_SCS1#<10>

DDRB_SRAS#<10> DDRB_SCAS#<10> DDRB_SWE#<10>

MEM_MB_RST#<10> MEM_MB_EVENT#<10>

DDRB_SMA0 DDRB_SMA1 DDRB_SMA2 DDRB_SMA3 DDRB_SMA4 DDRB_SMA5 DDRB_SMA6 DDRB_SMA7 DDRB_SMA8 DDRB_SMA9 DDRB_SMA10 DDRB_SMA11 DDRB_SMA12 DDRB_SMA13 DDRB_SMA14 DDRB_SMA15

DDRB_SBS0# DDRB_SBS1# DDRB_SBS2#

DDRB_SDM0 DDRB_SDM1 DDRB_SDM2 DDRB_SDM3 DDRB_SDM4 DDRB_SDM5 DDRB_SDM6 DDRB_SDM7

DDRB_SDQS0 DDRB_SDQS0# DDRB_SDQS1 DDRB_SDQS1# DDRB_SDQS2 DDRB_SDQS2# DDRB_SDQS3 DDRB_SDQS3# DDRB_SDQS4 DDRB_SDQS4# DDRB_SDQS5 DDRB_SDQS5# DDRB_SDQS6 DDRB_SDQS6# DDRB_SDQS7 DDRB_SDQS7#

DDRB_CLK0 DDRB_CLK0# DDRB_CLK1 DDRB_CLK1#

DDRB_CKE0 DDRB_CKE1

DDRB_ODT0 DDRB_ODT1

DDRB_SCS0# DDRB_SCS1#

DDRB_SRAS# DDRB_SCAS# DDRB_SWE#

MEM_MB_RST# MEM_MB_EVENT#

D

M28 M27 M24 M25

W26

AF25 AG22 AH18 AD14

AG24 AG25 AG21 AF21 AG17 AG18 AH14 AG14

W27

T27 P24 P25 N27 N26

L26 U26 L27 K27

K25 K24

U27 T28 K28

D14 A18 A22 C25

C15 B15 E18 D18 E22 D22 B26 A26

R26 R27 P27 P28

J26 J27

Y28

V25 Y27

V24 V27 V28

J25 T25

JCPU1C

MEMORY CHANNEL B

MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8 MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15

MB_BANK0 MB_BANK1 MB_BANK2

MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7

MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7

MB_CLK_H0 MB_CLK_L0 MB_CLK_H1 MB_CLK_L1

MB_CKE0 MB_CKE1

MB_ODT0 MB_ODT1

MB_CS_L0 MB_CS_L1

MB_RAS_L MB_CAS_L MB_WE_L

MB_RESET_L MB_EVENT_L

LOTES_ACA-ZIF-109-P12-A_FS1R2

ME@

MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7

MB_DATA8

MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15

MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23

MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31

MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39

MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47

MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55

MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63

A14 B14 D16 E16 B13 C13 B16 A16

C17 B18 B20 A20 E17 B17 B19 C19

C21 B22 C23 A24 D20 B21 E23 B23

E24 B25 B27 D28 B24 D24 D26 C27

AG26 AH26 AF23 AG23 AG27 AF27 AH24 AE24

AE22 AH22 AE20 AH20 AD23 AD22 AD21 AD20

AF19 AE18 AE16 AH16 AG20 AG19 AF17 AD16

AG15 AD15 AG13 AD13 AG16 AF15 AE14 AF13

DDRB_SDQ0 DDRB_SDQ1 DDRB_SDQ2 DDRB_SDQ3 DDRB_SDQ4 DDRB_SDQ5 DDRB_SDQ6 DDRB_SDQ7

DDRB_SDQ8 DDRB_SDQ9 DDRB_SDQ10 DDRB_SDQ11 DDRB_SDQ12 DDRB_SDQ13 DDRB_SDQ14 DDRB_SDQ15

DDRB_SDQ16 DDRB_SDQ17 DDRB_SDQ18 DDRB_SDQ19 DDRB_SDQ20 DDRB_SDQ21 DDRB_SDQ22 DDRB_SDQ23

DDRB_SDQ24 DDRB_SDQ25 DDRB_SDQ26 DDRB_SDQ27 DDRB_SDQ28 DDRB_SDQ29 DDRB_SDQ30 DDRB_SDQ31

DDRB_SDQ32 DDRB_SDQ33 DDRB_SDQ34 DDRB_SDQ35 DDRB_SDQ36 DDRB_SDQ37 DDRB_SDQ38 DDRB_SDQ39

DDRB_SDQ40 DDRB_SDQ41 DDRB_SDQ42 DDRB_SDQ43 DDRB_SDQ44 DDRB_SDQ45 DDRB_SDQ46 DDRB_SDQ47

DDRB_SDQ48 DDRB_SDQ49 DDRB_SDQ50 DDRB_SDQ51 DDRB_SDQ52 DDRB_SDQ53 DDRB_SDQ54 DDRB_SDQ55

DDRB_SDQ56 DDRB_SDQ57 DDRB_SDQ58 DDRB_SDQ59 DDRB_SDQ60 DDRB_SDQ61 DDRB_SDQ62 DDRB_SDQ63

E

DDRB_SDQ[63..0] <10>

EVENT# pull high 0.75V reference voltage

+1.5V_APU

4 4

1 2

R5 1K_0402_5%R5 1K_0402_5%

1 2

R6 1K_0402_5%R6 1K_0402_5%

MEM_MA_EVENT#

MEM_MB_EVENT# +MEM_VREF

A

R4

1K_0402_1%

R7

1K_0402_1%

+1.5V_APU

1 2

B

1

C45

C45 1000P_0402_50V7K

1000P_0402_50V7K

2

15mil

2

C46

0.1U_0402_16V7K

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/11/13 2013/11/12

Compal Secret Data

Deciphered Date

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Title

Size Document Number Rev

Compal Electronics, Inc.

FS1r2 DDRIII Memory I/F

VALGD MB L

6 57Friday, April 12, 2013

E

0.1

A

1 2

DP0_TXP0_C<26> DP0_TXN0_C<26>

1 1

ML_VGA_TXP0<12> ML_VGA_TXN0<12>

ML_VGA_TXP1<12> ML_VGA_TXN1<12>

ML_VGA_TXP2<12> ML_VGA_TXN2<12>

ML_VGA_TXP3<12> ML_VGA_TXN3<12>

HDMI_TX2+_CK<29> HDMI_TX2-_CK<29>

HDMI_TX1+_CK<29> HDMI_TX1-_CK<29>

HDMI_TX0+_CK<29> HDMI_TX0-_CK<29>

HDMI_CLK+_CK<29> HDMI_CLK-_CK<29>

C61~C68 Close Connector

APU_SVC<48>

12

C465100P_0402_50V8J

APU_SIC APU_SID ALERT_L ALLOW_STOP

ALLOW_STOP

APU_RST#

APU_PWRGD

APU_SVT

APU_SVC

APU_SVD

A

APU_SVD<48>

APU_SVT<48>

APU_PWRGD

2 2

APU_RST#< 11> APU_PWRGD<11,48>

ESD request

@ESD@

The VDDIO voltage source provides power to the DDR3 output drivers and other

3 3

miscellaneous functions within the processor. VDDIO_SENSE is internally tied to the processor substrate and is used for sensing the memory controller and interface voltage level at the processor. VDDIO_SENSE can be routed as a single-ended signal, or it can be routed with VSS_SENSE as its complement.

+1.5V_APU

RP9

SD309100180RP9

SD309100180 1 8 2 7 3 6 4 5

+1.5VS

4 4

1K_0804_8P4R_5%

1 2

R348 1K_0402_5%DEBUG@R348 1K_0402_5%DEBUG@

1 2

R52 300_0402_5%R52 300_0402_5%

1 2

R56 300_0402_5%R56 300_0402_5%

1 2

R40 1K_0402_5%

DEBUG@

1 2

R35 1K_0402_5%

DEBUG@

1 2

R38 1K_0402_5%

DEBUG@

C47 0.1U_0402_16V7KLVDS@ C47 0.1U_0402_16V7KLVDS@

1 2

C49 0.1U_0402_16V7KLVDS@ C49 0.1U_0402_16V7KLVDS@

Place near APU

1 2

C53 0.1U_0402_16V7KC53 0.1U_0402 _16V7K

1 2

C54 0.1U_0402_16V7KC54 0.1U_0402 _16V7K

1 2

C55 0.1U_0402_16V7KC55 0.1U_0402 _16V7K

1 2

C56 0.1U_0402_16V7KC56 0.1U_0402 _16V7K

1 2

C57 0.1U_0402_16V7KC57 0.1U_0402 _16V7K

1 2

C58 0.1U_0402_16V7KC58 0.1U_0402 _16V7K

1 2

C59 0.1U_0402_16V7KC59 0.1U_0402 _16V7K

1 2

C60 0.1U_0402_16V7KC60 0.1U_0402 _16V7K

C61 0.1U_0402_16V7KC61 0.1U_0402_16V7K C62 0.1U_0402_16V7KC62 0.1U_0402_16V7K

C63 0.1U_0402_16V7KC63 0.1U_0402_16V7K C64 0.1U_0402_16V7KC64 0.1U_0402_16V7K

C65 0.1U_0402_16V7KC65 0.1U_0402_16V7K C66 0.1U_0402_16V7KC66 0.1U_0402_16V7K

C67 0.1U_0402_16V7KC67 0.1U_0402_16V7K C68 0.1U_0402_16V7KC68 0.1U_0402_16V7K

RH140 0_0402_1% SHORT PAD@RH140 0_0402_1% SHORT PAD@ RH141 0_0402_1% SHORT PAD@RH141 0_0402_1% SHORT PAD@

Route as differential w

1 2 1 2

APU_CLK<11> APU_CLK#<11>

APU_DISP_CLK<11> APU_DISP_CLK#<11>

1 2 1 2

APU_PROCHOT#<11>

APU_VDD_SEN_L<48>

APU_VDDNB_SEN_H<48>

APU_VDD_SEN_H<48>

ith APU_VDD_SEN_L

APU_SIC APU_SID

APU_THERMTRIP# ALERT_L

APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBRDY APU_DBREQ#

CPU TSI interface level shift

DP0_TXP0DP0_TXP0 DP0_TXN0DP0_TXN0

DP1_TXP0 DP1_TXN0

DP1_TXP1 DP1_TXN1

DP1_TXP2 DP1_TXN2

DP1_TXP3 DP1_TXN3

DP2_TXP0 DP2_TXN0

DP2_TXP1 DP2_TXN1

DP2_TXP2 DP2_TXN2

DP2_TXP3 DP2_TXN3

+3VS

APU_SID

APU_SIC

B

L3

DP0_TXP0

L2

DP0_TXN0

K5

DP0_TXP1

K4

DP0_TXN1

K2

DP0_TXP2

K1

DP0_TXN2

J3

DP0_TXP3

J2

DP0_TXN3

H5

DP1_TXP0

H4

DP1_TXN0

H2

DP1_TXP1

H1

DP1_TXN1

G3

DP1_TXP2

G2

DP1_TXN2

F2

DP1_TXP3

F1

DP1_TXN3

L9

DP2_TXP0

L8

DP2_TXN0

L5

DP2_TXP1

L6

DP2_TXN1

K8

DP2_TXP2

K7

DP2_TXN2

J6

DP2_TXP3

J5

DP2_TXN3

AE11

CLKIN_H

AD11

CLKIN_L

AB11

DISP_CLKIN_H

AA11

DISP_CLKIN_L

B3

SVC

A3

SVD

C3

SVT

AG12

SIC

AH12

SID

AF10

RESET_L

AB12

PWROK

AC10

PROCHOT_L

AE12

THERMTRIP_L

AF12

ALERT_L

H10

TDI

J10

TDO

F10

TCK

G10

TMS

F9

TRST_L

G9

DBRDY

H9

DBREQ_L

B4

VSS_SENSE

C5

VDDP_SENSE

A4

VDDNB_SENSE

A5

VDDIO_SENSE

C4

VDD_SENSE

B5

VDDR_SENSE

ME@

1 2

R33

31.6K_0402_1%

B

JCPU1D

ANALOG/DISPLAY/MISC

LVDS

DISPLAY PORT 0

To FCH

DISPLAY PORT MISC.

HDMI

DISPLAY PORT 2 DISPLAY P ORT 1

TEST

CTRL SE R. CLK

JTAG

SENSE

LOTES_ACA-ZIF-109-P12-A_FS1R2

1 2

C69 0.1U_0402_16V4ZC69 0.1U_0402_16V4Z

1 2

R34

30K_0402_1%

G

2

Q3

13

D

S

D

S

BSH111 1N_SOT23-3

G

2

Q6

13

D

S

D

S

BSH111 1N_SOT23-3

DP0_AUXP DP0_AUXN

DP1_AUXP DP1_AUXN

DP2_AUXP DP2_AUXN

DP3_AUXP DP3_AUXN

DP4_AUXP DP4_AUXN

DP5_AUXP DP5_AUXN

DP0_HPD DP1_HPD DP2_HPD DP3_HPD DP4_HPD DP5_HPD

DP_BLON

DP_DIGON

DP_VARY_BL

DP_AUX_ZVSS

TEST10 TEST14 TEST15 TEST16 TEST17 TEST18 TEST19 TEST20 TEST24

TEST25_H

TEST25_L

TEST28_H

TEST28_L

TEST30_H

TEST30_L

TEST31

TEST32_H

TEST32_L

TEST35

DMAACTIVE_L

RSVD1 RSVD2 RSVD3

RSVD

RSVD4

C

D1

DP0_AUXP

D2

DP0_AUXN

E1

ML_VGA_AUXP

E2

ML_VGA_AUXN

D5 D6

E5 E6

F5 F6

G5 G6

D3 E3 D7 E7 F7 G7

C6 B6 A6

C1

DP_AUX_ZVSS

AD12

TEST6

M18

TEST9

N18 F11 G11 H11 J11 F12

APU_TEST18

G12

APU_TEST19

J12

APU_TEST20

H12

APU_TEST24

AE10

TEST25_H

AD10

TEST25_L

L10 M10 P19 R19 K22

APU_TEST31

T19 N19 AA12

APU_TEST35

W10

FS1R2

AC12

P18

TEST4

R18

TEST5

Y10 AA10 Y12 K21

BSH111, the Vgs is: min = 0.4V Max = 1.3V

EC_SMB_DA2_SUS <36>

EC_SMB_CK2_SUS <36>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

1 2

C48 0.1U_0402_16V7K LVDS@C48 0.1U_0402_16V7K LVDS@

1 2

C50 0.1U_0402_16V7K LVDS@C50 0.1U_0402_16V7K LVDS@

1 2

R15 150_0402_1%R15 150_0402_1%

T1

T1 T2

T2 T3

T3 T4

T4 T5

T5 T6

T6

R21 510_0402_1%R21 510_0402_1% R25 510_0402_1%R25 510_0402_1%

TEST POINT@

T7

TEST POINT@

T8

R27 39.2_0402_1%R27 39.2_0402_1%

1 2

R29 300_0402_5%R29 300_0402_5%

R30 300_0402_5%DEBUG@R30 300_0402_5%DEBUG@ R32 10K_0402_5%R32 10K_0402_5%

TEST POINT@

T9

TEST POINT@

T10

1 2

C51 0.1U_0402_16V7KC51 0.1U_0402_16V7K

1 2

C52 0.1U_0402_16V7KC52 0.1U_0402_16V7K

DP0_HPD <26> FCH_CRT_HPD <12> TMDS_B_HPD# <29>

DP_INT_PWM <26>

TEST POINT@

TEST POINT@ TEST POINT@

1K_0804_8P4R_5%

SD309100180

RP3

1 8 2 7 3 6 4 5 1 2 1 2

1 2

1 2 1 2

ALLOW_STOP <11>

TEST POINT@ TEST POINT@

TEST POINT@

To EC

2012/11/13 2013/11/12

C

HDMICLK_NB <29> HDMIDAT_NB <29>

+1.2VS

+1.5V_APU

+3VALW

Compal Secret Data

Deciphered Date

To HDMI

RP1

10K_0804_8P4R_5%

D

DP0_AUXP_C <26 > DP0_AUXN_C <26>

ML_VGA_AUXP_C <12> ML_VGA_AUXN_C <12>

Asserted as an input to force the processor into the HTC-active state

APU_PROCHOT#

THERMTRIP shutdown temperature: 125 degree

1K_0402_5%

APU_THERMTRIP#

+1.5V

APU_TRST#

18 27 36 45

D

To LVDS Translater

To FCH

+1.5V_APU

R12

1K_0402_5%

1 2

+1.5V_APU

12

R23

1 2

B

2

E

3 1

R23 10K_0402_5%

10K_0402_5%

Q2

C

R22

MMBT3904_NL_SOT23-3

11/14 Change net name

HDT Debug conn

JHDT1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

SAMTE_ASP-136446-07-B

ME@

Title

Size Document Number Rev

Custom

Date: Sheet of

If not used, pins are left unconnected (DG ref.) 20101111

ML_VGA_AUXP

ML_VGA_AUXN

DP0_AUXP

DP0_AUXN

1 2

R45 0_0402_1%

SHORT PAD@

Indicates to the FCH that a thermal trip has occurred. Its assertion will cause the FCH to transition the system to S5 immediately

1 2

R28 0_0402_1%

SHORT PAD@

SIT: For ESD requirement

+1.5V

Close to Header

RP2

1 8 2 7 3 6 4 5

1K_0804_8P4R_5%

SD309100180

1 2

R596 1K_0402_5%R596 1K_0402_5%

2

APU_TCK

4

APU_TMS

6

APU_TDI

8

APU_TDO

10

APU_PWRGD

12

APU_RST#

14

APU_DBRDY

16

APU_DBREQ#

18

APU_TEST19

20

APU_TEST18

Compal Electronics, Inc.

FS1r2 Display/MISC/HDT

E

H_PROCHOT# <36,48>

1

C438

ESD@

1000P_0402_50V7K

2

APU_DBREQ#

E

12

H_THERMTRIP# <13>

APU_TDI APU_TMS APU_TCK APU_TRST#

7 57Friday, April 12, 2013

R8 1.8K_0402_5%R8 1.8K_0402_5%

R9 1.8K_0402_5%R9 1.8K_0402_5%

R10 1.8K_0402_5%R10 1.8K_0402_5%

R11 1.8K_0402_5%R11 1.8K_0402_5%

VALGD MB L

0.1

A

Power Name

VDD

APU_CORE

+

VDDNB +APU_CORE_NB

VDDIO +1.5V

VDDP / VDDR +1.2VS

VDDA

1 1

+2.5VS

2 2

3 3

Consumption

5A / 3.5A

VDDP decoupling

180P_0402_50V8J

C107

C106

1

2

60A

29A

3.2A

0.5A

180P_0402_50V8J

C108

0.22U_0402_6.3V6K

1

2

+APU_CORE_NB

+1.2VS

C109

0.22U_0402_6.3V6K

C109

0.22U_0402_6.3V6K

1

2

+1.5V_APU

+APU_CORE

F8

VDD_1

H6

VDD_2

J1

VDD_3

J14

VDD_4

P6

VDD_5

P10

VDD_6

J16

VDD_7

J18

VDD_8

J9

VDD_9

K19

VDD_10

K3

VDD_11

K17

VDD_12

M3

VDD_13

K6

VDD_14

V10

VDD_15

V18

VDD_16

V3

VDD_17

F3

VDD_18

L18

VDD_19

V6

VDD_20

W1

VDD_21

T18

VDD_22

Y14

VDD_23

AA1

VDD_24

AB6

VDD_25

AC1

VDD_26

R1

VDD_27

P3

VDD_28

K10

VDD_29

H3

VDD_30

M19

VDD_31

C8

VDDNB_1

D10

VDDNB_2

B8

VDDNB_3

B12

VDDNB_4

C9

VDDNB_5

A9

VDDNB_6

A10

VDDNB_7

A8

VDDNB_8

A11

VDDNB_9

E10

VDDNB_10

E11

VDDNB_11

C10

VDDNB_12

H26

VDDIO_1

K20

VDDIO_2

J28

VDDIO_3

K23

VDDIO_4

K26

VDDIO_5

L22

VDDIO_6

L25

VDDIO_7

L28

VDDIO_8

M20

VDDIO_9

M23

VDDIO_10

M26

VDDIO_11

N22

VDDIO_12

N25

VDDIO_13

N28

VDDIO_14

P20

VDDIO_15

P23

VDDIO_16

P26

VDDIO_17

AA28

VDDIO_18

AH6

VDDP_1

AH5

VDDP_2

AH4

VDDP_3

AH3

VDDP_4

AH7

VDDP_5

AB10

VDDA

LOTES_ACA-ZIF-109-P12-A_FS1R2

ME@

JCPU1E

VDD_32 VDD_33 VDD_34 VDD_35 VDD_36 VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43 VDD_44 VDD_45 VDD_46 VDD_47 VDD_48 VDD_49 VDD_50 VDD_51 VDD_52 VDD_53 VDD_54 VDD_55 VDD_56 VDD_57 VDD_58 VDD_59 VDD_60 VDD_61 VDD_62

VDDNB_13 VDDNB_14 VDDNB_15 VDDNB_16 VDDNB_17 VDDNB_18 VDDNB_19 VDDNB_20 VDDNB_21 VDDNB_22 VDDNB_23

VDDNB_CAP_1 VDDNB_CAP_2

VDDIO_19 VDDIO_20 VDDIO_21 VDDIO_22 VDDIO_23 VDDIO_24 VDDIO_25 VDDIO_26 VDDIO_27 VDDIO_28 VDDIO_29 VDDIO_30 VDDIO_31 VDDIO_32 VDDIO_33 VDDIO_34 VDDIO_35 VDDIO_36

VDDR_1 VDDR_2 VDDR_3 VDDR_4

B

+APU_CORE

R11 T10 H8 G1 U11 W11 W13 W15 W17 W19 AB3 AD3 AD6 AE1 L1 Y6 M6 N11 N1 T3 T6 U19 U1 Y16 Y18 Y3 D4 F4 AF6 AF3 L11

C11 C12 D9 D8 D12 D11 B11 A12 B10 E12 B9

K13 K12

T23 T26 U22 U25 U28 Y26 T20 R28 R25 R22 V20 V23 V26 W22 W25 W28 Y24 G28

AG10 AH8 AH9 AH10

+APU_CORE_NB

+1.5V_APU

C110

180P_0402_50V8J

C110

180P_0402_50V8J

1

2

+APU_CORE

C70

0.22U_0402_6.3V6K

C70

0.22U_0402_6.3V6K

1

2

+APU_CORE_NB

C77

0.22U_0402_6.3V6K

C77

0.22U_0402_6.3V6K

1

2

+1.5V_APU

+VDDNB_CAP

C99

22U_0603_6.3V6M

C99

22U_0603_6.3V6M

C100

22U_0603_6.3V6M

C100

22U_0603_6.3V6M

C105

1

2

Northbridge Power Pins for Remote Decoupling

C111

180P_0402_50V8J

C111

180P_0402_50V8J

C112

1000P_0402_50V7K

C112

1000P_0402_50V7K

1

2

C

C71

0.01U_0402_16V7K

C71

0.01U_0402_16V7K

C76

0.01U_0402_16V7K

C76

C75

0.22U_0402_6.3V6K

C75

0.22U_0402_6.3V6K

1

2

C78

0.22U_0402_6.3V6K

C78

0.22U_0402_6.3V6K

C79

180P_0402_50V8J

C79

180P_0402_50V8J

1

2

0.01U_0402_16V7K

C73

180P_0402_50V8J

C73

C72

0.01U_0402_16V7K

C72

0.01U_0402_16V7K

1

2

C80

180P_0402_50V8J

C80

180P_0402_50V8J

1

2

180P_0402_50V8J

C74

180P_0402_50V8J

C74

1

2

C81

180P_0402_50V8J

C81

180P_0402_50V8J

1

2

180P_0402_50V8J

1

2

(330uF_6.3V_4.2L_ESR17m)*1=(SF000002Z00)

4.7U_0603_6.3V6K

C85

22U_0603_6.3V6M

C85

22U_0603_6.3V6M

C84

22U_0603_6.3V6M

C84

22U_0603_6.3V6M

C83

22U_0603_6.3V6M

C83

22U_0603_6.3V6M

1

2

180P_0402_50V8J

1

2

4.7U_0603_6.3V6K

C86

22U_0603_6.3V6M

C86

22U_0603_6.3V6M

C88

C87

1

2

VDDR decoupling

+1.2VS

C117

0.22U_0402_6.3V6K

C117

0.22U_0402_6.3V6K

C116

0.22U_0402_6.3V6K

C116

0.22U_0402_6.3V6K

1

2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K C90

C90

C89

1

2

C92

0.22U_0402_6.3V6K

C92

0.22U_0402_6.3V6K

C91

0.22U_0402_6.3V6K

C91

0.22U_0402_6.3V6K

C93

1

2

+1.5V

C101

0.22U_0402_6.3V6K

C101

0.22U_0402_6.3V6K

1

2

+1.5V +1.5V_APU

1

2

across VDDIO an d VSS split

C102

0.22U_0402_6.3V6K

C102

0.22U_0402_6.3V6K

C104

180P_0402_50V8J

C104

180P_0402_50V8J

1

2

SIT:Need Short

D

C94

0.22U_0402_6.3V6K

C94

0.22U_0402_6.3V6K

C95

0.22U_0402_6.3V6K

1

2

C114

180P_0402_50V8J

C114

180P_0402_50V8J

1

2

JUMP@

J2

1 2

PAD-OPEN 4x4m

Need Short

JUMP@

J3

1 2

PAD-OPEN 4x4m

E

JCPU1F

J20

VSS_1

L4

VSS_2

R7

VSS_3

W18

VSS_4

A15

VSS_5

AB17

VSS_6

AC22

VSS_7

AE21

VSS_8

AF24

VSS_9

AH23

VSS_10

AH25

VSS_11

B7

VSS_12

C14

VSS_13

C16

VSS_14

C2

VSS_15

C20

VSS_16

C22

VSS_17

C24

VSS_18

C26

VSS_19

C28

VSS_20

D13

VSS_21

D15

VSS_22

D17

VSS_23

D19

VSS_24

D23

VSS_25

D25

VSS_26

D27

VSS_27

E4

VSS_28

E9

VSS_29

F14

VSS_30

F16

VSS_31

F18

VSS_32

F20

VSS_33

F22

VSS_34

C98

330U_2.5V_M+C98

C97

180P_0402_50V8J

C97

0.22U_0402_6.3V6K

180P_0402_50V8J

C96

0.22U_0402_6.3V6K

C96

0.22U_0402_6.3V6K

1

2

330U_2.5V_M

1

+

2

F26

VSS_35

F28

VSS_36

G13

VSS_37

G15

VSS_38

G17

VSS_39

G19

VSS_40

G21

VSS_41

G23

VSS_42

G25

VSS_43

G4

VSS_44

J22

VSS_45

J24

VSS_46

J4

VSS_47

J7

VSS_48

K11

VSS_49

K14

VSS_50

K9

VSS_51

AC11

VSS_52

L19

VSS_53

L7

VSS_54

M11

VSS_55

AF11

VSS_56

V19

VSS_57

V9

VSS_58

W16

VSS_59

W4

VSS_60

W7

VSS_61

Y11

VSS_62

Y20

VSS_63

Y22

VSS_64

Y9

VSS_65

A17

VSS_66

A13

VSS_67

K16

VSS_68

F24

VSS_69

G8

VSS_70

H7

VSS_71

J8

VSS_72

LOTES_ACA-ZIF-109-P12-A_FS1R2

ME@

VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98

VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143

A19 A21 A23 A25 A7 AA4 AA7 AB13 AB15 AB19 AB21 AB23 AB25 AB27 AB9 AC14 AC16 AC18 AC20 AC24 AC26 AC28 AC4 AC7 AD9 AE13 AE15 AE17 M9 N10 N4 N7 R10 R4 T11 T9 U10 U18 U4 U7 V11 AE19 AE23 AE25 AE27 AE4 AE7 AF14 AF16 AF18 AF20 AF22 AF26 AF28 AF9 AG4 AG7 AH13 AH15 AH17 AH19 AH21 P9 C18 D21 W14 P11 C7 E8 K18 W12

Demo Board Capacitor

APU_CORE 22uF x 10

0.22uF x 2

0.01uF x 3 180pF x 2

CORE_NB 22uF x 2 10uF x 1

0.22uF x 2 180pF x 3

CORE_NB_CAP 22uF x 2 180pF x 1

VDDIO_SUS (CPU side) 22uF x 4

4.7uF x 4

0.22uF x 6 +2(split) 180pF x 1 + 2(split)

4 4

+2.5VS

L1

L1 FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

12

C118

3300P_0402_50V7K

C118

3300P_0402_50V7K

C119

0.22U_0402_6.3V6K

C119

0.22U_0402_6.3V6K

1

12

2

Check

A

40mil

+VDDA

C120

4.7U_0402_6.3V6M

C120

4.7U_0402_6.3V6M

1

2

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/11/13 2013/11/12

Compal Secret Data

Deciphered Date

D

VDDP 0

.22uF x 2

180pF x 2

VDDR

0.22uF x 2 1nF x 4 180pF x 2

Title

Size Document Number Rev

Custom

Date: Sheet of

VDDA

4.7uF x 1

0.22uF x 1

3.3nF x 1

Compal Electronics, Inc.

FS1r2 PWR/GND

VALGD MB L

E

VDDIO_SUS (DIMM x2) 100uF x 2

0.1uF x 12

8 57Friday, April 12, 2013

0.1

A

B

C

D

E

+VREF_DQ

DDRA_SDQ0 DDRA_SDQ1

DDRA_SDM0

DDRA_SDQ2

1 1

DDRA_SDQS1#<6> DDRA_SDQS1<6>

DDRA_SDQS2#<6> DDRA_SDQS2<6>

DDRA_CKE0<6>

2 2

3 3

+3VS

4 4

2.2U_0603_6.3V6K

DDRA_SBS2#<6>

DDRA_CLK0<6> DDRA_CLK0#<6>

DDRA_SBS0#<6>

DDRA_SWE#<6>

DDRA_SCAS#<6> DDRA_ODT0 <6>

DDRA_SCS1#<6>

DDRA_SDQS4#<6> DDRA_SDQS4<6>

DDRA_SDQS6#<6> DDRA_SDQS6<6>

1

2

1

C132

0.1U_0402_16V4Z

2

C131

DDRA_SDQ3

DDRA_SDQ8 DDRA_SDQ9

DDRA_SDQS1# DDRA_SDQS1

DDRA_SDQ10 DDRA_SDQ11

DDRA_SDQ16 DDRA_SDQ17

DDRA_SDQS2# DDRA_SDQS2

DDRA_SDQ18 DDRA_SDQ19

DDRA_SDQ24 DDRA_SDQ25

DDRA_SDM3

DDRA_SDQ26 DDRA_SDQ27

DDRA_CKE0

DDRA_SBS2#

DDRA_SMA12 DDRA_SMA9

DDRA_SMA8 DDRA_SMA5

DDRA_SMA3 DDRA_SMA1

DDRA_CLK0 DDRA_CLK0#

DDRA_SMA10 DDRA_SBS0#

DDRA_SWE# DDRA_SCAS# DDRA_ODT0

DDRA_SMA13 DDRA_SCS1#

DDRA_SDQ32 DDRA_SDQ33

DDRA_SDQS4# DDRA_SDQS4

DDRA_SDQ34 DDRA_SDQ35

DDRA_SDQ40 DDRA_SDQ41

DDRA_SDM5

DDRA_SDQ42 DDRA_SDQ43

DDRA_SDQ48 DDRA_SDQ49

DDRA_SDQS6# DDRA_SDQS6

DDRA_SDQ50 DDRA_SDQ51

DDRA_SDQ56 DDRA_SDQ57

DDRA_SDM7

DDRA_SDQ58 DDRA_SDQ59

+1.5V +1.5V

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DDRA_SA0

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

VSS3

DQS#0

DQS0

VSS6

VSS8 DQ12 DQ13

VSS10

DQ14 DQ15

DQ20 DQ21

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

VSS31

DQ38 DQ39

VSS33

DQ44

DQ45 VSS35 DQS#5

DQS5

VSS38

DQ46

DQ47 VSS40

DQ52

DQ53 VSS42

VSS43

DQ54

DQ55 VSS45

DQ60

DQ61 VSS47 DQS#7

DQS7

VSS50

DQ62

DQ63 VSS52

EVENT#

VTT2

FOX_AS0A626-U8SN-7F

ME@

DQ4 DQ5

DQ6 DQ7

DM1

DM2

CK1

BA1

NC2

DM4

DM6

SDA SCL

2 4

DDRA_SDQ4

6

DDRA_SDQ5

8 10

DDRA_SDQS0#

12

DDRA_SDQS0

14 16

DDRA_SDQ6

18

DDRA_SDQ7

20 22

DDRA_SDQ12

24

DDRA_SDQ13

26 28

DDRA_SDM1

30

MEM_MA_RST#

32 34

DDRA_SDQ14

36

DDRA_SDQ15

38 40

DDRA_SDQ20

42

DDRA_SDQ21

44 46

DDRA_SDM2

48 50

DDRA_SDQ22

52

DDRA_SDQ23

54 56

DDRA_SDQ28

58

DDRA_SDQ29

60 62

DDRA_SDQS3#

64

DDRA_SDQS3

66 68

DDRA_SDQ30

70

DDRA_SDQ31

72

74

DDRA_CKE1

76 78

A15 A14

A11

A7

A6 A4

A2 A0

S0#

G2

DDRA_SMA15

80

DDRA_SMA14

82 84

DDRA_SMA11

86

DDRA_SMA7

88 90

DDRA_SMA6

92

DDRA_SMA4

94 96

DDRA_SMA2

98

DDRA_SMA0

100 102

DDRA_CLK1

104

DDRA_CLK1#

106 108

DDRA_SBS1#

110

DDRA_SRAS#

112 114

DDRA_SCS0#

116 118 120

DDRA_ODT1

122 124 126 128 130

DDRA_SDQ36

132

DDRA_SDQ37

134 136

DDRA_SDM4

138 140

DDRA_SDQ38

142

DDRA_SDQ39

144 146

DDRA_SDQ44

148

DDRA_SDQ45

150 152

DDRA_SDQS5#

154

DDRA_SDQS5

156 158

DDRA_SDQ46

160

DDRA_SDQ47

162 164

DDRA_SDQ52

166

DDRA_SDQ53

168 170

DDRA_SDM6

172 174

DDRA_SDQ54

176

DDRA_SDQ55

178 180

DDRA_SDQ60

182

DDRA_SDQ61

184 186

DDRA_SDQS7#

188

DDRA_SDQS7

190 192

DDRA_SDQ62

194

DDRA_SDQ63

196 198

MEM_MA_EVENT#

200 202 204

206

+0.75VS

DDRA_SDQS0# <6> DDRA_SDQS0 <6 >

MEM_MA_RST# <6>

DDRA_SDQS3# <6> DDRA_SDQS3 <6 >

DDRA_CKE1 <6>

DDRA_CLK1 <6> DDRA_CLK1# <6>

DDRA_SBS1# <6> DDRA_SRAS# <6>

DDRA_SCS0# <6>

DDRA_ODT1 <6>

+VREF_CA

DDRA_SDQS5# < 6> DDRA_SDQS5 <6 >

DDRA_SDQS7# < 6> DDRA_SDQS7 <6 >

MEM_MA_EVENT# <6>

FCH_SDATA0 <10,13,30> FCH_SCLK0 <10 ,13,30>

DDRA_SDQ[0..63]

DDRA_SDM[0..7]

DDRA_SMA[0..15]

+1.5V

2

1

0.1U_0402_16V4Z

+VREF_DQ

DDRA_SDQ[0..63] <6>

DDRA_SDM[0..7] <6>

DDRA_SMA[0..15] <6>

Place near DIMM1

0.1U_0402_16V4Z

2

C122

C121

1

+VREF_DQ +VREF_CA

1

C127

2

0.1U_0402_16V4Z

2

C123

1

0.1U_0402_16V4Z

1

C128

2

1000P_0402_50V7K

0.1U_0402_16V4Z

2

C124

1

+1.5V

R65

R65 1K_0402_1%

1K_0402_1%

1 2

R67

R67 1K_0402_1%

1K_0402_1%

1 2

2

C125

1

0.1U_0402_16V4Z

2

C126

1

+VREF_CA

+1.5V

R66

R66 1K_0402_1%

1K_0402_1%

15mil15mil

1

C129

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z 1000P_0402_50V7K

1000P_0402_50V7K

1 2

1

C130

R68

R68 1K_0402_1%

2

1K_0402_1%

1 2

Security Classification

Issued Date

standard H:8mm

<Address: 00>

A

B

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/11/13 2013/11/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

DDRIII SO-DIMM 1

VALGD MB L

9 57Friday, April 12, 2013

E

0.1

A

B

C

D

E

DQ4 DQ5

VSS3

VSS6

DQ6 DQ7

VSS8

DM1

DM2

CK1

CK1#

BA1

NC2

DM4

DM6

SDA SCL

VTT2

+1.5V+1.5V

2 4

DDRB_SDQ4

6

DDRB_SDQ5

8 10

DDRB_SDQS0#

12

DDRB_SDQS0

14 16

DDRB_SDQ6

18

DDRB_SDQ7

20 22

DDRB_SDQ12

24

DDRB_SDQ13

26 28

DDRB_SDM1

30

MEM_MB_RST#

32 34

DDRB_SDQ14

36

DDRB_SDQ15

38 40

DDRB_SDQ20

42

DDRB_SDQ21

44 46

DDRB_SDM2

48 50

DDRB_SDQ22

52

DDRB_SDQ23

54 56

DDRB_SDQ28

58

DDRB_SDQ29

60 62

DDRB_SDQS3#

64

DDRB_SDQS3

66 68

DDRB_SDQ30

70

DDRB_SDQ31

72

74

DDRB_CKE1

76 78

A15 A14

A11

A7

A6 A4

A2 A0

S0#

G2

DDRB_SMA15

80

DDRB_SMA14

82 84

DDRB_SMA11

86

DDRB_SMA7

88 90

DDRB_SMA6

92

DDRB_SMA4

94 96

DDRB_SMA2

98

DDRB_SMA0

100 102

DDRB_CLK1

104

DDRB_CLK1#

106 108

DDRB_SBS1#

110

DDRB_SRAS#

112 114

DDRB_SCS0#

116

DDRB_ODT0DDRB_SCAS#

118 120

DDRB_ODT1

122 124 126 128 130

DDRB_SDQ36

132

DDRB_SDQ37

134 136

DDRB_SDM4

138 140

DDRB_SDQ38

142

DDRB_SDQ39

144 146

DDRB_SDQ44

148

DDRB_SDQ45

150 152

DDRB_SDQS5#

154

DDRB_SDQS5

156 158

DDRB_SDQ46

160

DDRB_SDQ47

162 164

DDRB_SDQ52

166

DDRB_SDQ53

168 170

DDRB_SDM6

172 174

DDRB_SDQ54

176

DDRB_SDQ55

178 180

DDRB_SDQ60

182

DDRB_SDQ61

184 186

DDRB_SDQS7#

188

DDRB_SDQS7

190 192

DDRB_SDQ62

194

DDRB_SDQ63

196 198

MEM_MB_EVENT#

200 202 204

206

+0.75VS

DDRB_SDQS0# < 6> DDRB_SDQS0 <6 >

MEM_MB_RST# <6>

DDRB_SDQS3# < 6> DDRB_SDQS3 <6 >

DDRB_CKE1 <6>

DDRB_CLK1 < 6> DDRB_CLK1# <6>

DDRB_SBS1# <6> DDRB_SRAS# <6>

DDRB_SCS0# <6> DDRB_ODT0 <6>

DDRB_ODT1 <6>

+VREF_CA

DDRB_SDQS5# < 6> DDRB_SDQS5 <6 >

DDRB_SDQS7# < 6> DDRB_SDQS7 <6 >

MEM_MB_EVENT# <6>

FCH_SDATA0 <13,30,9> FCH_SCLK0 <13 ,30,9>

DDRB_SDQ[0..63]

DDRB_SDM[0..7]

DDRB_SMA[0..15]

DDRB_SDQ[0..63] <6>

DDRB_SDM[0..7] <6>

DDRB_SMA[0..15] <6>

0.1U_0402_16V4Z

C143

0.1U_0402_16V4Z

+VREF_DQ

15mil 1

+VREF_DQ +VREF_CA

1000P_0402_50V7K

0.1U_0402_16V4Z

+1.5V

1

2

C137

1

+0.75VS

2

1

C133

1

2

0.1U_0402_16V4Z

2

C138

1

2

C134

2

C139

1

0.1U_0402_16V4Z

C144

4.7U_0603_6.3V6K

0.1U_0402_16V4Z

2

1

SIT:1/26 change to POLY

+VREF_CA

0.1U_0402_16V4Z

1

2

C140

0.1U_0402_16V4Z

5mil

1000P_0402_50V7K

C135

1

C136

2

Place near DIMM2

0.1U_0402_16V4Z

2

C141

C142

1

+1.5V

1

+

C145

@

220U_D2_2VY_R15M

2

SGA00004L00

C142

1

+VREF_DQ

DDRB_SDQ0 DDRB_SDQ1

DDRB_SDM0

DDRB_SDQ2

1 1

DDRB_SDQS1#<6> DDRB_SDQS1<6>

DDRB_SDQS2#<6> DDRB_SDQS2<6>

DDRB_CKE0<6>

2 2

3 3

4 4

+3VS

DDRB_SBS2#<6>

DDRB_CLK0<6> DDRB_CLK0#<6>

DDRB_SBS0#<6>

DDRB_SWE#<6>

DDRB_SCAS#<6>

DDRB_SCS1#<6>

DDRB_SDQS4#<6> DDRB_SDQS4<6>

DDRB_SDQS6#<6> DDRB_SDQS6<6>

R71 10K_0402_5%R71 10K _0402_5%

1 2

DDRB_SDQ3

DDRB_SDQ8 DDRB_SDQ9

DDRB_SDQS1# DDRB_SDQS1

DDRB_SDQ10 DDRB_SDQ11

DDRB_SDQ16 DDRB_SDQ17

DDRB_SDQS2# DDRB_SDQS2

DDRB_SDQ18 DDRB_SDQ19

DDRB_SDQ24 DDRB_SDQ25

DDRB_SDM3

DDRB_SDQ26 DDRB_SDQ27

DDRB_CKE0

DDRB_SBS2#

DDRB_SMA12 DDRB_SMA9

DDRB_SMA8 DDRB_SMA5

DDRB_SMA3 DDRB_SMA1

DDRB_CLK0 DDRB_CLK0#

DDRB_SMA10 DDRB_SBS0#

DDRB_SWE#

DDRB_SMA13 DDRB_SCS1#

DDRB_SDQ32 DDRB_SDQ33

DDRB_SDQS4# DDRB_SDQS4

DDRB_SDQ34 DDRB_SDQ35

DDRB_SDQ40 DDRB_SDQ41

DDRB_SDM5

DDRB_SDQ42 DDRB_SDQ43

DDRB_SDQ48 DDRB_SDQ49

DDRB_SDQS6# DDRB_SDQS6

DDRB_SDQ50 DDRB_SDQ51

DDRB_SDQ56 DDRB_SDQ57

DDRB_SDM7

DDRB_SDQ58 DDRB_SDQ59

DDRB_SA0

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U4SN-7F

E

@

M

DQS#0

DQS0

DQ12 DQ13

VSS10

DQ14 DQ15

DQ20 DQ21

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

VSS31

DQ38 DQ39

VSS33

DQ44

DQ45 VSS35 DQS#5

DQS5 VSS38

DQ46

DQ47 VSS40

DQ52

DQ53 VSS42

VSS43

DQ54

DQ55 VSS45

DQ60

DQ61 VSS47 DQS#7

DQS7 VSS50

DQ62

DQ63 VSS52

EVENT#

Security Classification

Issued Date

Standard H:4mm

<Address: 01>

A

B

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/11/13 2013/11/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

DDRIII SO-DIMM 2

VALGD MB L

10 57Friday, April 12, 2013

E

0.1

A

APU_PCIE_RST#<16,30,31>

PLT_RST#<36>

1 2

C146150P_0402_50V8J C146150P_0402_50V8J

UMI_RXP0<5> UMI_RXN0<5> UMI_RXP1<5> UMI_RXN1<5> UMI_RXP2<5> UMI_RXN2<5> UMI_RXP3<5>

GCLK_PCH_25MHZ<38>

C157

1 2

10P_0402_50V8J

C160

1 2

10P_0402_50V8J

UMI_RXN3<5>

UMI_TXP0<5> UMI_TXN0<5> UMI_TXP1<5> UMI_TXN1<5> UMI_TXP2<5> UMI_TXN2<5> UMI_TXP3<5> UMI_TXN3<5>

+VDDAN_11_PCIE

CLK_PCIE_VGA<16> CLK_PCIE_VGA#<16>

CLK_PCIE_WLAN1<30> CLK_PCIE_WLAN1#<30>

CLK_PCIE_LAN<31> CLK_PCIE_LAN#<31>

NOGCLK@

1 1

2 2

VGA

WLAN

LAN

3 3

4 4

25MHZ_10PF_X3G025000DC1H

X1

SHORT PAD@

12

0_0402_1%

R92

1 2

C153 0.1U_0402_16V7KC153 0.1U_0402_16V7K

1 2

C147 0.1U_0402_16V7KC147 0.1U_0402_16V7K

1 2

C148 0.1U_0402_16V7KC148 0.1U_0402_16V7K

1 2

C154 0.1U_0402_16V7KC154 0.1U_0402_16V7K

1 2

C149 0.1U_0402_16V7KC149 0.1U_0402_16V7K

1 2

C150 0.1U_0402_16V7KC150 0.1U_0402_16V7K

1 2

C151 0.1U_0402_16V7KC151 0.1U_0402_16V7K

1 2

C152 0.1U_0402_16V7KC152 0.1U_0402_16V7K

+1.1VS_CKVDD

APU

4

1

NOGCLK@

NC

OSC

OSC3NC

2

A

1 2

R74 33_0402_5%R74 33_ 0402_5%

1 2

R75 590_0402_1%R75 590_0402_1%

1 2

R76 2K_0402_1%R76 2K_0402_1%

R77

1 2

2K_0402_1%

APU_DISP_CLK<7>

APU_DISP_CLK#<7>

APU_CLK<7> APU_CLK#<7>

Remove 0 ohm on PVT

1 2

R801 0_0402_5%

GCLK@

25M_X1

R89

R89 1M_0402_5%

1M_0402_5%

NOGCLK@

25M_X2

A_RST#

UMI_RXP0_C UMI_RXN0_C UMI_RXP1_C UMI_RXN1_C UMI_RXP2_C UMI_RXN2_C UMI_RXP3_C UMI_RXN3_C

PCIE_CALRP PCIE_CALRN

CLK_CALRN

25M_X1GCLK_PCH_25MHZ

25M_X2

B

R74/ C146 close to FCH

U1A

AE2

PCIE_RST#

AD5

A_RST#

AE30

UMI_TX0P

AE32

UMI_TX0N

AD33

UMI_TX1P

AD31

UMI_TX1N

AD28

UMI_TX2P

AD29

UMI_TX2N

AC30

UMI_TX3P

AC32

UMI_TX3N

AB33

UMI_RX0P

AB31

UMI_RX0N

AB28

UMI_RX1P

AB29

UMI_RX1N

Y33

UMI_RX2P

Y31

UMI_RX2N

Y28

UMI_RX3P

Y29

UMI_RX3N

AF29

PCIE_CALRP

AF31

PCIE_CALRN

V33

GPP_TX0P

V31

GPP_TX0N

W30

GPP_TX1P

W32

GPP_TX1N

AB26

GPP_TX2P

AB27

GPP_TX2N

AA24

GPP_TX3P

AA23

GPP_TX3N

AA27

GPP_RX0P

AA26

GPP_RX0N

W27

GPP_RX1P

V27

GPP_RX1N

V26

GPP_RX2P

W26

GPP_RX2N

W24

GPP_RX3P

W23

GPP_RX3N

F27

CLK_CALRN

G30

PCIE_RCLKP

G28

PCIE_RCLKN

R26

DISP_CLKP

T26

DISP_CLKN

H33

DISP2_CLKP

H31

DISP2_CLKN

T24

APU_CLKP

T23

APU_CLKN

J30

SLT_GFX_CLKP

K29

SLT_GFX_CLKN

H27

GPP_CLK0P

H28

GPP_CLK0N

J27

GPP_CLK1P

K26

GPP_CLK1N

F33

GPP_CLK2P

F31

GPP_CLK2N

E33

GPP_CLK3P

E31

GPP_CLK3N

M23

GPP_CLK4P

M24

GPP_CLK4N

M27

GPP_CLK5P

M26

GPP_CLK5N

N25

GPP_CLK6P

N26

GPP_CLK6N

R23

GPP_CLK7P

R24

GPP_CLK7N

N27

GPP_CLK8P

R27

GPP_CLK8N

J26

14M_25M_48M_OSC

C31

25M_X1

C33

25M_X2

21807-A13-HUDSON-M3_FCBGA656

SA000066K70

A76M Bolton M3

B

PCI EXPRESS INTERFACES

CLOCK GENERATOR

HUDSON-2

PCI CLKS

PCICLK4/14M_OSC/GPO39

PCI INTERFACE

REQ2#/CLK_REQ8#/GPIO41 REQ3#/CLK_REQ5#/GPIO42

GNT2#/SD_LED/GPO45

GNT3#/CLK_REQ7#/GPIO46

LPCAPUS5 PLUS

LDRQ1#/CLK_REQ6#/GPIO49

PCICLK0 PCICLK1/GPO36 PCICLK2/GPO37 PCICLK3/GPO38

PCIRST#

AD0/GPIO0 AD1/GPIO1 AD2/GPIO2 AD3/GPIO3 AD4/GPIO4 AD5/GPIO5 AD6/GPIO6 AD7/GPIO7 AD8/GPIO8

AD9/GPIO9 AD10/GPIO10 AD11/GPIO11 AD12/GPIO12 AD13/GPIO13 AD14/GPIO14 AD15/GPIO15 AD16/GPIO16 AD17/GPIO17 AD18/GPIO18 AD19/GPIO19 AD20/GPIO20 AD21/GPIO21 AD22/GPIO22 AD23/GPIO23 AD24/GPIO24 AD25/GPIO25 AD26/GPIO26 AD27/GPIO27 AD28/GPIO28 AD29/GPIO29 AD30/GPIO30 AD31/GPIO31

CBE0# CBE1# CBE2# CBE3#

FRAME#

DEVSEL#

IRDY#

TRDY#

PAR

STOP# PERR# SERR#

REQ0#

REQ1#/GPIO40

GNT0#

GNT1#/GPO44

CLKRUN#

LOCK#

INTE#/GPIO32

INTF#/GPIO33 INTG#/GPIO34 INTH#/GPIO35

LPCCLK0

LPCCLK1

LAD0 LAD1 LAD2 LAD3

LFRAME#

LDRQ0#

SERIRQ/GPIO48

DMA_ACTIVE#

PROCHOT#

APU_PG

LDT_STP#

APU_RST#

S5_CORE_EN

RTCCLK

INTRUDER_ALERT#

VDDBT_RTC_G

32K_X1

32K_X2

C

AF3

1 2

AF1 AF5

RF1 0_0402_1 %

AG2

1 2

AF6

1 2

RF2 0_0402_1 %

RF2 0_0402_1 % RF3 0_0402_1 %

RF3 0_0402_1 %

AB5

AJ3 AL5 AG4 AL6 AH3 AJ5 AL1 AN5 AN6 AJ1 AL8 AL3 AM7 AJ6 AK7 AN8 AG9 AM11 AJ10 AL12 AK11 AN12 AG12 AE12 AC12 AE13 AF13 AH13 AH14 AD15 AC15 AE16 AN3 AJ8 AN10 AD12 AG10 AK9 AL10 AF10 AE10 AH1 AM9 AH8 AG15 AG13 AF15 AM17 AD16 AD13 AD21 AK17 AD19 AH9

AF18 AE18 AC16 AD18

B25

D25 D27 C28 A26 A29 A31 B27 AE27 AE19

G25 E28

APU_PROCHOT#_R

E26

APU_PWRGD_R

G26 F26

H7 F1 F3 E6

G2

32K_X1

G4

32K_X2

SHORT PAD@

SHORT PAD@ SHORT PAD@

SHORT PAD@

PCI_AD23 <15> PCI_AD24 <15> PCI_AD25 <15> PCI_AD26 <15> PCI_AD27 <15>

SIT: For EMI Request

EMI@

1 2

R85 33_0402_5%

LPC_CLK1 <15> LPC_AD0 <36> LPC_AD1 <36> LPC_AD2 <36> LPC_AD3 <36> LPC_FRAME# <36>

SERIRQ <36>

1 2

R86 0_0402_5%DEBUG@R86 0_0402_5%DEBUG@

1 2

R73 0_0402_1%

RTC_CLK <15,36>

+RTCBATT_R

PCI_CLK1 <15>

PCI_CLK3 <15> PCI_CLK4 <15>

TEST POINT@

T26

TEST POINT@

T27

SVT: For EMI Request

EMI@

1 2

C163 10P_0402_50V8J

SHORT PAD@

1 2

C530100P_0402_50V8J

@ESD@

W=20mils

1

C158

2

1U_0402_6.3V6K

1 2

R88 510_0402_5%R88 510_0402_5%

Need OPEN

D

CLK_PCI_EC <15,36>

ALLOW_STOP <7> APU_PROCHOT# <7> APU_PWRGD <48,7>

APU_RST# <7>

+RTCBATT

12

CLRP1 SHORT PADS

SHORT PADS

for Clear CMOS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/11/13 2013/11/12

Compal Secret Data

Deciphered Date

D

GCLK@

32K_X1 GCLK_32K

32.768KHZ_12.5PF_CM31532768DZFT

DEBUG@CLRP1

DEBUG@

1 2

R207 0_0402_5%

32K_X1

32K_X2

Close to HUDSON-M2/3

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

FCH PCIE/CLK/PCI/LPC/RTC

12

Y1

NOGCLK@

E

DVT change

C155

12

20P_0402_50V8J

20M_0402_5%

NOGCLK@

C156

20P_0402_50V8J

VALGD MB L

E

GCLK_32K <38>

NOGCLK@

R78

NOGCLK@

11 57Friday, April 12, 2013

0.1

A

1 1

HDD

ODD

2 2

+AVDD_SATA

+3VS

3 3

+3VS

R36 10K_0402_5%R 36 10K_0402_5%

#11/7 without pull up/ down need to confirm o

r check chipset pin internal status

4 4

A

12

SATA_ITX_C_DRX_P0<34> SATA_ITX_C_DRX_N0<34>

SATA_DTX_C_IRX_N0<34> SATA_DTX_C_IRX_P0<34>

SATA_ITX_C_DRX_P1<34> SATA_ITX_C_DRX_N1<34>

SATA_DTX_C_IRX_N1<34> SATA_DTX_C_IRX_P1<34>

12

R1051K_0402_1% R1051K_0402_1%

12

R106931_0402_1% R106931_0402_1%

1 2

R108 10K_0402_5%R108 10K_0402_5%

BT_DISABLE#

BT_DISABLE#<30>

WL_OFF#<30>

ODD_EN<34>

RP4

18 27

GPIO177

36 45

10K_0804_8P4R_5%

B

SATA_CALRP

SATA_CALRN

TEST POINT@

T12

BT_DISABLE# WL_OFF#

ODD_EN

GPIO174

B

U1B

AK19

SATA_TX0P

AM19

SATA_TX0N

AL20

SATA_RX0N

AN20

SATA_RX0P

AN22

SATA_TX1P

AL22

SATA_TX1N

AH20

SATA_RX1N

AJ20

SATA_RX1P

AJ22

SATA_TX2P

AH22

SATA_TX2N

AM23

SATA_RX2N

AK23

SATA_RX2P

AH24

SATA_TX3P

AJ24

SATA_TX3N

AN24

SATA_RX3N

AL24

SATA_RX3P

AL26

SATA_TX4P

AN26

SATA_TX4N

AJ26

SATA_RX4N

AH26

SATA_RX4P

AN29

SATA_TX5P

AL28

SATA_TX5N

AK27

SATA_RX5N

AM27

SATA_RX5P

AL29

NC6

AN31

NC7

AL31

NC8

AL33

NC9

AH33

NC10

AH31

NC11

AJ33

NC12

AJ31

NC13

AF28

SATA_CALRP

AF27

SATA_CALRN

AD22

SATA_ACT#/GPIO67

AF21

SATA_X1

AG21

SATA_X2

AH16

FANOUT0/GPIO52

AM15

FANOUT1/GPIO53

AJ16

FANOUT2/GPIO54

AK15

FANIN0/GPIO56

AN16

FANIN1/GPIO57

AL16

FANIN2/GPIO58

K6

TEMPIN0/GPIO171

K5

TEMPIN1/GPIO172

K3

TEMPIN2/GPIO173

M6

TEMPIN3/TALERT#/GPIO174

21807-A13-HUDSON-M3_FCBGA656

SA000066K70

A76M Bolton M3

HUDSON-2

SERIAL ATA

HW MONITOR

C

Share with EC need pop R245

GBE_COL

GBE_CRS

GBE_MDCK

GBE_MDIO

GBE_RXCLK

GBE_RXD3 GBE_RXD2 GBE_RXD1 GBE_RXD0

GBE_RXERR

GBE_TXCLK

GBE_TXD3 GBE_TXD2 GBE_TXD1 GBE_TXD0

VGA_RED

VGA_GREEN

VGA_BLUE

AUXCAL

NC1 NC2 NC3 NC4 NC5

C

AL14 AN14 AJ12 AH12 AK13 AM13 AH15 AJ14

AC4 AD3 AD9 W10 AB8 AH7 AF7 AE7 AD7 AG8 AD1 AB7 AF9 AG6 AE8 AD8 AB9 AC2 AA7 W9

V6 V5 V3

SPI_CLK_FCH_R

T6 V1

L30

L32

M29

M28 N30

M33 N32

K31

V28 V29

U28

AUXCAL

T31 T33 T29 T28 R32 R30 P29 P28

C29

N2

M3

L2

N4

P1

P3

M1

M5

AG16 AH10 A28 G27 L4

2012/11/13 2013/11/12

SPI_SB_CS0#_R SPI_SO_R

GBE_PHY_INTR

SPI_SO_R SPI_SI_R

SPI_SB_CS0#_R

SPI_WP#

1 2

R107 715_0402_1%R107 715_0402_1%

1 2

R109 100_0402_1%R109 100_0402_1%

GPIO177

1 2

R118 10K_0402_5%

GPIO182

Compal Secret Data

SHORT PAD@

1 2

R97 0_0402_1%

1 2

R98 0_0402_1%

SHORT PAD@

CRT_HSYNC <28> CRT_VSYNC <28>

CRT_DDC_DATA <28> CRT_DDC_CLK <28>

ML_VGA_AUXP_C <7> ML_VGA_AUXN_C <7>

ML_VGA_TXP0 <7> ML_VGA_TXN0 <7> ML_VGA_TXP1 <7> ML_VGA_TXN1 <7> ML_VGA_TXP2 <7> ML_VGA_TXN2 <7> ML_VGA_TXP3 <7> ML_VGA_TXN3 <7>

FCH_CRT_HPD <7>

DEBUG@

Need to enable i nternal pull down to lea ve unconnected

Deciphered Date

SD_CLK/SCLK_2/GPIO73

SD_CMD/SLOAD_2/GPIO74

SD_CD/GPIO75

SD_WP/GPIO76

SD_DATA0/SDATI_2/GPIO77

SD_DATA1/SDATO_2/GPIO78

SD CARDGBE LANSPI ROMVGA DACVGA MAINLINK

SD_DATA2/GPIO79 SD_DATA3/GPIO80

GBE_RXCTL/RXDV

GBE_TXCTL/TXEN

GBE_PHY_PD

GBE_PHY_RST#

GBE_PHY_INTR

SPI_DI/GPIO164

SPI_DO/GPIO163

SPI_CLK/GPIO162

SPI_CS1#/GPIO165

ROM_RST#/SPI_WP#/GPIO161

VGA_HSYNC/GPO68 VGA_VSYNC/GPO69

VGA_DDC_SDA/GPO70 VGA_DDC_SCL/GPO71

VGA_DAC_RSET

AUX_VGA_CH_P AUX_VGA_CH_N

ML_VGA_L0P

ML_VGA_L0N

ML_VGA_L1P

ML_VGA_L1N

ML_VGA_L2P

ML_VGA_L2N

ML_VGA_L3P

ML_VGA_L3N

ML_VGA_HPD/GPIO229

VIN0/GPIO175

VIN1/GPIO176

VIN2/SDATI_1/GPIO177

VIN3/SDATO_1/GPIO178

VIN4/SLOAD_1/GPIO179

VIN5/SCLK_1/GPIO180

VIN6/GBE_STAT3/GPIO181

VIN7/GBE_LED3/GPIO182

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

D

+3VALW

RP5

18

SPI_WP#

27

SPI_HOLD#

36 45

10K_0804_8P4R_5%

1 2

R245

SPI_SB_CS0# SPI_SO_L

SPI_WP#

SPI_SO_L

SPI_SI

SPI_CLK_FCH

SPI_SB_CS0#

GBE_PHY_INTR

SPI_SB_CS0#

10K_0402_5%ShareROM@

U3

1

/CS

2

DO/IO1

3

/WP/IO2

4

GND

W25Q32FVSSIQ_SO8

R125 0_0402_5%

R128 0_0402_5%

R233 0_0402_5%

R238 0_0402_5%

Co-lay EC share ROM

DAC_RED <28 >

DAC_GRN < 28>

DAC_BLU <28>

+VDDAN_11_ML

Module design FCH_CRT_HPD pull up 110K now 10 K

+FCH_VDDAN_33_DAC

12

R11010K_0402_5% R11010K_0402_5%

10K_0804_8P4R_5%

45 36 27

GPIO174

GPIO182

D

18

RP6

RP6 RP8

RP8

18 27 36 45

10K_0804_8P4R_5%

E

4MB SPI ROM

+3VALW

C165

1 2

0.1U_0402_16V4Z

8

VCC

7

/HOLD/IO3

ShareROM@

1 2

ShareROM@

1 2

ShareROM@

1 2

ShareROM@

1 2

ax = 800 mils

M

Title

Size Document Number Rev

Custom

Date: Sheet of

SPI_HOLD#

6

SPI_CLK_FCH

CLK

5

SPI_SI

DI/IO0

FRD#SPI_SO

FWR#SPI_SI

SPI_CLK

FSEL#SPICS#

DAC_RED DAC_GRN DAC_BLU

Compal Electronics, Inc.

FCH SATA/SPI/VGA/HWM/SD

EMI@

1 2

R100 0_0402_5%

1 2

SHORT PAD@

RP23

1 8 2 7 3 6 4 5

150_0804_8P4R_1%

VALGD MB L

22P_0402_50V8J

0_0402_1%

R99

FRD#SPI_SO <36>

FWR#SPI_SI <36>

SPI_CLK <36>

FSEL#SPICS# <36>

E

SPI_CLK_FCH_R

12 57Friday, April 12, 2013

SPI_CLK_FCH

R94

33_0402_5%

@EMI@

SPI_SI_R

C162

12

0.1

A

+3VALW

R127

R127 10K_0402_5%

10K_0402_5%

DEBUG@

1 2

1 1

SVT: For ESD requirement

+3VALW

2 2

+3VALW

R146 10K_0402_5%

R147 100K_0402_5%

3 3

R148 10K_0402_5%

+3VS

R154 2.2K_0402_5%R154 2.2K_0402_5%

R156 2.2K_0402_5%R156 2.2K_0402_5% R158 8.2K_0402_5%R158 8.2K_0402_5% R159 8.2K_0402_5%R159 8.2K_0402_5%

4 4

R164 2.2K_0402_5%R164 2.2K_0402_5%

R165 10K_0402_5%

R168 10K_0402_5%

R169 10K_0402_5%

SYS_RESET#

H_THERMTRIP#

1

C439

ESD@

1000P_0402_50V7K

2

For FCH internal debug use

1 2

R129 2.2K_0402_5%

DEBUG@

1 2

R130 2.2K_0402_5%

DEBUG@

1 2

R131 2.2K_0402_5%

DEBUG@

+3VALW

RP14

18

USB_OC0#

27

USB_OC1#

36

ODD_DETECT#

45

10K_0804_8P4R_5%

1 2

DEBUG@

1 2

DEBUG@

1 2

DEBUG@

1 2

1 2 1 2 1 2

RP10

10K_0804_8P4R_5%

1 2

DEBUG@

1 2

DEBUG@

1 2

DEBUG@

ODD_DA#_FCH

FCH_PCIE_WAKE#

#9/11 need to confirm, Intel using EC

CLKREQ_WLAN#

18 27 36 45

PEG_CLKREQ#_R

A

TEST0

TEST1

TEST2

Module design ODD_DETECT# without pull up need check chipset pin internal status

HDA_BITCLK_AUDIO<35> HDA_SDOUT_AUDIO<35>

HDA_SDIN0<35>

HDA_SYNC_AUDIO<35>

HDA_RST_AUDIO#<35>

H_THERMTRIP#

EC_LID_OUT#

GPIO187 H: 2G Vram L: 1G Vram

FCH_SCLK0

FCH_SDATA0

CLKREQ_LAN#

WD_PWRGD

FCH_SCLK1 FCH_SDATA1 GPIO188

EC_RSMRST#

HDA_BITCLK

HDA_SDIN0

+3VALW+3VALW

12

@

R160

10K_0402_5%

12

PX@

R166

10K_0402_5%

CLK_REQ_VGA#<17>

For RIGHT USB2.0 Port

For LEFT USB3.0 Port

+3VALW

PXS_RST#<16>

PXS_PWREN<18,36,45,51,52>

VGA_GATE#<36>

R161

GPIO189 GPIO190

R167

B

PCIE_RST2 : Reset PCIE device on Hudson2/3

EC_LID_OUT#<36>

PM_SLP_S3#<36> PM_SLP_S5#<36> PBTN_OUT#<36> FCH_PWRGD<36,48>

GATEA20<36>

KBRST#<36> EC_SCI#< 36> EC_SMI#<36>

FCH_PCIE_WAKE#<30>

H_THERMTRIP#<7>

EC_RSMRST#<36>

CLKREQ_LAN#<31>

HDA_SPKR<35> FCH_SCLK0<10,30,9> FCH_SDATA0<10,30,9>

CLKREQ_WLAN#< 30>

VGA_PWRGD<50>

R132 0_0402_5%@R132 0_0402_5%@

R138 33_0402_5%EM I@R138 33_0402_5%EMI@ R140 33_0402_5%R 140 33_0402_5%

R143 33_0402_5%R 143 33_0402_5% R144 33_0402_5%R 144 33_0402_5%

1 2

R364 10K_0402_5%X76@R364 10K_0402_5%X76@

1 2

R365 10K_0402_5%X76@R365 10K_0402_5%X76@

1 2

R366 10K_0402_5%

2

G

BOARD Config.

12

ODD_DETECT#<34>

USB_OC1#<37> USB_OC0#<39>

1 2 1 2

@

SHORT PAD@

PX@

Q70

2N7002K_SOT23-3

12 12

R150 0_0402_5%

R150 0_0402_5% R152 0_0402_5%

R152 0_0402_5%

13

D

S

GPIO189 GPIO190

0 0

1 1

B

FCH_PWRGD

TEST0 TEST1 TEST2

SYS_RESET#

WD_PWRGD

CLKREQ_LAN#

FCH_SCLK0 FCH_SDATA0 FCH_SCLK1 FCH_SDATA1 CLKREQ_WLAN#

PEG_CLKREQ#_R

USB_OC1# USB_OC0#

HDA_BITCLK HDA_SDOUT HDA_SDIN0

HDA_SYNC HDA_RST#

10

01

T13TEST POINT@T13TEST POINT@

GPIO187 GPIO188

GPIO189 GPIO190

Function

PX5

Reserved

DIS

UMA

C

U1D

HUDSON-2

AB6

PCIE_RST2#/PCI_PME#/GEVENT4#

R2

RI#/GEVENT22#

W7

SPI_CS3#/GBE_STAT1/GEVENT21#

T3

SLP_S3#

W2

SLP_S5#

J4

PWR_BTN#

N7

PWR_GOOD

T9

TEST0

T10

TEST1/TMS

V9

TEST2

AE22

GA20IN/GEVENT0#

AG19

KBRST#/GEVENT1#

R9

LPC_PME#/GEVENT3#

C26

LPC_SMI#/GEVENT23#

T5

LPC_PD#/GEVENT5#

U4

SYS_RESET#/GEVENT19#

K1

WAKE#/GEVENT8#

V7

IR_RX1/GEVENT20#

R10

THRMTRIP#/SMBALERT#/GEVEN T2#

AF19

WD_PWRGD

U2

RSMRST#

AG24

CLK_REQ4#/SATA_IS0#/GPIO64

AE24

CLK_REQ3#/SATA_IS1#/GPIO63

AE26

SMARTVOLT1/SATA_IS2#/GPIO50

AF22

CLK_REQ0#/SATA_IS3#/GPIO60

AH17

SATA_IS4#/FANOUT3/GPIO55

AG18

SATA_IS5#/FANIN3/GPIO59

AF24

SPKR/GPIO66

AD26

SCL0/GPIO43

AD25

SDA0/GPIO47

T7

SCL1/GPIO227

R7

SDA1/GPIO228

AG25

CLK_REQ2#/FANIN4/GPIO62

AG22

CLK_REQ1#/FANOUT4/GPIO61

J2

IR_LED#/LLB#/GPIO184

AG26

SMARTVOLT2/SHUTDOWN #/GPIO51

V8

DDR3_RST#/GEVENT7#/VGA_PD

W8

GBE_LED0/GPIO183

Y6

SPI_HOLD#/GBE_LED1/GEVENT9#

V10

GBE_LED2/GEVENT10#

AA8

GBE_STAT0/GEVENT11#

AF25

CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#

M7

BLINK/USB_OC7#/GEVENT18#

R8

USB_OC6#/IR_TX1/GEVENT6#

T1

USB_OC5#/IR_TX0/GEVENT17#

P6

USB_OC4#/IR_RX0/GEVENT16#

F5

USB_OC3#/AC_PRES/TDO/GEVENT15#

P5

USB_OC2#/TCK/GEVENT14#

J7

USB_OC1#/TDI/GEVENT13#

T8

USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT1 2#

AB3

AZ_BITCLK

AB1

AZ_SDOUT

AA2

AZ_SDIN0/GPIO167

Y5

AZ_SDIN1/GPIO168

Y3

AZ_SDIN2/GPIO169

Y1

AZ_SDIN3/GPIO170

AD6

AZ_SYNC

AE4

AZ_RST#

K19

PS2_DAT/SDA4/GPIO187

J19

PS2_CLK/CEC/SCL4/GPIO188

J21

SPI_CS2#/GBE_STAT2/GPIO166

D21

PS2KB_DAT/GPIO189

C20

PS2KB_CLK/GPIO190

D23

PS2M_DAT/GPIO191

C22

PS2M_CLK/GPIO192

F21

KSO_0/GPIO209

E20

KSO_1/GPIO210

F20

KSO_2/GPIO211

A22

KSO_3/GPIO212

E18

KSO_4/GPIO213

A20

KSO_5/GPIO214

J18

KSO_6/GPIO215

H18

KSO_7/GPIO216

G18

KSO_8/GPIO217

B21

KSO_9/GPIO218

K18

KSO_10/GPIO219

D19

KSO_11/GPIO220

A18

KSO_12/GPIO221

C18

KSO_13/GPIO222

B19

KSO_14/GPIO223

B17

KSO_15/GPIO224

A24

KSO_16/GPIO225

D17

KSO_17/GPIO226

21807-A13-HUDSON-M3_FCBGA656

A76M Bolton M3

SA000066K70

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

HUDSON-2

EMBEDDED CTRL

2012/11/13 2013/11/12

USBCLK/14M_25M_48M_OSC

USB MISCUSB 1.1USB 2.0USB 3.0

USB_FSD1P/GPIO186

USB_FSD0P/GPIO185

USB OC GPIO ACPI / WAKE UP EVENTSHD AUDIO

SCL3_LV/GPIO195

SDA3_LV/GPIO196 EC_PWM0/EC_TIMER 0/GPIO197 EC_PWM1/EC_TIMER 1/GPIO198

EC_PWM2/EC_TIMER 2/WOL_EN/GPIO199

EC_PWM3/EC_TIMER 3/GPIO200

Compal Secret Data

Deciphered Date

USB_RCOMP

USB_FSD1N

USB_FSD0N

USB_HSD13P USB_HSD13N

USB_HSD12P USB_HSD12N

USB_HSD11P USB_HSD11N

USB_HSD10P USB_HSD10N

USB_HSD9P USB_HSD9N

USB_HSD8P USB_HSD8N

USB_HSD7P USB_HSD7N

USB_HSD6P USB_HSD6N

USB_HSD5P USB_HSD5N

USB_HSD4P USB_HSD4N

USB_HSD3P USB_HSD3N

USB_HSD2P USB_HSD2N

USB_HSD1P USB_HSD1N

USB_HSD0P USB_HSD0N

USBSS_CALRP

USBSS_CALRN

USB_SS_TX3P USB_SS_TX3N

USB_SS_RX3P USB_SS_RX3N

USB_SS_TX2P USB_SS_TX2N

USB_SS_RX2P USB_SS_RX2N

USB_SS_TX1P USB_SS_TX1N

USB_SS_RX1P USB_SS_RX1N

USB_SS_TX0P USB_SS_TX0N

USB_SS_RX0P USB_SS_RX0N

SCL2/GPIO193

SDA2/GPIO194

KSI_0/GPIO201 KSI_1/GPIO202 KSI_2/GPIO203 KSI_3/GPIO204 KSI_4/GPIO205 KSI_5/GPIO206 KSI_6/GPIO207 KSI_7/GPIO208

D

G8

B9

USB_RCOMP

H1 H3

H6 H5

H10 G10

K10 J12

G12 F12

K12 K13

B11 D11

E10 F10

C10 A10

H9 G9

A8 C8

F8 E8

C6 A6

C5 A5

C1 C3

E1 E3

C16

USBSS_CALRP

A16

USBSS_CALRN

A14 C14

C12 A12

D15 B15

E14 F14

F15

USB3_TX1_P

G15

USB3_TX1_N

H13

USB3_RX1_P

G13

USB3_RX1_N

J16

USB3_TX0_P

H16

USB3_TX0_N

J15

USB3_RX0_P

K15

USB3_RX0_N

H19 G19 G22 G21 E22 H22 J22 H21

K21 K22 F22 F24 E24 B23 C24 F18

D

EC_PWM2

GPU_SEL

10K_0804_8P4R_5%

E

1 2

R122 11.8K_0402_1%R122 11.8K_0402_1%

USB20_P11 <39> USB20_N11 <39>

USB20_P10 <39> USB20_N10 <39>

USB20_P6 <37> USB20_N6 <37>

USB20_P4 <39> USB20_N4 <39>

USB20_P3 <27> USB20_N3 <27>

USB20_P2 <30> USB20_N2 <30>

USB20_P0 <37> USB20_N0 <37>ODD_DA#_FCH<34>

1 2

R133 1K_0402_1%R133 1K_0402_1%

1 2

R134 1K_0402_1%R134 1K_0402_1%

RP7

18 27 36 45

EC_PWM2 <15>

Title

Size Document Number Rev

Custom

Date: Sheet of

Card Reader

Touch Screen

+FCH_VDD_11_SSUSB_S

USB3_TX1_P <39> USB3_TX1_N <39>

USB3_RX1_P <39> USB3_RX1_N <39>

USB3_TX0_P <39> USB3_TX0_N <39>

USB3_RX0_P <39> USB3_RX0_N <39>

strap pin

Compal Electronics, Inc.

FCH-ACPI/USB/HDA/GPIO

VALGD MB L

CMOS

WLAN

RP1

100K_0402_5%

GPU_SEL

10K_0402_5%

E

LP2

LP1

+3VALW

PX@

R234

@

R235

13 57Friday, April 12, 2013

LP2

LP1

12

Root

Mars

0.1

A

B

C

D

E

+3VS

+FCH_VDDAN_33_DAC

1 1

+3VS +FCH_VDDAN_33_DAC

2 2

3/1 SIT downsize to 0402, BLM15AX221SN1D (Murata)

3 3

4 4

SHORT PAD@

1 2

L2 0_0603_5%

+VDDPL_33_SYS

220 ohm

SHORT PAD@

1 2

R172 0_0402_5%

1 2

FBMA-L11-201209-221LMA30T_0805

220 ohm

+3VALW

BLM15AX221SN1D 0402

+VDDAN_33_USB

BLM15AX221SN1D 0402

+3VS

1 2

L13 0_0603_5%

SHORT PAD@

+3VS

SHORT PAD@

1 2

L14 0_0603_5%

L4

L6

SM01000MK00

220 ohm

L77

SM01000MK00

220 ohm

+VDDPL_33_MLDAC

30mil

+VDDPL_33_PCIE

220 ohm

+VDDPL_33_SATA

A

C166

2.2U_0402_6.3V6M

C166

2.2U_0402_6.3V6M

1

2

0.1U_0402_16V7K

C175

1

2

C196

C195

2.2U_0603_6.3V6K

C195

2.2U_0603_6.3V6K

1

2

+VDDPL_33_SSUSB_S

C205

2.2U_0402_6.3V6M

C205

2.2U_0402_6.3V6M

1

2

+VDDPL_33_USB_S

C213

2.2U_0402_6.3V6M

C213

2.2U_0402_6.3V6M

1

2

220 ohm

C167

0.1U_0402_16V7K

C167

0.1U_0402_16V7K

1

2

0.1U_0402_16V7K

C176

1

2

LDO_CAP: Internally generated 1.8V

upply for the RGB outputs

s

+1.1VS

+3VS

+VDDPL_33_MLDAC

BLM15AX221SN1D 0402

L3

SM01000MK00

1 2

220 ohm/2A

3/1 SIT downsize to 0402, BLM15AX221SN1D (Murata)

0.1U_0402_16V4Z

1

2

+3VALW

FBMA-L11-201209-221LMA30T_0805

C206

0.1U_0402_16V7K

C206

0.1U_0402_16V7K

1

3/1 SIT downsize to 0402, BLM15AX221SN1D (Murata)

2

C214

0.1U_0402_16V7K

C214

0.1U_0402_16V7K

1

2

C220

2.2U_0402_6.3V6M

C220

2.2U_0402_6.3V6M

1

2

C227

2.2U_0402_6.3V6M

C227

2.2U_0402_6.3V6M

1

2

+1.1VALW

3/1 SIT downsize to 0402, BLM15AX221SN1D (Murata)

+1.1VALW

FBMA-L11-201209-221LMA30T_0805

L5

1 2

220 ohm/2A

L9

BLM15AX221SN1D 0402

SM01000MK00

220 ohm

L11

BLM15AX221SN1D 0402

SM01000MK00

220 ohm

+FCH_VDD_11_SSUSB_S

40mils

12

L78

42 ohm/4A

R171

0_0603_5%

SHORT PAD@

+VDDPL_33_SYS

1 2

R173 0_0402_5%

1 2

R174 0_0402_5%

SHORT PAD@

+VDDPL_33_USB_S

+VDDPL_33_PCIE

+VDDPL_33_SATA

SHORT PAD@

1 2

R178 0_0402_5%

1 2

R179 0_0603_5%

SHORT PAD@

R182 0_0402_5%

C200

1

2

C208

1

2

C215

1

2

SHORT PAD@

1 2

R185 0_0603_5%

R187 0_0603_5%

1 2

SHORT PAD@

B

C171

1

2

10U_0603_6.3V6M

2.2U_0402_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6M

C172

1

2

C188

1

2

1 2

SHORT PAD@

10U_0603_6.3V6M

C201

1

2

C209

0.1U_0402_16V7K

C209

0.1U_0402_16V7K

1

2

C216

0.1U_0402_16V7K

C216

0.1U_0402_16V7K

1

2

C221

1

2

C228

1

2

+VDDIO_33_PCIGP

0.1U_0402_16V7K

C173

C174

1

2

+VDDPL_33_SYS

+VDDPL_33_DAC

+VDDPL_33_ML

+FCH_VDDAN_33_DAC

+VDDPL_33_SSUSB_S

DEBUG@

1 2

C184 2.2U_0603_6.3V6K

+VDDPL_11_DAC

+VDDAN_11_ML

C189

0.1U_0402_16V7K

C189

0.1U_0402_16V7K

4.7U_0402_6.3V6M

C190

0.1U_0402_16V7K

C190

0.1U_0402_16V7K

1

2

+VDDAN_33_USB

C202

1

2

+VDDAN_11_USB_S

+VDDCR_11V_USB

C217

1

2

+VDDAN_11_SSUSB

1U_0402_6.3V6K

+VDDCR_11_SSUSB

10U_0603_6.3V6M

C204

C203

1U_0402_6.3V6K

C203

1U_0402_6.3V6K

0.1U_0402_16V7K

1

2

C223

0.1U_0402_16V7K

C223

0.1U_0402_16V7K

C222

0.1U_0402_16V7K

C222

0.1U_0402_16V7K

1

2

C230

C229

1U_0402_6.3V6K

C229

1U_0402_6.3V6K

1

2

U1C

HUDSON-2

102mA

AB17

VDDIO_33_PCIGP_1

AB18

VDDIO_33_PCIGP_2

AE9

VDDIO_33_PCIGP_3

AD10

VDDIO_33_PCIGP_4

AG7

VDDIO_33_PCIGP_5

AC13

VDDIO_33_PCIGP_6

AB12

VDDIO_33_PCIGP_7

AB13

VDDIO_33_PCIGP_8

AB14

VDDIO_33_PCIGP_9

AB16

VDDIO_33_PCIGP_10

47mA

H24

VDDPL_33_SYS

20mA

V22

VDDPL_33_DAC

12mA

U22

VDDPL_33_ML

3

0mA

T22

VDDAN_33_DAC

11mA

L18

VDDPL_33_SSUSB_S

14mA

D7

VDDPL_33_USB_S

11mA

AH29

VDDPL_33_PCIE

12mA

AG28

VDDPL_33_SATA

M31

LDO_CAP

7mA

V21

VDDPL_11_DAC

226mA

Y22

VDDAN_11_ML_1

V23

VDDAN_11_ML_2

V24

VDDAN_11_ML_3

V25

VDDAN_11_ML_4

AB10

VDDIO_33_GBE_S

AB11

VDDCR_11_GBE_S_1

AA11

VDDCR_11_GBE_S_2

AA9

VDDIO_GBE_S_1

AA10

VDDIO_GBE_S_2

470mA

G7

VDDAN_33_USB_S_1

H8

0.1U_0402_16V7K

VDDAN_33_USB_S_2

J8

VDDAN_33_USB_S_3

K8

VDDAN_33_USB_S_4

K9

VDDAN_33_USB_S_5

M9

VDDAN_33_USB_S_6

M10

VDDAN_33_USB_S_7

N9

VDDAN_33_USB_S_8

N10

VDDAN_33_USB_S_9

M12

VDDAN_33_USB_S_10

N12

VDDAN_33_USB_S_11

M11

VDDAN_33_USB_S_12

140mA

U12

VDDAN_11_USB_S_1

U13

VDDAN_11_USB_S_2

42mA

T12

VDDCR_11_USB_S_1

T13

VDDCR_11_USB_S_2

282mA

P16

VDDAN_11_SSUSB_S_1

M14

VDDAN_11_SSUSB_S_2

N14

VDDAN_11_SSUSB_S_3

P13

VDDAN_11_SSUSB_S_4

P14

VDDAN_11_SSUSB_S_5

424mA

N16

VDDCR_11_SSUSB_S_1

N17

VDDCR_11_SSUSB_S_2

P17

VDDCR_11_SSUSB_S_3

M17

VDDCR_11_SSUSB_S_4

21807-A13-HUDSON-M3_FCBGA656

0.1U_0402_16V7K

C231

0.1U_0402_16V7K

C231

0.1U_0402_16V7K

A76M Bolton M3

SA000066K70

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

HUDSON-2

PCI/GPIO I/O

USB SS USB MAIN LINKGBE LAN

POWER

C

VDDCR_11_1 VDDCR_11_2 VDDCR_11_3 VDDCR_11_4 VDDCR_11_5 VDDCR_11_6 VDDCR_11_7 VDDCR_11_8

CORE S0

VDDCR_11_9

VDDAN_11_CLK_1 VDDAN_11_CLK_2 VDDAN_11_CLK_3 VDDAN_11_CLK_4 VDDAN_11_CLK_5 VDDAN_11_CLK_6

CLKGEN I/OPCI EXPRESSSERIAL ATA3.3V_S5 I/O

VDDAN_11_CLK_7 VDDAN_11_CLK_8

VDDAN_11_PCIE_1 VDDAN_11_PCIE_2 VDDAN_11_PCIE_3 VDDAN_11_PCIE_4 VDDAN_11_PCIE_5 VDDAN_11_PCIE_6 VDDAN_11_PCIE_7 VDDAN_11_PCIE_8

VDDAN_11_SATA_1 VDDAN_11_SATA_4 VDDAN_11_SATA_2 VDDAN_11_SATA_3 VDDAN_11_SATA_5 VDDAN_11_SATA_6 VDDAN_11_SATA_7 VDDAN_11_SATA_8 VDDAN_11_SATA_9

VDDAN_11_SATA_10

VDDIO_33_S_1 VDDIO_33_S_2 VDDIO_33_S_3 VDDIO_33_S_4 VDDIO_33_S_5 VDDIO_33_S_6 VDDIO_33_S_7 VDDIO_33_S_8

VDDXL_33_S

VDDCR_11_S_1 VDDCR_11_S_2

VDDPL_11_SYS_S

VDDAN_33_HWM _S

VDDIO_AZ_S

2012/11/13 2013/11/12

1007mA

C179

T14 T17

1

T20 U16 U18

2

V14 V17 V20 Y17

340mA

H26 J25

C181

K24 L22

1

M22 N21 N22

2

P22

1088mA

AB24 Y21 AE25

C185

AD24 AB23

1

AA22 AF26 AG27

2

1337mA

AA21 Y20 AB21

C191

AB22 AC22

1

AC21 AA20 AA18

2

AB20 AC19

59mA

N18 L19

C197

M18 V12

1

V13 Y12 Y13

2

W11

5mA

G24

C207

1

2

187mA

N20 M20

C211

1

2

70mA

J24

C218

1

2

12mA

M8

C224

1

@

2

26mA

AA4

Compal Secret Data

Deciphered Date

+VCC_VDDCR_11

C168

0.1U_0402_16V7K

C168

0.1U_0402_16V7K

C180

0.1U_0402_16V7K

1

2

+1.1VS_CKVDD

C183

C182

0.1U_0402_16V7K

C182

0.1U_0402_16V7K

1U_0402_6.3V6K

2.2U_0402_6.3V6M

1U_0402_6.3V6K

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M@C224

2.2U_0402_6.3V6M

1

2

+VDDAN_11_PCIE

C187

C186

1U_0402_6.3V6K

C186

1U_0402_6.3V6K

1

2

C193

C192

1U_0402_6.3V6K

C192

1U_0402_6.3V6K

1

2

+VDDIO_33_S

C199

C198

1U_0402_6.3V6K

C198

1U_0402_6.3V6K

1

2

+VDDXL_3.3V

+VDDCR_1.1V

C212

1U_0402_6.3V6K

C212

1U_0402_6.3V6K

1

2

+VDDPL_11_SYS_S

0.1U_0402_16V7K

C219

1

2

+VDDAN_33_HWM

C225

0.1U_0402_16V7K@C225

0.1U_0402_16V7K

1

@

2

+VDDIO_AZ

C226 2.2U_0402_6.3V6MC226 2.2U_0402_6.3V6M

D

C169

1U_0402_6.3V6K

C177

1U_0402_6.3V6K

+VDDAN_11_PCIE

22U_0603_6.3V6M

C194

1U_0402_6.3V6K

2.2U_0402_6.3V6M

1 2

R170 0_0805_5%R170 0_0805_5%

1U_0402_6.3V6K

C170

10U_0603_6.3V6M

C170

10U_0603_6.3V6M

1

2

+1.1VS_CKVDD

1U_0402_6.3V6K

1

2

+AVDD_SATA

22U_0603_6.3V6M

1

2

R181 0_0402_5%

1 2

L7 0_0603_5%

SHORT PAD@

R183 0_0603_5%

SHORT PAD@

1 2

L12 0_0603_5%

C178

22U_0603_6.3V6M

C178

22U_0603_6.3V6M

1

2

1 2

SHORT PAD@

1 2

SHORT PAD@

42ohm @ 100MHz

1 2

R176 0_0603_5%

SHORT PAD@

42ohm @ 100MHz

112

JUMP_43X39

J14

42ohm @ 100MHz

112

JUMP_43X39

J15

220 ohm

1 2

R184 0_0402_5%

SHORT PAD@

SHORT PAD@ 1 2

R186 0_0402_5%

+1.1VS

2

JUMP@J14

JUMP@

+1.1VS

2

JUMP@J15

JUMP@

+3VALW

+VDDXL_3.3V Tie to +3.3V_S 5 rail if USB3 Wake is supported; otherwise, tie to +3.3V_S0 rail. Hudson-2 desig ns: Tie to +3.3 V_S0 rail.

+1.1VALW

+3VALW

AMD reply: VDDAN_33_HWM_S: Please connect it to +3.3V_S5 directly if HWM is not used.

+3VS

VDDIO_AZ_S should be tied to +3.3/1.5V_S5 rail if Wake on Ring is supported

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

FCH PWR

VALGD MB L

14 57Friday, April 12, 2013

E

of

0.1

A

B

C

D

E

1 1

2 2

3 3

U1E

HUDSON-2

A33

B13

D13

E12 E16 E29

F11 F13 F16 F17 F19 F23 F25 F29

G16 G32 H12 H15 H29

K16 K27 K28

M13 M16 M21 M25

N11 N13 N23 N24 P12 P18 P20 P21 P31 P33

R11 R25 R28 T11 T16 T18

K25

H25

A3

B7

D9

E5

F7 F9

G6

J6

J9 J10 J13 J28 J32

K7

L6 L12 L13 L15 L16 L21

N6

R4

N8

HUDSON-2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSAN_HWM

VSSXL

VSSPL_SYS

21807-A13-HUDSON-M3_FCBGA656

A76M Bolton M3

SA000066K70

GROUND

VSSPL_DAC VSSAN_DAC

VSSANQ_DAC

VSSIO_DAC

EFUSE

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

T25 T27 U6 U14 U17 U20 U21 U30 U32 V11 V16 V18 W4 W6 W25 W28 Y14 Y16 Y18 AA6 AA12 AA13 AA14 AA16 AA17 AA25 AA28 AA30 AA32 AB25 AC6 AC18 AC28 AD27 AE6 AE15 AE21 AE28 AF8 AF12 AF16 AF33 AG30 AG32 AH5 AH11 AH18 AH19 AH21 AH23 AH25 AH27 AJ18 AJ28 AJ29 AK21 AK25 AL18 AM21 AM25 AN1 AN18 AN28 AN33

T21 L28 K33 N28

R6

STRAP PINS

PCI_CLK1

ALLOW

PULL

PCIE GEN2

HIGH

DEFAULT

FORCE

PULL

PCIE GEN1

LOW

PCI_CLK1<11>

PCI_CLK3<11>

PCI_CLK4<11>

CLK_PCI_EC<11,36>

LPC_CLK1<11 >

EC_PWM2<13>

RTC_CLK<11,36>

PCI_CLK3

USE DEBUG STRAPS

IGNORE DEBUG STRAP

DEFAULT

R200 10K_0402_5%

Strap@

12

PCI_CLK4 CLK_PCI_EC

NON_FUSION CLOCK MODE

FUSION CLOCK MODE

DEFAULT

+3VALW+3VS

182736

+3VALW+3VS+3VS

R190 10K_0402_5%

Strap@

R190 10K_0402_5%

Strap@

182736

Strap@

12

45

R189 10K_0402_5%

Strap@

R189 10K_0402_5%

Strap@

12

RP12

10K_0804_8P4R_5%

EC ENABLED

EC DISABLED

DEFAULT

45

RP13

RP13 10K_0804_8P4R_5%

10K_0804_8P4R_5%

R191 10K_0402_5%

12

Strap@

12

R204 10K_0402_5%

CLKGEN ENABLED

DEFAULT

CLKGEN DISABLE

+3VALW

Strap@

12

DEBUG STRAPS

FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]

EC_PWM2

LPC ROM

SPI ROM

DEFAULT

R193 10K_0402_5%

R206 2.2K_0402_5%

R205 2.2K_0402_5%R205 2.2K_0402_5%

Strap@

12

RTC_CLKLPC_CLK1

S5 PLUS MODE DISABLED

DEFAULT

S5 PLUS MODE ENABLED

PCI_AD27 PCI_AD26

USE PCI

PULL

PLL

HIGH

DEFAULT

BYPASS

PULL

PCI PLL

LOW

PCI_AD27<11>

PCI_AD26<11>

PCI_AD25<11>

PCI_AD24<11>

PCI_AD23<11>

DISABLE ILA AUTORUN

DEFAULT

ENABLE ILA AUTORUN

R195 2.2K_0402_5%

12

Strap@

PCI_AD25 PCI_AD24

USE FC PLL

BYPASS FC PLL

R196 2.2K_0402_5%

12

Strap@

R197 2.2K_0402_5%

12

USE DEFAULT PCIE STRAPS

DEFAULT

USE EEPROM PCIE STRAPS

12

Strap@

R198 2.2K_0402_5%

PCI_AD23

DISABLE PCI MEM BOOT

DEFAULTDEFAULT

ENABLE PCI MEM BOOT

12

Strap@

R199 2.2K_0402_5%

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/11/13 2013/11/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet

Compal Electronics, Inc.

FCH-VSS/Strap

VALGD MB L

15 57Friday, April 12, 2013

E

0.1

of

A

B

C

D

E

PCIE_CTX_GRX_P[7..0]<5>

PCIE_CTX_GRX_N[7..0]<5>

1 1

2 2

3 3

CLK_PCIE_VGA<11> CLK_PCIE_VGA#<11>

PCIE_CTX_GRX_P[7..0]

PCIE_CTX_GRX_N[7..0]

PCIE_CTX_GRX_P0 PCIE_CTX_GRX_N0

PCIE_CTX_GRX_P1 PCIE_CTX_GRX_N1

PCIE_CTX_GRX_P2 PCIE_CTX_GRX_N2

PCIE_CTX_GRX_P3 PCIE_CTX_GRX_N3

PCIE_CTX_GRX_P4 PCIE_CTX_GRX_N4

PCIE_CTX_GRX_P5 PCIE_CTX_GRX_N5

PCIE_CTX_GRX_P6 PCIE_CTX_GRX_N6

PCIE_CTX_GRX_P7 PCIE_CTX_GRX_N7

CLK_PCIE_VGA CLK_PCIE_VGA#

PX@

RV2 1K_0 402_5%

GPU_RST#

12

PX@

RV4

RV4 100K_0402_5%

100K_0402_5%

AA38

W36

W38

U36

U38

R36

R38

N36

N38 M37

M35

H37

H35 G36

G38

AB35 AA36

AH16

AA30

Y37

Y35

V37

V35

T37

T35

P37

P35

L36

L38 K37

K35 J36

J38

F37

F35 E37

UV1A

PCIE_RX0P PCIE_RX0N

PCIE_RX1P PCIE_RX1N

PCIE_RX2P PCIE_RX2N

PCIE_RX3P PCIE_RX3N

PCIE_RX4P PCIE_RX4N

PCIE_RX5P PCIE_RX5N

PCIE_RX6P PCIE_RX6N

PCIE_RX7P PCIE_RX7N

NC NC

CLOCK

PCIE_REFCLKP PCIE_REFCLKN

TEST_PG

PERSTB

PX@

PART 1 0F 9

PCI EXPRESS INTERFACE

MARS-XTX M2_FCBGA962

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

CALIBRATION

PCIE_CALR_TX

PCIE_CALR_RX

PCIE_CRX_GTX_P[7..0]

PCIE_CRX_GTX_N[7..0]

Y33

PCIE_CRX_C_GTX_P0

Y32

PCIE_CRX_C_GTX_N0

W33

PCIE_CRX_C_GTX_P1

W32

PCIE_CRX_C_GTX_N1 PCIE_CRX_GTX_N1

U33

PCIE_CRX_C_GTX_P2

U32

PCIE_CRX_C_GTX_N2

U30

PCIE_CRX_C_GTX_P3

U29

PCIE_CRX_C_GTX_N3 PCIE_CRX_GTX_N3

T33

PCIE_CRX_C_GTX_P4

T32

PCIE_CRX_C_GTX_N4 PCIE_CRX_GTX_N4

T30

PCIE_CRX_C_GTX_P5

T29

PCIE_CRX_C_GTX_N5 PCIE_CRX_GTX_N5

P33

PCIE_CRX_C_GTX_P6

P32

PCIE_CRX_C_GTX_N6

P30

PCIE_CRX_C_GTX_P7

P29

PCIE_CRX_C_GTX_N7 PCIE_CRX_GTX_N7

N33

NC

N32

NC

N30

NC

N29

NC

L33

NC

L32

NC

L30

NC

L29

NC

K33

NC

K32

NC

J33

NC

J32

NC

K30

NC

K29

NC

H33

NC

H32

NC

Y30

1 2

RV1 1.69K_0402_1%PX@RV1 1.69K_0402_1%PX@

Y29

1 2

RV3 1K_0402_1%PX@RV3 1K_0402_1%P X@

PCIE_CRX_GTX_P[7..0] <5>

PCIE_CRX_GTX_N[7..0] <5>

1 2

CV10.1U_0402_16V7K PX@CV10.1U_0402_16V7K PX@

1 2

CV20.1U_0402_16V7K PX@CV20.1U_0402_16V7K PX@

1 2

CV30.1U_0402_16V7K PX@CV30.1U_0402_16V7K PX@

1 2

CV40.1U_0402_16V7K PX@CV40.1U_0402_16V7K PX@

1 2

CV50.1U_0402_16V7K PX@CV50.1U_0402_16V7K PX@

1 2

CV60.1U_0402_16V7K PX@CV60.1U_0402_16V7K PX@

1 2

CV70.1U_0402_16V7K PX@CV70.1U_0402_16V7K PX@

1 2

CV80.1U_0402_16V7K PX@CV80.1U_0402_16V7K PX@

1 2

CV90.1U_0402_16V7K PX@CV90.1U_0402_16V7K PX@

1 2

CV100.1U_0402_16V7K PX@CV100.1U_0402_16V7K PX@

1 2

CV110.1U_0402_16V7K PX@CV110.1U_0402_16V7K PX@

1 2

CV120.1U_0402_16V7K PX@CV120.1U_0402_16V7K PX@

1 2

CV130.1U_0402_16V7K PX@CV130.1U_0402_16V7K PX@

1 2

CV140.1U_0402_16V7K PX@CV140.1U_0402_16V7K PX@

1 2

CV150.1U_0402_16V7K PX@CV150.1U_0402_16V7K PX@

1 2

CV160.1U_0402_16V7K PX@CV160.1U_0402_16V7K PX@

+0.95VGS

PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0

PCIE_CRX_GTX_P1

PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P3

PCIE_CRX_GTX_P4

PCIE_CRX_GTX_P5

PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6

PCIE_CRX_GTX_P7

LVDS Interface

UV1D

PART 7 0F 9

RSVD/VARY_BL

RSVD/DIGON

LVDS CONTROL

TXCBP_DPB3P TXCBM_DPB3N

TX3P_DPB2P

TX3M_DPB2N

TX4P_DPB1P

TX4M_DPB1N

TX5P_DPB0P

TX5M_DPB0N

LVTMDP

TXCAP_DPA3P TXCAM_DPA3N

TX0P_DPA2P

TX0M_DPA2N

TX1P_DPA1P

TX1M_DPA1N

TX2P_DPA0P

TX2M_DPA0N

MARS-XTX M2_FCBGA962

PX@

+3VGS

5

2

PXS_RST#<13>

APU_PCIE_RST#<11,30,31>

P

B

1

A

G

3

AK27 AJ27

AK35 AL36

AJ38 AK37

AH35 AJ36

AG38 AH37

AF35

NC#AF35

AG36

NC#AG36

AP34 AR34

AW37 AU35

AR37 AU39

AP35 AR35

AN36

NC

AP37

NC

4

GPU_RST#

Y

PX@

UV2

UV2 MC74VHC1G08DFT2G SC70 5P

MC74VHC1G08DFT2G SC70 5P

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/11/13 2013/11/12

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

ATI_MarsXT_M2_PCIE/LVDS

VALGD MB L

16 57Friday, April 12, 2013

E

0.1

A

UV1B

MUTI GFX

+VREFG_GPU

PX_EN

TESTEN

JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO

GPIO_28_FDO

+TSVDD

1

CV32

2

0.1U_0402_16V4Z

PX@ CV32

PX@

AD29 AC29

AJ21 AK21

AW8

AW3

AW5

AW6

AR10

AW10

AU10 AP10 AV11 AT11 AR12

AW12

AU12 AP12

AJ23 AH23

AK26 AJ26

AH20 AH18 AN16

AH17 AJ17 AK17 AJ13 AH15 AJ16 AK16 AL16 AM16 AM14 AM13 AK14 AG30 AN14 AM17 AL13 AJ14 AK13 AN13

AG32 AG33

AJ19 AK19 AJ20 AK20 AJ24 AH26 AH24

AC30

AK24

AH13

AL21

AD28

AM23 AN23 AK23 AL24 AM24

AF29 AG29

AK32

AL31

AJ32 AJ33

AR8 AU8 AP8

AR3 AR1 AU1 AU3

AP6

AU5 AR6

AU6 AT7 AV7 AN7 AV9 AT9

GENLK_CLK GENLK_VSYNC

SWAPLOCKA SWAPLOCKB

NC NC DBG_CNTL0 NC NC NC DBG_DATA0 DBG_DATA1 DBG_DATA2 DBG_DATA3 DBG_DATA4 DBG_DATA5 DBG_DATA6 DBG_DATA7 DBG_DATA8 DBG_DATA9 DBG_DATA10 DBG_DATA11 DBG_DATA12 DBG_DATA13 DBG_DATA14 DBG_DATA15 DBG_DATA16 DBG_DATA17 DBG_DATA18 DBG_DATA19 DBG_DATA20 DBG_DATA21 DBG_DATA22 DBG_DATA23

SMBCLK

SMBus

SMBDATA

SCL

I2C

SDA

GENERAL PURPOSE I/O

GPIO_0 GPIO_1 GPIO_2

GPIO_5_AC_BATT GPIO_6_TACH GPIO_7_BLON GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK GPIO_11 GPIO_12 GPIO_13 GPIO_14_HPD2 GPIO_15_PWRCNTL_0 GPIO_16 GPIO_17_THERMAL_INT GPIO_18_HPD3 GPIO_19_CTF GPIO_20_PWRCNTL_1 GPIO_21 GPIO_22_ROMCSB CLKREQB

GPIO_29 GPIO_30

GENERICA GENERICB GENERICC GENERICD GENERICE_HPD4 GENERICF_HPD5 GENERICG_HPD6

CEC_1

HPD1

DBG_VREFG

BACO

PX_EN

DEBUG

TESTEN

JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO

THERMAL

DPLUS DMINUS

GPIO_28_FDO

TS_A

TSVDD TSVSS

PX@

GENLK_CLK

T31TEST POINT@ T31T EST POINT@

GENLK_VSYNC

T32TEST POINT@ T32T EST POINT@

1 1

VGA_SMB_CK2 VGA_SMB_DA2

2 2

3 3

+1.8VGS

GPIO_28_FDO

4 4

TSVDD MarsCR B Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

GPU_GPIO0<50>

GPU_VID5<50>

GPU_VID1<50>

GPU_VID2<50>

CLK_REQ_VGA#<13>

GPU_VID3<50> GPU_VID4<50>

PX@

12

RV13 499_0402_1%

PX@

12

RV14 249_0402_1%

12

0.1U_0402_16V7K

CV23

PX@

MLPS

H

Disable

Enable

L

1 2

BLM15BD121SN1D_0402

ACIN<36,43>

PX@ LV3

PX@

+VREFG_GPU

+3VGS

REMOTE1+<33> REMOTE1-<33>

+3VGS

LV3

A

@

DV1

DV1 RB751V_SOD323

RB751V_SOD323

RV12 10K_0402_5%@ RV12 10K_0402_5%@

0.60 V level, Please VREFG Divider ans cap close to ASIC

TEST POINT@

RV18 5.11K_0402_5%

RV19 1K_0402_5%

+TSVDD+1.8VGS

GPU_GPIO0

21

GPU_GPIO5 GPU_VID5

GPU_VID1

THM_ALERT#

1 2

GPU_VID2

CLK_REQ_VGA#

GPU_VID3 GPU_VID4

T29

DEBUG@

1 2

PX@

T11TEST POINT @ T11TEST POINT@

REMOTE1+ REMOTE1-

1 2

DEBUG@

RV26 10K_0402_5%

1 2

PX@

RV31 10K_0402_5%

(1.8V@13mA TSVDD)

1

CV31

CV30

2

1U_0402_6.3V6K

10U_0603_6.3V6M

PX@ CV31

PX@

PX@ CV30

PX@

PART 2 0F 9

DPA

DPB

DPC

DPD

B

AVSSN

DAC1

HSYNC VSYNC

RSET

AVDD

AVSSQ

VDD1DI

VSS1DI

NC_SVI2 NC_SVI2 NC_SVI2

MLPS

DDC/AUX

DDC1CLK

DDC1DATA

AUX1P AUX1N

DDC2CLK

DDC2DATA

AUX2P AUX2N

DDCVGACLK

DDCVGADATA

MARS-XTX M2_FCBGA962

B

PS_0

PS_1

PS_2

PS_3

C

AU24

NC

AV23

NC

AT25

NC

AR24

NC

AU26

NC

AV25

NC

AT27

NC

AR26

NC

AR30

NC

AT29

NC

AV31

NC

AU30

NC

AR32

NC

AT31

NC

AT33

NC

AU32

NC

AU14

NC

AV13

NC

AT15

NC

AR14

NC

AU16

NC

AV15

NC

AT17

NC

AR16

NC

AU20

NC

AT19

NC

AT21

NC

AR20

NC

AU22

NC

AV21

NC

AT23

NC

AR22

NC

AD39

VGA_R

R

AD37

AE36

VGA_G

G

AD35

AF37

VGA_B

B

AE38

AC36

HSYNC

AC38

VSYNC

AB34

RV11 499_0402_1%PX@RV11 499_0402_1%PX@

AD34

+AVDD

AE34

AC33

+VDD1DI

AC34

V13

NC

U13

NC

AF33

NC

AF32

NC

AA29

NC

AG21

NC

AC32

NC

AC31 AD30 AD32

AM34

PS_0

AD31

PS_1

AG31

PS_2

AD33

PS_3

AM26

VGA_CLK

AN26

VGA_DAT

AM27 AL27

AM19 AL19

AN20 AM20

AL30

NC

AM30

NC

AL29

NC

AM29

NC

AN21

NC

AM21

NC

AK30

NC

AK29

NC

AJ30 AJ31

T24 TEST POINT@T24 TEST POINT@

T25 TEST POINT@T25 TEST POINT@

T46 TEST POINT@T46 TEST POINT@

T34 TEST POINT@T34 TEST POINT@ T36 TEST POINT@T36 TEST POINT@

1 2

(1.8V@70mA AVDD)

(1.8V@117mA VDD1DI)

T37

T37 T28

T28

GPU_GPIO5

THM_ALERT#

JTAG_TRSTB JTAG_TDI JTAG_TMS

JTAG_TCK

1

CV20

2

PX@ CV20

PX@

0.1U_0402_16V7K

TEST POINT@

TEST POINT@ TEST POINT@

TEST POINT@

10K_0402_5%

VGA_SMB_CK2

VGA_SMB_DA2

1126A Blues Modify

STRAPS

RV5 100K_0402_5%Strap@RV5 100K_0402_5%Strap@

RV6 2.2K_0402_5%Strap@RV6 2.2K_0402_5%Strap@

RV7 10K_0402_5%Strap@RV7 10K_0402_5%Strap@ RV8 10K_0402_5%Strap@RV8 10K_0402_5%Strap@ RV9 10K_0402_5%Strap@RV9 10K_0402_5%Strap@

RV10 10K_0402_5%Strap@RV10 10K_0402_5%Strap@

+AVDD

1

CV18

CV17

2

PX@ CV18

PX@

PX@ CV17

PX@

1U_0402_6.3V6K

0.1U_0402_16V7K

1 2

1

CV22

CV21

2

PX@ CV22

PX@

PX@ CV21

PX@

1U_0402_6.3V6K

10U_0603_6.3V6M

DIS:+3VGS UMA:+3VS

+3VGS

12

@

RV24

RV25

RV25 10K_0402_5%

10K_0402_5%

DMN66D0LDW-7 2N_SOT363-6

C

+3VGS

12

+3VGS

12 12 12

12

AVDD MarsCRB Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

+1.8VGS

1 2

LV1

PX@LV1

PX@

BLM15BD121SN1D_0402

1

CV19

2

PX@ CV19

PX@

10U_0603_6.3V6M

+1.8VGS+VDD1DI

LV2

PX@LV2

PX@

BLM15BD121SN1D_0402

VDD1DI MarsC RB Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

+3VGS

2

61

5

QV3A

@ QV3A

@

4

QV3B

@ QV3B

@

DMN66D0LDW-7 2N_SOT363-6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

EC_SMB_CK2 <33,36>

3

EC_SMB_DA2 <33,36>

Compal Secret Data

2012/11/13 2013/11/12

Compal Secret Data

D

CONFIGURATION STRAPS

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

STRAPS

TX_PWRS_ENB

TX_DEEMPH_EN

BIF_GEN3_EN_A

BIF_VGA DIS

ROMIDCFG[2:0]

BIOS_ROM_EN PS_2[3]

AUD[1]

AUD[0]

CEC_DIS PS_0[4]

RESERVED PS_1[3]

RESERVED PS_1[2]

RESERVED NA

AUD_PORT_CONN_PINSTRAP[2] PS_3[5]

AUD_PORT_CONN_PINSTRAP[1] PS_3[4]

AUD_PORT_CONN_PINSTRAP[0] PS_0[5]

PS_1[4] 0:50% Tx output swing

PS_1[5] 0:Tx de-emphasis disabled

PS_1[1]

PS_2[4]

PS_0[3..1]

NA

DESCRIPTION OF DEFAULT SETTINGSMLPS

Transmitter Power Savings Enable

1:Full Tx output swing

PCIE Transmitter De-emphasis Enable

1:Tx de-emphasis enabled

PCIE Gen3 Enable (NOTE:RESERVED for Thames/Seymour and should be strapped to 0)

0:GEN3 not support at power-on 1:GEN3 supported at power-on

VGA control

0:VGA controller capacity enabled 1:VGA controller capacity disabled (for multi-GPU)

Serial ROM type or Memory Aperture Size Select

If PS_2[3]=0, defines memory aperture siz e If PS_2[3]=1, defines ROM type 100 - 512Kbit M25P05A (ST) 101 - 1Mbit M25P10A (ST ) 101 - 2Mbit M25P20 (ST) 101 - 4Mbit M25P40 (ST) 101 - 8Mbit M25P80 (ST) 100 - 512Kbit Pm25LV010 (Chingis) 101 - 1Mbit Pm25LV010 (Chingis)

Enable external BIOS ROM device

0:Disabled 1:Enabled

00 - No audio function 01 - Audio for DP only 10 - Audio for DP and HDMI if dongle is detected 11 - Audio for both DP and HDMI

HDMI must only be enabled on systems that are legally entitled. It isthe responsibility of the system designer to ensure that the system is entitled to support this feature.

Reserved for future ASIC

NOTE:ALLOW FOR PULLUP PADS FOR THE RESERVED STRAPS BUT DO NOT INSTALL RESISTOR IF THESE GPIOS ARE USEED, THEY MUST KEEP LOW AND NOT CONFLICT DURING RESET

Reserved

Reserved (for Thames/Whistler/Seymour only)

STRAPS TO INDICATE THE NUMBER OF AUDIO CAPABLE DISPLAY OUTPUTS

111 = 0 usable endpoints 110 = 1 usable endpoints 101 = 2 usable endpoints 100 = 3 usable endpoints 011 = 4 usable endpoints 010 = 5 usable endpoints 001 = 6 usable endpoints 000 = all endpoints are usable

MLPS Strap

CapacitorBits[5:4]

Deciphered Date

D

PS_0[5:1]

PS_1[5:1]

PS_2[5:1]

PS_3[5:1]

PS_0 PS_1 PS_2 PS_3

Strap@

CV26

0.01U_0402_16V7K

Bits[3:1]

0 0 1

1 1

0 0 0

1 1

0 0 0

0 0

1 1

X X X

Strap@

PX@

1

CV27

2

Strap@

CV29

1

CV28

2

0.01U_0402_16V7K

1

2

0.68U_0402_10V6K

R_pu R_pd

NC

8.45K 2K

NC

4.75K

680 nF

NC

4.75K

NC

X

12

Strap@

RV20

X76@ RV20

X76@

8.45K_0402_1%

RV27

X76@ RV27

X76@

8.45K_0402_1%

12

4.75K_0402_1%

PX@RV28

PX@

8.45K_0402_1%

4.75K_0402_1%

Place CLOSE VGA CHIP

Title

ATI_MarsXT_M2_Main_MSIC

Size Document Number Rev

C

Date: Sheet of

E

RECOMMENDED SETTINGS 0= DO NOT INSTALL RESISTOR 1 = INSTALL 10K RESISTOR X = DESIGN DEPENDANT NA = NOT APPLICABLE

Mapping to VRAM type please refer to page 21

X

12

Strap@

RV21

RV28

Compal Electronics, Inc.

8.45K_0402_1%

12

4.75K_0402_1%

RV22

RV29

PX@RV29

PX@

VALGD MB L

E

12

8.45K_0402_1%

12

PX@RV23

PX@

PX@RV30

PX@

2K_0402_1%

+1.8VGS

RV23

RV30

17 57Friday, April 12, 2013

Default Setting

X

1

0

XXX

X

XX

0

XXX

12

0.1

A

3/1 SIT downsize to 0402, BLM15AX221SN1D (Murata)

MPLL_PVDD Mars CRB Design 220ohm 1 1

0.1u 1 1

1 1

2 2

1u 1 1 10u 1 1

SPLL_PVDD Mars CRB Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

SPLL_VDDC Mars CRB Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

+1.8VGS

+0.95VGS

LV4

PX@LV4

PX@

BLM15AX221SN1D 0402

SM01000MK00

LV5

PX@LV5

PX@

1 2

BLM15BD121SN1D_0402

LV6

PX@LV6

PX@

1 2

BLM15BD121SN1D_0402

B

+SPLL_VDDC

+MPV18

10U_0603_6.3V6M

+SPV18

10U_0603_6.3V6M

1

CV33

2

PX@ CV33

PX@

1

CV38

2

PX@ CV38

PX@

1

CV43

2

PX@ CV43

PX@

(MPLL_PVDD:1.8V@130mA )

1

CV34

CV35

2

1U_0402_6.3V6K

PX@ CV34

1U_0402_6.3V6K

PX@

PX@ CV35

PX@

0.1U_0402_16V7K

(SPLL_PVDD:1.8V@75mA )

1

CV40

CV39

2

PX@ CV40

PX@

PX@ CV39

PX@

1U_0402_6.3V6K

0.1U_0402_16V7K

(SPLL_VDDC:0.95V@100mA )

1

CV44

CV45

2

PX@ CV45

PX@

PX@ CV44

PX@

1U_0402_6.3V6K

0.1U_0402_16V7K

+MPV18

+SPV18

+SPLL_VDDC

AM10

AN10

AF30 AF31

AN9

UV1C

H7 H8

PX@

C

MPLL_PVDD MPLL_PVDD

SPLL_PVDD

SPLL_VDDC

SPLL_PVSS

NC_XTAL_PVDD NC_XTAL_PVSS

PART 9 0F 9

PLLS/XTAL

MARS-XTX M2_FCBGA962

XTALIN

XTALOUT

XO_IN2

CLKTESTA CLKTESTB

XO_IN

AV33

AU34

AW34

AW35

AK10 AL10

XTALIN

RV40 0_0402_5%

XTALOUT

12

DEBUG@

CV41

0.1U_0402_16V7K

12

DEBUG@

RV33

51.1_0402_1%

For EMI

GCLK@

1 2

D

12

DEBUG@

CV42

0.1U_0402_16V7K

DEBUG@

RV34

51.1_0402_1%

PXNOGCLK@

15P_0402_50V8J

RV32 1M_0402_5%PXNOGCLK@ RV32 1M_0402_5%PXNOGCLK@

XTALIN

2

27MHZ 10PF +-20PPM X3G027000DA1H

CV36

1

GCLK_27MHZ <38>

1 2

YV1

4

NC

OSC

1

OSC

NC

PXNOGCLK@

E

3

XTALOUT

2

PXNOGCLK@

CV37

CV37 15P_0402_50V8J

15P_0402_50V8J

1

#9/11 need to confirm w/ Power team

300mil(7.2A)

PX@

1

CV48

4.7U_0603_6.3V6K

SIT: Change to +5VALW for Eur lot 6.

3 3

+5VALW

PXS_PWREN#

2

PX@

47K_0402_5%

RV41

PX@

QV2

QV2 2N7002_SOT23

2N7002_SOT23

+1.5V to +1.5VGS

+1.5V +1.5VGS

AO4430: Rdson: 5.5mohm @ VGS=10V

12

13

D

2

G

S

8 7 6 5

RV42 0_0402_5%

0_0402_5%

1 2

AO4304L_SO8

PX@

@RV42

@

UV4

4

1

PX@

CV53

0.1U_0402_25V6

2

+3VS to +3VGS

+3VS +3VGS

3 1

PXS_PWREN

+5VALW

RV37

1 2

100K_0402_5%

PX@

2

G

1 2

0_0402_5%

13

D

PX@

QV6

QV6 2N7002K_SOT23-3

2N7002K_SOT23-3

S

PX@

RV38

@

1

CV50

0.1U_0402_16V4Z

2

2N7002_SOT23

300mil(7.2A)

QV1

@

QV1

@

D

S

1 2

13

RV39

@RV39

@

470_0603_5%

2

PXS_PWREN#

G

#9/11 need to confirm w/ Power team

1 2 3

PX@

1

CV49

4.7U_0603_6.3V6K

2

PX@

QV8

QV8 LP2301ALT1G_SOT23-3

LP2301ALT1G_SOT23-3

2

1

PX@

CV52

0.1U_0402_16V4Z

2

10U_0603_6.3V6M

PX@

1

CV46

PX@

2

PXS_PWREN#

1U_0603_10V6K

1

CV47

2

12

13

D

S

@

RV36

RV36 470_0603_5%

470_0603_5%

2

G

@

QV7

QV7 2N7002K_SOT23-3

2N7002K_SOT23-3

+1.8VS to +1.8VGS

+3VALW

12

PX@

RV35

RV35 100K_0402_5%

100K_0402_5%

PXS_PWREN#

1

PX@

OUT

QV9

IN

GND

3

QV9 DTC124EKAT146_SC59-3

DTC124EKAT146_SC59-3

2

PXS_PWREN<13,36,45,51,52>

4 4

PXS_PWREN

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2012/11/13 2013/11/12

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

ATI_MarsXT_M2_BACO POWER

Size Docum ent Number Rev

Custom

Date: Sheet of

D

Date: Sheet

VALGD MB L

E

18 57Tuesday, April 16, 2013

0.1

of