Compal LA-A091P VALGC, G505s, G505, LA-A091P VALGD Schematic

A

1 1

B

C

D

E

Compal Confidential

2 2

VALGC_GD M/B Schematics Document

AMD Fs1r2 Richland Processor with DDRIII + Bolton-M3 FCH

AMD Mars XT M2

LA-A091P

3 3

2013-04-16

REV:1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/11/13 2013/11/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

VALGD MB L

0.1

1 57Friday, April 12, 2013

E

0.1

A

Compal confidential

File Name :LA-A091P

B

C

D

E

AMD MARS XT M2 128 bi

1 1

LVDS Conn.

HDMI Conn.

Sun Pro M2 64bit

VRAM: DDR3 type, 1GB/ 2GB

page 27

page 29

page 16~25

LVDS translator

RTD2132S

ts

page 26

PCIEx8 Gen2

DP Port0

DP Port2

AMD FS1r2 APU

Richland uPGA 722 pin

DP0

35mm x 35mm

DP2

DP1

page 5,6,7,8

Memory BUS(DDRIII)

Dual Channel

DDR3 / DDR3L 1600MHz

204pin DDRIII-SO-DIMM X2

BANK

0, 1, 2

page 9,10

x4 UMI Gen. 1

GPP0GPP1

PCIe Mini Card

WLAN+BT4.0 Combo

2 2

3 3

PCIe Port 1

USB20 Port 2

RJ45 Conn.

CRT Conn.

Thermal Sensor

Touch Pad

Int. KBD

page 32

page 28

page 33

page 37

page 30

LAN

PCIe Port 0

Atheros AR8162 QCA8172(10/100)

page 31

FCH CRT (VGA DAC)

EC

ENE KB9012

SPI ROM

4MB

USB20 x1

page 36

page 12

2.5GT/s per lane

Bolton M3

uFCBGA-656

24.5mm x 24.5mm

page 11~15

USB30 x2

USB20 x6

SATA Gen3

SATA

AZALIA

Audio Codec

CONEXANT CX20757

page 35

Left USB3.0 x2

USB30 Port 0,1

page 39

Touch Screen

USB20 Port 4

page 39

Right USB2.0

USB20 Port 0

page 39

Int. Camera

USB20 Port 3

Card Reader

Realtek RTS5170

USB20 Port 6

page 27

page 37

HDD Conn.

SATA Port 0

page 34

ODD Conn.

SATA Port 1

page 34

Int. MIC Conn.

page 35

Int. Speaker Conn.

page 35

Audio Combo Jacks

HP & MIC

page 37

Sub-borad

15" 14"

4 4

Power/B

LS9902P

IO/B

LS9901P LS9904P

LED/B

LS9903P

ODD/B

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/11/13 2013/11/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

MB Block Diagram

VALGD MB L

E

0.1

2 57Friday, April 12, 2013

0.1

A

Voltage Rails

power plane

1 1

+B

State

S0

S3

2 2

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery do

n't exist

O

X

+5VALW

+3VALW

+1.1VALW

O

X

X X X

+1.5V

+1.5V_APU

O

X X

X

SMBUS Control Table

SOURCE

SMB_EC_CK1 SMB_EC_DA1

SMB_EC_CK2_SUS SMB_EC_DA2_SUS

FCH_SCLK0 FCH_SDATA0

3 3

SMB_EC_CK2 SMB_EC_DA2

KB9012

+3VALW

KB9012

+3VALW

FCH

+3VS

KB9012

+3VS (LV shifter)

EC SM Bus1 address

Device

Smart Battery

PCH SM Bus address

4 4

Device Address

DDR DIMM0

DDR DIMM2

Address Address

0001 011X b

1001 000Xb

1001 010Xb

VGA BATT KB9012 SODIMM

X V

+3VALW

X

V V V

A

X

X X

X

X X

EC SM Bus2 address

Device

Thermal Sen sor

SB-TSI(default)

VGA(int. thermal)

RTD2132S

VGA(ext. thermal)

WLAN WWAN

X X

V

+3VS +3VS

X XX

V

1001_101xb

1001_100xb

1000_001xb

1010_1000b

0100_1101b

B

+5VS

+3VS

+2.5VS

+1.5VS

+1.2VS

+1.1VS

+0.75VS

+APU_CORE

+APU_CORE_NB

+VGA_CORE

+3.3VGS

+1.8VGS

+1.5VGS

+0.95VGS

Thermal Sensor

X

B

C

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S3# SLP_S5# +VALW +V +VS Clock

HIGHHIGH

HIGH

ON

HIGH HIGH

HIGH

LOW

LOW LOW

D

ONONON ON

ON

OFF

E

LOW

OFF

Board ID / SKU ID Table for AD channelBOARD ID Table

Board ID

0 1 2 3

OO

4 5 6

X

7

PCB Revision

0.2

ID BRD ID Ra Rb Vab

x

0

0V

0.25V

0.5V

0.82VR01 EVT

1

2

3

R10 MP0

R03 PVT

R02 DVT

100K

8.2K

18K

33K

Ra = R310 R

b = R311

BOM Structure Table

USB Port Table

X

USB 3.0USB 2.0 Port

0

4 External USB Port

USB Port 2.0 (Right Side)

1 2

Mini Card(WLAN)

3

Camera /

4

Touch Screen

FCH

X

XX XX

X

APU RTD2132

X X

V

+1.5V

X X

X

XHCI

5 6

Card Reader

7 8 9

10

0 1 2 3

USB 2.0 Port (Left Side)

11

USB 2.0 Port (Left Side)

12 13

USB OC MAPPING

OC# USB Port

USB20 port10,port11

0

USB20 port0

1 2 3

APU PCIE PORT LIST

Port Device

1

LAN

2

WLAN

FCH PCIE PORT LIST

Port Device

3 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/11/13 2013/11/12

USB30 port0,port1

1 2 3 4

Compal Secret Data

Deciphered Date

D

PX@ 14@ 15@ 45@ CMOS@ 8162@ 8172@ CMOS@ TS@ X76@ GCLK@ NOGCLK@ GCLK302@ GCLK238@ LVDS@ PXNOGCLK@ LDO@ SWR@

DEBUG@

ME@ MIC@ 885N@ JUMP@ TEST POINT@ SHORT PAD@ EMI@ @ESD@ @EMI@ @ MARS@ 2132S@ 2132R@ ShareROM@ Strap@

Date: Sheet of

BTO ItemBOM Structure

VGA circuit

For 14"

For 15"

HDMI LOGO

CMOS Camera part

AR8162 LAN part

AR8172 LAN part

For CMOS circuit

For Touch Screen circuit

X76 Level part for VRAM

Ues GCLK circuit

No use GCLK circuit

302 part for DIS

238 part for UMA

LVDS circuit

No use GCLK circuit in GPU

LDO mode for LAN

SWR mode for LAN

For debug

ME part

MIC part

Unpop in KBC page

JUMP

TSET POINT

SHORT PAD

EMI part

Reserve for ESD

Reserve for EMI

Unpop

VRAM CHB parts for MARS

Panel PWM part for RTD2132S

Panel PWM part for RTD2132R

Reserve for ShareROM

Reserve for Strap pin

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Compal Electronics, Inc.

Notes List

VALGD MB L

E

3 57Friday, April 12, 2013

0.1

5

Mars XT VRAM STRAP

Vendor

UV5,UV6,UV7,UV8, UV9,UV10,UV11,UV12

Samsung 2048Mbits SA000068U00

MS2G

D D

MM2G

MH2G 0 1 1 6.98K 4.99K

128M16 K4W2G1646E-BC1A FBGA

Micron 2048Mbits SA000067500 128Mx16 MT41J128M16JT-093G:k

Hynix 2048Mbits SA000065300 128M16 H5TQ2G63DFR-N0C FBGA

PS_3[3] PS_3[2] PS_3[1] R_pu R_pd

0 0 0 NC 4.75K

0 0 1 8.45K 2K

4

X76@X76@

RV20 RV27

4.53K 2K0 1 0

3

Sun PRO VRAM STRAP

X76@ X76@

Vendor

UV9,UV10,UV11,UV12

Samsung 2048Mbits

SS2G

SM2G

SS1G

SM1G

SH1G

SA000068R00 256M16 K4W4G1646B-HC11 FBGA

Micron 2048Mbits SA000065D00 256M16 MT41K256M16HA-107G

Samsung 1024Mbits SA000068U00 128M16 K4W2G1646E-BC1A FBGA

Micron 1024Mbits SA000067500 128Mx16 MT41J128M16JT-093G:k

Hynix 1024Mbits SA000065300 128M16 H5TQ2G63DFR-N0C FBGA

2

PS_3[2]PS_3[3] R_pdR_puPS_3[1]

0

1 1 1

00

100

01 1

1

RV27RV20

4.75KNC

2K8.45K

10K3.4K

4.75K NC

Power-Up/Down Sequence

C C

"Mars" has the following requirements with regards to power-supply sequencing to avoid damaging the ASIC:

All the ASIC supplies must reach their respective nominal voltages within 20ms

‧

of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred. The maximum slew rate on all rails is 50mV/us.

The external pull ups on the DDC/AUX signals (if applicable) should ramp up

‧

before or after both VDDC and VDD_CT have ramped up.

VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC should

‧

reach 90% before VDD_CT starts to ramp up (or vice versa).

For power down, reversing the ramp-up sequence is recommended.

‧

VDDR3(+3VGS)

PCIE_VDDC(+0.95VGS)

B B

VDDR1(+1.5VGS)

VDDC/VDDCI(+VGA_CORE)

VDD_CT(+1.8VGS)

PERSTb

REFCLK

Straps Reset

Straps Valid

A A

Global ASIC Reset

T4+16clock

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2012/11/13 2013/11/12

3

Compal Secret Data

Deciphered Date

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Compal Electronics, Inc.

VGA Notes List

VALGD MB L

1

4 57Friday, April 12, 2013

0.1

A

B

C

D

E

1 2

PCIE_CTX_GRX_P[0..7]

PCIE_CTX_GRX_N[0..7]

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2

C35 0.1U_0402_16V7KC35 0.1U_0402_16V7K

1 2

C36 0.1U_0402_16V7KC36 0.1U_0402_16V7K

1 2

C82 0.1U_0402_16V7KC82 0.1U_0402_16V7K

1 2

C103 0.1U_0402_16V7KC103 0.1U_0402_16V7K

1 2

C37 0.1U_0402_16V7KC37 0.1U_0402_16V7K

1 2

C38 0.1U_0402_16V7KC38 0.1U_0402_16V7K

1 2

C39 0.1U_0402_16V7KC39 0.1U_0402_16V7K

1 2

C40 0.1U_0402_16V7KC40 0.1U_0402_16V7K

1 2

C41 0.1U_0402_16V7KC41 0.1U_0402_16V7K

1 2

C42 0.1U_0402_16V7KC42 0.1U_0402_16V7K

1 2

C43 0.1U_0402_16V7KC43 0.1U_0402_16V7K

1 2

C44 0.1U_0402_16V7KC44 0.1U_0402_16V7K

PCIE_CTX_GRX_P[0..7] <16>

PCIE_CTX_GRX_N[0..7] <16>PCIE_CRX_GTX_N[0..7]<16>

CV2090.1U_0402_16V7K PX@CV2090.1U_0402_16V7K PX@ CV2150.1U_0402_16V7K PX@CV2150.1U_0402_16V7K PX@ CV2050.1U_0402_16V7K PX@CV2050.1U_0402_16V7K PX@ CV2030.1U_0402_16V7K PX@CV2030.1U_0402_16V7K PX@ CV2040.1U_0402_16V7K PX@CV2040.1U_0402_16V7K PX@ CV2120.1U_0402_16V7K PX@CV2120.1U_0402_16V7K PX@ CV2110.1U_0402_16V7K PX@CV2110.1U_0402_16V7K PX@ CV2130.1U_0402_16V7K PX@CV2130.1U_0402_16V7K PX@ CV2100.1U_0402_16V7K PX@CV2100.1U_0402_16V7K PX@ CV2060.1U_0402_16V7K PX@CV2060.1U_0402_16V7K PX@ CV2070.1U_0402_16V7K PX@CV2070.1U_0402_16V7K PX@ CV250.1U_0402_16V7K PX@CV250.1U_0402_16V7K PX@ CV510.1U_0402_16V7K PX@CV510.1U_0402_16V7K PX@ CV240.1U_0402_16V7K PX@CV240.1U_0402_16V7K PX@ CV2140.1U_0402_16V7K PX@CV2140.1U_0402_16V7K PX@ CV2080.1U_0402_16V7K PX@CV2080.1U_0402_16V7K PX@

PCIE_CTX_GRX_P0 PCIE_CTX_GRX_N0 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_P7 PCIE_CTX_GRX_N7

PCIE_PTX_C_DRX_P0 <31> PCIE_PTX_C_DRX_N0 <31> PCIE_PTX_C_DRX_P1 <30> PCIE_PTX_C_DRX_N1 <30>

UMI_TXP0 <11> UMI_TXN0 <11> UMI_TXP1 <11> UMI_TXN1 <11> UMI_TXP2 <11> UMI_TXN2 <11> UMI_TXP3 <11> UMI_TXN3 <11>

LAN

W

LAN

PCIE_CRX_GTX_P[0..7]<16>

1 1

PCIE_PRX_DTX_P0<31> PCIE_PRX_DTX_N0<31> PCIE_PRX_DTX_P1<30>

2 2

PCIE_PRX_DTX_N1<30>

UMI_RXP0<11> UMI_RXN0<11> UMI_RXP1<11> UMI_RXN1<11> UMI_RXP2<11> UMI_RXN2<11> UMI_RXP3<11> UMI_RXN3<11>

+1.2VS

PCIE_CRX_GTX_P[0..7]

PCIE_CRX_GTX_N[0..7]

PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_N7

1 2

R1 196_0402_1%R1 196_0402_1%

P_ZVDDP

AG11

AB8 AB7 AA9 AA8 AA5 AA6

AE5 AE6 AD8 AD7 AC9 AC8 AC5 AC6

AG8 AG9 AG6 AG5 AF7 AF8 AE8 AE9

Y8

Y7 W9 W8 W5 W6

V8

V7

U9

U8

U5

U6

T8

T7

R9

R8

R5

R6

P8

P7

N9

N8

N5

N6 M8 M7

JCPU1A

P_GFX_RXP0 P_GFX_RXN0 P_GFX_RXP1 P_GFX_RXN1 P_GFX_RXP2 P_GFX_RXN2 P_GFX_RXP3 P_GFX_RXN3 P_GFX_RXP4 P_GFX_RXN4 P_GFX_RXP5 P_GFX_RXN5 P_GFX_RXP6 P_GFX_RXN6 P_GFX_RXP7 P_GFX_RXN7 P_GFX_RXP8 P_GFX_RXN8 P_GFX_RXP9 P_GFX_RXN9 P_GFX_RXP10 P_GFX_RXN10 P_GFX_RXP11 P_GFX_RXN11 P_GFX_RXP12 P_GFX_RXN12 P_GFX_RXP13 P_GFX_RXN13 P_GFX_RXP14 P_GFX_RXN14 P_GFX_RXP15 P_GFX_RXN15

P_GPP_RXP0 P_GPP_RXN0 P_GPP_RXP1 P_GPP_RXN1 P_GPP_RXP2 P_GPP_RXN2 P_GPP_RXP3 P_GPP_RXN3

P_UMI_RXP0 P_UMI_RXN0 P_UMI_RXP1 P_UMI_RXN1 P_UMI_RXP2 P_UMI_RXN2 P_UMI_RXP3 P_UMI_RXN3

P_ZVDDP

ME@

PCI EXPRESS

LOTES_ACA-ZIF-109-P12-A_FS1R2

GPP GRAPHICS

UMI

P_GFX_TXP0 P_GFX_TXN0 P_GFX_TXP1 P_GFX_TXN1 P_GFX_TXP2 P_GFX_TXN2 P_GFX_TXP3 P_GFX_TXN3 P_GFX_TXP4 P_GFX_TXN4 P_GFX_TXP5 P_GFX_TXN5 P_GFX_TXP6 P_GFX_TXN6 P_GFX_TXP7 P_GFX_TXN7 P_GFX_TXP8 P_GFX_TXN8 P_GFX_TXP9

P_GFX_TXN9 P_GFX_TXP10 P_GFX_TXN10 P_GFX_TXP11 P_GFX_TXN11 P_GFX_TXP12 P_GFX_TXN12 P_GFX_TXP13 P_GFX_TXN13 P_GFX_TXP14 P_GFX_TXN14 P_GFX_TXP15 P_GFX_TXN15

P_GPP_TXP0

P_GPP_TXN0

P_GPP_TXP1

P_GPP_TXN1

P_GPP_TXP2

P_GPP_TXN2

P_GPP_TXP3

P_GPP_TXN3

P_UMI_TXP0 P_UMI_TXN0 P_UMI_TXP1 P_UMI_TXN1 P_UMI_TXP2 P_UMI_TXN2 P_UMI_TXP3 P_UMI_TXN3

P_ZVSS

AB2

PCIE_CTX_C_GRX_P0

AB1

PCIE_CTX_C_GRX_N0

AA3

PCIE_CTX_C_GRX_P1

AA2

PCIE_CTX_C_GRX_N1

Y5

PCIE_CTX_C_GRX_P2

Y4

PCIE_CTX_C_GRX_N2

Y2

PCIE_CTX_C_GRX_P3

Y1

PCIE_CTX_C_GRX_N3

W3

PCIE_CTX_C_GRX_P4

W2

PCIE_CTX_C_GRX_N4

V5

PCIE_CTX_C_GRX_P5

V4

PCIE_CTX_C_GRX_N5

V2

PCIE_CTX_C_GRX_P6

V1

PCIE_CTX_C_GRX_N6

U3

PCIE_CTX_C_GRX_P7

U2

PCIE_CTX_C_GRX_N7

T5 T4 T2 T1 R3 R2 P5 P4 P2 P1 N3 N2 M5 M4 M2 M1

AD5

PCIE_PTX_DRX_P0

AD4

PCIE_PTX_DRX_N0

AD2

PCIE_PTX_DRX_P1

AD1

PCIE_PTX_DRX_N1

AC3 AC2 AB5 AB4

AG2

UMI_TXP0_C

AG3

UMI_TXN0_C

AF4

UMI_TXP1_C

AF5

UMI_TXN1_C

AF1

UMI_TXP2_C

AF2

UMI_TXN2_C

AE2

UMI_TXP3_C

AE3

UMI_TXN3_C

AH11

P_ZVSS

R2 196_0402_1%R2 196_0402_1%

3 3

Power Sequence of APU

+1.5V

+2.5VS

+1.5VS

+APU_CORE

4 4

+APU_CORE_NB

+1.2VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/11/13 2013/11/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

FS1r2 PCIE/UMI

VALGD MB L

E

5 57Friday, April 12, 2013

Group A

Group B

0.1

A

1 1

JCPU1B

MEMORY CHANNEL A

DDRA_SMA[15..0]<9>

DDRA_SBS0#<9> DDRA_SBS1#<9> DDRA_SBS2#<9> DDRA_SDM[7..0]<9>

2 2

DDRA_SDQS0<9> DDRA_SDQS0#<9> DDRA_SDQS1<9> DDRA_SDQS1#<9> DDRA_SDQS2<9> DDRA_SDQS2#<9> DDRA_SDQS3<9> DDRA_SDQS3#<9> DDRA_SDQS4<9> DDRA_SDQS4#<9> DDRA_SDQS5<9> DDRA_SDQS5#<9> DDRA_SDQS6<9> DDRA_SDQS6#<9> DDRA_SDQS7<9> DDRA_SDQS7#<9>

DDRA_CLK0<9> DDRA_CLK0#<9> DDRA_CLK1<9> DDRA_CLK1#<9>

DDRA_CKE0<9> DDRA_CKE1<9>

DDRA_ODT0<9> DDRA_ODT1<9>

3 3

DDRA_SCS0#<9> DDRA_SCS1#<9>

DDRA_SRAS#<9> DDRA_SCAS#<9> DDRA_SWE#<9>

MEM_MA_RST#<9> MEM_MA_EVENT#<9>

+MEM_VREF

+1.5V_APU

Place them close to APU within 1"

Place them close to APU within 1"Place them close to APU within 1"

15mil

DDRA_SMA0 DDRA_SMA1 DDRA_SMA2 DDRA_SMA3 DDRA_SMA4 DDRA_SMA5 DDRA_SMA6 DDRA_SMA7 DDRA_SMA8 DDRA_SMA9 DDRA_SMA10 DDRA_SMA11 DDRA_SMA12 DDRA_SMA13 DDRA_SMA14 DDRA_SMA15

DDRA_SBS0# DDRA_SBS1# DDRA_SBS2#

DDRA_SDM0 DDRA_SDM1 DDRA_SDM2 DDRA_SDM3 DDRA_SDM4 DDRA_SDM5 DDRA_SDM6 DDRA_SDM7

DDRA_SDQS0 DDRA_SDQS0# DDRA_SDQS1 DDRA_SDQS1# DDRA_SDQS2 DDRA_SDQS2# DDRA_SDQS3 DDRA_SDQS3# DDRA_SDQS4 DDRA_SDQS4# DDRA_SDQS5 DDRA_SDQS5# DDRA_SDQS6 DDRA_SDQS6# DDRA_SDQS7 DDRA_SDQS7#

DDRA_CLK0 DDRA_CLK0# DDRA_CLK1 DDRA_CLK1#

DDRA_CKE0 DDRA_CKE1

DDRA_ODT0 DDRA_ODT1

DDRA_SCS0# DDRA_SCS1#

DDRA_SRAS# DDRA_SCAS# DDRA_SWE#

MEM_MA_RST#

MEM_MA_EVENT#

1 2

R3 39.2_0402_1%R3 39.2_0402_1%

M_ZVDDIO

M21

M22

AA25

AD27 AC23 AD19 AC15

AE26 AD26 AB22 AA22 AB18 AA18 AA14 AA15

AA27

AA26

W24 W23

W20

W21

U20 R20 R21 P22 P21 N24 N23 N20 N21

U23

L24

L21 L20

U24 U21

L23

E14

J17 E21 F25

G14 H14 G18 H18

J21 H21 E27 E26

T21 T22 R23 R24

H28 H27

Y25

V22

V21

H25 T24

MA_ADD0 MA_ADD1 MA_ADD2 MA_ADD3 MA_ADD4 MA_ADD5 MA_ADD6 MA_ADD7 MA_ADD8 MA_ADD9 MA_ADD10 MA_ADD11 MA_ADD12 MA_ADD13 MA_ADD14 MA_ADD15

MA_BANK0 MA_BANK1 MA_BANK2

MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7

MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7

MA_CLK_H0 MA_CLK_L0 MA_CLK_H1 MA_CLK_L1

MA_CKE0 MA_CKE1

MA_ODT0 MA_ODT1

MA_CS_L0 MA_CS_L1

MA_RAS_L MA_CAS_L MA_WE_L

MA_RESET_L MA_EVENT_L

M_VREF

M_ZVDDIO

ME@

MEMORY CHANNEL A

LOTES_ACA-ZIF-109-P12-A_FS1R2

B

MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7

MA_DATA8

MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15

MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23

MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31

MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39

MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47

MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55

MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63

E13 J13 H15 J15 H13 F13 F15 E15

H17 F17 E19 J19 G16 H16 H19 F19

H20 F21 J23 H23 G20 E20 G22 H22

G24 E25 G27 G26 F23 H24 E28 F27

AB28 AC27 AD25 AA24 AE28 AD28 AB26 AC25

Y23 AA23 Y21 AA20 AB24 AD24 AA21 AC21

AA19 AC19 AC17 AA17 AB20 Y19 AD18 AD17

AA16 Y15 AA13 AC13 Y17 AB16 AB14 Y13

DDRA_SDQ0 DDRA_SDQ1 DDRA_SDQ2 DDRA_SDQ3 DDRA_SDQ4 DDRA_SDQ5 DDRA_SDQ6 DDRA_SDQ7

DDRA_SDQ8 DDRA_SDQ9 DDRA_SDQ10 DDRA_SDQ11 DDRA_SDQ12 DDRA_SDQ13 DDRA_SDQ14 DDRA_SDQ15

DDRA_SDQ16 DDRA_SDQ17 DDRA_SDQ18 DDRA_SDQ19 DDRA_SDQ20 DDRA_SDQ21 DDRA_SDQ22 DDRA_SDQ23

DDRA_SDQ24 DDRA_SDQ25 DDRA_SDQ26 DDRA_SDQ27 DDRA_SDQ28 DDRA_SDQ29 DDRA_SDQ30 DDRA_SDQ31

DDRA_SDQ32 DDRA_SDQ33 DDRA_SDQ34 DDRA_SDQ35 DDRA_SDQ36 DDRA_SDQ37 DDRA_SDQ38 DDRA_SDQ39

DDRA_SDQ40 DDRA_SDQ41 DDRA_SDQ42 DDRA_SDQ43 DDRA_SDQ44 DDRA_SDQ45 DDRA_SDQ46 DDRA_SDQ47

DDRA_SDQ48 DDRA_SDQ49 DDRA_SDQ50 DDRA_SDQ51 DDRA_SDQ52 DDRA_SDQ53 DDRA_SDQ54 DDRA_SDQ55

DDRA_SDQ56 DDRA_SDQ57 DDRA_SDQ58 DDRA_SDQ59 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDQ62 DDRA_SDQ63

DDRA_SDQ[63..0] <9>

C

DDRB_SMA[15..0]<10>

DDRB_SBS0#<10> DDRB_SBS1#<10> DDRB_SBS2#<10> DDRB_SDM[7..0]<10>

DDRB_SDQS0<10> DDRB_SDQS0#<10> DDRB_SDQS1<10> DDRB_SDQS1#<10> DDRB_SDQS2<10> DDRB_SDQS2#<10> DDRB_SDQS3<10> DDRB_SDQS3#<10> DDRB_SDQS4<10> DDRB_SDQS4#<10> DDRB_SDQS5<10> DDRB_SDQS5#<10> DDRB_SDQS6<10> DDRB_SDQS6#<10> DDRB_SDQS7<10> DDRB_SDQS7#<10>

DDRB_CLK0<10> DDRB_CLK0#<10> DDRB_CLK1<10> DDRB_CLK1#<10>

DDRB_CKE0<10> DDRB_CKE1<10>

DDRB_ODT0<10> DDRB_ODT1<10>

DDRB_SCS0#<10> DDRB_SCS1#<10>

DDRB_SRAS#<10> DDRB_SCAS#<10> DDRB_SWE#<10>

MEM_MB_RST#<10> MEM_MB_EVENT#<10>

DDRB_SMA0 DDRB_SMA1 DDRB_SMA2 DDRB_SMA3 DDRB_SMA4 DDRB_SMA5 DDRB_SMA6 DDRB_SMA7 DDRB_SMA8 DDRB_SMA9 DDRB_SMA10 DDRB_SMA11 DDRB_SMA12 DDRB_SMA13 DDRB_SMA14 DDRB_SMA15

DDRB_SBS0# DDRB_SBS1# DDRB_SBS2#

DDRB_SDM0 DDRB_SDM1 DDRB_SDM2 DDRB_SDM3 DDRB_SDM4 DDRB_SDM5 DDRB_SDM6 DDRB_SDM7

DDRB_SDQS0 DDRB_SDQS0# DDRB_SDQS1 DDRB_SDQS1# DDRB_SDQS2 DDRB_SDQS2# DDRB_SDQS3 DDRB_SDQS3# DDRB_SDQS4 DDRB_SDQS4# DDRB_SDQS5 DDRB_SDQS5# DDRB_SDQS6 DDRB_SDQS6# DDRB_SDQS7 DDRB_SDQS7#

DDRB_CLK0 DDRB_CLK0# DDRB_CLK1 DDRB_CLK1#

DDRB_CKE0 DDRB_CKE1

DDRB_ODT0 DDRB_ODT1

DDRB_SCS0# DDRB_SCS1#

DDRB_SRAS# DDRB_SCAS# DDRB_SWE#

MEM_MB_RST# MEM_MB_EVENT#

D

M28 M27 M24 M25

W26

AF25 AG22 AH18 AD14

AG24 AG25 AG21 AF21 AG17 AG18 AH14 AG14

W27

T27 P24 P25 N27 N26

L26 U26 L27 K27

K25 K24

U27 T28 K28

D14 A18 A22 C25

C15 B15 E18 D18 E22 D22 B26 A26

R26 R27 P27 P28

J26 J27

Y28

V25 Y27

V24 V27 V28

J25 T25

JCPU1C

MEMORY CHANNEL B

MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8 MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15

MB_BANK0 MB_BANK1 MB_BANK2

MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7

MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7

MB_CLK_H0 MB_CLK_L0 MB_CLK_H1 MB_CLK_L1

MB_CKE0 MB_CKE1

MB_ODT0 MB_ODT1

MB_CS_L0 MB_CS_L1

MB_RAS_L MB_CAS_L MB_WE_L

MB_RESET_L MB_EVENT_L

LOTES_ACA-ZIF-109-P12-A_FS1R2

ME@

MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7

MB_DATA8

MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15

MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23

MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31

MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39

MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47

MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55

MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63

A14 B14 D16 E16 B13 C13 B16 A16

C17 B18 B20 A20 E17 B17 B19 C19

C21 B22 C23 A24 D20 B21 E23 B23

E24 B25 B27 D28 B24 D24 D26 C27

AG26 AH26 AF23 AG23 AG27 AF27 AH24 AE24

AE22 AH22 AE20 AH20 AD23 AD22 AD21 AD20

AF19 AE18 AE16 AH16 AG20 AG19 AF17 AD16

AG15 AD15 AG13 AD13 AG16 AF15 AE14 AF13

DDRB_SDQ0 DDRB_SDQ1 DDRB_SDQ2 DDRB_SDQ3 DDRB_SDQ4 DDRB_SDQ5 DDRB_SDQ6 DDRB_SDQ7

DDRB_SDQ8 DDRB_SDQ9 DDRB_SDQ10 DDRB_SDQ11 DDRB_SDQ12 DDRB_SDQ13 DDRB_SDQ14 DDRB_SDQ15

DDRB_SDQ16 DDRB_SDQ17 DDRB_SDQ18 DDRB_SDQ19 DDRB_SDQ20 DDRB_SDQ21 DDRB_SDQ22 DDRB_SDQ23

DDRB_SDQ24 DDRB_SDQ25 DDRB_SDQ26 DDRB_SDQ27 DDRB_SDQ28 DDRB_SDQ29 DDRB_SDQ30 DDRB_SDQ31

DDRB_SDQ32 DDRB_SDQ33 DDRB_SDQ34 DDRB_SDQ35 DDRB_SDQ36 DDRB_SDQ37 DDRB_SDQ38 DDRB_SDQ39

DDRB_SDQ40 DDRB_SDQ41 DDRB_SDQ42 DDRB_SDQ43 DDRB_SDQ44 DDRB_SDQ45 DDRB_SDQ46 DDRB_SDQ47

DDRB_SDQ48 DDRB_SDQ49 DDRB_SDQ50 DDRB_SDQ51 DDRB_SDQ52 DDRB_SDQ53 DDRB_SDQ54 DDRB_SDQ55

DDRB_SDQ56 DDRB_SDQ57 DDRB_SDQ58 DDRB_SDQ59 DDRB_SDQ60 DDRB_SDQ61 DDRB_SDQ62 DDRB_SDQ63

E

DDRB_SDQ[63..0] <10>

EVENT# pull high 0.75V reference voltage

+1.5V_APU

4 4

1 2

R5 1K_0402_5%R5 1K_0402_5%

1 2

R6 1K_0402_5%R6 1K_0402_5%

MEM_MA_EVENT#

MEM_MB_EVENT# +MEM_VREF

A

R4

1K_0402_1%

R7

1K_0402_1%

+1.5V_APU

1 2

B

1

C45

C45 1000P_0402_50V7K

1000P_0402_50V7K

2

15mil

2

C46

0.1U_0402_16V7K

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/11/13 2013/11/12

Compal Secret Data

Deciphered Date

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Title

Size Document Number Rev

Compal Electronics, Inc.

FS1r2 DDRIII Memory I/F

VALGD MB L

6 57Friday, April 12, 2013

E

0.1

A

1 2

DP0_TXP0_C<26> DP0_TXN0_C<26>

1 1

ML_VGA_TXP0<12> ML_VGA_TXN0<12>

ML_VGA_TXP1<12> ML_VGA_TXN1<12>

ML_VGA_TXP2<12> ML_VGA_TXN2<12>

ML_VGA_TXP3<12> ML_VGA_TXN3<12>

HDMI_TX2+_CK<29> HDMI_TX2-_CK<29>

HDMI_TX1+_CK<29> HDMI_TX1-_CK<29>

HDMI_TX0+_CK<29> HDMI_TX0-_CK<29>

HDMI_CLK+_CK<29> HDMI_CLK-_CK<29>

C61~C68 Close Connector

APU_SVC<48>

12

C465100P_0402_50V8J

APU_SIC APU_SID ALERT_L ALLOW_STOP

ALLOW_STOP

APU_RST#

APU_PWRGD

APU_SVT

APU_SVC

APU_SVD

A

APU_SVD<48>

APU_SVT<48>

APU_PWRGD

2 2

APU_RST#< 11> APU_PWRGD<11,48>

ESD request

@ESD@

The VDDIO voltage source provides power to the DDR3 output drivers and other

3 3

miscellaneous functions within the processor. VDDIO_SENSE is internally tied to the processor substrate and is used for sensing the memory controller and interface voltage level at the processor. VDDIO_SENSE can be routed as a single-ended signal, or it can be routed with VSS_SENSE as its complement.

+1.5V_APU

RP9

SD309100180RP9

SD309100180 1 8 2 7 3 6 4 5

+1.5VS

4 4

1K_0804_8P4R_5%

1 2

R348 1K_0402_5%DEBUG@R348 1K_0402_5%DEBUG@

1 2

R52 300_0402_5%R52 300_0402_5%

1 2

R56 300_0402_5%R56 300_0402_5%

1 2

R40 1K_0402_5%

DEBUG@

1 2

R35 1K_0402_5%

DEBUG@

1 2

R38 1K_0402_5%

DEBUG@

C47 0.1U_0402_16V7KLVDS@ C47 0.1U_0402_16V7KLVDS@

1 2

C49 0.1U_0402_16V7KLVDS@ C49 0.1U_0402_16V7KLVDS@

Place near APU

1 2

C53 0.1U_0402_16V7KC53 0.1U_0402 _16V7K

1 2

C54 0.1U_0402_16V7KC54 0.1U_0402 _16V7K

1 2

C55 0.1U_0402_16V7KC55 0.1U_0402 _16V7K

1 2

C56 0.1U_0402_16V7KC56 0.1U_0402 _16V7K

1 2

C57 0.1U_0402_16V7KC57 0.1U_0402 _16V7K

1 2

C58 0.1U_0402_16V7KC58 0.1U_0402 _16V7K

1 2

C59 0.1U_0402_16V7KC59 0.1U_0402 _16V7K

1 2

C60 0.1U_0402_16V7KC60 0.1U_0402 _16V7K

C61 0.1U_0402_16V7KC61 0.1U_0402_16V7K C62 0.1U_0402_16V7KC62 0.1U_0402_16V7K

C63 0.1U_0402_16V7KC63 0.1U_0402_16V7K C64 0.1U_0402_16V7KC64 0.1U_0402_16V7K

C65 0.1U_0402_16V7KC65 0.1U_0402_16V7K C66 0.1U_0402_16V7KC66 0.1U_0402_16V7K

C67 0.1U_0402_16V7KC67 0.1U_0402_16V7K C68 0.1U_0402_16V7KC68 0.1U_0402_16V7K

RH140 0_0402_1% SHORT PAD@RH140 0_0402_1% SHORT PAD@ RH141 0_0402_1% SHORT PAD@RH141 0_0402_1% SHORT PAD@

Route as differential w

1 2 1 2

APU_CLK<11> APU_CLK#<11>

APU_DISP_CLK<11> APU_DISP_CLK#<11>

1 2 1 2

APU_PROCHOT#<11>

APU_VDD_SEN_L<48>

APU_VDDNB_SEN_H<48>

APU_VDD_SEN_H<48>

ith APU_VDD_SEN_L

APU_SIC APU_SID

APU_THERMTRIP# ALERT_L

APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBRDY APU_DBREQ#

CPU TSI interface level shift

DP0_TXP0DP0_TXP0 DP0_TXN0DP0_TXN0

DP1_TXP0 DP1_TXN0

DP1_TXP1 DP1_TXN1

DP1_TXP2 DP1_TXN2

DP1_TXP3 DP1_TXN3

DP2_TXP0 DP2_TXN0

DP2_TXP1 DP2_TXN1

DP2_TXP2 DP2_TXN2

DP2_TXP3 DP2_TXN3

+3VS

APU_SID

APU_SIC

B

L3

DP0_TXP0

L2

DP0_TXN0

K5

DP0_TXP1

K4

DP0_TXN1

K2

DP0_TXP2

K1

DP0_TXN2

J3

DP0_TXP3

J2

DP0_TXN3

H5

DP1_TXP0

H4

DP1_TXN0

H2

DP1_TXP1

H1

DP1_TXN1

G3

DP1_TXP2

G2

DP1_TXN2

F2

DP1_TXP3

F1

DP1_TXN3

L9

DP2_TXP0

L8

DP2_TXN0

L5

DP2_TXP1

L6

DP2_TXN1

K8

DP2_TXP2

K7

DP2_TXN2

J6

DP2_TXP3

J5

DP2_TXN3

AE11

CLKIN_H

AD11

CLKIN_L

AB11

DISP_CLKIN_H

AA11

DISP_CLKIN_L

B3

SVC

A3

SVD

C3

SVT

AG12

SIC

AH12

SID

AF10

RESET_L

AB12

PWROK

AC10

PROCHOT_L

AE12

THERMTRIP_L

AF12

ALERT_L

H10

TDI

J10

TDO

F10

TCK

G10

TMS

F9

TRST_L

G9

DBRDY

H9

DBREQ_L

B4

VSS_SENSE

C5

VDDP_SENSE

A4

VDDNB_SENSE

A5

VDDIO_SENSE

C4

VDD_SENSE

B5

VDDR_SENSE

ME@

1 2

R33

31.6K_0402_1%

B

JCPU1D

ANALOG/DISPLAY/MISC

LVDS

DISPLAY PORT 0

To FCH

DISPLAY PORT MISC.

HDMI

DISPLAY PORT 2 DISPLAY P ORT 1

TEST

CTRL SE R. CLK

JTAG

SENSE

LOTES_ACA-ZIF-109-P12-A_FS1R2

1 2

C69 0.1U_0402_16V4ZC69 0.1U_0402_16V4Z

1 2

R34

30K_0402_1%

G

2

Q3

13

D

S

D

S

BSH111 1N_SOT23-3

G

2

Q6

13

D

S

D

S

BSH111 1N_SOT23-3

DP0_AUXP DP0_AUXN

DP1_AUXP DP1_AUXN

DP2_AUXP DP2_AUXN

DP3_AUXP DP3_AUXN

DP4_AUXP DP4_AUXN

DP5_AUXP DP5_AUXN

DP0_HPD DP1_HPD DP2_HPD DP3_HPD DP4_HPD DP5_HPD

DP_BLON

DP_DIGON

DP_VARY_BL

DP_AUX_ZVSS

TEST10 TEST14 TEST15 TEST16 TEST17 TEST18 TEST19 TEST20 TEST24

TEST25_H

TEST25_L

TEST28_H

TEST28_L

TEST30_H

TEST30_L

TEST31

TEST32_H

TEST32_L

TEST35

DMAACTIVE_L

RSVD1 RSVD2 RSVD3

RSVD

RSVD4

C

D1

DP0_AUXP

D2

DP0_AUXN

E1

ML_VGA_AUXP

E2

ML_VGA_AUXN

D5 D6

E5 E6

F5 F6

G5 G6

D3 E3 D7 E7 F7 G7

C6 B6 A6

C1

DP_AUX_ZVSS

AD12

TEST6

M18

TEST9

N18 F11 G11 H11 J11 F12

APU_TEST18

G12

APU_TEST19

J12

APU_TEST20

H12

APU_TEST24

AE10

TEST25_H

AD10

TEST25_L

L10 M10 P19 R19 K22

APU_TEST31

T19 N19 AA12

APU_TEST35

W10

FS1R2

AC12

P18

TEST4

R18

TEST5

Y10 AA10 Y12 K21

BSH111, the Vgs is: min = 0.4V Max = 1.3V

EC_SMB_DA2_SUS <36>

EC_SMB_CK2_SUS <36>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

1 2

C48 0.1U_0402_16V7K LVDS@C48 0.1U_0402_16V7K LVDS@

1 2

C50 0.1U_0402_16V7K LVDS@C50 0.1U_0402_16V7K LVDS@

1 2

R15 150_0402_1%R15 150_0402_1%

T1

T1 T2

T2 T3

T3 T4

T4 T5

T5 T6

T6

R21 510_0402_1%R21 510_0402_1% R25 510_0402_1%R25 510_0402_1%

TEST POINT@

T7

TEST POINT@

T8

R27 39.2_0402_1%R27 39.2_0402_1%

1 2

R29 300_0402_5%R29 300_0402_5%

R30 300_0402_5%DEBUG@R30 300_0402_5%DEBUG@ R32 10K_0402_5%R32 10K_0402_5%

TEST POINT@

T9

TEST POINT@

T10

1 2

C51 0.1U_0402_16V7KC51 0.1U_0402_16V7K

1 2

C52 0.1U_0402_16V7KC52 0.1U_0402_16V7K

DP0_HPD <26> FCH_CRT_HPD <12> TMDS_B_HPD# <29>

DP_INT_PWM <26>

TEST POINT@

TEST POINT@ TEST POINT@

1K_0804_8P4R_5%

SD309100180

RP3

1 8 2 7 3 6 4 5 1 2 1 2

1 2

1 2 1 2

ALLOW_STOP <11>

TEST POINT@ TEST POINT@

TEST POINT@

To EC

2012/11/13 2013/11/12

C

HDMICLK_NB <29> HDMIDAT_NB <29>

+1.2VS

+1.5V_APU

+3VALW

Compal Secret Data

Deciphered Date

To HDMI

RP1

10K_0804_8P4R_5%

D

DP0_AUXP_C <26 > DP0_AUXN_C <26>

ML_VGA_AUXP_C <12> ML_VGA_AUXN_C <12>

Asserted as an input to force the processor into the HTC-active state

APU_PROCHOT#

THERMTRIP shutdown temperature: 125 degree

1K_0402_5%

APU_THERMTRIP#

+1.5V

APU_TRST#

18 27 36 45

D

To LVDS Translater

To FCH

+1.5V_APU

R12

1K_0402_5%

1 2

+1.5V_APU

12

R23

1 2

B

2

E

3 1

R23 10K_0402_5%

10K_0402_5%

Q2

C

R22

MMBT3904_NL_SOT23-3

11/14 Change net name

HDT Debug conn

JHDT1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

SAMTE_ASP-136446-07-B

ME@

Title

Size Document Number Rev

Custom

Date: Sheet of

If not used, pins are left unconnected (DG ref.) 20101111

ML_VGA_AUXP

ML_VGA_AUXN

DP0_AUXP

DP0_AUXN

1 2

R45 0_0402_1%

SHORT PAD@

Indicates to the FCH that a thermal trip has occurred. Its assertion will cause the FCH to transition the system to S5 immediately

1 2

R28 0_0402_1%

SHORT PAD@

SIT: For ESD requirement

+1.5V

Close to Header

RP2

1 8 2 7 3 6 4 5

1K_0804_8P4R_5%

SD309100180

1 2

R596 1K_0402_5%R596 1K_0402_5%

2

APU_TCK

4

APU_TMS

6

APU_TDI

8

APU_TDO

10

APU_PWRGD

12

APU_RST#

14

APU_DBRDY

16

APU_DBREQ#

18

APU_TEST19

20

APU_TEST18

Compal Electronics, Inc.

FS1r2 Display/MISC/HDT

E

H_PROCHOT# <36,48>

1

C438

ESD@

1000P_0402_50V7K

2

APU_DBREQ#

E

12

H_THERMTRIP# <13>

APU_TDI APU_TMS APU_TCK APU_TRST#

7 57Friday, April 12, 2013

R8 1.8K_0402_5%R8 1.8K_0402_5%

R9 1.8K_0402_5%R9 1.8K_0402_5%

R10 1.8K_0402_5%R10 1.8K_0402_5%

R11 1.8K_0402_5%R11 1.8K_0402_5%

VALGD MB L

0.1

A

Power Name

VDD

APU_CORE

+

VDDNB +APU_CORE_NB

VDDIO +1.5V

VDDP / VDDR +1.2VS

VDDA

1 1

+2.5VS

2 2

3 3

Consumption

5A / 3.5A

VDDP decoupling

180P_0402_50V8J

C107

C106

1

2

60A

29A

3.2A

0.5A

180P_0402_50V8J

C108

0.22U_0402_6.3V6K

1

2

+APU_CORE_NB

+1.2VS

C109

0.22U_0402_6.3V6K

C109

0.22U_0402_6.3V6K

1

2

+1.5V_APU

+APU_CORE

F8

VDD_1

H6

VDD_2

J1

VDD_3

J14

VDD_4

P6

VDD_5

P10

VDD_6

J16

VDD_7

J18

VDD_8

J9

VDD_9

K19

VDD_10

K3

VDD_11

K17

VDD_12

M3

VDD_13

K6

VDD_14

V10

VDD_15

V18

VDD_16

V3

VDD_17

F3

VDD_18

L18

VDD_19

V6

VDD_20

W1

VDD_21

T18

VDD_22

Y14

VDD_23

AA1

VDD_24

AB6

VDD_25

AC1

VDD_26

R1

VDD_27

P3

VDD_28

K10

VDD_29

H3

VDD_30

M19

VDD_31

C8

VDDNB_1

D10

VDDNB_2

B8

VDDNB_3

B12

VDDNB_4

C9

VDDNB_5

A9

VDDNB_6

A10

VDDNB_7

A8

VDDNB_8

A11

VDDNB_9

E10

VDDNB_10

E11

VDDNB_11

C10

VDDNB_12

H26

VDDIO_1

K20

VDDIO_2

J28

VDDIO_3

K23

VDDIO_4

K26

VDDIO_5

L22

VDDIO_6

L25

VDDIO_7

L28

VDDIO_8

M20

VDDIO_9

M23

VDDIO_10

M26

VDDIO_11

N22

VDDIO_12

N25

VDDIO_13

N28

VDDIO_14

P20

VDDIO_15

P23

VDDIO_16

P26

VDDIO_17

AA28

VDDIO_18

AH6

VDDP_1

AH5

VDDP_2

AH4

VDDP_3

AH3

VDDP_4

AH7

VDDP_5

AB10

VDDA

LOTES_ACA-ZIF-109-P12-A_FS1R2

ME@

JCPU1E

VDD_32 VDD_33 VDD_34 VDD_35 VDD_36 VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43 VDD_44 VDD_45 VDD_46 VDD_47 VDD_48 VDD_49 VDD_50 VDD_51 VDD_52 VDD_53 VDD_54 VDD_55 VDD_56 VDD_57 VDD_58 VDD_59 VDD_60 VDD_61 VDD_62

VDDNB_13 VDDNB_14 VDDNB_15 VDDNB_16 VDDNB_17 VDDNB_18 VDDNB_19 VDDNB_20 VDDNB_21 VDDNB_22 VDDNB_23

VDDNB_CAP_1 VDDNB_CAP_2

VDDIO_19 VDDIO_20 VDDIO_21 VDDIO_22 VDDIO_23 VDDIO_24 VDDIO_25 VDDIO_26 VDDIO_27 VDDIO_28 VDDIO_29 VDDIO_30 VDDIO_31 VDDIO_32 VDDIO_33 VDDIO_34 VDDIO_35 VDDIO_36

VDDR_1 VDDR_2 VDDR_3 VDDR_4

B

+APU_CORE

R11 T10 H8 G1 U11 W11 W13 W15 W17 W19 AB3 AD3 AD6 AE1 L1 Y6 M6 N11 N1 T3 T6 U19 U1 Y16 Y18 Y3 D4 F4 AF6 AF3 L11

C11 C12 D9 D8 D12 D11 B11 A12 B10 E12 B9

K13 K12

T23 T26 U22 U25 U28 Y26 T20 R28 R25 R22 V20 V23 V26 W22 W25 W28 Y24 G28

AG10 AH8 AH9 AH10

+APU_CORE_NB

+1.5V_APU

C110

180P_0402_50V8J

C110

180P_0402_50V8J

1

2

+APU_CORE

C70

0.22U_0402_6.3V6K

C70

0.22U_0402_6.3V6K

1

2

+APU_CORE_NB

C77

0.22U_0402_6.3V6K

C77

0.22U_0402_6.3V6K

1

2

+1.5V_APU

+VDDNB_CAP

C99

22U_0603_6.3V6M

C99

22U_0603_6.3V6M

C100

22U_0603_6.3V6M

C100

22U_0603_6.3V6M

C105

1

2

Northbridge Power Pins for Remote Decoupling

C111

180P_0402_50V8J

C111

180P_0402_50V8J

C112

1000P_0402_50V7K

C112

1000P_0402_50V7K

1

2

C

C71

0.01U_0402_16V7K

C71

0.01U_0402_16V7K

C76

0.01U_0402_16V7K

C76

C75

0.22U_0402_6.3V6K

C75

0.22U_0402_6.3V6K

1

2

C78

0.22U_0402_6.3V6K

C78

0.22U_0402_6.3V6K

C79

180P_0402_50V8J

C79

180P_0402_50V8J

1

2

0.01U_0402_16V7K

C73

180P_0402_50V8J

C73

C72

0.01U_0402_16V7K

C72

0.01U_0402_16V7K

1

2

C80

180P_0402_50V8J

C80

180P_0402_50V8J

1

2

180P_0402_50V8J

C74

180P_0402_50V8J

C74

1

2

C81

180P_0402_50V8J

C81

180P_0402_50V8J

1

2

180P_0402_50V8J

1

2

(330uF_6.3V_4.2L_ESR17m)*1=(SF000002Z00)

4.7U_0603_6.3V6K

C85

22U_0603_6.3V6M

C85

22U_0603_6.3V6M

C84

22U_0603_6.3V6M

C84

22U_0603_6.3V6M

C83

22U_0603_6.3V6M

C83

22U_0603_6.3V6M

1

2

180P_0402_50V8J

1

2

4.7U_0603_6.3V6K

C86

22U_0603_6.3V6M

C86

22U_0603_6.3V6M

C88

C87

1

2

VDDR decoupling

+1.2VS

C117

0.22U_0402_6.3V6K

C117

0.22U_0402_6.3V6K

C116

0.22U_0402_6.3V6K

C116

0.22U_0402_6.3V6K

1

2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K C90

C90

C89

1

2

C92

0.22U_0402_6.3V6K

C92

0.22U_0402_6.3V6K

C91

0.22U_0402_6.3V6K

C91

0.22U_0402_6.3V6K

C93

1

2

+1.5V

C101

0.22U_0402_6.3V6K

C101

0.22U_0402_6.3V6K

1

2

+1.5V +1.5V_APU

1

2

across VDDIO an d VSS split

C102

0.22U_0402_6.3V6K

C102

0.22U_0402_6.3V6K

C104

180P_0402_50V8J

C104

180P_0402_50V8J

1

2

SIT:Need Short

D

C94

0.22U_0402_6.3V6K

C94

0.22U_0402_6.3V6K

C95

0.22U_0402_6.3V6K

1

2

C114

180P_0402_50V8J

C114

180P_0402_50V8J

1

2

JUMP@

J2

1 2

PAD-OPEN 4x4m

Need Short

JUMP@

J3

1 2

PAD-OPEN 4x4m

E

JCPU1F

J20

VSS_1

L4

VSS_2

R7

VSS_3

W18

VSS_4

A15

VSS_5

AB17

VSS_6

AC22

VSS_7

AE21

VSS_8

AF24

VSS_9

AH23

VSS_10

AH25

VSS_11

B7

VSS_12

C14

VSS_13

C16

VSS_14

C2

VSS_15

C20

VSS_16

C22

VSS_17

C24

VSS_18

C26

VSS_19

C28

VSS_20

D13

VSS_21

D15

VSS_22

D17

VSS_23

D19

VSS_24

D23

VSS_25

D25

VSS_26

D27

VSS_27

E4

VSS_28

E9

VSS_29

F14

VSS_30

F16

VSS_31

F18

VSS_32

F20

VSS_33

F22

VSS_34

C98

330U_2.5V_M+C98

C97

180P_0402_50V8J

C97

0.22U_0402_6.3V6K

180P_0402_50V8J

C96

0.22U_0402_6.3V6K

C96

0.22U_0402_6.3V6K

1

2

330U_2.5V_M

1

+

2

F26

VSS_35

F28

VSS_36

G13

VSS_37

G15

VSS_38

G17

VSS_39

G19

VSS_40

G21

VSS_41

G23

VSS_42

G25

VSS_43

G4

VSS_44

J22

VSS_45

J24

VSS_46

J4

VSS_47

J7

VSS_48

K11

VSS_49

K14

VSS_50

K9

VSS_51

AC11

VSS_52

L19

VSS_53

L7

VSS_54

M11

VSS_55

AF11

VSS_56

V19

VSS_57

V9

VSS_58

W16

VSS_59

W4

VSS_60

W7

VSS_61

Y11

VSS_62

Y20

VSS_63

Y22

VSS_64

Y9

VSS_65

A17

VSS_66

A13

VSS_67

K16

VSS_68

F24

VSS_69

G8

VSS_70

H7

VSS_71

J8

VSS_72

LOTES_ACA-ZIF-109-P12-A_FS1R2

ME@

VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98

VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143

A19 A21 A23 A25 A7 AA4 AA7 AB13 AB15 AB19 AB21 AB23 AB25 AB27 AB9 AC14 AC16 AC18 AC20 AC24 AC26 AC28 AC4 AC7 AD9 AE13 AE15 AE17 M9 N10 N4 N7 R10 R4 T11 T9 U10 U18 U4 U7 V11 AE19 AE23 AE25 AE27 AE4 AE7 AF14 AF16 AF18 AF20 AF22 AF26 AF28 AF9 AG4 AG7 AH13 AH15 AH17 AH19 AH21 P9 C18 D21 W14 P11 C7 E8 K18 W12

Demo Board Capacitor

APU_CORE 22uF x 10

0.22uF x 2

0.01uF x 3 180pF x 2

CORE_NB 22uF x 2 10uF x 1

0.22uF x 2 180pF x 3

CORE_NB_CAP 22uF x 2 180pF x 1

VDDIO_SUS (CPU side) 22uF x 4

4.7uF x 4

0.22uF x 6 +2(split) 180pF x 1 + 2(split)

4 4

+2.5VS

L1

L1 FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

12

C118

3300P_0402_50V7K

C118

3300P_0402_50V7K

C119

0.22U_0402_6.3V6K

C119

0.22U_0402_6.3V6K

1

12

2

Check

A

40mil

+VDDA

C120

4.7U_0402_6.3V6M

C120

4.7U_0402_6.3V6M

1

2

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/11/13 2013/11/12

Compal Secret Data

Deciphered Date

D

VDDP 0

.22uF x 2

180pF x 2

VDDR

0.22uF x 2 1nF x 4 180pF x 2

Title

Size Document Number Rev

Custom

Date: Sheet of

VDDA

4.7uF x 1

0.22uF x 1

3.3nF x 1

Compal Electronics, Inc.

FS1r2 PWR/GND

VALGD MB L

E

VDDIO_SUS (DIMM x2) 100uF x 2

0.1uF x 12

8 57Friday, April 12, 2013

0.1

A

B

C

D

E

+VREF_DQ

DDRA_SDQ0 DDRA_SDQ1

DDRA_SDM0

DDRA_SDQ2

1 1

DDRA_SDQS1#<6> DDRA_SDQS1<6>

DDRA_SDQS2#<6> DDRA_SDQS2<6>

DDRA_CKE0<6>

2 2

3 3

+3VS

4 4

2.2U_0603_6.3V6K

DDRA_SBS2#<6>

DDRA_CLK0<6> DDRA_CLK0#<6>

DDRA_SBS0#<6>

DDRA_SWE#<6>

DDRA_SCAS#<6> DDRA_ODT0 <6>

DDRA_SCS1#<6>

DDRA_SDQS4#<6> DDRA_SDQS4<6>

DDRA_SDQS6#<6> DDRA_SDQS6<6>

1

2

1

C132

0.1U_0402_16V4Z

2

C131

DDRA_SDQ3

DDRA_SDQ8 DDRA_SDQ9

DDRA_SDQS1# DDRA_SDQS1

DDRA_SDQ10 DDRA_SDQ11

DDRA_SDQ16 DDRA_SDQ17

DDRA_SDQS2# DDRA_SDQS2

DDRA_SDQ18 DDRA_SDQ19

DDRA_SDQ24 DDRA_SDQ25

DDRA_SDM3

DDRA_SDQ26 DDRA_SDQ27

DDRA_CKE0

DDRA_SBS2#

DDRA_SMA12 DDRA_SMA9

DDRA_SMA8 DDRA_SMA5

DDRA_SMA3 DDRA_SMA1

DDRA_CLK0 DDRA_CLK0#

DDRA_SMA10 DDRA_SBS0#

DDRA_SWE# DDRA_SCAS# DDRA_ODT0

DDRA_SMA13 DDRA_SCS1#

DDRA_SDQ32 DDRA_SDQ33

DDRA_SDQS4# DDRA_SDQS4

DDRA_SDQ34 DDRA_SDQ35

DDRA_SDQ40 DDRA_SDQ41

DDRA_SDM5

DDRA_SDQ42 DDRA_SDQ43

DDRA_SDQ48 DDRA_SDQ49

DDRA_SDQS6# DDRA_SDQS6

DDRA_SDQ50 DDRA_SDQ51

DDRA_SDQ56 DDRA_SDQ57

DDRA_SDM7

DDRA_SDQ58 DDRA_SDQ59

+1.5V +1.5V

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DDRA_SA0

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

VSS3

DQS#0

DQS0

VSS6

VSS8 DQ12 DQ13

VSS10

DQ14 DQ15

DQ20 DQ21

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

VSS31

DQ38 DQ39

VSS33

DQ44

DQ45 VSS35 DQS#5

DQS5

VSS38

DQ46

DQ47 VSS40

DQ52

DQ53 VSS42

VSS43

DQ54

DQ55 VSS45

DQ60

DQ61 VSS47 DQS#7

DQS7

VSS50

DQ62

DQ63 VSS52

EVENT#

VTT2

FOX_AS0A626-U8SN-7F

ME@

DQ4 DQ5

DQ6 DQ7

DM1

DM2

CK1

BA1

NC2

DM4

DM6

SDA SCL

2 4

DDRA_SDQ4

6

DDRA_SDQ5

8 10

DDRA_SDQS0#

12

DDRA_SDQS0

14 16

DDRA_SDQ6

18

DDRA_SDQ7

20 22

DDRA_SDQ12

24

DDRA_SDQ13

26 28

DDRA_SDM1

30

MEM_MA_RST#

32 34

DDRA_SDQ14

36

DDRA_SDQ15

38 40

DDRA_SDQ20

42

DDRA_SDQ21

44 46

DDRA_SDM2

48 50

DDRA_SDQ22

52

DDRA_SDQ23

54 56

DDRA_SDQ28

58

DDRA_SDQ29

60 62

DDRA_SDQS3#

64

DDRA_SDQS3

66 68

DDRA_SDQ30

70

DDRA_SDQ31

72

74

DDRA_CKE1

76 78

A15 A14

A11

A7

A6 A4

A2 A0

S0#

G2

DDRA_SMA15

80

DDRA_SMA14

82 84

DDRA_SMA11

86

DDRA_SMA7

88 90

DDRA_SMA6

92

DDRA_SMA4

94 96

DDRA_SMA2

98

DDRA_SMA0

100 102

DDRA_CLK1

104

DDRA_CLK1#

106 108

DDRA_SBS1#

110

DDRA_SRAS#

112 114

DDRA_SCS0#

116 118 120

DDRA_ODT1

122 124 126 128 130

DDRA_SDQ36

132

DDRA_SDQ37

134 136

DDRA_SDM4

138 140

DDRA_SDQ38

142

DDRA_SDQ39

144 146

DDRA_SDQ44

148

DDRA_SDQ45

150 152

DDRA_SDQS5#

154

DDRA_SDQS5

156 158

DDRA_SDQ46

160

DDRA_SDQ47

162 164

DDRA_SDQ52

166

DDRA_SDQ53

168 170

DDRA_SDM6

172 174

DDRA_SDQ54

176

DDRA_SDQ55

178 180

DDRA_SDQ60

182

DDRA_SDQ61

184 186

DDRA_SDQS7#

188

DDRA_SDQS7

190 192

DDRA_SDQ62

194

DDRA_SDQ63

196 198

MEM_MA_EVENT#

200 202 204

206

+0.75VS

DDRA_SDQS0# <6> DDRA_SDQS0 <6 >

MEM_MA_RST# <6>

DDRA_SDQS3# <6> DDRA_SDQS3 <6 >

DDRA_CKE1 <6>

DDRA_CLK1 <6> DDRA_CLK1# <6>

DDRA_SBS1# <6> DDRA_SRAS# <6>

DDRA_SCS0# <6>

DDRA_ODT1 <6>

+VREF_CA

DDRA_SDQS5# < 6> DDRA_SDQS5 <6 >

DDRA_SDQS7# < 6> DDRA_SDQS7 <6 >

MEM_MA_EVENT# <6>

FCH_SDATA0 <10,13,30> FCH_SCLK0 <10 ,13,30>

DDRA_SDQ[0..63]

DDRA_SDM[0..7]

DDRA_SMA[0..15]

+1.5V

2

1

0.1U_0402_16V4Z

+VREF_DQ

DDRA_SDQ[0..63] <6>

DDRA_SDM[0..7] <6>

DDRA_SMA[0..15] <6>

Place near DIMM1

0.1U_0402_16V4Z

2

C122

C121

1

+VREF_DQ +VREF_CA

1

C127

2

0.1U_0402_16V4Z

2

C123

1

0.1U_0402_16V4Z

1

C128

2

1000P_0402_50V7K

0.1U_0402_16V4Z

2

C124

1

+1.5V

R65

R65 1K_0402_1%

1K_0402_1%

1 2

R67

R67 1K_0402_1%

1K_0402_1%

1 2

2

C125

1

0.1U_0402_16V4Z

2

C126

1

+VREF_CA

+1.5V

R66

R66 1K_0402_1%

1K_0402_1%

15mil15mil

1

C129

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z 1000P_0402_50V7K

1000P_0402_50V7K

1 2

1

C130

R68

R68 1K_0402_1%

2

1K_0402_1%

1 2

Security Classification

Issued Date

standard H:8mm

<Address: 00>

A

B

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/11/13 2013/11/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

DDRIII SO-DIMM 1

VALGD MB L

9 57Friday, April 12, 2013

E

0.1

A

B

C

D

E

DQ4 DQ5

VSS3

VSS6

DQ6 DQ7

VSS8

DM1

DM2

CK1

CK1#

BA1

NC2

DM4

DM6

SDA SCL

VTT2

+1.5V+1.5V

2 4

DDRB_SDQ4

6

DDRB_SDQ5

8 10

DDRB_SDQS0#

12

DDRB_SDQS0

14 16

DDRB_SDQ6

18

DDRB_SDQ7

20 22

DDRB_SDQ12

24

DDRB_SDQ13

26 28

DDRB_SDM1

30

MEM_MB_RST#

32 34

DDRB_SDQ14

36

DDRB_SDQ15

38 40

DDRB_SDQ20

42

DDRB_SDQ21

44 46

DDRB_SDM2

48 50

DDRB_SDQ22

52

DDRB_SDQ23

54 56

DDRB_SDQ28

58

DDRB_SDQ29

60 62

DDRB_SDQS3#

64

DDRB_SDQS3

66 68

DDRB_SDQ30

70

DDRB_SDQ31

72

74

DDRB_CKE1

76 78

A15 A14

A11

A7

A6 A4

A2 A0

S0#

G2

DDRB_SMA15

80

DDRB_SMA14

82 84

DDRB_SMA11

86

DDRB_SMA7

88 90

DDRB_SMA6

92

DDRB_SMA4

94 96

DDRB_SMA2

98

DDRB_SMA0

100 102

DDRB_CLK1

104

DDRB_CLK1#

106 108

DDRB_SBS1#

110

DDRB_SRAS#

112 114

DDRB_SCS0#

116

DDRB_ODT0DDRB_SCAS#

118 120

DDRB_ODT1

122 124 126 128 130

DDRB_SDQ36

132

DDRB_SDQ37

134 136

DDRB_SDM4

138 140

DDRB_SDQ38

142

DDRB_SDQ39

144 146

DDRB_SDQ44

148

DDRB_SDQ45

150 152

DDRB_SDQS5#

154

DDRB_SDQS5

156 158

DDRB_SDQ46

160

DDRB_SDQ47

162 164

DDRB_SDQ52

166

DDRB_SDQ53

168 170

DDRB_SDM6

172 174

DDRB_SDQ54

176

DDRB_SDQ55

178 180

DDRB_SDQ60

182

DDRB_SDQ61

184 186

DDRB_SDQS7#

188

DDRB_SDQS7

190 192

DDRB_SDQ62

194

DDRB_SDQ63

196 198

MEM_MB_EVENT#

200 202 204

206

+0.75VS

DDRB_SDQS0# < 6> DDRB_SDQS0 <6 >

MEM_MB_RST# <6>

DDRB_SDQS3# < 6> DDRB_SDQS3 <6 >

DDRB_CKE1 <6>

DDRB_CLK1 < 6> DDRB_CLK1# <6>

DDRB_SBS1# <6> DDRB_SRAS# <6>

DDRB_SCS0# <6> DDRB_ODT0 <6>

DDRB_ODT1 <6>

+VREF_CA

DDRB_SDQS5# < 6> DDRB_SDQS5 <6 >

DDRB_SDQS7# < 6> DDRB_SDQS7 <6 >

MEM_MB_EVENT# <6>

FCH_SDATA0 <13,30,9> FCH_SCLK0 <13 ,30,9>

DDRB_SDQ[0..63]

DDRB_SDM[0..7]

DDRB_SMA[0..15]

DDRB_SDQ[0..63] <6>

DDRB_SDM[0..7] <6>

DDRB_SMA[0..15] <6>

0.1U_0402_16V4Z

C143

0.1U_0402_16V4Z

+VREF_DQ

15mil 1

+VREF_DQ +VREF_CA

1000P_0402_50V7K

0.1U_0402_16V4Z

+1.5V

1

2

C137

1

+0.75VS

2

1

C133

1

2

0.1U_0402_16V4Z

2

C138

1

2

C134

2

C139

1

0.1U_0402_16V4Z

C144

4.7U_0603_6.3V6K

0.1U_0402_16V4Z

2

1

SIT:1/26 change to POLY

+VREF_CA

0.1U_0402_16V4Z

1

2

C140

0.1U_0402_16V4Z

5mil

1000P_0402_50V7K

C135

1

C136

2

Place near DIMM2

0.1U_0402_16V4Z

2

C141

C142

1

+1.5V

1

+

C145

@

220U_D2_2VY_R15M

2

SGA00004L00

C142

1

+VREF_DQ

DDRB_SDQ0 DDRB_SDQ1

DDRB_SDM0

DDRB_SDQ2

1 1

DDRB_SDQS1#<6> DDRB_SDQS1<6>

DDRB_SDQS2#<6> DDRB_SDQS2<6>

DDRB_CKE0<6>

2 2

3 3

4 4

+3VS

DDRB_SBS2#<6>

DDRB_CLK0<6> DDRB_CLK0#<6>

DDRB_SBS0#<6>

DDRB_SWE#<6>

DDRB_SCAS#<6>

DDRB_SCS1#<6>

DDRB_SDQS4#<6> DDRB_SDQS4<6>

DDRB_SDQS6#<6> DDRB_SDQS6<6>

R71 10K_0402_5%R71 10K _0402_5%

1 2

DDRB_SDQ3

DDRB_SDQ8 DDRB_SDQ9

DDRB_SDQS1# DDRB_SDQS1

DDRB_SDQ10 DDRB_SDQ11

DDRB_SDQ16 DDRB_SDQ17

DDRB_SDQS2# DDRB_SDQS2

DDRB_SDQ18 DDRB_SDQ19

DDRB_SDQ24 DDRB_SDQ25

DDRB_SDM3

DDRB_SDQ26 DDRB_SDQ27

DDRB_CKE0

DDRB_SBS2#

DDRB_SMA12 DDRB_SMA9

DDRB_SMA8 DDRB_SMA5

DDRB_SMA3 DDRB_SMA1

DDRB_CLK0 DDRB_CLK0#

DDRB_SMA10 DDRB_SBS0#

DDRB_SWE#

DDRB_SMA13 DDRB_SCS1#

DDRB_SDQ32 DDRB_SDQ33

DDRB_SDQS4# DDRB_SDQS4

DDRB_SDQ34 DDRB_SDQ35

DDRB_SDQ40 DDRB_SDQ41

DDRB_SDM5

DDRB_SDQ42 DDRB_SDQ43

DDRB_SDQ48 DDRB_SDQ49

DDRB_SDQS6# DDRB_SDQS6

DDRB_SDQ50 DDRB_SDQ51

DDRB_SDQ56 DDRB_SDQ57

DDRB_SDM7

DDRB_SDQ58 DDRB_SDQ59

DDRB_SA0

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U4SN-7F

E

@

M

DQS#0

DQS0

DQ12 DQ13

VSS10

DQ14 DQ15

DQ20 DQ21

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

VSS31

DQ38 DQ39

VSS33

DQ44

DQ45 VSS35 DQS#5

DQS5 VSS38

DQ46

DQ47 VSS40

DQ52

DQ53 VSS42

VSS43

DQ54

DQ55 VSS45

DQ60

DQ61 VSS47 DQS#7

DQS7 VSS50

DQ62

DQ63 VSS52

EVENT#

Security Classification

Issued Date

Standard H:4mm

<Address: 01>

A

B

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/11/13 2013/11/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

DDRIII SO-DIMM 2

VALGD MB L

10 57Friday, April 12, 2013

E

0.1

A

APU_PCIE_RST#<16,30,31>

PLT_RST#<36>

1 2

C146150P_0402_50V8J C146150P_0402_50V8J

UMI_RXP0<5> UMI_RXN0<5> UMI_RXP1<5> UMI_RXN1<5> UMI_RXP2<5> UMI_RXN2<5> UMI_RXP3<5>

GCLK_PCH_25MHZ<38>

C157

1 2

10P_0402_50V8J

C160

1 2

10P_0402_50V8J

UMI_RXN3<5>

UMI_TXP0<5> UMI_TXN0<5> UMI_TXP1<5> UMI_TXN1<5> UMI_TXP2<5> UMI_TXN2<5> UMI_TXP3<5> UMI_TXN3<5>

+VDDAN_11_PCIE

CLK_PCIE_VGA<16> CLK_PCIE_VGA#<16>

CLK_PCIE_WLAN1<30> CLK_PCIE_WLAN1#<30>

CLK_PCIE_LAN<31> CLK_PCIE_LAN#<31>

NOGCLK@

1 1

2 2

VGA

WLAN

LAN

3 3

4 4

25MHZ_10PF_X3G025000DC1H

X1

SHORT PAD@

12

0_0402_1%

R92

1 2

C153 0.1U_0402_16V7KC153 0.1U_0402_16V7K

1 2

C147 0.1U_0402_16V7KC147 0.1U_0402_16V7K

1 2

C148 0.1U_0402_16V7KC148 0.1U_0402_16V7K

1 2

C154 0.1U_0402_16V7KC154 0.1U_0402_16V7K

1 2

C149 0.1U_0402_16V7KC149 0.1U_0402_16V7K

1 2

C150 0.1U_0402_16V7KC150 0.1U_0402_16V7K

1 2

C151 0.1U_0402_16V7KC151 0.1U_0402_16V7K

1 2

C152 0.1U_0402_16V7KC152 0.1U_0402_16V7K

+1.1VS_CKVDD

APU

4

1

NOGCLK@

NC

OSC

OSC3NC

2

A

1 2

R74 33_0402_5%R74 33_ 0402_5%

1 2

R75 590_0402_1%R75 590_0402_1%

1 2

R76 2K_0402_1%R76 2K_0402_1%

R77

1 2

2K_0402_1%

APU_DISP_CLK<7>

APU_DISP_CLK#<7>

APU_CLK<7> APU_CLK#<7>

Remove 0 ohm on PVT

1 2

R801 0_0402_5%

GCLK@

25M_X1

R89

R89 1M_0402_5%

1M_0402_5%

NOGCLK@

25M_X2

A_RST#

UMI_RXP0_C UMI_RXN0_C UMI_RXP1_C UMI_RXN1_C UMI_RXP2_C UMI_RXN2_C UMI_RXP3_C UMI_RXN3_C

PCIE_CALRP PCIE_CALRN

CLK_CALRN

25M_X1GCLK_PCH_25MHZ

25M_X2

B

R74/ C146 close to FCH

U1A

AE2

PCIE_RST#

AD5

A_RST#

AE30

UMI_TX0P

AE32

UMI_TX0N

AD33

UMI_TX1P

AD31

UMI_TX1N

AD28

UMI_TX2P

AD29

UMI_TX2N

AC30

UMI_TX3P

AC32

UMI_TX3N

AB33

UMI_RX0P

AB31

UMI_RX0N

AB28

UMI_RX1P

AB29

UMI_RX1N

Y33

UMI_RX2P

Y31

UMI_RX2N

Y28

UMI_RX3P

Y29

UMI_RX3N

AF29

PCIE_CALRP

AF31

PCIE_CALRN

V33

GPP_TX0P

V31

GPP_TX0N

W30

GPP_TX1P

W32

GPP_TX1N

AB26

GPP_TX2P

AB27

GPP_TX2N

AA24

GPP_TX3P

AA23

GPP_TX3N

AA27

GPP_RX0P

AA26

GPP_RX0N

W27

GPP_RX1P

V27

GPP_RX1N

V26

GPP_RX2P

W26

GPP_RX2N

W24

GPP_RX3P

W23

GPP_RX3N

F27

CLK_CALRN

G30

PCIE_RCLKP

G28

PCIE_RCLKN

R26

DISP_CLKP

T26

DISP_CLKN

H33

DISP2_CLKP

H31

DISP2_CLKN

T24

APU_CLKP

T23

APU_CLKN

J30

SLT_GFX_CLKP

K29

SLT_GFX_CLKN

H27

GPP_CLK0P

H28

GPP_CLK0N

J27

GPP_CLK1P

K26

GPP_CLK1N

F33

GPP_CLK2P

F31

GPP_CLK2N

E33

GPP_CLK3P

E31

GPP_CLK3N

M23

GPP_CLK4P

M24

GPP_CLK4N

M27

GPP_CLK5P

M26

GPP_CLK5N

N25

GPP_CLK6P

N26

GPP_CLK6N

R23

GPP_CLK7P

R24

GPP_CLK7N

N27

GPP_CLK8P

R27

GPP_CLK8N

J26

14M_25M_48M_OSC

C31

25M_X1

C33

25M_X2

21807-A13-HUDSON-M3_FCBGA656

SA000066K70

A76M Bolton M3

B

PCI EXPRESS INTERFACES

CLOCK GENERATOR

HUDSON-2

PCI CLKS

PCICLK4/14M_OSC/GPO39

PCI INTERFACE

REQ2#/CLK_REQ8#/GPIO41 REQ3#/CLK_REQ5#/GPIO42

GNT2#/SD_LED/GPO45

GNT3#/CLK_REQ7#/GPIO46

LPCAPUS5 PLUS

LDRQ1#/CLK_REQ6#/GPIO49

PCICLK0 PCICLK1/GPO36 PCICLK2/GPO37 PCICLK3/GPO38

PCIRST#

AD0/GPIO0 AD1/GPIO1 AD2/GPIO2 AD3/GPIO3 AD4/GPIO4 AD5/GPIO5 AD6/GPIO6 AD7/GPIO7 AD8/GPIO8

AD9/GPIO9 AD10/GPIO10 AD11/GPIO11 AD12/GPIO12 AD13/GPIO13 AD14/GPIO14 AD15/GPIO15 AD16/GPIO16 AD17/GPIO17 AD18/GPIO18 AD19/GPIO19 AD20/GPIO20 AD21/GPIO21 AD22/GPIO22 AD23/GPIO23 AD24/GPIO24 AD25/GPIO25 AD26/GPIO26 AD27/GPIO27 AD28/GPIO28 AD29/GPIO29 AD30/GPIO30 AD31/GPIO31

CBE0# CBE1# CBE2# CBE3#

FRAME#

DEVSEL#

IRDY#

TRDY#

PAR

STOP# PERR# SERR#

REQ0#

REQ1#/GPIO40

GNT0#

GNT1#/GPO44

CLKRUN#

LOCK#

INTE#/GPIO32

INTF#/GPIO33 INTG#/GPIO34 INTH#/GPIO35

LPCCLK0

LPCCLK1

LAD0 LAD1 LAD2 LAD3

LFRAME#

LDRQ0#

SERIRQ/GPIO48

DMA_ACTIVE#

PROCHOT#

APU_PG

LDT_STP#

APU_RST#

S5_CORE_EN

RTCCLK

INTRUDER_ALERT#

VDDBT_RTC_G

32K_X1

32K_X2

C

AF3

1 2

AF1 AF5

RF1 0_0402_1 %

AG2

1 2

AF6

1 2

RF2 0_0402_1 %

RF2 0_0402_1 % RF3 0_0402_1 %

RF3 0_0402_1 %

AB5

AJ3 AL5 AG4 AL6 AH3 AJ5 AL1 AN5 AN6 AJ1 AL8 AL3 AM7 AJ6 AK7 AN8 AG9 AM11 AJ10 AL12 AK11 AN12 AG12 AE12 AC12 AE13 AF13 AH13 AH14 AD15 AC15 AE16 AN3 AJ8 AN10 AD12 AG10 AK9 AL10 AF10 AE10 AH1 AM9 AH8 AG15 AG13 AF15 AM17 AD16 AD13 AD21 AK17 AD19 AH9

AF18 AE18 AC16 AD18

B25

D25 D27 C28 A26 A29 A31 B27 AE27 AE19

G25 E28

APU_PROCHOT#_R

E26

APU_PWRGD_R

G26 F26

H7 F1 F3 E6

G2

32K_X1

G4

32K_X2

SHORT PAD@

SHORT PAD@ SHORT PAD@

SHORT PAD@

PCI_AD23 <15> PCI_AD24 <15> PCI_AD25 <15> PCI_AD26 <15> PCI_AD27 <15>

SIT: For EMI Request

EMI@

1 2

R85 33_0402_5%

LPC_CLK1 <15> LPC_AD0 <36> LPC_AD1 <36> LPC_AD2 <36> LPC_AD3 <36> LPC_FRAME# <36>

SERIRQ <36>

1 2

R86 0_0402_5%DEBUG@R86 0_0402_5%DEBUG@

1 2

R73 0_0402_1%

RTC_CLK <15,36>

+RTCBATT_R

PCI_CLK1 <15>

PCI_CLK3 <15> PCI_CLK4 <15>

TEST POINT@

T26

TEST POINT@

T27

SVT: For EMI Request

EMI@

1 2

C163 10P_0402_50V8J

SHORT PAD@

1 2

C530100P_0402_50V8J

@ESD@

W=20mils

1

C158

2

1U_0402_6.3V6K

1 2

R88 510_0402_5%R88 510_0402_5%

Need OPEN

D

CLK_PCI_EC <15,36>

ALLOW_STOP <7> APU_PROCHOT# <7> APU_PWRGD <48,7>

APU_RST# <7>

+RTCBATT

12

CLRP1 SHORT PADS

SHORT PADS

for Clear CMOS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/11/13 2013/11/12

Compal Secret Data

Deciphered Date

D

GCLK@

32K_X1 GCLK_32K

32.768KHZ_12.5PF_CM31532768DZFT

DEBUG@CLRP1

DEBUG@

1 2

R207 0_0402_5%

32K_X1

32K_X2

Close to HUDSON-M2/3

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

FCH PCIE/CLK/PCI/LPC/RTC

12

Y1

NOGCLK@

E

DVT change

C155

12

20P_0402_50V8J

20M_0402_5%

NOGCLK@

C156

20P_0402_50V8J

VALGD MB L

E

GCLK_32K <38>

NOGCLK@

R78

NOGCLK@

11 57Friday, April 12, 2013

0.1

A

1 1

HDD

ODD

2 2

+AVDD_SATA

+3VS

3 3

+3VS

R36 10K_0402_5%R 36 10K_0402_5%

#11/7 without pull up/ down need to confirm o

r check chipset pin internal status

4 4

A

12

SATA_ITX_C_DRX_P0<34> SATA_ITX_C_DRX_N0<34>

SATA_DTX_C_IRX_N0<34> SATA_DTX_C_IRX_P0<34>

SATA_ITX_C_DRX_P1<34> SATA_ITX_C_DRX_N1<34>

SATA_DTX_C_IRX_N1<34> SATA_DTX_C_IRX_P1<34>

12

R1051K_0402_1% R1051K_0402_1%

12

R106931_0402_1% R106931_0402_1%

1 2

R108 10K_0402_5%R108 10K_0402_5%

BT_DISABLE#

BT_DISABLE#<30>

WL_OFF#<30>

ODD_EN<34>

RP4

18 27

GPIO177

36 45

10K_0804_8P4R_5%

B

SATA_CALRP

SATA_CALRN

TEST POINT@

T12

BT_DISABLE# WL_OFF#

ODD_EN

GPIO174

B

U1B

AK19

SATA_TX0P

AM19

SATA_TX0N

AL20

SATA_RX0N

AN20

SATA_RX0P

AN22

SATA_TX1P

AL22

SATA_TX1N

AH20

SATA_RX1N

AJ20

SATA_RX1P

AJ22

SATA_TX2P

AH22

SATA_TX2N

AM23

SATA_RX2N

AK23

SATA_RX2P

AH24

SATA_TX3P

AJ24

SATA_TX3N

AN24

SATA_RX3N

AL24

SATA_RX3P

AL26

SATA_TX4P

AN26

SATA_TX4N

AJ26

SATA_RX4N

AH26

SATA_RX4P

AN29

SATA_TX5P

AL28

SATA_TX5N

AK27

SATA_RX5N

AM27

SATA_RX5P

AL29

NC6

AN31

NC7

AL31

NC8

AL33

NC9

AH33

NC10

AH31

NC11

AJ33

NC12

AJ31

NC13

AF28

SATA_CALRP

AF27

SATA_CALRN

AD22

SATA_ACT#/GPIO67

AF21

SATA_X1

AG21

SATA_X2

AH16

FANOUT0/GPIO52

AM15

FANOUT1/GPIO53

AJ16

FANOUT2/GPIO54

AK15

FANIN0/GPIO56

AN16

FANIN1/GPIO57

AL16

FANIN2/GPIO58

K6

TEMPIN0/GPIO171

K5

TEMPIN1/GPIO172

K3

TEMPIN2/GPIO173

M6

TEMPIN3/TALERT#/GPIO174

21807-A13-HUDSON-M3_FCBGA656

SA000066K70

A76M Bolton M3

HUDSON-2

SERIAL ATA

HW MONITOR

C

Share with EC need pop R245

GBE_COL

GBE_CRS

GBE_MDCK

GBE_MDIO

GBE_RXCLK

GBE_RXD3 GBE_RXD2 GBE_RXD1 GBE_RXD0

GBE_RXERR

GBE_TXCLK

GBE_TXD3 GBE_TXD2 GBE_TXD1 GBE_TXD0

VGA_RED

VGA_GREEN

VGA_BLUE

AUXCAL

NC1 NC2 NC3 NC4 NC5

C

AL14 AN14 AJ12 AH12 AK13 AM13 AH15 AJ14

AC4 AD3 AD9 W10 AB8 AH7 AF7 AE7 AD7 AG8 AD1 AB7 AF9 AG6 AE8 AD8 AB9 AC2 AA7 W9

V6 V5 V3

SPI_CLK_FCH_R

T6 V1

L30

L32

M29

M28 N30

M33 N32

K31

V28 V29

U28

AUXCAL

T31 T33 T29 T28 R32 R30 P29 P28

C29

N2

M3

L2

N4

P1

P3

M1

M5

AG16 AH10 A28 G27 L4

2012/11/13 2013/11/12

SPI_SB_CS0#_R SPI_SO_R

GBE_PHY_INTR

SPI_SO_R SPI_SI_R

SPI_SB_CS0#_R

SPI_WP#

1 2

R107 715_0402_1%R107 715_0402_1%

1 2

R109 100_0402_1%R109 100_0402_1%

GPIO177

1 2

R118 10K_0402_5%

GPIO182

Compal Secret Data

SHORT PAD@

1 2

R97 0_0402_1%

1 2

R98 0_0402_1%

SHORT PAD@

CRT_HSYNC <28> CRT_VSYNC <28>

CRT_DDC_DATA <28> CRT_DDC_CLK <28>

ML_VGA_AUXP_C <7> ML_VGA_AUXN_C <7>

ML_VGA_TXP0 <7> ML_VGA_TXN0 <7> ML_VGA_TXP1 <7> ML_VGA_TXN1 <7> ML_VGA_TXP2 <7> ML_VGA_TXN2 <7> ML_VGA_TXP3 <7> ML_VGA_TXN3 <7>

FCH_CRT_HPD <7>

DEBUG@

Need to enable i nternal pull down to lea ve unconnected

Deciphered Date

SD_CLK/SCLK_2/GPIO73

SD_CMD/SLOAD_2/GPIO74

SD_CD/GPIO75

SD_WP/GPIO76

SD_DATA0/SDATI_2/GPIO77

SD_DATA1/SDATO_2/GPIO78

SD CARDGBE LANSPI ROMVGA DACVGA MAINLINK

SD_DATA2/GPIO79 SD_DATA3/GPIO80

GBE_RXCTL/RXDV

GBE_TXCTL/TXEN

GBE_PHY_PD

GBE_PHY_RST#

GBE_PHY_INTR

SPI_DI/GPIO164

SPI_DO/GPIO163

SPI_CLK/GPIO162

SPI_CS1#/GPIO165

ROM_RST#/SPI_WP#/GPIO161

VGA_HSYNC/GPO68 VGA_VSYNC/GPO69

VGA_DDC_SDA/GPO70 VGA_DDC_SCL/GPO71

VGA_DAC_RSET

AUX_VGA_CH_P AUX_VGA_CH_N

ML_VGA_L0P

ML_VGA_L0N

ML_VGA_L1P

ML_VGA_L1N

ML_VGA_L2P

ML_VGA_L2N

ML_VGA_L3P

ML_VGA_L3N

ML_VGA_HPD/GPIO229

VIN0/GPIO175

VIN1/GPIO176

VIN2/SDATI_1/GPIO177

VIN3/SDATO_1/GPIO178

VIN4/SLOAD_1/GPIO179

VIN5/SCLK_1/GPIO180

VIN6/GBE_STAT3/GPIO181

VIN7/GBE_LED3/GPIO182

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

D

+3VALW

RP5

18

SPI_WP#

27

SPI_HOLD#

36 45

10K_0804_8P4R_5%

1 2

R245

SPI_SB_CS0# SPI_SO_L

SPI_WP#

SPI_SO_L

SPI_SI

SPI_CLK_FCH

SPI_SB_CS0#

GBE_PHY_INTR

SPI_SB_CS0#

10K_0402_5%ShareROM@

U3

1

/CS

2

DO/IO1

3

/WP/IO2

4

GND

W25Q32FVSSIQ_SO8

R125 0_0402_5%

R128 0_0402_5%

R233 0_0402_5%

R238 0_0402_5%

Co-lay EC share ROM

DAC_RED <28 >

DAC_GRN < 28>

DAC_BLU <28>

+VDDAN_11_ML

Module design FCH_CRT_HPD pull up 110K now 10 K

+FCH_VDDAN_33_DAC

12

R11010K_0402_5% R11010K_0402_5%

10K_0804_8P4R_5%

45 36 27

GPIO174

GPIO182

D

18

RP6

RP6 RP8

RP8

18 27 36 45

10K_0804_8P4R_5%

E

4MB SPI ROM

+3VALW

C165

1 2

0.1U_0402_16V4Z

8

VCC

7

/HOLD/IO3

ShareROM@

1 2

ShareROM@

1 2

ShareROM@

1 2

ShareROM@

1 2

ax = 800 mils

M

Title

Size Document Number Rev

Custom

Date: Sheet of

SPI_HOLD#

6

SPI_CLK_FCH

CLK

5

SPI_SI

DI/IO0

FRD#SPI_SO

FWR#SPI_SI

SPI_CLK

FSEL#SPICS#

DAC_RED DAC_GRN DAC_BLU

Compal Electronics, Inc.

FCH SATA/SPI/VGA/HWM/SD

EMI@

1 2

R100 0_0402_5%

1 2

SHORT PAD@

RP23

1 8 2 7 3 6 4 5

150_0804_8P4R_1%

VALGD MB L

22P_0402_50V8J

0_0402_1%

R99

FRD#SPI_SO <36>

FWR#SPI_SI <36>

SPI_CLK <36>

FSEL#SPICS# <36>

E

SPI_CLK_FCH_R

12 57Friday, April 12, 2013

SPI_CLK_FCH

R94

33_0402_5%

@EMI@

SPI_SI_R

C162

12

0.1

A

+3VALW

R127

R127 10K_0402_5%

10K_0402_5%

DEBUG@

1 2

1 1

SVT: For ESD requirement

+3VALW

2 2

+3VALW

R146 10K_0402_5%

R147 100K_0402_5%

3 3

R148 10K_0402_5%

+3VS

R154 2.2K_0402_5%R154 2.2K_0402_5%

R156 2.2K_0402_5%R156 2.2K_0402_5% R158 8.2K_0402_5%R158 8.2K_0402_5% R159 8.2K_0402_5%R159 8.2K_0402_5%

4 4

R164 2.2K_0402_5%R164 2.2K_0402_5%

R165 10K_0402_5%

R168 10K_0402_5%

R169 10K_0402_5%

SYS_RESET#

H_THERMTRIP#

1

C439

ESD@

1000P_0402_50V7K

2

For FCH internal debug use

1 2

R129 2.2K_0402_5%

DEBUG@

1 2

R130 2.2K_0402_5%

DEBUG@

1 2

R131 2.2K_0402_5%

DEBUG@

+3VALW

RP14

18

USB_OC0#

27

USB_OC1#

36

ODD_DETECT#

45

10K_0804_8P4R_5%

1 2

DEBUG@

1 2

DEBUG@

1 2

DEBUG@

1 2

1 2 1 2 1 2

RP10

10K_0804_8P4R_5%

1 2

DEBUG@

1 2

DEBUG@

1 2

DEBUG@

ODD_DA#_FCH

FCH_PCIE_WAKE#

#9/11 need to confirm, Intel using EC

CLKREQ_WLAN#

18 27 36 45

PEG_CLKREQ#_R

A

TEST0

TEST1

TEST2

Module design ODD_DETECT# without pull up need check chipset pin internal status

HDA_BITCLK_AUDIO<35> HDA_SDOUT_AUDIO<35>

HDA_SDIN0<35>

HDA_SYNC_AUDIO<35>

HDA_RST_AUDIO#<35>

H_THERMTRIP#

EC_LID_OUT#

GPIO187 H: 2G Vram L: 1G Vram

FCH_SCLK0

FCH_SDATA0

CLKREQ_LAN#

WD_PWRGD

FCH_SCLK1 FCH_SDATA1 GPIO188

EC_RSMRST#

HDA_BITCLK

HDA_SDIN0

+3VALW+3VALW

12

@

R160

10K_0402_5%

12

PX@

R166

10K_0402_5%

CLK_REQ_VGA#<17>

For RIGHT USB2.0 Port

For LEFT USB3.0 Port

+3VALW

PXS_RST#<16>

PXS_PWREN<18,36,45,51,52>

VGA_GATE#<36>

R161

GPIO189 GPIO190

R167

B

PCIE_RST2 : Reset PCIE device on Hudson2/3

EC_LID_OUT#<36>

PM_SLP_S3#<36> PM_SLP_S5#<36> PBTN_OUT#<36> FCH_PWRGD<36,48>

GATEA20<36>

KBRST#<36> EC_SCI#< 36> EC_SMI#<36>

FCH_PCIE_WAKE#<30>

H_THERMTRIP#<7>

EC_RSMRST#<36>

CLKREQ_LAN#<31>

HDA_SPKR<35> FCH_SCLK0<10,30,9> FCH_SDATA0<10,30,9>

CLKREQ_WLAN#< 30>

VGA_PWRGD<50>

R132 0_0402_5%@R132 0_0402_5%@

R138 33_0402_5%EM I@R138 33_0402_5%EMI@ R140 33_0402_5%R 140 33_0402_5%

R143 33_0402_5%R 143 33_0402_5% R144 33_0402_5%R 144 33_0402_5%

1 2

R364 10K_0402_5%X76@R364 10K_0402_5%X76@

1 2

R365 10K_0402_5%X76@R365 10K_0402_5%X76@

1 2

R366 10K_0402_5%

2

G

BOARD Config.

12

ODD_DETECT#<34>

USB_OC1#<37> USB_OC0#<39>

1 2 1 2

@

SHORT PAD@

PX@

Q70

2N7002K_SOT23-3

12 12

R150 0_0402_5%

R150 0_0402_5% R152 0_0402_5%

R152 0_0402_5%

13

D

S

GPIO189 GPIO190

0 0

1 1

B

FCH_PWRGD

TEST0 TEST1 TEST2

SYS_RESET#

WD_PWRGD

CLKREQ_LAN#

FCH_SCLK0 FCH_SDATA0 FCH_SCLK1 FCH_SDATA1 CLKREQ_WLAN#

PEG_CLKREQ#_R

USB_OC1# USB_OC0#

HDA_BITCLK HDA_SDOUT HDA_SDIN0

HDA_SYNC HDA_RST#

10

01

T13TEST POINT@T13TEST POINT@

GPIO187 GPIO188

GPIO189 GPIO190

Function

PX5

Reserved

DIS

UMA

C

U1D

HUDSON-2

AB6

PCIE_RST2#/PCI_PME#/GEVENT4#

R2

RI#/GEVENT22#

W7

SPI_CS3#/GBE_STAT1/GEVENT21#

T3

SLP_S3#

W2

SLP_S5#

J4

PWR_BTN#

N7

PWR_GOOD

T9

TEST0

T10

TEST1/TMS

V9

TEST2

AE22

GA20IN/GEVENT0#

AG19

KBRST#/GEVENT1#

R9

LPC_PME#/GEVENT3#

C26

LPC_SMI#/GEVENT23#

T5

LPC_PD#/GEVENT5#

U4

SYS_RESET#/GEVENT19#

K1

WAKE#/GEVENT8#

V7

IR_RX1/GEVENT20#

R10

THRMTRIP#/SMBALERT#/GEVEN T2#

AF19

WD_PWRGD

U2

RSMRST#

AG24

CLK_REQ4#/SATA_IS0#/GPIO64

AE24

CLK_REQ3#/SATA_IS1#/GPIO63

AE26

SMARTVOLT1/SATA_IS2#/GPIO50

AF22

CLK_REQ0#/SATA_IS3#/GPIO60

AH17

SATA_IS4#/FANOUT3/GPIO55

AG18

SATA_IS5#/FANIN3/GPIO59

AF24

SPKR/GPIO66

AD26

SCL0/GPIO43

AD25

SDA0/GPIO47

T7

SCL1/GPIO227

R7

SDA1/GPIO228

AG25

CLK_REQ2#/FANIN4/GPIO62

AG22

CLK_REQ1#/FANOUT4/GPIO61

J2

IR_LED#/LLB#/GPIO184

AG26

SMARTVOLT2/SHUTDOWN #/GPIO51

V8

DDR3_RST#/GEVENT7#/VGA_PD

W8

GBE_LED0/GPIO183

Y6

SPI_HOLD#/GBE_LED1/GEVENT9#

V10

GBE_LED2/GEVENT10#

AA8

GBE_STAT0/GEVENT11#

AF25

CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#

M7

BLINK/USB_OC7#/GEVENT18#

R8

USB_OC6#/IR_TX1/GEVENT6#

T1

USB_OC5#/IR_TX0/GEVENT17#

P6

USB_OC4#/IR_RX0/GEVENT16#

F5

USB_OC3#/AC_PRES/TDO/GEVENT15#

P5

USB_OC2#/TCK/GEVENT14#

J7

USB_OC1#/TDI/GEVENT13#

T8

USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT1 2#

AB3

AZ_BITCLK

AB1

AZ_SDOUT

AA2

AZ_SDIN0/GPIO167

Y5

AZ_SDIN1/GPIO168

Y3

AZ_SDIN2/GPIO169

Y1

AZ_SDIN3/GPIO170

AD6

AZ_SYNC

AE4

AZ_RST#

K19

PS2_DAT/SDA4/GPIO187

J19

PS2_CLK/CEC/SCL4/GPIO188

J21

SPI_CS2#/GBE_STAT2/GPIO166

D21

PS2KB_DAT/GPIO189

C20

PS2KB_CLK/GPIO190

D23

PS2M_DAT/GPIO191

C22

PS2M_CLK/GPIO192

F21

KSO_0/GPIO209

E20

KSO_1/GPIO210

F20

KSO_2/GPIO211

A22

KSO_3/GPIO212

E18

KSO_4/GPIO213

A20

KSO_5/GPIO214

J18

KSO_6/GPIO215

H18

KSO_7/GPIO216

G18

KSO_8/GPIO217

B21

KSO_9/GPIO218

K18

KSO_10/GPIO219

D19

KSO_11/GPIO220

A18

KSO_12/GPIO221

C18

KSO_13/GPIO222

B19

KSO_14/GPIO223

B17

KSO_15/GPIO224

A24

KSO_16/GPIO225

D17

KSO_17/GPIO226

21807-A13-HUDSON-M3_FCBGA656

A76M Bolton M3

SA000066K70

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

HUDSON-2

EMBEDDED CTRL

2012/11/13 2013/11/12

USBCLK/14M_25M_48M_OSC

USB MISCUSB 1.1USB 2.0USB 3.0

USB_FSD1P/GPIO186

USB_FSD0P/GPIO185

USB OC GPIO ACPI / WAKE UP EVENTSHD AUDIO

SCL3_LV/GPIO195

SDA3_LV/GPIO196 EC_PWM0/EC_TIMER 0/GPIO197 EC_PWM1/EC_TIMER 1/GPIO198

EC_PWM2/EC_TIMER 2/WOL_EN/GPIO199

EC_PWM3/EC_TIMER 3/GPIO200

Compal Secret Data

Deciphered Date

USB_RCOMP

USB_FSD1N

USB_FSD0N

USB_HSD13P USB_HSD13N

USB_HSD12P USB_HSD12N

USB_HSD11P USB_HSD11N

USB_HSD10P USB_HSD10N

USB_HSD9P USB_HSD9N

USB_HSD8P USB_HSD8N

USB_HSD7P USB_HSD7N

USB_HSD6P USB_HSD6N

USB_HSD5P USB_HSD5N

USB_HSD4P USB_HSD4N

USB_HSD3P USB_HSD3N

USB_HSD2P USB_HSD2N

USB_HSD1P USB_HSD1N

USB_HSD0P USB_HSD0N

USBSS_CALRP

USBSS_CALRN

USB_SS_TX3P USB_SS_TX3N

USB_SS_RX3P USB_SS_RX3N

USB_SS_TX2P USB_SS_TX2N

USB_SS_RX2P USB_SS_RX2N

USB_SS_TX1P USB_SS_TX1N

USB_SS_RX1P USB_SS_RX1N

USB_SS_TX0P USB_SS_TX0N

USB_SS_RX0P USB_SS_RX0N

SCL2/GPIO193

SDA2/GPIO194

KSI_0/GPIO201 KSI_1/GPIO202 KSI_2/GPIO203 KSI_3/GPIO204 KSI_4/GPIO205 KSI_5/GPIO206 KSI_6/GPIO207 KSI_7/GPIO208

D

G8

B9

USB_RCOMP

H1 H3

H6 H5

H10 G10

K10 J12

G12 F12

K12 K13

B11 D11

E10 F10

C10 A10

H9 G9

A8 C8

F8 E8

C6 A6

C5 A5

C1 C3

E1 E3

C16

USBSS_CALRP

A16

USBSS_CALRN

A14 C14

C12 A12

D15 B15

E14 F14

F15

USB3_TX1_P

G15

USB3_TX1_N

H13

USB3_RX1_P

G13

USB3_RX1_N

J16

USB3_TX0_P

H16

USB3_TX0_N

J15

USB3_RX0_P

K15

USB3_RX0_N

H19 G19 G22 G21 E22 H22 J22 H21

K21 K22 F22 F24 E24 B23 C24 F18

D

EC_PWM2

GPU_SEL

10K_0804_8P4R_5%

E

1 2

R122 11.8K_0402_1%R122 11.8K_0402_1%

USB20_P11 <39> USB20_N11 <39>

USB20_P10 <39> USB20_N10 <39>

USB20_P6 <37> USB20_N6 <37>

USB20_P4 <39> USB20_N4 <39>

USB20_P3 <27> USB20_N3 <27>

USB20_P2 <30> USB20_N2 <30>

USB20_P0 <37> USB20_N0 <37>ODD_DA#_FCH<34>

1 2

R133 1K_0402_1%R133 1K_0402_1%

1 2

R134 1K_0402_1%R134 1K_0402_1%

RP7

18 27 36 45

EC_PWM2 <15>

Title

Size Document Number Rev

Custom

Date: Sheet of

Card Reader

Touch Screen

+FCH_VDD_11_SSUSB_S

USB3_TX1_P <39> USB3_TX1_N <39>

USB3_RX1_P <39> USB3_RX1_N <39>

USB3_TX0_P <39> USB3_TX0_N <39>

USB3_RX0_P <39> USB3_RX0_N <39>

strap pin

Compal Electronics, Inc.

FCH-ACPI/USB/HDA/GPIO

VALGD MB L

CMOS

WLAN

RP1

100K_0402_5%

GPU_SEL

10K_0402_5%

E

LP2

LP1

+3VALW

PX@

R234

@

R235

13 57Friday, April 12, 2013

LP2

LP1

12

Root

Mars

0.1

A

B

C

D

E

+3VS

+FCH_VDDAN_33_DAC

1 1

+3VS +FCH_VDDAN_33_DAC

2 2

3/1 SIT downsize to 0402, BLM15AX221SN1D (Murata)

3 3

4 4

SHORT PAD@

1 2

L2 0_0603_5%

+VDDPL_33_SYS

220 ohm

SHORT PAD@

1 2

R172 0_0402_5%

1 2

FBMA-L11-201209-221LMA30T_0805

220 ohm

+3VALW

BLM15AX221SN1D 0402

+VDDAN_33_USB

BLM15AX221SN1D 0402

+3VS

1 2

L13 0_0603_5%

SHORT PAD@

+3VS

SHORT PAD@

1 2

L14 0_0603_5%

L4

L6

SM01000MK00

220 ohm

L77

SM01000MK00

220 ohm

+VDDPL_33_MLDAC

30mil

+VDDPL_33_PCIE

220 ohm

+VDDPL_33_SATA

A

C166

2.2U_0402_6.3V6M

C166

2.2U_0402_6.3V6M

1

2

0.1U_0402_16V7K

C175

1

2

C196

C195

2.2U_0603_6.3V6K

C195

2.2U_0603_6.3V6K

1

2

+VDDPL_33_SSUSB_S

C205

2.2U_0402_6.3V6M

C205

2.2U_0402_6.3V6M

1

2

+VDDPL_33_USB_S

C213

2.2U_0402_6.3V6M

C213

2.2U_0402_6.3V6M

1

2

220 ohm

C167

0.1U_0402_16V7K

C167

0.1U_0402_16V7K

1

2

0.1U_0402_16V7K

C176

1

2

LDO_CAP: Internally generated 1.8V

upply for the RGB outputs

s

+1.1VS

+3VS

+VDDPL_33_MLDAC

BLM15AX221SN1D 0402

L3

SM01000MK00

1 2

220 ohm/2A

3/1 SIT downsize to 0402, BLM15AX221SN1D (Murata)

0.1U_0402_16V4Z

1

2

+3VALW

FBMA-L11-201209-221LMA30T_0805

C206

0.1U_0402_16V7K

C206

0.1U_0402_16V7K

1

3/1 SIT downsize to 0402, BLM15AX221SN1D (Murata)

2

C214

0.1U_0402_16V7K

C214

0.1U_0402_16V7K

1

2

C220

2.2U_0402_6.3V6M

C220

2.2U_0402_6.3V6M

1

2

C227

2.2U_0402_6.3V6M

C227

2.2U_0402_6.3V6M

1

2

+1.1VALW

3/1 SIT downsize to 0402, BLM15AX221SN1D (Murata)

+1.1VALW

FBMA-L11-201209-221LMA30T_0805

L5

1 2

220 ohm/2A

L9

BLM15AX221SN1D 0402

SM01000MK00

220 ohm

L11

BLM15AX221SN1D 0402

SM01000MK00

220 ohm

+FCH_VDD_11_SSUSB_S

40mils

12

L78

42 ohm/4A

R171

0_0603_5%

SHORT PAD@

+VDDPL_33_SYS

1 2

R173 0_0402_5%

1 2

R174 0_0402_5%

SHORT PAD@

+VDDPL_33_USB_S

+VDDPL_33_PCIE

+VDDPL_33_SATA

SHORT PAD@

1 2

R178 0_0402_5%

1 2

R179 0_0603_5%

SHORT PAD@

R182 0_0402_5%

C200

1

2

C208

1

2

C215

1

2

SHORT PAD@

1 2

R185 0_0603_5%

R187 0_0603_5%

1 2

SHORT PAD@

B

C171

1

2

10U_0603_6.3V6M

2.2U_0402_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6M

C172

1

2

C188

1

2

1 2

SHORT PAD@

10U_0603_6.3V6M

C201

1

2

C209

0.1U_0402_16V7K

C209

0.1U_0402_16V7K

1

2

C216

0.1U_0402_16V7K

C216

0.1U_0402_16V7K

1

2

C221

1

2

C228

1

2

+VDDIO_33_PCIGP

0.1U_0402_16V7K

C173

C174

1

2

+VDDPL_33_SYS

+VDDPL_33_DAC

+VDDPL_33_ML

+FCH_VDDAN_33_DAC

+VDDPL_33_SSUSB_S

DEBUG@

1 2

C184 2.2U_0603_6.3V6K

+VDDPL_11_DAC

+VDDAN_11_ML

C189

0.1U_0402_16V7K

C189

0.1U_0402_16V7K

4.7U_0402_6.3V6M

C190

0.1U_0402_16V7K

C190

0.1U_0402_16V7K

1

2

+VDDAN_33_USB

C202

1

2

+VDDAN_11_USB_S

+VDDCR_11V_USB

C217

1

2

+VDDAN_11_SSUSB

1U_0402_6.3V6K

+VDDCR_11_SSUSB

10U_0603_6.3V6M

C204

C203

1U_0402_6.3V6K

C203

1U_0402_6.3V6K

0.1U_0402_16V7K

1

2

C223

0.1U_0402_16V7K

C223

0.1U_0402_16V7K

C222

0.1U_0402_16V7K

C222

0.1U_0402_16V7K

1

2

C230

C229

1U_0402_6.3V6K

C229

1U_0402_6.3V6K

1

2

U1C

HUDSON-2

102mA

AB17

VDDIO_33_PCIGP_1

AB18

VDDIO_33_PCIGP_2

AE9

VDDIO_33_PCIGP_3

AD10

VDDIO_33_PCIGP_4

AG7

VDDIO_33_PCIGP_5

AC13

VDDIO_33_PCIGP_6

AB12

VDDIO_33_PCIGP_7

AB13

VDDIO_33_PCIGP_8

AB14

VDDIO_33_PCIGP_9

AB16

VDDIO_33_PCIGP_10

47mA

H24

VDDPL_33_SYS

20mA

V22

VDDPL_33_DAC

12mA

U22

VDDPL_33_ML

3

0mA

T22

VDDAN_33_DAC

11mA

L18

VDDPL_33_SSUSB_S

14mA

D7

VDDPL_33_USB_S

11mA

AH29

VDDPL_33_PCIE

12mA

AG28

VDDPL_33_SATA

M31

LDO_CAP

7mA

V21

VDDPL_11_DAC

226mA

Y22

VDDAN_11_ML_1

V23

VDDAN_11_ML_2

V24

VDDAN_11_ML_3

V25

VDDAN_11_ML_4

AB10

VDDIO_33_GBE_S

AB11

VDDCR_11_GBE_S_1

AA11

VDDCR_11_GBE_S_2

AA9

VDDIO_GBE_S_1

AA10

VDDIO_GBE_S_2

470mA

G7

VDDAN_33_USB_S_1

H8

0.1U_0402_16V7K

VDDAN_33_USB_S_2

J8

VDDAN_33_USB_S_3

K8

VDDAN_33_USB_S_4

K9

VDDAN_33_USB_S_5

M9

VDDAN_33_USB_S_6

M10

VDDAN_33_USB_S_7

N9

VDDAN_33_USB_S_8

N10

VDDAN_33_USB_S_9

M12

VDDAN_33_USB_S_10

N12

VDDAN_33_USB_S_11

M11

VDDAN_33_USB_S_12

140mA

U12

VDDAN_11_USB_S_1

U13

VDDAN_11_USB_S_2

42mA

T12

VDDCR_11_USB_S_1

T13

VDDCR_11_USB_S_2

282mA

P16

VDDAN_11_SSUSB_S_1

M14

VDDAN_11_SSUSB_S_2

N14

VDDAN_11_SSUSB_S_3

P13

VDDAN_11_SSUSB_S_4

P14

VDDAN_11_SSUSB_S_5

424mA

N16

VDDCR_11_SSUSB_S_1

N17

VDDCR_11_SSUSB_S_2

P17

VDDCR_11_SSUSB_S_3

M17

VDDCR_11_SSUSB_S_4

21807-A13-HUDSON-M3_FCBGA656

0.1U_0402_16V7K

C231

0.1U_0402_16V7K

C231

0.1U_0402_16V7K

A76M Bolton M3

SA000066K70

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

HUDSON-2

PCI/GPIO I/O

USB SS USB MAIN LINKGBE LAN

POWER

C

VDDCR_11_1 VDDCR_11_2 VDDCR_11_3 VDDCR_11_4 VDDCR_11_5 VDDCR_11_6 VDDCR_11_7 VDDCR_11_8

CORE S0

VDDCR_11_9

VDDAN_11_CLK_1 VDDAN_11_CLK_2 VDDAN_11_CLK_3 VDDAN_11_CLK_4 VDDAN_11_CLK_5 VDDAN_11_CLK_6

CLKGEN I/OPCI EXPRESSSERIAL ATA3.3V_S5 I/O

VDDAN_11_CLK_7 VDDAN_11_CLK_8

VDDAN_11_PCIE_1 VDDAN_11_PCIE_2 VDDAN_11_PCIE_3 VDDAN_11_PCIE_4 VDDAN_11_PCIE_5 VDDAN_11_PCIE_6 VDDAN_11_PCIE_7 VDDAN_11_PCIE_8

VDDAN_11_SATA_1 VDDAN_11_SATA_4 VDDAN_11_SATA_2 VDDAN_11_SATA_3 VDDAN_11_SATA_5 VDDAN_11_SATA_6 VDDAN_11_SATA_7 VDDAN_11_SATA_8 VDDAN_11_SATA_9

VDDAN_11_SATA_10

VDDIO_33_S_1 VDDIO_33_S_2 VDDIO_33_S_3 VDDIO_33_S_4 VDDIO_33_S_5 VDDIO_33_S_6 VDDIO_33_S_7 VDDIO_33_S_8

VDDXL_33_S

VDDCR_11_S_1 VDDCR_11_S_2

VDDPL_11_SYS_S

VDDAN_33_HWM _S

VDDIO_AZ_S

2012/11/13 2013/11/12

1007mA

C179

T14 T17

1

T20 U16 U18

2

V14 V17 V20 Y17

340mA

H26 J25

C181

K24 L22

1

M22 N21 N22

2

P22

1088mA

AB24 Y21 AE25

C185

AD24 AB23

1

AA22 AF26 AG27

2

1337mA

AA21 Y20 AB21

C191

AB22 AC22

1

AC21 AA20 AA18

2

AB20 AC19

59mA

N18 L19

C197

M18 V12

1

V13 Y12 Y13

2

W11

5mA

G24

C207

1

2

187mA

N20 M20

C211

1

2

70mA

J24

C218

1

2

12mA

M8

C224

1

@

2

26mA

AA4

Compal Secret Data

Deciphered Date

+VCC_VDDCR_11

C168

0.1U_0402_16V7K

C168

0.1U_0402_16V7K

C180

0.1U_0402_16V7K

1

2

+1.1VS_CKVDD

C183

C182

0.1U_0402_16V7K

C182

0.1U_0402_16V7K

1U_0402_6.3V6K

2.2U_0402_6.3V6M

1U_0402_6.3V6K

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M@C224

2.2U_0402_6.3V6M

1

2

+VDDAN_11_PCIE

C187

C186

1U_0402_6.3V6K

C186

1U_0402_6.3V6K

1

2

C193

C192

1U_0402_6.3V6K

C192

1U_0402_6.3V6K

1

2

+VDDIO_33_S

C199

C198

1U_0402_6.3V6K

C198

1U_0402_6.3V6K

1

2

+VDDXL_3.3V

+VDDCR_1.1V

C212

1U_0402_6.3V6K

C212

1U_0402_6.3V6K

1

2

+VDDPL_11_SYS_S

0.1U_0402_16V7K

C219

1

2

+VDDAN_33_HWM

C225

0.1U_0402_16V7K@C225

0.1U_0402_16V7K

1

@

2

+VDDIO_AZ

C226 2.2U_0402_6.3V6MC226 2.2U_0402_6.3V6M

D

C169

1U_0402_6.3V6K

C177

1U_0402_6.3V6K

+VDDAN_11_PCIE

22U_0603_6.3V6M

C194

1U_0402_6.3V6K

2.2U_0402_6.3V6M

1 2

R170 0_0805_5%R170 0_0805_5%

1U_0402_6.3V6K

C170

10U_0603_6.3V6M

C170

10U_0603_6.3V6M

1

2

+1.1VS_CKVDD

1U_0402_6.3V6K

1

2

+AVDD_SATA

22U_0603_6.3V6M

1

2

R181 0_0402_5%

1 2

L7 0_0603_5%

SHORT PAD@

R183 0_0603_5%

SHORT PAD@

1 2

L12 0_0603_5%

C178

22U_0603_6.3V6M

C178

22U_0603_6.3V6M

1

2

1 2

SHORT PAD@

1 2

SHORT PAD@

42ohm @ 100MHz

1 2

R176 0_0603_5%

SHORT PAD@

42ohm @ 100MHz

112

JUMP_43X39

J14

42ohm @ 100MHz

112

JUMP_43X39

J15

220 ohm

1 2

R184 0_0402_5%

SHORT PAD@

SHORT PAD@ 1 2

R186 0_0402_5%

+1.1VS

2

JUMP@J14

JUMP@

+1.1VS

2

JUMP@J15

JUMP@

+3VALW

+VDDXL_3.3V Tie to +3.3V_S 5 rail if USB3 Wake is supported; otherwise, tie to +3.3V_S0 rail. Hudson-2 desig ns: Tie to +3.3 V_S0 rail.

+1.1VALW

+3VALW

AMD reply: VDDAN_33_HWM_S: Please connect it to +3.3V_S5 directly if HWM is not used.

+3VS

VDDIO_AZ_S should be tied to +3.3/1.5V_S5 rail if Wake on Ring is supported

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

FCH PWR

VALGD MB L

14 57Friday, April 12, 2013

E

of

0.1

A

B

C

D

E

1 1

2 2

3 3

U1E

HUDSON-2

A33

B13

D13

E12 E16 E29

F11 F13 F16 F17 F19 F23 F25 F29

G16 G32 H12 H15 H29

K16 K27 K28

M13 M16 M21 M25

N11 N13 N23 N24 P12 P18 P20 P21 P31 P33

R11 R25 R28 T11 T16 T18

K25

H25

A3

B7

D9

E5

F7 F9

G6

J6

J9 J10 J13 J28 J32

K7

L6 L12 L13 L15 L16 L21

N6

R4

N8

HUDSON-2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSAN_HWM

VSSXL

VSSPL_SYS

21807-A13-HUDSON-M3_FCBGA656

A76M Bolton M3

SA000066K70

GROUND

VSSPL_DAC VSSAN_DAC

VSSANQ_DAC

VSSIO_DAC

EFUSE

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

T25 T27 U6 U14 U17 U20 U21 U30 U32 V11 V16 V18 W4 W6 W25 W28 Y14 Y16 Y18 AA6 AA12 AA13 AA14 AA16 AA17 AA25 AA28 AA30 AA32 AB25 AC6 AC18 AC28 AD27 AE6 AE15 AE21 AE28 AF8 AF12 AF16 AF33 AG30 AG32 AH5 AH11 AH18 AH19 AH21 AH23 AH25 AH27 AJ18 AJ28 AJ29 AK21 AK25 AL18 AM21 AM25 AN1 AN18 AN28 AN33

T21 L28 K33 N28

R6

STRAP PINS

PCI_CLK1

ALLOW

PULL

PCIE GEN2

HIGH

DEFAULT

FORCE

PULL

PCIE GEN1

LOW

PCI_CLK1<11>

PCI_CLK3<11>

PCI_CLK4<11>

CLK_PCI_EC<11,36>

LPC_CLK1<11 >

EC_PWM2<13>

RTC_CLK<11,36>

PCI_CLK3

USE DEBUG STRAPS

IGNORE DEBUG STRAP

DEFAULT

R200 10K_0402_5%

Strap@

12

PCI_CLK4 CLK_PCI_EC

NON_FUSION CLOCK MODE

FUSION CLOCK MODE

DEFAULT

+3VALW+3VS

182736

+3VALW+3VS+3VS

R190 10K_0402_5%

Strap@

R190 10K_0402_5%

Strap@

182736

Strap@

12

45

R189 10K_0402_5%

Strap@

R189 10K_0402_5%

Strap@

12

RP12

10K_0804_8P4R_5%

EC ENABLED

EC DISABLED

DEFAULT

45

RP13

RP13 10K_0804_8P4R_5%

10K_0804_8P4R_5%

R191 10K_0402_5%

12

Strap@

12

R204 10K_0402_5%

CLKGEN ENABLED

DEFAULT

CLKGEN DISABLE

+3VALW

Strap@

12

DEBUG STRAPS

FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]

EC_PWM2

LPC ROM

SPI ROM

DEFAULT

R193 10K_0402_5%

R206 2.2K_0402_5%

R205 2.2K_0402_5%R205 2.2K_0402_5%

Strap@

12

RTC_CLKLPC_CLK1

S5 PLUS MODE DISABLED

DEFAULT

S5 PLUS MODE ENABLED

PCI_AD27 PCI_AD26

USE PCI

PULL

PLL

HIGH

DEFAULT

BYPASS

PULL

PCI PLL

LOW

PCI_AD27<11>

PCI_AD26<11>

PCI_AD25<11>

PCI_AD24<11>

PCI_AD23<11>

DISABLE ILA AUTORUN

DEFAULT

ENABLE ILA AUTORUN

R195 2.2K_0402_5%

12

Strap@

PCI_AD25 PCI_AD24

USE FC PLL

BYPASS FC PLL

R196 2.2K_0402_5%

12

Strap@

R197 2.2K_0402_5%

12

USE DEFAULT PCIE STRAPS

DEFAULT

USE EEPROM PCIE STRAPS

12

Strap@

R198 2.2K_0402_5%

PCI_AD23

DISABLE PCI MEM BOOT

DEFAULTDEFAULT

ENABLE PCI MEM BOOT

12

Strap@

R199 2.2K_0402_5%

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/11/13 2013/11/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet

Compal Electronics, Inc.

FCH-VSS/Strap

VALGD MB L

15 57Friday, April 12, 2013

E

0.1

of

A

B

C

D

E

PCIE_CTX_GRX_P[7..0]<5>

PCIE_CTX_GRX_N[7..0]<5>

1 1

2 2

3 3

CLK_PCIE_VGA<11> CLK_PCIE_VGA#<11>

PCIE_CTX_GRX_P[7..0]

PCIE_CTX_GRX_N[7..0]

PCIE_CTX_GRX_P0 PCIE_CTX_GRX_N0

PCIE_CTX_GRX_P1 PCIE_CTX_GRX_N1

PCIE_CTX_GRX_P2 PCIE_CTX_GRX_N2

PCIE_CTX_GRX_P3 PCIE_CTX_GRX_N3

PCIE_CTX_GRX_P4 PCIE_CTX_GRX_N4

PCIE_CTX_GRX_P5 PCIE_CTX_GRX_N5

PCIE_CTX_GRX_P6 PCIE_CTX_GRX_N6

PCIE_CTX_GRX_P7 PCIE_CTX_GRX_N7

CLK_PCIE_VGA CLK_PCIE_VGA#

PX@

RV2 1K_0 402_5%

GPU_RST#

12

PX@

RV4

RV4 100K_0402_5%

100K_0402_5%

AA38

W36

W38

U36

U38

R36

R38

N36

N38 M37

M35

H37

H35 G36

G38

AB35 AA36

AH16

AA30

Y37

Y35

V37

V35

T37

T35

P37

P35

L36

L38 K37

K35 J36

J38

F37

F35 E37

UV1A

PCIE_RX0P PCIE_RX0N

PCIE_RX1P PCIE_RX1N

PCIE_RX2P PCIE_RX2N

PCIE_RX3P PCIE_RX3N

PCIE_RX4P PCIE_RX4N

PCIE_RX5P PCIE_RX5N

PCIE_RX6P PCIE_RX6N

PCIE_RX7P PCIE_RX7N

NC NC

CLOCK

PCIE_REFCLKP PCIE_REFCLKN

TEST_PG

PERSTB

PX@

PART 1 0F 9

PCI EXPRESS INTERFACE

MARS-XTX M2_FCBGA962

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

CALIBRATION

PCIE_CALR_TX

PCIE_CALR_RX

PCIE_CRX_GTX_P[7..0]

PCIE_CRX_GTX_N[7..0]

Y33

PCIE_CRX_C_GTX_P0

Y32

PCIE_CRX_C_GTX_N0

W33

PCIE_CRX_C_GTX_P1

W32

PCIE_CRX_C_GTX_N1 PCIE_CRX_GTX_N1

U33

PCIE_CRX_C_GTX_P2

U32

PCIE_CRX_C_GTX_N2

U30

PCIE_CRX_C_GTX_P3

U29

PCIE_CRX_C_GTX_N3 PCIE_CRX_GTX_N3

T33

PCIE_CRX_C_GTX_P4

T32

PCIE_CRX_C_GTX_N4 PCIE_CRX_GTX_N4

T30

PCIE_CRX_C_GTX_P5

T29

PCIE_CRX_C_GTX_N5 PCIE_CRX_GTX_N5

P33

PCIE_CRX_C_GTX_P6

P32

PCIE_CRX_C_GTX_N6

P30

PCIE_CRX_C_GTX_P7

P29

PCIE_CRX_C_GTX_N7 PCIE_CRX_GTX_N7

N33

NC

N32

NC

N30

NC

N29

NC

L33

NC

L32

NC

L30

NC

L29

NC

K33

NC

K32

NC

J33

NC

J32

NC

K30

NC

K29

NC

H33

NC

H32

NC

Y30

1 2

RV1 1.69K_0402_1%PX@RV1 1.69K_0402_1%PX@

Y29

1 2

RV3 1K_0402_1%PX@RV3 1K_0402_1%P X@

PCIE_CRX_GTX_P[7..0] <5>

PCIE_CRX_GTX_N[7..0] <5>

1 2

CV10.1U_0402_16V7K PX@CV10.1U_0402_16V7K PX@

1 2

CV20.1U_0402_16V7K PX@CV20.1U_0402_16V7K PX@

1 2

CV30.1U_0402_16V7K PX@CV30.1U_0402_16V7K PX@

1 2

CV40.1U_0402_16V7K PX@CV40.1U_0402_16V7K PX@

1 2

CV50.1U_0402_16V7K PX@CV50.1U_0402_16V7K PX@

1 2

CV60.1U_0402_16V7K PX@CV60.1U_0402_16V7K PX@

1 2

CV70.1U_0402_16V7K PX@CV70.1U_0402_16V7K PX@

1 2

CV80.1U_0402_16V7K PX@CV80.1U_0402_16V7K PX@

1 2

CV90.1U_0402_16V7K PX@CV90.1U_0402_16V7K PX@

1 2

CV100.1U_0402_16V7K PX@CV100.1U_0402_16V7K PX@

1 2

CV110.1U_0402_16V7K PX@CV110.1U_0402_16V7K PX@

1 2

CV120.1U_0402_16V7K PX@CV120.1U_0402_16V7K PX@

1 2

CV130.1U_0402_16V7K PX@CV130.1U_0402_16V7K PX@

1 2

CV140.1U_0402_16V7K PX@CV140.1U_0402_16V7K PX@

1 2

CV150.1U_0402_16V7K PX@CV150.1U_0402_16V7K PX@

1 2

CV160.1U_0402_16V7K PX@CV160.1U_0402_16V7K PX@

+0.95VGS

PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0

PCIE_CRX_GTX_P1

PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P3

PCIE_CRX_GTX_P4

PCIE_CRX_GTX_P5

PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6

PCIE_CRX_GTX_P7

LVDS Interface

UV1D

PART 7 0F 9

RSVD/VARY_BL

RSVD/DIGON

LVDS CONTROL

TXCBP_DPB3P TXCBM_DPB3N

TX3P_DPB2P

TX3M_DPB2N

TX4P_DPB1P

TX4M_DPB1N

TX5P_DPB0P

TX5M_DPB0N

LVTMDP

TXCAP_DPA3P TXCAM_DPA3N

TX0P_DPA2P

TX0M_DPA2N

TX1P_DPA1P

TX1M_DPA1N

TX2P_DPA0P

TX2M_DPA0N

MARS-XTX M2_FCBGA962

PX@

+3VGS

5

2

PXS_RST#<13>

APU_PCIE_RST#<11,30,31>

P

B

1

A

G

3

AK27 AJ27

AK35 AL36

AJ38 AK37

AH35 AJ36

AG38 AH37

AF35

NC#AF35

AG36

NC#AG36

AP34 AR34

AW37 AU35

AR37 AU39

AP35 AR35

AN36

NC

AP37

NC

4

GPU_RST#

Y

PX@

UV2

UV2 MC74VHC1G08DFT2G SC70 5P

MC74VHC1G08DFT2G SC70 5P

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/11/13 2013/11/12

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

ATI_MarsXT_M2_PCIE/LVDS

VALGD MB L

16 57Friday, April 12, 2013

E

0.1

A

UV1B

MUTI GFX

+VREFG_GPU

PX_EN

TESTEN

JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO

GPIO_28_FDO

+TSVDD

1

CV32

2

0.1U_0402_16V4Z

PX@ CV32

PX@

AD29 AC29

AJ21 AK21

AW8

AW3

AW5

AW6

AR10

AW10

AU10 AP10 AV11 AT11 AR12

AW12

AU12 AP12

AJ23 AH23

AK26 AJ26

AH20 AH18 AN16

AH17 AJ17 AK17 AJ13 AH15 AJ16 AK16 AL16 AM16 AM14 AM13 AK14 AG30 AN14 AM17 AL13 AJ14 AK13 AN13

AG32 AG33

AJ19 AK19 AJ20 AK20 AJ24 AH26 AH24

AC30

AK24

AH13

AL21

AD28

AM23 AN23 AK23 AL24 AM24

AF29 AG29

AK32

AL31

AJ32 AJ33

AR8 AU8 AP8

AR3 AR1 AU1 AU3

AP6

AU5 AR6

AU6 AT7 AV7 AN7 AV9 AT9

GENLK_CLK GENLK_VSYNC

SWAPLOCKA SWAPLOCKB

NC NC DBG_CNTL0 NC NC NC DBG_DATA0 DBG_DATA1 DBG_DATA2 DBG_DATA3 DBG_DATA4 DBG_DATA5 DBG_DATA6 DBG_DATA7 DBG_DATA8 DBG_DATA9 DBG_DATA10 DBG_DATA11 DBG_DATA12 DBG_DATA13 DBG_DATA14 DBG_DATA15 DBG_DATA16 DBG_DATA17 DBG_DATA18 DBG_DATA19 DBG_DATA20 DBG_DATA21 DBG_DATA22 DBG_DATA23

SMBCLK

SMBus

SMBDATA

SCL

I2C

SDA

GENERAL PURPOSE I/O

GPIO_0 GPIO_1 GPIO_2

GPIO_5_AC_BATT GPIO_6_TACH GPIO_7_BLON GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK GPIO_11 GPIO_12 GPIO_13 GPIO_14_HPD2 GPIO_15_PWRCNTL_0 GPIO_16 GPIO_17_THERMAL_INT GPIO_18_HPD3 GPIO_19_CTF GPIO_20_PWRCNTL_1 GPIO_21 GPIO_22_ROMCSB CLKREQB

GPIO_29 GPIO_30

GENERICA GENERICB GENERICC GENERICD GENERICE_HPD4 GENERICF_HPD5 GENERICG_HPD6

CEC_1

HPD1

DBG_VREFG

BACO

PX_EN

DEBUG

TESTEN

JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO

THERMAL

DPLUS DMINUS

GPIO_28_FDO

TS_A

TSVDD TSVSS

PX@

GENLK_CLK

T31TEST POINT@ T31T EST POINT@

GENLK_VSYNC

T32TEST POINT@ T32T EST POINT@

1 1

VGA_SMB_CK2 VGA_SMB_DA2

2 2

3 3

+1.8VGS

GPIO_28_FDO

4 4

TSVDD MarsCR B Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

GPU_GPIO0<50>

GPU_VID5<50>

GPU_VID1<50>

GPU_VID2<50>

CLK_REQ_VGA#<13>

GPU_VID3<50> GPU_VID4<50>

PX@

12

RV13 499_0402_1%

PX@

12

RV14 249_0402_1%

12

0.1U_0402_16V7K

CV23

PX@

MLPS

H

Disable

Enable

L

1 2

BLM15BD121SN1D_0402

ACIN<36,43>

PX@ LV3

PX@

+VREFG_GPU

+3VGS

REMOTE1+<33> REMOTE1-<33>

+3VGS

LV3

A

@

DV1

DV1 RB751V_SOD323

RB751V_SOD323

RV12 10K_0402_5%@ RV12 10K_0402_5%@

0.60 V level, Please VREFG Divider ans cap close to ASIC

TEST POINT@

RV18 5.11K_0402_5%

RV19 1K_0402_5%

+TSVDD+1.8VGS

GPU_GPIO0

21

GPU_GPIO5 GPU_VID5

GPU_VID1

THM_ALERT#

1 2

GPU_VID2

CLK_REQ_VGA#

GPU_VID3 GPU_VID4

T29

DEBUG@

1 2

PX@

T11TEST POINT @ T11TEST POINT@

REMOTE1+ REMOTE1-

1 2

DEBUG@

RV26 10K_0402_5%

1 2

PX@

RV31 10K_0402_5%

(1.8V@13mA TSVDD)

1

CV31

CV30

2

1U_0402_6.3V6K

10U_0603_6.3V6M

PX@ CV31

PX@

PX@ CV30

PX@

PART 2 0F 9

DPA

DPB

DPC

DPD

B

AVSSN

DAC1

HSYNC VSYNC

RSET

AVDD

AVSSQ

VDD1DI

VSS1DI

NC_SVI2 NC_SVI2 NC_SVI2

MLPS

DDC/AUX

DDC1CLK

DDC1DATA

AUX1P AUX1N

DDC2CLK

DDC2DATA

AUX2P AUX2N

DDCVGACLK

DDCVGADATA

MARS-XTX M2_FCBGA962

B

PS_0

PS_1

PS_2

PS_3

C

AU24

NC

AV23

NC

AT25

NC

AR24

NC

AU26

NC

AV25

NC

AT27

NC

AR26

NC

AR30

NC

AT29

NC

AV31

NC

AU30

NC

AR32

NC

AT31

NC

AT33

NC

AU32

NC

AU14

NC

AV13

NC

AT15

NC

AR14

NC

AU16

NC

AV15

NC

AT17

NC

AR16

NC

AU20

NC

AT19

NC

AT21

NC

AR20

NC

AU22

NC

AV21

NC

AT23

NC

AR22

NC

AD39

VGA_R

R

AD37

AE36

VGA_G

G

AD35

AF37

VGA_B

B

AE38

AC36

HSYNC

AC38

VSYNC

AB34

RV11 499_0402_1%PX@RV11 499_0402_1%PX@

AD34

+AVDD

AE34

AC33

+VDD1DI

AC34

V13

NC

U13

NC

AF33

NC

AF32

NC

AA29

NC

AG21

NC

AC32

NC

AC31 AD30 AD32

AM34

PS_0

AD31

PS_1

AG31

PS_2

AD33

PS_3

AM26

VGA_CLK

AN26

VGA_DAT

AM27 AL27

AM19 AL19

AN20 AM20

AL30

NC

AM30

NC

AL29

NC

AM29

NC

AN21

NC

AM21

NC

AK30

NC

AK29

NC

AJ30 AJ31

T24 TEST POINT@T24 TEST POINT@

T25 TEST POINT@T25 TEST POINT@

T46 TEST POINT@T46 TEST POINT@

T34 TEST POINT@T34 TEST POINT@ T36 TEST POINT@T36 TEST POINT@

1 2

(1.8V@70mA AVDD)

(1.8V@117mA VDD1DI)

T37

T37 T28

T28

GPU_GPIO5

THM_ALERT#

JTAG_TRSTB JTAG_TDI JTAG_TMS

JTAG_TCK

1

CV20

2

PX@ CV20

PX@

0.1U_0402_16V7K

TEST POINT@

TEST POINT@ TEST POINT@

TEST POINT@

10K_0402_5%

VGA_SMB_CK2

VGA_SMB_DA2

1126A Blues Modify

STRAPS

RV5 100K_0402_5%Strap@RV5 100K_0402_5%Strap@

RV6 2.2K_0402_5%Strap@RV6 2.2K_0402_5%Strap@

RV7 10K_0402_5%Strap@RV7 10K_0402_5%Strap@ RV8 10K_0402_5%Strap@RV8 10K_0402_5%Strap@ RV9 10K_0402_5%Strap@RV9 10K_0402_5%Strap@

RV10 10K_0402_5%Strap@RV10 10K_0402_5%Strap@

+AVDD

1

CV18

CV17

2

PX@ CV18

PX@

PX@ CV17

PX@

1U_0402_6.3V6K

0.1U_0402_16V7K

1 2

1

CV22

CV21

2

PX@ CV22

PX@

PX@ CV21

PX@

1U_0402_6.3V6K

10U_0603_6.3V6M

DIS:+3VGS UMA:+3VS

+3VGS

12

@

RV24

RV25

RV25 10K_0402_5%

10K_0402_5%

DMN66D0LDW-7 2N_SOT363-6

C

+3VGS

12

+3VGS

12 12 12

12

AVDD MarsCRB Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

+1.8VGS

1 2

LV1

PX@LV1

PX@

BLM15BD121SN1D_0402

1

CV19

2

PX@ CV19

PX@

10U_0603_6.3V6M

+1.8VGS+VDD1DI

LV2

PX@LV2

PX@

BLM15BD121SN1D_0402

VDD1DI MarsC RB Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

+3VGS

2

61

5

QV3A

@ QV3A

@

4

QV3B

@ QV3B

@

DMN66D0LDW-7 2N_SOT363-6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

EC_SMB_CK2 <33,36>

3

EC_SMB_DA2 <33,36>

Compal Secret Data

2012/11/13 2013/11/12

Compal Secret Data

D

CONFIGURATION STRAPS

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

STRAPS

TX_PWRS_ENB

TX_DEEMPH_EN

BIF_GEN3_EN_A

BIF_VGA DIS

ROMIDCFG[2:0]

BIOS_ROM_EN PS_2[3]

AUD[1]

AUD[0]

CEC_DIS PS_0[4]

RESERVED PS_1[3]

RESERVED PS_1[2]

RESERVED NA

AUD_PORT_CONN_PINSTRAP[2] PS_3[5]

AUD_PORT_CONN_PINSTRAP[1] PS_3[4]

AUD_PORT_CONN_PINSTRAP[0] PS_0[5]

PS_1[4] 0:50% Tx output swing

PS_1[5] 0:Tx de-emphasis disabled

PS_1[1]

PS_2[4]

PS_0[3..1]

NA

DESCRIPTION OF DEFAULT SETTINGSMLPS

Transmitter Power Savings Enable

1:Full Tx output swing

PCIE Transmitter De-emphasis Enable

1:Tx de-emphasis enabled

PCIE Gen3 Enable (NOTE:RESERVED for Thames/Seymour and should be strapped to 0)

0:GEN3 not support at power-on 1:GEN3 supported at power-on

VGA control

0:VGA controller capacity enabled 1:VGA controller capacity disabled (for multi-GPU)

Serial ROM type or Memory Aperture Size Select

If PS_2[3]=0, defines memory aperture siz e If PS_2[3]=1, defines ROM type 100 - 512Kbit M25P05A (ST) 101 - 1Mbit M25P10A (ST ) 101 - 2Mbit M25P20 (ST) 101 - 4Mbit M25P40 (ST) 101 - 8Mbit M25P80 (ST) 100 - 512Kbit Pm25LV010 (Chingis) 101 - 1Mbit Pm25LV010 (Chingis)

Enable external BIOS ROM device

0:Disabled 1:Enabled

00 - No audio function 01 - Audio for DP only 10 - Audio for DP and HDMI if dongle is detected 11 - Audio for both DP and HDMI

HDMI must only be enabled on systems that are legally entitled. It isthe responsibility of the system designer to ensure that the system is entitled to support this feature.

Reserved for future ASIC

NOTE:ALLOW FOR PULLUP PADS FOR THE RESERVED STRAPS BUT DO NOT INSTALL RESISTOR IF THESE GPIOS ARE USEED, THEY MUST KEEP LOW AND NOT CONFLICT DURING RESET

Reserved

Reserved (for Thames/Whistler/Seymour only)

STRAPS TO INDICATE THE NUMBER OF AUDIO CAPABLE DISPLAY OUTPUTS

111 = 0 usable endpoints 110 = 1 usable endpoints 101 = 2 usable endpoints 100 = 3 usable endpoints 011 = 4 usable endpoints 010 = 5 usable endpoints 001 = 6 usable endpoints 000 = all endpoints are usable

MLPS Strap

CapacitorBits[5:4]

Deciphered Date

D

PS_0[5:1]

PS_1[5:1]

PS_2[5:1]

PS_3[5:1]

PS_0 PS_1 PS_2 PS_3

Strap@

CV26

0.01U_0402_16V7K

Bits[3:1]

0 0 1

1 1

0 0 0

1 1

0 0 0

0 0

1 1

X X X

Strap@

PX@

1

CV27

2

Strap@

CV29

1

CV28

2

0.01U_0402_16V7K

1

2

0.68U_0402_10V6K

R_pu R_pd

NC

8.45K 2K

NC

4.75K

680 nF

NC

4.75K

NC

X

12

Strap@

RV20

X76@ RV20

X76@

8.45K_0402_1%

RV27

X76@ RV27

X76@

8.45K_0402_1%

12

4.75K_0402_1%

PX@RV28

PX@

8.45K_0402_1%

4.75K_0402_1%

Place CLOSE VGA CHIP

Title

ATI_MarsXT_M2_Main_MSIC

Size Document Number Rev

C

Date: Sheet of

E

RECOMMENDED SETTINGS 0= DO NOT INSTALL RESISTOR 1 = INSTALL 10K RESISTOR X = DESIGN DEPENDANT NA = NOT APPLICABLE

Mapping to VRAM type please refer to page 21

X

12

Strap@

RV21

RV28

Compal Electronics, Inc.

8.45K_0402_1%

12

4.75K_0402_1%

RV22

RV29

PX@RV29

PX@

VALGD MB L

E

12

8.45K_0402_1%

12

PX@RV23

PX@

PX@RV30

PX@

2K_0402_1%

+1.8VGS

RV23

RV30

17 57Friday, April 12, 2013

Default Setting

X

1

0

XXX

X

XX

0

XXX

12

0.1

A

3/1 SIT downsize to 0402, BLM15AX221SN1D (Murata)

MPLL_PVDD Mars CRB Design 220ohm 1 1

0.1u 1 1

1 1

2 2

1u 1 1 10u 1 1

SPLL_PVDD Mars CRB Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

SPLL_VDDC Mars CRB Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

+1.8VGS

+0.95VGS

LV4

PX@LV4

PX@

BLM15AX221SN1D 0402

SM01000MK00

LV5

PX@LV5

PX@

1 2

BLM15BD121SN1D_0402

LV6

PX@LV6

PX@

1 2

BLM15BD121SN1D_0402

B

+SPLL_VDDC

+MPV18

10U_0603_6.3V6M

+SPV18

10U_0603_6.3V6M

1

CV33

2

PX@ CV33

PX@

1

CV38

2

PX@ CV38

PX@

1

CV43

2

PX@ CV43

PX@

(MPLL_PVDD:1.8V@130mA )

1

CV34

CV35

2

1U_0402_6.3V6K

PX@ CV34

1U_0402_6.3V6K

PX@

PX@ CV35

PX@

0.1U_0402_16V7K

(SPLL_PVDD:1.8V@75mA )

1

CV40

CV39

2

PX@ CV40

PX@

PX@ CV39

PX@

1U_0402_6.3V6K

0.1U_0402_16V7K

(SPLL_VDDC:0.95V@100mA )

1

CV44

CV45

2

PX@ CV45

PX@

PX@ CV44

PX@

1U_0402_6.3V6K

0.1U_0402_16V7K

+MPV18

+SPV18

+SPLL_VDDC

AM10

AN10

AF30 AF31

AN9

UV1C

H7 H8

PX@

C

MPLL_PVDD MPLL_PVDD

SPLL_PVDD

SPLL_VDDC

SPLL_PVSS

NC_XTAL_PVDD NC_XTAL_PVSS

PART 9 0F 9

PLLS/XTAL

MARS-XTX M2_FCBGA962

XTALIN

XTALOUT

XO_IN2

CLKTESTA CLKTESTB

XO_IN

AV33

AU34

AW34

AW35

AK10 AL10

XTALIN

RV40 0_0402_5%

XTALOUT

12

DEBUG@

CV41

0.1U_0402_16V7K

12

DEBUG@

RV33

51.1_0402_1%

For EMI

GCLK@

1 2

D

12

DEBUG@

CV42

0.1U_0402_16V7K

DEBUG@

RV34

51.1_0402_1%

PXNOGCLK@

15P_0402_50V8J

RV32 1M_0402_5%PXNOGCLK@ RV32 1M_0402_5%PXNOGCLK@

XTALIN

2

27MHZ 10PF +-20PPM X3G027000DA1H

CV36

1

GCLK_27MHZ <38>

1 2

YV1

4

NC

OSC

1

OSC

NC

PXNOGCLK@

E

3

XTALOUT

2

PXNOGCLK@

CV37

CV37 15P_0402_50V8J

15P_0402_50V8J

1

#9/11 need to confirm w/ Power team

300mil(7.2A)

PX@

1

CV48

4.7U_0603_6.3V6K

SIT: Change to +5VALW for Eur lot 6.

3 3

+5VALW

PXS_PWREN#

2

PX@

47K_0402_5%

RV41

PX@

QV2

QV2 2N7002_SOT23

2N7002_SOT23

+1.5V to +1.5VGS

+1.5V +1.5VGS

AO4430: Rdson: 5.5mohm @ VGS=10V

12

13

D

2

G

S

8 7 6 5

RV42 0_0402_5%

0_0402_5%

1 2

AO4304L_SO8

PX@

@RV42

@

UV4

4

1

PX@

CV53

0.1U_0402_25V6

2

+3VS to +3VGS

+3VS +3VGS

3 1

PXS_PWREN

+5VALW

RV37

1 2

100K_0402_5%

PX@

2

G

1 2

0_0402_5%

13

D

PX@

QV6

QV6 2N7002K_SOT23-3

2N7002K_SOT23-3

S

PX@

RV38

@

1

CV50

0.1U_0402_16V4Z

2

2N7002_SOT23

300mil(7.2A)

QV1

@

QV1

@

D

S

1 2

13

RV39

@RV39

@

470_0603_5%

2

PXS_PWREN#

G

#9/11 need to confirm w/ Power team

1 2 3

PX@

1

CV49

4.7U_0603_6.3V6K

2

PX@

QV8

QV8 LP2301ALT1G_SOT23-3

LP2301ALT1G_SOT23-3

2

1

PX@

CV52

0.1U_0402_16V4Z

2

10U_0603_6.3V6M

PX@

1

CV46

PX@

2

PXS_PWREN#

1U_0603_10V6K

1

CV47

2

12

13

D

S

@

RV36

RV36 470_0603_5%

470_0603_5%

2

G

@

QV7

QV7 2N7002K_SOT23-3

2N7002K_SOT23-3

+1.8VS to +1.8VGS

+3VALW

12

PX@

RV35

RV35 100K_0402_5%

100K_0402_5%

PXS_PWREN#

1

PX@

OUT

QV9

IN

GND

3

QV9 DTC124EKAT146_SC59-3

DTC124EKAT146_SC59-3

2

PXS_PWREN<13,36,45,51,52>

4 4

PXS_PWREN

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2012/11/13 2013/11/12

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

ATI_MarsXT_M2_BACO POWER

Size Docum ent Number Rev

Custom

Date: Sheet of

D

Date: Sheet

VALGD MB L

E

18 57Tuesday, April 16, 2013

0.1

of

A

UV1G

PART 6 0F 9

AB39

GND

E39

GND

F34

GND

F39

GND

G33

GND

G34

GND

H31

GND

H34

GND

H39

GND

J31

M34 M39 N31 N34

R34

U31 U34

W31 W34

M17 M22 M24 N16 N18

N21 N23 N26

R15 R17

R20 R22 R24 R27

U15 U17

U20 U22 U24 U27

GND

J34

GND

K31

GND

K34

GND

K39

GND

L31

GND

L34

GND GND GND GND GND

P31

GND

P34

GND

P39

GND GND

T31

GND

T34

GND

T39

GND GND GND

V34

GND

V39

GND GND GND

Y34

GND

Y39

GND

F15

GND

F17

GND

F19

GND

F21

GND

F23

GND

F25

GND

F27

GND

F29

GND

F31

GND

F33

GND

F7

GND

F9

GND

G2

GND

G6

GND

H9

GND

J2

GND

J27

GND

J6

GND

J8

GND

K14

GND

K7

GND

L11

GND

L17

GND

L2

GND

L22

GND

L24

GND

L6

GND GND GND GND GND GND

N2

GND GND GND GND

N6

GND GND GND

R2

GND GND GND GND GND

R6

GND

T11

GND

T13

GND

T16

GND

T18

GND

T21

GND

T23

GND

T26

GND GND GND

U2

GND GND GND GND GND

U6

GND

V11

GND

V16

GND

V18

GND

V21

GND

V23

GND

V26

GND

W2

GND

W6

GND

Y15

GND

Y17

GND

Y20

GND

Y22

GND

Y24

GND

Y27

GND

PX@

GND

VSS_MECH VSS_MECH VSS_MECH

MARS-XTX M2_FCBGA962

1 1

2 2

3 3

4 4

A

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

B

A3 A37 AA16 AA18 AA2 AA21 AA23 AA26 AA28 AA6 AB12 AB15 AB17 AB20 AB22 AB24 AB27 AC11 AC13 AC16 AC18 AC2 AC21 AC23 AC26 AC28 AC6 AD15 AD17 AD20 AD22 AD24 AD27 AD9 AE2 AE6 AF10 AF16 AF18 AF21 AG17 AG2 AG20

AG6 AG9 AH21 AJ10 AJ11 AJ2 AJ28 AJ6 AK11 AK31 AK7 AL11 AL14 AL17 AL2 AL20

AL23 AL26 AL32 AL6 AL8 AM11 AM31 AM9 AN11 AN2 AN30 AN6 AN8 AP11 AP7 AP9 AR5 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B7 B9 C1 C39 E35 E5 F11 F13

AG22

NC

A39 AW1 AW39

MECH#1 MECH#2 MECH#3

B

+1.8VGS

1 2

RV43 0_0402_5%

PX@

TV12 PAD TEST POINT@TV12 PAD TE ST POINT@ TV13 PAD TEST POINT@TV13 PAD TE ST POINT@ TV14 PAD TEST POINT@TV14 PAD TE ST POINT@

+DP_VDDR

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

(DP_VDDR:1.8V@237mA/link )

+DP_VDDR

RV44 150_0402_1%PX@RV44 150_0402_1%PX@

12

C

D

UV1F

AN24

NC

AP24

NC

AP25

NC

AP26

NC

AU28

NC

AV29

NC

AP20

NC

AP21

NC

AP22

NC

AP23

NC

AU18

NC

AV19

NC

AH34

DP_VDDR

AJ34

DP_VDDR

AF34

DP_VDDR

AG34

DP_VDDR

AM37

DP_VDDR

AL38

DP_VDDR

AM32

DP_VDDR

AW28

NC

AW18

NC

AM39

DP_CALR

PX@

2012/11/13 2013/11/12

PART 8 0F 9

DP_VDDR DP_VDDC

DP GND

CALIBRATION

MARS-XTX M2_FCBGA962

Compal Secret Data

Deciphered Date

DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC

DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR

D

NC NC NC NC

(DP_VDDC:0.95V@280mA/link )

AP31 AP32 AN33 AP33 AL33 AM33 AK33 AK34 AN31

AP13 AT13 AP14 AP15

AN27 AP27 AP28 AW24 AW26 AN29 AP29 AP30 AW30 AW32 AN17 AP16 AP17 AW14 AW16 AN19 AP18 AP19 AW20 AW22 AN34 AP39 AR39 AU37 AF39 AH39 AK39 AL34 AV27 AR28 AV17 AR18 AN38 AM35 AN32

E

+0.95VGS

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

ATI_MarsXT_M2_PWR_GND

VALGD MB L

19 57Friday, April 12, 2013

E

0.1

A

B

C

D

E

SIT :220U 4V Y D2 ESR15M = SGA00000Y80

UV1E

AD11

AG10

AG26 AG27

AG23 AG24

AD12

AG11 AG13 AG15

AG28

AH29

AF26 AF27

AF23 AF24

AF11 AF12 AF13

AF15

AF28

AC7

AF7

AJ7 AK8 AL9 G11 G14 G17 G20 G23 G26 G29 H10

J7

J9 K11 K13

K8 L12 L16 L21 L23 L26

L7 M11 N11

P7 R11 U11

U7 Y11

Y7

UV1E

MEM I/O

VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1

LEVEL

TRANSLATION

VDD_CT VDD_CT VDD_CT VDD_CT

I/O

VDDR3 VDDR3 VDDR3 VDDR3

DVP

VDDR4 VDDR4 VDDR4 VDDR4

VOLTAGE

VOLTAGE SENESE

SENESE

FB_VDDC

FB_VDDCI

FB_GND

PX@

PART 5 0F 9

NC NC NC NC NC

NC NC_BIF_VDDC NC_BIF_VDDC

PCIE_PVDD

PCIE

PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC

BIF_VDDC

BACO

BIF_VDDC

VDDC

CORE

VDDC

VDDCI

CORE I/O

ISOLATED

VDDCI

MARS-XTX M2_FCBGA962

VDDCI

AA31 AA32 AA33 AA34 W30 Y31 V28 W29 AB37

G30 G31 H29 H30 J29 J30 L28 M28 N28 R28 T28 U28

N27 T27

AA15 AA17 AA20 AA22 AA24 AA27 AB16 AB18 AB21 AB23 AB26 AB28 AC17 AC20 AC22 AC24 AC27 AD18 AD21 AD23 AD26 AF17 AF20 AF22 AG16 AG18

AH22 AH27 AH28 M26 N24 R18 R21 R23 R26 T17 T20 T22 T24 U16 U18 U21 U23 U26 V17 V20 V22 V24 V27 Y16 Y18 Y21 Y23 Y26 Y28

AA13 AB13 AC12 AC15 AD13 AD16 M15 M16 M18 M23 N13 N15 N17 N20 N22 R12 R13 R16 T12 T15 V15 Y13

+1.5VGS

1

SGA00000Y80

1 1

VDDR1 MarsCR B Design

0.01u 5 0

0.1u 5 5 1u 0 5

2.2u 5 0 10u 3 5 220u 0 1

VDD_CT MarsC RB Design 120ohm 1 1

0.1u 1 1 1u 1 3 10u 1 1

VDDR3 MarsCR B Design 120ohm 1 0

2 2

0.1u 1 0 1u 2 3 10u 0 1

VDDR4 MarsCR B Design 220ohm 1 1

0.1u 1 1 1u 1 1 10u 1 0

3 3

1

CV60

+

CV66

2

PX@ CV60

PX@

10U_0603_6.3V6M

220U 4V Y D2 ESR15M

1

CV67

2

PX@ CV67

PX@

10U_0603_6.3V6M

3/1 SIT downsize to 0402, BLM15AX221SN1D (Murata)

1

CV69

CV70

CV68

2

10U_0603_6.3V6M

DEBUG@ CV69

DEBUG@

DEBUG@ CV70

DEBUG@

DEBUG@ CV68

DEBUG@

+1.8VGS +VDDC_CT

1 2

BLM15BD121SN1D_0402

+3VGS

1 2

BLM15BD121SN1D_0402

+1.8VGS

BLM15AX221SN1D 0402

SM01000MK00

For GDDR5, MVDDQ = 1.5V

(VDDR1:1.5V@3A,GDDR5:1125MHz )

1

CV71

2

PX@ CV71

PX@

1U_0402_6.3V6K

LV8

PX@LV8

PX@

LV9

PX@LV9

PX@

LV10

PX@LV10

PX@

CV74

CV73

CV72

2

PX@ CV74

PX@

PX@ CV73

PX@

PX@ CV72

PX@

1U_0402_6.3V6K

+VDDR3

10U_0603_6.3V6M

+VDDR4

1

CV75

2

PX@ CV75

PX@

1U_0402_6.3V6K

0.1U_0402_16V7K

(VDD_CT:1.8V@13mA )

1

CV89

2

PX@ CV89

PX@

10U_0603_6.3V6M

(VDDR3:3.3V@25mA)

1

CV93

CV92

2

PX@ CV92

PX@

1U_0402_6.3V6K

DEBUG@ CV93

DEBUG@

( VDDR4:1.8V@300mA)

+1.5VGS

1

CV76

2

PX@ CV76

PX@

1U_0402_6.3V6K

1

CV94

2

PX@ CV94

PX@

1

CV78

CV61

CV77

CV79

2

PX@ CV78

PX@

PX@ CV61

PX@

PX@ CV77

PX@

PX@ CV79

PX@

0.1U_0402_16V7K

1

CV91

CV90

2

DEBUG@ CV90

DEBUG@

1U_0402_6.3V6K

+VDDC_CT

PX@ CV91

PX@

0.1U_0402_16V7K

+VDDR3

1

CV95

2

PX@ CV95

PX@

+VDDR4

Route as differential pair

VGA_CORE_SEN<50>

TV15TEST POINT@ TV15TEST POINT@

VGA_VSS_SEN<50>

(PCIE_VDDR:1.8V@100mA )

+PCIE_VDDR

1

CV63

CV62

2

PX@ CV62

PX@

PX@ CV63

PX@

1U_0402_6.3V6K

0.1U_0402_16V7K

0.01U_0402_25V7K

(PCIE_VDDC:0.95V@2.5A_GEN2.0 )

+0.95VGS

1

CV81

CV80

2

PX@ CV81

PX@

PX@ CV80

PX@

1U_0402_6.3V6K

(BIF_VDDC:0.95V@1.4A)

+0.95VGS

1

CV87

CV86

2

PX@ CV87

PX@

PX@ CV86

PX@

1U_0402_6.3V6K

(VDDCI:0.9~1.15V@8.8A)

1

CV64

2

PX@ CV64

PX@

1

CV82

2

PX@ CV82

PX@

1U_0402_6.3V6K

CV88

PX@

10U_0603_6.3V6M

+PCIE_VDDR

LV7 0_0603_5%

1

CV84

2

10U_0603_6.3V6M

DEBUG@ CV84

DEBUG@

LV7 0_0603_5%

1

CV85

2

PX@ CV85

PX@

1

CV65

2

PX@ CV65

PX@

10U_0603_6.3V6M

1

CV83

2

PX@ CV83

PX@

1U_0402_6.3V6K

1

2

SHORT PAD@

1 2

+VGA_CORE

+1.8VGS

+0.95VGS

PCIE_VDDR Ma rsCRB Design

0.1u 0 2 1u 2 3 10u 1 1

PCIE_VDDC Ma rsCRB Design 1u 7 5 10u 2 1

+VGA_CORE

VGA_CORE Cap in power side sheet

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

C

2012/11/13 2013/11/12

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

ATI_MarsXT_M2_Power

VALGD MB L

E

of

20 57Friday, April 12, 2013

0.1

A

UV1H

PART 3 0F 9

GDDR5/DDR3

DQA0_0 DQA0_1 DQA0_2 DQA0_3 DQA0_4 DQA0_5 DQA0_6 DQA0_7 DQA0_8 DQA0_9 DQA0_10 DQA0_11 DQA0_12 DQA0_13 DQA0_14 DQA0_15 DQA0_16 DQA0_17 DQA0_18 DQA0_19 DQA0_20 DQA0_21 DQA0_22 DQA0_23 DQA0_24 DQA0_25 DQA0_26 DQA0_27 DQA0_28 DQA0_29 DQA0_30 DQA0_31 DQA1_0 DQA1_1 DQA1_2 DQA1_3 DQA1_4 DQA1_5 DQA1_6 DQA1_7 DQA1_8 DQA1_9 DQA1_10 DQA1_11 DQA1_12 DQA1_13 DQA1_14 DQA1_15 DQA1_16 DQA1_17 DQA1_18 DQA1_19 DQA1_20 DQA1_21 DQA1_22 DQA1_23 DQA1_24 DQA1_25 DQA1_26 DQA1_27 DQA1_28 DQA1_29 DQA1_30 DQA1_31

MVREFDA MVREFSA

NC NC NC

MEM_CALRP0

NC NC

PX@

GDDR5/DDR3

MEMORY INTERFACE A

MAA0_0/MAA_0 MAA0_1/MAA_1 MAA0_2/MAA_2 MAA0_3/MAA_3 MAA0_4/MAA_4 MAA0_5/MAA_5 MAA0_6/MAA_6 MAA0_7/MAA_7 MAA1_0/MAA_8

MAA1_1/MAA_9 MAA1_2/MAA_10 MAA1_3/MAA_11 MAA1_4/MAA_12

MAA1_5/MAA_BA2 MAA1_6/MAA_BA0 MAA1_7/MAA_BA1

WCKA0_0/DQMA_0

WCKA0B_0/DQMA_1

WCKA0_1/DQMA_2

WCKA0B_1/DQMA_3

WCKA1_0/DQMA_4

WCKA1B_0/DQMA_5

WCKA1_1/DQMA_6

WCKA1B_1/DQMA_7

EDCA0_0/QSA_0 EDCA0_1/QSA_1 EDCA0_2/QSA_2 EDCA0_3/QSA_3 EDCA1_0/QSA_4 EDCA1_1/QSA_5 EDCA1_2/QSA_6 EDCA1_3/QSA_7

DDBIA0_0/QSA_0B DDBIA0_1/QSA_1B DDBIA0_2/QSA_2B DDBIA0_3/QSA_3B DDBIA1_0/QSA_4B DDBIA1_1/QSA_5B DDBIA1_2/QSA_6B DDBIA1_3/QSA_7B

ADBIA0/ODTA0

ADBIA1/ODTA1

CLKA0

CLKA0B

CLKA1

CLKA1B

RASA0B RASA1B

CASA0B CASA1B

CSA0B_0 CSA0B_1

CSA1B_0 CSA1B_1

CKEA0 CKEA1

WEA0B WEA1B

MAA0_8/MAA_13 MAA1_8/MAA_14 MAA0_9/MAA_15

MAA1_9/RSVD

MARS-XTX M2_FCBGA962

G24 J23 H24 J24 H26 J26 H21 G21 H19 H20 L13 G16 J16 H16 J17 H17

A32 C32 D23 E22 C14 A14 E10 D9

C34 D29 D25 E20 E16 E12 J10 D7

A34 E30 E26 C20 C16 C12 J11 F8

J21 G19

H27 G27

J14 H14

K23 K19

K20 K17

K24 K27

M13 K16

K21 J20

K26 L15

H23 J19 M21 M20

C37

MDA0

C35

MDA1

A35

MDA2

E34

MDA3

G32

MDA4

D33

MDA5

F32

MDA6

E32

MDA7

D31

MDA8

F30

MDA9

C30

MDA10

A30

MDA11

F28

MDA12

C28

+VDD_MEM15_REFDA +VDD_MEM15_REFSA

1 2

PX@

MDA13 MDA14 MDA15 MDA16 MDA17 MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63

AG12

AH12

A28 E28 D27 F26 C26 A26 F24 C24 A24 E24 C22 A22 F22 D21 A20 F20 D19 E18 C18 A18 F18 D17 A16 F16 D15 E14 F14 D13 F12 A12 D11 F10 A10 C10 G13 H13

J13 H11 G10

G8

K9

K10

G9

A8 C8 E8 A6 C6 E6 A5

L18

L20

L27 N12

M27

M12

1 1

2 2

RV47 120_0402_1%

MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 A_BA2 A_BA0

A_BA1

ODTA0 ODTA1

CLKA0 CLKA0#

CLKA1 CLKA1#

RASA0# RASA1#

CASA0# CASA1#

CSA0#_0

CSA1#_0

CKEA0 CKEA1

WEA0# WEA1#

MAA13 MAA14

DQMA0 DQMA1 DQMA2 DQMA3 DQMA4 DQMA5 DQMA6 DQMA7

QSA0 QSA1 QSA2 QSA3 QSA4 QSA5 QSA6 QSA7

QSA#0 QSA#1 QSA#2 QSA#3 QSA#4 QSA#5 QSA#6 QSA#7

B

DQMA0 <22> DQMA1 <22> DQMA2 <22> DQMA3 <22> DQMA4 <23> DQMA5 <23> DQMA6 <23> DQMA7 <23>

QSA0 <22> QSA1 <22> QSA2 <22> QSA3 <22> QSA4 <23> QSA5 <23> QSA6 <23> QSA7 <23>

QSA#0 <22> QSA#1 <22> QSA#2 <22> QSA#3 <22> QSA#4 <23> QSA#5 <23> QSA#6 <23> QSA#7 <23>

ODTA0 <22> ODTA1 <23>

CLKA0 <22> CLKA0# <22>

CLKA1 <23> CLKA1# <23>

RASA0# <22> RASA1# <23>

CASA0# <22> CASA1# <23>

CSA0#_0 <22>

CSA1#_0 <23>

CKEA0 <22> CKEA1 <23>

WEA0# <22> WEA1# <23>

C

MDB[0..63]<24,25>

MAA[15..0]

A_BA[2..0]

MDA[0..63]

MAA[15..0] <22,23>

A_BA[2..0] <22,23>

MDA[0..63]<22,23>

MDB[0..63]

MAB[15..0]

B_BA[2..0]

MAB[15..0] <24,25>

B_BA[2..0] <24,25>

+VDD_MEM15_REFDB +VDD_MEM15_REFSB

MDB0 MDB1 MDB2 MDB3 MDB4 MDB5 MDB6 MDB7 MDB8 MDB9 MDB10 MDB11 MDB12 MDB13 MDB14 MDB15 MDB16 MDB17 MDB18 MDB19 MDB20 MDB21 MDB22 MDB23 MDB24 MDB25 MDB26 MDB27 MDB28 MDB29 MDB30 MDB31 MDB32 MDB33 MDB34 MDB35 MDB36 MDB37 MDB38 MDB39 MDB40 MDB41 MDB42 MDB43 MDB44 MDB45 MDB46 MDB47 MDB48 MDB49 MDB50 MDB51 MDB52 MDB53 MDB54 MDB55 MDB56 MDB57 MDB58 MDB59 MDB60 MDB61 MDB62 MDB63

D

AA12

E

UV1I

PART 4 0F 9

GDDR5/DDR3

DQB0_0 DQB0_1 DQB0_2 DQB0_3 DQB0_4 DQB0_5 DQB0_6 DQB0_7 DQB0_8 DQB0_9 DQB0_10 DQB0_11 DQB0_12 DQB0_13 DQB0_14 DQB0_15 DQB0_16 DQB0_17 DQB0_18 DQB0_19 DQB0_20 DQB0_21 DQB0_22 DQB0_23 DQB0_24 DQB0_25 DQB0_26 DQB0_27 DQB0_28 DQB0_29 DQB0_30 DQB0_31 DQB1_0 DQB1_1 DQB1_2 DQB1_3 DQB1_4 DQB1_5 DQB1_6 DQB1_7 DQB1_8 DQB1_9 DQB1_10 DQB1_11 DQB1_12 DQB1_13 DQB1_14 DQB1_15 DQB1_16 DQB1_17 DQB1_18 DQB1_19 DQB1_20 DQB1_21 DQB1_22 DQB1_23 DQB1_24 DQB1_25 DQB1_26 DQB1_27 DQB1_28 DQB1_29 DQB1_30 DQB1_31

MVREFDB MVREFSB

PX@

GDDR5/DDR3

MEMORY INTERFACE B

MARS-XTX M2_FCBGA962

MAB0_0/MAB_0 MAB0_1/MAB_1 MAB0_2/MAB_2 MAB0_3/MAB_3 MAB0_4/MAB_4 MAB0_5/MAB_5 MAB0_6/MAB_6 MAB0_7/MAB_7 MAB1_0/MAB_8

MAB1_1/MAB_9 MAB1_2/MAB_10 MAB1_3/MAB_11 MAB1_4/MAB_12

MAB1_5/BA2 MAB1_6/BA0 MAB1_7/BA1

WCKB0_0/DQMB_0

WCKB0B_0/DQMB_1

WCKB0_1/DQMB_2

WCKB0B_1/DQMB_3

WCKB1_0/DQMB_4

WCKB1B_0/DQMB_5

WCKB1_1/DQMB_6

WCKB1B_1/DQMB_7

EDCB0_0/QSB_0 EDCB0_1/QSB_1 EDCB0_2/QSB_2 EDCB0_3/QSB_3 EDCB1_0/QSB_4 EDCB1_1/QSB_5 EDCB1_2/QSB_6 EDCB1_3/QSB_7

DDBIB0_0/QSB_0B DDBIB0_1/QSB_1B DDBIB0_2/QSB_2B DDBIB0_3/QSB_3B DDBIB1_0/QSB_4B DDBIB1_1/QSB_5B DDBIB1_2/QSB_6B DDBIB1_3/QSB_7B

ADBIB0/ODTB0 ADBIB1/ODTB1

CLKB0

CLKB0B

CLKB1

CLKB1B

RASB0B RASB1B

CASB0B CASB1B

CSB0B_0 CSB0B_1

CSB1B_0 CSB1B_1

CKEB0 CKEB1

WEB0B WEB1B

MAB0_8/MAB_13 MAB1_8/MAB_14 MAB0_9/MAB_15

MAB1_9/RSVD

DRAM_RST

P8 T9 P9 N7 N8 N9 U9 U8 Y9 W9 AC8 AC9 AA7 AA8 Y8 AA9

H3 H1 T3 T5 AE4 AF5 AK6 AK5

F6 K3 P3 V5 AB5 AH1 AJ9 AM5

G7 K1 P1 W4 AC4 AH3 AJ8 AM3

T7 W7

L9 L8

AD8 AD7

T10 Y10

W10 AA10

P10 L10

AD10 AC10

U10 AA11

N10 AB11

T8 W8 U12 V12

AH11

MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 B_BA2 B_BA0 B_BA1

DQMB0 DQMB1 DQMB2 DQMB3 DQMB4 DQMB5 DQMB6 DQMB7

QSB0 QSB1 QSB2 QSB3 QSB4 QSB5 QSB6 QSB7

QSB#0 QSB#1 QSB#2 QSB#3 QSB#4 QSB#5 QSB#6 QSB#7

ODTB0 ODTB1

CLKB0 CLKB0#

CLKB1 CLKB1#

RASB0# RASB1#

CASB0# CASB1#

CSB0#_0

CSB1#_0

CKEB0 CKEB1

WEB0# WEB1#

MAB13 MAB14MAA15 MAB15

DRAM_RST#_R

DQMB0 <24> DQMB1 <24> DQMB2 <24> DQMB3 <24> DQMB4 <25> DQMB5 <25> DQMB6 <25> DQMB7 <25>

QSB0 <24> QSB1 <24> QSB2 <24> QSB3 <24> QSB4 <25> QSB5 <25> QSB6 <25> QSB7 <25>

QSB#0 <24> QSB#1 <24> QSB#2 <24> QSB#3 <24> QSB#4 <25> QSB#5 <25> QSB#6 <25> QSB#7 <25>

ODTB0 <24> ODTB1 <25>

CLKB0 <24> CLKB0# <24>

CLKB1 <25> CLKB1# <25>

RASB0# <24> RASB1# <25>

CASB0# <24> CASB1# <25>

CSB0#_0 <24>

CSB1#_0 <25>

CKEB0 <24> CKEB1 <25>

WEB0# <24> WEB1# <25>

C5 C3 E3 E1 F1 F3 F5 G4 H5 H6

J4 K6 K5

L4 M6 M1 M3 M5 N4 P6 P5 R4 T6 T1 U4 V6 V1 V3 Y6 Y1 Y3 Y5

AA4 AB6 AB1

AB3 AD6 AD1 AD3 AD5

AF1

AF3

AF6 AG4 AH5 AH6

AJ4

AK3

AF8

AF9 AG8 AG7

AK9

AL7 AM8 AM7

AK1

AL4 AM6 AM1 AN4

AP3

AP1

AP5

Y12

3 3

Ball to RV57 < 1"

+1.5VGS +1.5VGS

12

RV49

40.2_0402_1%

PX@

+VDD_MEM15_REFDA +VDD_MEM15_REFDBDRAM_RST#_R

12

1

CV98

RV55

100_0402_1%

PX@

4 4

A

CV98 1U_0402_6.3V6K

1U_0402_6.3V6K

2

PX@

RV50

40.2_0402_1%

RV56

100_0402_1%

12

PX@

+VDD_MEM15_REFSA +VDD_MEM15_REFSB+VDD_MEM15_REFDB

12

1

CV99

CV99 1U_0402_6.3V6K

PX@

1U_0402_6.3V6K

2

PX@

B

CV100 to RV57 < 200 mil CV100 to RV53 < 1"

1 2

PX@

DRAM_RST#<22,23,24,25>

DRAM_RST# is a daisy-chain ne t that connects to all VRAM

This basic topology should be used for DRAM_RST for DDR3/GDDR5.These Capacitors and Resistor values are an example only. The Series R and || Cap values will depend on the DRAM load and will have to be calculated for different Memory ,DRAM Load and board to pass Reset Signal Spec. Place all these components very close to GPU (Within 25mm) and keep all component close to each Other (within 5mm) except Rser2

PX@

RV53 51.1_0402_1%

+1.5VGS

12

RV48

4.7K_0402_5%

@

1 2

PX@

RV54 10_0402_5%

12

CV100

120P_0402_50V9

PX@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

C

RV57

4.99K_0402_1%

PX@

1 2

Compal Secret Data

2012/11/13 2013/11/12

Compal Secret Data

Deciphered Date

D

+1.5VGS +1.5VGS

RV51

40.2_0402_1%

PX@

RV58

100_0402_1%

PX@

12

1

CV101

CV101 1U_0402_6.3V6K

1U_0402_6.3V6K

2

PX@

Title

Size Document Number Rev

C

Date: Sheet of

12

RV52

40.2_0402_1%

PX@

12

RV59

100_0402_1%

PX@

Compal Electronics, Inc.

ATI_MarsXT_M2_MEM IF

VALGD MB L

1

CV102

CV102 1U_0402_6.3V6K

1U_0402_6.3V6K

2

PX@

E

0.1

21 57Friday, April 12, 2013

0.1

5

D D

C C

B B

MDA[0..31]<21>

MAA[15..0]<21,23>

CLKA0

RV60 40.2_0402_1%

CLKA0#

RV61 40.2_0402_1%

1 2

MARS@

1 2

MARS@

MDA[0..31]

MAA[15..0]

12

CV195

0.01U_0402_16V7K

MARS@

4

UV5

MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 MAA14 MAA15

QSA2 QSA0

DQMA2 DQMA0

QSA#2 QSA#0

12

4.99K_0402_1%

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

+1.5VGS

12

MARS@

RV62

+VREFC_A0

A_BA0<21,23> A_BA1<21,23> A_BA2<21,23>

CLKA0<21> CLKA0#<21> CKEA0<21>

ODTA0<21> CSA0#_0<21> RASA0#<21> CASA0#<21> WEA0#<21>

QSA2<21> QSA0<21>

DQMA2<21> DQMA0<21>

QSA#2<21> QSA#0<21>

DRAM_RST#<21,23,24,25>

RV84

RV84 240_0402_1%

240_0402_1%

MARS@

15mil

CV103

0.1U_0402_16V7K

CV103

0.1U_0402_16V7K

12

MARS@

RV64

4.99K_0402_1%

+VREFC_A0

12

MARS@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3

MDA23

F7

MDA19

F2

MDA22

F8

MDA18

H3

MDA21

H8

MDA17

G2

MDA20

H7

MDA16

D7

MDA0

C3

MDA5

C8

MDA1

C2

MDA6

A7

MDA3

A2

MDA4

B8

MDA2

A3

MDA7

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

+1.5VGS

3

QSA3<21> QSA1<21>

DQMA3<21> DQMA1<21>

QSA#3<21> QSA#1<21>

RV85

RV85 240_0402_1%

240_0402_1%

MARS@

+VREFC_A1

12

MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 MAA14 MAA15

A_BA0 A_BA1 A_BA2

CLKA0 CLKA0# CKEA0

ODTA0 CSA0#_0 RASA0# CASA0# WEA0#

QSA3 QSA1

DQMA3 DQMA1

QSA#3 QSA#1

DRAM_RST#

4.99K_0402_1%

UV6

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

+1.5VGS

12

MARS@

RV63

15mil

CV104

0.1U_0402_16V7K

CV104

0.1U_0402_16V7K

12

MARS@

RV65

12

MARS@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

+VREFC_A1

2

E3

MDA24

F7

MDA30

F2

MDA27

F8

MDA29

H3

MDA25

H8

MDA28

G2

MDA26

H7

MDA31

D7

MDA12

C3

MDA10

C8

MDA14

C2

MDA11

A7

MDA13

A2

MDA9

B8

MDA15

A3

MDA8

+1.5VGS

B2 D9 G7 K2 K8 N1 N9 R1 R9

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

1

+1.5VGS

CV105

10U_0603_6.3V6M

CV106

1U_0402_6.3V6K

CV108

1U_0402_6.3V6K

CV107

1U_0402_6.3V6K

CV109

1U_0402_6.3V6K

1

MARS@CV105

MARS@

MARS@CV106

MARS@

2

A A

5

SIT: Placed close to the UV5 SIT: Placed close to the UV6

4

1U_0402_6.3V6K

1

MARS@CV108

MARS@

MARS@CV107

MARS@

MARS@CV109

2

MARS@

2

CV111

0.1U_0402_16V7K

CV110

1U_0402_6.3V6K

1

MARS@CV110

MARS@

2

CV113

0.1U_0402_16V7K

CV112

0.1U_0402_16V7K

CV114

0.1U_0402_16V7K

1

@CV111

@

@CV113

@

@CV112

@

@CV114

2

@

2

+1.5VGS

CV115

10U_0603_6.3V6M

1

2

1

@CV115

@

2

+1.5VGS

CV123

0.1U_0402_16V7K

CV122

0.1U_0402_16V7K

CV121

1U_0402_6.3V6K

CV118

1U_0402_6.3V6K

CV117

1U_0402_6.3V6K

CV119

1U_0402_6.3V6K

CV116

10U_0603_6.3V6M

1

MARS@CV116

MARS@

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1U_0402_6.3V6K

CV120

1U_0402_6.3V6K

1

MARS@CV118

MARS@

MARS@CV117

MARS@

2

1

MARS@CV121

MARS@

MARS@CV119

MARS@

MARS@CV120

MARS@

2

2012/11/13 2013/11/12

CV124

0.1U_0402_16V7K

1

@CV123

@

@CV122

@

@CV124

@

2

Compal Secret Data

Deciphered Date

CV125

0.1U_0402_16V7K

1

@CV125

@

2

Compal Electronics, Inc.

Title

ATI_Whistler_M2_VRAM_B0

Size Document Number Rev

C 0.1

VALGD MB L

Date: Sheet of

1

22 57Friday, April 12, 2013

5

D D

MDA[32..63]<21>

MAA[15..0]<21,22>

C C

MDA[32..63]

MAA[15..0]

DRAM_RST#<21,22,24,25>

4

QSA4<21> QSA5<21>

DQMA4<21> DQMA5<21>

QSA#4<21> QSA#5<21>

3

UV7

M8

VREFCA

H1

VREFDQ

N3

MAA0

A0

P7

A1

P3

MAA2

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

MAA10

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

MAA15

A15/BA3

M2

A_BA0

QSA4 QSA5 QSA6

DQMA4 DQMA5 DQMA6

QSA#4 QSA#5 QSA#6

DRAM_RST#

12

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

A_BA0<21,22> A_BA1<21,22> A_BA2<21,22>

RV86

RV86 240_0402_1%

240_0402_1%

MARS@

+VREFC_A2

CLKA1<21> CLKA1#<21> CKEA1<21>

ODTA1<21> CSA1#_0<21> RASA1#<21> CASA1#<21> WEA1#<21>

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3

MDA38

F7

MDA36

F2

MDA39

F8

MDA34

H3

MDA35

H8

MDA33

G2

MDA37

H7

MDA32

D7

MDA42

C3

MDA44

C8

MDA40

C2

MDA46

A7

MDA43 MDA56

A2

MDA45

B8

MDA41

A3

MDA47

+1.5VGS

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

QSA6<21> QSA7<21>

DQMA6<21> DQMA7<21>

QSA#6<21> QSA#7<21>

RV87

RV87 240_0402_1%

240_0402_1%

MARS@

+VREFC_A3

12

MAA0MAA1 MAA1 MAA2MAA3 MAA3MAA4 MAA4MAA5 MAA5MAA6 MAA6MAA7 MAA7MAA8 MAA8MAA9 MAA9 MAA10MAA11 MAA11MAA12 MAA12MAA13 MAA13MAA14 MAA14 MAA15

A_BA0A_BA1 A_BA1A_BA2 A_BA2

CLKA1 CLKA1# CKEA1

ODTA1 CSA1#_0 RASA1# CASA1# WEA1#

QSA7

DQMA7

QSA#7

DRAM_RST#

2

UV8

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

1

E3

MDA49

F7

MDA51

F2

MDA48

F8

MDA52

H3

MDA50

H8

MDA53

G2

MDA55

H7

MDA54

D7

MDA60

C3

MDA57

C8

MDA63

C2 A7

MDA61

A2

MDA59

B8

MDA62

A3

MDA58

+1.5VGS

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

B B

1 2

CLKA1

MARS@

RV66 40.2_0402_1%

1 2

CLKA1#

MARS@

RV69 40.2_0402_1%

A A

12

CV196

0.01U_0402_16V7K

MARS@

+1.5VGS

CV128

10U_0603_6.3V6M

MARS@CV128

MARS@

1

2

1

MARS@CV131

MARS@

MARS@CV129

MARS@

MARS@CV130

MARS@

2

CV131

1U_0402_6.3V6K

CV129

1U_0402_6.3V6K

CV130

1U_0402_6.3V6K

4.99K_0402_1%

CV132

1U_0402_6.3V6K

1

MARS@CV132

MARS@

2

+1.5VGS

12

MARS@

RV68

15mil

+VREFC_A2

CV127

0.1U_0402_16V7K

CV127

0.1U_0402_16V7K

12

MARS@

RV71

12

CV133

1U_0402_6.3V6K

1

MARS@CV133

MARS@

2

MARS@

+1.5VGS

CV136

0.1U_0402_16V7K

CV137

0.1U_0402_16V7K

CV134

0.1U_0402_16V7K

@CV134

@

0.1U_0402_16V7K

CV135

0.1U_0402_16V7K

1

@CV136

@

@CV137

@

@CV135

@

2

CV138

10U_0603_6.3V6M

1

2

1

@CV138

@

2

+1.5VGS

CV139

10U_0603_6.3V6M

MARS@CV139

MARS@

1

2

SIT: Placed close to the UV7

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.5VGS

12

MARS@

RV67

4.99K_0402_1%

1U_0402_6.3V6K

15mil

+VREFC_A3

CV126

0.1U_0402_16V7K

CV126

0.1U_0402_16V7K

12

MARS@

RV70

CV141

1U_0402_6.3V6K

CV140

1

MARS@CV141

MARS@

MARS@CV140

MARS@

2

12

MARS@

CV146

0.1U_0402_16V7K

1

2

1

@CV145

@

MARS@CV144

MARS@

MARS@CV142

MARS@

MARS@CV143

MARS@

2

CV145

0.1U_0402_16V7K

CV144

1U_0402_6.3V6K

CV142

1U_0402_6.3V6K

CV143

1U_0402_6.3V6K

0.1U_0402_16V7K

CV147

0.1U_0402_16V7K

1

@CV146

@

@CV147

@

2

SIT: Placed close to the UV8

Compal Secret Data

2012/11/13 2013/11/12

Compal Secret Data

Deciphered Date

2

CV148

1

@CV148

@

2

Compal Electronics, Inc.

Title

ATI_Whistler_M2_VRAM_B1

Size Document Number Rev

C 0.1

VALGD MB L

Date: Sheet of

1

23 57Friday, April 12, 2013

5

D D

MDB[0..31]<21>

MAB[15..0]<21,25>

C C

CLKB0

RV72 40.2_0402_1%

CLKB0#

RV73 40.2_0402_1%

1 2

PX@

1 2

PX@

MDB[0..31]

MAB[15..0]

12

CV197

0.01U_0402_16V7K

PX@

4

UV9

M8

H1

N3

MAB0

P7

MAB1

P3

MAB2

N2

MAB3

P8

MAB4

P2

MAB5

R8

MAB6

R2

MAB7

T8

MAB8

R3

MAB9

L7

MAB10 MAB10

R7

MAB11

N7

MAB12

T3

MAB13

T7

MAB14

M7

MAB15 MAB15

M2

B_BA0<21,25> B_BA1<21,25> B_BA2<21,25>

N8

M3

J7 K7 K9

K1 L2 J3 K3 L3

F3

QSB2

C7

QSB0 QSB1

E7

DQMB2 DQMB3

D3

DQMB0 DQMB1

G3

QSB#2 QSB#3

B7

QSB#0 QSB#1

T2

L8

12

J1 L1 J9 L9

K4W1G1646E-HC12_FBGA96

X76@

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

BA0 BA1 BA2

CK CK CKE/CKE0

ODT/ODT0 CS/CS0 RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET

ZQ/ZQ0

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

QSB2<21> QSB0<21>

DQMB2<21> DQMB0<21>

QSB#2<21> QSB#0<21>

RV88

RV88 240_0402_1%

240_0402_1%

CLKB0<21> CLKB0#<21> CKEB0<21>

DRAM_RST#<21,22,23,25>

PX@

+VREFC_B0

ODTB0<21> CSB0#_0<21> RASB0#<21> CASB0#<21> WEB0#<21>

3

UV10

B_BA0 B_BA1 B_BA2

CLKB0 CLKB0# CKEB0

ODTB0 CSB0#_0 RASB0# CASB0# WEB0#

QSB3

DRAM_RST#

12

MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9

MAB11 MAB12 MAB13 MAB14

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

E3

MDB19

F7

MDB20

F2

MDB22

F8

MDB16

H3

MDB23

H8

MDB17

G2

MDB21

H7

MDB18

D7

MDB0

C3

MDB4

C8

MDB1

C2

MDB6

A7

MDB3

A2

MDB7

B8

MDB2

A3

MDB5

+1.5VGS

B2 D9 G7 K2 K8 N1 N9 R1 R9

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

QSB3<21> QSB1<21>

DQMB3<21> DQMB1<21>

QSB#3<21> QSB#1<21>

RV89

RV89 240_0402_1%

240_0402_1%

PX@

+VREFC_B1

2

E3

MDB26

F7

MDB30

F2

MDB24

F8

MDB29

H3

MDB27

H8

MDB28

G2

MDB25

H7

MDB31

D7

MDB15

C3

MDB10

C8

MDB14

C2

MDB11

A7

MDB12

A2

MDB9

B8

MDB13

A3

MDB8

+1.5VGS

B2 D9 G7 K2 K8 N1 N9 R1 R9

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

1

+1.5VGS

12

PX@

RV74

4.99K_0402_1%

B B

+1.5VGS

CV157

0.1U_0402_16V7K

CV156

1U_0402_6.3V6K

CV153

1U_0402_6.3V6K

CV152

1U_0402_6.3V6K

CV151

10U_0603_6.3V6M

1

PX@CV153

PX@

PX@CV152

PX@

PX@CV151

PX@

2

A A

1U_0402_6.3V6K

CV154

1U_0402_6.3V6K

CV155

1U_0402_6.3V6K

1

2

1

@CV157

@

PX@CV156

PX@

PX@CV154

PX@

PX@CV155

PX@

2

SIT: Placed close to the UV9

5

4.99K_0402_1%

CV158

0.1U_0402_16V7K

1

@CV158

@

2

PX@

RV76

15mil

12

0.1U_0402_16V7K

+1.5VGS

CV161

10U_0603_6.3V6M

@CV161

@

+VREFC_B0

CV149

12

PX@

+1.5VGS

CV167

1U_0402_6.3V6K

CV163

1U_0402_6.3V6K

CV164

1U_0402_6.3V6K

CV162

10U_0603_6.3V6M

1

2

10U_0603_6.3V6M

1

PX@CV163

PX@

PX@CV164

PX@

PX@CV162

PX@

2

1U_0402_6.3V6K

CV166

1U_0402_6.3V6K

CV165

1U_0402_6.3V6K

1

2

1

PX@CV167

PX@

PX@CV166

PX@

PX@CV165

PX@

2

SIT: Placed close to the UV10

Security Classification

4

3

+1.5VGS

12

PX@

RV75

4.99K_0402_1%

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PX@

RV77

15mil

+VREFC_B1

CV150

0.1U_0402_16V7K

CV150

0.1U_0402_16V7K

12

PX@

CV171

0.1U_0402_16V7K

CV169

0.1U_0402_16V7K

CV170

0.1U_0402_16V7K

1

@CV171

@

@CV169

@

@CV170

@

2

Compal Secret Data

2012/11/13 2013/11/12

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

ATI_Whistler_M2_VRAM_A0

Size Document Number Rev

C 0.1

VALGD MB L

Date: Sheet of

1

24 57Friday, April 12, 2013

5

D D

C C

MDB[32..63]<21>

MAB[15..0]<21,24>

MDB[32..63]

MAB[15..0]

DRAM_RST#<21,22,23,24>

4

B_BA0<21,24> B_BA1<21,24> B_BA2<21,24>

QSB4<21> QSB5<21>

DQMB4<21> DQMB5<21>

QSB#4<21> QSB#5<21>

RV90

RV90 240_0402_1%

240_0402_1%

PX@

3

UV11

+VREFC_B2

CLKB1<21> CLKB1#<21> CKEB1<21>

ODTB1<21> CSB1#_0<21> RASB1#<21> CASB1#<21> WEB1#<21>

M8

VREFCA

H1

VREFDQ

N3

MAB0 MAB0

A0

P7

MAB1 MAB1

A1

P3

MAB2 MAB2

A2

N2

MAB3 MAB3

A3

P8

MAB4 MAB4

A4

P2

MAB5 MAB5

A5

R8

MAB6 MAB6

A6

R2

MAB7 MAB7

A7

T8

MAB8 MAB8

A8

R3

MAB9 MAB9

A9

L7

MAB10 MAB10

A10/AP

R7

MAB11

A11

N7

MAB12 MAB12

A12

T3

MAB13 MAB13

A13

T7

MAB14 MAB14

A14

M7

MAB15 MAB15

A15/BA3

M2

B_BA0 B_BA1 B_BA2

QSB4 QSB5

DQMB4 DQMB5

QSB#4 QSB#5

DRAM_RST# DRAM_RST#

12

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3

MDB33

F7

MDB37

F2

MDB35

F8

MDB39

H3

MDB32

H8

MDB36

G2

MDB34

H7

MDB38

D7

MDB44

C3

MDB41

C8

MDB47

C2

MDB43

A7

MDB45

A2

MDB40

B8

MDB46

A3

MDB42

+1.5VGS

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

QSB6<21> QSB7<21>

DQMB6<21> DQMB7<21>

QSB#6<21> QSB#7<21>

RV91

RV91 240_0402_1%

240_0402_1%

PX@

+VREFC_B3

12

B_BA0 B_BA1 B_BA2

CLKB1 CLKB1# CKEB1

ODTB1 CSB1#_0 RASB1# CASB1# WEB1#

QSB6 QSB7

DQMB6 DQMB7

QSB#6 QSB#7

MAB11

M8 H1

N3

N2

R8 R2

R3

R7 N7

M7

M2 N8 M3

C7

D3

G3

UV12

VREFCA VREFDQ

A0

P7

A1

P3

A2 A3

P8

A4

P2

A5 A6 A7

T8

A8 A9

L7

A10/AP A11 A12

T3

A13

T7

A14 A15/BA3

BA0 BA1 BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL DQSU

E7

DML DMU

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

2

E3

MDB55

F7

MDB50

F2

MDB54

F8

MDB51

H3

MDB53

H8

MDB49

G2

MDB52

H7

MDB48

D7

MDB56

C3

MDB59

C8

MDB63

C2

MDB62

A7

MDB57

A2

MDB61

B8

MDB58

A3

MDB60

+1.5VGS

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

1

4.99K_0402_1%

+1.5VGS

CV184

10U_0603_6.3V6M

1

@CV184

@

2

+1.5VGS

12

PX@

RV78

15mil

+VREFC_B3

CV172

0.1U_0402_16V7K

CV172

0.1U_0402_16V7K

12

PX@

12

RV82

PX@

CV189

1U_0402_6.3V6K

CV190

1U_0402_6.3V6K

CV188

1U_0402_6.3V6K

CV185

10U_0603_6.3V6M

1

PX@CV185

PX@

2

1U_0402_6.3V6K

CV187

1U_0402_6.3V6K

CV186

1U_0402_6.3V6K

1

PX@CV186

PX@

2

1

PX@CV189

PX@

PX@CV188

PX@

PX@CV187

PX@

2

CV191

0.1U_0402_16V7K

CV193

0.1U_0402_16V7K

CV194

0.1U_0402_16V7K

1

PX@CV190

PX@

@CV191

@

2

0.1U_0402_16V7K

1

@CV193

@

@CV194

2

@

2

SIT: Placed close to the UV12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/11/13 2013/11/12

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

ATI_Whistler_M2_VRAM_A1

Size Document Number Rev

C 0.1

VALGD MB L

Date: Sheet of

1

25 57Friday, April 12, 2013

+1.5VGS

1 2

CLKB1

PX@

RV79 40.2_0402_1%

1 2

CLKB1#

PX@

RV81 40.2_0402_1%

B B

A A

RV81 40.2_0402_1%

12

CV198

0.01U_0402_16V7K

PX@

12

PX@

RV80

4.99K_0402_1%

+1.5VGS +1.5VGS

CV174

10U_0603_6.3V6M

PX@CV174

PX@

15mil

+VREFC_B2

CV173

0.1U_0402_16V7K

CV173

0.1U_0402_16V7K

12

PX@

RV83

1U_0402_6.3V6K

1

2

12

PX@

CV178

1U_0402_6.3V6K

CV177

1U_0402_6.3V6K

CV176

1U_0402_6.3V6K

CV175

1

PX@CV175

PX@

2

1

PX@CV178

PX@

PX@CV177

PX@

PX@CV176

PX@

2

CV180

0.1U_0402_16V7K

CV179

1U_0402_6.3V6K

1

@CV180

@

PX@CV179

PX@

2

CV183

0.1U_0402_16V7K

CV182

0.1U_0402_16V7K

CV181

0.1U_0402_16V7K

1

@CV183

@

@CV182

@

@CV181

@

2

SIT: Placed close to the UV11

5

4

A

B

C

D

E

+3VS +3VS_PS

30mil 30mil

Close to Pin3

10U_0603_6.3V6M

1 1

Close to Pin18

10U_0603_6.3V6M

Close to L29

2 2

DEBUG@

22U_0603_6.3V6M

1

2

R289

1 2

0.1U_0402_16V4Z

1

C411

2

0.1U_0402_16V4Z

1

C413

C414

2

DEBUG@

0.1U_0402_16V4Z

1

C418

C419

2

0_0603_5%

1

C410

2

Close to Pin13

Close to Pin27

0.1U_0402_16V4Z

22U_0603_6.3V6M

0.1U_0402_16V4Z

SHORT PAD@

1

C412

2

0.1U_0402_16V4Z

1

C415

2

1

C420

2

+DP_V33

Close to Pin18

1

C416

2

0.1U_0402_16V4Z

1

C421

2

Close to Pin7

+SWR_VDD

0.1U_0402_16V4Z

1

C417

2

+SWR_V12

R375 0_0805_5%

DP0_TXP0_C<7> DP0_TXN0_C<7>

Reserved for EC programming ROM Need EC confirm

DP0_HPD<7>

SHORT PAD@

1 2

+1.2VS

20110124 Modify

+3VS_PS

R294

100K_0402_5%

LVDS@

L28

L28 FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

LVDS@

L87

L87 FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

1 2

L29

4.7UH_PG031B-4R7MS_1.1A_20%

@

DP0_AUXP_C<7> DP0_AUXN_C<7>

R123

1 2

1K_0402_5%

LVDS@

12

+DP_V33

12

+SWR_VDD

+SWR_LX+SWR_V12

CSCL CSDA

DP0_HPD_R

R295

LVDS@R295

12K_0402_1%

Change to 12Kohm 1% (DG ref.) 20101114

LVDS@

1 2

40mil

60mil

60mil 60mil60mil

3

13 18

12 11 27

7

2 1

5 6

9

10

32

8 4

U9

DP_V33

SWR_VDD PVCC

SWR_LX SWR_VCCK VCCK DP_V12

AUX_P AUX_N

LANE0P LANE0N

CIICSCL1 CIICSDA1

HPD

DP_REXT DP_GND

S

A000069200

MIIC_SDA MIIC_SCL EDID_DATA EDID_CLK

Power

LVDS

RTD2132S

DP-IN

GPIO(PWM OUT)

GPIO(Panel_VCC)

GPIO(PWM IN)

GPIO

GPIO(BL_EN)

LVDS

Other

RTD2132S-VE-CG_QFN32_5X5

MIICSCL1

EDID

ROM

MIICSCL0

MIICSDA0

1 2

RA24 0_0402_5%DEBUG@RA24 0_0402_5%DEBUG@

1 2

RA15 0_0402_5%DEBUG@RA15 0_0402_5%DEBUG@

1 2

RA11 0_0402_5%DEBUG@RA11 0_0402_5%DEBUG@

1 2

RA10 0_0402_5%DEBUG@RA10 0_0402_5%DEBUG@

2132R@

TXEC+

TXEC-

TXE2+

TXE2-

TXE1+

TXE1-

TXE0+

TXE0-

MIICDA1

GND

19 20

21 22

23 24

25 26

14 15 16 17

29 28

31 30

33

TL_INVT_PWM

APU_INVT_PWM

MIIC_SCL MIIC_SDA

TEST POINT@

T14

T14 T15

T15

TEST POINT@

LVDS_ACLK <27> LVDS_ACLK# <27>

LVDS_A2 <27> LVDS_A2# <27>

LVDS_A1 <27> LVDS_A1# <27>

LVDS_A0 <27> LVDS_A0# <27>

TL_ENVDD <27>

ENBKL <36>

EDID_CLK < 27> EDID_DATA <27>

12

R826

R826 100K_0402_5%

100K_0402_5%

TL_INVT_PWM <27>

EDID_DATA EDID_CLK MIIC_SDA MIIC_SCL

4.7K_0804_8P4R_5%

1 8 2 7 3 6 4 5

RP16

LVDS@

+3VS_PS

Vendor advise reserve

0:RevE W/O EEPROM

Vendor advise reserve

+3VS

2

G

2132S@

12

13

R1458

4.7K_0402_5%

D

Q7

Q7 2N7002K_SOT23-3

2N7002K_SOT23-3

S

APU_INVT_PWM

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

Panel PWM

3 3

DP_INT_PWM<7>

4 4

Panel PWMPanel PWM

12

R63

4.7K_0402_5%

A

1 2

R62 2.2K_0402_5%

2132S@

12

R59

R59 47K_0402_5%

47K_0402_5%

2132S@

C

Q8

2

B

E

MMBT3904_NL_SOT23-3

3 1

2132S@

1 2

R54 0_0402_5%

SHORT PAD@

Issued Date

CSDA CSCL

C

SHORT PAD@

1 2

R357 0_0402_5%

1 2

R340 0_0402_5%

SHORT PAD@

Compal Secret Data

2012/11/13 2013/11/12

Compal Secret Data

TL_DATA <36>

TL_CLK <36>

Deciphered Date

3/1: SIT

SDA/Pin#30

Title

LVDS Translator - RTD2132S

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

SCL/Pin#31

0 0

1 1 R eserved

Compal Electronics, Inc.

VALGD MB L

10

01

E

FunctionConfig.

Reserved

Internal mode 2132R EP mode 2132S

26 57Friday, April 12, 2013

0.1

5

4

3

2

1

LCD POWER CIRCUIT

+3VS

W=60mils

+3VS

W=60mils

D D

12

@

R685 0_0402_5%

C C

BKOFF#<36>

BKOFF#

U72

5

VIN

4

SS

APL3512ABI-TRG_SOT23-5

TL_ENVDD<26>

12

R716

R716 10K_0402_5%

10K_0402_5%

VOUT

GND

EN

1

+LCDVDD_C ONN

2

3

+LCDVDD_C ONN

1

C516

2

4.7U_0603_6.3V6K

R435

CMOS@R 435

CMOS@

150K_0402_5%

CMOS_ON#<36>

150K_0402_5%

4.7V

1

C520

0.1U_0402_16V4Z

2

(20 MIL)

Q83

Q83 PMV65XP_SOT23-3~D

PMV65XP_SOT23-3~D

S

CMOS@C520

CMOS@

VGA LCD/PANEL BD. Conn.

C539

680P_0402_50V7K

EMI@

CMOS Camera

CMOS@

D

13

G

2

1

2

JCMOS1

2

112

JUMP_43X39@

(20 MIL)

1

CMOS@

C518

0.1U_0402_16V4Z

2

EMI@

R813

1 2

FBMA-L11-201209-221L MA30T_0805

C541

4.7U_0805_25V6-K

@

R02

R296 for CMOS shake issue reserve

B++LEDVDD

For EMI

+3VS_CMOS

1

2

C519

@C519

@

10U_0603_6.3V6M

JLVDS1

112

B B

LVDS_ACLK<26> LVDS_ACLK#<26>

LVDS_A2< 26> LVDS_A2#<26>

EDID_DATA<26>

1/21 SIT change PN to SM070001N00 for action plan

L58

EMI@

L58

EMI@

USB20_P3<13>

USB20_N3<13>

A A

USB20_P3 USB20_P3_R

USB20_N3

5

1

4

WCM- 2012-900T_4P

SM070001N00

2

3

2

3

USB20_N3_R

Security Classification

2012/11/13 2013/11/12

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

2012/11/13 2013/11/12

Compal Secret Data

Deciphered Date

3

EDID_CLK< 26>

+3VS

BKOFF#

2

334 556 778 9910 111112 131314 151516 171718 191920 212122 232324 252526 272728 292930

GND31GND

ACES_87142-3041-BS

ME@

Title

Size Document Number Rev

Custom

Date: Sheet of

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

32

Compal Electronics, Inc.

LVDS/CAMERA

VALGD MB L

USB20_N3_R USB20_P3_R

(60 MIL)

+LCDVDD_C ONN +3VS +3VS_CMOS

1

TL_INVT_PWM <26>

LVDS_A1 <26> LVDS_A1# <26>

LVDS_A0 <26> LVDS_A0# <26>

27 57Friday, April 12, 2013

0.1

A

1 1

DAC_RED<12>

DAC_GRN<12>

DAC_BLU<12>

RV195

RV196

RV194

150_0402_1%

2 2

+5VS

RV196

150_0402_1%

B

1/21 SIT downsize to 0402, BLM15BB121SN1D 0402 (Murata)

BLM15BB121SN1D 0402 SM010005X00

1

C522

2

10P_0402_50V8J

C524

C523

2

10P_0402_50V8J

C

L30

EMI@ L30

EMI@

L31

E

L31

E

MI@

L32

EMI@ L32

EMI@

1

2

1

C525

2

10P_0402_50V8J

RED

GREEN

BLUE

1

C527

C526

2

10P_0402_50V8J

NC11

T66PADTEST POINT@ T66PADTEST POINT@

RED

CRT_DDC_DAT_CONN GREEN

JVGA_HS_R BLUE

JVGA_VS_R

CRT_DDC_CLK_CONN

D

+5V_DISPLAY

JCRT1

6

11

1 7

12

2 8

16

G

13

17

G

3 9

14

4 10 15

5

SUYIN_070546FR015S251ZR

ME@

E

1

C531

2

C531

0.1U_0402_16V4Z

2

+3VS

C537

A

U10

1

VCC_SYNC

2

VCC_VIDEO

7

1

CRT_DDC_DATA<12>

2

CRT_DDC_CLK<12>

CRT_VSYNC<12>

CRT_HSYNC<12>

VCC_DDC

10

DDC_IN1

11

DDC_IN2

13

SYNC_IN1

15

SYNC_IN2

6

GND

TPD7S019-15DBQR_SSOP16

B

SYNC_OUT1

SYNC_OUT2

VIDEO1

VIDEO2

VIDEO3

DDC_OUT1

DDC_OUT2

BYP

8

1 2

C6 0.22U_0402_10V6KC6 0.22U_0402_10V6K

3

RED

4

GREEN

5

BLUE

9

CRT_DDC_DAT_CONN

12

CRT_DDC_CLK_CONN

14

JVGA_VS

16

JVGA_HS

1 2

R3334

22_0402_5%

R3335

1 2

22_0402_5%

+5V_DISPLAY

12

R31

4.7K_0402_5%

JVGA_VS_R

JVGA_HS_R

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

12

R3333

4.7K_0402_5%

Compal Secret Data

2012/11/13 2013/11/12

C

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

CRT Connector

VALGD MB L

28 57Friday, April 12, 2013

E

0.1

C529

0.1U_0402_16V4Z

3 3

4 4

0.1U_0402_16V4Z

5

1/21 SIT change PN to SM070003K00 for action plan

L35

EMI@ SM070003K00L35

EMI@ SM070003K00

1

4

WCM-2012HS-900T

L36

1

4

WCM-2012HS-900T

L37

1

4

WCM-2012HS-900T

L38

1

4

WCM-2012HS-900T

18 27 36 45

HDMI_CLK+_CK

HDMI_CLK-_CK

HDMI_TX0+_CK

HDMI_TX0-_CK

HDMI_TX1+_CK

HDMI_TX1-_CK

HDMI_TX2+_CK

HDMI_TX2-_CK

HDMIDAT_NB HDMIDAT_R HDMICLK_NB HDMICLK_R

HDMI_CLK+_CK<7>

HDMI_CLK-_CK<7>

D D

HDMI_TX0+_CK<7>

HDMI_TX0-_CK<7>

HDMI_TX1+_CK<7>

HDMI_TX1-_CK<7>

HDMI_TX2+_CK<7>

HDMI_TX2-_CK<7>

C C

+3VS

+5V_DISPLAY

B B

RP21

2.2K_0804_8P4R_5%

2

3

EMI@ SM070003K00L36

EMI@ SM070003K00

2

3

EMI@ SM070003K00L37

EMI@ SM070003K00

2

3

EMI@ SM070003K00L38

EMI@ SM070003K00

2

3

HDMICLK_NB<7>

HDMIDAT_NB<7>

ESD

D32

@ESD@

HDMIDAT_R

HDMICLK_R

HDMI_DET HDMI_DET HDMI_TX1-_CONN

9

10

8

9

7

6

6 5

D32

1

2

4

3

8

1

HDMIDAT_R

2

HDMICLK_R

4

5

3

HDMI_CLK-_CONN

HDMI_CLK+_CONN

HDMI_TX1+_CONN

4

HDMI_CLK+_CONNHDMI_CLK+_CONN

HDMI_CLK-_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_TX2+_CONN

HDMI_TX2-_CONN

+3VS

5

4

@ESD@

9

10

8

9

7

6

6 5

TMDS_B_HPD#<7>

Q63A

2

2N7002DW-T /R7_SOT363-6

61

3

Q63B

2N7002DW-T /R7_SOT363-6

D28

1

HDMI_CLK-_CONN

1

2

HDMI_CLK+_CONN

2

4

HDMI_TX1-_CONN

4

5

HDMI_TX1+_CONN

3

8

HDMICLK_R

HDMIDAT_R

R485

1M_0402_5%

TMDS_B_HPD#

DMN66D0LDW-7_SOT 363-6

HDMI_TX0-_CONN

HDMI_TX0+_CONN

HDMI_TX2-_CONN

HDMI_TX2+_CONN

3

1 2

+3VS

2

61

Q93A

@ESD@

9

10

8

9

7

6

6 5

0.1U_0402_16V4Z

R488

R488 20K_0402_5%

20K_0402_5%

1 2

D33

1

HDMI_TX0-_CONN

1

2

HDMI_TX0+_CONN

2

4

HDMI_TX2-_CONN

4

5

HDMI_TX2+_CONN

3

8

C544

+5VS

2

U73

1

2

IN

AP2330W-7_SC59-3

OUT

GND

3

2

W=40mils

0.1U_0402_16V4Z

+5V_DISPLAY

C543

HDMI_DET

+5V_DISPLAY

HDMIDAT_R HDMICLK_R

HDMI_CLK-_CONN

HDMI_CLK+_CONN HDMI_TX0-_CONN

HDMI_TX0+_CONN HDMI_TX1-_CONN

HDMI_TX1+_CONN HDMI_TX2-_CONN

HDMI_TX2+_CONN

1

2

1

ZZZ3

45@

HDMI Logo

RO0000003HM

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11 10

9 8 7 6 5 4 3 2 1

GND

CK_shield

GND

CK+

GND

D0-

GND D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+

CONCR_099ATAC19 NBLCNF

ME@

20 21 22 23

For LAN CHASSIS1_GND

#11/5 follow Design Guide#48890

HDMI_CLK-_CONN HDMI_CLK+_CONN HDMI_TX0-_CONN HDMI_TX0+_CONN HDMI_TX1-_CONN HDMI_TX1+_CONN HDMI_TX2+_CONN HDMI_TX2-_CONN

1 2

R784 604_0402_1%R784 604_0402_1%

1 2

R786 604_0402_1%R786 604_0402_1%

1 2

R788 604_0402_1%R788 604_0402_1%

1 2

R790 604_0402_1%R790 604_0402_1%

1 2

R792 604_0402_1%R792 604_0402_1%

1 2

R796 604_0402_1%R796 604_0402_1%

1 2

R807 604_0402_1%R807 604_0402_1%

1 2

R800 604_0402_1%R800 604_0402_1%

DMN66D0LDW-7_SOT 363-6

HDMI_GND

34

Q93B

5

+3VS

YSCLAMP0524P_SLP2510P8-10-9

A A

YSCLAMP0524P_SLP2510P8-10-9

5

YSCLAMP0524P_SLP2510P8-10-9

Security Classification

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

YSCLAMP0524P_SLP2510P8-10-9

Compal Secret Data

2012/11/13 2013/11/12

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Rev

B

Date: Sheet of

2

Date: Sheet

HDMI CONN

VALGD MB L

0.1

of

29 57Friday, April 12, 2013

1

A

B

C

D

E

Mini-Express Card for WLAN/WiMAX(Half)

1 1

@

C548

+3VS_WLAN

1

2

@

1

C547

0.1U_0402_16V4Z

2

WL_OFF# <12> APU_PCIE_RST# <11,16,31>

FCH_SCLK0 <10,13,9> FCH_SDATA0 <10,13,9>

JUMP@

J6

JUMP_43X79

JWLN1

FCH_PCIE_WAKE#<13>

BT_DISABLE#<12>

2 2

EC_TX<36 ,37> EC_RX<36,37>

3 3

CLKREQ_WLAN#<13>

CLK_PCIE_WLAN1#<11>

CLK_PCIE_WLAN1<11>

PCIE_PRX_DTX_N1<5> PCIE_PRX_DTX_P1<5>

PCIE_PTX_C_DRX_N1<5> PCIE_PTX_C_DRX_P1<5>

For EC to detect debug card insert.

100_0402_1%

R505

1 2 1 2

R506

100_0402_1%

+3VS_WLAN

EC_RX_R

R507

R507 100K_0402_5%

100K_0402_5%

1 2

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

GND1

GND2

LOTES_AAA-PCI-046-K01

ME@

JUMP_43X79

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

80mil

112

+3VS_WLAN+3VS

2

+1.5VS

+3VS_WLAN

1 2

R501 0_0402_5%@R501 0_0402_5%@

1 2

R502 0_0402_5%@R502 0_0402_5%@

4.7U_0603_6.3V6K

USB20_N2 <13> USB20_P2 <13>

Reserve for SW mini-pcie debug card. Series resistors closed to KBC side.

4 4

Security Classification

2012/11/13 2013/11/12

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/11/13 2013/11/12

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Mini-Card/NEW Card/SIM

VALGD MB L

E

0.1

30 57Friday, April 12, 2013

5

For LAN

D D

LAN_PWR_ON#<36>

C C

B B

A A

LAN_PWR_ON#

APU_PCIE_RST#<11,16,30>

PCIE_PRX_DTX_N0<5>

PCIE_PRX_DTX_P0<5>

PCIE_PTX_C_DRX_N0<5>

PCIE_PTX_C_DRX_P0<5>

CLK_PCIE_LAN#<11>

CLK_PCIE_LAN<11>

LAN_WAKE#<36>

5

Vendor recommand reseve the PU resistor close LAN chip

+3V_LAN

CLKREQ_LAN#<13>

Near Pin13

+3VALW

JUMP@

J12

112

JUMP_43X79

S

G

1 2

DEBUG@

Near Pin31

1

CL19

2

0.1U_0402_16V4Z

G

QL1

2

PMV65XP_SOT23-3~D

RL3

12

10K_0402_5%

Vendor recommand reseve the PU resistor close LAN chip

2

CL7

0.1U_0402_16V7K

1

1 2

RL4 4.7K_0402 _5%

DEBUG@

Place Close to Chip

CL9 0.1U_0402_16V7KCL9 0.1U_0402_16V7K

CL11 0.1U_0402_16V7KCL11 0.1U_0402_16V7K

1 2

RL7 0_0402_5%RL7 0_0402_5%

1 2

RL9 4.7K_0402_5%

DEBUG@

1 2

RL11 4.7K_0402_5%

1

CL17

CL18

2

0.1U_0402_16V4Z

Near Pin19

2

D

13

Near Pin6

GCLK_LAN_25MHZ<38>

4

+3V_LAN

APU_PCIE_RST#

PCIE_PRX_C_DTX_N0

PCIE_PRX_C_DTX_P0

APU_PCIE_RST#

PCIE_WAKE#_R

LAN_XTALO LAN_XTALI

+1.1_AVDDL +1.1_AVDDL +1.1_AVDDL +1.1_AVDDL_L +1.1_AVDDL

1

CL20

CL21

2

1U_0402_6.3V4Z

0.1U_0402_16V4Z

DEBUG@

value shoud be discuss ORB 5P

CL28

15P_0402_50V8J

NOGCLK@

4

UL1

8172@UL1

8172@

8172

UL1

29

TX_N

Atheros

30

36

35

32 33

2

3

25 26

28 27

7 8

4

13 19 31 34

6

41

RL13 0_0402_5%

1

2

Atheros

TX_P

AR8151/AR8161

RX_N

RX_P

REFCLK_N REFCLK_P

PERST#

WAKE#

SMCLK SMDATA

NC TESTMODE

XTLO XTLI

CLKREQ#

AVDDL AVDDL AVDDL AVDDL AVDDL_REG/AVDD L

GND

AR8162-BL3A-R_QFN40_5X5

8162@

GCLK@

1 2

YL1

NOGCLK@YL1

NOGCLK@

4

NC

OSC

1

OSC

25MHZ_10PF_7V25000014

NC

15P_0402_50V8J

NOGCLK@

1

2

3

2

LED_0 LED_1 LED_2

TRXN0 TRXP0 TRXN1 TRXP1 TRXN2 TRXP2 TRXN3 TRXP3

RBIAS

VDD33

VDDCT/ISOLAN

DVDDL/PPS

DVDDL_REG/DVDD L

AVDDH/AVDD33

AVDDH

AVDDH_REG

CL27

5P_0402_50V8C

GCLK@

LAN_XTALI

LAN_XTALO

1

CL29

2

3

Close together

LL1

SWR@LL1

SWR@

+LX_R +LX

1

CL1

CL2

2

1000P_0402_50V7K

SWR@

Close to Pin40

38

RL12 10K_0402_5%

39 23

12

MDI0-

11

MDI0+

15

MDI1-

14

MDI1+

18 17 21 20

10

LAN_RBIAS

1

+3V_LAN

40

+LX

LX

5

+1.7_VDDCT

24 37

+LX_R

16

+3V_LAN

22

+2.7_AVDDH

9

+2.7_AVDDH

DEBUG@

Near Pin9

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

1 2

4.7UH_SIA4012-4R7M_20%

1

Note: Place Close to LAN chip LL1 DCR< 0.15 ohm

2

Rate current > 1A

CL3

0.1U_0402_16V4Z

10U_0603_6.3V6M

10U

SWR@

12

LDO@

1 2

RL8 2.37K_0402_1%RL8 2.37K_0402_1%

Place Close to P IN1

+LX

RL10 30K_0402_5%RL10 30K_0402_5%

1 2

+2.7_AVDDH

1

CL22

2

1

CL23

CL24

2

1U_0402_6.3V4Z

0.1U_0402_16V4Z

Near Pin22

3

mount RL12 if us e LDO modue

0.1U_0402_16V4Z

+LX

MDI0- <32> MDI0+ <32> MDI1- <32> MDI1+ <32>

Place Close to PIN1

CL12

CL13

@

+3V_LAN

1

CL25

CL26

DEBUG@

2

1U_0402_6.3V4Z

0.1U_0402_16V4Z

Near

in37

P

Compal Secret Data

2012/11/13 2013/11/12

Compal Secret Data

1 2

1000P_0402_50V7K

DEBUG@

Deciphered Date

2

CL4

Place close to Pin34

+3V_LAN

1

CL14

2

1U_0402_6.3V4Z

0.1U_0402_16V4Z

2

1

CL16

CL15

2

10U_0603_6.3V6M

DEBUG@

1

LL3

FBMA-L11160808601LMA10T_2P

1 2

1

CL5

2

1U_0402_6.3V4Z

0.1U_0402_16V4Z

DEBUG@

LL2

FBMA-L11160808601LMA10T_2P

1 2

1

CL6

2

4.7U_0603_6.3V6K

1

CL8

CL10

2

1U_0402_6.3V4Z

0.1U_0402_16V4Z

Place close to Pin16

don't @ (could be B C cost done)

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

LAN-AR8162/8172

VALGD MB L

Friday, April 12, 2013

1

SWR@LL3

SWR@

+3V_LAN

+LX_R+1.1_AVDDL+1.1_AVDDL_L

31 57

0.1

5

4

3

2

1

ESD

@ESD@

DL1

AZC099-04S.R7G_SOT23- 6

Place Close to TL1

D D

DL1

AZC099-04S.R7G_SOT23- 6

1

I/O1

2

GND

I/O3

VDD

4

MDI0+MDI1+

5

Reserve gas tube for EMI go rural solution

1'S PN:SC300001G00 2'S PN:SC300002E00

3

I/O2

I/O4

6

MDI1-MDI0-

CL30

EMI@CL30

RL14

1 2

75_0805_5%

EMI@RL14

EMI@

1 2

1000P_1206_2KV7K

CHASSIS1_GND

TL1

MDI0+<31> MDI0-<31>

C C

1

CL31

EMI@ C L31

EMI@

0.01U_0402_16V7K

2

MDI1+<31> MDI1-<31>

MDI0+ MDI0-

MDI1+ MDI1-

1

TD+

2

TD-

3

CT

4

NC

5

NC

6

CT

7

RD+ RD-8RX-

MHPC_NS681612A

TX+

RX+

16

MDO0+

15

MDO0-

TX-

14

MCT

CT

13

NC

12

NC

11

MCT

CT

10

MDO1+

9

MDO1-

DLL1

DLL1 BS4200N-C-LV_SMB-F2

BS4200N-C-LV_SMB-F2

EMI@

Place Close to TL1

12

1 2

CL63 0.1U_0603_50V7K@EMI@ CL63 0.1U_0 603_50V7K@EMI@

1 2

CL61 0.1U_0603_50V7K@EMI@ C L61 0.1U_0603_50V7K@EMI@

1 2

CL32 0.1U_0402_16V7KESD@ CL32 0.1U_0402_1 6V7KESD@

1 2

CL33 0.1U_0402_16V7KESD@ CL33 0.1U_0402_1 6V7KESD@

SIT: For ESD request

JLAN1

MCT

B B

MCT

MDO1-

MCT

MDO1+

MDO0-

MDO0+

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

PS_HPKR0125-08A1A0R

ME@

SHLD1

SHLD2

CHASSIS1_GND

10

9

CHASSIS1_GND

A A

Security Classification

2012/11/13 2013/11/12

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/11/13 2013/11/12

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Rev

B

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

LAN_Transformer

VALGD MB L

1

0.1

32 57Friday, April 12, 2013

5

4

3

2

1

2 Channel

D D

SIT: Change power rial from +3VS to +3VGS.

SMSC thermal sensor placed near VRAM

+3VGS

SA00001Z710

U99

REMOTE1+<17>

2200P_0402_50V7K

C C

REMOTE1-<17>

2200P_0402_50V7K

C587

1

2

+3VGS

REMOTE1+

REMOTE1-

1 2

R335

4.7K_0402_5%

@

SIT: Change power rial from +3VS to +3VGS.

B B

MINI WLAN CPU

H1

H1 H_3P3

H_3P3

FAN1 Conn

+5VS

R581

12

SHORT PAD@

0_0603_5%

2

C591

C591 10U_0603_6.3V6M

10U_0603_6.3V6M

1

A A

EC_TACH<36>

EC_FAN_PWM<36>

JFAN1

1

2

3

4

5

G5

6

G6

ACES_85205-04001

ME@

SP020008X00

1

ME@

ZZZ

14@

ZZZ

14@

VALGC_DIS_PCB

DA6000YR100

ZZZ1

15@

ZZZ1

15@

VALGD_DIS_PCB

DA6000YR000

VGA

H2

H2 H_3P3

H_3P3

1

ME@

U99

1

VDD

2

D+

3

D-

THERM#4GND

ADM1032ARMZ-2REEL_MSOP8

SMBus address: 4D 1001101x

H3

H4

H_3P3

1

ME@

H14

H14 H_2P8

H_2P8

ME@

8

SCLK

7

SDATA

6

ALERT#

5

H6

H5

H5 H_3P8

H_3P8

1

ME@

H15

H15 H_2P8

H_2P8

1

ME@

H_3P8

1

ME@

H7

H7 H_3P8

H_3P8

ME@

EC_SMB_CK2

EC_SMB_DA2

1

SIV: change to H=4p6

H21

H20

H20 H_2P8

H_2P8

1

ME@

H21 H_4P6

H_4P6

1

ME@

H19

H19 H_2P8

H_2P8

1

ME@

EC_SMB_CK2 <17,36>

EC_SMB_DA2 <17,36>

H23

H22

H_2P8

1

ME@

FD1

1

ME@

R

H16

H16 H_3P0X4P0N

H_3P0X4P0N

ME@

FD2

FD3

FD4

1

ME@

H25

H24

H24 H_3P0N

H_3P0N

1

ME@

H25 H_3P0N

H_3P0N

1

ME@

H17

H17 H_7P0N

H_7P0N

1

ME@

1

E

M/B

橢橢橢

橢橢

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/11/13 2013/11/12

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Fintek-Thermal IC/FAN/screw

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

VALGD MB L

33 57Friday, April 12, 2013

1

0.1

A

B

C

D

E

F

G

H

SATA HDD Conn.

Near Connector

SATA_ITX_C_DRX_P0<12> SATA_ITX_C_DRX_N0<12>

SATA_DTX_C_IRX_N0<12>

SATA_DTX_C_IRX_P0<12>

1 1

+5VS_HDD

Near HDD

1

C598

C598 1000P_0402_50V7K

1000P_0402_50V7K

2

SATA_ITX_C_DRX_P0 SATA_ITX_C_DRX_N0

SATA_DTX_C_IRX_P0

1

C599

0.1U_0402_16V4Z

2

1

C602

C602 10U_0603_6.3V6M

10U_0603_6.3V6M

2

12

C1184 0.01U_0402_25V7KC1184 0.01U_0402_25V7K

12

C1185 0.01U_0402_25V7KC1185 0.01U_0402_25V7K

1 2

C596 0.01U_0402_25V7KC596 0.01U_0402_25V7K

1 2

C597 0.01U_0402_25V7KC597 0.01U_0402_25V7K

J10

+5VS

J10

112

JUMP_43X39

JUMP@

2

SATA_ITX_DRX_P0 SATA_ITX_DRX_N0

SATA_DTX_IRX_N0SATA_DTX_C_IRX_N0 SATA_DTX_IRX_P0

+5VS_HDD

JHDD1

1

GND

2

RX+

3

RX-

4

GND

5

TX-

6

TX+

7

GND

8

3.3V

9

3.3V

10 11 12 13 14 15 16 17 18 19 20 21 22

boss

3.3V

boss GND GND

GND GND

GND 5V 5V 5V GND Rsv GND 12V 12V 12V

LCN_ASF98-2231S10-0002

ME@

26 25

24 23

ODD Power Control

2 2

3 3

4 4

Per-MP: 4/3 un-pop ODD power control circuits

+5VS

+5VALW

12

@

R568

10K_0402_5%

ODD_EN<12>

2

IN

1 2

1

OUT

@

GND

Q100

Q100 DTC124EKAT146_SC59-3

DTC124EKAT146_SC59-3

3

R675

R675 100K_0402_5%

100K_0402_5%

@

JUMP@

J9

112

JUMP_43X79

S

G

2

1

2

D

13

Q99

Q99 PMV65XP_SOT23-3~D

PMV65XP_SOT23-3~D

@

C607

0.01U_0402_25V7K

+5V_ODD

1

2

1

@

C604

0.1U_0402_16V4Z

2

C608

C608 10U_0603_6.3V6M

10U_0603_6.3V6M

N

ear Connector

SATA_ITX_C_DRX_P1<12> SATA_ITX_C_DRX_N1<12>

SATA_DTX_C_IRX_N1<12>

SATA_DTX_C_IRX_P1<12>

ODD_DETECT#<13>

SATA_ITX_C_DRX_P1 SATA_ITX_C_DRX_N1

SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_P1 SATA_DTX_IRX_P1_15

1 2

R711 0_0402_5%@R711 0_0402_5%@

ODD_DA#_FCH<13>

C605 0.01U_0402_25V7K15@C605 0.01U_0402_25V7K15@ C606 0.01U_0402_25V7K15@C606 0.01U_0402_25V7K15@

C618 0.01U_0402_25V7K15@C618 0.01U_0402_25V7K15@ C617 0.01U_0402_25V7K15@C617 0.01U_0402_25V7K15@

ODD_DA#<36>

@

1 2 1 2

+3VS

D

1 3

+3VS

Q96

Q96 2N7002K_SOT23-3

2N7002K_SOT23-3

2

Near Connector

1 2

C616 0.01U_0402_25V7K14@C616 0.01U_0402_25V7K14@

SATA_ITX_C_DRX_N1

SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_P1 SATA_DTX_IRX_P1_14

1 2

C615 0.01U_0402_25V7K14@C615 0.01U_0402_25V7K14@

1 2

C614 0.01U_0402_25V7K14@C614 0.01U_0402_25V7K14@

1 2

C613 0.01U_0402_25V7K14@C613 0.01U_0402_25V7K14@

SIT: 3/1 Change footprint of JHDD1 from SANTA_191501-1_22P to LCN_ASF98-2231S10-0002_22P (DC010005W00 toDC010009C00)

FOR 15"

SATA ODD FFC Conn.

SATA_ITX_DRX_P1_15 SATA_ITX_DRX_N1_15

SATA_DTX_IRX_N1_15

SHORT PAD@

ODD_DA#

1 2

R555

10K_0402_5%

1 2

R710 0_0402_1%

#11/9 follow QAWYA

ODD_DETECT#_R +5V_ODD

Co-lay

S

G

FOR 14"

SATA ODD Conn.

1

SATA_ITX_DRX_P1_14SATA_ITX_C_DRX_P1 SATA_ITX_DRX_N1_14

SATA_DTX_IRX_N1_14

ODD_DETECT#_R +5V_ODD

ODD_DA#

2 3 4 5 6 7

8

9 10 11 12

JODD2

1

2

3

4

5

6

7

8

9

10

ACES_88058-100N

ME@

SP010016C00

JODD1

GND A+ AGND BB+ GND

DP +5V +5V MD GND GND13GND

SANTA_202801-1

ME@

GND GND

GND GND GND

11 12

14 15 16 17

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/11/13 2013/11/12

D

Compal Secret Data

Deciphered Date

E

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

F

Date: Sheet of

Compal Electronics, Inc.

HDD/ODD/BT Connector

VALGD MB L

G

0.1

34 57Friday, April 12, 2013

H

0.1

5

CX20757 High Definition Audio Codec SoC With Integrated Class-D Stereo Amplifier. An integrated 5 V to 3.3 V Low-dropout voltage regulator (LDO).

An integrated 3.3 V to 1.8V Low-dropout voltage regulator (LDO).

D D

C C

For EMI

EMI@

1 2

CA64 0.1 U_0402_16 V7K

EMI@

1 2

CA65 0.1 U_0402_16 V7K

EMI@

1 2

CA66 0.1 U_0402_16 V7K

B B

SIT:For no Speaker Hum Noise f eature

1 2

HDA_SDIN0<13>

1 2

RA4 0_0402_ 1%

SHORT PAD@

RA25 0_0 402_5%RA25 0_0402 _5%

1 2

RA26 0_0 402_5%@RA26 0_0402 _5%@

@EMI@

CA7

22P_040 2_50V8J

HDA_RST_AUD IO#<13>

HDA_BITCLK_ AUDIO<13 >

1 2

RA9 33_0402_ 5%RA9 33_0402_5 %

EC_MUTE#<36>

@

+3VLP

+3VS

Should be same supply rail as used for PCH HDA bus controller section

+3VS

HDA_SYNC_A UDIO<13>

HDA_SDOUT_A UDIO< 13>

Internal analog MIC

Internal SPEAKER

1

CA8

2

+VDDIO_HDA

1

CA16

2

@

@EMI@

1 2

RA21

33_0402 _5%

1U_0603_10V4Z

4.7U_0603_6.3V6K

+3V_AVDD_ HP

1

CA9

2

0.1U_0402_16V4Z

1

CA17

2

0.1U_0402_16V4Z

HDA_RST_AUD IO#

HDA_BITCLK_ AUDIO HDA_SYNC_A UDIO HDA_SDIN0 _R HDA_SDOUT_A UDIO

PC_BEEP

MIC_IN

SPK_L2+ SPK_L1-

SPK_R2+ SPK_R1-

4

+VREF_1V6 5

1

CA1

1

CA5

CA6

2

@

0.1U_0402_16V4Z

4.7U_0603_6.3V6K

+3VS

+LDO_1.8V

CA1

2

1U_0603_10V4Z

1

@

CA10

CA15

2

1U_0603_10V4Z

0.1U_0402_16V4Z

10 mils

1

CA24

CA25

2

0.1U_0402_16V4Z

4.7U_0603_6.3V6K

9

5 8 6 4

10 39

1

40

36 37

12 14

17 15

2

7

3

UA1

VDD_IO

FILT_1.8

RESET#

BIT_CLK SYNC SDATA_IN SDATA_OUT

PC_BEEP SPKR_MUTE#

DMIC_DAT/GPIO1 DMIC_CLK / MUSIC_REQ/GPIO0

MUSIC_REQ/GPIO0/PORTC_L_MIC GPIO1/PORTC_R_MIC

LEFT+ LEFT-

RIGHT+ RIGHT-

GND

41

1

CA2

2

0.1U_0402_16V4Z

29

18

DVDD_3.3

VDDO_3.3

VREF_1.65V

CA3 vendor suggest change to 2.2U

2

CA4

CA3

1

2.2U_0603_6.3V4Z

For Layout

27

24

28

LPWR_5.0 RPWR_5.0

AVDD_5V

AVDD_3.3

AVDD_HP

CLASS-D_REF

JSENSE

MICBIASB MICBIASC

PORTB_L_LINE

PORTB_R_LINE

PORTD_A_MIC PORTD_B_MIC

HGNDA HGNDB

PORTA_L PORTA_R

AVEE FLY_P FLY_N

CX20751 -11Z_QFN40

AVDD_3.3 pinis output of

1

internal LDO. NOT connect to external supply.

2

0.1U_0402_16V4Z

1

CA18

CA19

@

2

4.7U_0603_6.3V6K

13 16 11

38

JSENSE

34 35

32

MICB_L

33

MICB_R

30

APPLE_M IC

31

NOKIA_MIC

25

HGNDA

26

HGNDB

22

HP_L

23

HP_R

21 19 20

CA29 1U_0 603_10V4 ZCA29 1 U_0603_10 V4Z

0.1U_0402_16V4Z

1 2

+LDO_OUT_3 .3V

+MICBIASB +MICBIASC

Universal Jack

External MIC

Headphone

3

Layout Note:Path from +5VS to LPWR_5.0 RPWR_5.0 must be very low resistance (<0.01 ohms)

+5VS

1

CA21

CA20

2

0.1U_0402_16V4Z

1

For Layout

CA26

2

Please bypass caps very close to device.

0.1U_0402_16V4Z

1

CA23

CA22

@

2

0.1U_0402_16V4Z

4.7U_0603_6.3V6K

+5VS

For EMI

APPLE_M IC HGNDB NOKIA_MIC HGNDA HP_L HPOUT_L

RA16 100_04 02_1%RA16 100 _0402_1% RA12 100_04 02_1%RA12 100 _0402_1% RA13 15_040 2_5%RA13 15_0 402_5% RA14 15_040 2_5%RA14 15_0 402_5%

1 2 1 2 1 2 1 2

2

JSENSE

1 2

RA5 5.11 K_0402_1%RA5 5.11K _0402_1%

RA6 10K_ 0402_1%RA6 10K_ 0402_1%

1 2

RA7 20K_ 0402_1%RA7 20K_ 0402_1%

1 2

RA8 39.2 K_0402_1%RA8 39.2K _0402_1%

For Universal jack

SIV:For (Port-B) THD+N

1 2

CA28 2.2U_0402 _6.3V6MCA28 2.2U_0 402_6.3V6 M

1 2

CA27 2.2U_0402 _6.3V6MCA27 2.2U_0 402_6.3V6 M

1

Sense resistors must be connected same power that is used for VAUX_3.3

+3VS

mount RA6 on the Jack Sense circuit to configure Port-C for mono MIC.

PLUG_IN

Don't support LINE_IN function RA7 could be @

PLUG_IN <37>

HGNDA, HGNDB 80mils

HGNDB <37> HGNDA <37>

HPOUT_RHP_R

HPOUT_L <37> HPOUT_R <37>

For Universal jack

SIT:For (Port-B) THD+N

CA36

MICB_L HP_L

2

1

CA30

CA35

1

2

0.1U_0402_16V4Z

2.2U_0603_6.3V4Z

MICB_R HP _R

+MICBIASB

1 2

RA17 100_04 02_1%RA17 100 _0402_1%

1 2

RA18 100_04 02_1%RA18 100 _0402_1%

1 2

RA20 3K_040 2_5%RA20 3K_0402 _5%

1 2

RA19 3K_040 2_5%RA19 3K_0402 _5%

CA36

1 2

2.2U_040 2_6.3V6M

CA46

1 2

2.2U_040 2_6.3V6M

follow vendor suggest & reserver default design

JSPK1

PC Beep

EC Beep

ICH Beep

A A

BEEP#<3 6>

HDA_SPKR<13>

1 2

CA37 0.1U_0402 _16V4ZCA37 0. 1U_0402_1 6V4Z

1 2

CA45 0.1U_0402 _16V4ZCA45 0. 1U_0402_1 6V4Z

5

12

RA22

RA22 10K_040 2_5%

10K_040 2_5%

DEBUG@

RA492

1 2

33_0402 _5%

PC_BEEP

MIC1

WM-64PC Y_2P

MIC@

Place colose to Codec chip

+MICBIASC

12

RA23

2.2K_04 02_5%

CA41 1U_0603 _10V4ZCA41 1U_0 603_10V4 Z

1

EXT_MIC

2

GNDA

1

2

CA44

0.1U_0402_16V4Z

@

4

1 2

wide 40MIL

MIC_IN

3

SPK_R1SPK_R2+ SPK_L1SPK_L2+

1 2

LA1 FB MA-L11-1608 08-121LMT_06 03EMI@ LA1 FBMA-L11-160808 -121LMT_0603EMI@

1 2

LA2 FB MA-L11-1608 08-121LMT_06 03EMI@ LA2 FBMA-L11-160808 -121LMT_0603EMI@

1 2

LA3 FB MA-L11-1608 08-121LMT_06 03EMI@ LA3 FBMA-L11-160808 -121LMT_0603EMI@

1 2

LA4 FB MA-L11-1608 08-121LMT_06 03EMI@ LA4 FBMA-L11-160808 -121LMT_0603EMI@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

SPK_R1-_ CONN SPK_R2+_ CONN SPK_L1-_ CONN SPK_L2+ _CONN

+5VS

ESD

SPK_R1-_ CONN

1000P_0402_50V7K

SPK_R2+_ CONN SPK_L1-_ CONN

EMI@

1

CA39

CA38

2

1000P_0402_50V7K

EMI@

1

CA43

CA40

2

1000P_0402_50V7K

EMI@

SIT:For EMI requriement

Compal Secret Data

2012/11/13 2013/11/12

Compal Secret Data

Deciphered Date

2

DA3

6

5

4

AZC099-04 S.R7G_SOT23 -6

@ESD@

3

I/O4

VDD

I/O3

SPK_L2+ _CONN

I/O2

2

GND

1

I/O1

Compal Electronics, Inc.

Title

Size Docu ment Number Rev

Custom

Date: Sheet

Date: Sheet of

CX20757-11Z Codec

VALGD MB L

JSPK1

6

GND2

5

GND1

4

3

2

1

SP02000H700

ME@

ACES_88 231-04001

1

0.1

of

35 57Friday, April 12, 2013

A

C428

C434

2

1

EC_SMB_DA1 EC_SMB_CK1 EC_SMB_CK2 EC_SMB_DA2

#9/11 follow LA-9901

ECAGND

2

1

KSO[0..15]<37>

KSI[0..7]<37>

EC_SMB_CK2_SUS<7> EC_SMB_DA2_SUS<7>

RTC_CLK<11,15>

KSO[0..15]

KSI[0..7]

EC_SMB_CK1<42,43> EC_SMB_DA1<42,43>

EC_VGA_EN<50>

ADP_ID_CLOSE<41>

EC_TX<30,37> EC_RX<30,37>

FCH_PWRGD<13,48> NOVO#<37>

1 2

R318 0_0402_5%

SHORT PAD@

1 2

L331

+3VALW +EC _AVCC

1 1

2 2

885N@ R314

885N@

3 3

+3VALW

+3VS

L331

FBM-11-160808-601-T_0603

1 2

+3VALW

R306 47K_0402_5%R 306 47K_0402_5%

+3VS

12

R314 10K_0402_5%

10K_0402_5%

EC_FAN_PWM

RP24

2.2K_0804_8P4R_5%

+3VALW

0.1U_0402_16V4Z

1 2

L332 FBM-11-160808 -601-T_0603L332 FBM-11-160808 -601-T_0603

0.1U_0402_16V4Z

18 27 36 45

C423

0.1U_0402_16V4Z

C423

0.1U_0402_16V4Z

1

2

GATEA20<13> KBRST#<13>

LPC_FRAME#<11>

LPC_AD3<11> LPC_AD2<11> LPC_AD1<11> LPC_AD0<11>

CLK_PCI_EC<11,15>

PLT_RST#<11>

EC_SCI#< 13>

BATT_LEN#<42>

KSO16<37> KSO17<37>

EC_SMB_CK1 EC_SMB_DA1

EC_SMB_CK2_SUS

EC_SMB_DA2_SUS

PM_SLP_S3#<13> PM_SLP_S5#<13>

EC_SMI#<13> CMOS_ON#<27>

ODD_DA#<34>

EC_TACH<33>

NUM_LED#< 37>

R379

+3VALW

C424

0.1U_0402_16V4Z

C424

0.1U_0402_16V4Z

SERIRQ<11>

NUVOTON EC use

0_0402_5%885N@

B

R312

SHORT PAD@

12

0_0603_5%

1

2

LPC_AD3 LPC_AD2 LPC_AD1 BATT_TEMP LPC_AD0

PLT_RST# EC_RST# EC_SCI#

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17

EC_SMI#

EC_PME# EC_TX EC_RX

XCLKI

XCLKO

R320

100K_0402_5%

+3VALW_EC

C429

1000P_0402_50V7K

C429

1000P_0402_50V7K

1

@EMI@

2

1

GATEA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ

4

LPC_FRAME#

5

LPC_AD3

7

LPC_AD2

8

LPC_AD1

10

LPC_AD0

12

CLK_PCI_EC

13

PCIRST#/GPIO05

37

EC_RST#

20

EC_SCII#/GPIO0E

38

GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

EC_SMB_CK1/GPIO44

78

EC_SMB_DA1/GPIO45

79

EC_SMB_CK2/GPIO46

80

EC_SMB_DA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

GPIO0A

17

GPIO0B

18

GPIO0C

19

GPIO0D

25

EC_INVT_PWM/GPIO11

28

FAN_SPEED1/GPIO14

29

EC_PME#/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

PCH_PWROK/GPIO18

34

SUSP_LED#/GPIO19

36

NUM_LED#/GPIO1A

122

XCLKI/GPIO5D

123

XCLKO/GPIO5E

12

C437

C437 20P_0402_50V8

20P_0402_50V8

1 2

POP for susclk implemented 20100810

C427

1000P_0402_50V7K

C427

1000P_0402_50V7K

LPC & MISC

1

@EMI@

2

Int. K/B

Int. K/B Matrix

Matrix

SM Bus

+3VLP

C535 100P_0402_50V8J

9

22

33

96

125

111

EC_VDD0

EC_VDD/VCC

PWM Output

AD Input

DA Output

PS2 Interface

CPU1.5V_S3_GATE/GPXIOA00

SPI Device Interface

SPI Flash ROM

GPIO

GND/GND

GND0

11

24

35

94

113

885N@

1 2

+EC_AVCC

67

EC_VDD/AVCC

BATT_CHG_LED#/GPIO52

BATT_LOW_LED#/GPIO55

EC_RSMRST#/GPXIOA03 EC_LID_OUT#/GPXIOA04

PROCHOT_IN/GPXIOA05

H_PROCHOT#_EC/GPXIOA06

VCOUT0_PH/GPXIOA07

GPO

PBTN_OUT#/GPXIOA09

PCH_APWROK/GPXIOA10

SA_PGOOD/GPXIOA11

GPI

PECI_KB9012/GPXIOD07

AGND/AGND

69

ECAGND

C

U12

GPIO0F

BEEP#/GPIO10

GPIO12

ACOFF/GPIO13

BATT_TEMP/GPIO38

GPIO39

ADP_I/GPIO3A

GPIO3B GPIO42

IMON/GPIO43

DAC_BRIG/GPIO3C

EN_DFAN1/GPIO3D

IREF/GPIO3E

CHGVADJ/GPIO3F

EC_MUTE#/GPIO4A

USB_EN#/GPIO4B

CAP_INT#/GPIO4C

EAPD/GPIO4D

TP_CLK/GPIO4E

TP_DATA/GPIO4F

WOL_EN/GPXIOA01 HDA_SDO/GPXIOA02 VCIN0_PH/GPXIOD00

SPIDI/GPIO5B

SPIDO/GPIO5C SPICLK/GPIO58 SPICS#/GPIO5A

ENBKL/GPIO40

PECI_KB930/GPIO41

FSTCHG/GPIO50

CAPS_LED#/GPIO53

PWR_LED#/GPIO54

SYSON/GPIO56

VR_ON/GPIO57

PM_SLP_S4#/GPIO59

BKOFF#/GPXIOA08

AC_IN/GPXIOD01

EC_ON/GPXIOD02

ON/OFF/GPXIOD03

LID_SW#/GPXIOD04

SUSP#/GPXIOD05

GPXIOD06

V18R

KB9012QF-A2_LQFP128_14X14

D

4

/11 SVT: change RP11 form 10K to 100K (8P4R) SD309100300

USB_ON# EC_TACH VGA_GATE# EC_PME#

21

ADP_65

23

BEEP#

26 27

ACOFF

63 64

VGA_IMVP_IMON

65 66

ADP_ID

75

BRDID

76

ENBKL

68

ADP_90

70

ADP_135

71 72

83 84

USB_ON#

85

TL_CLK

86

TL_DATA

87

TP_CLK

88

TP_DATA

97

EC_TS_ON#

98 99 109

119

FRD#SPI_SO

120

FWR#SPI_SI

126

SPI_CLK

128

FSEL#SPICS#

73 74 89 90 91

CAPS_LED#

92 93 95

SYSON

121 127

R24 10K_0402_5%885N @R24 10K_0402_5%885N@

100 101

EC_LID_OUT#

102 103

H_PROCHOT#_EC

104

MAINPWON_R

105

BKOFF#

106

PBTN_OUT#

107 108

VGA_GATE#

110

ACIN

112

EC_ON

114 115

LID_SW#

116

SUSP# SUSP#

117 118

124

+V18R

1

C436

4.7U_0603_6.3V6K

2

ADP_65 <42>

BEEP# <35> EC_FAN_PWM <33> ACOFF <43>

ADP_I <42,43>

ADP_90 <42>

ADP_135 <42>

4/11 SVT: Del 1V_ALW_EN

EC_MUTE#

EC_MUTE# <35>

TP_CLK <37>

TP_DATA <37>

EC_TS_ON# <39>

4/11 SVT: Del VLDT_EN

NTC_V <42>

APU_IMON <48>

VGATE <48> LAN_PWR_ON# <31> BATT_CHG_LED# <37>

CAPS_LED# <37>

PWR_LED# <37> BATT_LOW_LED# <37>

SYSON <40,45>

VR_ON <48>

1 2

EC_RSMRST# <13>

EC_LID_OUT# <13>

BKOFF# <27> PBTN_OUT# <13>

PXS_PWREN <13,18,45,51,52>

VGA_GATE# <13>

ACIN <17,43> EC_ON <44> ON/OFF <37 > LID_SW# <37>

SUSP# <40,45,47,52>

BATT_TEMP <42>

VGA_IMVP_IMON <50>

ADP_ID <41>

ENBKL <26>

1 2

R308 10K_0402_5%R308 10K_0402_5%

USB_ON# <37,39>

FRD#SPI_SO <12>

FWR#SPI_SI <12>

SPI_CLK <12>

FSEL#SPICS# <12>

R372 0_0402_ 5%885N@R372 0_0402_5%885N @ R381 0_0402_ 5%885N@R381 0_0402_5%885N @

NUVOTON EC need PD in AMD platform, no use.

12

R373

R373 0_0402_5%

0_0402_5%

885N@

100K_0804_8P4R_5%

TL_CLK TL_DATA TP_CLK TP_DATA

CO_LAY NUVOTON EC Share FCH ROM

12 12

RP11

18 27 36 45

+3VALW

TL_CLK <26>

TL_DATA <26>

+5VALW

+3VS +3VALW

+3VS

RP25

18 27 36 45

2.2K_0804_8P4R_5%

Turbo_V <42>

PROCHOT <42> MAINPWON <44>

BATT_TEMP

ACIN

BRDID

ID BRD ID Ra Rb Vab

R10 MP0

R03 PVT

1

R02 DVT

2

3

E

1 2

C432 100P_0402_50V8JC432 100P_0402_50V8J

1 2

C433 100P_0402_50V8JC433 100P_0402_50V8J

@

R321

1

885N@

C435

C435 1000P_0402_50V7K

1000P_0402_50V7K

2

+3VALW

0V

0.25V

0.5V

0.82VR01 EVT

+3VALW

12

Ra

1 2

R310 100K_ 0402_5%

1 2

R311 0_0402_ 5%

SHORT PAD@

R

b

0

x

00K

8.2K

1

100K

18K

100K

33K

2/1 SIV: add PU resistor for LID_SW#

LID_SW#

100K_0402_5%

R330

R329

4.7K_0402_5%

4 4

R330

4.7K_0402_5%

EC_SMB_CK2_SUS EC_SMB_DA2_SUS

A

EC_SMB_DA2_SUS

EC_SMB_CK2_SUS

+3VS

2

6 1

DMN66D0LDW-7 2N_SOT363-6

Q143A

3

DMN66D0LDW-7 2N_SOT363-6

Q143B

5

EC_SMB_DA2

4

EC_SMB_CK2

B

EC_SMB_DA2 < 17,33>

EC_SMB_CK2 < 17,33>

13

D

H_PROCHOT#_EC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2

G

Q142

S

2N7002K_SOT23-3

S

Compal Secret Data

2012/11/13 2013/11/12

Compal Secret Data

H_PROCHOT# <48,7>

Deciphered Date

LAN_WAKE#<31>

Custom

Date: Sheet of

D

Date: Sheet

SHORT PAD@

1 2

0_0402_5%

R324

Title

Size Document Number Rev

0_0402_5%

Compal Electronics, Inc.

BIOS & EC I/O Port

VALGD MB L

EC_PME#

of

36 57Friday, April 12, 2013

E

0.1

For EC Debug PWR Button Key Board Conn.

+3VALW

+3VLP

R701

R701 100K_0402_5%

100K_0402_5%

DEBUG@

1 2

ON/OFF

ON/OFF <36>

JP3

+3VALW EC_TX<30,36> EC_RX<30,36>

1

2

3

4

ACES_85205-0400

ME@

TOP

BOT

J11

1 2

SHORT PADS

J13

1 2

SHORT PADS

NOVO#<36>

NOVO#

ON/OFF

R642

R642 100K_0402_5%

100K_0402_5%

1 2

D26

2

3

DAN202UT106_SC70-3

1

NOVO_BTN#

+3VS

12

R745

R744

300_0402_5%

R744 300_0402_5%

300_0402_5%

CAPS_LED#<36>

NUM_LED#<36>

IO/B Conn.

Ext. USB2.0

+5VALW +USB_VCCB

USB_ON#<36,39> USB_OC1# <13>

U36

1

GND

VOUT

2

VOUT7VIN

VIN3VOUT

4

FLG

EN

G547I2P81U_MSOP8

8

6 5

USB Right side

USB20_N0<13>

USB20_P0<13>

1/21 SIT change PN to SM070001N00 for action plan

L66

USB20_N0

USB20_P0

EMI@

4

1

WCM-2012-900T_4P

SM070001N00

3

2

USB20_N0_R

USB20_P0_R

2

3

D25

1

PJDLC05_SOT23-3

@ESD@D25

@ESD@

ESD

1/29 SIT: Del R806 & Q12 for change audio type from normal close to normal open.

220U_6.3V_M

6.3Φ * 5.9 SF000001500

C714

For 15"

KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6

KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15

KB1

KB2

KB_LED_PWR

KB_LED_PWR_2

+USB_VCCB

W=80mils

+USB_VCCB

1

+

C492

330p_0402_25V

2

SE074331K80

JKB1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

ACES_88514-3001

ME@

SP010011A00

SIV: EMI request

1

EMI@

2

KSO16 KB_LED_PWR KSO17 CAPS_LED#

31

GND

32

GND

Card Reader

USB20_N6<13> USB20_P6<13>

Audio Jack

HPOUT_L<35> HPOUT_R<35>

PLUG_IN<35>

1/29 SIT:change to PLUG_IN

R747

1 2 1 2

R746 0_0402_5%14@R746 0_0402_5%14@

1 2

R748 0_0402_5%15@R748 0_0402_5%15@

1 2

R749 0_0402_5%14@R749 0_0402_5%14@

HGNDA<35> HGNDB<35>

KSI[0..7]

KSO[0..17]

or 14"

F

KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6

KSO3 KSO12 KSO13 KSO14 KSO11

0_0402_5%

USB20_N6 USB20_P6

USB20_N0_R USB20_P0_R

HPOUT_L HPOUT_R HGNDA HGNDB

+3VS

KSO10 KSO15

KB1

KB2

15@

PLUG_IN

JKB2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

GND2 GND1

ACES_88514-02601-071

ME@

JIO1

14

G2

13

G1

12

11

10

9

8

7

6

5

4

3

2

1

ACES_85202-1405N

ME@

KSI[0..7] <36>

KSO[0..17] <36>

27 28

16 15

TP Switch & TP Conn. LED

+5VS

JTP1

8

GND

7

GND

6

TP_CLK<36> TP_DATA<36>

15@

12

R627

R627 0_0402_5%

0_0402_5%

12

R619 0_0402_5%

0_0402_5%

TP_CLK TP_DATA TP_3 TP_2 TP_1

TP_3

TP_1

14@R619

14@

L R

SW4

14@SW4

14@

SMT1-05_4P

5

6

2

4

3

1

SW6

15@SW6

15@

SMT1-05_4P

5

6

2

4

3

1

TP_3 TP_2

TP_2 TP_1

SW5

14@SW5

14@

SMT1-05_4P

5

6

2

4

3

1

SW7

15@SW7

15@

SMT1-05_4P

5

6

2

4

3

1

5

4

3

2

1

ACES_88058-060N

ME@

1

C491

C490

SP010010T00

@

2

0.1U_0402_10V6K

LED/B Conn.

15" 14"

VCC

1

CLK

2

DAT

3

GND

4

L

5

R

6

VCC

21CLK

3

DAT

4

5

GND

6

L

R

For 15"

LED1

21

R623

R623 300_0402_5%

300_0402_5%

14@

R764

R764 470_0402_5%

470_0402_5%

14@

R765

R765 300_0402_5%

300_0402_5%

14@

12

+5VALW

12

+3VALW

12

+5VALW

ESD@

D24

PJSOT24C 3P C/A SOT-23

SIT for ESD Request

2

3

1

SCA00001G00

NOVO_BTN# ON/OFF

PWR_LED#<36>

BATT_LOW_LED#<36>

BATT_CHG_LED#<36>

PWR_LED#

BATT_LOW_LED#

19-217-S2C-FM2P1VY-3T_ORANGE

BATT_CHG_LED#

19-213A-T1D-CP2Q2HY-3T_WHITE

LED2

14@LED2

14@

LED5

14@LED5

14@

19-213A-T1D-CP2Q2HY-3T_WHITE

Lid SW(For 14")

JLED1

+3VALW

LID_SW#

PWR_LED# BATT_LOW_LED# BATT_CHG_LED#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

1

2

3

4

5

6

7

GND

8

GND

ACES_88058-060N

ME@

SP010010T00

Compal Secret Data

2012/11/13 2013/11/12

Compal Secret Data

Deciphered Date

3

LID_SW#<36>

LID_SW#

2

C550

14@

10P_0402_50V8J

1

AH1806-W-7 SC59 3P

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet of

Compal Electronics, Inc.

ROM/KBD/PWR/CR/LED/TP Conn.

VALGD MB L

OUTPUT

2

VDD

GND

1

14@ U40

14@

JPWRB1

1

2

3

4

5

6

7

GND

8

GND

ME@

ACES_88058-060N

SP010010T00

+3VALW

1

14@

C551

0.1U_0402_16V4Z

2

U40

37 57Friday, April 12, 2013

0.1

14@

PWR/B Conn.

14@

LED1

A

B

C

D

E

For UMA

U71

GCLK238@U71

GCLK238@

1 1

2 2

3 3

SLG3NB244VTR_TQFN16_2X3

SIT:Add CG5, CG6 & CG7 for Vender Request

+3VALW

12

RG11

RG11 0_0402_1%

0_0402_1%

SHORT PAD@

1

@CG7

@

CG7

2

0.1U_0402_16V7K

CG8

GCLK@ CG8

GCLK@

15P_0402_50V8J

+3V_LAN +3VALW

1

@CG6

@

CG6

2

0.1U_0402_16V7K

Y8

4

NC

1

OSC

GCLK@

1

2

GCLK@

25MHZ_10PF_7V25000014

+1.8VGS

12

1

GCLK@

2

CG5 0.1U_0402_1 6V7K

RG9 0_0402_1%

3

OSC

2

NC

SHORT PAD@

CG1

0.1U_0402_16V7K

P/N:SA00005DO00

Every power trace need:

=20mils

W

For GreenCLK generate CLK:

+CHGRTC_R

12

+3VLP

RG12

RG12 390_0402_5%

390_0402_5%

GCLK@

1

CG3

GCLK@C G3

GCLK@

+GCLK_VBAT

22U_0805_6.3V6M

1

12

CG2

2

SHORT PAD@

RG8 0_0402_1%

0.1U_0402_16V7K

12

+3VS_GCLK

VGA_GCLK

PCH_GCLK GCLK_PCH_25MHZ

GREENCLK_XTALI GREENCLK_XTALO

1

CG9

CG9 12P_0402_50V8J

12P_0402_50V8J

2

GCLK@

22U_0805_6.3V6M

2

For DIS

U74

10

VBAT

15

+V3.3A

2

VDD

11

VDDIO_27M

8

VDDIO_25M_A

3

VDDIO_25M_B

1

XTAL_IN

16

XTAL_OUT

SLG3NB304VTR_TQFN 16_2X3

GCLK302@

VDD_RTC_OUT

32kHz

27MHz

25MHz_A

25MHz_B

GND1

GND2

GND3

4

7

13

17

14

9

12

6

5

GND4

P/N:SA00006D500

1

CG4

2.2U_0402_6.3V6M

2

GCLK@

GCLK_32K_R

GCLK_27MHZ_R GCLK_27MHZ

GCLK_LAN_25MHZ_R

GCLK_PCH_25MHZ_R

Close to GCLK

Mount: All parts in this page except Swing Level RES (Marked "*") NA: PD108, Y1,R98,C180,C181, Y2,R169,C196,C197, Y6,C968,C969

For EMI

SHORT PAD@

1 2

RG1 0_0402 _1%

1 2

RG2 10 _0402_5%GCLK@RG2 10_0402_5%GCLK@

1 2

RG3 33 _0402_5%GCLK@RG3 33_0402_5%GCLK@

1 2

RG4 33 _0402_5%GCLK@RG4 33_0402_5%GCLK@

SHORT PAD@

GCLK_32K

GCLK_LAN_25MHZ

Typical CLK_32K_FCH trace <= 6" Max. length <= 24"

GCLK_32K <11>

GCLK_27MHZ <18 >

GCLK_LAN_25MHZ <31>

GCLK_PCH_25MHZ <11>

FCH_32.768K dGPU LAN FCH_25M

Typical CLK_25M_FCH trace <= 8" Typical CLK_25M_LAN trace <= 8" Max. length <= 12"

12pF for Vender Request

Reserved for Swing Level adjustment ( Close GCLK side )

GCLK_27MHZ

GCLK_LAN_25MHZ

GCLK_PCH_25MHZ

4 4

Security Classification

2012/11/13 2013/11/12

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/11/13 2013/11/12

C

Compal Secret Data

Deciphered Date

D

1 2

RG5 0_0402_5% NOGCLK@RG5 0_0402_5% NOGCLK@

1 2

RG6 0_0402_5% NOGCLK@RG6 0_0402_5% NOGCLK@

1 2

RG7 0_0402_5% NOGCLK@RG7 0_0402_5% NOGCLK@

Compal Electronics, Inc.

Title

Size Document Num ber Rev

B

Date: Sheet of

Compal Electronics, Inc.

GCLK

VALGD MB L

0.1

38 57Friday, April 12, 2013

E

5

4

3

2

1

Touch Screen

+3VS +3VS_TS

TS@

1 2

R799 0_0402_5%

D

S

D

D D

R798 100K_0402_5%

100K_0402_5%

EC_TS_ON#<36>

1 2

0.1U_0402_16V7K

S

TS@

C669

Q156

2

PMV65XP_SOT23-3

@

1

TS@C669

TS@

2

C668

TS@

1

0.1U_0402_16V7K

13

G

TS@R798

USB20_N4<13>

USB20_P4<13>

+3VS_TS

1 2

R726 0_0402_5%TS@R726 0_0402_5%TS@

TS_RST#EC_TS_ON#

JTS1

1

2

3

4

5

6

7

GND

8

GND

ACES_50208-00601-P01

ME@

USB3.0

@

C704

.1U_0402_16V7K

USB_ON#<36,37> USB_OC0# <13>

C C

F

B B

CH_USB2.0

FCH_USB3.0

A A

Place TX AC coupling Cap (C843~C850). Close to conne

1 2

USB20_N10<13>

USB20_P10<13>

USB3_RX0_N<13>

USB3_RX0_P<13>

C850

C850 .1U_0402_16V7K

.1U_0402_16V7K

USB3_TX0_N<13>

USB3_TX0_P<13>

1 2

C848

C848 .1U_0402_16V7K

.1U_0402_16V7K

U35

1

GND

VOUT

2

VOUT7VIN

VIN3VOUT

4

FLG

EN

G547I2P81U_MSOP8

1/21 SIT change PN to SM070001N00 for action plan

WCM-2012-900T_4P

1

EMI@

443

L51

SM070001N00

WCM-2012-900T_4P

1

EMI@

443

L54

WCM-2012-900T_4P

1

U3TXDN0_L

U3TXDP0_L

1

EMI@

443

L53

1/21 SIT change PN from SM070001S00 to SM070003K00 for action plan

8

6 5

C737

220U_6.3V_M

SF000002Y00

S

M070003K00

SM070003K00

W=80mils

1

C735

@ C735

@

+

2

U2DN10

2

3

U2DP10

2

U3RXDN0

2

3

U3RXDP0

2

U3TXDN0

2

3

U3TXDP0

ctor

470P_0402_50V7K

Left Ext.USB Conn. 1

+USB3_VCCA

W=80mils

JUSB1

9

U3TXDP0

U3TXDN0 U2DP10

U2DN10 U3RXDP0

U3RXDN0

SSTX+

1

VBUS

8

SSTX-

3

D+

7

GND_D

2

D-

6

SSRX+

4

GND

5

SSRX-

OCTEK_USB-09EAAB

ME@

GND1 GND2 GND3 GND4

FCH_USB2.0

FCH_USB3.0

10 11 12 13

2A/Active Low

+5VALW +USB3_VCCA

@

ESD

U3RXDP0 U3RXDP1U3RXDP1U3RXDP0

U3TXDN0

U3TXDP0

USB20_N11<13>

USB20_P11<13>

USB3_RX1_N<13>

USB3_RX1_P<13>

USB3_TX1_N<13>

USB3_TX1_P<13>

D27

@ESD@

9

1

10

1

10

8

2

9

2

9

7

4

7

4

6

6 5

3

8

YSCLAMP0524P_SLP2510P8-10-9

1/21 SIT change PN to SM070001N00 for action plan

EMI@

C849

C849 .1U_0402_16V7K

.1U_0402_16V7K

1 2

U3TXDN1_L U3TXDN1

EMI@

1 2

EMI@

U3TXDP1_L

C847

1/21 SIT change PN from SM070001S00 to SM070003K00 for action plan

.1U_0402_16V7K

1

2

4

U3TXDN0

5

U3TXDP0

3

WCM-2012-900T_4P

1

443

WCM-2012-900T_4P

1

443

L50

WCM-2012-900T_4P

1

443

L49

L55

SM070001N00

S

SM070003K00L49

SM070003K00

U3RXDN1 U3RXDN1U3RXDN0U3RXDN0

U3TXDN1

U3TXDP1

YSCLAMP0524P_SLP2510P8-10-9

2

U2DN11

2

3

U2DP11

2

U3RXDN1

2

3

U3RXDP1

M070003K00

2

3

U3TXDP1

D30

@ESD@

9

10

8

9

7

6

6 5

1

2

4

U3TXDN1

4

5

U3TXDP1

3

8

Left Ext.USB Conn. 2

+USB3_VCCA

W=80mils

U3TXDP1

U3TXDN1 U2DP11

U2DN11 U3RXDP1

U3RXDN1

JUSB2

9

SSTX+

1

VBUS

8

SSTX-

3

D+

7

GND_D

2

D-

GND1

6

SSRX+

GND2

4

GND

GND3

5

SSRX-

GND4

OCTEK_USB-09EAAB

ME@

U2DN10

D22

@ESD@

3

I/O2

2

GND

1

I/O1

AZC099-04S.R7G_SOT23-6

10 11 12 13

D31

6

I/O4

5

+5VALW +5VALW

VDD

4

U2DP10

I/O3

U2DP11

D31

3

2

1

AZC099-04S.R7G_SOT23-6

@ESD@

6

I/O4

I/O2

5

VDD

GND

4

U2DN11

I/O3

I/O1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2012/11/13 2013 /11/12

2

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

USB3.0/Left USB Ports

VALGD MB L

1

39 57Friday, April 12, 2013

0.1

A

+5VALW to +5VS combine with +3VALW to +3VS

+5VALW +5VS

U54

1

1 1

SUSP#

+3VALW

2

3

4

5

6 7

TPS22966DPUR_SON14_2X3

Each 250pF on CAP_MOS1 (2) will make Slew Rate(uS/V) increase of 100uS/V

14

VOUT1

VIN1 VIN1

ON1

VBIAS

ON2

VIN2 VIN2

VOUT1

CT1

GND

CT2

VOUT2 VOUT2

GPAD

13

12

11

10

9 8

15

1 2

C466 100P_0402_50V8JC466 100P_0402_50V8J

1 2

C540 680P_0402_50V7KC540 680P_0402_50V7K

B

1

CC41

+3VS

1

CC39

2

10U_0603_6.3V6M

2

10U_0603_6.3V6M

C

+1.1VALW TO +1.1VS (5.15A)

+1.1VALW TO +1.1VS (5.15A)+1.1VALW TO +1.1VS (5.15A)

+1.1VALW +1.1VS

1

C1448

C1448 10U_0603_6.3V6M

10U_0603_6.3V6M

2

+VSB

12

R1105

R1105 270K_0402_5%

270K_0402_5%

34

Q157B

5

SUSP

DMN66D0LDW-7_SOT363-6

1 2

82K_0402_5%

D

U41

DMN3030LSS-13_SOP8L-8

8 7

5

R1106

U41

4

1.1VS_GATE_R1.1VS_GATE

1

C1034

0.1U_0402_25V6

2

1 2 36

1

C1447

C1447 10U_0603_6.3V6M

10U_0603_6.3V6M

2

@

1

C1449

C1449 1U_0603_10V6K

1U_0603_10V6K

2

1

C1451

0.1U_0603_25V7K

2

E

12

R1101

R1101 470_0603_5%

470_0603_5%

@

61

Q157A

DMN66D0LDW-7_SOT363-6

2

SUSP

+1.5V to +1.5VS

2 2

C440

10U_0603_6.3V6M

+5VALW

12

100K_0402_5%

100K_0402_5% R336

R336

1.5VS_GATE 1.5VS_GATE_R

13

D

2

SUSP#

3 3

4 4

G

SUSP

SUSP#<36,45,47,52>

Q26

Q26 2N7002K_SOT23-3

2N7002K_SOT23-3

S

+1.5V +1.5VS

1

LP2301ALT1G_SOT23-3

2

R339

1 2

22K_0402_5%

SUSP

DTC124EKAT146_SC59-3

Q20

3 1

2

1

C451

0.1U_0402_25V6

2

12

R1108

R1108 100K_0402_5%

100K_0402_5%

Q52

2

IN

+5VALW+RTCBATT

12

1

3

1

@

C441

C441 10U_0603_6.3V6M

10U_0603_6.3V6M

2

@

R1452

R1452 100K_0402_5%

100K_0402_5%

OUT

GND

1

2

1

C452

0.1U_0603_25V7K

2

C442

C442 1U_0603_10V6K

1U_0603_10V6K

12

13

D

S

SYSON<36,45>

R1454

R1454 470_0603_5%

470_0603_5%

@

2

SUSP

G

Q23

Q23 2N7002K_SOT23-3

2N7002K_SOT23-3

@

SYSON#

SYSON

R1453

100K_0402_5%

2

IN

+5VALW

12

@

1

3

OUT

Q29

Q29 DTC124EKAT146_SC59-3

DTC124EKAT146_SC59-3

@

GND

+0.75VS

R1137

R1137 470_0603_5%@

470_0603_5%@

1 2

34

5

@

Q159B

Q159B DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

+1.5V

R1139

R1139 470_0603_5%@

470_0603_5%@

1 2 61

@

SUSP SYSON#

2

Q159A

Q159A DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

Security Classification

2012/11/13 2013/11/12

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/11/13 2013/11/12

Compal Secret Data

C

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet

Compal Electronics, Inc.

DC Interface

VALGD MB L

0.1

of

40 57Friday, April 12, 2013

E

5

4

3

2

1

ADP_ID

AC Adapter 90W 65W

R(K ohm) open 10 ADP_ID(V) 3.3 1.65

Detection voltage >2.64 1.32~1.98

D D

PL101

PF101

7A_24VDC_429007.WRML

PR112

PR112 0_0402_5%

0_0402_5%

PC109

680P_0603_50V7K

7A_24VDC_429007.WRML

12

21

APDIN1APDIN

12

PC101

1000P_0402_50V7K

ADP_ID <36>

JDCIN1

1

2

3

4

5

ACES_50299-00501-003

C C

VIN

CONN@

+3VALW

PR110

1 2

100K_0402_1%

5

100K_0402_1%

PR102

1 2

750_0402_1%

PR111

12

PQ102A

PQ102A 2N7002KDW-2N_SOT363-6

2N7002KDW-2N_SOT363-6

6 1

2

34

PQ102B

1 2

5

2N7002KDW-2N_SOT363-6

12

PC108

0.1U_0402_16V7K

ADP_ID_CLOSE <36>

HCB2012KF-121T50 0805

12

PC102

@100P_0402_50V8J

1 2

PL102

1 2

VIN

12

PC104

PC103

100P_0402_50V8J

@1000P_0402_50V7K

+CHGRTC

B B

PD101

S SCH DIO BAS40CW SOT-323

+RTCBATT

2

1

3

PR101

1K_0603_5%

1 2

PR103

1K_0603_5%

1 2

+CHGRTC_R

RTC Battery

+3VLP

JRTC1

@JRTC1

@

1

2

3

GND

4

GND

ACES_50271-0020N-001

JRTC2

@JRTC2

@

1

2

3

GND

4

GND

ACES_50271-0020N-001

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PWR DCIN / RTC Battery

Size Document Number Rev

Custom

VALGD MB L

Date: Sheet of

2

Date: Sheet of

1

41 62Friday, April 12, 2013

0.1

5

1 2 3 4 5 6 7

1 2 3 4 5 6 7 8 9

1 2

VMB2

PC202

0.01U_0402_25V7K

BATT_TEMP<36,42>

12

PC207

PC207 100P_0402_50V8J

100P_0402_50V8J

PR208

@ PR208

@

@75K_0402_1%

PR217

@ PR217

@

@100K_0402_1%

PC213

@ PC213

@

12

@100P_0402_50V8J

EC_SMDA

EC_SMCA

12

PR204

100_0402_1%

PR204

100_0402_1%

PR201

100_0402_1%

PR201

100_0402_1%

1 2

PR206

6.49K_0402_1%

1 2

PR207

PR207 10K_0402_5%

10K_0402_5%

VL

8

3

P

+

1

O

2

-

G

PU201A

AS393MTR-E1 SO 8P OP

4

VLVMB +3V_LDO

8

5

P

+

6

-

G

4

PU201B

AS393MTR-E1 SO 8P OP

PF201

PF201 12A_65V_451012MRL

12A_65V_451012MRL

21

12

PR210

47K_0402_1%

PC208

0.068U_0402_16V7K~N

1 2

PR205

1.5M_0402_5%

12

7

O

@0.068U_0402_16V7K~N

1 2

PR218

@PR218

@

@47K_0402_1%

1 2

PC210

@PC210

@

@1.5M_0402_5%

PD201

PR223

@PR223

@

CONN@

JBAT1

D D

GND GND

SUYIN_200082GR007M229ZR

CONN@

JBAT2

GND GND

SUYIN_200082GR007M229ZR

C C

VL

PR202

PR202 75K_0402_1%

75K_0402_1%

1 2

PR213

PR213 100K_0402_1%

100K_0402_1%

1 2

B B

4

VMB

1 2

HCB2012KF-121T50 0805

1 2

HCB2012KF-121T50 0805

12

PC201

PC201 1000P_0402_50V7K

1000P_0402_50V7K

EC_SMB_CK1 < 36,43>

EC_SMB_DA1 < 36,43>

+3VLP

BATT_TEMP <36,42>

12

1N4148WS-7-F_SOD323-2

12

1 2

PL201

PL202

BATT+

12

PC203

PC203 @0.01U_0402_25V7K

@0.01U_0402_25V7K

3

PH201 under CPU botten side : CPU thermal protection at 93 +-3 degree C

90W(DIS) : 6.65K 100W active 90W recovery 65W(UMA): 1.65K 70W active 65W recovery

2

1

Recovery at 56 +-3 degree C

A/D

@100K_0402_1%

5

PQ206A

2N7002KDW-2N_SOT363-6

ADP_90<36>

ADP_I<36,43>

PR221

1 2

8.45K_0402_1%

NTC_V<36>

PR227

1 2

34

PJ202

PJ202 JUMP_43X39@

JUMP_43X39@

112

PR227

9.31K_0402_1%

PQ206B

2N7002KDW-2N_SOT363-6

ADP_135<36>

PR228

1 2

5.9K_0402_1%

PR222

PR222 100K_0402_1%

100K_0402_1%

13

2

G

ECAGND

2

1 2

D

PQ207

S

2N7002KW_SOT323-3

ECAGND

+VSB

+3VLP

12

PR226

12.7K_0402_1%

12

PH201

PH201 100K_0402_1%_TSM0B104F4251RZ

100K_0402_1%_TSM0B104F4251RZ

+3VALW

PR214

100K_0402_1%

PR211

100K_0402_1%

1 2

OR

34

PQ202B

5

2N7002KDW-2N_SOT363-6

OR

13

D

2

PQ208

G

@2N7002KW_SOT323-3

G

@2N7002KW_SOT323-3

S

BATT_LEN#<36>

+5VALW

12

PC212

@ PC212

PD203

@

@1N4148WS-7-F_SOD323-2

@

@22U_0603_6.3V6M

100K_0402_1%

1 2 61

PQ202A

2

2N7002KDW-2N_SOT363-6

+3VLP

PR220

100K_0402_1%

1 2

PU202

@PU202

@

1

IN

OUT

2

GND

SHDN#3BYP

@G9191-330T1U_SOT23-5

2

G

5

4

13

D

PQ205

2N7002KW_SOT323-3

S

12

PC211

@PC211

@

@1U_0402_16V6K

PROCHOT<3 6>

BATT_OUT <43>

ADP_65<36>

@

PC209

PC209 @4.7U_0402_6.3V6M

@4.7U_0402_6.3V6M

1 2

Turbo_V<36>

+3V_LDO

12

PR229

PR225

1 2

25.5K_0402_1%

61

2

ECAGND ECAGND

B+

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PWR-BATTERY CONN/OTP

Size Document Number Rev

Custom

VALGD MB L

Date: Sheet of

2

Date: Sheet of

1

42 62Friday, April 12, 2013

0.1

5

PQ301

PQ301 AO4407AL_SO8

AO4407AL_SO8

DTA144EUA_SC70-3

47K_0402_5%

13

2

PQ307A

PACIN

PR311

10K_0402_1%

1 2

2

G

8 7

5

PQ304

2

1 3

PQ303

DTC115EUA_SC70-3

PR303

47K_0402_1%

1 2

ACOFF-1

2

13

D

PQ314

S

2N7002KW_S OT323-3

4

VIN

D D

C C

B B

2

ACOFF<36>

BATT_OUT<42,43>

12

PR302

61

2N7002KDW -2N_SOT363-6

P2

1 2 36

12

PC302

0.1U_0603_25V7K

PQ307B

5

13

PQ305

DTC115EUA_SC70-3

PQ302

SI4483ADY

1 2 3 6

12

PR304

200K_0402_1%

P2-1

12

PR306

PR306 20K_0402_1%

20K_0402_1%

PQ306

D

PR305

S

150K_0402_1%

2N7002KDW-2N_SOT363-6

PQ306

13

2N7002KW_S OT323-3

2

G

PR308

64.9K_0402_1%

1 2

PC303

1 2

0.1U_0402_25V6

EC_SMB_DA1<36,42>

EC_SMB_CK1<36,42>

12

P2-2

34

4

5600P_0402_25V7K

BATT_OUT <42,43>

VIN

12

PR309

392K_0402_1%

4

8 7

5

1 2

PC301

ADP_I<36,42>

PC304 100P_0402_50V 8JP C304 100P_0402_50V8J

316K_0402_1%

+3VALW

PR315

1 2

100K_0402_1%

P3

1 2

PR316

PR301

0.01_1206_1%

1

2

ACPRN

6

ACDET

7

IOUT

8

SDA

BQ24727RGRR_VQFN20_ 3P5X3P5

9

SCL

10

12

ILIM

B+

4

3

ACP

4

5

ACOK

CMPIN

PU301

SRN12BM

11

12

PR317

6.8_0402_5%

PC306

0.1U_0402_25V6

1 2

PC307

1 2

3

13

CMPOUT

SRP

12

ACN

0.1U_0402_25V6

PC308

0.1U_0402_25V6

1 2

1

2

ACP

GND

15

14

PR318

10_0402_5%

3

1 2

PL301

1UH_PCMB042T-1R0M S_4.5A_20%

PC311

1 2

0.1U_0402_25V6

ACN

21

TP

20

19

18

17

16

BQ24737VCC

BST_CHG

PD301

RB751V-40_SOD323-2

12

PC312

PC312 1U_0603_25V6K

1U_0603_25V6K

VCC

PHASE

HIDRV

BTST

REGN

LODRV

P2

PR319

10_1206_5%

DH_CHG

12

DL_CHG

12

PC314

1 2

1U_0603_25V6K

2.2_0603_5%

1 2

PR320

BQ24737VDD

LX_CHG

12

PC315

10U_0805_25V6K

1 2

PR326

0_0402_5%

PC317

0.047U_0603_16V7K

1 2

PC316

10U_0805_25V6K

DH_CHG_1

2

CHG_B+

PQ312

AO4407AL_SO8

1 2 3 6

12

4

PC319

@2200P_0402_50V7K

5

DISCHG_G

PR322

200K_0402_1%

1 2

PR321

PR321 47K_0402_1%

47K_0402_1%

1 2

DISCHG_G-1

PQ311

13

DTC115EUA_SC70-3

2

PQ309

AON7408L_DFN8-5

123

4.7U 20% VMPI0703AR-4R7M-Z01 5.5A

1 2

12

PR323

@

MDV1527URH

PQ310

123

@4.7_1206_5%

24737_SN

12

PC320

@

@680P_0603_50V7K

PL302

4

ACOFF-1

PD302

1SS355_SOD323-2

1 2

PD303

1SS355_SOD323-2

CHG

SRP

12

PC324

0.1U_0402_25V6

PR324

0.01_1206_1%

1

2

1

8 7

5

200K_0402_1%

200K_0402_1% PR325

PR325

PACIN_1

PQ313

2N7002KW_S OT323-3

13

D

2

G

S

4

3

SRN

VIN

PACIN

PC322

BATT+

12

PC323

10U_0805_25V6K

12

PC305

0.1U_0402_25V6

BQ24737VDD

PR314

10K_0402_1%

4

10K_0402_1%

1 2

PACIN

12

PR312

12K_0402_1%

ACIN <17,36>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

12

PR307

47K_0402_1%

ACPRN

PQ308

DTC115EUA_SC70-3

A A

5

DTC115EUA_SC70-3

12

PR310

PR310 10K_0402_1%

10K_0402_1%

13

2

12

3

PC309

0.1U_0402_25V6

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

2012/07/112011/06/15

2

Title

Size D ocument Number Rev

Date: Sheet of

Compal Electronics, Inc.

CHARGER

VALGD MB L

1

0.1

43 62Friday, April 12, 2013

0.1

A

PC432

0.047U_0402_25V7K

1 1

B+

PL401

HCB1608KF-121T30_0603

1 2

PC403

@

@0.1U_0402_25V6

2 2

B+

PL403

HCB2012KF-121T50_0805

1 2

3 3

+3VLP

12

PC420

PC427

10U_0805_25V6K

3V_VIN

12

PC406

PC404

5V_VIN

12

PC417

2200P_0402_50V7K

PR409

1 2

100K_0402_1%

12

PC418

@

@0.1U_0402_25V6

10U_0805_25V6K

12

5V_VCC

PC422

8

9

5

2

4.7U_0603_6.3V6M

PU401

7

IN

8

9

EN1

IN

EN2

BS

LX

OUT

GND

PG2LDO

SY8208BQNC_QFN10_3X3

SPOK <46>

PU403

IN

EN1

EN2

BS

LX

GND

OUT

VCC

LDO

PG

SY8208CQNC_QFN10_3X3

1 2

1

3

6

10

4

7

1

3

6

BST_3V

10

4

5

B

PR412

1 2

10K_0402_5%

ENLDO_3V5V

PR401

1 2

1_0603_5%

3V5V_EN

1 2

BST_5V

1_0603_5%

12

03/06

3V5V_EN3V5V_EN_R

3V5V_EN_R

BST_3V_1

+3VLP

12

PC414

4.7U_0603_6.3V6M

PR405

VL

PC430

4.7U_0603_6.3V6M

FB_3V

PC402

1 2

0.1U_0603_25V7K

FB_5V

PC421

0.1U_0603_25V7K

1 2

BST_5V_1

LX_5V

12

PR403

PC407

150K_0402_1%

@1U_0603_25V6K

PC439

1 2

0.1U_0402_25V6K

LX_3V

1.5UH_PCMC063T-1R5MN_9A_20%

12

PR404

3V_SN

12

PC415

PC436

1 2

6800P_0402_25V7K

1.5UH_PCMC063T-1R5MN_9A_20%

12

PR406

5V_SN

12

PC429

499K_0402_1%

12

1 2

4.7_1206_5%

680P_0603_50V7K

03/06

1 2

4.7_1206_5%

680P_0603_50V7K

PR402

12

03/06

PR416

1K_0402_5%

PL402

PR413

1K_0402_5%

PL404

GLZ5.1B_LL34

12

C

PD401

D

12

B+

E

+3VALWP

12

PC409

PC408

22U_0805_6.3V6M

12

PC423

PC424

22U_0805_6.3V6M

12

PC412

PC410

22U_0805_6.3V6M

PC425

22U_0805_6.3V6M

PC412

PC411

22U_0805_6.3V6M

12

PC416

PC426

22U_0805_6.3V6M

12

PC434

PC435

470P_0402_50V8J

@470P_0402_50V8J

@22U_0805_6.3V6M

@470P_0402_50V8J

+5VALWP

+3VALWP +3VALW

12

PC437

PC438

@470P_0402_50V8J

+5VALWP

470P_0402_50V8J

PJ401

@PJ401

@

112

JUMP_43X118

PJ402

@PJ402

@

112

JUMP_43X118

2

+5VALW

PR407

2.2K_0402_5%

EC_ON<36>

MAINPWON<36>

4 4

A

1 2

PR408

1 2

@0_0402_5%

3V5V_EN

12

PC431

PR410

PC431

1M_0402_1%

4.7U_0402_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

3VALWP/5VALWP

Size Document Number Rev

Custom

VALGD MB L

Date: Sheet of

D

Date: Sheet of

44 62Friday, April 12, 2013

E

0.1

A

STATE S3 S5 1.5VP VTT_REFP 0.75VSP

S0

Hi Hi

S3

S4/S5

1 1

HiLo

Lo Lo

Note: S3 - sleep ; S5 - power off

On

Off

On

Off (Hi-Z)

Off Off

+0.75VSP

12

PC504

PC505

10U_0805_25V6K

12

PC506

0.033U_0402_16V7K

PR502

2 2

SUSP#

SYSON<36,40>

PR502

0_0402_5%

1 2

PC503

0.1U_0402_16V6K

12

PR505

0_0402_5%

1 2

PC508

@PC508

@

@0.1U_0402_16V7K

12

PU501

21

1

2

3

4

5

10K_0402_1%

PAD

VTTGND

VTTSNS

GND

VTTREF

VDDQ

B

+1.5VP

BST_1.5V BST_1.5V-1

19

20

18

VTT

BOOT

VLDOIN

RT8207MZQW_WQFN20_3X3

FB

S5

S3

6

8

7

FB_1.5V

S3_1.5V

S5_1.5V

PR507

10.2K_0402_1%

1 2

FB=Vref=0.75V

12

PR506

16

17

UGATE

TON

9

10

PR509

887K_0402_1%

1 2

UG_1.5V

PHASE LGATE

PGND

VDDP

PGOOD

CS

VDD

LX_1.5V

PR501

2.2_0603_5%

1 2

15

14

13

12

11

1.5V_B+

PR511

5.62K_0402_1%

1 2

PC510

remote_1.5V

PC512

0.1U_0603_25V7K

1 2

LG_1.5V

12

1U_0603_10V6K

100_0402_1%

1 2

PR514

5.1_0603_5%

PC511

1U_0603_10V6K

PC507

1 2

0.1U_0402_16V6K

PR508

1 2

4

C

5

PQ501

MDV1525URH_PDFN33-8-5

123

5

123

Rds(on)=2.7m-3.3m ohm

Rds(on)=2.7m-3.3m ohm Rds(on)=2.7m-3.3m ohm

12

AON6554

PQ502

12

+5VALW+1.5VP

12

1UH_PCMB104T-1R0MH_18A_20%

@

PR515

PR515 @4.7_1206_5%

@4.7_1206_5%

SUB_+1.5VP

@

PC517

PC517 @680P_0603_50V7K

@680P_0603_50V7K

+1.5V

UV4的1.5V

1.5V_B+

PC501

10U_0805_25V6K

1 2

12

PL501

D

PL502

1 2

HCB2012KF-121T50_0805

12

PC509

PC520

10U_0805_25V6K

PC513

@

@0.1U_0402_25V6

2200P_0402_50V7K

B+

Vo=1.518V

+1.5VP

1

+

PC521

2

220U 2V Y D2 ESR15M

+1.5VP OCP min 20A OVP min 1.65V

@

PJ504

2

112

JUMP_43X118

@

PJ505

+1.5VP +1.5V

112

JUMP_43X118

@

PJ506

112

JUMP_43X39

2

+0.75VS+0.75VSP

@680P_0402_50V7K

PU502

PU502 SY8032ABC_SOT23-6

SY8032ABC_SOT23-6

4

IN

5

PG

GND

FB6EN

@680P_0402_50V7K

LX

3 3

PJ508

+3VALW

4 4

A

112

JUMP_43X118 @

2

IN_1.8V LX_1.8V

12

PC532

22U_0805_6.3V6M

12

PC528

SNUB_1.8V

12

PR529

@4.7_0402_1%

3

2

1

EN_1.8V

12

PC531

PR525

PR525 100K_0402_1%

100K_0402_1%

1 2

12

PR530

1M_0402_5%

0.22U_0402_10V6K

B

PL505

1UH_PCMB042T-1R0MS_4.5A_20%

1 2

PXS_PWREN <13,18,36,51,52>

FB_1.8V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

PR527

12

PR526

PR526 100K_0402_1%

100K_0402_1%

12

PC530

200K_0402_1%

22P_0402_50V8J

2011/06/15 2012/07/11

+1.8VSP

12

PC529

PC527

22U_0805_6.3V6M

Compal Secret Data

Deciphered Date

C

1.8VSP max curre nt=1.94A

PJ507

112

JUMP_43X118 @

2

Title

Size Document Number Rev

Custom

Date: Sheet of

+1.8VGS+1.8VSP

+1.5VP/+1.8VSP

VALGD MB L

D

45 62Friday, April 12, 2013

0.1

5

D D

PR601

1 2

38.3K_0402_1%

PR603

0_0402_5%

SPOK<44>

C C

B B

1 2

38.3K_0402_1%

PC601

TRIP_+1.1VALWP

EN_+1.1VALWP

FB_+1.1VALWP

0.1U_0402_16V7K

12

RF_+1.1VALWP

12

470K_0402_1%

10K_0402_1%

10K_0402_1% PR608

PR608

PR606

5.76K_0402_1%

1 2

12

4

PU601

1

PGOOD

2

TRIP

3

EN

4

VFB

5

RF

TPS51212DSCR_SON10_3X3

PR607

VBST

DRVH

V5IN

DRVL

3

+1.1VALWP_B+

678

PQ601

PQ601 TPC8065-H_SO8

PC606

0.1U_0603_25V7K

PR602

1 2

2.2_0603_5%

10

BST_+1.1VALWP

9

UG_+1.1VALWP

8

7

6

11

SW_+1.1VALWP

LG_+1.1VALWP

SW

TP

2.2_0603_5%

0.1U_0603_25V7K

BST_+1.1VALWP_1

+5VALW

12

PC607

PC607 1U_0603_6.3V6M

1U_0603_6.3V6M

1 2

PQ602

4

TPC8065-H_SO8

35241

786

5

123

12

PR605

SUB_+1.1VALWP

MDS1521URH

12

PC610

12

PC603

PC602

@0.1U_0402_25V6

PL601

1UH_PCMC063T-1R0MN_11A _20%

1 2

@4.7_1206_5%

@680P_0603_50V7K

2

PL602

HCB2012KF-121T50_0805

1 2

12

2200P_0402_50V7K

12

PC604

PC605

10U_0805_25V6K

B+

1

+1.1VALWP

1

+

PC608

2

220U 6.3V M F62 LESR15M

PJP601

112

JUMP_43X118

+1.1VALW+1.1VALWP

@PJP601

@

2

A A

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/10/12 2013/10/12

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

PWR +1.1VALWP

VALGD MB L

1

46 51Friday, April 12, 2013

0.4

5

D D

PR610

1 2

124K_0402_ 1%

PR611

300K_0402_ 1%

SUSP#<36,40,45,52>

C C

1 2

@47K_0402_ 1%

PR612

124K_0402_ 1%

12

PC616

0.1U_0402_16V7K

TRIP_+1.2VSP

EN_+1.2VSP

FB_+1.2VSP

RF_+1.2VSP

12

PR613

470K_0402_ 1%

4

PU602

1

PGOOD

2

TRIP

3

EN

4

VFB

5

RF

TPS51212DSCR_SON1 0_3X3

PR615

7.15K_0402_ 1%

1 2

VBST

DRVH

V5IN

DRVL

3

5

PQ603

PC615

0.1U_0603_2 5V7K

PR609

1 2

2.2_0603_5 %

10

BST_+1.2VSP

9

UG_+1.2VSP

8

SW

TP

SW_+1.2VSP

7

6

LG_+1.2VSP

11

2.2_0603_5 %

0.1U_0603_2 5V7K

BST_+1.2VSP_1

12

PC617

PC617 1U_0603_6.3 V6M

1U_0603_6.3 V6M

1 2

+5VALW

4

AON7408L

123

5

PQ604

4

AON7506

123

2

+1.2VSP_B+

12

PC611

@0.1U_0402_25V6

PL605

@4.7_1206_5%

@680P_0603_50V7K

PL605

1 2

1.5UH +-20% PC MC063T-1R5MN

12

PR614

SUB_+1.2VSP

12

PC620

1

PL604

HCB2012KF-121 T50_0805

1 2

12

PC612

2200P_0402_50V7K

12

PC614

PC613

10U_0805_25V6K

B+

+1.2VSP

1

+

PC618

2

220U 2V Y D2 ESR15M

12

10K_0402_1 %

10K_0402_1 % PR616

PR616

B B

PU702

APL5508-25DC-TRL _SOT89-3

PJ703

+3VS

A A

5

4

112

JUMP_43X39@

2

IN_+2.5VSP

PC707

1U_0603_10V 6K

Security Classification

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

APL5508-25DC-TRL _SOT89-3

2

12

IN

3

OUT

GND

1

2011/10/12 2013/10/12

3

12

PC708

4.7U_0805_6.3V6K

Compal Secret Data

Deciphered Date

+2.5VSP

(0.38A,20mils ,Via NO.=1)

JUMP_43X39 @

PJ704

112

2

PJP602

112

JUMP_43X118

2

@PJP602

@

+1.2VS+1.2VSP

2

+2.5VS+2.5V SP

Title

Size Document Num ber Rev

Custom

Date: Sheet of

PWR +1.2VSP/2.5VSP

VALGD MB L

1

47 51Friday, April 12, 20 13

0.4

Compal Electronics, Inc.

5

PRZ1

PCZ1

2K_0402 _1%

330P_04 02_50V7K

1 2

PRZ2

2.94K_0 402_1%

PCZ6

@PC Z6

@

12

@PRZ8

@

@220P_0 402_50V7K

PRZ9

1 2

VSUM-

VSUM+

PRZ35

2.61K_0 402_1%

PHZ4

VSUM-

PCZ31

2.94K_0 402_1%

1 2

PCZ3

1000P_0 402_50V7 K

1 2

301_040 2_1%

1 2

PCZ7

@PCZ7

@

NTC_NB

IMON_NB

ENABLE

PRZ220_04 02_5% PRZ 220 _0402_5%

12

PRZ7

1 2

0.22U_04 02_10V6K

PRZ38

11K_0402_1%

APU_VDDNB _SEN_H<7>

PRZ5

D D

10K_040 2_5%_ERTJ0E R103J

C C

B B

A A

VSUMN_NB

PHZ1

2.61K_0 402_1%

2.61K_0 402_1% PRZ11

PRZ11

VSUMP_NB

18.2K_0 402_1%

127K_04 02_1%

1 2

1000P_0 402_25V6 K

+1.5VS

APU_IMON <36>

+APU_CORE_NB

12

0.1U_060 3_50V7K

0.1U_060 3_50V7K PCZ5

PCZ5

12

PRZ12

@27.4K_0 402_1%

PRZ13

1 2

PCZ10

1 2

PCZ13

1U_0603 _16V6K

1 2

PRZ25

133K_04 02_1%

1 2

PCZ18

1000P_0 402_25V6 K

PRZ10

11K_0402_1%

PHZ2

470K_04 02_5%_TSM0 B474J4702 RE

1 2

PRZ14

1 2

PRZ5

10_0402 _5%

1 2

@100_04 02_1%

12

PCZ8

PCZ9

0.1U_0402_25V6

0.047U_0402_16V7-K

APU_SVC<7>

H_PROCHOT#<36,7>

APU_SVD<7>

APU_SVT<7>

VR_ON<36>

APU_PW RGD<11, 7>

FCH_PWR GD<13,36>

PRZ32

@27.4K_0 402_1%

1 2

PHZ3

12

470K_04 02_5%_TSM0 B474J4702 RE

PRZ34

18.2K_0 402_1%

10K_040 2_5%_ERTJ0E R103J

@1000P_ 0402_50V7 K

PRZ8

1 2

464 +-1% 0 402

PRZ55 @0_0 402_5%PRZ55 @0_0402 _5%

0.1U_060 3_50V7K

PUZ1

1

NTC_NB

2

IMON_NB

3

SVC

4

VR_HOT_L

5

SVD

6

VDDIO

7

SVT

8

ENABLE

9

PWROK

10

IMON

PCZ20

1 2

PCZ21

1 2

12

PCZ24

0.01U_0402_16V7K

1 2

PRZ44

@100_04 02_1%

4

PRZ3

137K_04 02_1%

1 2

PCZ4

100P_04 02_50V8J

1 2

GND

41

40

TP

ISUMP_NB

11

NTC

12

0.22U_04 02_10V6K

0.22U_04 02_10V6K PCZ25

PCZ25

PRZ43

430_040 2_1%

1 2

@PRZ44

@

PCZ2

390P_04 02_50V7K

1 2

ISUMN_NB

FB_NB

COMP_NB

37

38

36

39

FB_NB

VSEN_NB

COMP_NB

ISUMN_NB

ISL6277 1HRTZ-T_TQFN40_5X5

ISUMP14ISEN212NTC

13

ISUMN

ISEN2

ISEN1

1 2

PCZ32

@PCZ32

@

@820P_0 402_50V7K

0.01U_04 02_25V7K

0.01U_04 02_25V7K PCZ35

PCZ35

1 2

PRZ4

41.2K_0 402_1%

LGATE_NB

PHASE_NB

34

35

33

LGATE_NB

PGOOD_NB

RTN17ISUMN15ISEN1

VSEN

16

FB

1000P_0 402_50V7 K

12

PCZ26330P_0402_50V7K PCZ26330P_0402_50V7K

12

UGATE_NB

32

PHASE_NB

UGATE_NB

COMP

FB18PGOOD

19

COMP

PCZ22

1 2

BOOT_NB

31

BOOT_NB

BOOT2

UGATE2

PHASE2

LGATE2

VDDP

VDD

LGATE1

PHASE1

UGATE1

BOOT1

20

PRZ36

301_040 2_1%

1 2

PRZ39

2.32K +-1 % 0402

1 2

30

29

28

27

26

25

24

23

22

21

10_0402 _5%

1 2

10_0402 _5%

BOOT2

UGATE2

PHASE2

LGATE2

VDDP

APU_VDD

LGATE1

PHASE1

UGATE1

BOOT1

+3VS

137K_04 02_1%

1 2

2K_0402 _1%

PRZ46

PRZ54

12

PRZ30

100K_04 02_5%

100P_04 02_50V8J

PRZ40

PRZ41

PRZ18

0_0402_ 5%

1 2

PRZ20

1_0603_ 5%

12

PCZ15

1U_0603_16V6K

VGATE <36>

PCZ23

1 2

PCZ29

390P_04 02_50V7K

1 2

PCZ30

680P_04 02_50V7K

+APU_CORE

APU_VDD_ SEN_H <7>

APU_VDD_ SEN_L <7>

3

+5VS

12

PRZ37

PRZ37 @32.4K_0 402_1%

@32.4K_0 402_1%

1 2

2

CPU_B+

12

PRG4

3.65K_0 402_1%

1 2

VSUMN_NB

12

PCZ14

2200P_0402_50V7K

680P_0402_50V7K

0.22UH +-20 % PCMB104T-R2 2MS 35A

PRZ27

10K_040 2_1%

1 2

PRZ31

3.65K_0 402_1%

1 2

PRZ33

1_0402_ 1%

1 2

12

PCZ47

2200P_0402_50V7K

680P_0402_50V7K

0.22UH +-20 % PCMB104T-R2 2MS 35A

PRZ45

10K_040 2_1%

1 2

PRZ51

3.65K_0 402_1%

1 2

PRZ53

1_0402_ 1%

1 2

12

PCG1

10U_0805_25V6K

PQG1

S TR MDU1516 URH 1N

5

BOOT_NB

UGATE_NB

PHASE_NB

1 2

2.2_060 3_5%

LGATE_NB

PRG2

1 2

PRG1

0_0603_ 5%

BOOT_NB_1

0.22U_06 03_25V7K

UGATE_NB1 -1

1 2

PCG3

AON6554

PQG2

4

UGATE_NB1 -1

123

5

4

LGATE_NB

PQG4

213

AON6554

5

PQZ1

S TR MDU1516 URH 1N POW ERDFN56-8

123

5

213

1 2

PCZ17

0.22U_06 03_25V7K

AON6554

PQZ2

4

PCZ16

1U_0603_16V6K

@

PHASE1

1 2

BOOT1

PRZ26

2.2_060 3_5%

LGATE1

PRZ23

2.2_060 3_5%

BOOT1_1

1 2

UGATE1 UGATE1-1

PCZ16

5

UGATE2

PHASE2

BOOT2

2.2_060 3_5%

LGATE2

1 2

PRZ47

1 2

PRZ42

2.2_060 3_5%

BOOT2_1

UGATE2-1

1 2

PCZ33

0.22U_06 03_25V7K

PQZ4

AON6554

4

PQZ3

MDU1516URH

123

5

4

213

4

5

4

213

12

PRZ29

@PR Z29

@

@4.7_120 6_5%

12

PCZ19

@PC Z19

@

@680P_0 603_50V7K

12

PCZ27

10U_0805_25V6K

12

PRZ49

@PR Z49

@

@4.7_120 6_5%

12

PCZ34

@PC Z34

@

@680P_0 603_50V7K

PQG3

S TR MDU1516 URH 1N

5

123

12

CPU_B+

12

PCZ28

10U_0805_25V6K

PRG3

4.7_120 6_5%

PCG4

680P_06 03_50V7K

VSUMP_NB

12

PCG7

ISEN1

VSUM+

VSUM-

12

PCG13

ISEN2

VSUM-

12

PCZ11

PCZ12

PCG12

2200P_0402_50V7K

0.22UH +-20 % PCMB104T-R2 2MS 35A

12

1

2

PLZ2_2

1

2

PLZ3_2VSUM+

PCZ12

10U_0805_25V6K

PLG1

1

4

3

2

VSUMP_NB 1

PRG5

1_0402_ 1%

1 2

PLZ1

HCB2012K F-121T50_08 05

1 2

PLZ4

HCB2012K F-121T50_08 05

1 2

PCG5

PCG2

68U 25V M 6.3X5.7

10U_0805_25V6K

PLZ2

4

3

PLZ3

4

3

10U_0805_25V6K

PLZ2_1

PLZ3_1

VSUMN_NB1

1 2

1

+

2

PRZ28

PRZ28 10K_040 2_1%

10K_040 2_1%

PRZ48

PRZ48 10K_040 2_1%

10K_040 2_1%

1

+

2

PCG6

PCG6 68U 25V M 6.3X5.7

68U 25V M 6.3X5.7

+APU_CORE

ISEN2

+APU_CORE

ISEN1

1

+APU_CORE_NB

B+

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

2011/04/18 2015/07/08

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU_CORE/CPU_CORE_NB

Size Docu ment Number Rev

Custom

Date: Sheet of

VALGD MB L

1

48 2Friday, April 12, 2 013

0.3

5

D D

+APU_CORE

4

APU_CORE_NB

+

+APU_CORE_NB

3

2

22uF/0805330uF/9m

10uF/0603

0.01uF/0402 180pF/04020.22uF/0402

1

12

PCZ36

PCZ37

22U_0805_6.3V6M

12

PCZ42

PCZ43

22U_0805_6.3V6M

C C

12

PCZ48

22U_0805_6.3V6M

12

PCZ49

0.22U_0402_16V7K

12

PCZ39

PCZ38

22U_0805_6.3V6M

12

PCZ44

PCZ45

22U_0805_6.3V6M

12

PCZ50

PCZ51

22U_0805_6.3V6M

12

PCZ40

PCZ41

22U_0805_6.3V6M

12

PCZ46

22U_0805_6.3V6M

12

PCG8

22U_0805_6.3V6M

12

PCG14

10U_0603_6.3V6M

12

PCG16

0.22U_0402_16V7K

+APU_CORE_NB

12

PCZ54

PCZ53

0.01U_0402_50V7K

B B

0.01U_0402_50V7K

+APU_CORE

12

PCZ55

0.01U_0402_50V7K

Local

12

PCZ56

PCZ57

PCZ58

@

180P_0402_50V8J

@

180P_0402_50V8J

@180P_0402_50V8J

12

PCG9

22U_0805_6.3V6M

12

PCG17

0.22U_0402_16V7K

12

PCG10

PCG11

PCG15

22U_0805_6.3V6M

@22U_0805_6.3V6M

12

PCG18

180P_0402_50V8J

12

PCG19

PCG20

180P_0402_50V8J

APU_CORE

APU_CORE_NB

2104

2

22

1

23

3

Local

1

+

2

1

+

PCG22

PCG23

2

330U_D2_2V_Y

390U 2.5V M C6 R10M

1

+

PCZ60

PCZ59

2

A A

5

330U_D2_2V_Y

1

+

PCZ62

PCZ61

2

330U_D2_2V_Y

Security Class ification

2011/07/ 29

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/07/ 29

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Rev

A3

Date: S heet of

2

Date: S heet of

Compal Electronics, Inc.

PROCESSOR DECOUPLING

VALGD MB L

49 2Friday, April 12, 2013

1

0.3

A

+3VGS

1 2

PR801 10K_0402_1%PR801 10K_0402_1%

1 1

PR820

1 2

EC_VGA_EN<36>

0_0402_5%

VGA_VR_ON

GPU_VID5

1 2

PR803 @10K_0402_1%@PR803 @ 10K_0402_1%@

PR802 10K_0402_1%PR802 10K_0402_1%

GPU_VID3

GPU_VID4

1 2

PR804 10K_0402_1%PR804 10K_0402_1%

PR806 @10K_0402_1%@PR806 @ 10K_0402_1%@

PR805 @10K_0402_1%@PR805 @ 10K_0402_1%@

GPU_VID2

GPU_VID1

GPU_VID0

B

VBOOT:

10K_0402_1%

Mars XT:0.85V 0110100 San Pro:0.9V 0110000

1 2

PR807 @10K_0402_1%@PR807 @10K_0402_1%@

PR808 @10K_0402_1%PR808 @10K_0402_1%

PR809 10K_0402_1%PR809 10K_0402_1%

GPU_VID3

GPU_VID5

GPU_VID4

1 2

PR810 @10K_0402_1%PR810 @10K_0402_1%

PR811 10K_0402_1%PR811 10K_0402_1%

PR812

GPU_VID2

GPU_VID1

GPU_VID0

C

+VGA_B+

@PC801

@

12

PC801

@0.1U_0402_25V6

12

PC802

2200P_0402_50V7K

12

PC803

PC804

10U_0805_25V6K

D

PL801

HCB2012KF-121T50 0805

1 2

PL804

1 2

HCB2012KF-121T50 0805

B+

PR816

@2.2K_0402_1%

1 2

+3VS

PR818

@PR818

12

PR831

1.91K_0402_1%

+3VS

47K_0402_1%

499_0402_1%

1 2

1.4K_0402_1%

1 2

12

1 2

@0_0402_5%

PR819

1 2

2.2K_0402_1%

PR830

@1.91K_0402_1%

1 2

@0_0402_5%

1 2

PR835

@2.2K_0402_1%

PR836

PR842

PR843

ISEN2_VGA

ISEN1_VGA

@0_0402_5%

1 2

PR863

A

@

100K_0402_1%

1 2

PR834

12

VW_VGA

1 2

PC871

22P_0402_50V8J

FB1_VGA

390P_0402_50V7K

@PR863

@

1 2

PR850

10_0402_1%

PR861

1 2

10_0402_1%

DPRSLPVR_VGA-1

CLK_ENABLE#_VGA

PR833

COMP_VGA

FB_VGA

ISEN3_VGA

PC874

1 2

12

VSUM-_VGA

330P_0402_50V7K

1000P_0402_50V7K

RBIAS_VGA

PC850

PSI#_VGA

0.22U_0402_10V6K

PC859

PC862

PU801

1 2 3 4 5 6 7 8 9

10

41

PR864

@PR864

@

@0_0402_5%

1 2

12

PC875

0.22U_0402_10V6K

PGOOD PSI# RBIAS VR_TT# NTC VW COMP FB ISEN3 ISEN2

AGND

12

39

40

37

38

VR_ON

CLK_EN#

DPRSLPVR

ISEN111VSEN12RTN13ISUM-14ISUM+15VDD

ISUM-_VGA

35

VID031VID132VID233VID334VID536VID6

VID4

BOOT2 UGATE2 PHASE2

VSSP2

LGATE2

VCCP

PWM3

LGATE1

VSSP1

PHASE1

VIN

IMON18BOOT119UGATE1

ISL62883CHRTZ-T_TQFN40_5X5

17

16

20

VDD_VGA

VIN_VGA

12

PC876

1U_0603_10V6K

PR862

PR862 931_0402_1%

931_0402_1%

1 2

GPU_GPIO0<17,50>

+3VS

VGA_PWRGD

2 2

@PR840

@

PR840

@120K_0402_1%

3 3

150P_0402_50V8J

4 4

1 2

PC848

1 2

GPU_GPIO0<17,50>

12

PR841

8.06K_0402_1%

PC847

33P_0402_50V8J

1 2

FB2_VGA

221K_0402_1%

61.9K_0402_1%

+VGA_CORE

VGA_CORE_SEN<20>

VGA_VSS_SEN<20>

12

PC873

1000P_0402_50V7K

PR846

1 2

PR849

+5VS

GPU_VID5

PR845

1 2

0_0402_5%

1 2

PR848

1_0402_5%

PC877

0.22U_0603_25V7K

<17>

GPU_VID4

30 29 28 27 26 25 24 23 22 21

12

PC860

0.33U_0603_10V7K

GPU_VID3

IMON_VGA

+VGA_B+

+5VS

PC861

0.047U_0603_25V7K

<17>

GPU_VID2

12

PC849

12

PC866

0.1U_0402_16V7K

<17>

@0.047U_0402_16V7-K

PR859

11K_0402_1%

<17>

GPU_VID1

GPU_VID0

PC812

PC812 1U_0603_10V6K

1U_0603_10V6K

1 2

12

PC872

PC872 1U_0603_10V6K

1U_0603_10V6K

0_0402_5%

1 2

PR844

1 2

VGA_IMVP_IMON<36>

PR865

PR865 @0_0402_5%

@0_0402_5%

PR847

1 2

@11K_0402_1%

VGA_VSS_SEN

VSUM+_VGA

12

PR853

2.61K_0402_1%

NTC_VGA

12

PH802

PH802 10K_0402_1%_TSM0A103F34D1RZ

10K_0402_1%_TSM0A103F34D1RZ

Layout Note: Place near Phase1 Choke

VSUM-_VGA

B

HGATE2_VGA_1 H GATE2_VGA

BOOT2_VGA BOOT2_2_VGA

+5VS

BOOT1_VGA

PR854 0_0603_5%PR854 0_0603_5%

2.2_0603_5%

12

1 2

PC806

1 2

0.22U_0603_10V7K

LGATE2_VGA

PR817

+VGA_CORE

12

PC824

2.2U_0402_6.3V6M

12

PC840

10U_0603_6.3V6M

PR851 0_0603_5%PR851 0_0603_5%

HGATE1_VGA_1 HGATE1_VGA

PR852

2.2_0603_5%

PHASE1_VGA

LGATE1_VGA

1 2

PC858

0.22U_0603_10V7K

12

BOOT1_1_VGA

0.22U_0603_10V7K

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

PQ801

CSD87351Q5D_SON8-7

PHASE2_VGA

12

PC825

PC841

PC827

PC826

2.2U_0402_6.3V6M

10U_0603_6.3V6M

2.2U_0402_6.3V6M

12

PC843

PC842

10U_0603_6.3V6M

PQ802

CSD87351Q5D_SON8-7

2011/06/30 2012/12/31

C

2

3

4

12

PC828

PC829

2.2U_0402_6.3V6M

12

PC844

PC845

10U_0603_6.3V6M

2

3

4

Compal Secret Data

1

7 6 5

8

12

PC831

PC830

2.2U_0402_6.3V6M

PC846

10U_0603_6.3V6M

1

7 6 5

8

Deciphered Date

12

2.2U_0402_6.3V6M

PC851

0.36UH_PDME104T-R36MS0R825_37A_20%

PL802

1

SW2_VGA

12

@PR826

@

PR826

@4.7_1206_5%

SNUB2_VGA

@PC811

@

12

PC811

@680P_0402_50V7K

12

PC832

PC833

2.2U_0402_6.3V6M

12

PC852

1U_0402_6.3V6K

@PC878

@

12

PC878

@0.1U_0402_25V6

12

@PR855

@

PR855

@4.7_1206_5%

SNUB1_VGA

@PC865

@

12

PC865

@680P_0402_50V7K

12

PC853

PR827

PC834

12

1U_0402_6.3V6K

PC879

2200P_0402_50V7K

SW1_VGA

12

3.65K_0402_1%

PR828

10K_0402_1%

ISEN2_VGA

VSUM+_VGA

12

PC836

PC835

2.2U_0402_6.3V6M

12

2.2U_0402_6.3V6M

12

PC854

12

PC855

1U_0402_6.3V6K

0.1U_0402_10V7K

+VGA_B+

12

PC880

PC881

10U_0805_25V6K

LF1_VGA

12

PR856

3.65K_0402_1%

PR857

10K_0402_1%

ISEN1_VGA

VSUM+_VGA

4

3

2

PC837

2.2U_0402_6.3V6M

PC856

0.1U_0402_10V7K

0.36UH_PDME104T-R36MS0R825_37A_20%

Title

Size Document Number Rev

Date: Sheet of

V2N_VGALF2_VGA

12

1_0402_1%

PR829

VSUM-_VGA

12

PC839

PC838

2.2U_0402_6.3V6M

12

PC857

0.1U_0402_10V7K

PL803

1

4

3

2

V1N_VGA

12

PR858

Compal Electronics, Inc.

VGA_COREP

VALGD MB L

D

1

+

PC807

2

330U_D2_2V_Y

1_0402_1%

VSUM-_VGA

+VGA_CORE

1

+

2

1

+

PC808

PC810

PC809

2

330U_D2_2V_Y

50 59Friday, April 12, 2013

330U_D2_2V_Y

+VGA_CORE

330U_D2_2V_Y

1.0

5

D D

B+

PL701

HCB2012KF-121T50_ 0805

1 2

12

@PC705

@

PC704

C C

ILMT_0.95V

12

0_0402_5%

0_0402_5% PR706

PR706

PC705

@0.1U_0402_25V6

2200P_0402_50V7K

B+_0.95V

12

PC715

10U_0805_25V6K

ILMT_0.95V

4

PU701

8

IN

9

GND

3

ILMT

2

PG

SY8208DQNC_QFN10_3X3

EN

BS

LX

FB

BYP

LDO

1

6

10

4

7

5

LDO_0.95V

0.95V_EN

PR705

PR705 0_0603_5%

0_0603_5%

1 2

12

PC712

100K_0402_5%

PR707

BST_0.95V_1BST_0.95V

12

PC713

4.7U_0603_6.3V6K

12

PC706

0.1U_0603_25V7K

1 2

FB_0.95V

+3VALW

PR703

20K_0402_1%

1 2

12

PC702

0.1U_0402_10V6K

LX_0.95V

FB=0.6V

3

PXS_PWREN <13,18,36,45,52>

PR704

@ PR704

@

@4.7_1206_5%

1 2

PL702

1UH_PCMB063T-1R0MS_12A_20%

1 2

SNB_0.95V

PC703

@ PC703

@

@680P_0603_50V7K

1 2

12

PR701

59K_0402_1%

12

PR702

100K_0402_1%

+0.95VSP

PC709

330P_0402_50V7K

2

PJ701

112

JUMP_43X118 @

2

+0.95VGS

1

+0.95VSP

12

PC710

47U_0805_6.3V6M

12

PC714

47U_0805_6.3V6M

12

PC711

PC701

22U_0805_6.3VAM

@ PC701

@

@22U_0805_6.3VAM

+0.95V TDC=4.56A

B B

A A

Security Classification

2011/06/15 2012/07/11

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

Title

+0.95VSP

Size Document Num ber Rev

B

Date: Sheet of

2

Date: Sheet of

VALGD MB L

51 62Friday, April 12, 2013

1

0.1

5

D D

PL451

@HCB2012KF-1 21T50_0805

B+

C C

ILMT_1.5V_VRAM LDO_1.5V_VRAM

12

PR457

PR457 @0_0402_5%

@0_0402_5%

1 2

12

PC454

@2200P_0402_50V7K

12

@PC455

@

PC455

@0.1U_0402_25V6

PC456

@10U_0805_25V6K

4

B+_1.5V_VRAM

12

PU451

8

IN

9

GND

3

ILMT_1.5V_VRAM

ILMT

2

PG

@SY8208DQNC_QF N10_3X3

EN

BS

LX

FB

BYP

LDO

1

@0.1U_0603_25V7K

6

BST_1.5V_VRAM

10

LX_1.5V_VRAM

4

FB_1.5V_VRAM

7

5

PC453

1 2

12

PC461

3

12

@4.7U_0603_6.3V6K

EN_1.5V_VRAM

12

@0.1U_0402_10V6K

+3VALW

PC462

@4.7U_0603_6.3V6K

1 2

@30K_0402_1%

PC463

1 2

@0_0402_5%

PR455

@ PR455

@

@4.7_1206_5%

1 2

@1UH_PCM B053T-1R0MS_7A_20%

SNB_1.5V_VRAM

PL452

1 2

PR453

PR454

@ PC452

@

@680P_0603_50V7K

1 2

12

PR451

@30.1K_0402_1%

12

PR452

@20K_0402_1%

2

PC452

12

PXS_PWREN <13,18,36,45,51>

SUSP# <36,40,45,47>

12

PC457

@220P_0402_50V7K

12

PC458

@47U_0805_6.3V6M

1

+1.5VSP

12

PC459

@47U_0805_6.3V6M

PC451

PC460

@ PC451

@

@22U_0805_6.3VAM

PJ451

2

+1.5VSP

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2011/10/03

Compal Secret Data

Deciphered Date

3

2014/12/31

2

112

@JUMP_43X118 @

Title

Size Document Number Rev

Friday, April 12, 2013

Date: Sheet of

+1.5VGS

Compal Electronics, Inc.

+1.5VSP(VRAM)

VALGD MB L

52 99

1

0.1Custom

5

Request

Item

Item Issue Description

ItemItem

D D

C C

Page# Title

Page#Page#

1

P41 add smart Adapter functionPWR12/11

2

P42

3

4

5 P50 P50-PWR-+VGA_CORE 01/08 PWR vender FAE requset change VGA enable pin from SUSP# to EC_VGA_EN

6 P45 P45-PWR-+1.5VP/+1.8VSP 01/08 PWR 0.75V can't power on change 0.75V enable pin from SUSP to SUSP#

P427 P42-PWR-BATTERY CONN/OTP 01/08 PWR modify smart Adapter schematic modify smart Adapter schematic

8 P44 P44-PWR-3VALWP/5VALWP 02/23 PWR Add RC delay for 3V power sequence Add RC delay for 3V power sequence

9 P48 P48-PWR-CPU_CORE/CPU_CORE_NB 02/23 PWR modify over temperature setting modify over temperature setting

10 P42 P42-PWR-BATTERY CONN/OTP 02/23 PWR Units will shut down on Optimized Battery Health mode when plug out battery modify battery health mode schematic

11 P45 P45-PWR-+1.5VP/+1.8VSP 02/23 PWR VRAM transient fail Add remote sense schematic

12 P50 P50-PWR-+VGA_CORE 02/23 PWR AMD change VBOOT SPEC

13 P41,42,48,50 P41,42,48,50 01/10 PWR Add bead for cost down plan Add bead for cost down plan

Title

TitleTitle

P41-PWR-DCIN / RTC Battery

P42-PWR-BATTERY CONN/OTP 12/11 PWR add smart Adapter function

Date

DateDate

RequestRequest Owner

Owner

OwnerOwner

12/11 PWR modify 1.5V output level modify PR701&PR702 to 59K&100KP51-PWR-+0.95VSPP51

4

Version Change List ( P. I. R. List )

Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )

Issue DescriptionDate

Issue DescriptionIssue Description

3

2

Page 1

Page 1Page 1

Solution Description

Solution Description Rev.

Solution DescriptionSolution Description

ADD PQ208,PQ102,PR111,PR225,PR228,PR227;Del PR973,PR974,PR972,PR975

change PQ206,PR110,PR222,PR221,PC109 part number

Add PC802 CAPEMI rulePWRPWRP50-PWR-+VGA_COREP50

change Mars XT VBOOT from 1.1V to 0.85V change Sun pro VBOOT from 1.1V to 0.9V

1

Rev.Page#

Rev.Rev.

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2012/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PWR - PIR

53 46Friday, April 12, 2013

1

0.1

5

Request

Item

Item Issue Description

ItemItem

D D

C C

B B

A A

Page# Title

Page#Page#

1 37 1114

2

38 1114

3

36 1114 1.VR_ON reserve PD 10K

4 1114A17 1.remove RV16,RV17

275 1114A 1.reserve RV687,RV92

6 12,30

7 40 1115

8 13

9 13

13,27,30,37 1.CMOS change port from port1 to port3

10

11 35 1119C 1.change netname from +3V_PCH to +3VALW

12 11 1119D 1.remove R84

13

7 1119D

14 20 1119D 1.change net name from VCCSENSE_VGA to VGA_CORE_SEN

15 36 1119D 1.remove EC_VGA_EN

16 34 1120A 1.reserve Q96,R711

17 7 1120C 1.remove C159,C161,C210,C164

18 26 1120C 1.add RP26,R241,R242

19 26 1121C 1.remove R301,R302,R826,C422,U11

21 19 1122 1.remove CV54,CV55,CV56,CV57,CV58,CV59

22 20 1122 1.remove CV96,CV97

23 36 1122A 1.remove C431,R305,C438,C439

24 7,26,36 1123A 1.remove C113,C115,RP26,R239~242 for eDP circuit

25 17,33,39 1126A 1. Change C736 from SGA00003000 to SE00000T780

26 38 1127 1. Change net name from +3VGS to +1.8VGS on U71 pin11

27 27 1127A 1.Change net name from DISPOFF# to BKOFF#

28 1127A33 1add ZZZ for MB PCB

Title

TitleTitle

5

Date

DateDate

RequestRequest Owner

Owner

OwnerOwner

1115 1.change netname from PCH_BT_ON# to BT_ON#

1116 1.change netname from LAN_CLKREQ# to CLKREQ_LAN#

1116A 1.change netname from WLAN_CLKREQ# to CLKREQ_WLAN#

1116B

1121C 1.remove R6872720

4

Version Change List ( P. I. R. List )

Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )

Issue DescriptionDate

Issue DescriptionIssue Description

1.SW3 add DEBUG@

2.add J13

1.change netname form +3VS_VGA to +3VGS

2.change netname form +V1.05S_VCCP to +3VALW

3.remove RG10

4.change U71 P/N form SA000063300 to SA00006D500 for DIS,.change U71 P/N form SA000057I00 to SA00005DO00 for UMA

2.change netname from PCH_WL_OFF# to WL_OFF#

1.change 1.1VALW to 1.1VS circuit follow QAWYA

2. remove R1138,Q158,R1140(include discharge of 1.2VS and 2.5VS)

3.change SUSP reverse circuit follow QAWYA

4.change SYSON reverse circuit follow QAWYA

5.remove VLDT_EN reverse circuit

6.add +1.5V to +1.5VS follow QAWYA

2.WLAN change port form port7 to port2

3.USB(R)change port form port8 to port0

1.change net name from APU_VDD_RUN_FB_L toAPU_VDD_SEN_L

2.change net name from APU_VDD_SEN to APU_VDD_SEN_H

3..change net name from APU_VDDNB_SEN to APU_VDDNB_SEN_H

2.change net name from VSSSENSE_VGA to VGA_VSS_SEN

2.remove VGA_AC_DET

2.change net name from LVDS_A1 to DP0_TXP1_C

3.change net name from LVDS_A1# to DP0_TXN1_C

2.add R826

3.add "ENBKL"signal

4. change EC GPIO(VGATE and EC_TS_ON)

2. Remove Q11

3. Set RV24,RV25,QV3 are @

4. Add REMOTE1+ to UV1.AF29 & REMOTE1- to UV1.AG29

2.update P04 table

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2

Page 1

Page 1Page 1

Compal Secret Data

2008/09/15 2012/12/31

Compal Secret Data

Deciphered Date

2

1

Solution Description

Solution Description Rev.

Solution DescriptionSolution Description

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PIR

VALGD MB L

1

Rev.Page#

Rev.Rev.

54 99Friday, April 12, 2013

2.0

5

Request

Item

Item Issue Description

ItemItem

D D

C C

B B

A A

Page# Title

Page#Page#

29 11,18,31,38 1128

30 31 1128 1.remove GCLK@ in RL3,CL7,QL1

31 37 1128 1.change U40 P/N to SA00005LN00

32 28 1128A 1.change RP22 to RV94~RV96

33 32 1128B 1.change CL30 P/N to SE067102K80

34 11 1128B 1.change CLK_PCIE_LAN/CLK_PCIE_LAN# form port0 to port3

35 28 1128B 1.add R3334,R3335

36 26 1129 1.add RA10,RA11,RA15,RA24,R1459,R1460

37 36,41 1129 1.add signal"ADP_ID_CLOSE"for smart adapter function

38 32,33 1130 1.remove OPT@ of C587

39 5,16 1130 1.change cap form .22u to .1u for PCIE Gen2

40 113035 1.change shot pad to .1u for CA64~CA66

41 39 1204 1.change JTS1 conn to SP010013W10

42 12,30 1204A 1.remove BT_ON#,add BT_DISABLE#

43 07 1204A 1.RP9.4 connect to +1.5V_APU,R348.1 connect to +1.5VS for leakage issue

44 11,18,31,38 1.add R801,R207,RV40,RL13,CL27 for GCLK circuit

45 36

46 1.change RG2 to 10ohm,RG3 to 33ohm,RG4 to 33ohm

47 39 1206A 1.change C736 to SE00000PL00(0805 package)

48 38 1210 1.add GCLK@ in RG2,RG3,RG4

49 55,56 1210A 1.add P55,P56

50 03,12,33,37,39 1212 1.update BOM Structure Table

51 41~52 1213 1.update PWR circuit for BOM

52 20 1220 1.change LV7 BOM structure from PX@ to SHORT PAD@

53 40 1220 1.remove @ in Q157A

54 20 1224 1.add TEST POINT@ to TV15

55 18 1224 1.change net name from PXS_PWREN to PXS_PWREN# in QV2.2

56 28 1224 1.remove C528 based on LA-9901 DVT schematic

57 37 1224 1.change JKB1 from SP01000WK00 to SP010011A00

58 34 1224 1.change JODD2 from SP01001FJ00 to SP010016C00

Title

TitleTitle

Date

DateDate

RequestRequest Owner

Owner

OwnerOwner

1204B

1205 1.change net name form NOVO# to EC_FAN_PWM in EC

120638

4

Version Change List ( P. I. R. List )

Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )

Issue DescriptionDate

Issue DescriptionIssue Description

1.remove R801,R207,RV40,RL13,CL27 for GCLK circuit

2.GCLK circuit in p.38

2.change LL1 P/N to SHI00008W00

2.change CLK_PCIE_WLAN1/CLK_PCIE_WLAN1# from port1 to port2

2.change from @EMI@ to EMI@ for CL30

2.add GCLK circuit in p.38

2.change net name form EC_FAN_PWM to NOVO# in EC

3.change net name form ENBKL to APU_IMON in EC

4.change net name form APU_IMON to ENBKL in EC

2.U74.2 change from +3V_LAN to +3VALW

2.change U3 symbol to SA00003K820

3.change U35,U36 symbol to SA00003TV00

4.change U99 P/N to SA00001Z710

2.change JTP1,JPWRB1 from SP010014M10 to SP010010T00

3

Page 2

Page 2Page 2

2

Solution Description

Solution Description Rev.

Solution DescriptionSolution Description

1

Rev.Page#

Rev.Rev.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2012/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PIR

VALGD MB L

55 99Friday, April 12, 2013

1

2.0

5

Request

Item

Item Issue Description

ItemItem

D D

C C

B B

A A

Page# Title

Page#Page#

59 35 1224

3760 1224 1.change JLED1 from SP01001A900 to SP010010T00

61

24,25 1225

62

26

63

29 1225 1.change Q93 & Q95 to Q93A & Q93B

63

27 0105 1.Change BID R311=>18K

64

35 0107 1.RA12,RA16 change to 100-ohm., RA13, RA14 to 15-ohm, ADD CA27,CA28 to 1uF

65

65 36 0108 1.add PXS_PWREN & EC_VGA_EN

66 14 ,34 0108 1.Change R177 ,180 & R550 from 0805 short pad to Jumper (J14, J15, & J10)

66 35 0110 1.RA22=>DEBUG@ for Beep 2. CA28 CA27=>2.2u for THD+N

68 011133 1.ADD ZZZ & ZZZ1 for 14"_DIS & 15"_DIS pcb

69 12 0114 1.ADD GPIO54 for RTD2132R@ 2.change U99

70 0116 1.change H21 from 2P8 to 4P6 2.change U99 to 1001101x (4D)33

1 1.add C737 &C735@ for USB droop (follow Intel)

72

28 0121 1.L30, L31 & L32 downsize to 0402,SM010005X00

73

39 1/21 L51,L55,L58 &L66 change PN to SM070001N00 for action plan

74

29

75

10 0126 SIT: change C145 from OS-Con to POLY

76

78 36 0201 2/1 SIV: add PU resistor for LID_SW#

9 1.upgrade capacitors of CA36 & CA46 from 1uF to 2.2uF/X5R 2.AVDD_HP connect to standby power rail (+3VLP) for prevent speaker hum noise issue.0221

357

2080 1.Change Cap of CV66 to 220U 4V Y D2 ESR15M = SGA00000Y80 for PWR request0221

3881 1.add CG5 on 1.8VGS for GCLK 2.reserve CG6 & CG7 for vender request.0221

22~2582 1. p22 & p23==>Channel B Mars@ 2.p24 & p25==>ChannelA PX@0221

3583 1. add speaker bypass Cap CA38,CA39,CA40 & CA43 for EMI requirement0225

0784 1. add C438 100pF on H_THERMTRIP# for ESD requirement0226

3485 SIT: 3/1 Change footprint of JHDD1 from SANTA_191501-1_22P to LCN_ASF98-2231S10-0002_22P (DC010005W00 toDC010009C00)0301

3486 Del CV168 ,CV159,CV160 &CV189 for VRAM body size issue0301

3787 change C492, SE00000FD80 to SE074331K80 by Sourcer requiremrnt.0301

88 LV4,LV10,L3,L6,L9,L11& L77 Downsize to 0402 BLM15AX221SN1D (Murata) ,SM01000MK00 by Sourcer requiremrnt.0301

89 Add R311=8.2K for SIT030136

90 Change R85 from 0 ohm short pad @ to 33 ohm EMI@030111

5

Title

TitleTitle

Date

DateDate

RequestRequest Owner

Owner

OwnerOwner

1225

011067 27, 32 and 37 1.R813=>220 ohm Bead 2.Add C492 for EMI request 3.DLL1=>EMI@

0116397

0121 1.change D24 to SCA00001G00 for ESD request

0121

0121 1/21 L35,L36,L37 &L38(HDMI) L49,L50,L53 & L54(USB3) change PN from SM070001S00 to SM070003K00 for action plan

01293777 1/29 SIT: Del R806 & Q12 for change audio type from normal close to normal open.

4

Version Change List ( P. I. R. List )

Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )

Issue DescriptionDate

Issue DescriptionIssue Description

1.change JSPK1 from SP02000RR00 to SP02000H700

1.change U99 from SA00001Z710 to SA000067P0033

1.change CHB form PX@ to MARS@

1.change Panel PWM circuit 2132R@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2

Page 3

Page 3Page 3

Compal Secret Data

2008/09/15 2012/12/31

Compal Secret Data

Deciphered Date

2

1

Solution Description

Solution Description Rev.

Solution DescriptionSolution Description

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PIR

VALGD MB L

Rev.Page#

Rev.Rev.

56 99Friday, April 12, 2013

1

2.0

5

Request

Item

Item Issue Description

ItemItem

D D

Pre-MP 100 33 0311 1.Change U99 to SA00001Z710

C C

Page# Title

Page#Page#

91 26 0301

92

93

26 0304 1.add R1462 for RTD2132R ,MIIC_SDA :MIIC_SCL=0 : 1 2.Del RP16.3 & RP16.4

4 0304 1.Change R367 from 10K to 100K. 2.Change R234 from 10K to 100K

12,139

3294 0305 1.add CL32 & CL33 for ESD request.

95 32 0

96 8 0306 1.add J3 for 1.5V

96 33 0306 1.Change Power rail of the U99 from +3VS to +3VGS.

97 12 0306 1.Change Power rail of the GPIO54 from +3VALW to +3VS.

98 12 0307 1.Change +1.5GVS enable pin from +VSB to +5Valw for Eup lot 6.

99 12,36 0311 1.Change BOM structure of R367 & R368 to @,2132S only 2.R237 & R236 =>@

Title

TitleTitle

Date

DateDate

RequestRequest Owner

Owner

OwnerOwner

306 1.add R236 & R237 (LVDS_SEL) for C build only.

4

Version Change List ( P. I. R. List )

Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )

Issue DescriptionDate

Issue DescriptionIssue Description

1.add R1461 for RTD2132R ,MIIC_SDA :MIIC_SCL=0 : 1

1.Change +VDDIO_HDA power rail from +3VALW to +3VS.35 0301

1.Reduce part count for RTD2132R only040312,36 & 26Pre-MP 101

1.Reduce part count for RTD2132R only040312,36 & 26Pre-MP 102

1.ODD Power Control cuicuits =>@040334Pre-MP 103

1.Change H17 form H_8P0N to H_7P0N SD309100280041033Pre-MP 104

1.Change RP11 form SD309100280(10K) to SD309100300(100K)041036Pre-MP 105

1.Change RV41 to 47K for Erp Lot6041018Pre-MP 106

1.Change RV37 from 20Kto 100K ,RV38 from 20K to 0 ohm.041018Pre-MP 107

1.Change RV37 from 20Kto 100K ,RV38 from 20K to 0 ohm.041018Pre-MP 108

1.Del Net VLDT_EN & 1V_ALW_EN041136Pre-MP 109

1.change C438 from 100p to 1000p. 2. add C439, 1000p for ESD request.04127, 13Pre-MP 110

3

Page 3

Page 3Page 3

2

Solution Description

Solution Description Rev.

Solution DescriptionSolution Description

1

Rev.Page#

Rev.Rev.

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2012/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PIR

VALGD MB L

57 99Friday, April 12, 2013

1

2.0

A

B+

PU401 SY8208BQKC

EC_ON

B

C

D

E

+3VLP

+3VALW

+EC_VCCA

QL1 PMV65XP

1 1

U35P TPS22966DPUR

LAN_PWR_ON#

SUSP#

U315V TPS22966DPUR

Q70 PMV65XP

PXS_PWREN

CMOS_ON#

+3V_LAN

+3VS

+3VGS

+3V_CMOS

PU502 SY8033BDBC

2 2

PU402 SY8208CQKC

PU501 RT8207MZQW

3 3

PU601 TPS51212DSCR

PU801 ISL62883CHRTZ

4 4

PU901 ISL62771HRTZ

A

EC_ON

U35P TPS22966DPUR

SUSP# / SYSON

Q20 LP2301ALT1G

U315V TPS22966DPUR

SPOK , 095_18ALW_PWR_EN

U1895P TPS22966DPUR

U1895V TPS22966DPUR

EC_VGA_EN

VR_ON

SPOK , 095_18ALW_PWR_EN

SUSP#

PXS_PWREN

095VS_PWR_EN

PXS_PWREN

B

U1895P TPS22966DPUR

U1895V TPS22966DPUR

+1.8VALW

SUSP#

+1.8VS

PXS_PWREN

+1.8VGS

+VL

+5VALW

+5VS

+0.75VS

+1.5V

+1.5VS

+1.5VGS

+0.95VALW

+0.95VS

+0.95VGS

+VGA_CORE

+APU_CORE

+APU_CORE_NB

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Power Map

VAWGA/GB

E

58 99Friday, April 12, 2013

0.1

5

B

+B+

D D

PU403 +5VALW / VL

VV

PU401 +3VALW/+3VLP

3A 4B

SPOK

PU601

V

+1.1VALW

4

+3VLP +3VALW

B+

V

2A 3B

1V_ALW_EN

EC_ON

EC

VV

4A

4B

5

3

EC_RSMRST#

BTN_OUT#

P

V

SLP_S3# / SLP_S5#

+3VALW/ +3VS / +1.1VALW /+1.1VS /

+2.5VS / +1.2VS / +1.5V / +1.5V_APU

+APU_CORE / +APU_CORE_NB

5

6

7

10KBRST#

V V

V

APU/FCH

+RTCBATT

2

20

PXS_RST#

19

APU_PCIE_RST#

17 APU_PWRGD

+3VGS

V

U5 A

ND GATE

V

21

GPU_RST#

1

+3VGS / +1.5VGS

+1.8VGS / +0.95VGS

GPU

V

MarsXT

+3VS +1.5VA

+VGA_CORE

BATT MODE BATT+

AC MODE VIN

C C

B B

+CHGRTC_R +3VLP

+RTCBATT

BATT+

1B

V

IN

1A

PU301 B+

ON/OFF

2B

4A

APU_PWRGD

R_ON

V

3VALW

+

+5VS / +3VS / +1.8VS

17

PU901 +APU_CORE /

14

+APU_CORE_NB

V V

+5VALW

B+

PU501

V

B++5VALW

15

VGATE

+3VALW

U54 +3VS

V

SYSON

8

+5VALW

V V

V

EC_VGA_EN

18LPC_RST#

11

+1.8VALW

PU502 +1.8VGS

SUSP#

9

+5VALW

U54

V

B+

+5VS

B+

PU701 +0.95VGS

+1.5V

Q20 +1.5VS

+5VALW

PU602

V

+1.2VS

+3VALW

+5VALW

B+

V

+5VALW

V

VGA_PEWGD

13

PXS_PWREN12

B+

+5VS +3VS

PU801

V

+

VGA_CORE

V

+3VS

Q15

V

+3VGS

+1.5V

UV4

V

+1.5VGS

+5VALW

+VSB

WLAN / WiMAX

V

Mini-Express Card

3V_LAN

+

LAN

V

MODEL NAME:

A A

PCB NAME:

PU501

V

+0.75VS

REVISION: DATE:

COMPAL CONFIDENTIAL

2012/12/10

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Power sequence

1

0.1

Compal LA-A091P VALGC, G505s, G505, LA-A091P VALGD Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual