Compal LA-A041P V1JB1 UMA SAGE 3G Schematic

A
B
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D
E
Compal Confidential
Model Name : SAGE 3G
1 1
Compal Project Name : V1JB1 File Name : LA-A041P
2 2
V1JB1 UMA M/B Schematics Document
Intel Ivy/Sandy Bridge SFF BGA 1023p Processor /Panther Point 989p PCH / DDR3L Memory Down *8
3 3
2013-03-26
REV:2.0
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
B
C
2011/06/24 2012/06/02
2011/06/24 2012/06/02
2011/06/24 2012/06/02
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Cover Page
Cover Page
Cover Page
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
E
1 52Tuesday, March 26, 2013
1 52Tuesday, March 26, 2013
1 52Tuesday, March 26, 2013
2.0
2.0
2.0
A
B
C
D
E
1 1
Fan (PWM)
page 34
eDP Conn.
page 22
eDP
120MHz
Intel
Ivy Bridge ULV
Processor
Memory BUS(DDR3L)
Dual Channel
1.35V DDR3L 1333
DDRIII-ON BOARD
page 11,12
BGA1023
DDRIII-ON BOARD
page 4~10
HDMI Conn.
page 23
100MHz 100MHz
2.7GT/s
2 2
PCI-Express x 8 (PCIE2.0 5GT/s)
port 2
Card Reader
Realtek RTS5209
page 32
port 1
WLAN
On Board WLAN/BT MD222
page 24
SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S)
mSATA Module
TMDS
port 0,1
page 25
100MHz
100MHz
SMLink
Intel
Panther Point-M
PCH
989pin BGA
DMI x4FDI x8
1GB/s x4
page 13~21
USBx14
HD Audio
SPI
JEDP1
USB port 3
page 22
Ext. USB3.0 JUSB1
USB20 port 1 USB30 port 2
3.3V 48MHz
3.3V 24MHz
SPI ROM (ME-2MB)
page 13
Touch Screen
PROX SENSOR STM8T143
3 3
Connect to EC
RTC CKT.
page 13
Sub/Board
SMLink1
HSPI
ITE IT 8518
LPC BUS
33MHz
page 28
TPM SLB9655
page 26
Camera1 JCMOS1(FRONT)
USB port 10
page 27
page 27
BT - On Board WLAN
USB port 8
page 24
HDA Codec
ALC271X-VB6 SUB/B
Int. Speaker Phone Jack
WLAN Frequency :
802.11b/g/n : 2.412 ~ 2.4835 GHz
802.11a/n : 5.15 ~ 5. 85GHz
Power On/Off CKT.
page 29
DC/DC Interface CKT.
page 34
Power Circuit DC/DC
4 4
page 35~46
A
Sub/Board
Sub/Board
ALS CM3218
page 30
ACCEL with E-COMPASS LSM303D
page 30
B
Sensor Hub STM32F
page 30
I2C1
GYRO L3GD20TR
page 30
USB Port 0
BT Frequency :
2.402~2.480 GHz
FSPI
SMBUS1
SPI ROM (BIOS+EC) (4MB)
page 28
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
SMBUS2
C
Battery Charger IC
page 36, 37
WWAN: WCDMA/HSDPA/HSUPA/HSPA+: 850 MHz/900 MHz/1700 MHz(AWS)/1900 MHz/2100 MHz GPRS/EDGE:
Thermal Sensor
page 11
Compal Secret Data
Compal Secret Data
2011/06/24 2012/06/02
2011/06/24 2012/06/02
2011/06/24 2012/06/02
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
850 MHz/900 MHz/1800 MHz/1900 MHz GPS: L1
D
Camera2 JCMOS2(REAR)
USB port 11
page 33
Sub/Board
3G Module MU736
USB port 2
page 31
Sub/Board
Int. MIC
COM_MIC
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Block Diagrams
Block Diagrams
Block Diagrams
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
Digital MIC
E
page 33
2 52Tuesday, March 26, 2013
2 52Tuesday, March 26, 2013
2 52Tuesday, March 26, 2013
0.1
0.1
0.1
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B
C
D
E
Voltage Rails
S1
Power Plane Description
VIN
BATT+ Battery power supply (12.6V) N/A N/A N/A
B+
1 1
+CPU_CORE
+VGFX_CORE Core voltage for UMA graphic ON OFF OFF
+1.05VS_VTT
+1.35V
+1.35VS
+0.675VS +0.675VSP to +0.675VS switched power rail for DDR3L terminator
+1.5VS +1.5VSP to +1.5VS power rail for PCH
+1.8VS (+5VALW or +3VALW) to 1.8VS switched power rail for PCH
+3VALW +3VALWP to +3VALW always on power rail
+VCCSUS3_3 +3VALW to +VCCSUS3_3 power rail for PCH ON ON
+3VS
+5VALW
+V5REF_SUS
2 2
+5VS +5VALW to +5VS switched power rail OFFON OFF
+VSB +VSBP to +VSB always on power rail for sequence control ON ON*
+RTCVCC RTC power
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
+1.05VS_VTTP to +1.05VS_VTT switched power rail for CPU
+1.35VP to +1.35V power rail for DDR3L
+1.35V to +1.35VS switched power rail
+3VALW to +3VS power rail
+5VALWP to +5VALW always on power rail
+5VALW to +V5REF_SUS power rail for PCH
S3 S5
N/A N/A N/A
N/AN/AN/A
OFF
ON
ON OFF OFF
ON OFF OFF+1.05VS_PCH +1.05VS_VTT to +1.05VS_PCH power for PCH
ON ON OFF
ON OFF OFF
ON OFF OFF
ON OFF OFF
ON
ON
ON
ON
ON ON
ON
ON
OFF
OFF
OFF
ON ON*
ON*
OFF
OFF
ON ON*
ON*
ONON
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
Board ID / SKU ID Table for AD channel
Vcc 3.3V +/- 5%
Board ID
0 1 2 3 4 5 6 7 NC
BOARD ID Table
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
EC SM Bus1 address
Device
Smart Battery
Address Address
0001 011X b
PCH SM Bus address
Device Address
ChannelA
ChannelB
3 3
A0A41010 000X
1010 010X
EC SM Bus2 address
Device
Sensor HUB SM Bus address
Device Address
Gyroscope
E-compass + G sensor
ALS sensor
D1 1101 000X b
D3 1101 001X b
33 0011 001X b
0010 000X b21
BOM Config
Sensors List
Connect to Sensor Hub Sensor Hub PCH(USB P3) Sensor Hub EC
4 4
Function
Gyroscope Accel+E-Compass
Device
ST - L3GD20TR
ST - LSM303DLHCTR Sensor Hub ST - STM32F103RCY6TR ALS Capella - CM3218
ST-STM8T143AU62TTRC06Prox
Board ID
0 1 2 3 4 5 6 7
Note :
USB Port Table
USB 2.0 USB 1.1 Port
EHCI1
EHCI2
SIGNAL
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
HIGH HIGH HIGH HIGH
LOW
LOW
LOW
HIGH
LOW LOW LOW LOW
100K +/- 5%Ra/Rc/Re
Rb / Rd / Rf V min
0
8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%
AD_BID
0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
PCB Revision
0.1
0.2
0.3
1.0
2.0*
2 External USB Port
0
UHCI0
UHCI1
UHCI2
UHCI3
UHCI4
UHCI5
UHCI6
Sensor Hub
1
Ext. USB Connector
2
3G Module - MU736/ME906
3
Touch Screen
4 5 6 7 8
BlueTooth(WLAN Module)
9
Debug Port(Reserve)
10
Camera(Front)
11
Camera(Rear)
12 13
LOWLOWLOW
ON
ON
ON
HIGHHIGHHIGH
HIGH
HIGH
V typ
AD_BID
ON
ON
ON
ON
OFF
ON
OFF
V
0 V 0 V
0.503 V
0.819 V
1.185 V 1.264 V
2.200 V
3.300 V
BTO Item BOM Structure
Unpop
UMA UMA@ CPU DDR3 DDR3L On Board DRAM Dual Channel DDR 128@
PCH Normal S3 Deep S3 TPM TPM@ Non TPM SKU WOTPM@
Foxconn MD222 Lite-On MD222
For EMI/RF(Unpop) XEMC@ Sensor(Intel F/W) INTEL@ Sensor(ST F/W) ST@
ON ON
ON
LOW
OFF
OFF
OFF
OFF
OFF
OFF
max
AD_BID
0.538 V
0.875 V
2.341 V
3.300 V
BTO Option Table
@ CONN@Connector
IVB@ DDR3@ DDR3L@ X76@
eDP@eDP HM77@ S3@ DS3@
LID@Hall Sensor FOXMD222@ LIONMD222@ EMC@For EMI/RF(Pop)
3G@3G SKU 3GEMC@3G SKU(EMC part)
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
B
C
2011/06/24 2012/06/02
2011/06/24 2012/06/02
2011/06/24 2012/06/02
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Notes List
Notes List
Notes List
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
E
3 52Wednesday, March 13, 2013
3 52Wednesday, March 13, 2013
3 52Wednesday, March 13, 2013
0.1
0.1
0.1
A
B
C
D
E
+1.05VS_ VTT
12
R532
R532
24.9_040 2_1%
24.9_040 2_1%
UCPU1A
1 1
DMI_CRX_P TX_N015 DMI_CRX_P TX_N115 DMI_CRX_P TX_N215 DMI_CRX_P TX_N315
DMI_CRX_P TX_P015 DMI_CRX_P TX_P115 DMI_CRX_P TX_P215 DMI_CRX_P TX_P315
DMI_CTX_P RX_N015 DMI_CTX_P RX_N115 DMI_CTX_P RX_N215 DMI_CTX_P RX_N315
DMI_CTX_P RX_P015 DMI_CTX_P RX_P115 DMI_CTX_P RX_P215 DMI_CTX_P RX_P315
FDI_CTX_P RX_N015 FDI_CTX_P RX_N115 FDI_CTX_P RX_N215
2 2
eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mohms should not be left floating ,even if disable eDP function...
+1.05VS_ VTT
12
R118
R118
24.9_040 2_1%
24.9_040 2_1%
W=4mil,S=15mil,L=500mil
3 3
W=12mil,S=15mil,L=500mil
Add eDP circuit
+1.05VS_ VTT
12
R809
R809 1K_0402 _5%eDP@
1K_0402 _5%eDP@
EDP_HPD #22
EDP_HPD #
FDI_CTX_P RX_N315 FDI_CTX_P RX_N415 FDI_CTX_P RX_N515 FDI_CTX_P RX_N615 FDI_CTX_P RX_N715
FDI_CTX_P RX_P015 FDI_CTX_P RX_P115 FDI_CTX_P RX_P215 FDI_CTX_P RX_P315 FDI_CTX_P RX_P415 FDI_CTX_P RX_P515 FDI_CTX_P RX_P615 FDI_CTX_P RX_P715
FDI_FSYNC015 FDI_FSYNC115
FDI_INT15
FDI_LSYNC015 FDI_LSYNC115
EDP_COM P
EDP_HPD #
EDP_AUX N22 EDP_AUX P22
EDP_TXN 022 EDP_TXN 122
EDP_TXP 022 EDP_TXP 122
UCPU1A
M2
DMI_RX#[0]
P6
DMI_RX#[1]
P1
DMI_RX#[2]
P10
DMI_RX#[3]
N3
DMI_RX[0]
P7
DMI_RX[1]
P3
DMI_RX[2]
P11
DMI_RX[3]
K1
DMI_TX#[0]
M8
DMI_TX#[1]
N4
DMI_TX#[2]
R2
DMI_TX#[3]
K3
DMI_TX[0]
M7
DMI_TX[1]
P4
DMI_TX[2]
T3
DMI_TX[3]
U7
FDI0_TX#[0]
W11
FDI0_TX#[1]
W1
FDI0_TX#[2]
AA6
FDI0_TX#[3]
W6
FDI1_TX#[0]
V4
FDI1_TX#[1]
Y2
FDI1_TX#[2]
AC9
FDI1_TX#[3]
U6
FDI0_TX[0]
W10
FDI0_TX[1]
W3
FDI0_TX[2]
AA7
FDI0_TX[3]
W7
FDI1_TX[0]
T4
FDI1_TX[1]
AA3
FDI1_TX[2]
AC8
FDI1_TX[3]
AA11
FDI0_FSYNC
AC12
FDI1_FSYNC
U11
FDI_INT
AA10
FDI0_LSYNC
AG8
FDI1_LSYNC
AF3
eDP_COMPIO
AD2
eDP_ICOMPO
AG11
eDP_HPD#
AG4
eDP_AUX#
AF4
eDP_AUX
AC3
eDP_TX#[0]
AC4
eDP_TX#[1]
AE11
eDP_TX#[2]
AE7
eDP_TX#[3]
AC1
eDP_TX[0]
AA4
eDP_TX[1]
AE10
eDP_TX[2]
AE6
eDP_TX[3]
IVY-BRIDGE_BGA1 023
IVY-BRIDGE_BGA1 023
IVB@
IVB@
CPU P/N:
1.I3-3217 SA00005L5C0:S IC AV8063801058401 SR0N9 L1 1.8G ABO!
2.I5-3317 SA00005K6B0:S IC AV8063801058002 SR0N8 L1 1.7G ABO!
3.I3-2365 SA000051H60:S IC AV8062701047904 SR0CV J1 1.4G ABO!
DMI Intel(R) FDI
DMI Intel(R) FDI
eDP
eDP
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]
PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]
PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]
PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]
PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8]
PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]
PCI EXPRESS -- GRAPHICS
PCI EXPRESS -- GRAPHICS
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9]
G3 G1 G4
H22 J21 B22 D21 A19 D17 B14 D13 A11 B10 G8 A8 B6 H8 E5 K7
K22 K19 C21 D19 C19 D16 C13 D12 C11 C9 F8 C8 C5 H6 F6 K6
G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4
F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4
PEG_COM P
G3,W=4mil,S=15mil,L=500mil G1,W=12mil,S=15mil,L=500mil G4,W=4mil,S=15mil,L=500mil
UCPU1_B 22
UCPU1_A 19
UCPU1_B 14
UCPU1_A 11 UCPU1_B 10
UCPU1_B 6
T25 PAD@ T25 PAD@
T26 PAD@ T26 PAD@
T27 PAD@ T27 PAD@
T22 PAD@ T22 PAD@ T34 PAD@ T34 PAD@
T39 PAD@ T39 PAD@
UMA only=>PEG NC
PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with - max length = 500 mils­typical impedance = 14.5 mohms
SAGE 3G PVT For DFB demand
4 4
Security Class ification
Security Class ification
Security Class ification
2011/06/ 24 2012/06/ 02
2011/06/ 24 2012/06/ 02
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2011/06/ 24 2012/06/ 02
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(1/7) DMI,FDI,PEG
PROCESSOR(1/7) DMI,FDI,PEG
PROCESSOR(1/7) DMI,FDI,PEG
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
4 52Wednesd ay, March 13, 20 13
4 52Wednesd ay, March 13, 20 13
4 52Wednesd ay, March 13, 20 13
E
0.1
0.1
0.1
A
B
C
D
E
1 1
PCH->CPU UNCOREPWRGOOD: SM_DRAMPWROK:DRAM power ok RESET#:
ok
CPU
CORE
reset
OK
Follow DG 1.2 & CRB1.0
@
@
C784 0.1U_0201_10V6K
C784 0.1U_0201_10V6K
R223 10K_0402_5%R223 10K_0402_5%
12
12
Follow DG 1.2 & CRB1.0 Use open drain MOS:
Buffered reset to CPU
2 2
PLT_RST#17,26,28,31,32
RESET#:
+3VS
1
NC
2
A
ok
5
P
G
3
H_CPUPWRGD
H_CPUPWRGD
SAGE 3G
1
2
U15
U15
Y
SN74LVC1G07DCKR_SC70-5
SN74LVC1G07DCKR_SC70-5
CPU
Processor Pullups follow CRB1.0
+1.05VS_VTT PH pop 75ohm series resister pop 43ohm
+1.05VS_VTT
C396
C396
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4
BUFO_CPU_RST#
reset
H_PROCHOT#28,36
PROC_SELECT# Future platforms,PH VCPLL and connect to PCH DF_TVS
H_SNB_IVB#17
CPU
XBOX
12
H_THRMTRIP#18
H_CPUPWRGD18
H_PM_SYNC15
UNCOREPWRGOOD:
12
R226
R226 75_0402_5%
75_0402_5%
R227
R227
43_0402_1%
43_0402_1%
1 2
+1.05VS_VTT
R220 62_0402_5%R220 62_0402_5%
BUF_CPU_RST#
SAGE 3G
@
H_CATERR#
T1 PAD@T1 PAD
H_PECI
R216
R216
56_0402_5%
56_0402_5%
1 2
H_PROCHOT#_RH_PROCHOT#
R80 0_0402_5%
R80 0_0402_5%
1 2
H_CPUPWRGD_R
@
@
CPU_CORE
PM_DRAM_PWR GD_R
SM_DRAMPWROK:DRAM power ok
BUF_CPU_RST#
UCPU1B
UCPU1B
F49
PROC_SELECT#
C57
PROC_DETECT#
C49
CATERR#
A48
PECI
C45
PROCHOT#
D45
THERMTRIP#
C48
PM_SYNC
B46
UNCOREPWRGOOD
OK
BE45
SM_DRAMPWR OK
D44
RESET#
IVY-BRIDGE_BGA1023
IVY-BRIDGE_BGA1023
IVB@
IVB@
J3
BCLK
MISC THERMAL PWR MANAGEMENT
MISC THERMAL PWR MANAGEMENT
DPLL_REF_CLK
DPLL_REF_CLK#
CLOCKS
CLOCKS
SM_DRAMRST#
SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]
DDR3
MISC
DDR3
MISC
JTAG & BPM
JTAG & BPM
BCLK#
PRDY#
PREQ#
TCK TMS
TRST#
TDO
DBR#
BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]
H2
AG3
CLK_CPU_DPLL
AG1
CLK_CPU_DPLL#
AT30
SM_DRAMRST#
BF44
SM_RCOMP0
BE43
SM_RCOMP1
BG43
SM_RCOMP2
DDR3 Compensation Signals Trace:10mil ,Spacing:13mil, Max.Length:500mil
N53 N55
L56
XDP_TCK
L55
XDP_TMS
J58
XDP_TRST#
M60
XDP_TDI
TDI
L59
XDP_TDO
K58
XDP_DBRESET#
G58 E55 E59 G55 G59 H60 J59 J61
CLK_CPU_DMI 14 CLK_CPU_DMI# 14
CLK_CPU_DPLL 14 CLK_CPU_DPLL# 1 4
SM_DRAMRST# 6H_PECI28
R149 140_0402_1%R149 140_0402_1% R486 25.5_0402_1%R486 25.5_0402_1% R484 200_0402_1%R484 200_0402_1%
12 12 12
T2PAD@ T2PAD@ T3PAD@ T3PAD@ T4PAD@ T4PAD@
T5PAD@ T5PAD@ T6PAD@ T6PAD@
1 2
C102 100P_0402_50V8J
100P_0402_50V8J
XDP_DBRESET# 15
XEMC@C102
XEMC@
For EMI
SAGE 3G
+1.05VS_VTT
CLK_CPU_DPLL#
CLK_CPU_DPLL
Checklist1.0 P.64 Processor Graphis Disable Guide DIS only SKU or UMA eDP disable DPLL_REF_SSCLK PD 1K_5% to GND DPLL_REF_SSCLK# PH 1K_5% to +1.05VS_VTT
XDP_DBRESET#
CRB1.0 PH 1K +3VS Check list 1.0 PH 5K +3VS Check list 1.2 PH 10K +3VS Debug port DG1.1-1.2 50~5K ohm
R116 1K_0402_5%@R 116 1K_0402_5%@
R117 1K_0402_5%@R 117 1K_0402_5%@
R569 1K_0402_5%R569 1K_0402_5%
12
12
+3VS
12
3 3
Follow DG 1.2 & CRB1.0
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 2
VR_ON28,42
SYS_PWROK15
R82 0_0402_5%@R82 0_0402_5%@
R81 0_0402_5%@R81 0_0402_5%@
PM_DRAM_PWR GD15
1 2
C101
C101
+3VALW
1
2
5
U5
U5
2
P
B
Y
1
A
G
MC74VHC1G09DFT2G_SC70-5
MC74VHC1G09DFT2G_SC70-5
3
+1.35VS
12
R88
R88 200_0402_5%
200_0402_5%
4
PM_SYS_PWRGD_BUF PM_DRAM_ PWRGD_R
Use open drain MOS: +1.35VS PH pop 200ohm series resister pop 130ohm
1 2
R97 130_0402_5%R97 130_04 02_5%
SAGE 3G
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
B
C
2011/06/24 2012/06/02
2011/06/24 2012/06/02
2011/06/24 2012/06/02
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(2/7) PM,XDP,CLK
PROCESSOR(2/7) PM,XDP,CLK
PROCESSOR(2/7) PM,XDP,CLK
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
E
5 52Wednesday, March 13, 2013
5 52Wednesday, March 13, 2013
5 52Wednesday, March 13, 2013
0.1
0.1
0.1
A
UCPU1C
DDR_A_D[0..63]11
1 1
2 2
3 3
DDR_A_BS011 DDR_A_BS111 DDR_A_BS211
DDR_A_CAS#11 DDR_A_RAS#11 DDR_A_WE#11
DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
UCPU1C
AG6
SA_DQ[0]
AJ6
SA_DQ[1]
AP11
SA_DQ[2]
AL6
SA_DQ[3]
AJ10
SA_DQ[4]
AJ8
SA_DQ[5]
AL8
SA_DQ[6]
AL7
SA_DQ[7]
AR11
SA_DQ[8]
AP6
SA_DQ[9]
AU6
SA_DQ[10]
AV9
SA_DQ[11]
AR6
SA_DQ[12]
AP8
SA_DQ[13]
AT13
SA_DQ[14]
AU13
SA_DQ[15]
BC7
SA_DQ[16]
BB7
SA_DQ[17]
BA13
SA_DQ[18]
BB11
SA_DQ[19]
BA7
SA_DQ[20]
BA9
SA_DQ[21]
BB9
SA_DQ[22]
AY13
SA_DQ[23]
AV14
SA_DQ[24]
AR14
SA_DQ[25]
AY17
SA_DQ[26]
AR19
SA_DQ[27]
BA14
SA_DQ[28]
AU14
SA_DQ[29]
BB14
SA_DQ[30]
BB17
SA_DQ[31]
BA45
SA_DQ[32]
AR43
SA_DQ[33]
AW48
SA_DQ[34]
BC48
SA_DQ[35]
BC45
SA_DQ[36]
AR45
SA_DQ[37]
AT48
SA_DQ[38]
AY48
SA_DQ[39]
BA49
SA_DQ[40]
AV49
SA_DQ[41]
BB51
SA_DQ[42]
AY53
SA_DQ[43]
BB49
SA_DQ[44]
AU49
SA_DQ[45]
BA53
SA_DQ[46]
BB55
SA_DQ[47]
BA55
SA_DQ[48]
AV56
SA_DQ[49]
AP50
SA_DQ[50]
AP53
SA_DQ[51]
AV54
SA_DQ[52]
AT54
SA_DQ[53]
AP56
SA_DQ[54]
AP52
SA_DQ[55]
AN57
SA_DQ[56]
AN53
SA_DQ[57]
AG56
SA_DQ[58]
AG53
SA_DQ[59]
AN55
SA_DQ[60]
AN52
SA_DQ[61]
AG55
SA_DQ[62]
AK56
SA_DQ[63]
BD37
SA_BS[0]
BF36
SA_BS[1]
BA28
SA_BS[2]
BE39
SA_CAS#
BD39
SA_RAS#
AT41
SA_WE#
IVY-BRIDGE_BGA1023
IVY-BRIDGE_BGA1023
IVB@
IVB@
Follow CRB1.0
CPUDIMMreset
SM_DRAMRST#5
4.99K_0402_1%
4.99K_0402_1%
4 4
DRAMRST_CNTRL_PC H14
DRAMRST_CNTRL_EC28
A
1 2
R413 0_0402_5%DS3@R413 0_0402_5%DS3@
SAGE 3G DVT
R79
R79
1 2
C78
C78
.047U_0402_16V7K
.047U_0402_16V7K
S
S
G
G
2
1
2
D
D
13
DIMM_DRAMRST#_RSM_DRAMRST#
Q6
Q6 BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
SAGE 3G
B
AU36
SA_CK[0]
AV36
SA_CK#[0]
AY26
SA_CKE[0]
AT40
SA_CK[1]
AU40
SA_CK#[1]
BB26
SA_CKE[1]
BB40
SA_CS#[0]
BC41
SA_CS#[1]
AY40
SA_ODT[0]
BA41
SA_ODT[1]
AL11
SA_DQS#[0]
AR8
SA_DQS#[1]
AV11
SA_DQS#[2]
AT17
SA_DQS#[3]
AV45
SA_DQS#[4]
AY51
SA_DQS#[5]
AT55
SA_DQS#[6]
AK55
SA_DQS#[7]
AJ11
SA_DQS[0]
AR10
SA_DQS[1]
AY11
SA_DQS[2]
AU17
SA_DQS[3]
AW45
SA_DQS[4]
AV51
SA_DQS[5]
AT56
SA_DQS[6]
AK54
SA_DQS[7]
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
BG35
SA_MA[0]
BB34
SA_MA[1]
BE35
SA_MA[2]
BD35
SA_MA[3]
AT34
SA_MA[4]
AU34
SA_MA[5]
BB32
SA_MA[6]
AT32
SA_MA[7]
AY32
SA_MA[8]
AV32
SA_MA[9]
BE37
SA_MA[10]
BA30
SA_MA[11]
BC30
SA_MA[12]
AW41
SA_MA[13]
AY28
SA_MA[14]
AU26
SA_MA[15]
+1.35V
12
R66
R66
1K_0402_5%
1K_0402_5%
R63
R63 1K_0402_5%
1K_0402_5%
1 2
S0 DRAMRST_CNTRL_PCH hgih ,MOS ON SM_DRAMRST# HIGH,DDR3 DRAMRST# HIGH Dimm not reset S3 DRAMRST_CNTRL_PCH Low ,MOS OFF SM_DRAMRST# Low,DDR3 DRAMRST# HIGH Dimm not reset S4,S5 DRAMRST_CNTRL_PCH Low ,MOS OFF SM_DRAMRST# Low,DDR3 DRAMRST# Low Dimm reset
B
DDR_A_CLK1 DDR_A_CLK1#
DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7
DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15
DIMM_DRAMRST# 11,12
DDR_A_CKE1 11
C
UCPU1D
DDR_B_D[0..63]12
DDR_A_CLK0 11 DDR_A_CLK0# 11 DDR_A_CKE0 11
12
R263
R263 75_0402_1%
75_0402_1%
DDR_A_CS0# 11 DDR_A_CS1# 11
SAGE 3G PVT SAGE 3G PVT
DDR_A_ODT0 11 DDR_A_ODT1 11
DDR_A_DQS#[0..7] 11
DDR_A_DQS[0..7] 11
DDR_A_MA[0..15] 11
DDR_B_BS012 DDR_B_BS112 DDR_B_BS212
DDR_B_CAS#12 DDR_B_RAS#12 DDR_B_WE#12
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
2011/06/24 2012/06/02
2011/06/24 2012/06/02
2011/06/24 2012/06/02
UCPU1D
AL4
SB_DQ[0]
AL1
SB_DQ[1]
AN3
SB_DQ[2]
AR4
SB_DQ[3]
AK4
SB_DQ[4]
AK3
SB_DQ[5]
AN4
SB_DQ[6]
AR1
SB_DQ[7]
AU4
SB_DQ[8]
AT2
SB_DQ[9]
AV4
SB_DQ[10]
BA4
SB_DQ[11]
AU3
SB_DQ[12]
AR3
SB_DQ[13]
AY2
SB_DQ[14]
BA3
SB_DQ[15]
BE9
SB_DQ[16]
BD9
SB_DQ[17]
BD13
SB_DQ[18]
BF12
SB_DQ[19]
BF8
SB_DQ[20]
BD10
SB_DQ[21]
BD14
SB_DQ[22]
BE13
SB_DQ[23]
BF16
SB_DQ[24]
BE17
SB_DQ[25]
BE18
SB_DQ[26]
BE21
SB_DQ[27]
BE14
SB_DQ[28]
BG14
SB_DQ[29]
BG18
SB_DQ[30]
BF19
SB_DQ[31]
BD50
SB_DQ[32]
BF48
SB_DQ[33]
BD53
SB_DQ[34]
BF52
SB_DQ[35]
BD49
SB_DQ[36]
BE49
SB_DQ[37]
BD54
SB_DQ[38]
BE53
SB_DQ[39]
BF56
SB_DQ[40]
BE57
SB_DQ[41]
BC59
SB_DQ[42]
AY60
SB_DQ[43]
BE54
SB_DQ[44]
BG54
SB_DQ[45]
BA58
SB_DQ[46]
AW59
SB_DQ[47]
AW58
SB_DQ[48]
AU58
SB_DQ[49]
AN61
SB_DQ[50]
AN59
SB_DQ[51]
AU59
SB_DQ[52]
AU61
SB_DQ[53]
AN58
SB_DQ[54]
AR58
SB_DQ[55]
AK58
SB_DQ[56]
AL58
SB_DQ[57]
AG58
SB_DQ[58]
AG59
SB_DQ[59]
AM60
SB_DQ[60]
AL59
SB_DQ[61]
AF61
SB_DQ[62]
AH60
SB_DQ[63]
BG39
SB_BS[0]
BD42
SB_BS[1]
AT22
SB_BS[2]
AV43
SB_CAS#
BF40
SB_RAS#
BD45
SB_WE#
IVY-BRIDGE_BGA1023
IVY-BRIDGE_BGA1023
IVB@
IVB@
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
BA34
SB_CK[0]
AY34
SB_CK#[0]
AR22
SB_CKE[0]
BA36
SB_CK[1] SB_CK#[1] SB_CKE[1]
SB_CS#[0] SB_CS#[1]
SB_ODT[0] SB_ODT[1]
SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]
SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]
D
DDR_B_CLK1
BB36
DDR_B_CLK1#
BF27
BE41 BE47
AT43 BG47
AL3
DDR_B_DQS#0
AV3
DDR_B_DQS#1
BG11
DDR_B_DQS#2
BD17
DDR_B_DQS#3
BG51
DDR_B_DQS#4
BA59
DDR_B_DQS#5
AT60
DDR_B_DQS#6
AK59
DDR_B_DQS#7
AM2
DDR_B_DQS0
AV1
DDR_B_DQS1
BE11
DDR_B_DQS2
BD18
DDR_B_DQS3
BE51
DDR_B_DQS4
BA61
DDR_B_DQS5
AR59
DDR_B_DQS6
AK61
DDR_B_DQS7
BF32
DDR_B_MA0
BE33
DDR_B_MA1
BD33
DDR_B_MA2
AU30
DDR_B_MA3
BD30
DDR_B_MA4
AV30
DDR_B_MA5
BG30
DDR_B_MA6
BD29
DDR_B_MA7
BE30
DDR_B_MA8
BE28
DDR_B_MA9
BD43
DDR_B_MA10
AT28
DDR_B_MA11
AV28
DDR_B_MA12
BD46
DDR_B_MA13
AT26
DDR_B_MA14
AU22
DDR_B_MA15
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
DDR_B_CKE1 12
Address 0~13:For 128*16 Address 0~14:For 256*16 Address 0~15:For 512*16
Title
Title
Title
PROCESSOR(3/7) DDRIII
PROCESSOR(3/7) DDRIII
PROCESSOR(3/7) DDRIII
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
DDR_B_CLK0 12 DDR_B_CLK0# 12 DDR_B_CKE0 12
DDR_B_CS0# 12 DDR_B_CS1# 12
DDR_B_ODT0 12 DDR_B_ODT1 12
DDR_B_DQS#[0..7] 12
DDR_B_DQS[0..7] 12
DDR_B_MA[0..15] 12
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
E
12
E
R264
R264 75_0402_1%
75_0402_1%
0.1
0.1
6 52Wednesday, March 13, 2013
6 52Wednesday, March 13, 2013
6 52Wednesday, March 13, 2013
0.1
A
B
C
D
E
Default "1",EDS R1.0 P.88
CFG Straps for Processor
UCPU1E
UCPU1E
T72 PAD @T72 PA D@
1 1
2 2
3 3
+CPU_CO RE
1 2
1 2
+VGFX_C ORE
1 2
1 2
R810
R810
@
@
49.9_040 2_1%
49.9_040 2_1%
R812
R812
@
@
49.9_040 2_1%
49.9_040 2_1%
R811
R811
@
@
49.9_040 2_1%
49.9_040 2_1%
R813
R813
@
@
49.9_040 2_1%
49.9_040 2_1%
VCC_VAL _SENSE
VSS_VAL _SENSE
VAXG_VA L_SENSE
VSSAXG_ VAL_SENSE
CFG0
CFG2
CFG4 CFG5 CFG6 CFG7
VCC_VAL _SENSE VSS_VAL _SENSE
VAXG_VA L_SENSE VSSAXG_ VAL_SENSE
T56 PAD @T56 PA D@
B50
CFG[0]
C51
CFG[1]
B54
CFG[2]
D53
CFG[3]
A51
CFG[4]
C53
CFG[5]
C55
CFG[6]
H49
CFG[7]
A55
CFG[8]
H51
CFG[9]
K49
CFG[10]
K53
CFG[11]
F53
CFG[12]
G53
CFG[13]
L51
CFG[14]
F51
CFG[15]
D52
CFG[16]
L53
CFG[17]
H43
VCC_VAL_SENSE
K43
VSS_VAL_SENSE
H45
VAXG_VAL_SENSE
K45
VSSAXG_VAL_SENSE
F48
VCC_DIE_SENSE
H48
RSVD6
K48
RSVD7
BA19
RSVD8
AV19
RSVD9
AT21
RSVD10
BB21
RSVD11
BB19
RSVD12
AY21
RSVD13
BA22
RSVD14
AY22
RSVD15
AU19
RSVD16
AU21
RSVD17
BD21
RSVD18
BD22
RSVD19
BD25
RSVD20
BD26
RSVD21
BG22
RSVD22
BE22
RSVD23
BG26
RSVD24
BE26
RSVD25
BF23
RSVD26
BE24
RSVD27
IVY-BRIDGE_BGA1 023
IVY-BRIDGE_BGA1 023
IVB@
IVB@
RESERVED
RESERVED
BCLK_ITP#
DC_TEST_A4 DC_TEST_C4 DC_TEST_D3
DC_TEST_D1 DC_TEST_A58 DC_TEST_A59
DC_TEST_C59
DC_TEST_A61
DC_TEST_C61 DC_TEST_D61
DC_TEST_BD61
DC_TEST_BE61
DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58
DC_TEST_BG4 DC_TEST_BG3 DC_TEST_BE3 DC_TEST_BG1 DC_TEST_BE1 DC_TEST_BD1
BCLK_ITP
RSVD30 RSVD31 RSVD32 RSVD33
RSVD34 RSVD35 RSVD36 RSVD37 RSVD38
RSVD39 RSVD40
RSVD41 RSVD42 RSVD43 RSVD44
RSVD45
N59 N58
N42 L42 L45 L47
M13 M14 U14 W14 P13
AT49 K24
AH2 AG13 AM14 AM15
N50
A4 C4 D3
DC_TEST _C4_D3
D1 A58 A59 C59
DC_TEST _A59_C59
A61 C61
DC_TEST _A61_C61
D61 BD61 BE61 BE59
DC_TEST _BE59_BE61
BG61 BG59
DC_TEST _BG59_BG61
BG58 BG4 BG3 BE3
DC_TEST _BE3_BG3
BG1 BE1
DC_TEST _BE1_BG1
BD1
These pins are for solder joint reliability and non-critical to function. For BGA only.
CLK_RES _ITP 14 CLK_RES _ITP# 14
PEG Static Lane Reversal - CFG2 is for the 16x
1: Normal Operation; Lane # definition matches
CFG2
socket pin map definition
0:Lane Reversed
*
CFG2
12
R234
R234 1K_0402 _1%
1K_0402 _1%
eDP enable
CFG4
1:Disable
*
0:Enable
CFG4
12
eDP@
eDP@
R204
R204 1K_0402 _1%
1K_0402 _1%
PCIE Port Bifurcation Straps
11: (Default) 1x16 PCI Express
*
CFG[6:5]
10: 2x8 PCI Express
01: Reserved
00: 1x8,2x4 PCI Express
CFG6
CFG5
12
12
R230
R230
1K_0402 _1% @
1K_0402 _1% @
R228
R228
1K_0402 _1%@
1K_0402 _1%@
PEG DEFER TRAINING
CFG7
1: (Default) PEG Train immediately following xxRESETB de assertion
CRB1.0 P.12
0: PEG Wait for BIOS for training
CFG7
4 4
Security Class ification
Security Class ification
Security Class ification
2011/06/ 24 2012/06/ 02
2011/06/ 24 2012/06/ 02
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2011/06/ 24 2012/06/ 02
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
12
R224
R224 1K_0402 _1%@
1K_0402 _1%@
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(4/7) RSVD,CFG
PROCESSOR(4/7) RSVD,CFG
PROCESSOR(4/7) RSVD,CFG
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
7 52Wednesd ay, March 13, 20 13
7 52Wednesd ay, March 13, 20 13
7 52Wednesd ay, March 13, 20 13
E
0.1
0.1
0.1
A
INTEL Recommend VCC 3*330uF,12*22uF(0805),16*2.2uF(0402) PD0.9
1 1
2 2
3 3
4 4
B
UCPU1F
ULV SC/DC 33A
+CPU_CORE
UCPU1F
A26
VCC[1]
A29
VCC[2]
A31
VCC[3]
A34
VCC[4]
A35
VCC[5]
A38
VCC[6]
A39
VCC[7]
A42
VCC[8]
C26
VCC[9]
C27
VCC[10]
C32
VCC[11]
C34
VCC[12]
C37
VCC[13]
C39
VCC[14]
C42
VCC[15]
D27
VCC[16]
D32
VCC[17]
D34
VCC[18]
D37
VCC[19]
D39
VCC[20]
D42
VCC[21]
E26
VCC[22]
E28
VCC[23]
E32
VCC[24]
E34
VCC[25]
E37
VCC[26]
E38
VCC[27]
F25
VCC[28]
F26
VCC[29]
F28
VCC[30]
F32
VCC[31]
F34
VCC[32]
F37
VCC[33]
F38
VCC[34]
F42
VCC[35]
G42
VCC[36]
H25
VCC[37]
H26
VCC[38]
H28
VCC[39]
H29
VCC[40]
H32
VCC[41]
H34
VCC[42]
H35
VCC[43]
H37
VCC[44]
H38
VCC[45]
H40
VCC[46]
J25
VCC[47]
J26
VCC[48]
J28
VCC[49]
J29
VCC[50]
J32
VCC[51]
J34
VCC[52]
J35
VCC[53]
J37
VCC[54]
J38
VCC[55]
J40
VCC[56]
J42
VCC[57]
K26
VCC[58]
K27
VCC[59]
K29
VCC[60]
K32
VCC[61]
K34
VCC[62]
K35
VCC[63]
K37
VCC[64]
K39
VCC[66]
K42
VCC[67]
L25
VCC[68]
L28
VCC[69]
L33
VCC[70]
L36
VCC[71]
L40
VCC[72]
N26
VCC[73]
N30
VCC[74]
N34
VCC[75]
N38
VCC[76]
IVY-BRIDGE_BGA1023
IVY-BRIDGE_BGA1023
IVB@
IVB@
C
POWER
POWER
CORE SUPPLY
CORE SUPPLY
VCCIO[1] VCCIO[3] VCCIO[4] VCCIO[5] VCCIO[6] VCCIO[7] VCCIO[8]
VCCIO[9] VCCIO[10] VCCIO[11] VCCIO[12] VCCIO[13] VCCIO[14] VCCIO[15] VCCIO[16] VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20] VCCIO[21] VCCIO[22] VCCIO[23] VCCIO[24] VCCIO[25] VCCIO[26] VCCIO[27] VCCIO[28] VCCIO[29]
VCCIO[30] VCCIO[31] VCCIO[32]
PEG IO AND DDR IO
PEG IO AND DDR IO
VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49]
VCCIO50
VCCIO51
VCCIO_SEL
VCCPQE[1] VCCPQE[2]
RAILS
RAILS
VIDALERT#
VIDSCLK
VIDSOUT
VCC_SENSE VSS_SENSE
VCCIO_SENSE
VSS_SENSE_VCCIO
SENSE LINES SVID QUIET
SENSE LINES SVID QUIET
8.5A
AF46 AG48 AG50 AG51 AJ17 AJ21 AJ25 AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48
AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15
W16 W17
BC22
AM25 AN22
A44 B43 C44
F43 G43
AN16 AN17
VCCSENSE_R VSSSENSE_R
VCCIO_SEL_R
+1.05VS_VTT
1
C951
C951 1U_0402_6.3V6K
1U_0402_6.3V6K
2
H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT
VCCIO_SENSE VSSIO_SENSE
D
+1.05VS_VTT
INTEL Recommend VCCIO PD 0.9
330uF 1+1 10uF (0603) *5 1uF (0201) *16
+1.05VS_VTT
330uF 1 10uF (0603) *5 1uF (0201) *10
10K_0402_5%
10K_0402_5%
+1.05VS_VTT
R582
R582
1 2
+1.05VS_VTT
SAGE 3G
Place the PU,PD resistors close to CPU
1 2
R579 0_0402_5%@R579 0_0402_5%@ R581 0_0402_5%@R581 0_0402_5%@
1 2
1 2
R107 10_0402_5%R107 10_0402_5%
12
R105
R105 10_0402_5%
10_0402_5%
VCCIO_SEL
10K_0402_5% @
10K_0402_5% @
0_0402_5%@
0_0402_5%@
12
R574
R574 130_0402_5%
130_0402_5%
+1.05VS_VTT
VCCIO_SENSE 40
Should change to connect from power cirucit & layout differential with VCCIO_SENSE.
+3VALW
VCCIO_SEL For 2012 CPU support
R521
R521
R520
R520
1 2
R576 43_0402_1%R576 43_0402_1% R577 0_0402_5%@R577 0_0402_5%@
1 2 1 2
R578 0_0402_5%@R578 0_0402_5%@
+CPU_CORE
1 2
12
12
12
A19
R588
R588 100_0402_1%
100_0402_1%
R589
R589 100_0402_1%
100_0402_1%
E
1 : +1.05VS_VTT
*
0: +1.0VS_VTT
Check List R1.5 VIDALERT#:75ohm ±5% pull-up to VCCIO close to IMVP7 VIDSCLK: 55ohm ±5% pull-up to VCCIO close to IMVP7 VIDSOUT: 130ohm ±5% pull-up to VCCIO close to CPU 130ohm ±5% pull-up to VCCIO close to IMVP7
VR_SVID_ALRT# 42 VR_SVID_CLK 42 VR_SVID_DAT 42
VCCSENSE 42 VSSSENSE 42
Check List R1.5 VCCSENSE:100ohm ±1% pull-up to VCC near processor. VSSSENSE:100ohm ±1% pull-down to GND near processor.
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2011/06/24 2012/06/02
2011/06/24 2012/06/02
2011/06/24 2012/06/02
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(5/7) PWR,BYPASS
PROCESSOR(5/7) PWR,BYPASS
PROCESSOR(5/7) PWR,BYPASS
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
E
8 52Wednesday, March 13, 2013
8 52Wednesday, March 13, 2013
8 52Wednesday, March 13, 2013
0.1
0.1
0.1
A
INTEL Recommend VAXG
+VGFX_CORE
2*330uF,5*22uF(0805),6*10uF(0603),6*1uF(0402) PD 0.9
1 1
2 2
Check List R1.5 VCCAXG_SENSE:100ohm ±5% pull-up to VCC near processor. VSSAXG_SENSE:100ohm ±5% pull-down to GND near processor.
INTEL Recommend VCCPLL 1*330uF,2*1uF(0402) PD 0.9
3 3
SAGE 3G
+1.8VS
+1.35VS
+VCCSA
J16
112
JUMP_43X39
JUMP_43X39
R500
R500 0_0805_5%
0_0805_5%
1 2
@
@
@J16
@
2
1
+
+
C607
C607 330U_B2_2VM_R15M
330U_B2_2VM_R15M
SGA00004700
SGA00004700
2
1
+
+
C606
C606 220U_B2_2.5VM_R15M
220U_B2_2.5VM_R15M
SGA00004I00
SGA00004I00
2
VCC_AXG_SENSE42
VSS_AXG_SENSE42
+VCCSA
+1.8VS_VCCPLL
SAGE 3G
C1181
C1181
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
B
ULV SC/DC GT1: 18A GT2: 33A
R381
1 2
100_0402_5%
100_0402_5%
1 2
100_0402_5%
100_0402_5%
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
R381
R396
R396
1.2A
C584
1U_0402_6.3V6K
C584
1U_0402_6.3V6K
C583
C583
1
2
+VGFX_CORE
6A
C1179
C1179
C1180
C1180
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
2
2
UCPU1G
UCPU1G
AA46
VAXG[1]
AB47
VAXG[2]
AB50
VAXG[3]
AB51
VAXG[4]
AB52
VAXG[5]
AB53
VAXG[6]
AB55
VAXG[7]
AB56
VAXG[8]
AB58
VAXG[9]
AB59
VAXG[10]
AC61
VAXG[11]
AD47
VAXG[12]
AD48
VAXG[13]
AD50
VAXG[14]
AD51
VAXG[15]
AD52
VAXG[16]
AD53
VAXG[17]
AD55
VAXG[18]
AD56
VAXG[19]
AD58
VAXG[20]
AD59
VAXG[21]
AE46
VAXG[22]
N45
VAXG[23]
P47
VAXG[24]
P48
VAXG[25]
P50
VAXG[26]
P51
VAXG[27]
P52
VAXG[28]
P53
VAXG[29]
P55
VAXG[30]
P56
VAXG[31]
P61
VAXG[32]
T48
VAXG[33]
T58
VAXG[34]
T59
VAXG[35]
T61
VAXG[36]
U46
VAXG[37]
V47
VAXG[38]
V48
VAXG[39]
V50
VAXG[40]
V51
VAXG[41]
V52
VAXG[42]
V53
VAXG[43]
V55
VAXG[44]
V56
VAXG[45]
V58
VAXG[46]
V59
VAXG[47]
W50
VAXG[48]
W51
VAXG[49]
W52
VAXG[50]
W53
VAXG[51]
W55
VAXG[52]
W56
VAXG[53]
W61
VAXG[54]
Y48
VAXG[55]
Y61
VAXG[56]
F45
VAXG_SENSE
G45
VSSAXG_SENSE
BB3
VCCPLL[1]
BC1
VCCPLL[2]
BC4
VCCPLL[3]
L17
VCCSA[1]
L21
VCCSA[2]
N16
VCCSA[3]
N20
VCCSA[4]
N22
VCCSA[5]
P17
VCCSA[6]
P20
VCCSA[7]
R16
VCCSA[8]
R18
VCCSA[9]
R21
VCCSA[10]
U15
VCCSA[11]
V16
VCCSA[12]
V17
VCCSA[13]
V18
VCCSA[14]
V21
VCCSA[15]
W20
VCCSA[16]
IVY-BRIDGE_BGA1023
IVY-BRIDGE_BGA1023
IVB@
IVB@
POWER
POWER
VREF
VREF
DDR3 - 1.5V RAILS
DDR3 - 1.5V RAILS
GRAPHICS
GRAPHICS
SENSE
LINES
SENSE
LINES
1.8V RAIL
1.8V RAIL
SA RAIL
SA RAIL
VCCSA VID
VCCSA VID
C
SM_VREF
SA_DIMM_VREFDQ SB_DIMM_VREFDQ
VDDQ[10] VDDQ[11] VDDQ[12] VDDQ[13] VDDQ[14] VDDQ[15] VDDQ[16] VDDQ[17] VDDQ[18] VDDQ[19] VDDQ[20] VDDQ[21] VDDQ[22] VDDQ[23] VDDQ[24] VDDQ[25] VDDQ[26]
VCCDQ[1] VCCDQ[2]
QUIET RAILS
QUIET RAILS
VDDQ_SENSE
VSS_SENSE_VDDQ
VCCSA_SENSE
SENSE LINES
SENSE LINES
VCCSA_VID[0] VCCSA_VID[1]
lines
lines
SA_DIMM_VREFDQ SB_DIMM_VREFDQ For Future CPU M3 support, Sandey bridge not support M3, Check list1.0 & CRB say can NC
AY43
+V_SM_VREF
BE7
SA_DIMM_VREFDQ
BG7
SB_DIMM_VREFDQ
5A
AJ28
VDDQ[1]
AJ33
VDDQ[2]
AJ36
VDDQ[3]
AJ40
VDDQ[4]
AL30
VDDQ[5]
AL34
VDDQ[6]
AL38
VDDQ[7]
AL42
VDDQ[8]
AM33
VDDQ[9]
AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33
AM28 AN26
BC43 BA43
U10
D48 D49
+1.35VS
VCCSA_SENSE
CPU EDS1.3 P.93 VCCSA_VID0 Must PD
H_VCCSA_VID0 H_VCCSA_VID1
12
12
@
@
R69
R69
1K_0402_1%
1K_0402_1%
Place BOT OUT Conn
C985
1U_0402_6.3V6K
C985
1U_0402_6.3V6K
1
SAGE 3G
2
12
R129
R129 0_0402_5%
0_0402_5%
@
@
@
@
R68
R68
1K_0402_1%
1K_0402_1%
C977
C977
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
D
SAGE 3G
C978
C978
C979
C979
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
2
2
C998
C998
C999
C999
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
12
12
@
@
SAGE 3G
@
@
T55
T55
H_VCCSA_VID0 41 H_VCCSA_VID1 41
+1.35VS
+V_SM_VREF should have 20 mil trace width
1
C647
C647
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
INTEL Recommend VDDQ 1*330uF,8*10uF(0603) ,10*1uF(0402) PD0.9
Short for +1.35VS to +1.35V_CPU_VDDQ
1
+
+
C599
C599 330U_B2_2VM_R15M
330U_B2_2VM_R15M
SGA00004700
SGA00004700
2
10U_0603_6.3V6M
10U_0603_6.3V6M
VCCSA
SNB IVB
Vout
0.9V
0.8V
0.85V V
0.725V
0.675V
12
PAD
PAD
SAGE 3G
C990
C990
10U_0603_6.3V6M
10U_0603_6.3V6M
12
@
@
C970
C970
C987
C987
C989
C989
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
12
12
@
@
VCCSA_VID
For 2012 future CPU VCCSA voltage select
VID0
VID1
0
0
1
0
0 X1
1 1
12
R534
R534
1K_0402_1%
1K_0402_1%
12
R540
R540
1K_0402_1%
1K_0402_1%
V V
V
E
+1.35VS
ULV
V
V
V
V
VX
V
INTEL Recommend VCCSA
4 4
1*330uF,5*10uF(0603) ,5*1uF(0402)
C995
C995
10U_0603_6.3V6M
10U_0603_6.3V6M
12
C997
C997
C996
C996
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
12
12
PD0.9
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2011/06/24 2012/06/02
2011/06/24 2012/06/02
2011/06/24 2012/06/02
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(6/7) PWR
PROCESSOR(6/7) PWR
PROCESSOR(6/7) PWR
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
E
9 52Wednesday, March 13, 2013
9 52Wednesday, March 13, 2013
9 52Wednesday, March 13, 2013
0.1
0.1
0.1
A
1 1
2 2
3 3
B
UCPU1H
UCPU1H
A13
AA13 AA50 AA51 AA52 AA53 AA55 AA56
AB16 AB18 AB21 AB48 AB61 AC10 AC14 AC46
AC6 AD17 AD20
AD4 AD61 AE13
AE8
AF1
AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58
AF59 AG10 AG14 AG18 AG47 AG52 AG61
AG7 AH4
AH58
AJ13
AJ16
AJ20
AJ22
AJ26
AJ30
AJ34
AJ38
AJ42
AJ45
AJ48
AK1
AK52
AL10
AL13
AL17
AL21
AL25
AL28
AL33
AL36
AL40
AL43
AL47
AL61 AM13 AM20 AM22 AM26 AM30 AM34
VSS[1]
A17
VSS[2]
A21
VSS[3]
A25
VSS[4]
A28
VSS[5]
A33
VSS[6]
A37
VSS[7]
A40
VSS[8]
A45
VSS[9]
A49
VSS[10]
A53
VSS[11]
A9
VSS[12]
AA1
VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20]
AA8
VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69]
AJ7
VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90]
VSS
VSS
VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]
VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180]
AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13
C
UCPU1I
UCPU1I
BG17
VSS[181]
BG21
VSS[182]
BG24
VSS[183]
BG28
VSS[184]
BG37
VSS[185]
BG41
VSS[186]
BG45
VSS[187]
BG49
VSS[188]
BG53
VSS[189]
BG9
VSS[190]
C29
VSS[191]
C35
VSS[192]
C40
VSS[193]
D10
VSS[194]
D14
VSS[195]
D18
VSS[196]
D22
VSS[197]
D26
VSS[198]
D29
VSS[199]
D35
VSS[200]
D4
VSS[201]
D40
VSS[202]
D43
VSS[203]
D46 D50 D54 D58
E25 E29
E35 E40 F13 F15 F19 F29 F35 F40 F55 G51
G61 H10 H14 H17 H21
H53 H58
K11 K21 K51
M11 M15
VSS[204] VSS[205] VSS[206] VSS[207]
D6
VSS[208] VSS[209] VSS[210]
E3
VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221]
G6
VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227]
H4
VSS[228] VSS[229] VSS[230]
J1
VSS[231]
J49
VSS[232]
J55
VSS[233] VSS[234] VSS[235] VSS[236]
K8
VSS[237]
L16
VSS[238]
L20
VSS[239]
L22
VSS[240]
L26
VSS[241]
L30
VSS[242]
L34
VSS[243]
L38
VSS[244]
L43
VSS[245]
L48
VSS[246]
L61
VSS[247] VSS[248] VSS[249]
VSS
VSS
NCTF
NCTF
VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301]
VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8
VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14
D
M4 M58 M6 N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61 P14 P16 P18 P21 P58 P59 P9 R17 R20 R4 R46 T1 T47 T50 T51 T52 T53 T55 T56 U13 U8 V20 V61 W13 W15 W18 W21 W46 W8 Y4 Y47 Y58 Y59 G48
A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61
T58PAD@ T58PAD@ T59PAD@ T59PAD@ T60PAD@ T60PAD@ T61PAD@ T61PAD@ T62PAD@ T62PAD@ T63PAD@ T63PAD@ T64PAD@ T64PAD@ T65PAD@ T65PAD@ T66PAD@ T66PAD@ T67PAD@ T67PAD@ T68PAD@ T68PAD@ T69PAD@ T69PAD@ T70PAD@ T70PAD@ T71PAD@ T71PAD@
E
CR CheckList Rev1.5
IVY-BRIDGE_BGA1023
IVY-BRIDGE_BGA1023
IVB@
IVB@
IVY-BRIDGE_BGA1023
4 4
A
B
IVY-BRIDGE_BGA1023
IVB@
IVB@
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2011/06/24 2012/06/02
2011/06/24 2012/06/02
2011/06/24 2012/06/02
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Compal Electronics, Inc.
PROCESSOR(7/7) VSS
PROCESSOR(7/7) VSS
PROCESSOR(7/7) VSS
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
E
10 52Wednesday, March 13, 2013
10 52Wednesday, March 13, 2013
10 52Wednesday, March 13, 2013
0.1
0.1
0.1
A
B
C
D
E
Channel A
DDR_A_MA[0..15]6
DDR_A_DQS#[0..7]6
DDR_A_DQS[0..7]6
DDR_A_D[0..63]6
+VREFCA_A
1 1
C1252
0.1U_0402_16V4Z
C1252
0.1U_0402_16V4Z
1
2
+VREFDQ_A
C1253
0.1U_0402_16V4Z
C1253
0.1U_0402_16V4Z
1
2
2 2
DIMM_DRAMRST#12,6
DDR_A_MA[0..15]
DDR_A_DQS#[0..7]
DDR_A_DQS[0..7]
DDR_A_D[0..63]
U56
U56
M8
VREFCA
H1
VREFDQ
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12
C1258
2.2U_0603_6.3V6K@C1258
2.2U_0603_6.3V6K
12
DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 DDR_A_MA15 DDR_A_MA15 DDR_A_MA15
@
DDR_A_BS0 DDR_A_BS1 DDR_A_BS2
DDR_A_CLK0 DDR_A_CLK0# DDR_A_CKE0
DDR_A_ODT0 DDR_A_CS0# DDR_A_RAS# DDR_A_CAS# DDR_A_WE#
DDR_A_DQS1 DDR_A_DQS0
DDR_A_DQS#1 DDR_A_DQS#0
DIMM_DRAMRST#
1 2
R992
R992
240_0402_1%
240_0402_1%
DDR_A_ODT1 DDR_A_CS1# DDR_A_CKE1
1 2
R996
R996
240_0402_1%
240_0402_1%
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12
T3
A13
T7
A14
M7
A15/BA3
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE/CKE0
K1
ODT/ODT0
L2
CS/CS0
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
NC/ODT1
L1
NC/CS1
J9
NC/CE1
L9
NCZQ1
96-BALL
96-BALL SDRAM DDR3
SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96
H5TQ2G63BFR-11C_FBGA96
X76@
X76@
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VSSQ VSSQ
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
E3
DDR_A_D8
F7
DDR_A_D10
F2
DDR_A_D13
F8
DDR_A_D11
H3
DDR_A_D12
H8
DDR_A_D15
G2
DDR_A_D9
H7
DDR_A_D14
D7
DDR_A_D3
C3
DDR_A_D1
C8
DDR_A_D2
C2
DDR_A_D4
A7
DDR_A_D7
A2
DDR_A_D0
B8
DDR_A_D6
A3
DDR_A_D5
B2
VDD
D9
VDD
G7
VDD
K2
VDD
K8
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VDD
A1 A8 C1 C9 D2 E9 F1 H2 H9
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J2
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSS
B1 B9 D1 D8 E2 E8 F9 G1 G9
+VREFCA_A
C1255
0.1U_0402_16V4Z
C1255
0.1U_0402_16V4Z
1
2
+VREFDQ_A
C1254
0.1U_0402_16V4Z
C1254
0.1U_0402_16V4Z
1
2
SAGE 3G PVTSAGE 3G PVT SAGE 3G PVT SAGE 3G PVT
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12
C1259
2.2U_0603_6.3V6K@C1259
2.2U_0603_6.3V6K
12
DDR_A_MA13 DDR_A_MA14
@
DDR_A_BS0
DDR_A_BS1 DDR_A_BS2
SAGE 3GSAGE 3G SAGE 3G SAGE 3G
DDR_A_CLK0 DDR_A_CLK0# DDR_A_CKE0
DDR_A_ODT0 DDR_A_CS0# DDR_A_RAS# DDR_A_CAS# DDR_A_WE#
DDR_A_DQS2 DDR_A_DQS3
DDR_A_DQS#2 DDR_A_DQS#3
DIMM_DRAMRST#
1 2
R993
R993
240_0402_1%
240_0402_1%
DDR_A_ODT1 DDR_A_CS1# DDR_A_CKE1
1 2
R997
R997
240_0402_1%
240_0402_1%
U57
U57
M8
VREFCA
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12
T3
A13
T7
A14
M7
A15/BA3
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE/CKE0
K1
ODT/ODT0
L2
CS/CS0
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
NC/ODT1
L1
NC/CS1
J9
NC/CE1
L9
NCZQ1
96-BALL
96-BALL SDRAM DDR3
SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96
H5TQ2G63BFR-11C_FBGA96
X76@
X76@
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VSSQ VSSQ
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
U58
E3
DDR_A_D16
F7
DDR_A_D19
F2
DDR_A_D20
F8
DDR_A_D18
H3
DDR_A_D22
H8
DDR_A_D23
G2
DDR_A_D17
H7
DDR_A_D21
D7
DDR_A_D25
C3
DDR_A_D29
C8
DDR_A_D27
C2
DDR_A_D28
A7
DDR_A_D31
A2
DDR_A_D30
B8
DDR_A_D26
A3
DDR_A_D24
B2
VDD
D9
VDD
G7
VDD
K2
VDD
K8
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VDD
A1 A8 C1 C9 D2 E9 F1 H2 H9
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J2
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSS
B1 B9 D1 D8 E2 E8 F9 G1 G9
+VREFCA_A
C1256
0.1U_0402_16V4Z
C1256
0.1U_0402_16V4Z
+VREFDQ_A
1
2
C1260
0.1U_0402_16V4Z
C1260
0.1U_0402_16V4Z
1
2
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12
C1261
2.2U_0603_6.3V6K@C1261
2.2U_0603_6.3V6K
12
DDR_A_MA13 DDR_A_MA14
@
DDR_A_BS0
DDR_A_BS1 DDR_A_BS2
DDR_A_CLK0 DDR_A_CLK0# DDR_A_CKE0
DDR_A_ODT0 DDR_A_CS0# DDR_A_RAS# DDR_A_CAS# DDR_A_WE#
DDR_A_DQS4 DDR_A_DQS5
DDR_A_DQS#4 DDR_A_DQS#5
DIMM_DRAMRST#
1 2
R994
R994
240_0402_1%
240_0402_1%
DDR_A_ODT1 DDR_A_CS1# DDR_A_CKE1
1 2
R998
R998
240_0402_1%
240_0402_1%
U58
M8
VREFCA
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12
T3
A13
T7
A14
M7
A15/BA3
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE/CKE0
K1
ODT/ODT0
L2
CS/CS0
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
NC/ODT1
L1
NC/CS1
J9
NC/CE1
L9
NCZQ1
96-BALL
96-BALL SDRAM DDR3
SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96
H5TQ2G63BFR-11C_FBGA96
X76@
X76@
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
+1.35V
+VREFCA_A
C1257
0.1U_0402_16V4Z
C1257
0.1U_0402_16V4Z
+VREFDQ_A
E3
DDR_A_D32
F7
DDR_A_D34
F2
DDR_A_D33
F8
DDR_A_D39
H3
DDR_A_D37
H8
DDR_A_D35
G2
DDR_A_D36
H7
DDR_A_D38
D7
DDR_A_D42
C3
DDR_A_D45
C8
DDR_A_D47
C2
DDR_A_D44
A7
DDR_A_D46
A2
DDR_A_D40
B8
DDR_A_D43
A3
DDR_A_D41
B2
VDD
D9
VDD
G7
VDD
K2
VDD
K8
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VDD
A1 A8 C1 C9 D2 E9 F1 H2 H9
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J2
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSS
B1 B9 D1 D8 E2 E8 F9 G1 G9
U59
U59
M8
VREFCA
H1
1
2
C1262
0.1U_0402_16V4Z
C1262
0.1U_0402_16V4Z
1
2
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12
C1263
2.2U_0603_6.3V6K@C1263
2.2U_0603_6.3V6K
12
DDR_A_MA13 DDR_A_MA14
@
DDR_A_BS0 DDR_A_BS1 DDR_A_BS2
DDR_A_CLK0 DDR_A_CLK0# DDR_A_CKE0
DDR_A_ODT0 DDR_A_CS0# DDR_A_RAS# DDR_A_CAS# DDR_A_WE#
DDR_A_DQS6 DDR_A_DQS7
DDR_A_DQS#6 DDR_A_DQS#7
DIMM_DRAMRST#
1 2
R995
R995
240_0402_1%
240_0402_1%
DDR_A_ODT1 DDR_A_CS1# DDR_A_CKE1
1 2
R999
R999
240_0402_1%
240_0402_1%
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12
T3
A13
T7
A14
M7
A15/BA3
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE/CKE0
K1
ODT/ODT0
L2
CS/CS0
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
NC/ODT1
L1
NC/CS1
J9
NC/CE1
L9
NCZQ1
96-BALL
96-BALL SDRAM DDR3
SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96
H5TQ2G63BFR-11C_FBGA96
X76@
X76@
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VSSQ VSSQ
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
E3
DDR_A_D52
F7
DDR_A_D54
F2
DDR_A_D48
F8
DDR_A_D50
H3
DDR_A_D53
H8
DDR_A_D55
G2
DDR_A_D49
H7
DDR_A_D51
D7
DDR_A_D63
C3
DDR_A_D57
C8
DDR_A_D58
C2
DDR_A_D60
A7
DDR_A_D59
A2
DDR_A_D56
B8
DDR_A_D62
A3
DDR_A_D61
B2
VDD
D9
VDD
G7
VDD
K2
VDD
K8
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VDD
A1 A8 C1 C9 D2 E9 F1 H2 H9
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J2
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSS
B1 B9 D1 D8 E2 E8 F9 G1 G9
+1.35V+1.35V +1.35V
SAGE 3G
3 3
+0.675VS
C1459
1U_0402_6.3V6K
C1459
C1461
1U_0402_6.3V6K
C1461
1U_0402_6.3V6K
C1462
1U_0402_6.3V6K
C1462
1U_0402_6.3V6K
12
12
Layout Note: Place near each memory part
+1.35V
C1466
1U_0402_6.3V6K
C1466
1U_0402_6.3V6K
C1476
1U_0402_6.3V6K
C1476
1U_0402_6.3V6K
12
12
+1.35V
4 4
C1479
10U_0603_6.3V6M
C1479
10U_0603_6.3V6M
C1469
10U_0603_6.3V6M
C1469
10U_0603_6.3V6M
12
12
1U_0402_6.3V6K
C1460
1U_0402_6.3V6K
C1460
1U_0402_6.3V6K
12
C1477
1U_0402_6.3V6K
C1477
1U_0402_6.3V6K
12
C1463
10U_0603_6.3V6M
C1463
10U_0603_6.3V6M
12
C1514
1U_0402_6.3V6K
C1514
1U_0402_6.3V6K
12
12
C1467
1U_0402_6.3V6K
C1467
1U_0402_6.3V6K
C1470
1U_0402_6.3V6K
C1470
1U_0402_6.3V6K
12
12
C1465
10U_0603_6.3V6M
C1465
10U_0603_6.3V6M
C1475
10U_0603_6.3V6M
C1475
10U_0603_6.3V6M
12
12
SAGE 3G
C1512
1U_0402_6.3V6K
C1512
1U_0402_6.3V6K
C1511
1U_0402_6.3V6K
C1511
C1513
1U_0402_6.3V6K
C1513
1U_0402_6.3V6K
12
1U_0402_6.3V6K
12
12
SAGE 3G
1K_0402_1%
1K_0402_1%
1K_0402_1%
1K_0402_1%
R1108
R1108
R1107
R1107
+1.35V
12
C1483
0.1U_0402_16V4Z
C1483
0.1U_0402_16V4Z
12
1
2
C1478
1U_0402_6.3V6K
C1478
1U_0402_6.3V6K
C1468
1U_0402_6.3V6K
C1468
C1471
1U_0402_6.3V6K
C1471
1U_0402_6.3V6K
12
C1473
10U_0603_6.3V6M
C1473
10U_0603_6.3V6M
12
1U_0402_6.3V6K
12
12
C1472
10U_0603_6.3V6M
C1472
10U_0603_6.3V6M
C1474
10U_0603_6.3V6M
C1474
10U_0603_6.3V6M
330U_D2_2V_Y
330U_D2_2V_Y
C1464
C1464
12
12
12
+
+
+VREFCA_A
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
C1482
C1482
+1.35V
12
R1106
R1106 1K_0402_1%
1K_0402_1%
+VREFDQ_A
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K C1480
C1480
0.1U_0402_16V4Z
12
R1104
R1104 1K_0402_1%
1K_0402_1%
0.1U_0402_16V4Z
1
12
2
12
near U56 near U57 near U58 near U59
A
B
+0.675VS
C1481
C1481
DDR3 CTL/ADD Termination
1 8
RP30
RP30
RP31
RP31
RP32
RP32
RP33
RP33
RP34
RP34
RP35
RP35
DDR_A_ODT0
2 7
DDR_A_RAS#
3 6
DDR_A_CAS#
4 5
DDR_A_CKE0
36_8P4R_5%
36_8P4R_5%
1 8
DDR_A_CS0#
2 7
DDR_A_MA10
3 6
DDR_A_WE#
4 5
DDR_A_MA15
36_8P4R_5%
36_8P4R_5%
1 8
DDR_A_BS0
2 7
DDR_A_BS1
3 6
DDR_A_BS2
4 5
DDR_A_MA12
36_8P4R_5%
36_8P4R_5%
1 8
DDR_A_MA3
2 7
DDR_A_MA4
3 6
DDR_A_MA0
4 5
DDR_A_MA1
36_8P4R_5%
36_8P4R_5%
1 8
DDR_A_MA2
2 7
DDR_A_MA11
3 6
DDR_A_MA5
4 5
DDR_A_MA6
36_8P4R_5%
36_8P4R_5%
1 8
DDR_A_MA9
2 7
DDR_A_MA14
3 6
DDR_A_MA13
4 5
DDR_A_MA8
36_8P4R_5%
36_8P4R_5%
1 2
DDR_A_MA7
R332 36_0201_1%R332 36_0201_1%
1 2
DDR_A_CKE1
R333 36_0201_1%R333 36_0201_1%
1 2
DDR_A_CS1#
R335 36_0201_1%R335 36_0201_1%
1 2
DDR_A_ODT1
R336 36_0201_1%R336 36_0201_1%
SAGE 3G PVT
C
C1458
C1458
1 2
0.1U_0402_16V4Z
DDR_A_ODT0 6 DDR_A_RAS# 6 DDR_A_CAS# 6 DDR_A_CKE0 6
DDR_A_CS0# 6
DDR_A_WE# 6
DDR_A_BS0 6 DDR_A_BS1 6 DDR_A_BS2 6
DDR_A_CKE1 6
DDR_A_CS1# 6
DDR_A_ODT1 6
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
DDR_A_CLK06
DDR_A_CLK0#6
1.CAD Note: Cterm= 1.8pF should be kept near feeding point of first SDRAM
2.CAD Note: Rtt= 30.1ohms, Ctt= 0.1uF should be kept within 600mils from last SDRAM
0.1U_0402_16V4Z
30.1_0402_1%
30.1_0402_1%
1
C1457
C1457
1.8P_0402_50V8
1.8P_0402_50V8
2
<BOM Structure>
<BOM Structure>
Compal Secret Data
Compal Secret Data
2011/06/24 2012/07/12
2011/06/24 2012/07/12
2011/06/24 2012/07/12
Compal Secret Data
SAGE 3G
DDR3 CLK Termination
12
12
R1102
R1102
Deciphered Date
Deciphered Date
Deciphered Date
D
R1103
R1103
30.1_0402_1%
30.1_0402_1%
END topology
TM_D+33
TM_D-33
1
C233
C233
2
2200P_0402_50V7K
2200P_0402_50V7K
External DDR Thermal Sensor
+3VS
C97
C97
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
U4
U4
1
VDD
2
TM_D+
TM_D-
D+
3
D-
THERM#4GND
W83L771AWG-2 TSSOP8P
W83L771AWG-2 TSSOP8P
SA00003PU00
SA00003PU00
SA00003PU00 S IC W83L771AWG-2 TSSOP 8P SENSOR
Title
Title
Title
DDRIII DIMMA
DDRIII DIMMA
DDRIII DIMMA
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
Date: Sheet of
Date: Sheet of
Date: Sheet of
8
SCLK
7
SDATA
6
5
E
1 2
R546 10K_0402_5%R546 10K_0402_5%
ALERT#
Compal E lectronics, Inc.
Compal E lectronics, Inc.
Compal E lectronics, Inc.
EC_SMB_CK2 14,28
EC_SMB_DA2 14,28
11 52Wednesday, March 13, 2013
11 52Wednesday, March 13, 2013
11 52Wednesday, March 13, 2013
+3VS
0.1
0.1
0.1
A
B
C
D
E
U60
U60
M8
VREFCA
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12
T3
A13
T7
A14
M7
A15/BA3
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE/CKE0
K1
ODT/ODT0
L2
CS/CS0
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
NC/ODT1
L1
NC/CS1
J9
NC/CE1
L9
NCZQ1
96-BALL
96-BALL SDRAM DDR3
SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96
H5TQ2G63BFR-11C_FBGA96
X76@
X76@
DDR_B_DQS#[0..7] 6
DDR_B_DQS[0..7] 6
DDR_B_D[0..63] 6
DDR_B_MA[0..15] 6
E3
DQL0
F7
DQL1
F2
DQL2
F8
DQL3
H3
DQL4
H8
DQL5
G2
DQL6
H7
DQL7
D7
DQU0
C3
DQU1
C8
DQU2
C2
DQU3
A7
DQU4
A2
DQU5
B8
DQU6
A3
DQU7
B2
VDD
D9
VDD
G7
VDD
K2
VDD
K8
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VDD
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H2
VDDQ
H9
VDDQ
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J2
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSS
B1
VSSQ
B9
VSSQ
D1
VSSQ
D8
VSSQ
E2
VSSQ
E8
VSSQ
F9
VSSQ
G1
VSSQ
G9
VSSQ
SAGE 3G SAGE 3G SAGE 3G SAGE 3G
DDR_B_D14 DDR_B_D8 DDR_B_D15 DDR_B_D9 DDR_B_D11 DDR_B_D12 DDR_B_D10 DDR_B_D13
DDR_B_D5 DDR_B_D6 DDR_B_D2 DDR_B_D3 DDR_B_D0 DDR_B_D7 DDR_B_D4 DDR_B_D1
C1295
0.1U_0402_16V4Z
C1295
0.1U_0402_16V4Z
+VREFDQ_B+VREFDQ_B
128@
128@
+VREFCA_B
1
2
128@
128@
1
2
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12
C1293
2.2U_0603_6.3V6K@C1293
2.2U_0603_6.3V6K
C1299
0.1U_0402_16V4Z
C1299
0.1U_0402_16V4Z
12
DDR_B_MA13 DDR_B_MA14
@
DDR_B_BS0 DDR_B_BS1 DDR_B_BS2
DDR_B_CLK0 DDR_B_CLK0# DDR_B_CKE0
DDR_B_ODT0 DDR_B_CS0# DDR_B_RAS# DDR_B_CAS# DDR_B_WE#
DDR_B_DQS2 DDR_B_DQS3
DDR_B_DQS#2 DDR_B_DQS#3
DIMM_DRAMRST#
R1006
1 2
240_0402_1%
240_0402_1%
DDR_B_ODT1 DDR_B_CS1# DDR_B_CKE1
R1010
R1010
1 2
240_0402_1%
240_0402_1%
128@
128@
128@R1006
128@
U61
U61
M8
VREFCA
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12
T3
A13
T7
A14
M7
A15/BA3
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE/CKE0
K1
ODT/ODT0
L2
CS/CS0
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
NC/ODT1
L1
NC/CS1
J9
NC/CE1
L9
NCZQ1
96-BALL
96-BALL SDRAM DDR3
SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96
H5TQ2G63BFR-11C_FBGA96
X76@
X76@
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
U62
128@R1007
128@
U62
M8
VREFCA
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12
T3
A13
T7
A14
M7
A15/BA3
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE/CKE0
K1
ODT/ODT0
L2
CS/CS0
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
NC/ODT1
L1
NC/CS1
J9
NC/CE1
L9
NCZQ1
96-BALL
96-BALL SDRAM DDR3
SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96
H5TQ2G63BFR-11C_FBGA96
X76@
X76@
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
E3
DDR_B_D34
F7
DDR_B_D36
F2
DDR_B_D39
F8
DDR_B_D37
H3
DDR_B_D35
H8
DDR_B_D32
G2
DDR_B_D38
H7
DDR_B_D33
D7
DDR_B_D40
C3
DDR_B_D46
C8
DDR_B_D45
C2
DDR_B_D42
A7
DDR_B_D41
A2
DDR_B_D43
B8
DDR_B_D44
A3
DDR_B_D47
B2
VDD
D9
VDD
G7
VDD
K2
VDD
K8
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VDD
A1 A8 C1 C9 D2 E9 F1 H2 H9
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J2
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSS
B1 B9 D1 D8 E2 E8 F9 G1 G9
E3
DDR_B_D23
DQL0
F7
DDR_B_D21
DQL1
F2
DDR_B_D18
DQL2
F8
DDR_B_D17
DQL3
H3
DDR_B_D19
DQL4
H8
DDR_B_D20
DQL5
G2
DDR_B_D22
DQL6
H7
DDR_B_D16
DQL7
D7
DDR_B_D24
C3
DDR_B_D26
C8
DDR_B_D29
C2
DDR_B_D31
A7
DDR_B_D25
A2
DDR_B_D30
B8
DDR_B_D28
A3
DDR_B_D27
B2
VDD
D9
VDD
G7
VDD
K2
VDD
K8
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VDD
A1 A8 C1 C9 D2 E9 F1 H2 H9
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J2
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSS
B1 B9 D1 D8 E2 E8 F9 G1 G9
C1296
0.1U_0402_16V4Z
C1296
0.1U_0402_16V4Z
1
2
128@
128@
+VREFDQ_B
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
128@
128@
+1.35V +1.35V
2
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12
C1291
2.2U_0603_6.3V6K@C1291
2.2U_0603_6.3V6K
C1300
C1300
12
DDR_B_MA13 DDR_B_MA14
@
DDR_B_BS0 DDR_B_BS1 DDR_B_BS2
DDR_B_CLK0 DDR_B_CLK0# DDR_B_CKE0
DDR_B_ODT0 DDR_B_CS0# DDR_B_RAS# DDR_B_CAS# DDR_B_WE#
DDR_B_DQS4 DDR_B_DQS5
DDR_B_DQS#4 DDR_B_DQS#5
DIMM_DRAMRST#
R1007
1 2
240_0402_1%
240_0402_1%
DDR_B_ODT1 DDR_B_CS1# DDR_B_CKE1
R1011
R1011
1 2
240_0402_1%
240_0402_1%
128@
128@
C1297
0.1U_0402_16V4Z
C1297
0.1U_0402_16V4Z
+VREFDQ_B
128@
128@
+VREFCA_B+VREFCA_B
1
2
128@
128@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12
C1301
C1301
C1302
2.2U_0603_6.3V6K@C1302
2.2U_0603_6.3V6K
12
DDR_B_MA13 DDR_B_MA14
@
DDR_B_BS0 DDR_B_BS1 DDR_B_BS2
SAGE 3GSAGE 3GSAGE 3GSAGE 3G
DDR_B_CLK0 DDR_B_CLK0# DDR_B_CKE0
DDR_B_CS0# DDR_B_RAS# DDR_B_CAS# DDR_B_WE#
DDR_B_DQS7 DDR_B_DQS6
DDR_B_DQS#7 DDR_B_DQS#6
DIMM_DRAMRST#
R1008
1 2
240_0402_1%
240_0402_1%
DDR_B_ODT1 DDR_B_CS1# DDR_B_CKE1
R1012
R1012
1 2
240_0402_1%
240_0402_1%
128@
128@
128@R1008
128@
U63
U63
M8
VREFCA
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12
T3
A13
T7
A14
M7
A15/BA3
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE/CKE0
K1
ODT/ODT0
L2
CS/CS0
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
NC/ODT1
L1
NC/CS1
J9
NC/CE1
L9
NCZQ1
96-BALL
96-BALL SDRAM DDR3
SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96
H5TQ2G63BFR-11C_FBGA96
X76@
X76@
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
E3
DDR_B_D58
DQL0
F7
DDR_B_D56
DQL1
F2
DDR_B_D63
DQL2
F8
DDR_B_D60
DQL3
H3
DDR_B_D62
DQL4
H8
DDR_B_D61
DQL5
G2
DDR_B_D59
DQL6
H7
DDR_B_D57
DQL7
D7
DDR_B_D49
DQU0
C3
DDR_B_D55
DQU1
C8
DDR_B_D52
DQU2
C2
DDR_B_D51
DQU3
A7
DDR_B_D53
DQU4
A2
DDR_B_D50
DQU5
B8
DDR_B_D48
DQU6
A3
DDR_B_D54
DQU7
B2
VDD
D9
VDD
G7
VDD
K2
VDD
K8
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VDD
A1 A8 C1 C9 D2 E9 F1 H2 H9
A9
VSS
B3
VSS
E1
VSS
G8
VSS
J2
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VSS
B1
VSSQ
B9
VSSQ
D1
VSSQ
D8
VSSQ
E2
VSSQ
E8
VSSQ
F9
VSSQ
G1
VSSQ
G9
VSSQ
+1.35V+1.35V
Channel B
+VREFCA_B
1 1
2 2
C1294
0.1U_0402_16V4Z
C1294
0.1U_0402_16V4Z
1
2
128@
128@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
128@
128@
2
DIMM_DRAMRST#11 ,6
SAGE 3G PVT SAGE 3G PVT SAGE 3G PVT SAGE 3G PVT
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12
C1292
2.2U_0603_6.3V6K@C1292
2.2U_0603_6.3V6K
C1298
C1298
12
DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 DDR_B_MA15 DDR_B_MA15 DDR_B_MA15
@
DDR_B_BS0 DDR_B_BS1 DDR_B_BS2
DDR_B_CLK0 DDR_B_CLK0# DDR_B_CKE0
DDR_B_ODT0 DDR_B_ODT0 DDR_B_CS0# DDR_B_RAS# DDR_B_CAS# DDR_B_WE#
DDR_B_DQS1 DDR_B_DQS0
DDR_B_DQS#1 DDR_B_DQS#0
DIMM_DRAMRST#
R1005
128@R1005
128@
1 2
240_0402_1%
240_0402_1%
DDR_B_ODT1 DDR_B_CS1# DDR_B_CKE1
R1009
R1009
1 2
240_0402_1%
240_0402_1%
128@
128@
+VREFCA_B
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
C1507
C1507
+1.35V
12
R1123
R1123 1K_0402_1%
1K_0402_1%
128@
128@
+VREFDQ_B
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K C1509
C1509
128@
R1121
R1121 1K_0402_1%
1K_0402_1%
128@
128@
128@
C1510
0.1U_0402_16V4Z
C1510
0.1U_0402_16V4Z
1
12
2
128@
128@
C
12
128@
128@
12
+0.675VS
SAGE 3G
DDR3 CTL/ADD Termination
RP36
RP36
4 5
DDR_B_ODT0
3 6
DDR_B_CKE0
2 7
DDR_B_RAS#
1 8
DDR_B_CAS#
36_8P4R_5%128@
36_8P4R_5%128@
RP37
RP37
4 5
DDR_B_CS0#
3 6
DDR_B_WE#
2 7
DDR_B_MA10
1 8
DDR_B_BS0
36_8P4R_5%128@
36_8P4R_5%128@
RP38
RP38
4 5
DDR_B_MA15
3 6
DDR_B_BS2
2 7
DDR_B_BS1
1 8
DDR_B_MA0
36_8P4R_5%128@
36_8P4R_5%128@
RP39
RP39
4 5
DDR_B_MA12
3 6
DDR_B_MA3
2 7
DDR_B_MA1
1 8
DDR_B_MA2
36_8P4R_5%128@
36_8P4R_5%128@
RP40
RP40
4 5
DDR_B_MA4
3 6
DDR_B_MA5
2 7
DDR_B_MA11
1 8
DDR_B_MA9
36_8P4R_5%128@
36_8P4R_5%128@
RP41
RP41
4 5
DDR_B_MA6
3 6
DDR_B_MA7
2 7
DDR_B_MA14
1 8
DDR_B_MA13
36_8P4R_5%128@
36_8P4R_5%128@
128@
128@
1 2
DDR_B_MA8
R390 36_0 201_1%
R390 36_0 201_1%
128@
128@
1 2
DDR_B_CKE1
R339 36_0 201_1%
R339 36_0 201_1%
128@
128@
1 2
DDR_B_CS1#
R340 36_0 201_1%
R340 36_0 201_1%
128@
128@
1 2
DDR_B_ODT1
R342 36_0 201_1%
R342 36_0 201_1%
SAGE 3G PVT
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DDR_B_ODT0 6 DDR_B_CKE0 6 DDR_B_RAS# 6 DDR_B_CAS# 6
DDR_B_CS0# 6
DDR_B_WE# 6
DDR_B_BS0 6
DDR_B_BS2 6 DDR_B_BS1 6
DDR_B_CKE1 6
DDR_B_CS1# 6
DDR_B_ODT1 6
Compal Secret Data
Compal Secret Data
D
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2011/06/24 2012/06/02
2011/06/24 2012/06/02
2011/06/24 2012/06/02
1.CAD Note: Cterm= 1.8pF should be kept near feeding point of first SDRAM
2.CAD Note: Rtt= 30.1ohms, Ctt= 0.1uF should be kept within 600mils from last SDRAM
SAGE 3G
DDR_B_CLK06
DDR_B_CLK0#6
DDR3 CLK Termination
C1506
128@ C1506
128@
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R1117
R1117
30.1_0402_1%
30.1_0402_1%
12
12
R1118
R1118
30.1_0402_1%
30.1_0402_1%
128@
128@
128@
128@
END topology
1
C1505
C1505
1.8P_0402_50V8
1.8P_0402_50V8
128@
128@
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
DDRIII DIMMB
DDRIII DIMMB
DDRIII DIMMB
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
E
0.1
0.1
0.1
12 52Wednesday, March 13, 2013
12 52Wednesday, March 13, 2013
12 52Wednesday, March 13, 2013
+0.675VS
C1504
1U_0402_6.3V6K@C1504
1U_0402_6.3V6K
C1503
1U_0402_6.3V6K@C1503
1U_0402_6.3V6K
12
3 3
4 4
12
@
@
Layout Note: Place near each memory part
+1.35V
C1497
1U_0402_6.3V6K@C1497
1U_0402_6.3V6K
C1487
1U_0402_6.3V6K@C1487
1U_0402_6.3V6K
12
12
@
@
+1.35V
C1490
10U_0603_6.3V6M@C1490
10U_0603_6.3V6M
C1500
10U_0603_6.3V6M@C1500
10U_0603_6.3V6M
@
@
12
12
A
C1501
1U_0402_6.3V6K@C1501
1U_0402_6.3V6K
C1502
1U_0402_6.3V6K@C1502
1U_0402_6.3V6K
12
12
@
@
C1488
1U_0402_6.3V6K@C1488
1U_0402_6.3V6K
C1498
1U_0402_6.3V6K@C1498
1U_0402_6.3V6K
12
12
@
@
C1496
10U_0603_6.3V6M@C1496
10U_0603_6.3V6M
C1485
10U_0603_6.3V6M@C1485
10U_0603_6.3V6M
@
@
12
12
SAGE 3G
SAGE 3G
+1.35V
12
R1120
R1120
1K_0402_1%
1K_0402_1%
128@
128@
128@
128@
12
C1508
0.1U_0402_16V4Z
C1508
0.1U_0402_16V4Z
1
R1119
R1119
1K_0402_1%
1K_0402_1%
128@
128@
B
2
A
12
1
R568
+RTCVCC
R338 20K_0402_5%R338 20K_0402_ 5%
R337 20K_0402_5%R337 20K_0402_ 5%
1 1
C516
C516
1U_0402_6.3V6K
1U_0402_6.3V6K
1 2
1 2
C502
C502
1U_0402_6.3V6K
1U_0402_6.3V6K
R568 0_0603_5%
0_0603_5%
@
@
2
PCH_RTCRST#
PCH_SRTCRST#
12
1
R561
R561 0_0603_5%
0_0603_5%
@
@
2
SAGE 3G
1 2
R638 10M_0402_5%R638 10M_0402_5%
X1
X1
SJ100004Z00
SJ100004Z00
12
32.768KHZ_12.5PF_1TJF125DP1A000D
32.768KHZ_12.5PF_1TJF125DP1A000D
1
C756
C756 15P_0402_50V8J
15P_0402_50V8J
2
SAGE 3G DVT
R561, R568 put on TOP
+RTCVCC
1 2
R353 1M_0402_5%R353 1M_0402_5%
1 2
R347 330K_0402_5%R347 330K_0402_5 %
INTVRMEN
H
Integrated VRM enable
*
L
Integrated VRM disable
SM_INTRUDER#
PCH_INTVRMEN
(INTVRMEN should always be pull high.)
+3VS
HIGH= Enable ( No Reboot)Disable TCO timer system reboot feature
LOW= Disable (Default internal PD)
*
2 2
HDA_SDO28
HDA_SDO
ME debug mode,this signal has a weak internal PD
Low = Disabled (Default)
*
High = Enabled [Flash Descriptor Security Overide]
+VCCSUS3_3
This signal has a weak internal pull-down
On Die PLL VR Select is supplied by
1.5V when smapled high
*
1.8V when sampled low Needs to be pulled High for Huron River platfrom
HDA_BITCLK_AUDIO33
3 3
HDA_SYNC_AUDIO33 HDA_RST_AUDIO#33
HDA_SDOUT_AUDIO33
@
@
1 2
R405 1K_0402_5%
R405 1K_0402_5%
+VCCSUS3_3
R328 1K_0402_ 5%R328 1K_0402_5%
1K_0402_5%
1K_0402_5%
0_0402_5%
0_0402_5%
12
R322
@R32 2
@
@
@
R320
R320
12
12
HDA_SYNC_PCH
PCH_SPKR
HDA_SDOUT_PCH
SAGE 3G
RP11
RP11
45
HDA_BITCLK_PCH
36
HDA_SYNC_PCH_R
27
HDA_RST_PCH#
18
HDA_SDOUT_PCH
33_8P4R_5%
33_8P4R_5%
SAGE 3G Reserve for RF / Close to PCH
12
PCH_SPI_CLK_0
C1031.8P_0402_50V8XEMC@ C1031.8P_0402 _50V8XEMC@
12
PCH_SPI_CLK_1
C1041.8P_0402_50V8XEMC@ C1041.8P_0402_50V8XEMC@
12
HDA_BITCLK_AUDIO
C1051.8P_0402_50V8XEMC@ C1051.8P_0402 _50V8XEMC@
Prevent back drive issue.
+5VS
G
G
2
Q20
Q20 BSS138W-7-F_SOT323
BSS138W-7-F_SOT323
13
HDA_SYNC_PCH
D
S
D
S
R302
R302
1 2
0_0402_5%@
R468
R468 1M_0402_5%
1M_0402_5%
<BOM Structure>
<BOM Structure>
PCH_SPI_CLK_0
PCH_SPI_CLK_1
SAGE 3G
PCH_SPI_MOSI_0
PCH_SPI_MOSI_1
PCH_SPI_MISO_0
PCH_SPI_MISO_1
0_0402_5%@
R739 33_0402_5%R739 33_0402_ 5%
R704 33_0402_5%R704 33_0402_ 5%
R737 33_0402_5%R737 33_0402_ 5%
R734 33_0402_5%R734 33_0402_ 5%
R736 33_0402_5%R736 33_0402_ 5%
R738 33_0402_5%R738 33_0402_ 5%
12
HSPI to EC
PCH_SPI_CS1#28
4 4
PCH_SPI_CLK_128
PCH_SPI_MISO_128
PCH_SPI_MOSI_128
PCH_SPI_CS1# PCH_SPI_CLK_1 PCH_SPI_MISO_1 PCH_SPI_MOSI_1
B
PCH_RTCX1
PCH_RTCX2
1
C757
C757 15P_0402_50V8J
15P_0402_50V8J
2
PCH_SPKR33
HDA_SDIN033
12
12
12
12
12
12
R672
R672
51_0402_5%
51_0402_5%
T57 PAD @T57 PAD @
T73 PAD @T73 PAD @
T75 PAD @T75 PAD @
PCH_RTCX1
PCH_RTCX2
PCH_RTCRST#
PCH_SRTCRST#
SM_INTRUDER#
PCH_INTVRMEN
HDA_BITCLK_PCH
HDA_SYNC_PCH
PCH_SPKR
HDA_RST_PCH#
HDA_SDIN0
HDA_SDOUT_PCH
SAGE 3G
12
PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#
PCH_SPI_MOSI
PCH_SPI_MISO
+RTCVCC
+RTCBATT
3
1
C197
C197
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
U37A
U37A
A20
RTCX1
C20
RTCX2
D20
RTCRST#
G22
SRTCRST#
K22
INTRUDER#
C17
INTVRMEN
N34
HDA_BCLK
L34
HDA_SYNC
T10
SPKR
K34
HDA_RST#
E34
HDA_SDIN0
G34
HDA_SDIN1
C34
HDA_SDIN2
A34
HDA_SDIN3
A36
HDA_SDO
C36
HDA_DOCK_EN# / GPIO33
N32
HDA_DOCK_RST# / GPIO13
J3
JTAG_TCK
H7
JTAG_TMS
K5
JTAG_TDI
H1
JTAG_TDO
T3
SPI_CLK
Y14
SPI_CS0#
T1
SPI_CS1#
V4
SPI_MOSI
U3
SPI_MISO
COUGARPOINT_FCBGA989~D
COUGARPOINT_FCBGA989~D
HM77@
HM77@
1
D5
D5 BAS40-04_SOT23-3
BAS40-04_SOT23-3
2
+CHGRTC
20MIL
RTC Battery:Chargeable
RTCIHDA
RTCIHDA
JTAG
JTAG
SPI
SPI
S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO!SA00005AGI0
S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO!SA00005AGI0
C
FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3
LPC
LPC
FWH4 / LFRAME#
LDRQ0#
LDRQ1# / GPIO23
SERIRQ
SATA0RXN SATA0RXP SATA0TXN
SATA0TXP
SATA1RXN
SATA 6G
SATA 6G
SATA1RXP SATA1TXN
SATA1TXP
SATA2RXN SATA2RXP SATA2TXN
SATA2TXP
SATA3RXN SATA3RXP SATA3TXN
SATA3TXP
SATA4RXN SATA4RXP SATA4TXN
SATA
SATA
SATA4TXP
SATA5RXN SATA5RXP SATA5TXN
SATA5TXP
SATAICOMPO
SATAICOMPI
SATA3RCOMPO
SATA3COMPI
SATA3RBIAS
SATALED#
SATA0GP / GPIO21
SATA1GP / GPIO19
C38 A38 B37 C37
D36
E36 K36
V5
AM3 AM1 AP7 AP5
AM10 AM8 AP11 AP10
AD7 AD5 AH5 AH4
AB8 AB10 AF3 AF1
Y7 Y5 AD3 AD1
Y3 Y1 AB3 AB1
Y11
Y10
AB12
AB13
AH1
P3
V14
P1
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
LPC_FRAME#
PCH_GPIO23
SERIRQ
SATA_COMP
SATA3_COMP
RBIAS_SATA3
PCH_SATALED#
PCH_GPIO21
PCH_GPIO19
LPC_AD0 26,2 8 LPC_AD1 26,2 8 LPC_AD2 26,2 8 LPC_AD3 26,2 8
LPC_FRAME# 26,28
PCH_GPIO23 18
SERIRQ 26, 28
SATA_PRX_DTX_N0 25 SATA_PRX_DTX_P0 25 SATA_PTX_DRX_N0 25 SATA_PTX_DRX_P0 25
SATA_PRX_DTX_N1 25 SATA_PRX_DTX_P1 25 SATA_PTX_DRX_N1 25 SATA_PTX_DRX_P1 25
+1.05VS_PCH
R389
R389
37.4_0402_1%
37.4_0402_1%
1 2
+1.05VS_PCH
R388
R388
49.9_0402_1%
49.9_0402_1%
1 2
1 2
R650 750_0402_1%R650 750_0402_1%
D
PCH_GPIO201 4
No use PH 10K +3VS
GPIO19 has internal Pull up
SAGE 3G
SERIRQ PCH_SATALED# PCH_GPIO20 PCH_GPIO21
Switchable
*
Boot BIOS
Reserved
*
CRB:10K ohm Check List 1.0:8.2K ohm
4 5 3 6 2 7 1 8
RP28 10K_8P4R_5 %RP28 10K_8P4R_5 %
R688 10K_0402_5%
R688 10K_0402_5%
12
@
@
Switchable Graph
GPIO21
0
Non SG
PCH_GPIO19
Debug Port DG 1.2 PH 4.7K +3VS
Boot BIOS Strap
1
R674
R674
4.7K_0402_5%
4.7K_0402_5%
GPIO51
LPC
0 0 0
-
SPI
1 1 1
E
+3VS
+3VS
12
GPIO19
1 0
R703 3.3K_0402_5%R703 3.3K_0402_5%
+3VS
A
1 2
PCH_SPI_CS0# PCH_SPI_MISO_0 SPI_WP0#
2MB=16Mb
U42
U42
1
CS#
2
SO
3
WP#
4
GND
W25Q16CVSSIG_SO8
W25Q16CVSSIG_SO8
SA00003FO10
SA00003FO10
VCC
HOLD#
SCLK
+3VS
8 7
SPI_HOLD0#
6
PCH_SPI_CLK_0
5
PCH_SPI_MOSI_0
SI
B
R701 3.3K_0402_5%R701 3.3K_0402_5%
12
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
+3VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2011/06/24 2012/06/02
2011/06/24 2012/06/02
2011/06/24 2012/06/02
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Do cument Number Rev
Size Do cument Number Rev
Size Do cument Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (1/8) SATA,HDA,SPI, LPC, XDP
PCH (1/8) SATA,HDA,SPI, LPC, XDP
PCH (1/8) SATA,HDA,SPI, LPC, XDP
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
E
13 52Wednesday, March 13, 2 013
13 52Wednesday, March 13, 2 013
13 52Wednesday, March 13, 2 013
0.1
0.1
0.1
A
Mini Card 1 On Board WLAN
Card Reader
1 1
2 2
Mini Card 1 (On Board WLAN)
PCIE_PRX_DTX_N124
PCIE_PRX_DTX_P124 PCIE_PTX_C_DRX_N124 PCIE_PTX_C_DRX_P124
PCIE_PRX_DTX_N232
PCIE_PRX_DTX_P232 PCIE_PTX_C_DRX_N232 PCIE_PTX_C_DRX_P232
SAGE 3G
No use PH 10K +3VALW
CLK_PCIE_MINI1#24 CLK_PCIE_MINI124
MINI1_CLKREQ#24
1 2
C573 0.1U_0402_16V7KC573 0.1U_0402_16V7K
1 2
C572 0.1U_0402_16V7KC572 0.1U_0402_16V7K
1 2
C574 0.1U_0402_16V7KC574 0.1U_0402_16V7K
1 2
C575 0.1U_0402_16V7KC575 0.1U_0402_16V7K
No use PH 10K +3VS
PCH_GPIO2013
No use PH 10K +3VS
No use PH 10K +3VALW
SAGE 3G
3 3
CLK_PCIE_CARD#32 CLK_PCIE_CARD32
CARD_CLKREQ#32
No use PH 10K +3VALW
No use PH 10K +3VALW
No use PH 10K +3VALW
CLK_RES_ITP#7 CLK_RES_ITP7
R1134 0_0201_5%@R1134 0_0201_5%@ R1135 0_0201_5%@R1135 0_0201_5%@
12 12
No use PH 10K +3VALW
AK14:CLKOUT_ITPXDP_N AK13:CLKOUT_ITPXDP_P
SAGE 3G
4 4
+3VS
+VCCSUS3_3
4 5 3 6 2 7 1 8
RP22 10K_8P4R_5%RP22 10K_8P4R_5%
4 5 3 6 2 7 1 8
RP21 10K_8P4R_5%RP21 10K_8P4R_5%
A
CARD_CLKREQ# PCH_GPIO25 PEG_CLKREQ# MINI1_CLKREQ#
PCH_GPIO73 PCH_GPIO44 PCH_GPIO45 PCH_GPIO46
B
PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1
PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2
PCH_GPIO73
MINI1_CLKREQ#
PCH_GPIO20
PCH_GPIO25
CARD_CLKREQ#
PCH_GPIO44
PEG_CLKREQ#
PCH_GPIO45
PCH_GPIO46
CLK_BCLK_ITP# CLK_BCLK_ITP
B
U37B
U37B
BG34
PERN1
BJ34
PERP1
AV32
PETN1
AU32
PETP1
BE34
PERN2
BF34
PERP2
BB32
PETN2
AY32
PETP2
BG36
PERN3
BJ36
PERP3
AV34
PETN3
AU34
PETP3
BF36
PERN4
BE36
PERP4
AY34
PETN4
BB34
PETP4
BG37
PERN5
BH37
PERP5
AY36
PETN5
BB36
PETP5
BJ38
PERN6
BG38
PERP6
AU36
PETN6
AV36
PETP6
BG40
PERN7
BJ40
PERP7
AY40
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW38
PETN8
AY38
PETP8
Y40
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P
J2
PCIECLKRQ0# / GP IO73
AB49
CLKOUT_PCIE1N
AB47
CLKOUT_PCIE1P
M1
PCIECLKRQ1# / GP IO18
AA48
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P
V10
PCIECLKRQ2# / GP IO20
Y37
CLKOUT_PCIE3N
Y36
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GP IO25
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P
L12
PCIECLKRQ4# / GP IO26
V45
CLKOUT_PCIE5N
V46
CLKOUT_PCIE5P
L14
PCIECLKRQ5# / GP IO44
AB42
CLKOUT_PEG_B_N
AB40
CLKOUT_PEG_B_P
E6
PEG_B_CLKRQ# / GPIO56
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
T13
PCIECLKRQ6# / GP IO45
V38
CLKOUT_PCIE7N
V37
CLKOUT_PCIE7P
K12
PCIECLKRQ7# / GP IO46
AK14
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
AK13
CLKOUT_BCLK0_P / CLKOUT_PCIE8P
COUGARPOINT_FCBGA989~D
COUGARPOINT_FCBGA989~D
HM77@
HM77@
S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO!SA00005AGI0
S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO!SA00005AGI0
SMBUSController
SMBUSController
SML1ALERT# / PC HHOT# / GPIO74
PCI-E*
PCI-E*
CLOCKS
CLOCKS
CLKOUT_DP_N / C LKOUT_BCLK1_N
CLKOUT_DP_P / C LKOUT_BCLK1_P
CLKIN_GND1_N CLKIN_GND1_P
C
SMBALERT# / GP IO11
SMBCLK
SMBDATA
SML0ALERT# / GP IO60
SML0CLK
SML0DATA
SML1CLK / GPIO58
SML1DATA / GPIO7 5
CL_CLK1
Link
Link
PEG_A_CLKRQ# / GPIO47
CLKIN_SATA_N / CKS SCD_N CLKIN_SATA_P / CKS SCD_P
FLEX CLOCKS
FLEX CLOCKS
CL_DATA1
CL_RST1#
CLKOUT_PEG_A_N CLKOUT_PEG_A_P
CLKOUT_DMI_N CLKOUT_DMI_P
CLKIN_DMI_N CLKIN_DMI_P
CLKIN_DMI2_N CLKIN_DMI2_P
CLKIN_DOT_96N CLKIN_DOT_96P
REFCLK14IN
CLKIN_PCILOOPBACK
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
CLKOUTFLEX0 / G PIO64
CLKOUTFLEX1 / G PIO65
CLKOUTFLEX2 / G PIO66
CLKOUTFLEX3 / G PIO67
E12
SMB_ALERT#
H14
PCH_SMBCLK
C9
PCH_SMBDATA
A12
DRAMRST_CNTRL_PC H
C8
PCH_SML0CLK
G12
PCH_SML0DATA
C13
PCH_GPIO74
E14
PCH_SML1CLK
M16
PCH_SML1DATA
M7
T11
P10
M10
PCH_GPIO47
AB37 AB38
AV22
CLK_CPU_DMI#
AU22
CLK_CPU_DMI
AM12
CLK_CPU_DPLL#
AM13
CLK_CPU_DPLL
BF18
CLK_BUF_CPU_DMI#
BE18
CLK_BUF_CPU_DMI
BJ30
CLKIN_GND1#
BG30
CLKIN_GND1
G24
CLK_BUF_DREF_96M#
E24
CLK_BUF_DREF_96M
AK7
CLK_BUF_PCIE_SATA#
AK5
CLK_BUF_PCIE_SATA
K45
CLK_BUF_ICH_14M
H45
CLK_PCI_LPBACK
V47
XTAL25_IN
V49
XTAL25_OUT
Y47
XCLK_RCOMP
K43
CLK_FLEX0
F47
CLK_FLEX1
H47
CLK_FLEX2
K49
DGPU_PRSNT#
DRAMRST_CNTRL_PC H 6
S3 reduse
CLK_CPU_DMI# 5 CLK_CPU_DMI 5
CLK_CPU_DPLL# 5 CLK_CPU_DPLL 5
1 2
R357 10K_0402_5 %R357 10K_0402_5%
1 2
R358 10K_0402_5 %R358 10K_0402_5%
1 2
R330 10K_0402_5 %R330 10K_0402_5%
1 2
R331 10K_0402_5 %R331 10K_0402_5%
1 2
R346 10K_0402_5 %R346 10K_0402_5%
1 2
R345 10K_0402_5 %R345 10K_0402_5%
1 2
R387 10K_0402_5 %R387 10K_0402_5%
1 2
R393 10K_0402_5 %R393 10K_0402_5%
1 2
R292 10K_0402_5 %R292 10K_0402_5%
R293 33_0402_5%
R293 33_0402_5%
XEMC@
XEMC@
Reserve for EMI please close to PCH
R289
R289
90.9_0402_1%
90.9_0402_1%
1 2
@
@
PAD
PAD
T52
T52
@
@
PAD
PAD
T53
T53
@
@
PAD
PAD
T21
T21
D
No use PH 10K +3VALW
PH 2.2K +3VALW
No use PH 10K +3VALWS3 reduse
No use PH 10K +3VALW
PH 2.2K +3VALW
No use PH 10K +3VALW
120MHz for eDP.
12
1 2
C421 22P_0402_50V8J
C421 22P_0402_50V8J
XEMC@
XEMC@
+1.05VS_PCH
Pull down 10K ohm for using internal Clock
SAGE 3G
SAGE 3G DVT
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2011/06/24 2012/06/02
2011/06/24 2012/06/02
2011/06/24 2012/06/02
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
E
SAGE 3G
RP18
RP18
PCH_SMBCLK PCH_SMBDATA PCH_SML0CLK PCH_SML0DATA
PCH_SML1CLK
PCH_SML1DATA
DRAMRST_CNTRL_PC H
SMB_ALERT# PCH_GPIO74 PCH_GPIO47 DGPU_PRSNT#
DIS,Optimus
+3VS
PCH_SML1DATA
PCH_SML1CLK
CLK_PCI_LPBACK 17
3 4
Q22A
Q22A DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
XTAL25_IN
XTAL25_OUT
C744
C744 12P_0402_50V8J
12P_0402_50V8J
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
Date: Sheet of
Date: Sheet of
Date: Sheet of
4 5 3 6 2 7 1 8
2.2K_8P4R_5%
2.2K_8P4R_5%
1 2
R375 2.2K_0402_5%R375 2.2K_0402_5%
1 2
R369 2.2K_0402_5%R369 2.2K_0402_5%
1 2
R648 1K_0402_5%R648 1K_0402_5%
RP23
RP23
4 5 3 6 2 7 1 8
10K_8P4R_5%
10K_8P4R_5%
GPIO67
DGPU_PRSNT#
0
UMA
5
SGD
SGD
2
G
G
6 1
S
D
S
D
Q22B
Q22B DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
1
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
PCH (2/8) PCIE, SMBUS, CLK
PCH (2/8) PCIE, SMBUS, CLK
PCH (2/8) PCIE, SMBUS, CLK
1
Pull up at EC side.
For DDR,EC
EC_SMB_DA2
EC_SMB_CK2
1 2
R611 1M_0402_5%R611 1M_0402_5%
25MHZ_10PF_7V25000014
25MHZ_10PF_7V25000014
3
3
GND
4
Y1
Y1
E
+VCCSUS3_3
EC_SMB_DA2 11,28
EC_SMB_CK2 11,28
1
GND
2
1
14 52Wednesday, March 13, 2013
14 52Wednesday, March 13, 2013
14 52Wednesday, March 13, 2013
+3VS
1
C745
C745 12P_0402_50V8J
12P_0402_50V8J
2
0.1
0.1
0.1
A
SAGE 3G
+3VLP
R341 100K_0402_5%R341 100K_0402_5%
+VCCSUS3_3
1 1
R373 200_0402_5%R373 200_0402_5%
RP24 10K_8P4R_5%RP24 10K_8P4R_5%
4 5 3 6 2 7 1 8
12
12
PCH_ACIN
PM_DRAM_PWR GD
PCH_GPIO72 PCH_GPIO30 RI# PCH_RSMRST#
SAGE 3G
not support Deep S4,S5 mux with SUS_PWR_DN_ACK
not support AMT APWROK can mux
2 2
with PWROK (check list1.0 P.40)
SAGE 3G
No use PH 10K +3VALW
SAGE 3G
12
C7530.1U_0201_10V6K
C7530.1U_0201_10V6K
XEMC@
XEMC@
PM_DRAM_PWR GD
XDP_DBRESET#
T16PAD@ T16PAD@
3 3
Ring Indicator CRB1.0 PH 10K +3VALW
SUSACK#28
XDP_DBRESET#5
SAGE 3G
SA_PGOOD28,41
PM_DRAM_PWR GD5
PCH_RSMRST#28
SUSWARN#28
PBTN_OUT#28
ACPRESENT28
PCH_BATLOW#28
B
DMI_CTX_PRX_N04 DMI_CTX_PRX_N14 DMI_CTX_PRX_N24 DMI_CTX_PRX_N34
DMI_CTX_PRX_P04 DMI_CTX_PRX_P14 DMI_CTX_PRX_P24 DMI_CTX_PRX_P34
DMI_CRX_PTX_N04 DMI_CRX_PTX_N14 DMI_CRX_PTX_N24 DMI_CRX_PTX_N34
DMI_CRX_PTX_P04 DMI_CRX_PTX_P14 DMI_CRX_PTX_P24 DMI_CRX_PTX_P34
+1.05VS_PCH
R632 750_0402_1%R632 750_0402_1%
4mil width and place within 500mil of the PCH
PCH_GPIO30
R409 0_0402_5%
R409 0_0402_5%
R372 0_0402_5%
R372 0_0402_5%
R661 0_0402_5%
R661 0_0402_5%
PCH_PWROK
R382 0_0402_ 5%
R382 0_0402_ 5%
R412 0_0402_5%
R412 0_0402_5%
R456
R456
DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3
DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3
DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3
DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3
1 2
R625 49.9_0402_1%R625 49.9_0402_1%
1 2
1 2
S3@
S3@
1 2
1 2
1 2
1 2 1 2
1 2
0_0402_5%
0_0402_5%
1 2
@
@
R502 0_0402_5%
R502 0_0402_5%
@
@
@
@
@
@
@
@
1 2
@
@
DMI_IRCOMP
DMI2RBIAS
XDP_DBRESET#_R
SYS_PWROK
PCH_PWROK_R
APWROK
R4870_0402_5% @ R4870_0402_5% @
R4930_0402_5% @ R4930_0402_5% @
PM_DRAM_PWR GD
PCH_RSMRST#
PCH_GPIO30
PBTN_OUT#
PCH_ACIN
PCH_GPIO72
RI#
U37C
U37C
BC24
DMI0RXN
BE20
DMI1RXN
BG18
DMI2RXN
BG20
DMI3RXN
BE24
DMI0RXP
BC20
DMI1RXP
BJ18
DMI2RXP
BJ20
DMI3RXP
AW24
DMI0TXN
AW20
DMI1TXN
BB18
DMI2TXN
AV18
DMI3TXN
AY24
DMI0TXP
AY20
DMI1TXP
AY18
DMI2TXP
AU18
DMI3TXP
BJ24
DMI_ZCOMP
BG25
DMI_IRCOMP
BH21
DMI2RBIAS
C12
SUSACK#
K3
SYS_RESET#
P12
SYS_PWROK
L22
PWROK
L10
APWROK
B13
DRAMPWROK
C21
RSMRST#
K16
SUSWARN# / SUS_PW R_DN_ACK / GPIO30
E20
PWRBTN#
H20
ACPRESENT / GPIO31
E10
BATLOW# / GPIO72
A10
RI#
COUGARPOINT_FCBGA989~D
COUGARPOINT_FCBGA989~D
HM77@
HM77@
S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO!SA00005AGI0
S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO!SA00005AGI0
C
DMI
FDI
DMI
FDI
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
System Power Management
System Power Management
SLP_LAN# / GPIO29
FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7
FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWVRMEN
DPWROK
WAKE#
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
PMSYNCH
BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9
BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9
AW16
AV12
BC10
AV14
BB10
A18
E22
B9
N3
G8
N14
D10
H4
F4
G10
G16
AP14
K14
FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7
FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWODVREN
1 2
R426
1 2
R421
PCH_PCIE_WAKE#
CLKRUN#
SUS_STAT#
SUSCLK
PM_SLP_S5#
PM_SLP_S4#
PM_SLP_S3#
SLP_A#
SLP_SUS#
H_PM_SYNC
PCH_GPIO29
S3@R426
S3@
NC
@R421
@
PCH_RSMRST#
0_0402_5%
0_0402_5%
DPWROK
0_0402_5%
0_0402_5%
T19 PAD
T19 PAD
@
@
T18 PAD
T18 PAD
@
@
T51 PAD
T51 PAD
@
@
D
FDI_CTX_PRX_N0 4 FDI_CTX_PRX_N1 4 FDI_CTX_PRX_N2 4 FDI_CTX_PRX_N3 4 FDI_CTX_PRX_N4 4 FDI_CTX_PRX_N5 4 FDI_CTX_PRX_N6 4 FDI_CTX_PRX_N7 4
FDI_CTX_PRX_P0 4 FDI_CTX_PRX_P1 4 FDI_CTX_PRX_P2 4 FDI_CTX_PRX_P3 4 FDI_CTX_PRX_P4 4 FDI_CTX_PRX_P5 4 FDI_CTX_PRX_P6 4 FDI_CTX_PRX_P7 4
FDI_INT 4
FDI_FSYNC0 4
FDI_FSYNC1 4
FDI_LSYNC0 4
FDI_LSYNC1 4
DPWROK 28
PCH_PCIE_WAKE# 24
No use PH 10K +3VS
PM_SLP_S5# 28
PM_SLP_S4# 28
PM_SLP_S3# 28
SLP_SUS# 28
H_PM_SYNC 5
No use PH 10K +3VALW
SAGE 3G
Can be left NC when IAMT is not support on the platfrom
not support Deep S4,S5 can NC PCH EDS1.2 P.74
E
+RTCVCC
DSWODVREN
*
not support Deep S4,S5 DPWROK mux with RSMRST# check list1.0 P.42
PCH_PCIE_WAKE#
PCH_GPIO29
CLKRUN#
DPWROK
R361 330K_0402_5%R361 330K_0402_5%
R360 330K_0402_5%@R360 330 K_0402_5%@
DSWODVREN - On Die DSW VR Enable
H
Enable internal DSW +1.05VS
L
Disable
Must always PH at +RTCVCC
CRB=>1k ohm Follow Check Li st R1.5
R656 10K_0402_5%R656 10K_0402_5%
R395 10K_0402_5%@R395 10K_0402_5%@
R653 8.2K_0402_5%R653 8.2K_0402_5%
R667 100K_0402_5%R667 100K_0402_5%
12
12
+VCCSUS3_3
1 2
1 2
+3VS
1 2
1 2
CR CHKLST Rev2.0
For EMI
tell PCH all power ok but cpu core
PCH_PWROK28
4 4
A
12
R680
R680 10K_0402_5%
10K_0402_5%
VGATE42
+3VS
5
U39
U39
2
B
1
A
3
ALL power OK
P
4
SYS_PWROK
Y
G
MC74VHC1G08DFT2G_SC70-5
MC74VHC1G08DFT2G_SC70-5
12
R681
R681 10K_0402_5%
10K_0402_5%
B
1
C603
C603
.047U_0402_16V7K
.047U_0402_16V7K
2
@
@
SYS_PWROK 5
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2011/06/24 2012/06/02
2011/06/24 2012/06/02
2011/06/24 2012/06/02
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (3/8) DMI,FDI,PM
PCH (3/8) DMI,FDI,PM
PCH (3/8) DMI,FDI,PM
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
E
of
15 52Wednesday, March 13, 2013
15 52Wednesday, March 13, 2013
15 52Wednesday, March 13, 2013
0.1
0.1
0.1
A
B
C
D
E
UMA Panel Backlight ON/OFF
ENBKL28
R612 0_0402_5%@R612 0_04 02_5%@
12
PD 100K at EC side
1 1
2 2
3 3
IGPU_BKLT_ENENBKL
U37D
U37D
PCH_ENVDD22
INVTPWM4 4
IGPU_BKLT_EN
Delete LVDS function
LVDS disable: DATA/Clock/Control can NC VCC_TX_LVDS,VCCA_LVDS connected to GND
CRT disable: DATA/Clock/Control can NC DAC_IREF still need PD VCCADAC connected to +3VS
CRT_IREF
For CRT diable =>Change 1K 0.5% to 5%
1K_0402_5%
1K_0402_5%
R307
R307
12
J47
L_BKLTEN
M45
L_VDD_EN
P45
L_BKLTCTL
T40
L_DDC_CLK
K47
L_DDC_DATA
T45
L_CTRL_CLK
P39
L_CTRL_DATA
AF37
LVD_IBG
AF36
LVD_VBG
AE48
LVD_VREFH
AE47
LVD_VREFL
AK39
LVDSA_CLK#
AK40
LVDSA_CLK
AN48
LVDSA_DATA#0
AM47
LVDSA_DATA#1
AK47
LVDSA_DATA#2
AJ48
LVDSA_DATA#3
AN47
LVDSA_DATA0
AM49
LVDSA_DATA1
AK49
LVDSA_DATA2
AJ47
LVDSA_DATA3
AF40
LVDSB_CLK#
AF39
LVDSB_CLK
AH45
LVDSB_DATA#0
AH47
LVDSB_DATA#1
AF49
LVDSB_DATA#2
AF45
LVDSB_DATA#3
AH43
LVDSB_DATA0
AH49
LVDSB_DATA1
AF47
LVDSB_DATA2
AF43
LVDSB_DATA3
N48
CRT_BLUE
P49
CRT_GREEN
T49
CRT_RED
T39
CRT_DDC_CLK
M40
CRT_DDC_DATA
M47
CRT_HSYNC
M49
CRT_VSYNC
T43
DAC_IREF
T42
CRT_IRTN
COUGARPOINT_FCBGA989~D
COUGARPOINT_FCBGA989~D
HM77@
HM77@
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_STALLN SDVO_STALLP
SDVO_INTN SDVO_INTP
SDVO_CTRLCLK
SDVO_CTRLDATA
DDPB_AUXN DDPB_AUXP
DDPB_HPD
LVDS
LVDS
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN DDPC_AUXP
DDPC_HPD
Digital Display Interface
Digital Display Interface
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN DDPD_AUXP
CRT
CRT
S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO!SA0 0005AGI0
S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO!SA0 0005AGI0
DDPD_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P
DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P
AP43 AP45
AM42 AM40
AP39 AP40
SDVO_CTRLDATA strap pull high at level shift page
P38
SDVO_SCLK
M39
SDVO_SDATA
AT49 AT47 AT40
PCH_DPB_HPD
AV42
PCH_DPB_N0
AV40
PCH_DPB_P0
AV45
PCH_DPB_N1
AV46
PCH_DPB_P1
AU48
PCH_DPB_N2
AU47
PCH_DPB_P2
AV47
PCH_DPB_N3
AV49
PCH_DPB_P3
P46 P42
AP47 AP49 AT38
AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49
M43 M36
AT45 AT43 BH41
BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42
SDVO_SCLK 2 3 SDVO_SDATA 23
PCH_DPB_HPD 23
PCH_DPB_N0 23 PCH_DPB_P0 23 PCH_DPB_N1 23 PCH_DPB_P1 23 PCH_DPB_N2 23 PCH_DPB_P2 23 PCH_DPB_N3 23 PCH_DPB_P3 23
HDMI D2
HDMI D1
HDMI D0
HDMI CLK
4 4
Security Classification
Security Classification
Security Classification
2011/06/24 2012/06/02
2011/06/24 2012/06/02
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
2011/06/24 2012/06/02
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
PCH (4/9) LVDS,CRT,DP,HDMI
PCH (4/9) LVDS,CRT,DP,HDMI
PCH (4/9) LVDS,CRT,DP,HDMI
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
V1JB1 M/B LA-A041P Schematic
16 52Wednesday, Ma rch 13, 2013
16 52Wednesday, Ma rch 13, 2013
16 52Wednesday, Ma rch 13, 2013
E
0.1
0.1
0.1
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