Compal LA-9861P Schematics

CyberForum.ru

A

1 1

B

C

D

E

VFKTA

Rosetta 10FT/10FTG

2 2

LA-9861P REV 0.3 Schematic

Intel Processor (Ivy Bridge/Sandy Bridge)+

3 3

PCH(Panther Point)

2013-01-11 Rev 0.3

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

2012/04/19 2015/04/19

2012/04/19 2015/04/19

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

Cover Page

Cover Page

VFKTA

VFKTA

VFKTA

1 56Thursday, January 17, 2013

1 56Thursday, January 17, 2013

1 56Thursday, January 17, 2013

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D

E

VGA (DDR3)

nVIDIA N14x

page 13,14,15,16,17,18,19,20,21

1 1

PCI-Express Gen3 4X

8GT/s

eDP 1.1 2x

2.7GT/s

LVDS colay eDP Conn.

page 22

2 2

HDMI Conn.

RJ45
Conn.

page 23

RTL8106E & 8111G

PCIe port 1

USB Left

USB20 port 2

page 35

page 35

To sub-board

PCIe Gen1 1x

1.5V 5GT/s

USB20 2x

5V 480MHz

Intel CPU
Ivy Bridge
35W

BGA-1023

31mm*24mm

page 5,6,7,8,9,10

FDI X8

2.7GT/s

DMI X4

5GT/s

Intel PCH
Panther Point

FCBGA-989

25mm*25mm

page 24,25,26,27,28,29,30,31,32

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 1066/1333/1600 MT/s

USB30 2x

5V 5GT/s

USB20 3x

5V 480MHz

USB20 2x

5V 480MHz

PCIe Gen1 1x

1.5V 5GT/s

USB20 2x

5V 480MHz

SATA Gen3 1x

5V 6GHz(600MB/s)

SATA Gen2 1x

5V 3GHz(300MB/s)

USB Right

USB20 port 0,1
USB30 port 1,2

CardReader GL834L

PCIeMini Card WLAN and BT

SATA HDD

SATA ODD

200pin DDRIII-SO-DIMM X2

BANK 0, 1, 2, 3

page 37

page 11,12

Int. Camera

USB port 11

page 22

SATA port 0

page 33

SATA port 2

page 34

USB20 port 8

page 37

PCIe port 2 &USB port 9

page 34

3 3

RTC CKT.

page 24

SPI ROM
(4MB + 2MB)

page 24

Debug Port

page 42

LPC BUS

3.3V 33 MHz

KB9012

page 40

HD Audio

3.3V 24MHz

HDA Codec

ALC259

page 38

DC/DC Interface CKT.

page 42

Power Circuit DC/DC

page 43,44,45,46,47,48,
49,50,51

GCLK

4 4

SLG3NB300VTR

page 34

Touch Pad

Power/B

page 41

To sub-board

A

Int.KBD

page 41page 41

B

CIR

page 41

G-Sensor

page 41

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

LED+LID/B

C

page 41

2012/04/19 2015/04/19

2012/04/19 2015/04/19

2012/04/19 2015/04/19

SPK Conn

page 39

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

JPIO
(HP & MIC)

page 39

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Block Diagram

Block Diagram

Block Diagram

VFKTA

VFKTA

VFKTA

2 56Thursday, January 17, 2013

2 56Thursday, January 17, 2013

2 56Thursday, January 17, 2013

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5

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3

2

1

DESIGN CURRENT 0.1A

B+

D D

RT8243AZQW

C C

VR_ON

B B

ISL95833HRTZ

SUSP#

SY8208DQNC

SYSON

RT8207MZQW

A A

DGPU_PWR_EN

NCP81172MNTWG

5

Ipeak=8.5A, Imax=5.95A, Iocp min=10.2

SUSP#

SY8032ABC

SUSP#

TPS22966DPUR

Ipeak=5A, Imax=3.5A, Iocp min=6.12A

SUSP#

TPS22966DPUR

Ipeak=14.37A, Imax=10.06A, Iocp min=17.24A

VGA_PWROK#

N-CHANNEL

AO3416

VCCP_PWRGOOD

G978F11U

Ipeak=16.66A, Imax=11.66A, Iocp min=20A

0.75VR_ON

SUSP

N-CHANNEL

FDS6676AS

1.5_PWR_EN#

N-CHANNEL

FDS6676AS

Ipeak=50A, Imax=35A, Iocp min=60A

P-CHANNEL

P-CHANNEL

G9191-330T1U

P-CHANNEL

P-CHANNEL

P-CHANNEL

APL3512ABI

P-CHANNEL

4

PCH_PWR_EN#

AO-3413

KB_LED

AO-3413

+5VS

LDO

ODD_EN#

AO-3413

WOWL_EN#

AO-3413

PCH_PWR_EN#

AO-3413

LCD_ENVDD

DGPU_PWR_EN

AO-3413

DESIGN CURRENT 5A

DESIGN CURRENT 2A

DESIGN CURRENT 6A

DESIGN CURRENT 400mA

DESIGN CURRENT 300mA

DESIGN CURRENT 1.6A

DESIGN CURRENT 5A

DESIGN CURRENT 330mA

DESIGN CURRENT 3A

DESIGN CURRENT 6A

DESIGN CURRENT 1.5A

DESIGN CURRENT 0.1A

DESIGN CURRENT 65A

DESIGN CURRENT 40A

DESIGN CURRENT 3A

DESIGN CURRENT 6A

DESIGN CURRENT 2A

DESIGN CURRENT 1.5A

DESIGN CURRENT 2A

DESIGN CURRENT 2A

DESIGN CURRENT 11A

DESIGN CURRENT 30A

+3VL

+5VALW

+5VALW_PCH

+1.8VS

+5VS

+5VS_LED

+3VS_HDP

+5VS_ODD

+3VALW

+3V_LAN

+3V_WLAN

+3VALW_PCH

+3VS

+LCD_VDD

+3VS_DGPU

+CPU_CORE

+GFX_CORE

+1.05VS_VCCP

+1.05VS_DGPU

+VCCSA

+1.5V

+0.75VS

+1.5V_CPU

+1.5VS

+VRAM_1.5VS

+VGA_CORE

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2012/09/24 2013/09/24

2012/09/24 2013/09/24

2012/09/24 2013/09/24

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Power Tree

Power Tree

Power Tree

VFKTA

VFKTA

VFKTA

1

of

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3 61Thursday, January 17, 2013

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+5VALW

+3VALW

B

BTO Option Table

+1.5V

+5VS

+3VS

+1.8VS

+1.5VS

+1.05VS

+0.75VS

+CPU_CORE

+VGA_CORE

+GFX_CORE

+VTT

+VRAM_1.5V S

+3VS_DGPU

+1.05VS_DGPU

Function

description

description

A

Voltage Rails

power
plane

1 1

State

( O MEANS ON X MEANS OFF )

+RTCVCC

B+

+5VL

+3VL

explain

BTO

Function

explain

BTO

C

CPU

Ivy Bridge i3

Ivy Bridge i3 Ivy Bridge i5

CPUI3@ CPUI5@

WOWL

WOWL

WOWL

WOWL@

Ivy Bridge i5

G-SENSOR

G-SENSOR

G-SENSOR

GSENSOR@

w/

ZPODD@

ZPODD

ZPODD

D

w/o

NONZP@

LVDS-eDP

LVDS-eDP

LVDS eDP

LVDS@ IEDP@

Camera & Mic

Camera & Mic

Camera & Mic

CAM@

CAM@EMI@ @CAM@EMI@

E

KB Light

KB Light

KB Light

KBL@

S0

S1

S3

2 2

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

O

O

O

O

O

O

O

O

O

O

O

X

O

O

O

O

O

X

O

O

O

O

X

X

O

X X

X

X X

OO

OO

X

description

explain

BTO

Function

X

description

explain

BTO

EMI@ @EMI@ ESD@ @ESD@ @RF@

Function

Function

PCH SM Bus Address

HEX

0001 0110 bSmart Battery

Address

1010 0000 bA0 H

1010 0100 bA4 H

PowerPower

+3VS

+3VS

+3VS

EC SM Bus2 Address

Device

96 H

1001 0110 bPCH

NVIDIA GPU 1001 1010 b

9E H

40 H

0100 0000 b

Power

+3VS

+3VS

+3VS

3 3

Device

DDR SO-DIMM 0

DDR SO-DIMM 1

WLAN/WIMAX

EC SM Bus1 Address

Device Address Address

+3VL

+3VL USB S&C 14640 35 H 0011 0101 b G-Sensor

HEX HEX

16 H

12 H 0001 0010 bSmart Charger+3VL

description

explain

BTO

KB9012 NPCE885N

GPU

N14M-GL

N14MGL@

9012@ 885@

N14P-GV2

N14P-GV2N14M-GL

N14PGV2@

EMI/ESD/RF part

EMI/ESD/RF part

EMI/ESD/RF part

EC

EC

GCLK@

ISPD

HDMI Logo

HDMI Logo

HDMI45@

GCLK

GCLK non-GCLK

GCLK@EMI@ @GCLK@EMI@

w/ S&M w/o S&M

GCLK

Sleep & Music

Sleep & Music

269@ 259@

non-GCLK

NOGCLK@

CRT

CRT

w/ CRT w/o CRT

CRT@ CRT@EMI@ NOCRT@

Panther Point

HM76R1@

PCH

Dual Rank

HM70HM76

HM70R1@

Red Word: don't mount

Dual Rank

DRANK@

Touch Screen

Touch Screen

Touch Screen

TOUCH@EMI@

VRAM

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

2012/04/19 2015/04/19

2012/04/19 2015/04/19

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Notes List

Notes List

Notes List

VFKTA

VFKTA

VFKTA

4 56Thursday, January 17, 2013

4 56Thursday, January 17, 2013

4 56Thursday, January 17, 2013

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H_PROCHOT#<41>

H_THERMTRIP#<30>

H_PM_SYNC<27>

H_PWRGOOD<30>

+1.5V_CPU

12

RC14

RC14
200_0402_5%

200_0402_5%

B

H_SNB_IVB#<30>

T1 PADT1 PAD

T2 PADT2 PAD

H_PECI<41>

1 2

RC170 130_0402_5%RC170 130_0402_5%

H_SNB_IVB#

TP_SKTOCC#

H_CATERR#

H_PECI

RC159

RC159

1 2

H_PROCHOT#_R

56_0402_5%

56_0402_5%

H_THERMTRIP#

H_PM_SYNC

1 2

H_PWRGOOD_R

@

@

RC183 0_0402_5%

RC183 0_0402_5%

PM_DRAM_PWR GD_RPM _SYS_PWRGD_BUF

BUF_CPU_RST#

UC1B

UC1B

F49

PROC_SELECT#

C57

PROC_DETECT#

C49

CATERR#

A48

PECI

C45

PROCHOT#

D45

THERMTRIP#

C48

PM_SYNC

B46

UNCOREPWRGOOD

BE45

SM_DRAMPWR OK

D44

RESET#

IVY-BRIDGE_BGA1023 <BOM>

IVY-BRIDGE_BGA1023 <BOM>

CPU@

CPU@

A

@

@

12

PM_DRAM_PWR GD_R

CC621000P_0402_50V7K

CC621000P_0402_50V7K

ESD@

ESD@

1 2

@ESD@

@ESD@

1 2

1 1

H_PWRGOOD_R

CC63180P_0402_50V8J

CC63180P_0402_50V8J

H_THERMTRIP#

CC1100P_0402_50V8J

CC1100P_0402_50V8J

by ESD requestion and place near CPU

+1.05VS_VCCP

12

DRAMPWROK

+3VS

DRAMPWROK

12

12

RC44 62_0402_5%RC44 62_0402_5%

RC45 10K_0402_5%RC45 10K_0402_5%

2 2

+3VALW_PCH

RC11 200_0402_5%RC11 200_0402_5%

DRAMPWROK<27>

H_PROCHOT#

H_PWRGOOD

@

@

12

CC701000P_0402_50V7K

CC701000P_0402_50V7K

@

@

12

CC671000P_0402_50V7K

CC671000P_0402_50V7K

@

@

12

CC661000P_0402_50V7K

CC661000P_0402_50V7K

H_PECI

H_PM_SYNC

BUF_CPU_RST#

Please place near JCPU

+3VALW_PCH

@

@

0.1U_0402_10V7K

0.1U_0402_10V7K
CC33

CC33

UC3

UC3

5

74AHC1G09GW_TSSOP5

12

1

B

2

A

74AHC1G09GW_TSSOP5

P

4

PM_SYS_PWRGD_BUF

O

G

3

10K_0402_5%

10K_0402_5%

RC13

RC13

12

C

MISC THERMAL PWR MANAGEMENT

MISC THERMAL PWR MANAGEMENT

CLOCKS

CLOCKS

DDR3

DDR3

JTAG & BPM

JTAG & BPM

DPLL_REF_CLK

DPLL_REF_CLK#

SM_DRAMRST#

MISC

MISC

BCLK

BCLK#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

PRDY#

PREQ#

TCK
TMS

TRST#

TDO

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

D

100 MHz

J3

CLK_CPU_DMI

H2

CLK_CPU_DMI#

120 MHz

AG3

CLK_CPU_EDP

AG1

CLK_CPU_EDP#

AT30

H_DRAMRST#

BF44

SM_RCOMP_0

BE43
BG43

N53
N55

L56
L55
J58

M60

TDI

L59

K58

G58
E55
E59
G55
G59
H60
J59
J61

RC56 140_0402_1%RC56 140_0402_1%

SM_RCOMP_1

RC59 25.5_0402_1%RC59 25.5_0402_1%

SM_RCOMP_2

RC61 200_0402_1%RC61 200_0402_1%

XDP_TCK

XDP_TMS

XDP_TRST#

XDP_TDI

XDP_TDO

Close to CPU side

CLK_CPU_DMI <26>
CLK_CPU_DMI# <26>

CLK_CPU_EDP <26>
CLK_CPU_EDP# <26>

H_DRAMRST# <7>

12
12
12

T3 PAD@T3 PAD@
T4 PAD@T4 PAD@

1 2

RC55 51_0402_5%RC55 51_0402_5%

T6 PAD@T6 PAD@
T7 PAD@T7 PAD@

Stuff RC158&RC157 if do not support eDP

CLK_CPU_EDP#

CLK_CPU_EDP

H_DRAMRST#

by ESD requestion and place near CPU

DDR3 Compensatio n Signals
Layout Note:Plac e these
resistors near P rocessor

H_DRAMRST#

Routed as a sing le daisy chain

E

LVDS@

LVDS@

1 2

RC157 1K_0402_5%

RC157 1K_0402_5%

1 2

RC158 1K_0402_5%

RC158 1K_0402_5%

LVDS@

LVDS@

@ESD@

@ESD@

1 2

CC34 180P_0402_50V8J

CC34 180P_0402_50V8J

@ESD@

@ESD@

1 2

CC35 180P_0402_50V8J

CC35 180P_0402_50V8J

+1.05VS_VCCP

3 3

Buffered Rest to CPU

+3VS

0.1U_0402_10V7K

0.1U_0402_10V7K

1

CC36

CC36

@

PLT_RST# <29,35,36,41>

UC2

UC2

PLT_RST#

4 4

1

OE#

2

IN

3

GND

74AHC1G125GW_SOT353-5

74AHC1G125GW_SOT353-5

A

@

2

5

VCC

4

BUFO_CPU_RST# BUF_CPU_RST#

OUT

+1.05VS_VCCP

12

RC38

RC38
75_0402_5%

75_0402_5%

43_0402_1%

43_0402_1%

1 2

RC35

RC35

B

XDP Connector

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

Issued Date

Issued Date

Issued Date

For power consumption

+5VS +3VS

R1

1A

Compal Secret Data

Compal Secret Data

2012/04/19 2015/04/19

2012/04/19 2015/04/19

2012/04/19 2015/04/19

C

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

R1

1 2

0_0603_5%

0_0603_5%

D

FAN_SPEED1<41>

FAN Control Circuit

+FAN1

12

R2

R2
10K_0402_5%

10K_0402_5%

1

C4

C4

0.01U_0402_25V7K

0.01U_0402_25V7K

@

@

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

JFAN

6

GND

5

GND

4

4

FANPWM<41>

+FAN1

12

D1

D1

BAS16_SOT23-3

BAS16_SOT23-3

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Ivy Bridge_JTAG/XDP/FAN

Ivy Bridge_JTAG/XDP/FAN

Ivy Bridge_JTAG/XDP/FAN

VFKTA

VFKTA

VFKTA

10U_0603_6.3V6M

10U_0603_6.3V6M

E

3
2
1

ACES_50273-0040N-001

ACES_50273-0040N-001

1

C5

C5

2

5 56Thursday, January 17, 2013

5 56Thursday, January 17, 2013

5 56Thursday, January 17, 2013

3
2
1

of

of

of

@JFAN

@

0.3

0.3

0.3

CyberForum.ru

A

B

C

D

E

+1.05VS_VCCP

RC1

RC1

24.9_0402_1%

UC1A

UC1A

1 1

2 2

+1.05VS_VCCP

eDP_COMP signals should be
shorted near balls and
routed with typical
impedance <25m ohm

3 3

+1.05VS_VCCP

CPU_EDP_HPD<22>

4 4

2

G

G

IEDP@

IEDP@

RC9

RC9
100K_0402_5%

100K_0402_5%

1 2

DMI_PTX_CRX_N0<27>
DMI_PTX_CRX_N1<27>
DMI_PTX_CRX_N2<27>
DMI_PTX_CRX_N3<27>

DMI_PTX_CRX_P0<27>
DMI_PTX_CRX_P1<27>
DMI_PTX_CRX_P2<27>
DMI_PTX_CRX_P3<27>

DMI_CTX_PRX_N0<27>
DMI_CTX_PRX_N1<27>
DMI_CTX_PRX_N2<27>
DMI_CTX_PRX_N3<27>

DMI_CTX_PRX_P0<27>
DMI_CTX_PRX_P1<27>
DMI_CTX_PRX_P2<27>
DMI_CTX_PRX_P3<27>

FDI_CTX_PRX_N0<27>
FDI_CTX_PRX_N1<27>
FDI_CTX_PRX_N2<27>
FDI_CTX_PRX_N3<27>
FDI_CTX_PRX_N4<27>
FDI_CTX_PRX_N5<27>
FDI_CTX_PRX_N6<27>
FDI_CTX_PRX_N7<27>

FDI_CTX_PRX_P0<27>
FDI_CTX_PRX_P1<27>
FDI_CTX_PRX_P2<27>
FDI_CTX_PRX_P3<27>
FDI_CTX_PRX_P4<27>
FDI_CTX_PRX_P5<27>
FDI_CTX_PRX_P6<27>
FDI_CTX_PRX_P7<27>

FDI_FSYNC0<27>
FDI_FSYNC1<27>

FDI_INT<27>

FDI_LSYNC0<27>
FDI_LSYNC1<27>

1 2

RC2 24.9_0402_1%RC2 24.9_0402_1%

RC10

RC10
1K_0402_5%

1K_0402_5%

1 2

H_EDP_HPD#

13

D

D

2N7002_SOT23-3

2N7002_SOT23-3
QC1

QC1

IEDP@

IEDP@

S

S

H_EDP_AUXN<22>
H_EDP_AUXP<22>

H_EDP_TXP0<22>
H_EDP_TXP1<22>

H_EDP_TXN0<22>
H_EDP_TXN1<22>

DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3

DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_FSYNC0
FDI_FSYNC1

FDI_INT

FDI_LSYNC0
FDI_LSYNC1

EDP_COMP

H_EDP_HPD#

M2

DMI_RX#[0]

P6

DMI_RX#[1]

P1

DMI_RX#[2]

P10

DMI_RX#[3]

N3

DMI_RX[0]

P7

DMI_RX[1]

P3

DMI_RX[2]

P11

DMI_RX[3]

K1

DMI_TX#[0]

M8

DMI_TX#[1]

N4

DMI_TX#[2]

R2

DMI_TX#[3]

K3

DMI_TX[0]

M7

DMI_TX[1]

P4

DMI_TX[2]

T3

DMI_TX[3]

U7

FDI0_TX#[0]

W11

FDI0_TX#[1]

W1

FDI0_TX#[2]

AA6

FDI0_TX#[3]

W6

FDI1_TX#[0]

V4

FDI1_TX#[1]

Y2

FDI1_TX#[2]

AC9

FDI1_TX#[3]

U6

FDI0_TX[0]

W10

FDI0_TX[1]

W3

FDI0_TX[2]

AA7

FDI0_TX[3]

W7

FDI1_TX[0]

T4

FDI1_TX[1]

AA3

FDI1_TX[2]

AC8

FDI1_TX[3]

AA11

FDI0_FSYNC

AC12

FDI1_FSYNC

U11

FDI_INT

AA10

FDI0_LSYNC

AG8

FDI1_LSYNC

AF3

eDP_COMPIO

AD2

eDP_ICOMPO

AG11

eDP_HPD#

AG4

eDP_AUX#

AF4

eDP_AUX

AC3

eDP_TX#[0]

AC4

eDP_TX#[1]

AE11

eDP_TX#[2]

AE7

eDP_TX#[3]

AC1

eDP_TX[0]

AA4

eDP_TX[1]

AE10

eDP_TX[2]

AE6

eDP_TX[3]

IVY-BRIDGE_BGA1023 <BOM>

IVY-BRIDGE_BGA1023 <BOM>

CPU@

CPU@

DMI Intel(R) FDI

DMI Intel(R) FDI

eDP

eDP

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PCI EXPRESS -- GRAPHICS

PCI EXPRESS -- GRAPHICS

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]

PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

G3
G1
G4

H22

PCIE_GTX_C_CRX_N0

J21

PCIE_GTX_C_CRX_N1

B22

PCIE_GTX_C_CRX_N2

D21

PCIE_GTX_C_CRX_N3

A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7

K22

PCIE_GTX_C_CRX_P0

K19

PCIE_GTX_C_CRX_P1

C21

PCIE_GTX_C_CRX_P2

D19

PCIE_GTX_C_CRX_P3

C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6

G22

PCIE_CTX_GRX_N0

C23

PCIE_CTX_GRX_N1

D23

PCIE_CTX_GRX_N2

F21

PCIE_CTX_GRX_N3

H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4

F22

PCIE_CTX_GRX_P0

A23

PCIE_CTX_GRX_P1

D24

PCIE_CTX_GRX_P2

E21

PCIE_CTX_GRX_P3

G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4

PEG_COMP

24.9_0402_1%

CC8 0.22U_0402_16V7KOPT@CC8 0.22U_0402_1 6V7KOPT@
CC11 0.22U_0402_16V7KOPT@C C11 0.22U_0402_16V7KOPT@
CC16 0.22U_0402_16V7KOPT@C C16 0.22U_0402_16V7KOPT@
CC20 0.22U_0402_16V7KOPT@C C20 0.22U_0402_16V7KOPT@

CC10 0.22U_0402_16V7KOPT@C C10 0.22U_0402_16V7KOPT@
CC5 0.22U_0402_16V7KOPT@CC5 0.22U_0402_1 6V7KOPT@
CC6 0.22U_0402_16V7KOPT@CC6 0.22U_0402_1 6V7KOPT@
CC7 0.22U_0402_16V7KOPT@CC7 0.22U_0402_1 6V7KOPT@

IVY Bridge

SANDY Bridge Gen1/Gen2 180 nF~265 nF

NV N13X Gen1/2/3 Suggest 220 nF

PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical

12

impedance = 43 m ohm (4 mils)
PEG_ICOMPO signals should be routed with ­max length = 500 mils

- typical impedance = 14.5 m ohm (12 mils)

PCIE_GTX_C_CRX_N[0..15] <13>

PCIE_GTX_C_CRX_P[0..15] <13>

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_N3

PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_P3

PEG DG suggest AC cap

Gen1/Gen2

Gen3

75 nF~265 nF

180 nF~265 nF

PCIE_CTX_C_GRX_N[0..15] <13>

PCIE_CTX_C_GRX_P[0..15] <13>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

2012/04/19 2015/04/19

2012/04/19 2015/04/19

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Ivy Bridge_DMI/PEG/FDI

Ivy Bridge_DMI/PEG/FDI

Ivy Bridge_DMI/PEG/FDI

VFKTA

VFKTA

VFKTA

6 56Thursday, January 17, 2013

6 56Thursday, January 17, 2013

6 56Thursday, January 17, 2013

E

0.3

0.3

0.3

of

of

of

CyberForum.ru

A

DDR_A_D[0..63]<11>

UC1C

UC1C

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6

1 1

2 2

DDR_A_BS0<11>
DDR_A_BS1<11>

3 3

DDR_A_BS2<11>

DDR_A_CAS#<11>
DDR_A_RAS#<11>

DDR_A_WE#<11>

DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#

AG6

AP11

AJ10

AR11

AU6

AR6

AT13

AU13

BC7

BA13
BB11

AY13
AV14
AR14

AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43

AW48

BC48
BC45
AR45

AT48

AY48
BA49
AV49
BB51

AY53
BB49
AU49
BA53
BB55
BA55
AV56
AP50
AP53
AV54

AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56

BD37

BF36
BA28

BE39
BD39

AT41

SA_DQ[0]

AJ6

SA_DQ[1]
SA_DQ[2]

AL6

SA_DQ[3]
SA_DQ[4]

AJ8

SA_DQ[5]

AL8

SA_DQ[6]

AL7

SA_DQ[7]
SA_DQ[8]

AP6

SA_DQ[9]
SA_DQ[10]

AV9

SA_DQ[11]
SA_DQ[12]

AP8

SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]

BB7

SA_DQ[17]
SA_DQ[18]
SA_DQ[19]

BA7

SA_DQ[20]

BA9

SA_DQ[21]

BB9

SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

B

SA_CK[0]
SA_CK#[0]
SA_CKE[0]

SA_CK[1]
SA_CK#[1]
SA_CKE[1]

SA_CS#[0]
SA_CS#[1]

SA_ODT[0]
SA_ODT[1]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

DDR_B_D[0..63]<12>

AU36

DDRA_CLK0

AV36

DDRA_CLK0#

AY26

DDRA_CKE0

AT40

DDRA_CLK1 DDRB_ CLK1

AU40

DDRA_CLK1# DDRB_ CLK1#

BB26

DDRA_CKE1 DDRB_CKE1

BB40

DDRA_SCS0# DDRB_SCS0#

BC41

DDRA_SCS1#

AY40

DDRA_ODT0 DDRB_ODT0

BA41

DDRA_ODT1

AL11

DDR_A_DQS#0

AR8

DDR_A_DQS#1

AV11

DDR_A_DQS#2

AT17

DDR_A_DQS#3

AV45

DDR_A_DQS#4

AY51

DDR_A_DQS#5

AT55

DDR_A_DQS#6

AK55

DDR_A_DQS#7

AJ11

DDR_A_DQS0

AR10

DDR_A_DQS1

AY11

DDR_A_DQS2

AU17

DDR_A_DQS3

AW45

DDR_A_DQS4

AV51

DDR_A_DQS5

AT56

DDR_A_DQS6

AK54

DDR_A_DQS7

BG35

DDR_A_MA0

BB34

DDR_A_MA1

BE35

DDR_A_MA2

BD35

DDR_A_MA3

AT34

DDR_A_MA4

AU34

DDR_A_MA5

BB32

DDR_A_MA6

AT32

DDR_A_MA7

AY32

DDR_A_MA8

AV32

DDR_A_MA9

BE37

DDR_A_MA10

BA30

DDR_A_MA11

BC30

DDR_A_MA12

AW41

DDR_A_MA13

AY28

DDR_A_MA14

AU26

DDR_A_MA15

DDRA_CLK0 <11> DDRB_CLK0 <12>
DDRA_CLK0# <11>
DDRA_CKE0 <11> DDRB_CKE0 <12>

DDRA_CLK1 <11>
DDRA_CLK1# <11> DDRB_CLK1# <12>
DDRA_CKE1 <11>

DDRA_SCS0# <11>
DDRA_SCS1# <11> DDRB_SCS1# <12>

DDRA_ODT0 <11> DDRB_ODT0 <12>
DDRA_ODT1 <11> DDRB_ODT1 <12>

DDR_A_DQS#[0..7] <11>

DDR_A_DQS[0..7] <11>

DDR_A_MA[0..15] <11>

C

UC1D

UC1D

BD13
BF12

BD10
BD14
BE13
BF16
BE17
BE18
BE21
BE14
BG14
BG18
BF19
BD50
BF48
BD53
BF52
BD49
BE49
BD54
BE53
BF56
BE57
BC59
AY60
BE54
BG54

BA58
AW59
AW58

AU58

AN61

AN59

AU59

AU61

AN58

AR58

AK58

AL58

AG58

AG59
AM60

AL59

AF61

AH60

BG39

BD42

AT22

AV43

BF40

BD45

AL4
AL1
AN3
AR4
AK4
AK3
AN4
AR1
AU4
AT2
AV4
BA4
AU3
AR3
AY2
BA3
BE9
BD9

BF8

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_BS0<12>
DDR_B_BS1<12>
DDR_B_BS2<12>

DDR_B_CAS#<12>
DDR_B_RAS#<12>

DDR_B_WE#<12>

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#

D

BA34
AY34
AR22

BA36
BB36
BF27

BE41
BE47

AT43
BG47

AL3
AV3
BG11
BD17
BG51
BA59
AT60
AK59

AM2
AV1
BE11
BD18
BE51
BA61
AR59
AK61

BF32
BE33
BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
BD46
AT26
AU22

DDRB_CLK0
DDRB_CLK0#
DDRB_CKE0

DDRB_SCS1#

DDRB_ODT1

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8

DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

SB_CK[0]
SB_CK#[0]
SB_CKE[0]

SB_CK[1]
SB_CK#[1]
SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

SB_MA[0]

SB_MA[1]

SB_MA[2]

SB_MA[3]

SB_MA[4]

SB_MA[5]

SB_MA[6]

SB_MA[7]

SB_MA[8]

SB_MA[9]

SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

E

DDRB_CLK0# <12>

DDRB_CLK1 <12>

DDRB_CKE1 <12>

DDRB_SCS0# <12>

DDR_B_DQS#[0..7] <12>

DDR_B_DQS[0..7] <12>

DDR_B_MA[0..15] <12>

IVY-BRIDGE_BGA1023 <BOM>

IVY-BRIDGE_BGA1023 <BOM>

CPU@

CPU@

+1.5V

12

RC76

RC76

1K_0402_5%

1K_0402_5%

QC3

QC3

D

S

D

S

13

H_DRAMRST#<5>

RC78

RC78

4.99K_0402_1%

4.99K_0402_1%

4 4

DRAMRST_CNTRL_PC H<26,9>

1 2

RC73 0_0402_5%RC73 0_0402_5%

A

1 2

DRAMRST_CNTRL

BSS138 1N SOT23-3

BSS138 1N SOT23-3

G

G

2

1

CC37

CC37

0.047U_0402_25V6K

0.047U_0402_25V6K

2

DDR3_DRAMRST#_RH_DRAMRST#

B

RC77

RC77
1K_0402_5%

1K_0402_5%

1 2

SM_DRAMRST# <11,12>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

2012/04/19 2015/04/19

2012/04/19 2015/04/19

IVY-BRIDGE_BGA1023 <BOM>

IVY-BRIDGE_BGA1023 <BOM>

CPU@

CPU@

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Ivy Bridge_DDR3

Ivy Bridge_DDR3

Ivy Bridge_DDR3

VFKTA

VFKTA

VFKTA

7 56Thursday, January 17, 2013

7 56Thursday, January 17, 2013

7 56Thursday, January 17, 2013

E

of

of

of

0.3

0.3

0.3

CyberForum.ru

A

B

C

D

E

+CPU_CORE +1.05VS_VCCP

1 1

2 2

3 3

UC1F

UC1F

A26

VCC[1]

A29

VCC[2]

A31

VCC[3]

A34

VCC[4]

A35

VCC[5]

A38

VCC[6]

A39

VCC[7]

A42

VCC[8]

C26

VCC[9]

C27

VCC[10]

C32

VCC[11]

C34

VCC[12]

C37

VCC[13]

C39

VCC[14]

C42

VCC[15]

D27

VCC[16]

D32

VCC[17]

D34

VCC[18]

D37

VCC[19]

D39

VCC[20]

D42

VCC[21]

E26

VCC[22]

E28

VCC[23]

E32

VCC[24]

E34

VCC[25]

E37

VCC[26]

E38

VCC[27]

F25

VCC[28]

F26

VCC[29]

F28

VCC[30]

F32

VCC[31]

F34

VCC[32]

F37

VCC[33]

F38

VCC[34]

F42

VCC[35]

G42

VCC[36]

H25

VCC[37]

H26

VCC[38]

H28

VCC[39]

H29

VCC[40]

H32

VCC[41]

H34

VCC[42]

H35

VCC[43]

H37

VCC[44]

H38

VCC[45]

H40

VCC[46]

J25

VCC[47]

J26

VCC[48]

J28

VCC[49]

J29

VCC[50]

J32

VCC[51]

J34

VCC[52]

J35

VCC[53]

J37

VCC[54]

J38

VCC[55]

J40

VCC[56]

J42

VCC[57]

K26

VCC[58]

K27

VCC[59]

K29

VCC[60]

K32

VCC[61]

K34

VCC[62]

K35

VCC[63]

K37

VCC[64]

K39

VCC[66]

K42

VCC[67]

L25

VCC[68]

L28

VCC[69]

L33

VCC[70]

L36

VCC[71]

L40

VCC[72]

N26

VCC[73]

N30

VCC[74]

N34

VCC[75]

N38

VCC[76]

POWER

POWER

CORE SUPPLY

CORE SUPPLY

8.5A33A

AF46

VCCIO[1]

AG48

VCCIO[3]

AG50

VCCIO[4]

AG51

VCCIO[5]

AJ17

VCCIO[6]

AJ21

VCCIO[7]

AJ25

VCCIO[8]

AJ43

VCCIO[9]

AJ47

VCCIO[10]

AK50

VCCIO[11]

AK51

VCCIO[12]

AL14

VCCIO[13]

AL15

VCCIO[14]

AL16

VCCIO[15]

AL20

VCCIO[16]

AL22

VCCIO[17]

AL26

VCCIO[18]

AL45

VCCIO[19]

AL48

VCCIO[20]

AM16

VCCIO[21]

AM17

VCCIO[22]

AM21

VCCIO[23]

AM43

VCCIO[24]

AM47

VCCIO[25]

AN20

VCCIO[26]

AN42

VCCIO[27]

AN45

VCCIO[28]

AN48

VCCIO[29]

AA14

VCCIO[30]

AA15

VCCIO[31]

AB17

VCCIO[32]
VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]

VCCIO50
VCCIO51

1mA

VCCIO_SEL

VCCPQE[1]
VCCPQE[2]

VIDALERT#

VIDSCLK

VIDSOUT

AB20
AC13
AD16
AD18
AD21
AE14
AE15
AF16
AF18
AF20
AG15
AG16
AG17
AG20
AG21
AJ14
AJ15

+1.05VS_VCCP

W16
W17

BC22

+1.05VS_VCCP

AM25
AN22

A44

H_CPU_SVIDALRT#

B43
C44

PEG IO AND DDR IO

PEG IO AND DDR IO

RAILS

RAILS

For DDR

For PEG

1

CC71

CC71
1U_0402_6.3V6K

1U_0402_6.3V6K

2

+1.05VS_VCCP

1

1

CC17

2

ESD@ CC17

ESD@

100P_0402_50V8J

100P_0402_50V8J

1

CC18

CC19

2

2

ESD@ CC18

ESD@

ESD@ CC19

ESD@

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

by ESD requestion and place near CPU

+1.05VS_VCCP+1.05VS_VCCP

12

RC91

RC91
130_0402_5%

130_0402_5%

1 2

RC90 43_0402_1%RC90 43_0402_1%

+CPU_CORE

12

RC89

RC89
75_0402_5%

75_0402_5%

VR_SVID_ALRT# <5 1>
VR_SVID_CLK <51>
VR_SVID_DAT <51>

Pull high resistor on VR side

RC93

RC93
100_0402_1%

100_0402_1%

Issued Date

Issued Date

Issued Date

1 2

12

RC97

RC97
100_0402_1%

100_0402_1%

Close to CPU

C

VCCSENSE <51>
VSSSENSE <51>

Compal Secret Data

Compal Secret Data

2012/04/19 2015/04/19

2012/04/19 2015/04/19

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Ivy Bridge_POWER-1

Ivy Bridge_POWER-1

Ivy Bridge_POWER-1

VFKTA

VFKTA

VFKTA

8 56Thursday, January 17, 2013

8 56Thursday, January 17, 2013

8 56Thursday, January 17, 2013

E

of

of

of

0.3

0.3

0.3

VCC_SENSE
VSS_SENSE

4 4

IVY-BRIDGE_BGA1023 <BOM>

IVY-BRIDGE_BGA1023 <BOM>

CPU@

CPU@

A

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID QUIET

SENSE LINES SVID QUIET

B

F43
G43

AN16
AN17

Close to CPU

VCCIO_SENSE

12

RC96

RC96
10_0402_1%

10_0402_1%

VCCIO_SENSE <49>

12

RC98

RC98
10_0402_1%

10_0402_1%

+1.05VS_VCCP

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

CyberForum.ru

A

B

C

D

E

+GFX_CORE

UC1G

UC1G

29A

AA46

VAXG[1]

AB47

VAXG[2]

AB50

VAXG[3]

AB51

1 1

2 2

+GFX_CORE

12

RC105

RC105
100_0402_1%

100_0402_1%

Close to CPU

CC59

CC59

CC41

CC41

2

1

1

2

10U_0603_6.3V6M

10U_0603_6.3V6M

VCC_AXG_SENSE
VSS_AXG_SENSE

1 2

+1.8VS_VCCPLL

CC60

CC60

1

2

CC43

CC43

2

1

10U_0603_6.3V6M

10U_0603_6.3V6M

RC106

RC106

100_0402_1%

100_0402_1%

1

CC61

@ CC61

@

1U_0402_6.3V6K

1U_0402_6.3V6K

2

1U_0402_6.3V6K

1U_0402_6.3V6K

VCC_AXG_SENSE<51>
VSS_AXG_SENSE<51>

3 3

VCCPLL Decoupling:
1X 330U (6m ohm), 1X 10U, 2x1U

+1.8VS

Reserve for power consumption
Remove on PVT phase

RC119 0_0805_5%R C119 0_0805_5%

+VCCSA

CC44

CC44

12

@

@

47U_0805_6.3V6M

47U_0805_6.3V6M

1 2

10U_0603_6.3V6M

10U_0603_6.3V6M

CC40

CC40

12

@

@

47U_0805_6.3V6M

47U_0805_6.3V6M

CC42

CC42

2

1

Place TOP IN BGA

10U_0603_6.3V6M

10U_0603_6.3V6M

Place BOT OUT BGA

CC75

CC77

CC77

1

4 4

2

+VCCSA Decoupling:

CC75

CC74

CC74

CC73

CC76

CC76

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

CC73

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

VAXG[4]

AB52

VAXG[5]

AB53

VAXG[6]

AB55

VAXG[7]

AB56

VAXG[8]

AB58

VAXG[9]

AB59

VAXG[10]

AC61

VAXG[11]

AD47

VAXG[12]

AD48

VAXG[13]

AD50

VAXG[14]

AD51

VAXG[15]

AD52

VAXG[16]

AD53

VAXG[17]

AD55

VAXG[18]

AD56

VAXG[19]

AD58

VAXG[20]

AD59

VAXG[21]

AE46

VAXG[22]

N45

VAXG[23]

P47

VAXG[24]

P48

VAXG[25]

P50

VAXG[26]

P51

VAXG[27]

P52

VAXG[28]

P53

VAXG[29]

P55

VAXG[30]

P56

VAXG[31]

P61

VAXG[32]

T48

VAXG[33]

T58

VAXG[34]

T59

VAXG[35]

T61

VAXG[36]

U46

VAXG[37]

V47

VAXG[38]

V48

VAXG[39]

V50

VAXG[40]

V51

VAXG[41]

V52

VAXG[42]

V53

VAXG[43]

V55

VAXG[44]

V56

VAXG[45]

V58

VAXG[46]

V59

VAXG[47]

W50

VAXG[48]

W51

VAXG[49]

W52

VAXG[50]

W53

VAXG[51]

W55

VAXG[52]

W56

VAXG[53]

W61

VAXG[54]

Y48

VAXG[55]

Y61

VAXG[56]

F45

VAXG_SENSE

G45

VSSAXG_SENSE

1.2A

BB3

VCCPLL[1]

BC1

VCCPLL[2]

BC4

VCCPLL[3]

6A

L17

VCCSA[1]

L21

VCCSA[2]

N16

VCCSA[3]

N20

VCCSA[4]

N22

VCCSA[5]

P17

VCCSA[6]

P20

VCCSA[7]

R16

VCCSA[8]

R18

VCCSA[9]

R21

VCCSA[10]

U15

VCCSA[11]

V16

VCCSA[12]

V17

VCCSA[13]

V18

VCCSA[14]

V21

VCCSA[15]

W20

VCCSA[16]

IVY-BRIDGE_BGA1023 <BOM>

IVY-BRIDGE_BGA1023 <BOM>

CPU@

CPU@

1U_0402_6.3V6K

1U_0402_6.3V6K

POWER

POWER

VREF

VREF

DDR3 - 1.5V RAILS

DDR3 - 1.5V RAILS

GRAPHICS

GRAPHICS

SENSE

LINES

SENSE

LINES

1.8V RAIL

1.8V RAIL

SA RAIL

SA RAIL

VCCSA VID

VCCSA VID

SM_VREF

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

VDDQ[1]
VDDQ[2]
VDDQ[3]
VDDQ[4]
VDDQ[5]
VDDQ[6]
VDDQ[7]
VDDQ[8]

VDDQ[9]
VDDQ[10]
VDDQ[11]
VDDQ[12]
VDDQ[13]
VDDQ[14]
VDDQ[15]
VDDQ[16]
VDDQ[17]
VDDQ[18]
VDDQ[19]
VDDQ[20]
VDDQ[21]
VDDQ[22]
VDDQ[23]
VDDQ[24]
VDDQ[25]
VDDQ[26]

1mA

VCCDQ[1]
VCCDQ[2]

QUIET RAILS

QUIET RAILS

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

SENSE LINES

SENSE LINES

VCCSA_VID[0]
VCCSA_VID[1]

lines

lines

5A

+V_SM_VREF should
have 20 mil trace width

AY43

BE7
BG7

AJ28
AJ33
AJ36
AJ40
AL30
AL34
AL38
AL42
AM33
AM36
AM40
AN30
AN34
AN38
AR26
AR28
AR30
AR32
AR34
AR36
AR40
AV41
AW26
BA40
BB28
BG33

AM28
AN26

BC43
BA43

U10

D48
D49

+V_SM_VREF

+VREF_DQA_M3
+VREF_DQB_M3

CC57

CC57

2

1

CC82

CC82

1

2

+1.5V_CPU

1

CC72

CC72
1U_0402_6.3V6K

1U_0402_6.3V6K

2

H_VCCSA_VID0
H_VCCSA_VID1

Please kindly ch eck whether
there is pull-do wn resister
in PWR-side or H W-side

CC65

CC65

1

2

0.1U_0402_10V7K

0.1U_0402_10V7K

Place TOP IN BGA

CC52

CC52

CC51

CC51

2

2

1

1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CC80

CC80

CC81

CC81

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

H_VCCSA_VID0 <50>
H_VCCSA_VID1 <50>

RC120 1K_0402_0.5%RC120 1K_0402_0.5%

RC109 1K_0402_0.5%RC109 1K_0402_0.5%

CC55

CC55

2

1

10U_0603_6.3V6M

10U_0603_6.3V6M

Place BOT OUT BGA

CC79

CC79

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

+1.5V_CPU

1 2

1 2

+1.5V_CPU

CC50

CC50

CC53

12

@

@

47U_0805_6.3V6M

47U_0805_6.3V6M

CC86

CC86

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

VCCSA_VID1

CC85

CC85

1

2

12

CC53

@

@

0

1

0

47U_0805_6.3V6M

47U_0805_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

CC54

CC54

2

1

10U_0603_6.3V6M

10U_0603_6.3V6M

CC78

CC78

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

VCCSA_VID0

CC56

CC56

2

1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CC87

CC87

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0

0

1

1 1

+1.5V_CPU +1.5V

1 2

CC46 0.1U_0402_10V7K@CC46 0.1U_0402_10V7K@

1 2

CC47 0.1U_0402_10V7K@CC47 0.1U_0402_10V7K@

1 2

CC48 0.1U_0402_10V7K@CC48 0.1U_0402_10V7K@

1 2

CC45 0.1U_0402_10V7K@CC45 0.1U_0402_10V7K@

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

Intel DDR Vref M3

BSS138 1N SOT23-3

BSS138 1N SOT23-3

+VREF_DQA_M3

+VREF_DQB_M3

BSS138 1N SOT23-3

BSS138 1N SOT23-3

+1.5V_CPU Decoupling:
2X 47U(MLCC), 6X 10U, 8X 1U

+VCCSA

0.90 V

0.80 V

0.725 V

0.675 V

Vgs=10V,Id=14.5A ,Rds=6mohm

RC203

RC203

470_0805_5%

470_0805_5%

1 2
34

SUSP

5

QC5B

QC5B

For Sandy Bridge

1

CC68

CC68
10U_0603_6.3V6M@

10U_0603_6.3V6M@

2

0.1U_0402_25V6

0.1U_0402_25V6

CC69

CC69

S

S

G

G

2

G

G

2

S

S

1
2
3
4

FDS6676AS_SO8

FDS6676AS_SO8

1

2

QC7

QC7

D

D

13

13

D

D

QC8

QC8

PJ1

@ PJ1

@

2

JUMP_43X39

JUMP_43X39

QC4

QC4

S
S
S
G

RUN_ON_CPU1.5VS3

12

RC205

RC205
820K_0402_5%

820K_0402_5%

+VREF_DQA

DRAMRST_CNTRL_PC H <26,7>

+VREF_DQB

+1.5VS+1.5V_CPU

112

+1.5V

8

D

7

D

6

D

5

D

@

@

1 2

CC83

CC83

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

RC204

RC204

1 2

220K_0402_5%

220K_0402_5%

61

QC5A

QC5A

2

SUSP

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

B+

SUSP <43>

2X 47U(MLCC), 3X 10U, 5X 1U

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

2012/04/19 2015/04/19

2012/04/19 2015/04/19

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Ivy Bridge_POWER-2

Ivy Bridge_POWER-2

Ivy Bridge_POWER-2

VFKTA

VFKTA

VFKTA

9 56Thursday, January 17, 2013

9 56Thursday, January 17, 2013

9 56Thursday, January 17, 2013

E

0.3

0.3

0.3

of

of

of

CyberForum.ru

VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]

B

VSS

VSS

VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11

NCTF

NCTF

VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14

M4
M58
M6
N1
N17
N21
N25
N28
N33
N36
N40
N43
N47
N48
N51
N52
N56
N61
P14
P16
P18
P21
P58
P59
P9
R17
R20
R4
R46
T1
T47
T50
T51
T52
T53
T55
T56
U13
U8
V20
V61
W13
W15
W18
W21
W46
W8
Y4
Y47
Y58
Y59
G48

A5
A57
BC61
BD3
BD59
BE4
BE58
BG5
BG57
C3
C58
D59
E1
E61

T89 PAD@T89 PAD@

A

UC1H

UC1H

A13

VSS[1]

A17

VSS[2]

A21

VSS[3]

A25

VSS[4]

A28

VSS[5]

A33

VSS[6]

A37

VSS[7]

A40

VSS[8]

A45

AA13
AA50
AA51
AA52
AA53
AA55
AA56

AB16
AB18
AB21
AB48
AB61
AC10
AC14
AC46

AC6
AD17
AD20

AD4
AD61
AE13

AE8

AF1
AF17
AF21
AF47
AF48
AF50
AF51
AF52
AF53
AF55
AF56
AF58
AF59
AG10
AG14
AG18
AG47
AG52
AG61

AG7

AH4
AH58

AJ13
AJ16
AJ20
AJ22
AJ26
AJ30
AJ34
AJ38
AJ42
AJ45
AJ48

AK1
AK52

AL10
AL13
AL17
AL21
AL25
AL28
AL33
AL36
AL40
AL43
AL47

AL61
AM13
AM20
AM22
AM26
AM30
AM34

VSS[9]

A49

VSS[10]

A53

VSS[11]

A9

VSS[12]

AA1

VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]

AA8

VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]

AJ7

VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]

VSS

VSS

1 1

2 2

3 3

VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]

AM38
AM4
AM42
AM45
AM48
AM58
AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54
AP10
AP51
AP55
AP7
AR13
AR17
AR21
AR41
AR48
AR61
AR7
AT14
AT19
AT36
AT4
AT45
AT52
AT58
AU1
AU11
AU28
AU32
AU51
AU7
AV17
AV21
AV22
AV34
AV40
AV48
AV55
AW13
AW43
AW61
AW7
AY14
AY19
AY30
AY36
AY4
AY41
AY45
AY49
AY55
AY58
AY9
BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53
BC13
BC5
BC57
BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44
BD48
BD52
BD56
BD8
BE5
BG13

UC1I

UC1I

BG17
BG21
BG24
BG28
BG37
BG41
BG45
BG49
BG53

BG9

C29
C35
C40
D10
D14
D18
D22
D26
D29
D35

D4
D40
D43
D46
D50
D54
D58

D6
E25
E29

E3
E35
E40
F13
F15
F19
F29
F35
F40
F55
G51

G6
G61
H10
H14
H17
H21

H4
H53
H58

J1
J49
J55

K11
K21
K51

K8
L16
L20
L22
L26
L30
L34
L38
L43
L48
L61

M11
M15

IVY-BRIDGE_BGA1023 <BOM>

IVY-BRIDGE_BGA1023 <BOM>

CPU@

CPU@

C

UC1E

UC1E

B50

CFG0

CFG2

CFG4
CFG5
CFG6
CFG7

@

T87PAD@T87PAD

CFG[0]

C51

CFG[1]

B54

CFG[2]

D53

CFG[3]

A51

CFG[4]

C53

CFG[5]

C55

CFG[6]

H49

CFG[7]

A55

CFG[8]

H51

CFG[9]

K49

CFG[10]

K53

CFG[11]

F53

CFG[12]

G53

CFG[13]

L51

CFG[14]

F51

CFG[15]

D52

CFG[16]

L53

CFG[17]

H43

VCC_VAL_SENSE

K43

VSS_VAL_SENSE

H45

VAXG_VAL_SENSE

K45

VSSAXG_VAL_SENSE

F48

VCC_DIE_SENSE

H48

RSVD6

K48

RSVD7

BA19

RSVD8

AV19

RSVD9

AT21

RSVD10

BB21

RSVD11

BB19

RSVD12

AY21

RSVD13

BA22

RSVD14

AY22

RSVD15

AU19

RSVD16

AU21

RSVD17

BD21

RSVD18

BD22

RSVD19

BD25

RSVD20

BD26

RSVD21

BG22

RSVD22

BE22

RSVD23

BG26

RSVD24

BE26

RSVD25

BF23

RSVD26

BE24

RSVD27

IVY-BRIDGE_BGA1023 <BOM>

IVY-BRIDGE_BGA1023 <BOM>

CPU@

CPU@

RESERVED

RESERVED

These pins are for s older joi nt
reliabilit y and non- critical to
function. For BGA on ly.

DC_TEST_A4
DC_TEST_C4
DC_TEST_D3
DC_TEST_D1

DC_TEST_A58
DC_TEST_A59
DC_TEST_C59
DC_TEST_A61
DC_TEST_C61

DC_TEST_D61
DC_TEST_BD61
DC_TEST_BE61
DC_TEST_BE59

DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58

DC_TEST_BG4
DC_TEST_BG3
DC_TEST_BE3
DC_TEST_BG1
DC_TEST_BE1
DC_TEST_BD1

BCLK_ITP

BCLK_ITP#

RSVD30
RSVD31
RSVD32
RSVD33

RSVD34
RSVD35
RSVD36
RSVD37
RSVD38

RSVD39
RSVD40

RSVD41
RSVD42
RSVD43
RSVD44

RSVD45

D

N59
N58

N42
L42
L45
L47

M13
M14
U14
W14
P13

AT49
K24

AH2
AG13
AM14
AM15

N50

A4
C4
D3

DC_TEST_C4_D3

D1
A58
A59
C59

DC_TEST_A59_C59

A61
C61

DC_TEST_A61_C61

D61
BD61
BE61
BE59

DC_TEST_BE61_BE59

BG61
BG59

DC_TEST_BG61_BG59

BG58
BG4
BG3
BE3

DC_TEST_BG3_BE3

BG1
BE1

DC_TEST_BG1_BE1

BD1

E

CFG Straps for Processor

(CFG[17:0] internal pull high 5~15K to VCCIO)

CFG2

12

RC79

RC79
1K_0402_1%

1K_0402_1%

@

@

PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane # definition

CFG2

matches socket pin map definition

0:Lane Reversed

*

CFG4

12

RC82

RC82
1K_0402_1%

1K_0402_1%

IEDP@

IEDP@

Embedded Display Port Presence Strap

1 : Disabled; No Physical Display Port
attached to Embedded Display Port

*

CFG4

0 : Enabled; An external Display Port
device is connected to the Embedded
Display Port

CFG7

12

RC85

RC85
1K_0402_1%

1K_0402_1%

@

@

PEG DEFER TRAINING

1: (Default) PEG Train immediately
following xxRESETB de assertion

*

CFG7

0: PEG Wait for BIOS for training

CFG6

CFG5

1K_0402_1%

1K_0402_1%

RC83

RC83

12

12

RC84

RC84
1K_0402_1%

1K_0402_1%

@

@

@

@

PCIE Port Bifurcation Straps

IVY-BRIDGE_BGA1023 <BOM>

IVY-BRIDGE_BGA1023 <BOM>

CPU@

CPU@

CFG[6:5]

4 4

11: (Default) x16 - Device 1 functions 1 and 2
disabled

*

10: x8, x8 - Device 1 function 1 enabled;
function 2 disabled

01: Reserved - (Device 1 function 1 disabled;
function 2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

2012/04/19 2015/04/19

2012/04/19 2015/04/19

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Ivy Bridge_GND/RSVD/CFG

Ivy Bridge_GND/RSVD/CFG

Ivy Bridge_GND/RSVD/CFG

VFKTA

VFKTA

VFKTA

10 56Thursday, January 17, 2013

10 56Thursday, January 17, 2013

10 56Thursday, January 17, 2013

E

0.3

0.3

0.3

of

of

of

CyberForum.ru

5

4

3

2

1

+1.5V

JDDR3L

+VREF_DQA

1

CD2

CD1

CD1

0.1U_0402_10V7K

0.1U_0402_10V7K

2

D D

Close to JDDRL.1

C C

B B

A A

+3VS

DDR_A_BS2<7>

DDRA_CLK0<7>
DDRA_CLK0#<7>

DDR_A_BS0<7>

DDR_A_WE#<7>

DDR_A_CAS#<7>

DDRA_SCS1#<7>

0.1U_0402_10V7K

0.1U_0402_10V7K

DDR_A_D0
DDR_A_D1

1

@CD2

@

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_D26
DDR_A_D27

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

DDR_A_MA10

DDR_A_MA13

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59

1

CD26

CD26

2

SPD setting (SA0 , SA1)
PU/PD by Channel A/B

->Channel A 00

->Channel B 01

5

+0.75VS

JDDR3L

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4406-0102

LCN_DAN06-K4406-0102
@

@

VSS3

DQS#0

DQS0
VSS6

VSS8
DQ12
DQ13

VSS10

DQ14
DQ15

DQ20
DQ21

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

VSS31

DQ38
DQ39

VSS33

DQ44

DQ45
VSS35
DQS#5

DQS5
VSS38

DQ46

DQ47
VSS40

DQ52

DQ53
VSS42

VSS43

DQ54

DQ55
VSS45

DQ60

DQ61
VSS47
DQS#7

DQS7
VSS50

DQ62

DQ63
VSS52

EVENT#

VTT2

DQ4
DQ5

DQ6
DQ7

DM1

DM2

CK1

BA1

NC2

DM4

DM6

SDA
SCL

+1.5V

2
4

DDR_A_D4

6

DDR_A_D5

8
10

DDR_A_DQS#0

12

DDR_A_DQS0

14
16

DDR_A_D6

18

DDR_A_D7

20
22

DDR_A_D12

24

DDR_A_D13

26
28
30
32
34

DDR_A_D14

36

DDR_A_D15

38
40

DDR_A_D20

42

DDR_A_D21

44
46
48
50

DDR_A_D22

52

DDR_A_D23

54
56

DDR_A_D28

58

DDR_A_D29

60
62

DDR_A_DQS#3

64

DDR_A_DQS3

66
68

DDR_A_D30

70

DDR_A_D31

72

74
76
78

A15
A14

A11

A7

A6
A4

A2
A0

S0#

G2

DDR_A_MA15

80

DDR_A_MA14

82
84

DDR_A_MA11

86

DDR_A_MA7

88
90

DDR_A_MA6

92

DDR_A_MA4

94
96

DDR_A_MA2

98

DDR_A_MA0

100
102
104
106
108
110
112
114
116
118
120
122
124
126

+VREF_CAA

128
130

DDR_A_D36

132

DDR_A_D37

134
136
138
140

DDR_A_D38

142

DDR_A_D39

144
146

DDR_A_D44

148

DDR_A_D45

150
152

DDR_A_DQS#5

154

DDR_A_DQS5

156
158

DDR_A_D46

160

DDR_A_D47

162
164

DDR_A_D52

166

DDR_A_D53

168
170
172
174

DDR_A_D54

176

DDR_A_D55

178
180

DDR_A_D60

182

DDR_A_D61

184
186

DDR_A_DQS#7

188

DDR_A_DQS7

190
192

DDR_A_D62

194

DDR_A_D63

196
198
200
202
204

+0.75VS

206

4

DDR3 SO-DIMM A
Standard Type

SM_DRAMRST# <12,7>

DDRA_CKE1 <7>DDRA_CKE0<7>

DDRA_CLK1 <7>
DDRA_CLK1# <7>

DDR_A_BS1 <7>
DDR_A_RAS# <7>

DDRA_SCS0# <7>
DDRA_ODT0 <7>

DDRA_ODT1 <7>

1

1

CD16

CD16

CD15

CD15

close to JDDRL.126

PM_SMBDATA <12,26,35,42>
PM_SMBCLK <12,26,35,42>

0.1U_0402_10V7K

0.1U_0402_10V7K

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

@

@

2

2

DDR_A_DQS[0..7] <7>

DDR_A_DQS#[0..7] <7>

DDR_A_D[0..63] <7>

DDR_A_MA[0..15] <7>

+1.5V

12

RD1

RD1

1K_0402_1%

1K_0402_1%

+VREF_DQA

+1.5V

12

RD6

RD6

1K_0402_1%

1K_0402_1%

12

RD7

RD7

1K_0402_1%

1K_0402_1%

Layout Note:
Place near JDDRL

+1.5V +1.5V +0.75VS

1 2

CD8 10U_0603_6.3V6MCD8 10U_0603_6.3V6M

1 2

CD9 10U_0603_6.3V6MCD9 10U_0603_6.3V6M

1 2

CD10 10U_0603_6.3V6MCD10 10U_0603_6.3V6M

1 2

CD11 10U_0603_6.3V6MCD11 10U_0603_6.3V6M

1 2

CD12 10U_0603_6.3V6MCD12 10U_0603_6.3V6M

1 2

CD13 10U_0603_6.3V6MCD13 10U_0603_6.3V6M

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/09/24 2013/09/24

2012/09/24 2013/09/24

2012/09/24 2013/09/24

Compal Secret Data

Compal Secret Data

Compal Secret Data

12

Deciphered Date

Deciphered Date

Deciphered Date

+VREF_DQB

RD2

RD2

1K_0402_1%

1K_0402_1%

Layout Note: Place these 4 Caps near
Command and Control signals of DIMMA

CD20 0.1U_0402_10V7KCD20 0.1U_0402_10V7K

CD17 0.1U_0402_10V7KCD17 0.1U_0402_10V7K

CD18 0.1U_0402_10V7KCD18 0.1U_0402_10V7K

CD19 0.1U_0402_10V7KCD19 0.1U_0402_10V7K

2

1 2

1 2

1 2

1 2

+1.5V

12

RD10

RD10

1K_0402_1%

1K_0402_1%

12

RD11

RD11

1K_0402_1%

1K_0402_1%

Date: Sheet

Date: Sheet

Date: Sheet

Layout Note:
Place near JDDRL1.203 and 204

12

CD24 1U_0402_6.3V6KCD24 1U_0402_6.3V6K

12

CD21 1U_0402_6.3V6KCD21 1U_0402_6.3V6K

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Compal Electronics, Inc.

DDRIII-SODIMM0

DDRIII-SODIMM0

DDRIII-SODIMM0

VFKTA

VFKTA

VFKTA

11 56Thursday, January 17, 2013

11 56Thursday, January 17, 2013

11 56Thursday, January 17, 2013

1

of

of

of

0.3

0.3

0.3

CyberForum.ru

A

B

C

D

E

DQ4
DQ5

DQ6
DQ7

DM1

DM2

CK1

BA1

NC2

DM4

DM6

SDA
SCL

+1.5V

2
4

DDR_B_D4

6

DDR_B_D5

8
10

DDR_B_DQS#0

12

DDR_B_DQS0

14
16

DDR_B_D6

18

DDR_B_D7

20
22

DDR_B_D12

24

DDR_B_D13

26
28
30
32
34

DDR_B_D14

36

DDR_B_D15

38
40

DDR_B_D20

42

DDR_B_D21

44
46
48
50

DDR_B_D22

52

DDR_B_D23

54
56

DDR_B_D28

58

DDR_B_D29

60
62

DDR_B_DQS#3

64

DDR_B_DQS3

66
68

DDR_B_D30

70

DDR_B_D31

72

74
76
78

A15
A14

A11

A7

A6
A4

A2
A0

S0#

G2

DDR_B_MA15

80

DDR_B_MA14

82
84

DDR_B_MA11

86

DDR_B_MA7

88
90

DDR_B_MA6

92

DDR_B_MA4

94
96

DDR_B_MA2

98

DDR_B_MA0

100
102
104
106
108
110
112
114
116
118
120
122
124
126

+VREF_CAB

128
130

DDR_B_D36

132

DDR_B_D37

134
136
138
140

DDR_B_D38

142

DDR_B_D39

144
146

DDR_B_D44

148

DDR_B_D45

150
152

DDR_B_DQS#5

154

DDR_B_DQS5

156
158

DDR_B_D46

160

DDR_B_D47

162
164

DDR_B_D52

166

DDR_B_D53

168
170
172
174

DDR_B_D54

176

DDR_B_D55

178
180

DDR_B_D60

182

DDR_B_D61

184
186

DDR_B_DQS#7

188

DDR_B_DQS7

190
192

DDR_B_D62

194

DDR_B_D63

196
198
200
202
204

+0.75VS

206

B

DDRB_CKE1 <7>

DDRB_CLK1 <7>
DDRB_CLK1# <7>

DDR_B_BS1 <7>
DDR_B_RAS# <7>DDR_B_BS0<7>

DDRB_SCS0# <7>
DDRB_ODT0 <7>

DDRB_ODT1 <7>

CD46

CD46

Close to JDDRH.126

PM_SMBDATA <11,26,35,42>
PM_SMBCLK <11,26,35,42>

DDR3 SO-DIMM B
Standard Type

SM_DRAMRST# <11,7>

CD47

CD47

1

@

@

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1

0.1U_0402_10V7K

0.1U_0402_10V7K

2

2

DDR_B_DQS#[0..7] <7>

DDR_B_DQS[0..7] <7>

DDR_B_D[0..63] <7>

DDR_B_MA[0..15] <7>

+1.5V

12

RD12

RD12

1K_0402_1%

1K_0402_1%

12

RD13

RD13

1K_0402_1%

1K_0402_1%

Layout Note:
Place near JDDRH

+1.5V +0.75VS+1.5V

1 2

CD31 47U_0805_6.3V6MCD31 47U_0805_6.3V6M

1 2

CD41 10U_0603_6.3V6MCD41 10U_0603_6.3V6M

1 2

CD36 10U_0603_6.3V6MCD36 10U_0603_6.3V6M

1 2

CD37 10U_0603_6.3V6MCD37 10U_0603_6.3V6M

1 2

CD38 10U_0603_6.3V6MCD38 10U_0603_6.3V6M

1 2

CD39 10U_0603_6.3V6MCD39 10U_0603_6.3V6M

1 2

CD40 10U_0603_6.3V6MCD40 10U_0603_6.3V6M

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/09/24 2013/09/24

2012/09/24 2013/09/24

2012/09/24 2013/09/24

Compal Secret Data

Compal Secret Data

Compal Secret Data

Layout Note: Place these 4 Caps near
Command and Control signals of DIMMB

CD33 0.1U_0402_10V7KCD33 0.1U_0402_10V7K

CD29 0.1U_0402_10V7KCD29 0.1U_0402_10V7K

CD30 0.1U_0402_10V7KCD30 0.1U_0402_10V7K

CD32 0.1U_0402_10V7KCD32 0.1U_0402_10V7K

Deciphered Date

Deciphered Date

Deciphered Date

D

1 2

1 2

1 2

1 2

Date: Sheet

Date: Sheet

Date: Sheet

Layout Note:
Place near JDDRH.203 and 204

12

CD45 1U_0402_6.3V6KCD45 1U_0402_6.3V6K

12

CD42 1U_0402_6.3V6KCD42 1U_0402_6.3V6K

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Compal Electronics, Inc.

DDRIII-SODIMM1

DDRIII-SODIMM1

DDRIII-SODIMM1

VFKTA

VFKTA

VFKTA

12 56Thursday, January 17, 2013

12 56Thursday, January 17, 2013

12 56Thursday, January 17, 2013

E

of

of

of

0.3

0.3

0.3

+1.5V

JDDR3H

+VREF_DQB

CD28

CD28

1

@

@

2.2U_0402_6.3V6M

1 1

2.2U_0402_6.3V6M

2

Close to JDDRH.1

+3VS

DDRB_CKE0<7>

DDR_B_BS2<7>

DDRB_CLK0<7>
DDRB_CLK0#<7>

DDR_B_WE#<7>
DDR_B_CAS#<7>

DDRB_SCS1#<7>

1

CD49

CD49

2

0.1U_0402_10V7K

0.1U_0402_10V7K

2 2

3 3

4 4

DDR_B_D0
DDR_B_D1

CD27

CD27

1

DDR_B_D2
DDR_B_D3

0.1U_0402_10V7K

0.1U_0402_10V7K

2

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_D26
DDR_B_D27

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

DDR_B_MA10

DDR_B_MA13

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_D58
DDR_B_D59

12

RD15 10K_0402_5%R D15 10 K_0402_5%

SPD setting (SA0 , SA1)
PU/PD by Channel A/B

->Channel A 00

->Channel B 01

A

+0.75VS

JDDR3H

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4806-0102

LCN_DAN06-K4806-0102

@

@

VSS3

DQS#0

DQS0

VSS6

VSS8
DQ12
DQ13

VSS10

DQ14
DQ15

DQ20
DQ21

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35
DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47
DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

VTT2

CyberForum.ru

A

PCIE_GTX_C_CRX_P[0..3]<6>

PCIE_GTX_C_CRX_N[0..3]<6>

PCIE_CTX_C_GRX_P[0..3]<6>

PCIE_CTX_C_GRX_N[0..3]<6>

1 1

PCIE_GTX_C_CRX_P0
PCIE_GTX_C_CRX_N0
PCIE_GTX_C_CRX_P1
PCIE_GTX_C_CRX_N1
PCIE_GTX_C_CRX_P2
PCIE_GTX_C_CRX_N2
PCIE_GTX_C_CRX_P3
PCIE_GTX_C_CRX_N3

2 2

3 3

CLK_REQ_VGA#<26>

4 4

PCIE_GTX_C_CRX_P[0..3]

PCIE_GTX_C_CRX_N[0..3]

PCIE_CTX_C_GRX_P[0..3]

PCIE_CTX_C_GRX_N[0..3]

1 2

CV1 0.22U_0402_16V7KOPT@CV1 0.22U_0402_16V7KOPT @

1 2

CV2 0.22U_0402_16V7KOPT@CV2 0.22U_0402_16V7KOPT @

1 2

CV3 0.22U_0402_16V7KOPT@CV3 0.22U_0402_16V7KOPT @

1 2

CV4 0.22U_0402_16V7KOPT@CV4 0.22U_0402_16V7KOPT @

1 2

CV5 0.22U_0402_16V7KOPT@CV5 0.22U_0402_16V7KOPT @

1 2

CV6 0.22U_0402_16V7KOPT@CV6 0.22U_0402_16V7KOPT @

1 2

CV7 0.22U_0402_16V7KOPT@CV7 0.22U_0402_16V7KOPT @

1 2

CV8 0.22U_0402_16V7KOPT@CV8 0.22U_0402_16V7KOPT @

CLK_PCIE_VGA<26>

CLK_PCIE_VGA#<26>

PLTRST_VGA#<29>

61

QV2A

QV2A

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

OPT@

OPT@

2

1 2

@

@

RV4 200_04 02_1%

RV4 200_04 02_1%

+3VS_DGPU

PCIE_CTX_C_GRX_P0

PCIE_CTX_C_GRX_N0

PCIE_CTX_C_GRX_P1

PCIE_CTX_C_GRX_N1

PCIE_CTX_C_GRX_P2

PCIE_CTX_C_GRX_N2

PCIE_CTX_C_GRX_P3

PCIE_CTX_C_GRX_N3

PCIE_GTX_CRX_P0
PCIE_GTX_CRX_N0
PCIE_GTX_CRX_P1
PCIE_GTX_CRX_N1
PCIE_GTX_CRX_P2
PCIE_GTX_CRX_N2
PCIE_GTX_CRX_P3
PCIE_GTX_CRX_N3

CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_REQ_GPU#

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT#

RV5

RV5

2.49K_0402_1%

2.49K_0402_1%

OPT@

OPT@

1 2

B

UV1A

UV1A

AG6

PEX_RX0

AG7

PEX_RX0_N

AF7

PEX_RX1

AE7

PEX_RX1_N

AE9

PEX_RX2

AF9

PEX_RX2_N

AG9

PEX_RX3

AG10

PEX_RX3_N

AF10

PEX_RX4

AE10

PEX_RX4_N

AE12

PEX_RX5

AF12

PEX_RX5_N

AG12

PEX_RX6

AG13

PEX_RX6_N

AF13

PEX_RX7

AE13

PEX_RX7_N

AE15

NC

AF15

NC

AG15

NC

AG16

NC

AF16

NC

AE16

NC

AE18

NC

AF18

NC

AG18

NC

AG19

NC

AF19

NC

AE19

NC

AE21

NC

AF21

NC

AG21

NC

AG22

NC

AC9

PEX_TX0

AB9

PEX_TX0_N

AB10

PEX_TX1

AC10

PEX_TX1_N

AD11

PEX_TX2

AC11

PEX_TX2_N

AC12

PEX_TX3

AB12

PEX_TX3_N

AB13

PEX_TX4

AC13

PEX_TX4_N

AD14

PEX_TX5

AC14

PEX_TX5_N

AC15

PEX_TX6

AB15

PEX_TX6_N

AB16

PEX_TX7

AC16

PEX_TX7_N

AD17

NC

AC17

NC

AC18

NC

AB18

NC

AB19

NC

AC19

NC

AD20

NC

AC20

NC

AC21

NC

AB21

NC

AD23

NC

AE23

NC

AF24

NC

AE24

NC

AG24

NC

AG25

NC

AE8

PEX_REFCLK

AD8

PEX_REFCLK_N

AC6

PEX_CLKREQ_N

AF22

PEX_TSTCLK_OUT

AE22

PEX_TSTCLK_OUT_N

AC7

PEX_RST_N

AF25

PEX_TERMP

N14P-GV2-S-A2_FCBGA595

N14P-GV2-S-A2_FCBGA595

N14PGV2@

N14PGV2@

1

CV17

CV17
18P_0402_50V8J

18P_0402_50V8J

NOGCLK@

NOGCLK@

2

Part 1 of 6

Part 1 of 6

PCI EXPRESS

PCI EXPRESS

YV1

YV1

1

1

DACsI2C GPIO

DACsI2C GPIO

120mA

52mA

71mA

41mA

CLK

CLK

NOGCLK@

NOGCLK@

27MHZ_16PF

27MHZ_16PF

GND

2

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21

DACA_RED

DACA_GREEN

DACA_BLUE

DACA_HSYNC
DACA_VSYNC

DACA_VDD
DACA_VREF
DACA_RSET

I2CA_SCL

I2CA_SDA

I2CB_SCL

I2CB_SDA

I2CC_SCL

I2CC_SDA

I2CS_SCL

I2CS_SDA

CORE_PLLVDD

SP_PLLVDD

VID_PLLVDD

XTAL_IN

XTAL_OUT

XTAL_SSIN

XTAL_OUTBUFF

3

3

GND

4

18P_0402_50V8J

18P_0402_50V8J

NC

XTAL_OUTXTALIN

NOGCLK@

NOGCLK@

C6
B2
D6
C7
F9
A3
A4
B6
A6
F8
C5
E7
D7
B4
B3
C3
D5
D4
C2
F7
E6
C4

AB6

AG3
AF4
AF3

AE3
AE4

W5
AE2
AF2

B7
A7

C9
C8

A9
B9

D9
D8

L6
M6

N6

C11
B10

A10
C10

CV18

CV18

FB_CLAMP_MON

FB_CLAMP_REQ#

OVERT#_VGA
GPU_EVENT

DGPU_VID
GPS_DOWN#
PSI

VGA_CRT_CLK
VGA_CRT_DATA

HDCP_SCL
HDCP_SDA

VGA_EDID_CLK
VGA_EDID_DATA

SMB_CLK_GPU
SMB_DATA_GPU

+PLLVDD

+GPU_PLLVDD

XTALIN
XTAL_OUT

XTAL_SSIN
XTAL_OUTBUFF

1

2

C

+3VS_DGPU

G

G

2

QV8

QV8

13

D

D

S

S

2N7002KW_SOT323-3

2N7002KW_SOT323-3

DGPU_VID <53>

GPS_DOWN# <41 >

PSI <53>

1

2

CV42, CV43 under GPU
close to ball : AE8,AD7

VGA_X1<35>

10_0402_5%

10_0402_5%

10P_0402_50V8J

10P_0402_50V8J

RB751V40_SC76-2

RB751V40_SC76-2

OPT@

OPT@

N14PGV2@

N14PGV2@

EC GPS_DOWN# must be OD\Low
to avoid leakage

1

CV9

CV9

CV10

CV10

2

0.1U_0402_10V7K

0.1U_0402_10V7K

12

RV7

@EMI@RV7

@EMI@

1

CV113

@EMI@CV113

@EMI@

2

for EMI

DV1

DV1

12

CLK_REQ_GC6# <41>

BLM18PG181SN1D_2P

BLM18PG181SN1D_2P

1

CV11

CV11

2

0.1U_0402_10V7K

0.1U_0402_10V7K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1 2

RV8 0_0402_5%

RV8 0_0402_5%

GCLK@

GCLK@

LV1

LV1

1 2

1

CV12

CV12

2

22U_0805_6.3V6M

22U_0805_6.3V6M

FB_CLAMP <14,17,41>

For GC6

+1.05VS_DGPU

1

CV13

CV13

2

10U_0603_6.3V6M

10U_0603_6.3V6M

XTALIN

D

Internal Thermal Sensor

SMB_CLK_GPU

SMB_DATA_GPU

under GPU
close to AD8

JTAG_TRST<15>
TESTMODE<15>

OPT@

OPT@

QV1A

QV1A

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

+PLLVDD

1

2

GPS_DOWN#
GPU_EVENT
XTAL_OUTBUFF
XTAL_SSIN

VGA_EDID_DATA
VGA_EDID_CLK
SMB_DATA_GPU
SMB_CLK_GPU

VGA_CRT_CLK
VGA_CRT_DATA
HDCP_SCL
HDCP_SDA

FB_CLAMP
OVERT#_VGA
FB_CLAMP_MON
FB_CLAMP_REQ#

CLK_REQ_GC6#

CLK_REQ_GPU#

+3VS_DGPU

5

OPT@

OPT@

QV1B

QV1B

4

2

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

61

1

CV14

2

OPT@ CV14

OPT@

0.1U_0402_10V7K

0.1U_0402_10V7K

E

RPV1

RPV1

1 8
2 7
3 6
4 5

10K_8P4R_5%

10K_8P4R_5%

OPT@

OPT@

RPV2

RPV2

1 8
2 7
3 6
4 5

2.2K_8P4R_5%

2.2K_8P4R_5%

OPT@

OPT@

RPV3

RPV3

1 8
2 7
3 6
4 5

2.2K_8P4R_5%

2.2K_8P4R_5%

OPT@

OPT@

RPV12

RPV12

1 8
2 7
3 6
4 5

10K_8P4R_5%

10K_8P4R_5%

OPT@

OPT@

RPV13

RPV13

1 8
2 7
3 6
4 5

10K_8P4R_5%

10K_8P4R_5%

OPT@

OPT@

3

LV2

1 2

FBMA-L11-160808300LMA25T_2P

FBMA-L11-160808300LMA25T_2P

CV15

OPT@ CV15

OPT@

22U_0805_6.3V6M

22U_0805_6.3V6M

EC_SMB_CK2 <26,34,41>

EC_SMB_DA2 <26,34,41>

+1.05VS_DGPU

OPT@LV2

OPT@

+3VS_DGPU

1

2

+3VS

CV16

OPT@ CV16

OPT@

10U_0603_6.3V6M

10U_0603_6.3V6M

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/09/28 2013/09/28

2012/09/28 2013/09/28

2012/09/28 2013/09/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

VGA_N14x PEG & DAC

VGA_N14x PEG & DAC

VGA_N14x PEG & DAC

13 56Thursday, January 17, 2013

13 56Thursday, January 17, 2013

E

13 56Thursday, January 17, 2013

0.3

0.3

0.3

of

of

of

CyberForum.ru

A

VRAM Interface

+FB_PLLAVDD

CV20

22U_0805_6.3V6M

22U_0805_6.3V6M

1

OPT@CV20

OPT@

2

MDA[15..0]

MDA[31..16]

MDA[47..32]

MDA[63..48]

Close to H22

CV21

0.1U_0402_10V7K

0.1U_0402_10V7K

2

OPT@CV21

OPT@

1

CV22

1

OPT@CV22

OPT@

2

Close to P22

CV114

0.1U_0402_10V7K

0.1U_0402_10V7K

OPT@CV114

OPT@

UV1B

UV1B

Part 2 of 6

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58

0.1U_0402_10V7K

0.1U_0402_10V7K

1

2

FB_CLAMP<13,17,41>

MDA59
MDA60
MDA61
MDA62
MDA63

+FB_PLLAVDD

TV1 PAD

TV1 PAD
TV2 PAD

TV2 PAD

E18
F18
E16
F17
D20
D21
F20
E21
E15
D15
F15
F13
C13
B13
E13
D13
B15
C16
A13
A15
B18
A18
A19
C19
B24
C23
A25
A24
A21
B21
C20
C21
R22
R24
T22
R23
N25
N26
N23
N24
V23
V22
T23
U22
Y24

AA24

Y22
AA23
AD27
AB25
AD26
AC25
AA27
AA26

W26

Y25

R26

T25

N27

R27

V26

V27

W27
W25

F16

P22

D23

H22

@

@

F22

J22

@

@

FBA_D00
FBA_D01
FBA_D02
FBA_D03
FBA_D04
FBA_D05
FBA_D06
FBA_D07
FBA_D08
FBA_D09
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

FB_PLLAVDD_1
FB_PLLAVDD_2

FB_VREF_PROBE

FB_DLLAVDD

F3

FB_CLAMP

FBA_DEBUG0
FBA_DEBUG1

N14P-GV2-S-A2_FCBGA595

N14P-GV2-S-A2_FCBGA595

N14PGV2@

N14PGV2@

Part 2 of 6

MEMORY

MEMORY

62mA
62mA

35mA

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8

FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

FBA_DQS_RN0
FBA_DQS_RN1

INTERFACE A

INTERFACE A

FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

FBA_CLK0

FBA_CLK0_N

FBA_CLK1

FBA_CLK1_N

FBA_WCK01

FBA_WCK01_N

FBA_WCK23

FBA_WCK23_N

FBA_WCK45

FBA_WCK45_N

FBA_WCK67

FBA_WCK67_N

C27
C26
E24
F24
D27
D26
F25
F26
F23
G22
G23
G24
F27
G25
G27
G26
M24
M23
K24
K23
M27
M26
M25
K26
K22
J23
J25
J24
K27
K25
J27
J26

D19
D14
C17
C22
P24
W24
AA25
U25

F19
C14
A16
A22
P25
W22
AB27
T27

E19
C15
B16
B22
R25
W23
AB26
T26

D24
D25

N22
M22

D18
C18
D17
D16
T24
U24
V24
V25

CMDA0
CMDA1
CMDA2
CMDA3
CMDA4
CMDA5
CMDA6
CMDA7
CMDA8
CMDA9
CMDA10
CMDA11
CMDA12
CMDA13
CMDA14
CMDA15
CMDA16
CMDA17
CMDA18
CMDA19
CMDA20
CMDA21
CMDA22
CMDA23
CMDA24
CMDA25
CMDA26
CMDA27
CMDA28
CMDA29
CMDA30

DQSA#0
DQSA#1
DQSA#2
DQSA#3
DQSA#4
DQSA#5
DQSA#6
DQSA#7

DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7

DQSA0
DQSA1
DQSA2
DQSA3
DQSA4
DQSA5
DQSA6
DQSA7

CMDA[30..0] <18,19,20,21>

CLKA0 <18,20>
CLKA0# <18,20>

CLKA1 <19,21>
CLKA1# <19,21>

DQMA[3..0] <18,20>

DQMA[7..4] <19,21>

DQSA#[3..0] <18,20>

DQSA#[7..4] <19,21>

DQSA[3..0] <18,20>

DQSA[7..4] <19,21>

MDA[15..0]<18,20>

MDA[31..16]<18,20>

MDA[47..32]<19,21>

MDA[63..48]<19,21>

1 1

30ohms (ESR=0.01)

+1.05VS_DGPU

LV3

OPT@LV3

OPT@

1 2

FBMA-L11-160808300LMA25T_2P

FBMA-L11-160808300LMA25T_2P

Place close to B GA

Near GPU Close to F16

Place close to t he first T poin t

+VRAM_1.5VS

109876

12345

+VRAM_1.5VS

109876

12345

+VRAM_1.5VS

DDR3

CMDA16
CMDA19
CMDA3
CMDA0
CMDA20

RV10 100_0402_5%

RV10 100_0402_5%

RV12 100_0402_5%

RV12 100_0402_5%

CMDA12
CMDA14
CMDA15
CMDA7

RPV4

RPV4
100_1206_10P8R_5%

100_1206_10P8R_5%

OPT@

OPT@

CMDA11
CMDA4
CMDA5
CMDA6

CMDA22
CMDA9
CMDA21
CMDA24

RPV6

RPV6
100_1206_10P8R_5%

100_1206_10P8R_5%

OPT@

OPT@

CMDA23
CMDA13
CMDA8
CMDA10

RPV8

RPV8

18

CMDA26

27

CMDA25

36

CMDA27

45

CMDA28

100_0804_8P4R_5%

100_0804_8P4R_5%

OPT@

OPT@

12

OPT@

OPT@

12

OPT@

OPT@

Command Bit Default Pull-down

ODTx

CKEx

RST

CS* No Termination

1 2

RV36 10K_0402_5%OPT@RV36 10K_0 402_5%OPT@

1 2

RV37 10K_0402_5%OPT@RV37 10K_0 402_5%OPT@

1 2

RV38 10K_0402_5%OPT@RV38 10K_0 402_5%OPT@

1 2

RV40 10K_0402_5%OPT@RV40 10K_0 402_5%OPT@

1 2

RV15 10K_0402_5%OPT@RV15 10K_0 402_5%OPT@

CMDA29

CMDA30

10k

10k

10k

109876

12345

109876

12345

1 8

CMDA28

2 7

CMDA27

3 6

CMDA25

4 5

CMDA26

RV11 100_0402_5%

RV11 100_0402_5%

RV13 100_0402_5%

RV13 100_0402_5%

RPV5

RPV5
100_1206_10P8R_5%

100_1206_10P8R_5%

OPT@

OPT@

RPV7

RPV7
100_1206_10P8R_5%

100_1206_10P8R_5%

OPT@

OPT@

RPV9

RPV9

100_0804_8P4R_5%

100_0804_8P4R_5%

OPT@

OPT@

12

OPT@

OPT@

12

OPT@

OPT@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

2012/09/28 2013/09/28

2012/09/28 2013/09/28

2012/09/28 2013/09/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

N14x VRAM Interface

N14x VRAM Interface

N14x VRAM Interface

14 56Thursday, January 17, 2013

14 56Thursday, January 17, 2013

14 56Thursday, January 17, 2013

of

of

of

0.3

0.3

0.3

CyberForum.ru

5

UV1C

UV1C

AC3

IFPA_TXC

AC4

IFPA_TXC_N

Y4

IFPA_TXD0

Y3

IFPA_TXD0_N

AA3

IFPA_TXD1

AA2

IFPA_TXD1_N

AB1

IFPA_TXD2

AA1

IFPA_TXD2_N

AA4

D D

C C

B B

A A

IFPA_TXD3

AA5

IFPA_TXD3_N

AB5

IFPB_TXC

AB4

IFPB_TXC_N

AB3

IFPB_TXD4

AB2

IFPB_TXD4_N

AD3

IFPB_TXD5

AD2

IFPB_TXD5_N

AE1

IFPB_TXD6

AD1

IFPB_TXD6_N

AD4

IFPB_TXD7

AD5

IFPB_TXD7_N

T2

IFPC_L0

T3

IFPC_L0_N

T1

IFPC_L1

R1

IFPC_L1_N

R2

IFPC_L2

R3

IFPC_L2_N

N2

IFPC_L3

N3

IFPC_L3_N

V3

IFPD_L0

V4

IFPD_L0_N

U3

IFPD_L1

U4

IFPD_L1_N

T4

IFPD_L2

T5

IFPD_L2_N

R4

IFPD_L3

R5

IFPD_L3_N

N1

NC

M1

NC

M2

NC

M3

NC

K2

NC

K3

NC

K1

NC

J1

NC

M4

NC

M5

NC

L3

NC

L4

NC

K4

NC

K5

NC

J4

NC

J5

NC

N4

IFPC_AUX_I2CW_SCL

N5

IFPC_AUX_I2CW_SDA_N

P3

IFPD_AUX_I2CX_SCL

P4

IFPD_AUX_I2CX_SDA_N

J2

IFPE_AUX_I2CY_SCL

J3

IFPE_AUX_I2CY_SDA_N

H3

IFPF_AUX_I2CZ_SCL

H4

IFPF_AUX_I2CZ_SDA_N

N14P-GV2-S-A2_FCBGA595

N14P-GV2-S-A2_FCBGA595

N14PGV2@

N14PGV2@

Part 3 of 6

Part 3 of 6

NC

NC

GENERAL

GENERAL

MULTI_STRAP_REF0_GND

LVDS/TMDS

LVDS/TMDS

VDD_SENSE

GND_SENSE

TEST

TEST

JTAG_TRST_N

SERIAL

SERIAL

BUFRST_N

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

THERMDP

THERMDN

TESTMODE

JTAG_TCK

JTAG_TDI

JTAG_TDO

JTAG_TMS

ROM_CS_N

ROM_SI

ROM_SO

ROM_SCLK

F11

NC

AD10

NC

AD7

NC

B19

NC

V5

NC

V6

NC

G1

NC

G2

NC

G3

NC

G4

NC

G5

NC

G6

NC

G7

NC

V1

NC

V2

NC

W1

NC

W2

NC

W3

NC

W4

NC

D11

D10

NC

E9

NC

E10

NC

F10

NC

D1
D2
E4
E3
D3
C1

NC

F6
F4

NC

F5

NC

F12

E12

F2

F1

AD9
AE5
AE6
AF6
AD6
AG4

D12
B12
A12
C12

4

OPT@

OPT@

1 2

RV16 10K_0402_5%

RV16 10K_0402_5%

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

MULTI_STRAP_REF0_GND

VGA_VCC_SENSE

trace width: 16mils
differential voltage sensing.

VGA_VSS_SENSE

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS

ROM_SI
ROM_SO
ROM_SCLK

differential signal routing.

PAD

PAD
PAD

PAD
PAD @

PAD @
PAD

PAD

N14PGV2@

N14PGV2@

1 2

RV17 40.2K_0402_1%

RV17 40.2K_0402_1%

+VGA_CORE

RV26

RV26
100_0402_1%

100_0402_1%

OPT@

OPT@

1 2

OPT@

OPT@

12

RV35

RV35

100_0402_1%

100_0402_1%

TESTMODE <13>

@

@

TV3

TV3

@

@

TV4

TV4
TV5

TV5
TV6

@TV6

@

JTAG_TRST <13>

VGA_VCC_SENSE < 53>

VGA_VSS_SENSE <53>

N14P-GV2

3

Physical
Strapping pin

ROM_SO

ROM_SCLK

ROM_SI

STRAP0

STRAP1

STRAP2

STRAP3

STRAP4

Power Rail

+3VS_DGPU

+3VS_DGPU

+3VS_DGPU

+3VS_DGPU

+3VS_DGPU 3GIO_PADCFG[0]3GIO_PADCFG[1]3GIO_PADCFG[2]

+3VS_DGPU

+3VS_DGPU SOR0_EXPOSEDSOR2_EXPOSED SOR1_EXPOSED

+3VS_DGPU DP_PLL_VDD33V

Logical
Strapping Bit3

FB[1]

PCI_DEVID[4]

USER[3]

3GIO_PADCFG[3]

PCI_DEVID[3]

SOR3_EXPOSED

RESERVED

SKU Device ID biit5 to b it0

N14P-GV2

N14M-GL

MULTI LEVEL STRAPS

12

12

@

@

N14PGV2@

N14PGV2@

RV18

RV18

45.3K_0402_1%

STRAP0
STRAP1 STRAP3
STRAP2

45.3K_0402_1%

12

12

@

@

N14PGV2@

N14PGV2@

RV27

RV27

4.99K_0402_1%

4.99K_0402_1%

0x1140 000000

+3VS_DGPU

12

@

@

10K_0402_1%

10K_0402_1%

10K_0402_1%

RV19

RV19

RV28

RV28

10K_0402_1%

RV20

RV20

12

N14PGV2@

N14PGV2@

RV29

RV29

45.3K_0402_1%

45.3K_0402_1%

15K_0402_1%

15K_0402_1%

N14PGV2@

N14PGV2@

FB Memory gDDR3

900MHz

1
2
8
M

x
1
6

2
5
6
M

x
1
6

Samsung

Hynix

Micron

Micron

1GHz

900MHz

1GHz

900MHz

900MHz

900MHz

K4W2G1646E-BC11

K4W2G1646E-BC1A

H5TQ2G63DFR-11C

H5TQ2G63DFR-N0C

MT41K128M16JT-107G

K4W4G1646B-HC11Samsung

MT41K256M16HA-107G

010010TBD

12

12

@

@

@

@

RV21

RV21

RV22

RV22

4.99K_0402_1%

4.99K_0402_1%

12

12

N14PGV2@

N14PGV2@

RV31

RV31

RV30

RV30

4.99K_0402_1%

4.99K_0402_1%

ROM_SIGPU

PD 45K

PD 34.8K

PD 30K

PD 20K

PD 10K

10K_0402_1%

10K_0402_1%

STRAP4

45.3K_0402_1%

45.3K_0402_1%

2

PCIE_SPEED_CHANGE_GEN3

RV31

RV31

10K_0402_1%

10K_0402_1%

N14MGL@

N14MGL@

N14M-GL

Logical
Strapping Bit2

FB[0]

SUB_VENDOR

Resistor Values

For X76 (N14P-GV2)For X76 (N14M-GL)

Samsung

1
2
8
M

Hynix

x
1
6

Micron

Samsung K4W4G1646B-HC11

2
5
6
M

Hynix

x
1
6

Micron

Logical
Strapping Bit1

SMB_ALT_ADDR

PCI_DEVID[5]

RAMCFG[1]RAMCFG[3] RAMCFG[2]

PCIE_MAX_SPEED

5K

10K

15K

20K

25K

30K

35K

45K

ROM_SI
ROM_SO
ROM_SCLK

FB Memory gDDR3

1GHz

1GHz

900MHz

900MHz

900MHz

900MHz

1

Logical
Strapping Bit0

VGA_DEVICE

PEX_PLLEN_TERM

RAMCFG[0]

USER[0]USER[1]USER[2]

PCI_DEVID[0]PCI_DEVID[1]PCI_DEVID[2]

Pull-up to +3VS
_DGPU

1000

1001

1010

1011

1100

1101

1110

1111

12

12

@

@

RV23

RV23

4.99K_0402_1%

4.99K_0402_1%

N14PGV2@

N14PGV2@

12

12

N14MGL@

N14MGL@

N14MGL@

N14MGL@

RV32

RV32

10K_0402_1%

10K_0402_1%

K4W2G1646E-BC11900MHz

K4W2G1646E-BC1A

H5TQ2G63DFR-11C900MHz

H5TQ2G63DFR-N0C

MT41K128M16JT-107G

H5TC4G63AFR-11C

MT41K256M16HA-107G

Pull-down to Gnd

0000

0001

0010

0011

0100

0101

0110

0111

+3VS_DGPU

12

N14PGV2@

N14PGV2@

RV24

RV24

RV25

RV25

4.99K_0402_1%

4.99K_0402_1%

12

N14MGL@

N14MGL@

RV33

RV33

RV34

RV34

10K_0402_1%

10K_0402_1%

STRAP[3:0]GPU

4.99K_0402_1%

4.99K_0402_1%

10K_0402_1%

10K_0402_1%

0101

0110

0001

1011

0100

1101

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/09/28 2013/09/28

2012/09/28 2013/09/28

2012/09/28 2013/09/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

VGA_N14x LVDS&TMDS

VGA_N14x LVDS&TMDS

VGA_N14x LVDS&TMDS

15 56Thursday, January 17, 2013

15 56Thursday, January 17, 2013

1

15 56Thursday, January 17, 2013

0.3

0.3

0.3

of

of

of

CyberForum.ru

5

4

3

2

1

Under GPU

+VRAM_1.5VS

D D

Under GPU

1

1

1

1

CV32

CV24

2

2

2

OPT@ CV32

OPT@

OPT@ CV24

OPT@

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1

CV33

2

OPT@ CV33

OPT@

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CV34

CV25

CV35

2

2

OPT@ CV34

OPT@

OPT@ CV25

OPT@

OPT@ CV35

1U_0402_6.3V6K

1U_0402_6.3V6K

OPT@

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

Near GPU

1

1

CV44

CV43

2

2

OPT@ CV44

OPT@

OPT@ CV43

OPT@

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

C C

B B

UV1D

UV1D

B26
C25
E23
E26
F14
F21
G13
G14
G15
G16
G18
G19
G20
G21
H24
H26

J21
K21

L22

L24

L26

M21

N21
R21
T21
V21

W21

V7

W7
AA6

W6

Y6

M7
N7

T6
P6

T7
R7
U6
R6

J7

K7

K6
H6

J6

N14P-GV2-S-A2_FCBGA595

N14P-GV2-S-A2_FCBGA595

N14PGV2@

N14PGV2@

Part 4 of 6

Part 4 of 6

3500 mA 2000 mA

FBVDDQ_01
FBVDDQ_02
FBVDDQ_03
FBVDDQ_04
FBVDDQ_05
FBVDDQ_06
FBVDDQ_07
FBVDDQ_08
FBVDDQ_09
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27

IFPAB_PLLVDD_1
IFPAB_PLLVDD_2
IFPAB_RSET
IFPA_IOVDD
IFPB_IOVDD

IFPC_PLLVDD_1
IFPC_PLLVDD_2
IFPC_RSET
IFPC_IOVDD

IFPD_PLLVDD_2
IFPD_PLLVDD_1
IFPD_RSET
IFPD_IOVDD

NC
NC
NC
NC
NC

PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8

PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14

PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
PEX_IOVDD_6

VDD33_1
VDD33_2
VDD33_3
VDD33_4

POWER

POWER

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CAL_TERM_GND

PEX_PLL_HVDD_1
PEX_PLL_HVDD_2

PEX_SVDD_3V3

120mA

PEX_PLLVDD_1

PEX_PLLVDD_2

AA10
AA12
AA13
AA16
AA18
AA19
AA20
AA21
AB22
AC23
AD24
AE25
AF26
AF27

AA22
AB23
AC24
AD25
AE26
AE27

G10
G12
G8
G9

D22

C24

B25

AA8
AA9

AB8

AA14
AA15

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CAL_TERM_GND

Under GPU

1

2

Near Ball

1 2

Near GPU

1

CV54

2

OPT@ CV54

OPT@

0.1U_0402_10V7K

0.1U_0402_10V7K

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

CV55

OPT@ CV55

OPT@

1

2

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

Near GPU

1

CV26

CV23

2

OPT@ CV26

OPT@

OPT@ CV23

OPT@

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CV37

CV36

2

OPT@ CV37

OPT@

OPT@ CV36

OPT@

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

+VRAM_1.5VS

RV3940.2_0402_1 %

RV3940.2_0402_1 %

12

RV4142.2_0402_1 %

RV4142.2_0402_1 %

12

RV4251.1_0402_1 %

RV4251.1_0402_1 %

1

CV56

2

OPT@ CV56

OPT@

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

midway between G PU
and Power supply

1

1

CV28

CV27

2

2

OPT@ CV28

OPT@

OPT@ CV27

OPT@

10U_0603_6.3V6M

10U_0603_6.3V6M

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1

1

CV38

CV39

2

2

OPT@ CV39

OPT@

OPT@ CV38

OPT@

10U_0603_6.3V6M

10U_0603_6.3V6M

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

Under GPU

1

1

CV46

CV45

2

2

OPT@ CV46

OPT@

OPT@ CV45

OPT@

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

+1.05VS_DGPU

LV4

LV4

N14MGL@

N14MGL@

RV1

RV1

0_0603_5%

0_0603_5%

N14PGV2@

N14PGV2@

12

12

BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

1

CV29

2

OPT@ CV29

OPT@

10U_0603_6.3V6M

10U_0603_6.3V6M

1

CV40

2

OPT@ CV40

OPT@

10U_0603_6.3V6M

10U_0603_6.3V6M

Near GPU

1

CV47

2

OPT@ CV47

OPT@

0.1U_0402_10V7K

0.1U_0402_10V7K

+1.05VS_DGPU

1

1

CV30

2

2

OPT@ CV30

OPT@

22U_0805_6.3V6M

22U_0805_6.3V6M

+1.05VS_DGPU

1

1

CV41

2

2

OPT@ CV41

OPT@

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

CV48

2

2

OPT@ CV48

OPT@

1U_0402_6.3V6K

1U_0402_6.3V6K

Under GPU
Close to AH12/AG 12

CV31

OPT@ CV31

OPT@

22U_0805_6.3V6M

22U_0805_6.3V6M

CV42

OPT@ CV42

OPT@

22U_0805_6.3V6M

22U_0805_6.3V6M

+3VS_DGPU

CV49

OPT@ CV49

OPT@

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1

2

Near GPU

1

CV50

CV51

2

OPT@ CV50

OPT@

OPT@ CV51

OPT@

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

+3VS_DGPU

1

1

CV52

CV53

2

2

OPT@ CV52

OPT@

OPT@ CV53

OPT@

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/09/28 2013/09/28

2012/09/28 2013/09/28

2012/09/28 2013/09/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

VGA_N14x POWER

VGA_N14x POWER

VGA_N14x POWER

1

0.3

0.3

16 56Thursday, January 17, 2013

16 56Thursday, January 17, 2013

16 56Thursday, January 17, 2013

0.3

of

of

of

CyberForum.ru

5

4

3

2

1

+1.05VS_VCCP to +1.05VS_DGPU

+5VALW

12

RV43

RV43
270K_0402_5%

270K_0402_5%

OPT@

OPT@

61

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

0.01U_0402_25V7K

0.01U_0402_25V7K

VGA_PWROK

OPT@

OPT@

QV4A

QV4A

2

VGA_PWROK#

QV5A

QV5A

2

G

G

OPT@

OPT@

AO3416_SOT23-3

AO3416_SOT23-3

+1.05VS_DGPU

+1.05VS_VCCP

Vgs=4.5V,Id=6.5A ,Rds<22mohm

QV3

OPT@

QV3

OPT@

13

D

D

2

G

G

S

S

CV57

CV57

OPT@

OPT@

1

2

+1.5V to +VRAM_1.5VS

CV59

CV59

OPT@

OPT@

+1.5V

QV6

OPT@QV6

OPT@

8

D

7

D

6

D

5

D

FDS6676AS_SO8

FDS6676AS_SO8

1

CV60

CV60

OPT@

OPT@

2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

+VRAM_1.5VS

Vgs=10V,Id=14.5A ,Rds=6mohm

1

S

2

S

3

S

4

G

VRAM_1.5VS_GATE

1

12

RV48

RV48
820K_0402_5%OPT@

0.01U_0402_25V7K

0.01U_0402_25V7K

820K_0402_5%OPT@

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

2

1.5V_PWR_EN

OPT@

OPT@

RV47

RV47

1 2

180K_0402_5%

180K_0402_5%

61

QV7A

QV7A

2

OPT@

OPT@

QV5B

QV5B

5

G

G

OPT@

OPT@

B+

1.5V_PWR_EN#

34

D

D

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

S

S

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

1 2

OPT@

OPT@

61

D

D

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

S

S

RV46

RV46
470_0805_5%

470_0805_5%

OPT@

OPT@

1 2

3

QV7B

QV7B

5

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

OPT@

OPT@

4

1 2

RV49100K_0402_5%

RV49100K_0402_5%

OPT@

OPT@

+1.05VS_DGPU

RV44

RV44

22_0805_5%OPT@

22_0805_5%OPT@

1 2

3

OPT@

OPT@

QV4B

QV4B

5

4

RV45100K_0402_5%

RV45100K_0402_5%

+5VALW

+5VALW

+3VS

5

3

+VGA_CORE+VGA_CORE

V18
V16
V14
V12
V10
U17
U15
U13
U11
T18
T16
T14
T12
T10
R17
R15
R13
R11
P18
P16
P14

UV2

UV2

4

Vcc

G

1.5V_PWR_EN

Y

NC7SZ32P5X_SC70-5N14PGV2@

NC7SZ32P5X_SC70-5N14PGV2@

UV1E

UV1E

A2

A26
AB11
AB14
AB17
AB20

D D

C C

B B

AB24

AC2
AC22
AC26

AC5

AC8
AD12
AD13
AD15
AD16
AD18
AD19
AD21
AD22
AE11
AE14
AE17
AE20

AF1
AF11
AF14
AF17
AF20
AF23

AF5

AF8

AG2
AG26

B1
B11
B14
B17
B20
B23
B27

B5

B8
E11
E14
E17

E2
E20
E22
E25

E5

E8

H2
H23
H25

H5

N14P-GV2-S-A2_FCBGA595

N14P-GV2-S-A2_FCBGA595

N14PGV2@

N14PGV2@

GND_001
GND_002
GND_003
GND_004
GND_005
GND_006
GND_007
GND_008
GND_009
GND_010
GND_011
GND_012
GND_013
GND_014
GND_015
GND_016
GND_017
GND_018
GND_019
GND_020
GND_021
GND_022
GND_023
GND_024
GND_025
GND_026
GND_027
GND_028
GND_029
GND_030
GND_031
GND_032
GND_033
GND_034
GND_035
GND_036
GND_037
GND_038
GND_039
GND_040
GND_041
GND_042
GND_043
GND_044
GND_045
GND_046
GND_047
GND_048
GND_049
GND_050
GND_051
GND_052
GND_053
GND_054
GND_055
GND_056

Part 5 of 6

Part 5 of 6

GND

GND

GND_057
GND_058
GND_059
GND_060
GND_061
GND_062
GND_063
GND_064
GND_065
GND_066
GND_067
GND_068
GND_069
GND_070
GND_071
GND_072
GND_073
GND_074
GND_075
GND_076
GND_077
GND_078
GND_079
GND_080
GND_081
GND_082
GND_083
GND_084
GND_085
GND_086
GND_087
GND_088
GND_089
GND_090
GND_091
GND_092
GND_093
GND_094
GND_095
GND_096
GND_097
GND_098
GND_099
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112

GND
GND

K11
K13
K15
K17
L10
L12
L14
L16
L18
L2
L23
L25
L5
M11
M13
M15
M17
N10
N12
N14
N16
N18
P11
P13
P15
P17
P2
P23
P26
P5
R10
R12
R14
R16
R18
T11
T13
T15
T17
U10
U12
U14
U16
U18
U2
U23
U26
U5
V11
V13
V15
V17
Y2
Y23
Y26
Y5

AA7
AB7

For GC6

VGA_PWROK<30,53>

K10

VDD_001

K12

VDD_002

K14

VDD_003

K16

VDD_004

K18

VDD_005

L11

VDD_006

L13

VDD_007

L15

VDD_008

L17

VDD_009

M10

VDD_010

M12

VDD_011

M14

VDD_012

M16

VDD_013

M18

VDD_014

N11

VDD_015

N13

VDD_016

N15

VDD_017

N17

VDD_018

P10

VDD_019

P12

VDD_020

N14P-GV2-S-A2_FCBGA595

N14P-GV2-S-A2_FCBGA595

N14PGV2@

N14PGV2@

FB_CLAMP<13,14,41>

UV1F

UV1F

Part 6 of 6

Part 6 of 6

POWER

POWER

0.1U_0402_10V7K

0.1U_0402_10V7K

VDD_041
VDD_040
VDD_039
VDD_038
VDD_037
VDD_036
VDD_035
VDD_034
VDD_033
VDD_032
VDD_031
VDD_030
VDD_029
VDD_028
VDD_027
VDD_026
VDD_025
VDD_024
VDD_023
VDD_022
VDD_021

@

@

1

CV58

CV58

2

2

B

1

A

1 2

RV50 0_0402_5%

RV50 0_0402_5%

N14MGL@

N14MGL@

+3VS to +3VS_DGPU

+VGA_CORE

RV51

RV51

470_0805_5%

470_0805_5%

OPT@

OPT@

1 2
3

QV9B

QV9B

5

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

A A

5

4

OPT@

OPT@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

DGPU_PWR_EN#

4

3

RV52

RV52

470_0805_5%

470_0805_5%

OPT@

OPT@

1 2
3

QV2B

QV2B

5

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

OPT@

OPT@

4

Compal Secret Data

Compal Secret Data

2012/09/28 2013/09/28

2012/09/28 2013/09/28

2012/09/28 2013/09/28

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

DGPU_PWR_EN<29>

2

DGPU_PWR_EN#

+3VS+3VS_DGPU

RV53

RV53
10K_0402_5%OPT@

10K_0402_5%OPT@

1 2

RV54

RV54

1 2

33K_0402_5%

33K_0402_5%

61

OPT@

QV9A

QV9A

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

OPT@

2

OPT@

OPT@

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

2

CV61

CV61

0.1U_0402_10V7K

0.1U_0402_10V7K

OPT@

OPT@

1

AO3413_SOT23

AO3413_SOT23

2

CV62

CV62

OPT@

OPT@

0.01U_0402_25V7K

0.01U_0402_25V7K

1

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

VGA_N14x POWER & GND

VGA_N14x POWER & GND

VGA_N14x POWER & GND

+3VS

Vgs=-4.5V,Id=3A, Rds<97mohm

S

S

QV11

QV11

G

G

2

OPT@

OPT@

D

D

1 3

+3VS_DGPU

17 56Thursday, January 17, 2013

17 56Thursday, January 17, 2013

1

17 56Thursday, January 17, 2013

0.3

0.3

0.3

of

of

of