Compal LA-7202P PWWHA Delhi 10R, Satellite C660 Schematic

A

1 1

B

C

D

E

PWWHA

2 2

Delhi 10R

LA-7202P SchematicREV 1.0

3 3

4 4

Intel Processor(Sandy Bridge) / PCH(Cougar Point)

2011-02-08 Rev 1.0

Security Class ification

Security Class ification

Security Class ification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/09/ 03 2012/12/ 31

2010/09/ 03 2012/12/ 31

2010/09/ 03 2012/12/ 31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

B

B

B

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

Cover Page

Cover Page

PWWHA LA-7202P M/B

PWWHA LA-7202P M/B

PWWHA LA-7202P M/B

1 43Friday, February 25, 2011

1 43Friday, February 25, 2011

1 43Friday, February 25, 2011

E

1.0

1.0

1.0

A

B

C

D

E

Intel CPU
Sandy Bridge

1 1

CRT

page 14

rPGA-989

37.5mm*37.5mm

page 5,6,7,8,9,10

FDI X8

2.7GT/s

DMI X4

5GT/s

LVDS Conn.

page 13

2 2

Intel PCH

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 1066/1333/1600 MT/s

USB/B Left

USB port 0,1

USB

5V 480MHz

page 24

PCIeMini Card

USB

5V 480MHz

PCIe 1x

1.5V 5GT/s

WiMax

USB port 9

PCIeMini Card
WLAN

PCIe port 2

200pin DDRIII-SO-DIMM X2

page 11,12

Int. Camera

USB port 11

page 25

page 25

BANK 0, 1, 2, 3

2IN1 RTS5137

USB port 10

page 27

page 13

Cougar Point - M

RJ45

page 26

3 3

RTL8105E 10/100M

PCIe port 1

page 26

PCIe 1x

1.5V 5GT/s

FCBGA-989

25mm*25mm

page 15,16,17,18,19,20,21,22,23

SATA port 0

5V 6GHz(600MB/s)

SATA port 2

5V 3GHz(300MB/s)

SATA HDD

SATA port 1

page 24

SATA ODD

SATA port 4

page 24

LPC BUS

3.3V 33 MHz

HD Audio

3.3V 24MHz

HDA Codec

SPI ROM
(4MB)

page 15

Debug Port

page 31

ENE KB930

page 30

ALC259

page 28

RTC CKT.

page 16

DC/DC Interface CKT.

page 33

4 4

Touch Pad

page 32

Int.KBD

page 32

EC ROM
(128KB)

page 31

Int.

MIC Conn

SPK Conn

page 29page 29

HP & MIC

page 29

Power Circuit DC/DC

page 34,35,36,37,38,39
,40,41

Power/B
DA40000XR10

page 32

A

B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/09/03 2012/12/31

2010/09/03 2012/12/31

2010/09/03 2012/12/31

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

Block Diagram

Block Diagram

PWWHA LA-7202P M/B

PWWHA LA-7202P M/B

PWWHA LA-7202P M/B

2 43Wednesday, March 02, 2011

2 43Wednesday, March 02, 2011

2 43Wednesday, March 02, 2011

E

1.0

1.0

1.0

5

B+

SY8033BDBC

4

Ipeak=5A, Imax=3.5A, Iocp min=7.9A

SUSP#

3

DESIGN CURRENT 0.1A

DESIGN CURRENT 5A

DESIGN CURRENT 2A

+3VL

+5VALW

+1.8VS

2

1

SUSP

D D

N-CHANNEL

SI4800

ODD_EN#

P-CHANNEL

AO-3413

DESIGN CURRENT 4A

DESIGN CURRENT 1.8A

+5VS

+5VS_ODD

TPS51125ARGER

Ipeak=5A, Imax=3.5A, Iocp min=7.7A

C C

SUSP

N-CHANNEL

SI4800

WOL_EN#

P-CHANNEL

AO-3413

P-CHANNEL

AO-3413

LCD_ENVDD

DESIGN CURRENT 5A

DESIGN CURRENT 330mA

DESIGN CURRENT 4A

DESIGN CURRENT 1.5A

+3VALW

+3V_LAN

+3VS

+LCD_VDD

VR_ON

ISL95831HRTZ-T

Ipeak=94A, Imax=52A, Iocp min=122A

Ipeak=33A, Imax=21.5A, Iocp min=40A

DESIGN CURRENT 94A

DESIGN CURRENT 33A

+CPU_CORE

+GFX_CORE

SUSP#

B B

TPS51117RGYR

Ipeak=17A, Imax=11.9A, Iocp min=19.23A

DESIGN CURRENT 15A

+1.05VS_VCCP

VCCPPWRGD

TPS51117RGYR

SYSON

TPS51117RGYR

Ipeak=6A, Imax=4.2A, Iocp min=7A

Ipeak=9A, Imax=6.3A, Iocp min=9.92A

SUSP

N-CHANNEL

FDS6676AS

SUSP

N-CHANNEL

SI4800

+3V

APL5930KAI-TRG

A A

0.75VR_EN#

UP7711U8

DESIGN CURRENT 6A

DESIGN CURRENT 10A

DESIGN CURRENT 2A

DESIGN CURRENT 2A

DESIGN CURRENT 1A

DESIGN CURRENT 1.5A

+VCCSA

+1.5V

+1.5V_CPU

+1.5VS

+1.05V

+0.75VS

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/03 2012/12/31

2010/09/03 2012/12/31

2010/09/03 2012/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Power Tree

Power Tree

Power Tree

PWWHA LA-7202P M/B

PWWHA LA-7202P M/B

PWWHA LA-7202P M/B

1

1.0

1.0

3 43Friday, February 25, 2011

3 43Friday, February 25, 2011

3 43Friday, February 25, 2011

1.0

A

B

C

D

E

Voltage Rails

State

power
plane

1 1

( O MEANS ON X MEANS OFF )

+RTCVCC

B+

+3VL

+5VALW

+3VALW

+VSB

+1.5V

+5VS

+3VS

+1.8VS

+1.5VS

+1.05VS

+0.75VS

+CPU_CORE

+GFX_CORE

BTO Option Table

Function

S0

S1

2 2

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

O

O

O

O

O

O

O

O

O

O

O

X

O

O

O

O

O

X

O

O

O

O

X

X

O

X X

X

X X

OO

OO

X

X

description

explain

BTO

MINI PCI-E SLOT

SLOT1 LAN

WIMAX

WIMAX@

LAN

10/100M Giga

8105E@ 8111E@

Camera & Mic

Camera & Mic

Camera & Mic

CAM@

FAN

FAN

PWM RPM

PWM@ RPM@

S3 Power Saving

S3 Power Saving

1.5V 1.5VS

WPS3@ PS3@

Load Power Switch

Load Power Switch

Old Sch. New Sch.

OLS@ NLS@

PCH SM Bus Address

HEX

A0 H

D2 H

0001 0110 bSmart Battery

Address

1010 0000 b

1010 0100 bA4 H

1101 0010 b

PowerPower

+3VS

EC SM Bus2 Address

Device

96 H

1001 0110 bPCH

B

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

G3 LOW LOWLOW

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/09/03 2012/12/31

2010/09/03 2012/12/31

2010/09/03 2012/12/31

C

SIGNAL

SLP_S3# SLP_S4# SLP_S5#

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

HIGH HIGHHIGH

HIGH HIGHHIGH

LOW

HIGH

LOW LOW

LOW LOWLOW

HIGH

HIGH

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Notes List

Notes List

Notes List

PWWHA LA-7202P M/B

PWWHA LA-7202P M/B

PWWHA LA-7202P M/B

4 43Friday, February 25, 2011

4 43Friday, February 25, 2011

4 43Friday, February 25, 2011

E

1.0

1.0

1.0

Power

+3VS

3 3

+3VS

+3VS

+3VS

Device

DDR SO-DIMM 0

DDR SO-DIMM 1

Clock Generator

WLAN/WIMAX

EC SM Bus1 Address

Device Address Address

+3VL

4 4

A

HEX HEX

16 H

5

@

@

PM_DRAM_PWR GD_R

C4871000P_0402_50V7K

C4871000P_0402_50V7K

12

@

@

12

D D

+1.05VS_VCCP

R47 62_0402_5%R47 62_0402_5%

R51 10K_0402_5%R51 10K_0402_5%

12

12

C4881000P_0402_50V7K

C4881000P_0402_50V7K

H_PWRGOOD

H_PROCHOT#

H_PWRGOOD

H_PROCHOT#<30,35>

H_THERMTRIP#<20>

Remove R14 (o ohm) fo r HW Revi ew demand

H_PM_SYNC< 17>

H_PWRGOOD<20>

C C

+3VALW

1

C93

C93

0.1U_0402_16V4Z

0.1U_0402_16V4Z

PS3@

PS3@

2

U10

U10
74AHC1G09GW_TSSOP5

R312

R312

0_0402_5%

0_0402_5%

PM_PWROK<17,30>

DRAMPWROK<17>

B B

1 2

PS3@

PS3@

R384 0_0402_5%

R384 0_0402_5%

74AHC1G09GW_TSSOP5

5

PS3@

PS3@

1

P

B

2

A

G

3

1 2

WPS3@

WPS3@

SUSP<9,25,33,40>

PM_SYS_PWRGD_BUF

4

O

SUSP

+1.5V_CPU

12

R340

R340
39_0402_5%

39_0402_5%

@

@

13

D

D

Q5

Q5
2N7002_SOT23

2N7002_SOT23

2

G

@

G

@

S

S

Buffered Reset to CPU

+3VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C84

C84

PLT_RST# <19,25,26,30,31>

U3

PLT_RST#

A A

U3

1

OE#

2

IN

3

GND

74AHC1G125GW_SOT353-5

74AHC1G125GW_SOT353-5

5

2

5

VCC

BUFO_CPU_RST# BUF _CPU_RST#

4

OUT

+1.05VS_VCCP

12

R69

R69
75_0402_5%

75_0402_5%

43_0402_1%

43_0402_1%

1 2

R155

R155

12

R209

R209
0_0402_5%

0_0402_5%

@

@

H_SNB_IVB#<19>

12

R339

R339
200_0402_5%

200_0402_5%

4

H_PECI<30>

4

H_SNB_IVB#

R450

R450

1 2

BUF_CPU_RST#

PBTN_OUT#< 17,30>

CLK_CPU_ITP<16>
CLK_CPU_ITP#<16>
+1.05VS_VCCP

TP_SKTOCC#

H_CATERR#

H_PECI

H_PROCHOT#_R

56_0402_5%

56_0402_5%

H_THERMTRIP#

H_PM_SYNC

H_PWRGOOD

PM_DRAM_PWR GD_RPM_SYS_PWRGD_BUF

CFG0<10>

VGATE<17,30,41>

T1 PADT1 P AD

T2 PADT2 P AD

1 2

R454 130_0402_5%R454 130_0402_5%

JCPUB

JCPUB

PROC_SELECT#

C26

SNB_IVB#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWR OK

AR33

RESET#

Sandy Bridge_rPGA_Rev0p61

Sandy Bridge_rPGA_Rev0p61

XDP Connector

H_PWRGOOD XDP_CPU_HOOK0
PBTN_OUT#
CFG0
VGATE

C8

C8

0.1U_0402_10V6K

0.1U_0402_10V6K

@

@

PLT_RST#

1

2

R35 1K_0402_5%@R35 1K_0402_5%@

1 2

R152 0_0402_5%@R152 0_0402_5%@

1 2

R37 1K_0402_5%@R37 1K_0402_5%@

1 2

R451 0_0402_5%@R451 0_0402_5%@

1 2

@

@

1 2

R40 1K_0402_5%

R40 1K_0402_5%

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MISCTHERMALPWR MANAGEMENT

MISCTHERMALPWR MANAGEMENT

XDP_PREQ#
XDP_PRDY#

XDP_BPM#0
XDP_BPM#1

XDP_BPM#2
XDP_BPM#3

Issued Date

Issued Date

Issued Date

3

CLOCKS

CLOCKS

DDR3

DDR3

JTAG & BPM

JTAG & BPM

XDP_CPU_HOOK1
XDP_CPU_HOOK2
XDP_CPU_HOOK3
CLK_CPU_ITP
CLK_CPU_ITP#

XDP_CPU_HOOK6
XDP_DBRESET#

XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS

XDP_TCK

2

100 MHz

CLK_CPU_DMI

BCLK

BCLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

MISC

MISC

PRDY#

PREQ#

TMS

TRST#

TDO

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

TCK

TDI

@

@

A28
A27

120 MHz

A16
A15

R8

AK1
A5
A4

AP29
AP27

AR26
AR27
AP30

AR28
AP26

AL35

AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32

CLK_CPU_DMI#

CLK_CPU_DPLL
CLK_CPU_DPLL#

H_DRAMRST#

SM_RCOMP_0

R1437 140_0402_1%R1437 140_0402_1%

SM_RCOMP_1

R1438 25.5_0402_1%R1438 25.5_0402_1%

SM_RCOMP_2

R1439 200_0402_1%R1439 200_0402_1%

XDP_PRDY#_R
XDP_PREQ#_R

XDP_TCK_R
XDP_TMS_R
XDP_TRST#_R

XDP_TDI_R
XDP_TDO_R

XDP_DBRESET#_R

XDP_BPM#0_R
XDP_BPM#1_R
XDP_BPM#2_R
XDP_BPM#3_R

CLK_CPU_DMI <16>
CLK_CPU_DMI# <16>

H_DRAMRST# <7>

12
12
12

R1 0_0402_5%@R1 0_0402_5%@

1 2

R2 0_0402_5%@R2 0_0402_5%@

1 2

R4 0_0402_5%@R4 0_0402_5%@

1 2

R6 0_0402_5%@R6 0_0402_5%@

1 2

R7 0_0402_5%@R7 0_0402_5%@

1 2

R8 0_0402_5%@R8 0_0402_5%@

1 2

R10 0_0402_5%@R10 0_0402_5%@

1 2

R11 0_0402_5%@R11 0_0402_5%@

1 2

R12 0_0402_5%@R12 0_0402_5%@

1 2

R13 0_0402_5%@R13 0_0402_5%@

1 2

R15 0_0402_5%@R15 0_0402_5%@

1 2

R18 0_0402_5%@R18 0_0402_5%@

1 2

Close to CPU side

FAN Control Circuit (RPM and PWM)

C3

C3

10U_0805_10V6K

10U_0805_10V6K

PWM@

PWM@

+FAN2

10mil

+5VS

2

1

2

EN_DFAN1<30>

JXDP

@JXDP

@

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

27
28

MOLEX 52435-2671

MOLEX 52435-2671

Compal Secret Data

Compal Secret Data

2010/09/03 2012/12/31

2010/09/03 2012/12/31

2010/09/03 2012/12/31

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

+5VS

1

C15

C15
10U_0805_10V6K

10U_0805_10V6K

2

1A

1 2

1A

U1

U1

1

EN

2

VIN

3

VOUT

4

VSET

APL5607KI-TRG_SO8

APL5607KI-TRG_SO8

RPM@

RPM@

RPM@

RPM@

FAN_SPEED1<30>

R154

R154

0_0603_5%

0_0603_5%

PWM@

PWM@

Stuff R41 and R42 if do not support eDP

DDR3 Compensati on Signals
Layout Note:Pla ce these
resistors near Processor

XDP_PRDY#
XDP_PREQ#

XDP_TCK
XDP_TMS
XDP_TRST#

XDP_TDI
XDP_TDO

XDP_DBRESET#

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3

40 mil

+FAN1

Routed as a sin gle daisy chai n

1 2

1K_0402_5%

1K_0402_5%

2

C12

C12

10U_0805_10V6K

10U_0805_10V6K

RPM@

RPM@

1

8

GND

7

GND

6

GND

5

GND

+3VS

12

R3

R3
10K_0402_5%

10K_0402_5%

PWM@

PWM@

1

C6

C6

0.01U_0402_25V7K

0.01U_0402_25V7K

@

@

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

CLK_CPU_DPLL#

CLK_CPU_DPLL

R36

R36

R42 1K_0402_5%R42 1K_04 02_5%

R41 1K_0402_5%R41 1K_04 02_5%

+3VS

XDP_DBRESET# <17>

1 2

1 2

PU/PD for JTAG signals

XDP_TMS_R

XDP_TDI_R

XDP_TDO

XDP_TCK_R

XDP_TRST#_R

R28 51_0402_5%R28 51_0402_5%

R29 51_0402_5%R29 51_0402_5%

R30 51_0402_5%R30 51_0402_5%

R31 51_0402_5%R31 51_0402_5%

R32 51_0402_5%R32 51_0402_5%

01/24 pin define change by Thermal

+FAN2

2

C14

C14
1000P_0402_50V7K

1000P_0402_50V7K

@

@

1

R14 10K_0402_5% R PM@R14 10K_0402_5% R PM@

1

C13

C13

0.01U_0402_25V7K

0.01U_0402_25V7K

@

@

2

D86

D86

PWM@

PWM@

FANPWM

12

10U_0805_10V6K

10U_0805_10V6K

2

1

FANPWM<30>

+FAN1

PWM@

PWM@

+5VS

D57 1SS355_SOD32 3-2

D57 1SS355_SOD32 3-2

1 2

BAS16_SOT23-3

BAS16_SOT23-3

Close to Connector

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Sandy Bridge_JTAG/XDP/FAN

Sandy Bridge_JTAG/XDP/FAN

Sandy Bridge_JTAG/XDP/FAN

PWWHA LA-7202P M/B

PWWHA LA-7202P M/B

PWWHA LA-7202P M/B

1

+1.05VS_VCCP

+1.05VS_VCCP

12

12

12

12

12

JFAN2

1

1

2

2

3

3

4

GND

5

GND

ACES_85204-0300N

ACES_85204-0300N

12

FAN_SPEED1

1
2
3
4

ACES_85204-0400N

ACES_85204-0400N

1000P_0402_50V7K

1000P_0402_50V7K

1

C4

C4

PWM@

PWM@

2

5 43Friday, February 25, 2011

5 43Friday, February 25, 2011

5 43Friday, February 25, 2011

@JFAN2

@

+3VS

JFAN

JFAN

1
2
3
4

@

@

C379

C379

PWM@

PWM@

1.0

1.0

1.0

5

4

3

2

1

+1.05VS_VCCP

R34

R34

24.9_0402_1%

JCPUA

D D

DMI_PTX_CRX_N0<17>
DMI_PTX_CRX_N1<17>
DMI_PTX_CRX_N2<17>
DMI_PTX_CRX_N3<17>

DMI_PTX_CRX_P0<17>
DMI_PTX_CRX_P1<17>
DMI_PTX_CRX_P2<17>
DMI_PTX_CRX_P3<17>

DMI_CTX_PRX_N0<17>
DMI_CTX_PRX_N1<17>
DMI_CTX_PRX_N2<17>
DMI_CTX_PRX_N3<17>

DMI_CTX_PRX_P0<17>
DMI_CTX_PRX_P1<17>
DMI_CTX_PRX_P2<17>
DMI_CTX_PRX_P3<17>

FDI_CTX_PRX_N0<17>
FDI_CTX_PRX_N1<17>
FDI_CTX_PRX_N2<17>

C C

+1.05VS_VCCP

B B

+1.05VS_VCCP

FDI_CTX_PRX_N3<17>
FDI_CTX_PRX_N4<17>
FDI_CTX_PRX_N5<17>
FDI_CTX_PRX_N6<17>
FDI_CTX_PRX_N7<17>

FDI_CTX_PRX_P0<17>
FDI_CTX_PRX_P1<17>
FDI_CTX_PRX_P2<17>
FDI_CTX_PRX_P3<17>
FDI_CTX_PRX_P4<17>
FDI_CTX_PRX_P5<17>
FDI_CTX_PRX_P6<17>
FDI_CTX_PRX_P7<17>

FDI_FSYNC0<17>
FDI_FSYNC1<17>

FDI_INT<17>

FDI_LSYNC0<17>
FDI_LSYNC1<17>

R9 24.9_0402_1%R9 24.9_0402_1%

1 2

R33 10K_0402_5%R33 10K_0402_5%

12

DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3

DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_FSYNC0
FDI_FSYNC1

FDI_INT

FDI_LSYNC0
FDI_LSYNC1

EDP_COMP

Reserve R33 for HW Review demand

eDP_COMP signals should be
shorted near balls and
routed with typical
impedance <25m ohm

JCPUA

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

Sandy Bridge_rPGA_Rev0p61

Sandy Bridge_rPGA_Rev0p61

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]

PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PCI EXPRESS* - GRAPHICS

PCI EXPRESS* - GRAPHICS

PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]

PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]

PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[10]

PEG_TX[11]

PEG_TX[12]

PEG_TX[13]

PEG_TX[14]

PEG_TX[15]

DMI

DMI

Intel(R) FDI

Intel(R) FDI

eDP

eDP

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]

J22
J21
H22

K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32

J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32

M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25

M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25

@

@

PEG_COMP

24.9_0402_1%

PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical

12

impedance = 43 m ohm (4 mils)
PEG_ICOMPO signals should be routed with ­max length = 500 mils

- typical impedance = 14.5 m ohm (12 mils)

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2010/09/03 2012/12/31

2010/09/03 2012/12/31

2010/09/03 2012/12/31

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Sandy Bridge_DMI/PEG/FDI

Sandy Bridge_DMI/PEG/FDI

Sandy Bridge_DMI/PEG/FDI

PWWHA LA-7202P M/B

PWWHA LA-7202P M/B

PWWHA LA-7202P M/B

6 43Friday, February 25, 2011

6 43Friday, February 25, 2011

6 43Friday, February 25, 2011

1

1.0

1.0

1.0

5

JCPUC

G10

M10

AG6
AG5
AK6
AK5
AH5
AH6

AK8

AK9
AH8
AH9

AP11

AN11

AL12
AM12
AM11

AL11

AP12
AN12

AJ14
AH14

AL15

AK15

AL14

AK14

AJ15
AH15

AE10

AF10

AE8
AD9

JCPUC

C5

SA_DQ[0]

D5

SA_DQ[1]

D3

SA_DQ[2]

D2

SA_DQ[3]

D6

SA_DQ[4]

C6

SA_DQ[5]

C2

SA_DQ[6]

C3

SA_DQ[7]

F10

SA_DQ[8]

F8

SA_DQ[9]
SA_DQ[10]

G9

SA_DQ[11]

F9

SA_DQ[12]

F7

SA_DQ[13]

G8

SA_DQ[14]

G7

SA_DQ[15]

K4

SA_DQ[16]

K5

SA_DQ[17]

K1

SA_DQ[18]

J1

SA_DQ[19]

J5

SA_DQ[20]

J4

SA_DQ[21]

J2

SA_DQ[22]

K2

SA_DQ[23]

M8

SA_DQ[24]

N10

SA_DQ[25]

N8

SA_DQ[26]

N7

SA_DQ[27]
SA_DQ[28]

M9

SA_DQ[29]

N9

SA_DQ[30]

M7

SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]

AJ5

SA_DQ[38]

AJ6

SA_DQ[39]

AJ8

SA_DQ[40]
SA_DQ[41]

AJ9

SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]

AL9

SA_DQ[46]

AL8

SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]

V6

SA_BS[2]

SA_CAS#
SA_RAS#

AF9

SA_WE#

DDR_A_D[0..63]<11>

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3

D D

C C

B B

DDR_A_BS0<11>
DDR_A_BS1<11>
DDR_A_BS2<11>

DDR_A_CAS#<11>
DDR_A_RAS#<11>

DDR_A_WE#< 11>

DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#

4

DDRA_CLK0

AB6

SA_CLK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CLK[1]

SA_CLK#[1]

SA_CKE[1]

SA_CLK[2]

SA_CLK#[2]

SA_CKE[2]

SA_CLK[3]

SA_CLK#[3]

SA_CKE[3]

SA_CS#[0]
SA_CS#[1]
SA_CS#[2]
SA_CS#[3]

SA_ODT[0]

SA_ODT[1]
SA_ODT[2]
SA_ODT[3]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

DDRA_CLK0#

AA6

DDRA_CKE0

V9

DDRA_CLK1 DDRB_ CLK1

AA5

DDRA_CLK1# DDRB_ CLK1#

AB5

DDRA_CKE1 DDRB_CKE1

V10

AB4
AA4
W9

AB3
AA3
W10

DDRA_SCS0# DDRB_SCS0#

AK3

DDRA_SCS1#

AL3
AG1
AH1

DDRA_ODT0 DDRB_ODT0

AH3

DDRA_ODT1

AG3
AG2
AH2

DDR_A_DQS#0

C4

DDR_A_DQS#1

G6

DDR_A_DQS#2

J3

DDR_A_DQS#3

M6

DDR_A_DQS#4

AL6

DDR_A_DQS#5

AM8

DDR_A_DQS#6

AR12

DDR_A_DQS#7

AM15

DDR_A_DQS0

D4

DDR_A_DQS1

F6

DDR_A_DQS2

K3

DDR_A_DQS3

N6

DDR_A_DQS4

AL5

DDR_A_DQS5

AM9

DDR_A_DQS6

AR11

DDR_A_DQS7

AM14

DDR_A_MA0

AD10

DDR_A_MA1

W1

DDR_A_MA2

W2

DDR_A_MA3

W7

DDR_A_MA4

V3

DDR_A_MA5

V2

DDR_A_MA6

W3

DDR_A_MA7

W6

DDR_A_MA8

V1

DDR_A_MA9

W5

DDR_A_MA10

AD8

DDR_A_MA11

V4

DDR_A_MA12

W4

DDR_A_MA13

AF8

DDR_A_MA14

V5

DDR_A_MA15

V7

DDRA_CLK0 <11> DDRB_CLK0 <12>
DDRA_CLK0# <11>
DDRA_CKE0 <11> DDRB_CKE0 <12>

DDRA_CLK1 <11>
DDRA_CLK1# <11> DDRB_CLK1# <12>
DDRA_CKE1 <11>

DDRA_SCS0# <11>
DDRA_SCS1# <11> DDRB_SCS1# <12>

DDRA_ODT0 <1 1> DDRB_ODT0 <12>
DDRA_ODT1 <1 1> DDRB_ODT1 <12>

DDR_A_DQS#[0..7] <11>

DDR_A_DQS[0..7] <11>

DDR_A_MA[0..15] <11>

3

JCPUD

D10

K10

AM5
AM6
AR3

AP3
AN3
AN2
AN1

AP2

AP5
AN9

AT5

AT6

AP6
AN8
AR6
AR5
AR9

AJ11

AT8

AT9

AH11

AR8

AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15

AA9
AA7

AA10

AB8
AB9

JCPUD

C9
A7

C8
A9
A8
D9
D8

G4

F4

F1
G1
G5

F5

F2
G2

J7
J8

K9

J9

J10

K8

K7
M5

N4

N2

N1
M4

N5
M2
M1

R6

DDR_B_D[0..63]<12>

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_BS0<12>
DDR_B_BS1<12>
DDR_B_BS2<12>

DDR_B_CAS#<12>
DDR_B_RAS#<12>

DDR_B_WE#< 12>

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

2

DDRB_CLK0

AE2

SB_CLK[0]

SB_CLK#[0]

SB_CKE[0]

SB_CLK[1]

SB_CLK#[1]

SB_CKE[1]

SB_CLK[2]

SB_CLK#[2]

SB_CKE[2]

SB_CLK[3]

SB_CLK#[3]

SB_CKE[3]

SB_CS#[0]
SB_CS#[1]
SB_CS#[2]
SB_CS#[3]

SB_ODT[0]
SB_ODT[1]
SB_ODT[2]
SB_ODT[3]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

AD2
R9

AE1
AD1
R10

AB2
AA2
T9

AA1
AB1
T10

AD3
AE3
AD6
AE6

AE4
AD4
AD5
AE5

D7
F3
K6
N3
AN5
AP9
AK12
AP15

C7
G3
J6
M3
AN6
AP8
AK11
AP14

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

DDRB_CLK0#
DDRB_CKE0

DDRB_SCS1#

DDRB_ODT1

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8

DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

1

DDRB_CLK0# <12>

DDRB_CLK1 <12>

DDRB_CKE1 <12>

DDRB_SCS0# <12>

DDR_B_DQS#[0..7] <12>

DDR_B_DQS[0..7] <12>

DDR_B_MA[0..15] <12>

Sandy Bridge_rPGA_Rev0p61

Sandy Bridge_rPGA_Rev0p61

R466

R466

0_0402_5%

0_0402_5%

1 2

WPS3@

WPS3@

D

S

D

S

1 2

13

Q14

Q14
BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

G

G

PS3@

PS3@

2

1

C140

C140

0.047U_0402_25V6K

0.047U_0402_25V6K

PS3@

PS3@

2

H_DRAMRST#<5>

R464

R464

4.99K_0402_1%

A A

DRAMRST_CNTRL_PC H<16>

5

4.99K_0402_1%

DRAMRST_CNTRL

1 2

R463 0_0402_5%

R463 0_0402_5%

PS3@

PS3@

1K_0402_5%

1K_0402_5%

DDR3_DRAMRST#_RH_DRAMRST#

PS3@

PS3@

4

R465

R465

+1.5V

12

@

@

R467

R467
1K_0402_5%

1K_0402_5%

1 2

SM_DRAMRST# <11,12>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/09/03 2012/12/31

2010/09/03 2012/12/31

2010/09/03 2012/12/31

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Sandy Bridge_rPGA_Rev0p61

Sandy Bridge_rPGA_Rev0p61

2

@

@

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Sandy Bridge_DDR3

Sandy Bridge_DDR3

Sandy Bridge_DDR3

PWWHA LA-7202P M/B

PWWHA LA-7202P M/B

PWWHA LA-7202P M/B

7 43Friday, February 25, 2011

7 43Friday, February 25, 2011

7 43Friday, February 25, 2011

1

1.0

1.0

1.0

5

4

3

2

1

+CPU_CORE

D D

C C

B B

A A

JCPUF

JCPUF

94A (Quad Core 45W)
53A (SV 35W)

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

Sandy Bridge_rPGA_Rev0p6 1

Sandy Bridge_rPGA_Rev0p6 1

POWER

POWER

CORE SUPPLY

CORE SUPPLY

5

8.5A

VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30

PEG AND DDR

PEG AND DDR

VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

VCCIO40

VIDALERT#

VIDSCLK

VIDSOUT

VCC_SENSE
VSS_SENSE

VCCIO_SENSE
VSSIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID

SENSE LINES SVID

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9

@

@

22U_0805_6.3V6M

22U_0805_6.3V6M

AH13
AH10

C146

C146

AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11

C147

C147

H14
H12
H11
G14
G13

22U_0805_6.3V6M

22U_0805_6.3V6M

G12
F14
F13
F12
F11
E14
E12

Bottom Socket Cavity x 5

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

J23

H_CPU_SVIDALRT#

AJ29

H_CPU_SVIDCLK

AJ30

H_CPU_SVIDDAT

AJ28

VCCSENSE_R

AJ35

VSSSENSE_R

AJ34

VCCIO_SENSE

B10
A10

R102

R102
0_0402_5%

0_0402_5%

1 2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

C143

C143

C144

C144

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

C145

C145

2

2

12

R70

R70
130_0402_5%

130_0402_5%

R65 0_0402_5%R65 0_0402_5%

1 2

R52 0_0402_5%R52 0_0402_5%

1 2

R105

R105
100_0402_1%

100_0402_1%

@

@

1 2

+1.05VS_VCCP

Close to CPU

4

TOP Socket Cavity x 7

22U_0805_6.3V6M

22U_0805_6.3V6M

1

2

C137

C137

+1.05VS_VCCP+1.05VS_VCCP

1

C136

C136

2

22U_0805_6.3V6M

22U_0805_6.3V6M

12

R68

R68
75_0402_5%

75_0402_5%

+CPU_CORE

R64

R64
100_0402_1%

100_0402_1%

1 2

12

R62

R62
100_0402_1%

100_0402_1%

1

C141

C141

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1 2

R67 43_0402_1%R67 43_0402_1%

1 2

R63 0_0402_5%R63 0_0402_5%

1 2

R66 0_0402_5%R66 0_0402_5%

VCCIO_SENSE <40>

+1.05VS_VCCP Decoupling:
2X 330U (6m ohm), 12X 22U

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C135

C135

2

ESR 9mohm

330U_D2_2V_Y

330U_D2_2V_Y

VR_SVID_ALRT# <4 1>
VR_SVID_CLK <4 1>
VR_SVID_DAT <41>

Pull high resistor on VR side

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

C134

C134

C133

C133

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

330U_D2_2V_Y

330U_D2_2V_Y

1

+

+

C10

C10

C11

C11

2

Close to CPU

VCCSENSE <41>
VSSSENSE < 41>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C142

C142

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

+

+

2

3

+1.05VS_VCCP

1

2

+CPU_CORE Decoupling:
4X 470U (4m ohm), 16X 22U, 10X 10U

Bottom Socket Cavity

+CPU_CORE

10U_0805_10V6K

10U_0805_10V6K

1

C101

C101

2

10U_0805_10V6K

10U_0805_10V6K

+CPU_CORE

C159

C159

22U_0805_6.3V6M

22U_0805_6.3V6M

C102

C102

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C151

C151

2

1

C103

C103

2

10U_0805_10V6K

10U_0805_10V6K

1

C130

C130

2

22U_0805_6.3V6M

22U_0805_6.3V6M

10U_0805_10V6K

10U_0805_10V6K

1

C104

C104

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C129

C129

2

1

C105

C105

2

10U_0805_10V6K

10U_0805_10V6K

Top Socket Edge

1

2

Top Socket Cavity

+CPU_CORE

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C158

C158

C150

C150

2

22U_0805_6.3V6M

22U_0805_6.3V6M

Compal Secret Data

Compal Secret Data

2010/09/03 2012/12/31

2010/09/03 2012/12/31

2010/09/03 2012/12/31

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

1

C128

C128

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C127

C127

2

2

1

2

10U_0805_10V6K

10U_0805_10V6K

1

C106

C106

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C124

C124

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C120

C120

2

22U_0805_6.3V6M

22U_0805_6.3V6M

10U_0805_10V6K

1

C109

C109

2

10U_0805_10V6K

10U_0805_10V6K

1

C125

C125

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

2

10U_0805_10V6K

1

C110

C110

2

1

@

@

2

1

C111

C111

@

@

2

10U_0805_10V6K

10U_0805_10V6K

1

2

C123

C123

C118

C118

1

2

10U_0805_10V6K

10U_0805_10V6K

1

C107

C107

C108

C108

2

10U_0805_10V6K

10U_0805_10V6K

1

1

C122

C122

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

C119

C119

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

C121

C121

22U_0805_6.3V6M

22U_0805_6.3V6M

C117

C117

Bottom Socket Edge

+CPU_CORE

330U_D2_2V_Y

330U_D2_2V_Y

1

1

+

+

C5

C5

C2

C2

330U_D2_2V_Y

330U_D2_2V_Y

2

330U_D2_2V_Y

330U_D2_2V_Y

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Do cument Number Rev

Size Do cument Number Rev

Size Do cument Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PWWHA LA-7202P M/B

PWWHA LA-7202P M/B

PWWHA LA-7202P M/B

1

+

+

+

+

C9

C9

C7

C7

2

2

330U_D2_2V_Y

330U_D2_2V_Y

Sandy Bridge_POWER-1

Sandy Bridge_POWER-1

Sandy Bridge_POWER-1

1

1

+

+

2

330U_D2_2V_Y

330U_D2_2V_Y

1

+

+

C1

C1

2

8 43Friday, February 25, 20 11

8 43Friday, February 25, 20 11

8 43Friday, February 25, 20 11

1.0

1.0

1.0

5

4

3

2

1

+GFX_CORE Decoupling:
1X 560U (10m ohm), 12X 22U

+GFX_CORE

Change C873 from 330uF to 560uF for power issue

Bottom Socket Edge

560U_2.5V_M_R17

560U_2.5V_M_R17

1

1

C267

C267

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

C344

C344

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

C350

C350

@

@

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

ESR 10mohm

22U_0805_6.3V6M

22U_0805_6.3V6M

C271

C271

1

+

+

C873

C873

2

1

C338

C338

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C341

C341

2

1

2

Bottom Socket Edge

22U_0805_6.3V6M

1

C346

C346

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C347

C347

2

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C345

C345

Top Socket Edge

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C391

C391

@

@

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

2

C351

C351

@

@

1

C342

C342

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C348

C348

2

22U_0805_6.3V6M

22U_0805_6.3V6M

D D

22U_0805_6.3V6M

22U_0805_6.3V6M

C266

C266

Bottom Socket
Cavity

22U_0805_6.3V6M

22U_0805_6.3V6M

C343

C343

Top Socket

C C

Cavity

22U_0805_6.3V6M

22U_0805_6.3V6M

C349

C349

@

@

AT24
AT23
AT21
AT20
AT18

AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17

AL24

AL23

AL21

AL20

AL18

AL17
AK24
AK23
AK21
AK20
AK18
AK17

AJ24

AJ23

AJ21

AJ20

AJ18

AJ17
AH24
AH23
AH21
AH20
AH18
AH17

JCPUG

JCPUG

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54

VCCPLL Decoupling:
1X 330U (6m ohm), 1X 10U, 2x1U

+1.8VS

R76

R76

10U_0805_10V6K

10U_0805_10V6K

B B

A A

12

0_0805_5%

0_0805_5%

C185

C185

+

+

@

@

330U_B2_2.5VM_R15M

330U_B2_2.5VM_R15M

1

C186

C186

2

+1.8VS_VCCPLL

1

1

C206

C206

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C230

C230

1U_0402_6.3V6K

1U_0402_6.3V6K

2

1.2A

B6

VCCPLL1

A6

VCCPLL2

A2

VCCPLL3

Sandy Bridge_rPGA_Rev0p61

Sandy Bridge_rPGA_Rev0p61

33A

POWER

POWER

SENSE

SENSE

GRAPHICS

GRAPHICS

1.8V RAIL

1.8V RAIL

VSSAXG_SENSE

LINES

LINES

VREFMISC

VREFMISC

DDR3 -1.5V RAILS

DDR3 -1.5V RAILS

SA RAIL

SA RAIL

VCCSA_SENSE

VCCSA_VID0

VAXG_SENSE

SM_VREF

5A

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

6A

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

FC_C22

VCCSA_VID1

VCC_AXG_SENSE

AK35

VSS_AXG_SENSE

AK34

+V_SM_VREF should
have 20 mil trace width

+V_SM_VREF_CNT +V_SM_VREF

AL1

12

R486

R486

C148

C148

@

@

100K_0402_5%

100K_0402_5%

AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

0_0402_5%

0_0402_5%

2

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

10U_0805_10V6K

10U_0805_10V6K

1

C114

C114

2

10U_0805_10V6K

10U_0805_10V6K

R111

R111

@

@

AP2302GN-HF_SOT23-3

AP2302GN-HF_SOT23-3

1

RUN_ON_CPU1.5VS3

C115

C115

Bottom Socket Cavity

10U_0805_10V6K

1

1

C447

C447

2

2

10U_0805_10V6K

10U_0805_10V6K

10U_0805_10V6K

1

C476

C476

2

M27
M26
L26
J26
J25
J24
H26
H25

10U_0805_10V6K

10U_0805_10V6K

C100

C100

Bottom Socket Edge

VCCSA_SENSE

H23

0_0402_5% @

@

@

C22
C24

VCCSA_VID0

R114

R114

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

1 2

0_0402_5% @

R119

R119

12

3

Q2

Q2

1

C116

C116

2

10U_0805_10V6K

10U_0805_10V6K

10U_0805_10V6K

10U_0805_10V6K

1

1

C154

C154

C149

C149

2

2

10U_0805_10V6K

10U_0805_10V6K

12

+VCCSA Decoupling:
1X 330U (17m ohm), 4X 10U

+VCCSA

1 2

R253 0_0402_5%R253 0_0402_5%

1

1

+

C477

C477

10U_0805_10V6K

10U_0805_10V6K

1 2

1 2

+

C877

C877
330U_2.5V_M_R17

@

@

R95

R95

@

@

330U_2.5V_M_R17

@

@

2

2

VCCSA_SENSE <39>

VCCSAP_VID1 <39>

+1.5V_CPU +1.5V

+GFX_CORE

R74

R74
100_0402_1%

100_0402_1%

1 2

12

R75

R75
100_0402_1%

100_0402_1%

1 2

R252

R252
1K_0402_5%

1K_0402_5%

1

2

+1.5V_CPU Decoupling:
1X 330U (17m ohm), 6X 10U

+1.5V_CPU

10U_0805_10V6K

10U_0805_10V6K

C155

C155

1

2

VCCSA_SENSE

1

+

+

C875

C875
330U_2.5V_M_R17

330U_2.5V_M_R17

ESR 17mohm

2

ESR 17mohm

PS3@

PS3@

C213 0.1U_0402_16V4Z

C213 0.1U_0402_16V4Z

1 2

PS3@

PS3@

C212 0.1U_0402_16V4Z

C212 0.1U_0402_16V4Z

1 2

PS3@

PS3@

C211 0.1U_0402_16V4Z

C211 0.1U_0402_16V4Z

1 2

PS3@

PS3@

C210 0.1U_0402_16V4Z

C210 0.1U_0402_16V4Z

1 2

Close to CPU

VCC_AXG_SENSE <41>
VSS_AXG_SENSE <41>

IF PS3@, short PJ32.

1K_0402_5%

1K_0402_5%
R122

R122

Vgs=10V,Id=14.5A,Rds=6mohm

470_0805_5%

470_0805_5%

SUSP

5

Q46B

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

Q46B

PJ32

PJ32

112

JUMP_43X118

JUMP_43X118

R449

R449

@

@

1 2
3

4

@

@

2

@

@

0

0

1

1 1

1

C179

C179
10U_0805_10V4K

10U_0805_10V4K

@

@

2

0.1U_0402_25V6

0.1U_0402_25V6

+1.5VS

+1.5V_CPU

IF WPS3@, short PJ30.

1

C472

C472

@

@

2

0

1

0

PJ30

2

JUMP_43X118

JUMP_43X118

Q33

1

S

2

S

3

S

4

G

FDS6676AS_SO8

FDS6676AS_SO8

12

+VCCSAVCCSA_VID0 VCCSA_VID1

0.90 V

0.80 V

0.75 V

0.65 V

+1.5V+1.5V_CPU

@PJ30

@

112

@Q33

@

8

D

7

D

6

D

5

D

RUN_ON_CPU1.5VS3

R420

R420
820K_0402_5%

820K_0402_5%

@

@

For Sandy Bridge

R455

@R455

@

1 2

220K_0402_5%

220K_0402_5%

61

SUSP

2

Q46A

Q46A
2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

@

@

+VSB

SUSP <5,25,33,40>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECTRONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECTRONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECTRONICS, INC. AND CONTAINS CON FIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/03 2012/12/31

2010/09/03 2012/12/31

2010/09/03 2012/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Sandy Bridge_POWER-2

Sandy Bridge_POWER-2

Sandy Bridge_POWER-2

PWWHA LA-7202P M/B

PWWHA LA-7202P M/B

PWWHA LA-7202P M/B

1

9 43Friday, February 25, 2011

9 43Friday, February 25, 2011

9 43Friday, February 25, 2011

1.0

1.0

1.0

5

JCPUH

JCPUH

AT35

VSS1

AT32

VSS2

AT29

VSS3

AT27

VSS4

AT25

VSS5

AT22

VSS6

AT19

VSS7

AT16

VSS8

AT13

VSS9

AT10

VSS10

AR25
AR22
AR19
AR16
AR13
AR10

AR7
AR4

AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10

AP7

AP4

AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10

AN7

AN4

AM29
AM25
AM22
AM19
AM16
AM13
AM10

AM7

AM4

AM3

AM2

AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10

AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10

AK7

AK4
AJ25

AT7

VSS11

AT4

VSS12

AT3

VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

AL7

VSS66

AL4

VSS67

AL2

VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

VSS

VSS

D D

C C

B B

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

T35
T34
T33
T32
T31
T30
T29
T28
T27
T26

P9
P8
P6
P5
P3

P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34

L33
L30
L27

L9

L8

L6

L5

L4

L3

L2

L1

K35
K32
K29
K26
J34

J31
H33
H30
H27
H24
H21
H18
H15
H13
H10

H9
H8
H7
H6
H5
H4
H3
H2

H1
G35
G32
G29
G26
G23
G20
G17
G11

F34
F31
F29

JCPUI

JCPUI

VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233

4

VSS

VSS

VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

3

JCPUE

JCPUE

F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

CFG0<5>

T5 PADT5 PAD
T6 PADT6 PAD
T7 PADT7 PAD
T11 PADT11 PAD
T12 PADT12 PAD
T15 PADT15 PAD
T18 PADT18 PAD
T16 PADT16 PAD
T19 PADT19 PAD
T21 PADT21 PAD
T20 PADT20 PAD
T44 PADT44 PAD
T45 PADT45 PAD
T46 PADT46 PAD
T47 PADT47 PAD
T26 PADT26 PAD
T27 PADT27 PAD

T22 PADT22 PAD
T24 PADT24 PAD
T25 PADT25 PAD
T23 PADT23 PAD

R115

R115

1K_0402_1%

1K_0402_1%

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17

CPU_RSVD6
CPU_RSVD7

12

12

R116

R116
1K_0402_1%

1K_0402_1%

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

RSVD1

AH31

RSVD2

AJ33

RSVD3

AH33

RSVD4

AJ26

RSVD5

SA_DIMM_VREFDQ

B4

RSVD6

D1

RSVD7

SB_DIMM_VREFDQ

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

A19

RSVD26

VCCIO_SEL

J15

RSVD27

Sandy Bridge_rPGA_Rev0p61

Sandy Bridge_rPGA_Rev0p61

RESERVED

RESERVED

RSVD28
RSVD29
RSVD30
RSVD31
RSVD32

RSVD33
RSVD34
RSVD35

RSVD37
RSVD38
RSVD39
RSVD40

RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

RSVD46
RSVD47
RSVD48
RSVD49
RSVD50

RSVD51
RSVD52

RSVD53

RSVD54
RSVD55

RSVD56
RSVD57
RSVD58

L7
AG7
AE7
AK2
W8

AT26
AM33
AJ27

T8
J16
H16
G16

2

CFG Straps for Processor

(CFG[17:0] internal pull high to VCCIO)

CFG2

12

R254

R254
1K_0402_1%

1K_0402_1%

@

@

PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane # definition matches
socket pin map definition

*

CFG2

1

0:Lane Reversed

AR35
AT34
AT33
AP35
AR34

B34
A33
A34
B35
C35

AJ32
AK32

AH27

AN35
AM35

AT2
AT1
AR1

B1

KEY

@

@

T28 PADT28 PAD

CLK_RES_ITP <16>
CLK_RES_ITP# <1 6>

PCIE Port Bifurcation Straps

CFG[6:5]

CFG4

12

R255

R255
1K_0402_1%

1K_0402_1%

@

@

Embedded Display Port Presence Strap

1 : Disabled; No Physical Display Port
attached to Embedded Display Port

*

CFG4

11: (Default) x16 - Device 1 functions 1 and 2 disabled

*

10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled

01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

CFG6

CFG5

1K_0402_1%

1K_0402_1%

R257

R257

12

12

R256

R256
1K_0402_1%

1K_0402_1%

@

@

@

@

Sandy Bridge_rPGA_Rev0p61

Sandy Bridge_rPGA_Rev0p61

@

@

Sandy Bridge_rPGA_Rev0p61

Sandy Bridge_rPGA_Rev0p61

@

@

CFG7

12

R258

R258
1K_0402_1%

1K_0402_1%

@

@

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB
de assertion

CFG7

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/03 2012/12/31

2010/09/03 2012/12/31

2010/09/03 2012/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

0: PEG Wait for BIOS for training

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Sandy Bridge_GND/RSVD/CFG

Sandy Bridge_GND/RSVD/CFG

Sandy Bridge_GND/RSVD/CFG

PWWHA LA-7202P M/B

PWWHA LA-7202P M/B

PWWHA LA-7202P M/B

1.0

1.0

10 43Friday, February 25, 2011

10 43Friday, February 25, 2011

1

10 43Friday, February 25, 2011

1.0

5

+VREF_DQA

1

C157

C157

C156

C156

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

D D

Close to JDDRL.1

C C

B B

A A

+3VS

C181

C181

DDR_A_BS2<7>

DDRA_CLK0<7>
DDRA_CLK0#<7>

DDR_A_BS0<7>

DDR_A_WE#<7>

DDR_A_CAS#<7>

DDRA_SCS1#<7>

1

C182

C182

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

R90

R90
10K_0402_5%

10K_0402_5%

1

2

5

DDR_A_D0
DDR_A_D1

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_D26
DDR_A_D27

DDRA_CKE0

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

DDRA_CLK0
DDRA_CLK0#

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13
DDRA_SCS1#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59

1 2

+0.75VS

12

R91

R91
10K_0402_5%

10K_0402_5%

+1.5V

JDDRL

JDDRL

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

GND2

FOX_AS0A626-U2SN-7F_204P

FOX_AS0A626-U2SN-7F_204P

@

@

VSS
DQ4
DQ5

VSS

DQS0#

DQS0

VSS
DQ6
DQ7

VSS

DQ12
DQ13

VSS
DM1

RESET#

VSS

DQ14
DQ15

VSS

DQ20
DQ21

VSS
DM2

VSS

DQ22
DQ23

VSS

DQ28
DQ29

VSS

DQS3#

DQS3

VSS

DQ30
DQ31

VSS

CKE1

VDD

A15

A14
VDD

A11

VDD

VDD

VDD

CK1

CK1#

VDD

BA1

RAS#

VDD

S0#

ODT0

VDD

ODT1

VDD

VREF_CA

VSS

DQ36
DQ37

VSS
DM4

VSS

DQ38
DQ39

VSS

DQ44
DQ45

VSS

DQS5#

DQS5

VSS

DQ46
DQ47

VSS

DQ52
DQ53

VSS
DM6

VSS

DQ54
DQ55

VSS

DQ60
DQ61

VSS

DQS7#

DQS7

VSS

DQ62
DQ63

VSS

EVENT#

SDA

SCL

VTT

BOSS1
BOSS2

A7

A6
A4

A2
A0

NC

4

+1.5V

2

DDR_A_D4

4

DDR_A_D5

6
8

DDR_A_DQS#0

10

DDR_A_DQS0

12
14

DDR_A_D6

16

DDR_A_D7

18
20

DDR_A_D12

22

DDR_A_D13

24
26
28

SM_DRAMRST#

30
32

DDR_A_D14

34

DDR_A_D15

36
38

DDR_A_D20

40

DDR_A_D21

42
44
46
48

DDR_A_D22

50

DDR_A_D23

52
54

DDR_A_D28

56

DDR_A_D29

58
60

DDR_A_DQS#3

62

DDR_A_DQS3

64
66

DDR_A_D30

68

DDR_A_D31

70
72

DDRA_CKE1

74
76

DDR_A_MA15

78

DDR_A_MA14

80
82

DDR_A_MA11

84

DDR_A_MA7

86
88

DDR_A_MA6

90

DDR_A_MA4

92
94

DDR_A_MA2

96

DDR_A_MA0

98
100

DDRA_CLK1

102

DDRA_CLK1#

104
106

DDR_A_BS1

108

DDR_A_RAS#

110
112

DDRA_SCS0#

114

DDRA_ODT0

116
118

DDRA_ODT1

120
122
124

+VREF_CAA

126
128

DDR_A_D36

130

DDR_A_D37

132
134
136
138

DDR_A_D38

140

DDR_A_D39

142
144

DDR_A_D44

146

DDR_A_D45

148
150

DDR_A_DQS#5

152

DDR_A_DQS5

154
156

DDR_A_D46

158

DDR_A_D47

160
162

DDR_A_D52

164

DDR_A_D53

166
168
170
172

DDR_A_D54

174

DDR_A_D55

176
178

DDR_A_D60

180

DDR_A_D61

182
184

DDR_A_DQS#7

186

DDR_A_DQS7

188
190

DDR_A_D62

192

DDR_A_D63

194
196
198

PM_SMBDATA

200

PM_SMBCLK

202
204

+0.75VS

206
208

4

DDR3 SO-DIMM A
Reverse Type

SM_DRAMRST# <7,12>

DDRA_CKE1 <7>DDRA_CKE0<7>

DDRA_CLK1 <7>
DDRA_CLK1# <7>

DDR_A_BS1 <7>
DDR_A_RAS# <7>

DDRA_SCS0# <7>
DDRA_ODT0 <7>

DDRA_ODT1 <7>

1

C161

C161

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

close to JDDRL.126

PM_SMBDATA <12,16,25>
PM_SMBCLK <12,16,25>

1

C162

C162

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

DDR_A_DQS[0..7] <7>

DDR_A_DQS#[0..7] <7>

DDR_A_D[0..63] <7>

DDR_A_MA[0..15] <7>

+1.5V

+VREF_DQA

+1.5V

12

R80

R80

1K_0402_1%

1K_0402_1%

12

R82

R82

1K_0402_1%

1K_0402_1%

Layout Note:
Place near JDDRL

+1.5V

2010/09/03 2012/12/31

2010/09/03 2012/12/31

2010/09/03 2012/12/31

3

@

@

+

+

C218 390U_2.5V_M_R10

C218 390U_2.5V_M_R10

1 2

C166 10U_0603_6.3V6MC166 10U_0603_6.3V6M

1 2

C168 10U_0603_6.3V6MC168 10U_0603_6.3V6M

1 2

C171 10U_0603_6.3V6MC171 10U_0603_6.3V6M

1 2

C174 10U_0603_6.3V6MC174 10U_0603_6.3V6M

1 2

C176 10U_0603_6.3V6MC176 10U_0603_6.3V6M

1 2

C178 10U_0603_6.3V6MC178 10U_0603_6.3V6M

1 2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Layout Note: Place these 4 Caps near
Command and Control signals of DIMMA

+1.5V +0.75VS

2

12

R79

R79

1K_0402_1%

1K_0402_1%

12

R81

R81

1K_0402_1%

1K_0402_1%

C164 0.1U_0402_16V4ZC164 0.1U_0402_16V4Z

1 2

C167 0.1U_0402_16V4ZC167 0.1U_0402_16V4Z

1 2

C170 0.1U_0402_16V4ZC170 0.1U_0402_16V4Z

1 2

C173 0.1U_0402_16V4ZC173 0.1U_0402_16V4Z

1 2

2

1

Layout Note:
Place near JDDRL1.203 and 204

C165 10U_0603_6.3V6MC165 10U_0603_6.3V6M

1 2

C169 1U_0402_6.3V6KC169 1U_0402_6.3V6K

12

C172 1U_0402_6.3V6KC172 1U_0402_6.3V6K

12

C175 1U_0402_6.3V6KC175 1U_0402_6.3V6K

12

C177 1U_0402_6.3V6KC177 1U_0402_6.3V6K

12

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM0

DDRIII-SODIMM0

DDRIII-SODIMM0

PWWHA LA-7202P M/B

PWWHA LA-7202P M/B

PWWHA LA-7202P M/B

11 43Friday, February 25, 2011

11 43Friday, February 25, 2011

11 43Friday, February 25, 2011

1

1.0

1.0

1.0

A

+VREF_DQB

1

C184

C184

C183

C183

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

1 1

2

Close to JDDRH.1

DDRB_CKE0<7>

2 2

3 3

4 4

+3VS

C207

C207

DDR_B_BS2<7>

DDRB_CLK0<7>
DDRB_CLK0#<7>

DDR_B_WE#<7>
DDR_B_CAS#<7>

DDRB_SCS1#<7>

1

1

C208

C208

@

@

@

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

2

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

R98

R98
10K_0402_5%

10K_0402_5%

R99

R99

1 2

10K_0402_5%

10K_0402_5%

A

DDR_B_D0
DDR_B_D1

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_D26
DDR_B_D27

DDRB_CKE0

DDR_B_BS2

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

DDRB_CLK0
DDRB_CLK0#

DDR_B_MA10
DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

DDR_B_MA13
DDRB_SCS1#

DDR_B_D37
DDR_B_D36

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D54
DDR_B_D55

DDR_B_D56
DDR_B_D57

DDR_B_D58
DDR_B_D59

1 2

+0.75VS

+1.5V

JDDRH

JDDRH

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

GND2

FOX_AS0A626-UASN-7F_204P

FOX_AS0A626-UASN-7F_204P

@

@

VSS
DQ4
DQ5

VSS

DQS0#

DQS0

VSS
DQ6
DQ7

VSS

DQ12
DQ13

VSS
DM1

RESET#

VSS

DQ14
DQ15

VSS

DQ20
DQ21

VSS
DM2

VSS

DQ22
DQ23

VSS

DQ28
DQ29

VSS

DQS3#

DQS3

VSS

DQ30
DQ31

VSS

CKE1

VDD

A15

A14
VDD

A11

VDD

VDD

VDD

CK1

CK1#

VDD

BA1

RAS#

VDD

S0#

ODT0

VDD

ODT1

VDD

VREF_CA

VSS

DQ36
DQ37

VSS
DM4

VSS

DQ38
DQ39

VSS

DQ44
DQ45

VSS

DQS5#

DQS5

VSS

DQ46
DQ47

VSS

DQ52
DQ53

VSS
DM6

VSS

DQ54
DQ55

VSS

DQ60
DQ61

VSS

DQS7#

DQS7

VSS

DQ62
DQ63

VSS

EVENT#

SDA

SCL

VTT

BOSS1
BOSS2

A7

A6
A4

A2
A0

NC

B

+1.5V

2

DDR_B_D4

4

DDR_B_D5

6
8

DDR_B_DQS#0

10

DDR_B_DQS0

12
14

DDR_B_D6

16

DDR_B_D7

18
20

DDR_B_D12

22

DDR_B_D13

24
26
28

SM_DRAMRST#

30
32

DDR_B_D14

34

DDR_B_D15

36
38

DDR_B_D20

40

DDR_B_D21

42
44
46
48

DDR_B_D22

50

DDR_B_D23

52
54

DDR_B_D28

56

DDR_B_D29

58
60

DDR_B_DQS#3

62

DDR_B_DQS3

64
66

DDR_B_D30

68

DDR_B_D31

70
72

DDRB_CKE1

74
76

DDR_B_MA15

78

DDR_B_MA14

80
82

DDR_B_MA11

84

DDR_B_MA7

86
88

DDR_B_MA6

90

DDR_B_MA4

92
94

DDR_B_MA2

96

DDR_B_MA0

98
100

DDRB_CLK1

102

DDRB_CLK1#

104
106

DDR_B_BS1

108

DDR_B_RAS#

110
112

DDRB_SCS0#

114

DDRB_ODT0

116
118

DDRB_ODT1

120
122
124

+VREF_CAB

126
128

DDR_B_D32

130

DDR_B_D33

132
134
136
138

DDR_B_D38

140

DDR_B_D39

142
144

DDR_B_D44

146

DDR_B_D45

148
150

DDR_B_DQS#5

152

DDR_B_DQS5

154
156

DDR_B_D46

158

DDR_B_D47

160
162

DDR_B_D52

164

DDR_B_D53

166
168
170
172

DDR_B_D50

174

DDR_B_D51

176
178

DDR_B_D60

180

DDR_B_D61

182
184

DDR_B_DQS#7

186

DDR_B_DQS7

188
190

DDR_B_D62

192

DDR_B_D63

194
196
198

PM_SMBDATA

200

PM_SMBCLK

202
204

206
208

+0.75VS

B

SM_DRAMRST# <7,11>

DDRB_CKE1 <7>

DDRB_CLK1 <7>
DDRB_CLK1# <7>

DDR_B_BS1 <7>
DDR_B_RAS# <7>DDR_B_BS0<7>

DDRB_SCS0# <7>
DDRB_ODT0 <7>

DDRB_ODT1 <7>

C187

C187

Close to JDDRH.126

PM_SMBDATA <11,16,25>
PM_SMBCLK <11,16,25>

Reverse Type
DDR3 SO-DIMM B

1

1

C188

C188

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

DDR_B_DQS#[0..7] <7>

DDR_B_DQS[0..7] <7>

DDR_B_D[0..63] <7>

DDR_B_MA[0..15] <7>

+1.5V

12

R83

R83

1K_0402_1%

1K_0402_1%

+VREF_DQB

+1.5V

12

R86

R86

1K_0402_1%

1K_0402_1%

12

R94

R94

1K_0402_1%

1K_0402_1%

Layout Note:
Place near JDDRH

+1.5V

C192 10U_0603_6.3V6MC192 10U_0603_6.3V6M

1 2

C194 10U_0603_6.3V6MC194 10U_0603_6.3V6M

1 2

C197 10U_0603_6.3V6MC197 10U_0603_6.3V6M

1 2

C200 10U_0603_6.3V6MC200 10U_0603_6.3V6M

1 2

C202 10U_0603_6.3V6MC202 10U_0603_6.3V6M

1 2

C204 10U_0603_6.3V6MC204 10U_0603_6.3V6M

1 2

Compal Secret Data

Compal Secret Data

2010/09/03 2012/12/31

2010/09/03 2012/12/31

2010/09/03 2012/12/31

C

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

12

R84

R84

1K_0402_1%

1K_0402_1%

Layout Note: Place these 4 Caps near
Command and Control signals of DIMMB

D

C190 0.1U_0402_16V4ZC190 0.1U_0402_16V4Z

1 2

C193 0.1U_0402_16V4ZC193 0.1U_0402_16V4Z

1 2

C196 0.1U_0402_16V4ZC196 0.1U_0402_16V4Z

1 2

C199 0.1U_0402_16V4ZC199 0.1U_0402_16V4Z

1 2

D

E

Layout Note:
Place near JDDRH.203 and 204

+0.75VS+1.5V

C191 10U_0603_6.3V6MC191 10U_0603_6.3V6M

1 2

C195 1U_0402_6.3V6KC195 1U_0402_6.3V6K

12

C198 1U_0402_6.3V6KC198 1U_0402_6.3V6K

12

C201 1U_0402_6.3V6KC201 1U_0402_6.3V6K

12

C203 1U_0402_6.3V6KC203 1U_0402_6.3V6K

12

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM1

DDRIII-SODIMM1

DDRIII-SODIMM1

PWWHA LA-7202P M/B

PWWHA LA-7202P M/B

PWWHA LA-7202P M/B

12 43Friday, February 25, 2011

12 43Friday, February 25, 2011

12 43Friday, February 25, 2011

E

1.0

1.0

1.0

A

B

C

D

E

F

G

H

R108

R108

100K_0402_5%

100K_0402_5%

2

5

R112

R112
100K_0402_5%

100K_0402_5%

1 2

+3VS

12

0.1U_0402_16V7K

0.1U_0402_16V7K

R109

R109

1 2

47K_0402_5%

47K_0402_5%

3

0.01U_0402_25V7K

0.01U_0402_25V7K

Q1B

Q1B
2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

4

C228

C228

LCDPWR_GATE

C229

C229

+3VS

2

W=60mils

S

S

Q17

Q17

G

G

1

1

2

AO3413_SOT23

AO3413_SOT23

2

D

D

1 3

+LCD_VDD

W=60mils

1

C233

C233

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

+LCD_VDD

Reserve fo r EMI requ est

@

@

1 2

R78 0_0402_5%

R78 0_0402_5%
L55

CAM@L55

CAM@

USB20_P11<19>

1 1

12

LCD_EDID_CLK

LCD_EDID_DATA

LED_PWM

12

R120

R120
47K_0402_5%

47K_0402_5%

LCD_EDID_CLK<18>

LCD_EDID_DATA<18>

PCH_PWM<18>

D2

D2

RB751V40_SC76-2

RB751V40_SC76-2

Close to LVDS Connector

USB20_N11<19>

1

1

4

4

WCM-2012-900T_0805

WCM-2012-900T_0805

@

@

1 2

R96 0_0402_5%

R96 0_0402_5%

2

3

USB20_P11_R

2

USB20_N11_R

3

UMA_ENVDD<18>

150_0603_5%

150_0603_5%

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

12

R107

R107

61

Q1A

Q1A

UMA_ENVDD

LCD/PANEL BD. Conn.

CAM@

+3VS

2 2

Pin13 is GND pin but LVDS cable is NC.

3 3

1 2

R388 0_0603_5%

R388 0_0603_5%

JLVDS

31

G1

32

G2

33

G3

34

G4

ACES_88341-3001

ACES_88341-3001

@JLVDS

@

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

LCD_EDID_DATA

W=20mils

CAM@

CAM@

+3VS_LVDS_CAM

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C225

C225

USB20_N11_R
USB20_P11_R

INT_MIC_CLK
INT_MIC_DATA

LCD_EDID_CLK

LED_PWM
BKOFF#_R

68P_0402_50V8J

68P_0402_50V8J

CAM@

1 2

2

3

PACDN042Y3R_SOT23-3

PACDN042Y3R_SOT23-3

D1

1 2

R113 10K_0402_5%R113 10K_0402_5%

C234

C234

D1

RB751V40_SC76-2

RB751V40_SC76-2

1 2

+LCD_INV

Rated Current MAX:600mA

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

1

1

C235

C235

0.1U_0402_25V6

0.1U_0402_25V6

2

2

D84

@D84

@

1

LCD_TXOUT0+ <18>

LCD_TXOUT1+ <18>

LCD_TXOUT2+ <18>

LCD_TXCLK+ <18>

12

INT_MIC_CLK <28>

INT_MIC_DATA <28>

LCD_TXOUT0- <18>

LCD_TXOUT1- <18>

LCD_TXOUT2- <18>

LCD_TXCLK- <18>

BKOFF# <30>

B+

L2

L2

For EMI

@

@

C231

C231

680P_0402_50V7K

680P_0402_50V7K

1

2

+LCD_VDD_R

+3VS

1

C232

C232

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1.5A

L15

L15

0_0805_5%

0_0805_5%

1

C226

C226

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

12

1

2

+LCD_VDD

C227

C227

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CON TAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CON TAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CON TAINS CONFIDENTIAL
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2010/09/03 2012/12/31

2010/09/03 2012/12/31

2010/09/03 2012/12/31

E

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

F

Date: Sheet of

Compal Electronics, Inc.

LVDS

LVDS

LVDS

PWWHA LA-7202P M/B

PWWHA LA-7202P M/B

PWWHA LA-7202P M/B

G

1.0

1.0

13 43Friday, February 25, 2011

13 43Friday, February 25, 2011

13 43Friday, February 25, 2011

H

1.0

A

B

C

D

E

CRT CONNECTOR

1

D3

DAN217_ SC59

DAN217_ SC59

1 2

1 2

1 2

1

2

2.2P_0402_50V8C

2.2P_0402_50V8C

2

5

P

A2Y

G

3

1 1

UMA_CRT _R<18>

UMA_CRT _G<1 8>

UMA_CRT _B<18>

R140

R140

R139

R139

R138

R138

12

2 2

UMA_CRT _HSYNC<18>

UMA_CRT _VSYNC<18>

12

12

150_0402_1%

150_0402_1%

150_0402_1%

150_0402_1%

C244 0.1U _0402_16V4ZC244 0.1U _0402_16V4Z

SN74AHC T1G125GW_ SOT353-5

SN74AHC T1G125GW_ SOT353-5

150_0402_1%

150_0402_1%

C238

C238

1 2

1

2

2.2P_0402_50V8C

2.2P_0402_50V8C

+CRT_VC C

5

P

A2Y

G

3

C239

C239

1

L3 NBQ1005 05T-800Y_0402L3 NBQ1005 05T-800Y_0402

L4 NBQ1005 05T-800Y_0402L4 NBQ1005 05T-800Y_0402

L5 NBQ1005 05T-800Y_0402L5 NBQ1005 05T-800Y_0402

1

C240

C240

2

2.2P_0402_50V8C

2.2P_0402_50V8C

4

OE#

+CRT_VC C

U6

U6

SN74AHC T1G125GW_ SOT353-5

SN74AHC T1G125GW_ SOT353-5

1

@D3

@

D4

DAN217_ SC59

DAN217_ SC59

3

2

1

C241

C241

2

2.2P_0402_50V8C

2.2P_0402_50V8C

R141 10K _0402_5%R141 10K _0402_5%

1

4

OE#

U7

U7

D5

@D4

@

DAN217_ SC59

DAN217_ SC59

2

3

1

C242

C242

2

2.2P_0402_50V8C

2.2P_0402_50V8C

12

D_CRT_H SYNC

D_CRT_V SYNC

1

C243

C243

@D5

@

3

+3VS

1

2

2.2P_0402_50V8C

2.2P_0402_50V8C

1 2

L6 10_040 2_5%L6 10_040 2_5%

1 2

L7 10_040 2_5%L7 10_040 2_5%

CRT_R_L

CRT_G_L

CRT_B_L

C246

C246

@

@

If=1A

D6

D6

2

3

+CRT_VC C

HSYNC

VSYNC

1

2

10P_0402_50V8J

10P_0402_50V8J

1

RB491D_ SOT23-3

RB491D_ SOT23-3

CRT_R_L

CRT_DDC _DAT
CRT_G_L

HSYNC
CRT_B_L

VSYNC

CRT_DDC _CLK

F1

F1

21

1.1A_6V_ MINISMDC110F-2

1.1A_6V_ MINISMDC110F-2

T76 PADT76 PAD

T77 PADT77 PAD

+5VS +CRT_VC C_R +CRT_VCC

1

C245

C245

@

@

2

10P_0402_50V8J

10P_0402_50V8J

40 mils

C237

C237

0.1U_040 2_16V4Z

0.1U_040 2_16V4Z

@

@

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

ALLTO_C 10532-11505-L_ 15P-T

ALLTO_C 10532-11505-L_ 15P-T

JCRT

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

1

2

@JCRT

@

16

G

17

G

3 3

+CRT_VC C

+3VS

R153

R153

4.7K_040 2_5%

4.7K_040 2_5%

2

Q205A

UMA_CRT _CLK<18>

UMA_CRT _DATA<18>

33P_040 2_50V8K

33P_040 2_50V8K

4 4

Security Class ification

Security Class ification

Security Class ification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C282

C282

2

@

@

2010/09/ 03 2012/12/ 31

2010/09/ 03 2012/12/ 31

2010/09/ 03 2012/12/ 31

C

Q205A

5

2N7002D W-T/R7_SOT3 63-6

2N7002D W-T/R7_SOT3 63-6

Q205B

Q205B

4

2N7002D W-T/R7_SOT3 63-6

2N7002D W-T/R7_SOT3 63-6

1

C285

C285
33P_040 2_50V8K

33P_040 2_50V8K

2

@

@

61

3

470P_04 02_50V8J

470P_04 02_50V8J

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

C284

C284

@

@

1 2

1 2

1

1

2

2

R159

R159

4.7K_040 2_5%

4.7K_040 2_5%

CRT_DDC _CLK

CRT_DDC _DAT

C283

C283
470P_04 02_50V8J

470P_04 02_50V8J

@

@

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CRT

CRT

CRT

PWWHA LA-7202P M/B

PWWHA LA-7202P M/B

PWWHA LA-7202P M/B

14 43Friday, February 25, 20 11

14 43Friday, February 25, 20 11

14 43Friday, February 25, 20 11

E

of

1.0

1.0

1.0