Compal LA-7201P PWWHA Delhi 10RG, Satellite C660 Schematic

A

1 1

B

C

D

E

PWWHA

2 2

LA-7201P SchematicR

3 3

Intel Processor(Sandy Bridge) / PCH(Cougar Point)

Delhi 10RG

EV 0.1

2010-09-09 Rev 0.1

4 4

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/09/ 03 2012/12/ 31

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Rev

B

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

PWWHA LA-7201P M/B

1 50Tuesday, October 12 , 2010

E

0.1

A

B

C

D

E

Fan Control

Intel CPU

APL5607

page 5

Sandy Bridge

1 1

rPGA-989

37.5mm*37.5mm

page 5,6,7,8,9,10

FDI X8

2.7GT/s

DMI X4

5GT/s

CRT

page 14

2 2

LVDS Conn.

page 13

Intel PCH

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 1066/1333/1600 MT/s

USB/B Left

USB port 0,1

USB

5V 480MHz

page 24

PCIeMini Card

USB

5V 480MHz

PCIe 1x

1.5V 5GT/s

WiMax

USB port 13

PCIeMini Card WLAN

PCIe port 2

200pin DDRIII-SO-DIMM X2

page 11,12

Int. Camera

USB port 11

page 25

BANK 0, 1, 2, 3

2IN1 RTS5137

USB port 10

page 27

page 13

Cougar Point - M

RJ45

page 26

3 3

RTL8105E 10/100M

PCIe port 1

page 26

PCIe 1x

1.5V 5GT/s

FCBGA-989

25mm*25mm

page 15,16,17,18,19,20,21,22,23

SATA port 0

5V 6GHz(600MB/s)

SATA port 2

5V 3GHz(300MB/s)

SATA HDD

SATA port 1

page 24

SATA ODD

SATA port 4

page 24

LPC BUS

3.3V 33 MHz

HD Audio

3.3V 24MHz

HDA Codec

SPI ROM (4MB)

page 15

Debug Port

page 31

ENE KB930

page 30

ALC259

page 28

RTC CKT.

page 16

DC/DC Interface CKT.

page 33

4 4

Touch Pad

page 32

Int.KBD

page 32

EC ROM (128KB)

page 31

Int.

MIC Conn

SPK Conn

page 29page 29

HP Conn

page 29

Power Circuit DC/DC

page 34,35,36,37,38 39,40,41

Power/B

page 32

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/09/03 2012/12/31

C

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

PWWHA LA-7201P M/B

2 50Tuesday, October 12, 2010

E

0.1

5

D D

C C

4

3

2

1

B B

A A

5

4

3

2

1

A

B

C

D

E

Voltage Rails

State

S0

S1

S3

S5 S4/AC

power plane

1 1

2 2

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

PCH SM Bus Address

( O MEANS ON X MEANS OFF )

+RTCVCC

O

B+

O

X

+3VL

O

X

+5VALW

+3VALW

+VSB

O

X

+1.5V

+5VS

+3VS

+1.8VS

+1.5VS

+1.05VS

+0.75VS

+CPU_CORE

+GFX_CORE

O

X X

X

X X

BTO Option Table

Function

description

explain

OO

X

BTO

Function

description

MINI PCI-E SLOT

SLOT1

WLAN/BT

explain

X

BTO

Function

description

explain

S3 Power Saving

Power Saving

BTO

LAN

10/100M

Camera & Mic

CAM@

HEX

A0 H

D2 H

0001 0110 bSmart Battery

Address

1010 0000 b

1010 0100 bA4 H

1101 0010 b

PowerPower

+3VS

EC SM Bus2 Address

Device

96 H

1001 0110 bPCH

B

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

G3 LOW LOWLOW

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/09/03 2012/12/31

C

Compal Secret Data

Deciphered Date

SIGNAL

D

SLP_S3# SLP_S4# SLP_S5#

HIGH HIGHHIGH

LOW

LOW LOW

Title

Size Document Number Rev

Custom

Date: Sheet of

HIGH

LOW LOWLOW

HIGH

Compal Electronics, Inc.

Notes List

PWWHA LA-7201P M/B

E

0.1

4 50Tuesday, October 12, 2010

0.1

Power

+3VS

3 3

+3VS

Device

DDR SO-DIMM 0

DDR SO-DIMM 1

Clock Generator

WLAN/WIMAX

EC SM Bus1 Address

Device Address Address

+3VL

4 4

A

HEX HEX

16 H

5

@

PM_DRAM_PWR GD_R

C4871000P_0402_50V7K

12

@

12

D D

+1.05VS_VCCP

R47 62_0402_5%R47 62_0402_5%

R51 10K_0402_5%R51 10K_0402_5%

12

C4881000P_0402_50V7K

H_PWRGOOD

H_PROCHOT#

H_PWRGOOD

H_PROCHOT#<36,41>

H_THERMTRIP#<26>

Remove R14 (o ohm) fo r HW Revi ew demand

H_PM_SYNC< 23>

H_PWRGOOD<26>

C C

+3VALW

0.1U_0402_16V4Z

PM_PWROK<23,36>

DRAMPWROK<23>

B B

1 2

R312

0_0402_5%

2

1

2

R384 0_0402_5%@R384 0_0402_5%@

1 2

U10

U10 74AHC1G09GW_TSSOP5

74AHC1G09GW_TSSOP5

5

P

B

4

O

A

G

3

SUSP<9,39,46>

PM_SYS_PWRGD_BUF

SUSP

1

C93

0.1U_0402_16V4Z

+1.5V_CPU

12

R340

R340 39_0402_5%

39_0402_5%

@

13

D

Q5

Q5 2N7002_SOT23

2N7002_SOT23

2

G

@

G

@

S

H_SNB_IVB#<25>

12

R339

R339 200_0402_5%

200_0402_5%

4

H_PECI<36>

H_SNB_IVB#

R450

1 2

BUF_CPU_RST#

TP_SKTOCC#

H_CATERR#

H_PECI

H_PROCHOT#_R

56_0402_5%

H_THERMTRIP#

H_PM_SYNC

H_PWRGOOD

PM_DRAM_PWR GD_RPM_SYS_PWRGD_BUF

T1 PADT1 PAD

T2 PADT2 PAD

1 2

R454 130_0402_5%R454 130_0402_5%

JCPUB

PROC_SELECT#

C26

SNB_IVB#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWR OK

AR33

RESET#

Sandy Bridge_rPGA_Rev0p61

3

BCLK

BCLK#

MISCTHERMALPWR MANAGEMENT

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLOCKS

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

DDR3

MISC

DDR3

MISC

PRDY#

PREQ#

TCK

TMS

TRST#

TDI

TDO

DBR#

BPM#[0]

JTAG & BPM

BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

@

100 MHz

A28 A27

120 MHz

A16 A15

R8

AK1 A5 A4

AP29 AP27

AR26 AR27 AP30

AR28 AP26

AL35

AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32

CLK_CPU_DMI CLK_CPU_DMI#

CLK_CPU_DPLL CLK_CPU_DPLL#

H_DRAMRST#

SM_RCOMP_0

R1437 140_0402_1%R1437 140_0402_1%

SM_RCOMP_1

R1438 25.5_0402_1%R1438 25.5_0402_1%

SM_RCOMP_2

R1439 200_0402_1%R1439 200_0402_1%

XDP_PRDY#_R XDP_PREQ#_R

XDP_TCK_R XDP_TMS_R XDP_TRST#_R

XDP_TDI_R XDP_TDO_R

XDP_DBRESET#_R

XDP_BPM#0_R XDP_BPM#1_R XDP_BPM#2_R XDP_BPM#3_R

2

H_DRAMRST# <7>

R1 0_0402_5%@R1 0_0402_5%@

1 2

R2 0_0402_5%@R2 0_0402_5%@

1 2

R4 0_0402_5%@R4 0_0402_5%@

1 2

R6 0_0402_5%@R6 0_0402_5%@

1 2

R7 0_0402_5%@R7 0_0402_5%@

1 2

R8 0_0402_5%@R8 0_0402_5%@

1 2

R10 0_0402_5%@R10 0_0402 _5%@

1 2

R11 0_0402_5%@R11 0_0402 _5%@

1 2

R12 0_0402_5%@R12 0_0402 _5%@

1 2

R13 0_0402_5%@R13 0_0402 _5%@

1 2

R15 0_0402_5%@R15 0_0402 _5%@

1 2

R18 0_0402_5%@R18 0_0402 _5%@

1 2

CLK_CPU_DMI <22> CLK_CPU_DMI# <22>

12 12 12

Stuff R41 and R42 if do not support eDP

DDR3 Compensati on Signals Layout Note:Pla ce these resistors near Processor

XDP_PRDY# XDP_PREQ#

XDP_TCK XDP_TMS XDP_TRST#

XDP_TDI XDP_TDO

XDP_DBRESET#

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3

Routed as a sin gle daisy chai n

1 2

1K_0402_5%

CLK_CPU_DPLL#

CLK_CPU_DPLL

R36

R42 1K_0402_5%R42 1K_0402_5%

R41 1K_0402_5%R41 1K_0402_5%

+3VS

XDP_DBRESET# <23>

PU/PD for JTAG signals

XDP_TMS_R

XDP_TDI_R

XDP_TDO

XDP_TCK_R

XDP_TRST#_R

R28 51_0402_5%R28 51_0402_5%

R29 51_0402_5%R29 51_0402_5%

R30 51_0402_5%R30 51_0402_5%

R31 51_0402_5%R31 51_0402_5%

R32 51_0402_5%R32 51_0402_5%

1

+1.05VS_VCCP

1 2

+1.05VS_VCCP

12

JXDP

@JXDP

XDP Connector

Buffered Reset to CPU

+3VS

0.1U_0402_16V4Z

1

C84

PLT_RST# <13,25,31,32,36,37>

U3

PLT_RST#

A A

U3

1

OE#

2

IN

3

GND

74AHC1G125GW_SOT353-5

5

2

5

VCC

BUFO_CPU_RST# BUF _CPU_RST#

4

OUT

+1.05VS_VCCP

12

R69

R69 75_0402_5%

75_0402_5%

43_0402_1%

1 2

R155

12

R209

R209 0_0402_5%

0_0402_5%

@

4

PBTN_OUT#< 23,36>

VGATE<23,36,47>

CLK_CPU_ITP<22> CLK_CPU_ITP#<22> +1.05VS_VCCP

H_PWRGOOD XDP_CPU_HOOK0 PBTN_OUT# CFG0

CFG0<10>

VGATE

C8

0.1U_0402_10V6K

@

PLT_RST#

1

2

R35 1K_0402_5%@R35 1K_0402_5%@ R152 0_0402_5%@R152 0_0402_5%@ R37 1K_0402_5%@R37 1K_0402_5%@ R451 0_0402_5%@R451 0_0402_5%@

R40 1K_0402_5%

XDP_PREQ# XDP_PRDY#

XDP_BPM#0 XDP_BPM#1

XDP_BPM#2 XDP_BPM#3

1 2 1 2 1 2 1 2

@

1 2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

3

XDP_CPU_HOOK1 XDP_CPU_HOOK2 XDP_CPU_HOOK3 CLK_CPU_ITP CLK_CPU_ITP#

XDP_CPU_HOOK6 XDP_DBRESET#

XDP_TDO XDP_TRST# XDP_TDI XDP_TMS

XDP_TCK

@

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

27 28

MOLEX 52435-2671

2010/09/03 2012/12/31

FAN Control Circuit

+5VS

R1445

1A

1 2

0_0603_5%

2

C902

10U_0805_10V6K

Compal Secret Data

Deciphered Date

1

2

FAN_SPEED1<36>

40 mil

+FAN1

+3VS

12

R1444

R1444 10K_0402_5%

10K_0402_5%

D86

@

FANPWM

12

C900

10U_0805_10V6K

2

1

+5VS

1

C899

0.01U_0402_25V7K

@

2

D85

@D85

@

1 2

1SS355_SOD323-2

FANPWM<36>

+FAN1

BAS16_SOT23-3

Close to Connector

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Sandy Bridge_JTAG/XDP/FAN

PWWHA LA-7201P M/B

1

JFAN

1

2

3

4

ACES_85204-0400N

@

1

C901

2

1000P_0402_50V7K

5 50Tuesday, October 12, 2010

0.1

5

4

3

2

1

+1.05VS_VCCP

R34

24.9_0402_1%

JCPUA

D D

DMI_PTX_CRX_N0<23> DMI_PTX_CRX_N1<23> DMI_PTX_CRX_N2<23> DMI_PTX_CRX_N3<23>

DMI_PTX_CRX_P0<23> DMI_PTX_CRX_P1<23> DMI_PTX_CRX_P2<23> DMI_PTX_CRX_P3<23>

DMI_CTX_PRX_N0<23> DMI_CTX_PRX_N1<23> DMI_CTX_PRX_N2<23> DMI_CTX_PRX_N3<23>

DMI_CTX_PRX_P0<23> DMI_CTX_PRX_P1<23> DMI_CTX_PRX_P2<23> DMI_CTX_PRX_P3<23>

FDI_CTX_PRX_N0<23> FDI_CTX_PRX_N1<23> FDI_CTX_PRX_N2<23>

C C

+1.05VS_VCCP

B B

+1.05VS_VCCP

FDI_CTX_PRX_N3<23> FDI_CTX_PRX_N4<23> FDI_CTX_PRX_N5<23> FDI_CTX_PRX_N6<23> FDI_CTX_PRX_N7<23>

FDI_CTX_PRX_P0<23> FDI_CTX_PRX_P1<23> FDI_CTX_PRX_P2<23> FDI_CTX_PRX_P3<23> FDI_CTX_PRX_P4<23> FDI_CTX_PRX_P5<23> FDI_CTX_PRX_P6<23> FDI_CTX_PRX_P7<23>

FDI_FSYNC0<23> FDI_FSYNC1<23>

FDI_INT<23>

FDI_LSYNC0<23> FDI_LSYNC1<23>

R9 24.9_0402_1%R9 24.9_0402_1%

1 2

R33 10K_0402_5%

@

12

DMI_PTX_CRX_N0 DMI_PTX_CRX_N1 DMI_PTX_CRX_N2 DMI_PTX_CRX_N3

DMI_PTX_CRX_P0 DMI_PTX_CRX_P1 DMI_PTX_CRX_P2 DMI_PTX_CRX_P3

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_FSYNC0 FDI_FSYNC1

FDI_INT

FDI_LSYNC0 FDI_LSYNC1

EDP_COMP

Reserve R33 for HW Review demand

eDP_COMP signals should be shorted near balls and routed with typical impedance <25m ohm

JCPUA

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

Sandy Bridge_rPGA_Rev0p61

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5]

DMI

Intel(R) FDI

eDP

PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[10]

PEG_RX[11]

PEG_RX[12]

PEG_RX[13]

PEG_RX[14]

PEG_RX[15]

PEG_TX#[0]

PEG_TX#[1]

PEG_TX#[2]

PEG_TX#[3]

PEG_TX#[4]

PEG_TX#[5]

PEG_TX#[6]

PEG_TX#[7]

PEG_TX#[8]

PEG_TX#[9]

PEG_TX#[10] PEG_TX#[11]

PCI EXPRESS* - GRAPHICS

PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PEG_TX[10]

PEG_TX[11]

PEG_TX[12]

PEG_TX[13]

PEG_TX[14]

PEG_TX[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9]

PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9]

J22 J21 H22

K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32

J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32

M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25

M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25

@

PEG_COMP

PCIE_GTX_C_CRX_N8 PCIE_GTX_C_CRX_N9 PCIE_GTX_C_CRX_N10 PCIE_GTX_C_CRX_N11 PCIE_GTX_C_CRX_N12 PCIE_GTX_C_CRX_N13 PCIE_GTX_C_CRX_N14 PCIE_GTX_C_CRX_N15

PCIE_GTX_C_CRX_P8 PCIE_GTX_C_CRX_P9 PCIE_GTX_C_CRX_P10 PCIE_GTX_C_CRX_P11 PCIE_GTX_C_CRX_P12 PCIE_GTX_C_CRX_P13 PCIE_GTX_C_CRX_P14 PCIE_GTX_C_CRX_P15

PCIE_CTX_GRX_N8 PCIE_CTX_GRX_N9 PCIE_CTX_GRX_N10 PCIE_CTX_GRX_N11 PCIE_CTX_GRX_N12 PCIE_CTX_GRX_N13 PCIE_CTX_GRX_N14 PCIE_CTX_GRX_N15

PCIE_CTX_GRX_P8 PCIE_CTX_GRX_P9 PCIE_CTX_GRX_P10 PCIE_CTX_GRX_P11 PCIE_CTX_GRX_P12 PCIE_CTX_GRX_P13 PCIE_CTX_GRX_P14 PCIE_CTX_GRX_P15

24.9_0402_1%

C29 .1U_0402_16V7KC29 .1U_0402_16V7K C30 .1U_0402_16V7KC30 .1U_0402_16V7K C31 .1U_0402_16V7KC31 .1U_0402_16V7K C32 .1U_0402_16V7KC32 .1U_0402_16V7K C33 .1U_0402_16V7KC33 .1U_0402_16V7K C34 .1U_0402_16V7KC34 .1U_0402_16V7K C35 .1U_0402_16V7KC35 .1U_0402_16V7K C36 .1U_0402_16V7KC36 .1U_0402_16V7K

C45 .1U_0402_16V7KC45 .1U_0402_16V7K C46 .1U_0402_16V7KC46 .1U_0402_16V7K C47 .1U_0402_16V7KC47 .1U_0402_16V7K C48 .1U_0402_16V7KC48 .1U_0402_16V7K C49 .1U_0402_16V7KC49 .1U_0402_16V7K C50 .1U_0402_16V7KC50 .1U_0402_16V7K C51 .1U_0402_16V7KC51 .1U_0402_16V7K C52 .1U_0402_16V7KC52 .1U_0402_16V7K

PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical

12

impedance = 43 m ohm (4 mils) PEG_ICOMPO signals should be routed with max length = 500 mils

- typical impedance = 14.5 m ohm (12 mils)

PCIE_GTX_C_CRX_N[8..15] <13>

PCIE_GTX_C_CRX_P[8..15] <13>

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

PCIE_CTX_C_GRX_N8

PCIE_CTX_C_GRX_N9 PCIE_CTX_C_GRX_N10 PCIE_CTX_C_GRX_N11 PCIE_CTX_C_GRX_N12 PCIE_CTX_C_GRX_N13 PCIE_CTX_C_GRX_N14 PCIE_CTX_C_GRX_N15

PCIE_CTX_C_GRX_P8

PCIE_CTX_C_GRX_P9

PCIE_CTX_C_GRX_P10 PCIE_CTX_C_GRX_P11 PCIE_CTX_C_GRX_P12 PCIE_CTX_C_GRX_P13 PCIE_CTX_C_GRX_P14 PCIE_CTX_C_GRX_P15

PCIE_CTX_C_GRX_N[8..15] <13>

PCIE_CTX_C_GRX_P[8..15] <13>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2010/09/03 2012/12/31

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Sandy Bridge_DMI/PEG/FDI

PWWHA LA-7201P M/B

6 50Tuesday, October 12, 2010

1

0.1

5

JCPUC

F10

G10

N10

M10

AG6 AG5 AK6 AK5 AH5 AH6

AJ5 AJ6 AJ8

AK8

AJ9 AK9 AH8 AH9

AL9

AL8

AP11

AN11

AL12 AM12 AM11

AL11 AP12 AN12

AJ14 AH14

AL15 AK15

AL14 AK14

AJ15 AH15

AE10

AF10

AE8 AD9

AF9

M8

M9

M7

C5 D5 D3 D2 D6 C6 C2 C3

F8

G9 F9 F7 G8 G7 K4 K5 K1

J1 J5 J4 J2

K2

N8 N7

N9

V6

JCPUC

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

DDR_A_D[0..63]<11>

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3

D D

C C

B B

DDR_A_BS0<11> DDR_A_BS1<11> DDR_A_BS2<11>

DDR_A_CAS#<11> DDR_A_RAS#<11>

DDR_A_WE#< 11>

DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

DDR_A_CAS# DDR_A_RAS# DDR_A_WE#

4

DDRA_CLK0

AB6

SA_CLK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CLK[1]

SA_CLK#[1]

SA_CKE[1]

SA_CLK[2]

SA_CLK#[2]

SA_CKE[2]

SA_CLK[3]

SA_CLK#[3]

SA_CKE[3]

SA_CS#[0] SA_CS#[1] SA_CS#[2] SA_CS#[3]

SA_ODT[0]

SA_ODT[1] SA_ODT[2] SA_ODT[3]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

DDR SYSTEM MEMORY A

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

DDRA_CLK0#

AA6

DDRA_CKE0

V9

DDRA_CLK1 DDRB_ CLK1

AA5

DDRA_CLK1# DDRB_ CLK1#

AB5

DDRA_CKE1 DDRB_CKE1

V10

AB4 AA4 W9

AB3 AA3 W10

DDRA_SCS0# DDRB_SCS0#

AK3

DDRA_SCS1#

AL3 AG1 AH1

DDRA_ODT0 DDRB_ODT0

AH3

DDRA_ODT1

AG3 AG2 AH2

DDR_A_DQS#0

C4

DDR_A_DQS#1

G6

DDR_A_DQS#2

J3

DDR_A_DQS#3

M6

DDR_A_DQS#4

AL6

DDR_A_DQS#5

AM8

DDR_A_DQS#6

AR12

DDR_A_DQS#7

AM15

DDR_A_DQS0

D4

DDR_A_DQS1

F6

DDR_A_DQS2

K3

DDR_A_DQS3

N6

DDR_A_DQS4

AL5

DDR_A_DQS5

AM9

DDR_A_DQS6

AR11

DDR_A_DQS7

AM14

DDR_A_MA0

AD10

DDR_A_MA1

W1

DDR_A_MA2

W2

DDR_A_MA3

W7

DDR_A_MA4

V3

DDR_A_MA5

V2

DDR_A_MA6

W3

DDR_A_MA7

W6

DDR_A_MA8

V1

DDR_A_MA9

W5

DDR_A_MA10

AD8

DDR_A_MA11

V4

DDR_A_MA12

W4

DDR_A_MA13

AF8

DDR_A_MA14

V5

DDR_A_MA15

V7

3

JCPUD

AM5 AM6 AR3

AN3 AN2 AN1

AN9

AN8 AR6 AR5 AR9

AJ11

AH11

AR8

AJ12

AH12

AT11 AN14 AR14

AT14

AT12 AN15 AR15

AT15

AA10

JCPUD

C9 A7

D10

C8 A9 A8 D9 D8

G4

F4

F1 G1 G5

F5

F2 G2

J7 J8

K10

K9

J9

J10

K8

K7 M5

N4

N2

N1 M4

N5 M2 M1

AP3

AP2 AP5

AT5 AT6 AP6

AT8 AT9

AA9 AA7

R6

AB8 AB9

DDR_B_D[0..63]<12>

DDRA_CLK0 <11> DDRB_CLK0 <12> DDRA_CLK0# <11> DDRA_CKE0 <11> DDRB_CKE0 <12>

DDRA_CLK1 <11> DDRA_CLK1# <11> DDRB_CLK1# <12> DDRA_CKE1 <11>

DDRA_SCS0# <11> DDRA_SCS1# <11> DDRB_SCS1# <12>

DDRA_ODT0 <1 1> DDRB_ODT0 <12> DDRA_ODT1 <1 1> DDRB_ODT1 <12>

DDR_A_DQS#[0..7] <11>

DDR_A_DQS[0..7] <11>

DDR_A_MA[0..15] <11>

DDR_B_BS0<12> DDR_B_BS1<12> DDR_B_BS2<12>

DDR_B_CAS#<12> DDR_B_RAS#<12>

DDR_B_WE#< 12>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

DDR_B_CAS# DDR_B_RAS# DDR_B_WE#

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE#

2

AE2

SB_CLK[0]

AD2

SB_CLK#[0]

R9

SB_CKE[0]

AE1

SB_CLK[1]

AD1

SB_CLK#[1]

R10

SB_CKE[1]

AB2

SB_CLK[2]

AA2

SB_CLK#[2]

T9

SB_CKE[2]

AA1

SB_CLK[3]

AB1

SB_CLK#[3]

T10

SB_CKE[3]

AD3

SB_CS#[0]

AE3

SB_CS#[1]

AD6

SB_CS#[2]

AE6

SB_CS#[3]

AE4

SB_ODT[0]

AD4

SB_ODT[1]

AD5

SB_ODT[2]

AE5

SB_ODT[3]

DDR_B_DQS#0

D7

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6]

DDR SYSTEM MEMORY B

SB_DQS[7]

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

F3 K6 N3 AN5 AP9 AK12 AP15

C7 G3 J6 M3 AN6 AP8 AK11 AP14

AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4

DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDRB_CLK0 DDRB_CLK0# DDRB_CKE0

DDRB_SCS1#

DDRB_ODT1

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8

DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

1

DDRB_CLK0# <12>

DDRB_CLK1 <12>

DDRB_CKE1 <12>

DDRB_SCS0# <12>

DDR_B_DQS#[0..7] <12>

DDR_B_DQS[0..7] <12>

DDR_B_MA[0..15] <12>

Sandy Bridge_rPGA_Rev0p61

R466

0_0402_5%

1 2

@

Q14

D

S

D

S

1 2

13

BSS138_NL_SOT23-3

G

2

1

C140

0.047U_0402_25V6K

2

H_DRAMRST#<5>

R464

4.99K_0402_1%

A A

DRAMRST_CNTRL_PC H<22>

5

4.99K_0402_1%

DRAMRST_CNTRL

1 2

R463 0_0402_5%R463 0_0402_5%

1K_0402_5%

DDR3_DRAMRST#_RH_DRAMRST#

@

+1.5V

12

R465

R467

R467 1K_0402_5%

1K_0402_5%

1 2

4

SM_DRAMRST# <11,12>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/09/03 2012/12/31

3

Compal Secret Data

Deciphered Date

Sandy Bridge_rPGA_Rev0p61

2

@

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Sandy Bridge_DDR3

PWWHA LA-7201P M/B

7 50Tuesday, October 12, 2010

1

0.1

5

4

3

2

1

+CPU_CORE

JCPUF

53A (SV 35W)

D D

C C

B B

A A

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

Sandy Bridge_rPGA_Rev0p6 1

POWER

PEG AND DDR

CORE SUPPLY

VSS_SENSE_VCCIO

SENSE LINES SVID

5

8.5A

VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8

VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24

VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39

VCCIO40

VIDALERT#

VIDSCLK

VIDSOUT

VCC_SENSE VSS_SENSE

VCCIO_SENSE VSSIO_SENSE

@

22U_0805_6.3V6M

AH13 AH10

C146

AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11

C147

H14 H12 H11 G14 G13

22U_0805_6.3V6M

G12 F14 F13 F12 F11 E14 E12

Bottom Socket Cavity x 5

E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

J23

H_CPU_SVIDALRT#

AJ29

H_CPU_SVIDCLK

AJ30

H_CPU_SVIDDAT

AJ28

VCCSENSE_R

AJ35

VSSSENSE_R

AJ34

VCCIO_SENSE

B10 A10

R102

R102 0_0402_5%

0_0402_5%

1 2

22U_0805_6.3V6M

1

C143

C144

2

22U_0805_6.3V6M

1

C145

C163

2

22U_0805_6.3V6M

12

R65 0_0402_5 %R65 0_0402_5 %

1 2

R52 0_0402_5 %R52 0_0402_5 %

1 2

R105

R105 100_0402_1%

100_0402_1%

@

1 2

@

R70

R70 130_0402_5%

130_0402_5%

+1.05VS_VCCP

Close to CPU

4

TOP Socket Cavity x 7

22U_0805_6.3V6M

1

C141

2

22U_0805_6.3V6M

1

C153

@

2

1 2

R67 43_0402_1%R67 43_0402_1%

1 2

R63 0_0402 _5%R63 0_0402 _5%

1 2

R66 0_0402 _5%R66 0_0402 _5%

VCCIO_SENSE <46>

C137

2

1

C160

@

2

22U_0805_6.3V6M

+1.05VS_VCCP+1.05VS_VCCP

1

C136

2

22U_0805_6.3V6M

1

C152

@

2

12

R68

R68 75_0402_5%

75_0402_5%

+CPU_CORE

R64

R64 100_0402_1%

100_0402_1%

1 2

12

R62

R62 100_0402_1%

100_0402_1%

+1.05VS_VCCP Decoupling:

22U_0805_6.3V6M

1

C135

2

1

C139

@

2

22U_0805_6.3V6M

ESR 9mohm

330U_D2_2V_Y

1

C134

2

22U_0805_6.3V6M

1

C138

@

2

1

+

C10

2

2X 330U (6m ohm), 12X 22U

22U_0805_6.3V6M

C133

C132

@

22U_0805_6.3V6M

330U_D2_2V_Y

C11

1

C142

2

22U_0805_6.3V6M

1

2

1

+

C12

2

+1.05VS_VCCP

1

2

1

+

2

close to CPU

VR_SVID_ALRT# <47> VR_SVID_CLK <47> VR_SVID_DAT < 47>

Pull high resistor on VR side

C

lose to CPU

VCCSENSE <47> VSSSENSE < 47>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+CPU_CORE Decoupling: 4X 470U (4m ohm), 16X 22U, 10X 10U

+CPU_CORE

10U_0805_10V6K

1

C103

2

10U_0805_10V6K

1

C130

2

22U_0805_6.3V6M

10U_0805_10V6K

1

2

330U_D2_2V_Y

10U_0805_10V6K

1

C101

2

10U_0805_10V6K

+CPU_CORE

C159

22U_0805_6.3V6M

C102

22U_0805_6.3V6M

1

C151

2

Top Socket Cavity

+CPU_CORE

22U_0805_6.3V6M

1

C128

2

22U_0805_6.3V6M

1

C127

2

1

C120

2

22U_0805_6.3V6M

1

C150

C158

2

22U_0805_6.3V6M

Co-Lay with C2, C5, C7, C9

+CPU_CORE

470U_D2_2VM_R4.5M

1

+

C890

2 3

470U_D2_2VM_R4.5M

9/02 Add C898 3Pin Bulk Cap by Power Demand

9/02 Change C890, C891, C894 from SGA00005R00 to SGA00004X80 for Power demand

Compal Secret Data

2010/09/03 2012/12/31

Compal Secret Data

Deciphered Date

1

+

C891

2 3

1

+

2 3

470U_D2_2VM_R4.5M

Bottom Socket Cavity

10U_0805_10V6K

C104

1

C105

2

10U_0805_10V6K

1

C106

2

Top Socket Edge

22U_0805_6.3V6M

1

C129

2

22U_0805_6.3V6M

1

C118

2

C894

2

1

C124

2

22U_0805_6.3V6M

1

C119

2

22U_0805_6.3V6M

1

C123

2

22U_0805_6.3V6M

1

C117

2

330U_D2_2V_Y

10U_0805_10V6K

1

C108

C107

2

10U_0805_10V6K

1

C122

2

22U_0805_6.3V6M

C121

1

C109

2

10U_0805_10V6K

1

C125

2

22U_0805_6.3V6M

10U_0805_10V6K

1

C110

2

1

@

2

1

C111

@

2

10U_0805_10V6K

1

2

9/02 Remove C126, C131 by Power Demand

1

2

Bottom Socket Edge

+CPU_CORE

330U_D2_2V_Y

1

@

+

C2

2

330U_D2_2V_Y

Title

Size Do cument Number Rev

Custom

Date: Sheet of

@

+

C5

C7

2

Compal Electronics, Inc.

Sandy Bridge_POWER-1

PWWHA LA-7201P M/B

1

@

+

C9

330U_D2_2V_Y

2

8 50Tuesday, October 12, 2 010

1

0.1

5

AT24

D D

C C

1 2

R14

R14 0_0402_5%

0_0402_5%

AT23 AT21 AT20 AT18

AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17

AL24

AL23

AL21

AL20

AL18

AL17 AK24 AK23 AK21 AK20 AK18 AK17

AJ24

AJ23

AJ21

AJ20

AJ18

AJ17 AH24 AH23 AH21 AH20 AH18 AH17

VCCPLL Decoupling: 1X 330U (6m ohm), 1X 10U, 2x1U

+1.8VS

R76

10U_0805_10V6K

B B

A A

12

0_0805_5%

C185

+

@

330U_B2_2.5VM_R15M

1

C186

2

+1.8VS_VCCPLL

1

C206

2

1U_0402_6.3V6K

1

C230

1U_0402_6.3V6K

2

4

JCPUG

VAXG1 VAXG2 VAXG3 VAXG4 VAXG5

3

VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54

1.2A

B6

VCCPLL1

A6

VCCPLL2

A2

VCCPLL3

Sandy Bridge_rPGA_Rev0p61

POWER

3A

GRAPHICS

1.8V RAIL

VAXG_SENSE

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

VREFMISC

DDR3 -1.5V RAILS

SA RAIL

VCCSA_SENSE

VCCSA_VID0

VCCSA_VID1

AK35 AK34

+V_SM_VREF should have 20 mil trace width

+V_SM_VREF_CNT +V_SM_VREF

AL1

SM_VREF

R486

100K_0402_5%

5A

AF7

VDDQ1

AF4

VDDQ2

AF1

VDDQ3

AC7

VDDQ4

AC4

VDDQ5

AC1

VDDQ6

Y7

VDDQ7

Y4

VDDQ8

Y1

VDDQ9

U7

VDDQ10

U4

VDDQ11

U1

VDDQ12

P7

VDDQ13

P4

VDDQ14

P1

VDDQ15

Bottom Socket Cavity

6A

VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8

FC_C22

@

M27 M26 L26 J26 J25 J24 H26 H25

H23

C22 C24

10K_0402_5%

10U_0805_10V6K

VCCSA_SENSE

VCCSA_VID0

12

C148

@

0.1U_0402_16V4Z

10U_0805_10V6K

1

C100

2

10U_0805_10V6K

R114

C447

1 2

1

2

C114

08/18 Reserve R119 to follow CRB 1.0

3

R111

0_0402_5%

12

3

2

Q2

@

AP2302GN-HF_SOT23-3

1

RUN_ON_CPU1.5VS3

10U_0805_10V6K

1

C115

C116

2

10U_0805_10V6K

+VCCSA Decoupling: 1X 330U (6m ohm), 3X 10U

10U_0805_10V6K

1

C476

C477

@

2

10U_0805_10V6K

Bottom Socket Edge

R95

1 2

0_0402_5% @

R119

@

10K_0402_5%

@

1 2

12

R252

R252 1K_0402_5%

1K_0402_5%

10U_0805_10V6K

1

C149

2

+VCCSA

1

+

2

10U_0805_10V6K

1

C154

2

10U_0805_10V6K

1

C155

2

Co-lay for Cost Down Plan

VCCSA_SENSE

1 2

R253 0_0402_5%R253 0_0402_5%

1

C485

@

330U_D2_2VM_R6M

2

VCCSA_SENSE <45>

VCCSAP_VID1 <45>

+1.5V_CPU +1.5V

C213 0.1U_0402_16V4ZC213 0.1U_0402_16V4Z

1 2

C212 0.1U_0402_16V4ZC212 0.1U_0402_16V4Z

1 2

C211 0.1U_0402_16V4ZC211 0.1U_0402_16V4Z

1 2

C210 0.1U_0402_16V4ZC210 0.1U_0402_16V4Z

1 2

2

PJ32

2

112

JUMP_43X118

R122

1 2

1K_0402_5%

JUMP_43X118

8/20 Add PJ32 for Cost down +1.5V to +1.5V_CPU

+1.5V_CPU Decoupling: 1X 330U (6m ohm), 6X 10U

+1.5V_CPU

ESR 6mohm

1

+

C180

@

330U_D2_2VM_R6M

2

Co-lay for Cost Down Plan

ESR 17mohm

2N7002DW-T/R7_SOT363-6

ESR 17mohm

+VCCSA

1

+

2

C877

330U_2.5V_M_R17

470_0805_5%

Q46B

SUSP

5

R449

330U_2.5V_M_R17

1 2 3

4

+1.5VS

@

+1.5V_CPU

1

+

C875

2

0

1

1 1

1

C179

C179 10U_0805_10V4K

10U_0805_10V4K

2

0.1U_0402_25V6

C472

0

1

0

PJ30

2

JUMP_43X118

Q33

1

S

2

S

3

S

4

G

FDS6676AS_SO8

1

2

+VCCSAVCCSA_VID0 VCCSA_VID1

0.90 V

0.80 V

0.75 V

0.65 V

@PJ30

@

112

8

D

7

D

6

D

5

D

RUN_ON_CPU1.5VS3

12

R420

R420 820K_0402_5%

820K_0402_5%

1

+1.5V+1.5V_CPU

R455

1 2

220K_0402_5%

61

Q46A

SUSP

2

2N7002DW-T/R7_SOT363-6

For Sandy Bridge

+VSB

SUSP <5,39,46>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECTRONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECTRONICS, INC. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/03 2012/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Sandy Bridge_POWER-2

PWWHA LA-7201P M/B

1

9 50Tuesday, October 12, 2010

0.1

5

JCPUH

AT35

VSS1

AT32

VSS2

AT29

VSS3

AT27

VSS4

AT25

VSS5

AT22

VSS6

AT19

VSS7

AT16

VSS8

AT13

VSS9

AT10

VSS10

AR25 AR22 AR19 AR16 AR13 AR10

AR7 AR4

AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10

AP7

AP4

AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10

AN7

AN4

AM29 AM25 AM22 AM19 AM16 AM13 AM10

AM7

AM4

AM3

AM2

AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10

AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10

AK7

AK4 AJ25

AT7

VSS11

AT4

VSS12

AT3

VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65

AL7

VSS66

AL4

VSS67

AL2

VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80

VSS

D D

C C

B B

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

T35 T34 T33 T32 T31 T30 T29 T28 T27 T26

P9 P8 P6 P5 P3

P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 M34

L33 L30 L27

L9

L8

L6

L5

L4

L3

L2

L1

K35 K32 K29 K26 J34

J31 H33 H30 H27 H24 H21 H18 H15 H13 H10

H9 H8 H7 H6 H5 H4 H3 H2

H1 G35 G32 G29 G26 G23 G20 G17 G11

F34 F31 F29

JCPUI

VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233

4

VSS

VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285

3

JCPUE

F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3

CFG0<5>

T5 PADT5 PAD T6 PADT6 PAD T7 PADT7 PAD T11 PADT11 PAD T12 PADT12 PAD T15 PADT15 PAD T18 PADT18 PAD T16 PADT16 PAD T19 PADT19 PAD T21 PADT21 PAD T20 PADT20 PAD T44 PADT44 PAD T45 PADT45 PAD T46 PADT46 PAD T47 PADT47 PAD T26 PADT26 PAD T27 PADT27 PAD

T22 PADT22 PAD T24 PADT24 PAD T25 PADT25 PAD T23 PADT23 PAD

R115

1K_0402_1%

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17

CPU_RSVD6 CPU_RSVD7

12

R116

R116 1K_0402_1%

1K_0402_1%

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

RSVD1

AH31

RSVD2

AJ33

RSVD3

AH33

RSVD4

AJ26

RSVD5

SA_DIMM_VREFDQ

B4

RSVD6

D1

RSVD7

SB_DIMM_VREFDQ

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

A19

RSVD26

VCCIO_SEL

J15

RSVD27

Sandy Bridge_rPGA_Rev0p61

RESERVED

RSVD28 RSVD29 RSVD30 RSVD31 RSVD32

RSVD33 RSVD34 RSVD35

RSVD37 RSVD38 RSVD39 RSVD40

RSVD41 RSVD42 RSVD43 RSVD44 RSVD45

RSVD46 RSVD47 RSVD48 RSVD49 RSVD50

RSVD51 RSVD52

RSVD53

RSVD54 RSVD55

RSVD56 RSVD57 RSVD58

L7 AG7 AE7 AK2 W8

AT26 AM33 AJ27

T8 J16 H16 G16

2

CFG Straps for Processor

(CFG[17:0] internal pull high to VCCIO)

CFG2

12

R254

R254 1K_0402_1%

1K_0402_1%

@

PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane # definition matches socket pin map definition

*

CFG2

1

0:Lane Reversed

AR35 AT34 AT33 AP35 AR34

B34 A33 A34 B35 C35

AJ32 AK32

AH27

AN35 AM35

AT2 AT1 AR1

B1

KEY

@

T28 PADT28 PAD

CLK_RES_ITP <22> CLK_RES_ITP# <2 2>

PCIE Port Bifurcation Straps

CFG[6:5]

CFG4

12

R255

R255 1K_0402_1%

1K_0402_1%

@

Embedded Display Port Presence Strap

1 : Disabled; No Physical Display Port attached to Embedded Display Port

*

CFG4

11: (Default) x16 - Device 1 functions 1 and 2 disabled

*

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled

01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

CFG6

CFG5

1K_0402_1%

R257

12

R256

R256 1K_0402_1%

1K_0402_1%

@

Sandy Bridge_rPGA_Rev0p61

@

Sandy Bridge_rPGA_Rev0p61

@

CFG7

12

R258

R258 1K_0402_1%

1K_0402_1%

@

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB de assertion

CFG7

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/03 2012/12/31

Compal Secret Data

Deciphered Date

2

0: PEG Wait for BIOS for training

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Sandy Bridge_GND/RSVD/CFG

PWWHA LA-7201P M/B

0.1

10 50Tuesday, October 12, 2010

1

10 50Tuesday, October 12, 2010

0.1

5

+VREF_DQA

1

C157

C156

0.1U_0402_16V4Z

2

D D

Close to JDDRL.1

C C

B B

A A

+3VS

C181

DDR_A_BS2<7>

DDRA_CLK0<7> DDRA_CLK0#<7>

DDR_A_BS0<7>

DDR_A_WE#<7>

DDR_A_CAS#<7>

DDRA_SCS1#<7>

1

C182

2

2.2U_0603_6.3V4Z

1

2

R90

R90 10K_0402_5%

10K_0402_5%

1

2

0.1U_0402_16V4Z

5

DDR_A_D0 DDR_A_D1

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_D26 DDR_A_D27

DDRA_CKE0

DDR_A_BS2

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

DDRA_CLK0 DDRA_CLK0#

DDR_A_MA10 DDR_A_BS0

DDR_A_WE# DDR_A_CAS#

DDR_A_MA13 DDRA_SCS1#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_D58 DDR_A_D59

1 2

+0.75VS

12

R91

R91 10K_0402_5%

10K_0402_5%

+1.5V

JDDRL

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

GND2

FOX_AS0A626-U2SN-7F_204P

@

VSS DQ4 DQ5 VSS

DQS0#

DQS0

VSS DQ6 DQ7

VSS DQ12 DQ13

VSS

DM1

RESET#

VSS DQ14 DQ15

VSS DQ20 DQ21

VSS

DM2

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS

DQS3#

DQS3

VSS DQ30 DQ31

VSS

CKE1

VDD

A15 A14

VDD

A11

VDD

CK1 CK1#

VDD

BA1 RAS#

VDD

S0#

ODT0

VDD ODT1

VDD

VREF_CA

VSS DQ36 DQ37

VSS

DM4

VSS DQ38 DQ39

VSS DQ44 DQ45

VSS

DQS5#

DQS5

VSS DQ46 DQ47

VSS DQ52 DQ53

VSS

DM6

VSS DQ54 DQ55

VSS DQ60 DQ61

VSS

DQS7#

DQS7

VSS DQ62 DQ63

VSS

EVENT#

SDA

SCL

VTT

BOSS1 BOSS2

A7

A6 A4

A2 A0

NC

4

+1.5V

2

DDR_A_D4

4

DDR_A_D5

6 8

DDR_A_DQS#0

10

DDR_A_DQS0

12 14

DDR_A_D6

16

DDR_A_D7

18 20

DDR_A_D12

22

DDR_A_D13

24 26 28

SM_DRAMRST#

30 32

DDR_A_D14

34

DDR_A_D15

36 38

DDR_A_D20

40

DDR_A_D21

42 44 46 48

DDR_A_D22

50

DDR_A_D23

52 54

DDR_A_D28

56

DDR_A_D29

58 60

DDR_A_DQS#3

62

DDR_A_DQS3

64 66

DDR_A_D30

68

DDR_A_D31

70 72

DDRA_CKE1

74 76

DDR_A_MA15

78

DDR_A_MA14

80 82

DDR_A_MA11

84

DDR_A_MA7

86 88

DDR_A_MA6

90

DDR_A_MA4

92 94

DDR_A_MA2

96

DDR_A_MA0

98 100

DDRA_CLK1

102

DDRA_CLK1#

104 106

DDR_A_BS1

108

DDR_A_RAS#

110 112

DDRA_SCS0#

114

DDRA_ODT0

116 118

DDRA_ODT1

120 122 124

+VREF_CAA

126 128

DDR_A_D36

130

DDR_A_D37

132 134 136 138

DDR_A_D38

140

DDR_A_D39

142 144

DDR_A_D44

146

DDR_A_D45

148 150

DDR_A_DQS#5

152

DDR_A_DQS5

154 156

DDR_A_D46

158

DDR_A_D47

160 162

DDR_A_D52

164

DDR_A_D53

166 168 170 172

DDR_A_D54

174

DDR_A_D55

176 178

DDR_A_D60

180

DDR_A_D61

182 184

DDR_A_DQS#7

186

DDR_A_DQS7

188 190

DDR_A_D62

192

DDR_A_D63

194 196 198

PM_SMBDATA

200

PM_SMBCLK

202 204

+0.75VS

206 208

4

DDR3 SO-DIMM A Reverse Type

SM_DRAMRST# <7,12>

DDRA_CKE1 <7>DDRA_CKE0<7>

DDRA_CLK1 <7> DDRA_CLK1# <7>

DDR_A_BS1 <7> DDR_A_RAS# <7>

DDRA_SCS0# <7> DDRA_ODT0 <7>

DDRA_ODT1 <7>

1

C162

C161

close to JDDRL.126

PM_SMBDATA <12,22,31> PM_SMBCLK <12,22,31>

0.1U_0402_16V4Z

2.2U_0603_6.3V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

DDR_A_DQS[0..7] <7>

DDR_A_DQS#[0..7] <7>

DDR_A_D[0..63] <7>

DDR_A_MA[0..15] <7>

+VREF_DQA

+1.5V

12

R80

1K_0402_1%

12

R82

1K_0402_1%

Layout Note: Place near JDDRL

Change C218 to OSCON at DVT

+1.5V

+

C218 390U_2.5V_M_R10

1 2

C166 10U_0603_6.3V6MC166 10U_0603_6.3V6M

1 2

C168 10U_0603_6.3V6MC168 10U_0603_6.3V6M

1 2

C171 10U_0603_6.3V6MC171 10U_0603_6.3V6M

1 2

C174 10U_0603_6.3V6MC174 10U_0603_6.3V6M

1 2

C176 10U_0603_6.3V6MC176 10U_0603_6.3V6M

1 2

C178 10U_0603_6.3V6MC178 10U_0603_6.3V6M

1 2

Compal Secret Data

2010/09/03 2012/12/31

3

Compal Secret Data

Deciphered Date

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

2

+1.5V

12

R79

1K_0402_1%

12

R81

1K_0402_1%

Layout Note: Place near JDDRL1.203 and 204

+1.5V +0.75VS

C164 0.1U_0402_16V4ZC164 0.1U_0402_16V4Z

1 2

C167 0.1U_0402_16V4ZC167 0.1U_0402_16V4Z

1 2

C170 0.1U_0402_16V4ZC170 0.1U_0402_16V4Z

1 2

C173 0.1U_0402_16V4ZC173 0.1U_0402_16V4Z

1 2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM0

PWWHA LA-7201P M/B

1

C165 10U_0603_6.3V6MC165 10U_0603_6.3V6M

1 2

C169 1U_0402_6.3V6KC169 1U_0402_6.3V6K

12

C172 1U_0402_6.3V6KC172 1U_0402_6.3V6K

12

C175 1U_0402_6.3V6KC175 1U_0402_6.3V6K

12

C177 1U_0402_6.3V6KC177 1U_0402_6.3V6K

12

11 50Tuesday, October 12, 2010

1

0.1

A

+VREF_DQB

1

C183

C184

2.2U_0603_6.3V4Z

1 1

2

Close to JDDRH.1

DDRB_CKE0<7>

2 2

3 3

4 4

+3VS

2.2U_0603_6.3V4Z

C207

@

DDR_B_BS2<7>

DDRB_CLK0<7> DDRB_CLK0#<7>

DDR_B_WE#<7> DDR_B_CAS#<7>

DDRB_SCS1#<7>

1

2

1

C208

2

@

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

2

R98

R98 10K_0402_5%

10K_0402_5%

R99

1 2

10K_0402_5%

DDR_B_D0 DDR_B_D1

DDR_B_D2 DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18 DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_D26 DDR_B_D27

DDRB_CKE0

DDR_B_BS2

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA5

DDR_B_MA3 DDR_B_MA1

DDRB_CLK0 DDRB_CLK0#

DDR_B_MA10 DDR_B_BS0

DDR_B_WE# DDR_B_CAS#

DDR_B_MA13 DDRB_SCS1#

DDR_B_D37 DDR_B_D36

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_D42 DDR_B_D43

DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D54 DDR_B_D55

DDR_B_D56 DDR_B_D57

DDR_B_D58 DDR_B_D59

1 2

A

+0.75VS

+1.5V

JDDRH

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

GND2

FOX_AS0A626-UASN-7F_204P

@

VSS

DQ4

DQ5

VSS

DQS0#

DQS0

VSS

DQ6

DQ7

VSS DQ12 DQ13

VSS

DM1

RESET#

VSS DQ14 DQ15

VSS DQ20 DQ21

VSS

DM2

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS

DQS3#

DQS3

VSS DQ30 DQ31

VSS

CKE1

VDD

A15 A14

VDD

A11

VDD

CK1 CK1#

VDD

BA1 RAS#

VDD

S0#

ODT0

VDD ODT1

VDD

VREF_CA

VSS DQ36 DQ37

VSS

DM4

VSS DQ38 DQ39

VSS DQ44 DQ45

VSS

DQS5#

DQS5

VSS DQ46 DQ47

VSS DQ52 DQ53

VSS

DM6

VSS DQ54 DQ55

VSS DQ60 DQ61

VSS

DQS7#

DQS7

VSS DQ62 DQ63

VSS

EVENT#

SDA

SCL

VTT

BOSS1 BOSS2

A7

A6 A4

A2 A0

NC

B

+1.5V

2

DDR_B_D4

4

DDR_B_D5

6 8

DDR_B_DQS#0

10

DDR_B_DQS0

12 14

DDR_B_D6

16

DDR_B_D7

18 20

DDR_B_D12

22

DDR_B_D13

24 26 28

SM_DRAMRST#

30 32

DDR_B_D14

34

DDR_B_D15

36 38

DDR_B_D20

40

DDR_B_D21

42 44 46 48

DDR_B_D22

50

DDR_B_D23

52 54

DDR_B_D28

56

DDR_B_D29

58 60

DDR_B_DQS#3

62

DDR_B_DQS3

64 66

DDR_B_D30

68

DDR_B_D31

70 72

DDRB_CKE1

74 76

DDR_B_MA15

78

DDR_B_MA14

80 82

DDR_B_MA11

84

DDR_B_MA7

86 88

DDR_B_MA6

90

DDR_B_MA4

92 94

DDR_B_MA2

96

DDR_B_MA0

98 100

DDRB_CLK1

102

DDRB_CLK1#

104 106

DDR_B_BS1

108

DDR_B_RAS#

110 112

DDRB_SCS0#

114

DDRB_ODT0

116 118

DDRB_ODT1

120 122 124

+VREF_CAB

126 128

DDR_B_D32

130

DDR_B_D33

132 134 136 138

DDR_B_D38

140

DDR_B_D39

142 144

DDR_B_D44

146

DDR_B_D45

148 150

DDR_B_DQS#5

152

DDR_B_DQS5

154 156

DDR_B_D46

158

DDR_B_D47

160 162

DDR_B_D52

164

DDR_B_D53

166 168 170 172

DDR_B_D50

174

DDR_B_D51

176 178

DDR_B_D60

180

DDR_B_D61

182 184

DDR_B_DQS#7

186

DDR_B_DQS7

188 190

DDR_B_D62

192

DDR_B_D63

194 196 198

PM_SMBDATA

200

PM_SMBCLK

202 204

206 208

+0.75VS

B

SM_DRAMRST# <7,11>

DDRB_CKE1 <7>

DDRB_CLK1 <7> DDRB_CLK1# <7>

DDR_B_BS1 <7> DDR_B_RAS# <7>DDR_B_BS0<7>

DDRB_SCS0# <7> DDRB_ODT0 <7>

DDRB_ODT1 <7>

C187

Close to JDDRH.126

PM_SMBDATA <11,22,31> PM_SMBCLK <11,22,31>

Reverse Type DDR3 SO-DIMM B

+VREF_DQB

1

C188

0.1U_0402_16V4Z

2.2U_0603_6.3V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

DDR_B_DQS#[0..7] <7>

DDR_B_DQS[0..7] <7>

DDR_B_D[0..63] <7>

DDR_B_MA[0..15] <7>

+1.5V

12

R83

1K_0402_1%

12

R84

1K_0402_1%

+1.5V

12

R86

1K_0402_1%

12

R94

1K_0402_1%

Layout Note: Place near JDDRH

+1.5V

C192 10U_0603_6.3V6MC192 10U_0603_6.3V6M

1 2

C194 10U_0603_6.3V6MC194 10U_0603_6.3V6M

1 2

C197 10U_0603_6.3V6MC197 10U_0603_6.3V6M

1 2

C200 10U_0603_6.3V6MC200 10U_0603_6.3V6M

1 2

C202 10U_0603_6.3V6MC202 10U_0603_6.3V6M

1 2

C204 10U_0603_6.3V6MC204 10U_0603_6.3V6M

1 2

Compal Secret Data

2010/09/03 2012/12/31

C

Compal Secret Data

Deciphered Date

Layout Note: Place these 4 Caps near Command and Control signals of DIMMB

D

C190 0.1U_0402_16V4ZC190 0.1U_0402_16V4Z

1 2

C193 0.1U_0402_16V4ZC193 0.1U_0402_16V4Z

1 2

C196 0.1U_0402_16V4ZC196 0.1U_0402_16V4Z

1 2

C199 0.1U_0402_16V4ZC199 0.1U_0402_16V4Z

1 2

D

E

Layout Note: Place near JDDRH.203 and 204

+0.75VS+1.5V

C191 10U_0603_6.3V6MC191 10U_0603_6.3V6M

1 2

C195 1U_0402_6.3V6KC195 1U_0402_6.3V6K

12

C198 1U_0402_6.3V6KC198 1U_0402_6.3V6K

12

C201 1U_0402_6.3V6KC201 1U_0402_6.3V6K

12

C203 1U_0402_6.3V6KC203 1U_0402_6.3V6K

12

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM1

PWWHA LA-7201P M/B

12 50Tuesday, October 12, 2010

E

0.1

5

PCIE_CTX_C_GRX_P[8..15]<6>

PCIE_CTX_C_GRX_N[8..15]<6>

PCIE_GTX_C_CRX_P[8..15]<6>

PCIE_GTX_C_CRX_N[8..15]<6>

D D

C C

B B

PCIE_CTX_C_GRX_P[8..15]

PCIE_CTX_C_GRX_N[8..15]

PCIE_GTX_C_CRX_P[8..15]

PCIE_GTX_C_CRX_N[8..15]

PCIE_GTX_C_CRX_P8 PCIE_GTX_C_CRX_N8 PCIE_GTX_C_CRX_P9 PCIE_GTX_C_CRX_N9 PCIE_GTX_C_CRX_P10 PCIE_GTX_C_CRX_N10 PCIE_GTX_C_CRX_P11 PCIE_GTX_C_CRX_N11 PCIE_GTX_CRX_N11 PCIE_GTX_C_CRX_P12 PCIE_GTX_C_CRX_N12 PCIE_GTX_C_CRX_P13 PCIE_GTX_C_CRX_N13 PCIE_GTX_C_CRX_P14 PCIE_GTX_C_CRX_N14 PCIE_GTX_C_CRX_P15 PCIE_GTX_C_CRX_N15

CV18 .1U_0402_16V7KCV18 .1U_0402_16V7K CV19 .1U_0402_16V7KCV19 .1U_0402_16V7K CV20 .1U_0402_16V7KCV20 .1U_0402_16V7K CV21 .1U_0402_16V7KCV21 .1U_0402_16V7K CV22 .1U_0402_16V7KCV22 .1U_0402_16V7K CV23 .1U_0402_16V7KCV23 .1U_0402_16V7K CV24 .1U_0402_16V7KCV24 .1U_0402_16V7K CV25 .1U_0402_16V7KCV25 .1U_0402_16V7K CV26 .1U_0402_16V7KCV26 .1U_0402_16V7K CV27 .1U_0402_16V7KCV27 .1U_0402_16V7K CV28 .1U_0402_16V7KCV28 .1U_0402_16V7K CV29 .1U_0402_16V7KCV29 .1U_0402_16V7K CV30 .1U_0402_16V7KCV30 .1U_0402_16V7K CV31 .1U_0402_16V7KCV31 .1U_0402_16V7K CV32 .1U_0402_16V7KCV32 .1U_0402_16V7K CV33 .1U_0402_16V7KCV33 .1U_0402_16V7K

Differential signal

PLT_RST#<5,25,31,32,36,37>

+3VS

4

12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12

CLK_PCIE_VGA<22>

CLK_PCIE_VGA#<22>

1 2

RV13 200_0402_1%@RV13 200_0402_1%@

RV15 2.49K_0402_1%RV15 2.49K_0402_1%

1 2

RV18 0_0402_5%RV18 0_0402_5%

1 2

RV21 10K_04 02_5%RV21 10K_04 02_5%

3

UV1A

AE12 AF12 AG12 AG13 AF13 AE13 AE15 AF15 AG15 AG16 AF16 AE16 AE18 AF18 AG18

PCIE_CTX_C_GRX_P8 PCIE_CTX_C_GRX_N8 PCIE_CTX_C_GRX_P9 PCIE_CTX_C_GRX_N9 PCIE_CTX_C_GRX_P10 PCIE_CTX_C_GRX_N10 PCIE_CTX_C_GRX_P11 PCIE_CTX_C_GRX_N11 PCIE_CTX_C_GRX_P12 PCIE_CTX_C_GRX_N12 PCIE_CTX_C_GRX_P13 PCIE_CTX_C_GRX_N13 PCIE_CTX_C_GRX_P14 PCIE_CTX_C_GRX_N14 PCIE_CTX_C_GRX_P15 PCIE_CTX_C_GRX_N15

PCIE_GTX_CRX_P8 PCIE_GTX_CRX_N8 PCIE_GTX_CRX_P9 PCIE_GTX_CRX_N9 PCIE_GTX_CRX_P10 PCIE_GTX_CRX_N10 PCIE_GTX_CRX_P11

PCIE_GTX_CRX_P12 PCIE_GTX_CRX_N12 PCIE_GTX_CRX_P13 PCIE_GTX_CRX_N13 PCIE_GTX_CRX_P14 PCIE_GTX_CRX_N14 PCIE_GTX_CRX_P15 PCIE_GTX_CRX_N15

PEX_TSTCLK_OUT PEX_TSTCLK_OUT# XTALSSIN

12

CLK_REQ#

AG19 AF19 AE19 AE21 AF21 AG21 AG22 AF22 AE22 AE24 AF24 AG24 AF25 AG25 AG26 AF27 AE27

AD10 AD11 AD12 AC12 AB11 AB12 AD13 AD14 AD15 AC15 AB14 AB15 AC16 AD16 AD17 AD18 AC18 AB18 AB19 AB20 AD19 AD20 AD21 AC21 AB21 AB22 AC22 AD22 AD23 AD24 AE25 AE26

AB10 AC10

AF10 AE10

AG10

AD9

AE9

N12M-GE-S-B1 BGA 533P

Part 1 of 5

PEX_RX0 PEX_RX0_N PEX_RX1 PEX_RX1_N PEX_RX2 PEX_RX2_N PEX_RX3 PEX_RX3_N PEX_RX4 PEX_RX4_N PEX_RX5 PEX_RX5_N PEX_RX6 PEX_RX6_N PEX_RX7 PEX_RX7_N PEX_RX8 PEX_RX8_N PEX_RX9 PEX_RX9_N PEX_RX10 PEX_RX10_N PEX_RX11 PEX_RX11_N PEX_RX12 PEX_RX12_N PEX_RX13 PEX_RX13_N PEX_RX14 PEX_RX14_N PEX_RX15 PEX_RX15_N

PEX_TX0 PEX_TX0_N PEX_TX1 PEX_TX1_N PEX_TX2 PEX_TX2_N PEX_TX3 PEX_TX3_N PEX_TX4 PEX_TX4_N PEX_TX5 PEX_TX5_N PEX_TX6 PEX_TX6_N PEX_TX7 PEX_TX7_N PEX_TX8 PEX_TX8_N PEX_TX9 PEX_TX9_N PEX_TX10 PEX_TX10_N PEX_TX11 PEX_TX11_N PEX_TX12 PEX_TX12_N PEX_TX13 PEX_TX13_N PEX_TX14 PEX_TX14_N PEX_TX15 PEX_TX15_N

PEX_REFCLK PEX_REFCLK_N

PEX_TSTCLK_OUT PEX_TSTCLK_OUT_N

PEX_TERMP

PEX_RST_N

PEX_CLKREQ_N

PCI EXPRESS

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8

GPIO9 GPIO10 GPIO11

GPIO

GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19

DACA_HSYNC DACA_VSYNC

DACA_RED

DACA_BLUE

DACA_GREEN

DACA_VREF DACA_RSET

DACB_HSYNC DACB_VSYNC

DACB_RED

DACB_BLUE

DACB_GREEN

DACB_VREF DACB_RSET

JTAG_TCK

JTAG_TDI JTAG_TDO JTAG_TMS

JTAG_TRST_N

TEST

TESTMODE

I2CA_SCL

I2CA_SDA

I2CB_SCL

I2CB_SDA

I2CC_SCL

I2CC_SDA

I2C DACADACB

GPIO20 GPIO21

I2CS_SCL

I2CS_SDA

XTAL_SSIN

XTAL_OUTBUFF

XTAL_OUT

XTAL_IN

CLK

N1 G1 C1 M2 M3 K3 K2 J2 C2 M1 D2 D1 J3 J1 K1 F3 G3 G2 F1 F2

AD2 AD1

AE2 AD3 AE3

AF1 AE1

U6 U4

T5 R4 T4

R6 V6

AF3 AG4 AE4 AF4 AG3

AD25

R1 T3

R2 R3

A2 B1

A3 A4

T1 T2

D11

E9

E10

D10

CLK_27M_IN

1

CV34

2

18P_0402_50V8J

VGA_BL_PWM VGA_ENVDD VGA_ENBKL GPU_VID0 GPU_VID1

GPU_GPIO8 GPU_GPIO9

GPU_GPIO12

TV8@TV8@

DACA_VREF DACA_RSET

GPU_JTAG_TCK GPU_JTAG_TDI GPU_JTAG_TDO GPU_JTAG_TMS GPU_JTAG_TRST#

GPU_TESTMODE

I2CB_SCL I2CB_SDA

I2CH_SCL I2CH_SDA

XTALOUTBUFF

CLK_27M_IN

27MHZ_16PF_X5H027000FG1H

1 2

RV6 124_0402_1%RV6 124_0402_1%

GPU_SMBCLK GPU_SMBDAT

1 2

RV12 1 0K_0402_5%RV12 10K _0402_5%

1 2

RV16 1 0K_0402_5%RV16 10K _0402_5%

1 2

RV19 0 _0402_5%RV19 0_0402_5%

YV1

1 2

2

VGA_BL_PWM <19 > VGA_ENVDD <19> VGA_ENBKL <36> GPU_VID0 <48> GPU_VID1 <48>

VGA_CRT_HSYNC <20>

VGA_CRT_VSYNC <20>

VGA_CRT_R <20>

VGA_CRT_B <20>

VGA_CRT_G <20>

CV13 0 .1U_0402_16V4ZCV13 0.1U_0402_16V4Z

1 2

TV1@TV1@ TV2@TV2@ TV3@TV3@ TV4@TV4@

1 2

RV9 1K_0402_1%RV9 1K_0402_1%

VGA_CRT_CLK <20>

VGA_CRT_DATA <20>

LCD_EDID_CLK <19>

LCD_EDID_DATA <19>

FERMI Changed

NV_CLK_27M_OUT

1

CV35

2

18P_0402_50V8J

FERMI Changed

2.2K_0402_5%

GPU_SMBCLK

GPU_SMBDAT

RV22

+3VS

1 2

VGA_CRT_CLK

VGA_CRT_DATA

I2CH_SCL

I2CH_SDA

I2CB_SCL

I2CB_SDA

GPU_GPIO8

GPU_GPIO9

GPU_GPIO12

LCD_EDID_CLK

LCD_EDID_DATA

VGA_BL_PWM

VGA_ENBKL

VGA_CRT_R

VGA_CRT_G

VGA_CRT_B

+3VS

RV25

2.2K_0402_5%

1 2

2N7002DW-T/R7_SOT363-6

QV1A

2

4

2N7002DW-T/R7_SOT363-6

61

1

1 2

Close to GPU

RV3 150_0402_1%RV3 150_0402_1%

1 2

RV4 150_0402_1%RV4 150_0402_1%

1 2

RV5 150_0402_1%RV5 150_0402_1%

1 2

GPU_TESTMODE

5

QV1B

3

+3VS

RV234.7K_0402_5% RV234.7K_0402_5%

12

RV244.7K_0402_5% RV244.7K_0402_5%

12

RV10010K_0402_5% @RV10010K_0402_5% @

12

RV10110K_0402_5% @RV10110K_0402_5% @

12

RV272.2K_0402_5% RV272.2K_0402_5%

RV282.2K_0402_5% RV282.2K_0402_5%

RV10210K_0402_5% RV10210K_0402_5%

12

RV2610K_0402_5% RV2610K_0402_5%

RV2910K_0402_5% RV2910K_0402_5%

RV142.2K_0402_5% RV142.2K_0402_5%

RV172.2K_0402_5% RV172.2K_0402_5%

RV1010K_0402_5% RV1010K_0402_5%

RV1110K_0402_5% RV1110K_0402_5%

+3VS

12

RV7

@ R V7

@

10K_0402_5%

12

RV8

RV8 10K_0402_5%

10K_0402_5%

EC_SMB_CK2 <22,36>

EC_SMB_DA2 <22,36>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHE ET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHE ET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/03 2 012/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N12P PCIe,DAC,GPIO

PWWHA LA-7201P M/B

1

13 50Tuesday, October 12, 2010

0.1

5

LCD_TXCLK+<19>

LCD_TXCLK-< 19>

LCD_TXOUT0+<19>

LCD_TXOUT0-<19>

LCD_TXOUT1+<19>

LCD_TXOUT1-<19>

LCD_TXOUT2+<19>

D D

C C

+3VS

strap pin need change for Fermi???

LCD_TXOUT2-<19>

AC4 AD4

AA5 AA4

AB4 AB5

AB3 AB2

AA2 AA3 AB1 AA1

V5 V4

W4

Y4

W1

V1 W3 W2

G4 G5

P4

N4

M5 M4

L4

K4

H4

J4

D3

D4

F5

F4

E4

D5

C3

C4

B3

B4

F7

G6

D6

C6

A6

A7

B6

B7

E6

E7

4

UV1C

IFPA_TXC IFPA_TXC_N IFPA_TXD0 IFPA_TXD0_N IFPA_TXD1 IFPA_TXD1_N IFPA_TXD2 IFPA_TXD2_N IFPA_TXD3 IFPA_TXD3_N

IFPB_TXC IFPB_TXC_N IFPB_TXD4 IFPB_TXD4_N IFPB_TXD5 IFPB_TXD5_N IFPB_TXD6 IFPB_TXD6_N IFPB_TXD7 IFPB_TXD7_N

IFPC_AUX_I2CW_SCL IFPC_AUX_I2CW_SDA_N IFPC_L0 IFPC_L0_N IFPC_L1 IFPC_L1_N IFPC_L2 IFPC_L2_N IFPC_L3 IFPC_L3_N

IFPD_AUX_I2CX_SCL IFPD_AUX_I2CX_SDA_N IFPD_L0 IFPD_L0_N IFPD_L1 IFPD_L1_N IFPD_L2 IFPD_L2_N IFPD_L3 IFPD_L3_N

IFPE_AUX_I2CY_SCL IFPE_AUX_I2CY_SDA_N IFPE_L0 IFPE_L0_N IFPE_L1 IFPE_L1_N IFPE_L2 IFPE_L2_N IFPE_L3 IFPE_L3_N

N12M-GE-S-B1 BGA 533P

Part 3 of 5

PGOOD

NCDBG

MULTI_STRAP_REF2_GND

DBG_DATA1 DBG_DATA2 DBG_DATA3 DBG_DATA4

STRAP0

STRAP1

STRAP2

BUFRST_N

LVDS / TMDS

THERMDN

THERMDP

STRAP4

GENERAL STRAPSERIAL

STRAP3

ROM_CS_N

ROM_SCLK

ROM_SI

ROM_SO

IFPAB_RSET

IFPC_RSET

IFPD_RSET

IFPE_RSET

C15

NC

D15

NC

1 2

J5

RV1 10K_0402_1%@RV1 10K_0402_1%@

GB1B-64 : PGOOD

T6

1 2

RV2 40.2_0402_1%RV2 40.2_0402_1%

W6

GB1B-64 : MULTI_STRAP_REF2_GND

Y6 AA6 N3

STRAP0

C7

STRAP1

B9

STRAP2

A9

N5

D8

D9

STRAP4

N2

STRAP3

F9

B10

ROM_SCLK_GPU

C9

ROM_SI_GPU

A10

ROM_SO_GPU

C10

AB6

R5

M6

F8

1 2

RV32 1K_0402_1%@RV32 1K_0402_1%@

1 2

RV45 1K_0402_1%@RV45 1K_0402_1%@

1 2

RV47 1K_0402_1%@RV47 1K_0402_1%@

1 2

RV48 1K_0402_1%@RV48 1K_0402_1%@

3

Fermi changed

2

UV1E

B2

GND

B5

GND

B8

GND

B11

GND

B14

GND

B17

GND

B20

GND

B23

GND

B26

GND

E2

GND

E5

GND

E8

GND

E11

GND

E17

GND

E20

GND

E23

GND

E26

GND

H2

GND

H5

GND

J11

GND

J14

GND

J17

GND

K9

GND

K19

GND

L2

GND

L5

GND

L11

GND

L12

GND

L13

GND

L14

GND

L15

GND

L16

GND

L17

GND

M12

GND

M13

GND

M14

GND

M15

GND

M16

GND

P2

GND

P5

GND

P9

GND

P19

GND

P23

GND

P26

GND

T12

GND

T13

GND

W16

GND_SENSE

E14

GND_SENSE

N12M-GE-S-B1 BGA 533P

Part 5 of 5

FB_CAL_TERM_GND

MULTI_STRAP_REF0_GND

MULTI_STRAP_REF1_GND

GND

FB_CAL_PU_GND

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

U2 U5 U11 U12 U13 U14 U15 U16 U17 U23 U26 V9 V19 W11 W14 W17 Y2 Y5 Y23 Y26 AC2 AC5 AC6 AC8 AC11 AC14 AC17 AC20 AC23 AC26 AF2 AF5 AF8 AF11 AF14 AF17 AF20 AF23 AF26 T16 T15 T14 F6

1 2

A15

RV42 4 0.2_0402_1%RV42 40.2_0402_1%

B16

1 2

RV43 6 0.4_0402_1%RV43 60.4_0402_1%

F11

1 2

RV44 4 0.2K_0402_1%RV44 40.2K_0402_1%

F10

1 2

RV46 4 0.2K_0402_1%RV46 40.2K_0402_1%

1

set to multi-level straps

RV53

RV54

RV49

RV50

B B

1 2

45.3K_0402_1%

34.8K_0402_1%

RV55

RV56

34.8K_0402_1%

4.99K_0402_1%

@

1 2

RV52

RV51

15K_0402_1%

1 2

RV57

RV58

4.99K_0402_1%

@

15K_0402_1%

1 2

Hynix 64Mx16 DDR3 part stuff RV59=15K Samsung 64Mx16 DDR3 part stuff RV59=20K

Hynix 128Mx16 DDR3 part stuff RV59=35K

**

A A

Samsung 128Mx16 DDR3 part stuff RV59=45.3K

STRAP0

STRAP1

STRAP2

USER[3:0]

3GIO_PADCFG_LUT_ADR[3:0]

PCI_DEVID[3:0]

RV54

@

1 2

4.99K_0402_1%

RV60

RV59

34.8K_0402_1%

10K_0402_1%

1 2

5

RV98

RV97

@

10K_0402_1%

1 2

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 ROM_SCLK_GPU ROM_SI_GPU ROM_SO_GPU

RV99

RV41

4.99K_0402_1%

20K_0402_1%

1 2

Resistor Values

5K

10K

15K

20K

25K

30K

35K

45K

4

Pull-up to +3V

01111

01110

01011

01001

00111

00110

00011

00000

Pull-down to Gnd

11111

11110

11011

11001

10111

ROM_SI

ROM_SO

PCIDEVID_EXT, SUB_VENDOR, SLOT_CLK, PEX_PLL_ENROM_SCLK

RAM_CFG[3:0]

XCLK_417, FB_0_BAR_SIZE, ALT_ADOOR, VGA_DEVICE

10110

10011

100000

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHE ET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHE ET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/03 2 012/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

N12P LVDS,HDMI,DP,GND

PWWHA LA-7201P M/B

1

14 50Tuesday, October 12, 2010

0.1

5

CV164

D D

NV DG for VDD Cap:

0.01uF 10% X7R x6

0.047uF 10% X7R x3

0.1uF 10% X7R x1

4.7uF 10% X5R x1 For GB1b-64 add:

4.7u X5R x1

1

2

.1U_0402_16V7K

CV162

.1U_0402_16V7K

CV49

CV40

1

2

0.022U_0402_25V7K

CV161

1

2

1

2

.1U_0402_16V7K

CV41

CV50

1

2

0.022U_0402_25V7K

1U_0402_6.3V6K

1

CV58

CV44

2

under GPU

+3VS

C C

+1.8VS

B B

220R 100MHZ

LV11 PBY160808T-221Y-N_2PLV11 PBY160808T-221Y-N_2P

12

4.7U_0603_6.3V6K

1

2

CV175

220R 100MHZ

LV1

PBY160808T-221Y-N_2P

1 2

285mA

+IFPAB_IOVDD

.1U_0402_16V7K

1U_0402_6.3V6K

1

CV172

2

+3.3V_RUN_VDD33

+3VS

4.7U_0603_6.3V6K

CV80

1

2

.1U_0402_16V7K

CV166

CV174

1

2

1U_0402_6.3V6K

4.7U_0603_6.3V6K

1

2

CV75

CV74

2

.1U_0402_16V7K

CV81

1

2

4

+VGA_CORE

22U_0603_6.3V6M

1

2

.1U_0402_16V7K

CV51

1

2

1

2

0.022U_0402_25V7K

.1U_0402_16V7K

1

CV68

2

CV59

CV163

1

2

22U_0603_6.3V6M

1

2

1U_0402_6.3V6K

CV43

CV42

1

2

1

CV60

2

0.022U_0402_25V7K

.1U_0402_16V7K

1

CV69

CV76

120mA

2

120mA

+IFPAB_IOVDD

+IFPAB_PLLVDD

12

J9 J10 J12 J13

L9

M9 M11 M17

N9

N11 N12 N13 N14 N15 N16 N17 N19 P11 P12 P13 P14 P15 P16 P17

R9

R11 R12 R13 R14 R15 R16 R17

T9 T11 T17

U9 U19

W9 W10 W12 W13 W18 W19

A12 B12 C12 D12 E12 F12

AG9

V3

V2

J6

H6

AD5

P6

N6

D7

RV20

RV20 10K_0402_5%

10K_0402_5%

UV1D

N12M-GE-S-B1 BGA 533P

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDD33 VDD33 VDD33 VDD33 VDD33 VDD33

PEX_SVDD_3V3

IFPA_IOVDD

IFPB_IOVDD

IFPCD_IOVDD

IFPE_IOVDD

IFPAB_PLLVDD

IFPC_PLLVDD

IFPD_PLLVDD

IFPE_PLLVDD

Part 4 of 5

POWER

2A

FB_CAL_PD_VDDQ

PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ

PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD

PEX_PLLVDD

VID_PLLVDD

SP_PLLVDD

FB_PLLAVDD

FB_DLLAVDD

VDD_SENSE

+1.05VS_VCCP

FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ

PLLVDD

DACA_VDD

DACB_VDD

1

2

3

A13 B13 C13 D13 D14 E13 F13 F14 F15 F16 F17 F19 F22 H23 H26 J15 J16 J18 J19 L19 L23 L26 M19 N22 U22 Y22

AG6 AF6 AE6 AD6 AC13 AC7 AB17 AB16 AB13 AB9 AB8 AB7

AG7 AF7 AE7 AD8 AD7 AC9

+PEX_PLLVDD

AF9

+PLLVDD

K6

L6

K5

R19

AC19

T19

AG2

W5

RV63 10K_0402_1%RV63 10K_0 402_1%

B15

W15

E15

LV3

SBK160808T-300Y-N_2P

22U_0603_6.3V6M

CV84

2.97A

0.01U_0402_25V7K

1

2

1

CV52

2

.1U_0402_16V7K

1

2

PLACE CLOSE TO BALL PLACE NEAR GPU

.1U_0402_16V7K

1

2

0.01U_0402_25V7K

CV38

1

2

1

CV53

2

0.047U_0402_25V6K

.1U_0402_16V7K

CV61

1

2

.1U_0402_16V7K

CV70

1

2

0.01U_0402_25V7K

CV45

0.047U_0402_25V6K

CV62

CV71

CV54

CV46

1

2

1

2

1

2

1

2

1

2

@

0.047U_0402_25V6K

1U_0402_6.3V6K

CV63

1

2

1U_0402_6.3V6K

CV72

1

2

120mA

PLACE NEAR GPU

Close to Pin C1747 to be close to the GPU

+FB_AVDD

100mA

+DACA_VDD

1 2

+1.5V_MEM_VDDQ

route as 50ohm

12

RV65 40.2_0402_1%RV65 40.2_0402_1%

VDD_SENSE <4 8>

150mA , 10mil

.1U_0402_16V7K

CV87

1

2

20 mil

12

.1U_0402_16V7K

CV88

1

2

+PLLVDD

CV179

1

2

.1U_0402_16V7K

CV180

+1.5V_MEM_GFX

10U_0603_6.3V6M

CV181

1

2

1U_0402_6.3V6K

CV47

1

2

1U_0402_6.3V6K

CV64

1

2

1U_0402_6.3V6K

CV73

1

2

1U_0402_6.3V6K

1

CV82

2

add for GB1b-64

4.7U_0603_6.3V6K

CV83

CV48

CV65

CV77

@

10U_0603_6.3V6M

1

2

+PEX_PLLVDD

1

2

10U_0603_6.3V6M

+1.5V_MEM_GFX

CV39

1

2

N10M SPEC FBVDDQ TYP. 1.8V.

+1.5V_MEM_GFX

+1.05VS_VCCP

10U_0603_6.3V6M

22U_0805_6.3V6M

CV66

CV67

1

2

22U_0805_6.3V6M

1

2

120mA

.1U_0402_16V7K

CV90

CV67

1

2

+1.05VS_VCCP

10U_0603_6.3V6M

CV79

CV78

1

2

.1U_0402_16V7K

CV165

1

2

add for GB1b-64

1U_0402_6.3V6K

CV92

1

2

4.7U_0603_6.3V6K

1

2

LV2

SBK160808T-300Y-N_2P

12

LV4

SBK160808T-121Y-N_2P

CV93

1

+1.05VS_VCCP

12

4.7U_0603_6.3V6K

CV91

1

2

add for GB1b-64

+1.05VS_VCCP

A A

LV10

SBK160808T-121Y-N_2P

12

5

285mA

+IFPAB_PLLVDD

1U_0402_6.3V6K

4.7U_0603_6.3V6K

1

CV171

CV168

2

add for GB1b-64

.1U_0402_16V7K

CV167

1

2

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHE ET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHE ET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/03 2 012/12/31

Compal Secret Data

Deciphered Date

2

120mA

+DACA_VDD

1U_0402_6.3V6K

1

2

add for GB1b-64

.1U_0402_16V7K

CV107

1

2

.1U_0402_16V7K

CV110

CV109

1

2

Title

Size Document Number Rev

Custom

Date: Sheet of

300ohm 100MHz ESR0.25ohm

.1U_0402_16V7K

CV108

CV112

1

2

1

2

Compal Electronics, Inc.

N12P Power

PWWHA LA-7201P M/B

+3VS

LV7

TAI-TECH FCM1608CF-301T04_2P

1 2

4.7U_0603_6.3V6K

CV113

1

4.7U_0603_6.3V6K

CV114

1

2

15 50Tuesday, October 12, 2010

0.1

5

4

3

2

1

FBAD[0..63]

FBA_CMD[0..30]

DQMA#[0..7]

DQSA_RN[0..7]

DQSA_WP[0..7]

D D

10K_0402_5%

12

10K_0402_5%

12

C C

10K_0402_5%

12

10K_0402_5%

12

10K_0402_5%

12

B B

+1.5V_MEM_GFX

1.1K_0402_1%

12

RV77

1.1K_0402_1%

12

@

RV78

@

RV66

RV68

RV71

RV72

RV75

CKE_1

ODT_2

ODT_1

CKE_2

RST

FBA_CMD3

FBA_CMD19

FBA_CMD0

FBA_CMD16

FBA_CMD20

+FB_VREF

1

2

FBAD[0..63] <17,18>

FBA_CMD[0..30] <17,18>

DQMA#[0..7] <17,18>

DQSA_RN[0..7] <17,18>

DQSA_WP[0..7] <17,18>

16mil

0.01U_0402_25V7K

CV128

FBAD0 FBAD1 FBAD2 FBAD3 FBAD4 FBAD5 FBAD6 FBAD7 FBAD8 FBAD9 FBAD10 FBAD11 FBAD12 FBAD13 FBAD14 FBAD15 FBAD16 FBAD17 FBAD18 FBAD19 FBAD20 FBAD21 FBAD22 FBAD23 FBAD24 FBAD25 FBAD26 FBAD27 FBAD28 FBAD29 FBAD30 FBAD31 FBAD32 FBAD33 FBAD34 FBAD35 FBAD36 FBAD37 FBAD38 FBAD39 FBAD40 FBAD41 FBAD42 FBAD43 FBAD44 FBAD45 FBAD46 FBAD47 FBAD48 FBAD49 FBAD50 FBAD51 FBAD52 FBAD53 FBAD54 FBAD55 FBAD56 FBAD57 FBAD58 FBAD59 FBAD60 FBAD61 FBAD62 FBAD63

UV1B

D22

FBA_D0

E24

FBA_D1

E22

FBA_D2

D24

FBA_D3

D26

FBA_D4

D27

FBA_D5

C27

FBA_D6

B27

FBA_D7

A21

FBA_D8

B21

FBA_D9

C21

FBA_D10

C19

FBA_D11

C18

FBA_D12

D18

FBA_D13

B18

FBA_D14

C16

FBA_D15

E21

FBA_D16

F21

FBA_D17

D20

FBA_D18

F20

FBA_D19

D17

FBA_D20

F18

FBA_D21

D16

FBA_D22

E16

FBA_D23

A22

FBA_D24

C24

FBA_D25

D21

FBA_D26

B22

FBA_D27

C22

FBA_D28

A25

FBA_D29

B25

FBA_D30

A26

FBA_D31

U24

FBA_D32

V24

FBA_D33

V23

FBA_D34

R24

FBA_D35

T23

FBA_D36

R23

FBA_D37

P24

FBA_D38

P22

FBA_D39

AC24

FBA_D40

AB23

FBA_D41

AB24

FBA_D42

W24

FBA_D43

AA22

FBA_D44

W23

FBA_D45

W22

FBA_D46

V22

FBA_D47

AA25

FBA_D48

W27

FBA_D49

W26

FBA_D50

W25

FBA_D51

AB25

FBA_D52

AB26

FBA_D53

AD26

FBA_D54

AD27

FBA_D55

V25

FBA_D56

R25

FBA_D57

V26

FBA_D58

V27

FBA_D59

R26

FBA_D60

T25

FBA_D61

N25

FBA_D62

N26

FBA_D63

N12M-GE-S-B1 BGA 533P

Part 2 of 5

MEMORY INTERFACE

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8

FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30

FBA_DQM0

FBA_DQM1

FBA_DQM2

FBA_DQM3

FBA_DQM4

FBA_DQM5

FBA_DQM6

FBA_DQM7

FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7

FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7

FB_VREF

FBA_CLK0

FBA_CLK0_N

FBA_CLK1

FBA_CLK1_N

FBA_DEBUG

G24 F27 F25 F26 G26 G27 G25 J25 J24 H24 H22 J26 G22 G23 J22 J27 M24 L24 J23 K23 K22 M23 K24 M27 N27 M26 K26 K27 K25 M25 L22

C26 B19 D19 D23 T24 AA23 AB27 T26

D25 A18 E18 B24 R22 Y24 AA27 R27

C25 A19 E19 A24 T22 AA24 AA26 T27

A16

F24 F23

N24 N23

M22

DQMA#0 DQMA#1 DQMA#2 DQMA#3 DQMA#4 DQMA#5 DQMA#6 DQMA#7

DQSA_RN0 DQSA_RN1 DQSA_RN2 DQSA_RN3 DQSA_RN4 DQSA_RN5 DQSA_RN6 DQSA_RN7

DQSA_WP0 DQSA_WP1 DQSA_WP2 DQSA_WP3 DQSA_WP4 DQSA_WP5 DQSA_WP6 DQSA_WP7

+FB_VREF

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30

1 2

RV76 10K_04 02_5%RV76 10K_04 02_5%

Mode E - Mirror Mode Mapping

TV6PAD ~D @TV6PAD ~D @

TV5PAD ~D @TV5PAD ~D @

CLKA0 <17> CLKA0# <17>

CLKA1 <18> CLKA1# <18>

+1.5V_MEM_GFX

Address

CMD0

CMD1

CMD2

CMD3

CMD4

CMD5

CMD6

CMD7

CMD8

CMD9

CMD10

CMD11

CMD12

CMD13

CMD14

CMD16

CMD17

CMD18

CMD19

CMD20

CMD21

CMD22

CMD23

CMD24

CMD25

CMD26

CMD27

CMD28

CMD29

CMD30

0..31

ODT_L

CS1#_L

CS0#_L

CKE_L

A9

A6

A3

A0

A8

A12

A1

RAS#

A13

BA1

A14

CAS#CMD15

RST

A7

A4

A11

A2

A10

A5

BA2

WE#

BA0

A15

DATA Bus

32..63

A11

A7

BA1

A12

A8

A0

A2

RAS#

A14

A3

A13

CAS#

CKE_H

CS1#_H

CS0#_H

ODT_H

RST

A6

A5

A9

A1

WE#

A4

A15

A10

BA0

BA2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHE ET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHE ET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/03 2 012/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N12P MEM Interface

PWWHA LA-7201P M/B

1

16 50Tuesday, October 12, 2010

0.1