Compal LA-7121P P3MJ0, Aspire 3830TG Schematic

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Compal Confidential

Model Name : P3MJ0

1 1

File Name : LA-7121P
BOM P/N:43XXXXXXL01(UMA)

43XXXXXXL02(DIS)

Compal Confidential

2 2

M/B Schematics Document

Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH

Nvidia N12P-GS/GV

2010-11-16

3 3

REV:0.2

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

2010/12/312009/08/01

2010/12/312009/08/01

2010/12/312009/08/01

D

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

4019BI

4019BI

4019BI

Tuesday, December 14, 2010

Tuesday, December 14, 2010

Tuesday, December 14, 2010

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57

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P3MJ0 block diagram

1 1

VRAM * 8
DDR3
64*16
128*16

Nvidia N12P-GS(128bit)
Nvidia N12P-GV(64bit)
BGA

25W/15W

page22~33

HDMI Conn.

page 36

PEG(DIS)

CRT Conn.

page 35

LVDS Conn.

page 34

HDMI(UMA/Optimus)

2 2

PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)

port 4

USB 3.0 controller
UPD720200AF1
+ Charger

page 44

Card Reader
RTS5209

port 3 port 1

MINI Card

WLAN (+BT)

page 40

Wireless HDMI

port 2

page 39

PCI-E 2.0x16 5GT/s PER LANE100MHz

EDP
(reserved)

page 34

LVDS(UMA/Optimus)

CRT(UMA/Optimus)

TMDS(UMA/Optimus)

LAN(GbE)

Atheros AR8151
Atheros AR8152

sub board

133MHz

FDI x8

100MHz

2.7GT/s

100MHz
100MHz

SATA x 6
(GEN1 1.5GT/S ,GEN2 3GT/S)

port 0

Fan Control

page 46

Intel

Sandy Bridge

Processor
DC/QC 35W

SV2 lane

rPGA989

Intel

Cougar Point-M

PCH

989pin BGA

page 13~21

page 4~10

DMI x4

100MHz
1GB/s x4

SPI

SPI ROM x1
4MB

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 1333

USB 2.0 conn

page 37

port 1

USBx14

HD Audio

3.3V 48MHz

3.3V 24MHz

HDA Codec

Conexnt 20584

sub board

page 14

204pin DDRIII-SO-DIMM X2

BANK 0, 1, 2, 3

WLAN Conn

CMOS Camera

page 11,12

for Bluetooth

page 39

port 8 port 10

page 34

port 0

USB 2.0 conn

sub board

BT
standalone

page 40

port 13

MINI Card

WWAN

page 39

SIM card

page 39

Power off design

port 11

port 12

SATA HDD

conn x 1

page 43

3 3

5 in 1 slot

page 40

RJ45

sub board

Conn.

page 38

LPC BUS

33MHz

Int. Speaker MIC Jack

page 46

sub board sub board

DMIC

module

SPDIF/HP Jack

RTC CKT.

page 13

Power On/Off CKT.

page 43

Touch Pad

P3MJ0 Sub-board

DC/DC Interface CKT.

page 45

4 4

Power Circuit DC/DC

page 48~56

LED

page 42

Sub board conn
& buttons

A

page 46

USB 2.0 +
Audio Codec + Jack

LAN

Power Board

B

ENE KB930

page 41

page 42

BIOS ROM

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Int.KBD

page 42

page 41

Compal Secret Data

Compal Secret Data

2009/08/01 2010/08/01

2009/08/01 2010/08/01

2009/08/01 2010/08/01

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

CPU XDP

page 5

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

4019BI

4019BI

4019BI

Tuesday, December 14, 2010

Tuesday, December 14, 2010

Tuesday, December 14, 2010

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Voltage Rails

S1

Power Plane Description
VIN
BATT+ Battery power supply (12.6V) N/A N/A N/A
B+
+CPU_CORE

1 1

2 2

+VGA_CORE
+VGFX_CORE Core voltage for UMA graphic ON OFF OFF
+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator
+1.0VSDGPU +1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU
+1.05VS_VCCP
+1.05VS_PCH +1.05VS_VCCP to +1.05VS_PCH power for PCH
+1.5V
+1.5VS
+1.5VSDGPU +1.5VS to +1.5VSDGPU switched power rail for GPU ON OFF OFF
+1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU
+3VALW +3VALW always on power rail
+3VALW_EC +3VALW always to KBC ON ON ON*
+3V_LAN
+3VALW_PCH
+3VS
+5VALW
+5VALW_PCH
+5VS +5VALW to +5VS switched power rail OFFON OFF
+VSB +VSBP to +VSB always on power rail for sequence control ON ON*
+RTCVCC RTC power
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

EC SM Bus1 address

Device

Smart Battery

Adapter power supply (19V)

AC or battery power rail for power circuit.
Core voltage for CPU
Core voltage for GPU

+1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU

+1.5VP to +1.5V power rail for DDRIII ON ON OFF
+1.5V to +1.5VS switched power rail

+3VALW to +3V_LAN power rail for LAN
+3VALW to +3VALW_PCH power rail for PCH (Short Jumper)
+3VALW to +3VS power rail
+5VALWP to +5VALW power rail
+5VALW to +5VALW_PCH power rail for PCH (Short resister)

EC SM Bus2 address

Address Address

0001 011X b

Device

S3 S5

N/A N/A N/A

N/AN/AN/A

OFF

ON
ON

ON OFF OFF
ON OFF OFF
ON OFF OFF
ON OFF OFF

ON OFF OFF

ON
ON

ON ON
ON ON
ON
ON
ON ON

ON
ON

OFF
OFF

OFF

OFF

OFF

ON ON*

ON*
ON*

OFF

OFF

ON ON*

ON*

ONON

PCH SM Bus address

Device

Clock Generator (9LVS3199AKLFT,
RTM890N-631-VB-GRT)

DDR DIMM0
DDR DIMM2

3 3

4 4

3G & BT Config
3G SKU:
BT SKU:

BOM Config
UMA Only:
N12P-GS OPTIMUS:
N12P-GV OPTIMUS:

3G@
BT@

VRAM BOM Config

add later

Address

1101 0010b

1001 000Xb
1001 010Xb

UMA@ /BT@/3G@
OPT@/GS@/X76@/BT@/3G@
OPT@/GV@/X76@/BT@/3G@

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

Board ID / SKU ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6
7NC

BOARD ID Table

Board ID

Project ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

JM30
JM40
JM50
SJM30
SJM40
SJM50

NC

USB Port Table

USB 2.0 USB 1.1 Port

EHCI1

EHCI2

SIGNAL

SLP_S1# SLP_S3#

HIGH HIGH HIGH HIGH

LOW

LOW

LOW LOW LOW LOW

100K +/- 5%Ra/Rc/Re

Rb / Rd / Rf V min

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

0

NCNC
NC

UHCI0

UHCI1

UHCI2

UHCI3

UHCI4

UHCI5

UHCI6

PCB Revision

0.1

0.2

0.3

1.0

0
1
2
3
4
5
6
7
8

9
10
11
12
13

0
1
2
3
4
5
6
7

100K +/- 5%Ra/Rc/Re

Rb / Rd / Rf V min

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%

SLP_S4# SLP_S5# +VALW +V +VS Clock

ONONON ON

ON

HIGHHIGHHIGH

ON

HIGH

LOWLOWLOW

HIGH

ON

HIGH

ON

ON

V typ

AD_BID

0 V 0 V

0.503 V

0.819 V

1.185 V 1.264 V

2.200 V

3.300 V

LOW

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

ON

OFF

OFF

V

AD_BID

0.538 V

0.875 V

2.341 V

3.300 V

ON

OFF

OFF

OFF

BTO Option Table

BTO Item

UMA Only

VRAM
Connector CONN@

Blue Tooth BT@
Unpop
N12P-GS
N12P-GV

AD_PID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

3 External
USB Port

USB/B (Left Side)
USB/B (Left Side)

Mini Card(WLAN)
Mini Card(WWAN)
Camera

SIM Card
Blue Tooth

V typ

AD_PID

0 V 0 V

0.503 V

0.819 V

1.185 V 1.264 V

V

max

AD_PID

0.538 V

0.875 V

Design Common

schematics pages
sequence

CPU/PCH/CLK

dGPU
LVDS/CRT/HDMI/DP 2100~2199

LAN 1200~1299
Card Reader
Other IO

(HDD/ODD/MINI/
USB/KBD/BIOS/
Button/LED)
KBC

POK CKT, DC/DC

max

LOW

OFF

OFF

OFF

BOM Structure

UMA@
OPT@Discrete(OPTIMUS)
X76@

3G@3G

@
GS@
GV@

Part count location define

1~1099
2000~2099DIMM
1400~1999

1100~1199Audio

1300~1399

2400~xxxx

2200~2299
2300~2399

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

2010/08/012009/08/01

2010/08/012009/08/01

2010/08/012009/08/01

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

4019BI

4019BI

4019BI

Tuesday, December 14, 2010

Tuesday, December 14, 2010

Tuesday, December 14, 2010

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

357

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357

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JCPU1A

JCPU1A

EDP_COMP

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

Sandy Bridge_rPGA_Rev1p0

Sandy Bridge_rPGA_Rev1p0

CONN@

CONN@

DMI

DMI

Intel(R) FDI

Intel(R) FDI

eDP

eDP

INETL_RPGA_989P-S

DMI_CRX_PTX_N015
DMI_CRX_PTX_N115
DMI_CRX_PTX_N215
DMI_CRX_PTX_N315

DMI_CRX_PTX_P015
DMI_CRX_PTX_P115
DMI_CRX_PTX_P215
DMI_CRX_PTX_P315

DMI_CTX_PRX_N015
DMI_CTX_PRX_N115
DMI_CTX_PRX_N215
DMI_CTX_PRX_N315

DMI_CTX_PRX_P015
DMI_CTX_PRX_P115
DMI_CTX_PRX_P215
DMI_CTX_PRX_P315

C C

FDI_CTX_PRX_N015
FDI_CTX_PRX_N115
FDI_CTX_PRX_N215
FDI_CTX_PRX_N315
FDI_CTX_PRX_N415
FDI_CTX_PRX_N515
FDI_CTX_PRX_N615
FDI_CTX_PRX_N715

FDI_CTX_PRX_P015
FDI_CTX_PRX_P115
FDI_CTX_PRX_P215
FDI_CTX_PRX_P315
FDI_CTX_PRX_P415
FDI_CTX_PRX_P515
FDI_CTX_PRX_P615

+1.05VS_VCCP

12

R2

R2

24.9_0402_1%

24.9_0402_1%

B B

eDP_COMPIO and ICOMPO signals
should be shorted near balls
and routed with typical
impedance <25 mohms

A A

FDI_CTX_PRX_P715
FDI_FSYNC015

FDI_FSYNC115
FDI_INT15
FDI_LSYNC015

FDI_LSYNC115

EDP_HPD#34

EDP_AUXP34
EDP_AUXN34

EDP_TXP034
EDP_TXP134

EDP_TXN034
EDP_TXN134

EDP_TXP1

EDP_TXN1

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]

PCI EXPRESS* - GRAPHICS

PCI EXPRESS* - GRAPHICS

PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

PEG_COMP

J22
J21
H22

PEG_HRX_GTX_N15

K33

PEG_HRX_GTX_N14

M35

PEG_HRX_GTX_N13

L34

PEG_HRX_GTX_N12

J35

PEG_HRX_GTX_N11

J32

PEG_HRX_GTX_N10

H34

PEG_HRX_GTX_N9

H31

PEG_HRX_GTX_N8

G33

PEG_HRX_GTX_N7

G30

PEG_HRX_GTX_N6

F35

PEG_HRX_GTX_N5

E34

PEG_HRX_GTX_N4

E32

PEG_HRX_GTX_N3

D33

PEG_HRX_GTX_N2

D31

PEG_HRX_GTX_N1

B33

PEG_HRX_GTX_N0

C32

PEG_HRX_GTX_P15

J33

PEG_HRX_GTX_P14

L35

PEG_HRX_GTX_P13

K34

PEG_HRX_GTX_P12

H35

PEG_HRX_GTX_P11

H32

PEG_HRX_GTX_P10

G34

PEG_HRX_GTX_P9

G31

PEG_HRX_GTX_P8

F33

PEG_HRX_GTX_P7

F30

PEG_HRX_GTX_P6

E35

PEG_HRX_GTX_P5

E33

PEG_HRX_GTX_P4

F32

PEG_HRX_GTX_P3

D34

PEG_HRX_GTX_P2

E31

PEG_HRX_GTX_P1

C33

PEG_HRX_GTX_P0

B32

PEG_HTX_GRX_N15 PEG_HTX_C_GRX_N15

M29

PEG_HTX_GRX_N14 PEG_HTX_C_GRX_N14

M32

PEG_HTX_GRX_N13 PEG_HTX_C_GRX_N13

M31

PEG_HTX_GRX_N12 PEG_HTX_C_GRX_N12

L32

PEG_HTX_GRX_N11 PEG_HTX_C_GRX_N11

L29

PEG_HTX_GRX_N10 PEG_HTX_C_GRX_N10

K31

PEG_HTX_GRX_N9 PEG_HTX_C_GRX_N9

K28

PEG_HTX_GRX_N8 PEG_HTX_C_GRX_N8

J30

PEG_HTX_GRX_N7 PEG_HTX_C_GRX_N7

J28

PEG_HTX_GRX_N6 PEG_HTX_C_GRX_N6

H29

PEG_HTX_GRX_N5 PEG_HTX_C_GRX_N5

G27

PEG_HTX_GRX_N4 PEG_HTX_C_GRX_N4

E29

PEG_HTX_GRX_N3 PEG_HTX_C_GRX_N3

F27

PEG_HTX_GRX_N2 PEG_HTX_C_GRX_N2

D28

PEG_HTX_GRX_N1 PEG_HTX_C_GRX_N1

F26

PEG_HTX_GRX_N0 PEG_HTX_C_GRX_N0

E25

PEG_HTX_GRX_P15 PEG_HTX_C_GRX_P15

M28

PEG_HTX_GRX_P14 PEG_HTX_C_GRX_P14

M33

PEG_HTX_GRX_P13 PEG_HTX_C_GRX_P13

M30

PEG_HTX_GRX_P12 PEG_HTX_C_GRX_P12

L31

PEG_HTX_GRX_P11 PEG_HTX_C_GRX_P11

L28

PEG_HTX_GRX_P10 PEG_HTX_C_GRX_P10

K30

PEG_HTX_GRX_P9 PEG_HTX_C_GRX_P9

K27

PEG_HTX_GRX_P8 PEG_HTX_C_GRX_P8

J29

PEG_HTX_GRX_P7 PEG_HTX_C_GRX_P7

J27

PEG_HTX_GRX_P6 PEG_HTX_C_GRX_P6

H28

PEG_HTX_GRX_P5 PEG_HTX_C_GRX_P5

G28

PEG_HTX_GRX_P4 PEG_HTX_C_GRX_P4

E28

PEG_HTX_GRX_P3 PEG_HTX_C_GRX_P3

F28

PEG_HTX_GRX_P2 PEG_HTX_C_GRX_P2

D27

PEG_HTX_GRX_P1 PEG_HTX_C_GRX_P1

E26

PEG_HTX_GRX_P0 PEG_HTX_C_GRX_P0

D25

Typ- suggest 220nF. The change in AC capacitor
value from 100nF to 220nF is to enable
compatibility with future platforms having PCIE
Gen3 (8GT/s)

+1.05VS_VCCP

R1

R1

24.9_0402_1%

24.9_0402_1%

C1 .1U_0402_16V7KOPT@C1 .1U_0402_16V7KOPT@

1 2

C2 .1U_0402_16V7KOPT@C2 .1U_0402_16V7KOPT@

1 2

C3 .1U_0402_16V7KOPT@C3 .1U_0402_16V7KOPT@

1 2

C4 .1U_0402_16V7KOPT@C4 .1U_0402_16V7KOPT@

1 2

C5 .1U_0402_16V7KOPT@C5 .1U_0402_16V7KOPT@

1 2

C6 .1U_0402_16V7KOPT@C6 .1U_0402_16V7KOPT@

1 2

C7 .1U_0402_16V7KOPT@C7 .1U_0402_16V7KOPT@

1 2

C8 .1U_0402_16V7KOPT@C8 .1U_0402_16V7KOPT@

1 2

C9 .1U_0402_16V7KOPT@C9 .1U_0402_16V7KOPT@

1 2

C10 .1U_0402_16V7KOPT@C10 .1U_0402_16V7KOPT@

1 2

C11 .1U_0402_16V7KOPT@C11 .1U_0402_16V7KOPT@

1 2

C12 .1U_0402_16V7KOPT@C12 .1U_0402_16V7KOPT@

1 2

C13 .1U_0402_16V7KOPT@C13 .1U_0402_16V7KOPT@

1 2

C14 .1U_0402_16V7KOPT@C14 .1U_0402_16V7KOPT@

1 2

C15 .1U_0402_16V7KOPT@C15 .1U_0402_16V7KOPT@

1 2

C16 .1U_0402_16V7KOPT@C16 .1U_0402_16V7KOPT@

1 2

C17 .1U_0402_16V7KOPT@C17 .1U_0402_16V7KOPT@

1 2

C18 .1U_0402_16V7KOPT@C18 .1U_0402_16V7KOPT@

1 2

C19 .1U_0402_16V7KOPT@C19 .1U_0402_16V7KOPT@

1 2

C20 .1U_0402_16V7KOPT@C20 .1U_0402_16V7KOPT@

1 2

C21 .1U_0402_16V7KOPT@C21 .1U_0402_16V7KOPT@

1 2

C22 .1U_0402_16V7KOPT@C22 .1U_0402_16V7KOPT@

1 2

C23 .1U_0402_16V7KOPT@C23 .1U_0402_16V7KOPT@

1 2

C24 .1U_0402_16V7KOPT@C24 .1U_0402_16V7KOPT@

1 2

C25 .1U_0402_16V7KOPT@C25 .1U_0402_16V7KOPT@

1 2

C26 .1U_0402_16V7KOPT@C26 .1U_0402_16V7KOPT@

1 2

C27 .1U_0402_16V7KOPT@C27 .1U_0402_16V7KOPT@

1 2

C28 .1U_0402_16V7KOPT@C28 .1U_0402_16V7KOPT@

1 2

C29 .1U_0402_16V7KOPT@C29 .1U_0402_16V7KOPT@

1 2

C30 .1U_0402_16V7KOPT@C30 .1U_0402_16V7KOPT@

1 2

C31 .1U_0402_16V7KOPT@C31 .1U_0402_16V7KOPT@

1 2

C32 .1U_0402_16V7KOPT@C32 .1U_0402_16V7KOPT@

1 2

12

PEG_HRX_GTX_N[0..15] 22
PEG_HRX_GTX_P[0..15] 22

PEG_HTX_C_GRX_N[0..15] 22
PEG_HTX_C_GRX_P[0..15] 22

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01 2010/12/31

2009/12/01 2010/12/31

2009/12/01 2010/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

4019BI

4019BI

4019BI

1

457Tuesday, December 14, 2010

457Tuesday, December 14, 2010

457Tuesday, December 14, 2010

A

A

A

of

5

+1.05VS_VCCP

D D

C C

PM_DRAM_PWRGD15

Processor Pullups

R5 62_0402_5%R5 62_0402_5%

R8 10K_0402_5%R8 10K_0402_5%

12

12

C211 220P_0402_50V7K@C211 220P_0402_50V7K@

12

220pF close to CPU(ESD)

Buffered reset to CPU

PLT_RST#17,40,41,44,46

PLT_RST#

C34

C34

0.1U_0402_16V4Z

0.1U_0402_16V4Z

R18

R18

10K_0402_5%

10K_0402_5%

1 2

H_PROCHOT#

H_CPUPWRGD_R

+3VS

5

1

P

NC

2

A

G

3

+3VALW+3VS

1

2

5

1

P

B

2

A

G

3

SUSP45,53

1

C33

C33

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

U1

U1

BUFO_CPU_RST#

4

Y

SN74LVC1G07DCKR_SC70-5

SN74LVC1G07DCKR_SC70-5

U2

U2
74AHC1G09GW_TSSOP5

74AHC1G09GW_TSSOP5

PM_SYS_PWRGD_BUF

4

O

SUSP

2

G

G

+1.05VS_VCCP

12

R15

R15
75_0402_5%

75_0402_5%

R17

R17

43_0402_1%

43_0402_1%

1 2

12

@

@
R20

R20
39_0402_5%

39_0402_5%

13

D

D

Q1

Q1
2N7002H_SOT23-3

2N7002H_SOT23-3
@

@

S

S

BUF_CPU_RST#

12

@

@
R19

R19
0_0402_5%

0_0402_5%

+1.5V_CPU_VDDQ

12

R16

R16
200_0402_5%

200_0402_5%

4

H_PECI18,41

H_PROCHOT#41,50

H_THRMTRIP#18

H_PM_SYNC15

H_CPUPWRGD18

PM_SYS_PWRGD_BUF

T3 PADT3 PAD

1 2

56_0402_5%

56_0402_5%

130_0402_5%

130_0402_5%

1 2

R9

0_0402_5%R90_0402_5%

R10

R10

1 2

R11

R11

0_0402_5%

0_0402_5%

1 2

R12

R12

0_0402_5%

0_0402_5%

1 2

R13

R13

0_0402_5%

0_0402_5%

1 2

R14

R14

H_CATERR#

H_PECI_ISO

H_PROCHOT#_R

H_THEMTRIP#_R

H_PM_SYNC_R

H_CPUPWRGD_R

PM_DRAM_PWRGD_R

BUF_CPU_RST#

JCPU1B

JCPU1B

C26

PROC_SELECT#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWROK

AR33

RESET#

Sandy Bridge_rPGA_Rev1p0

Sandy Bridge_rPGA_Rev1p0
CONN@

CONN@

3

MISCTHERMALPWR MANAGEMENT

MISCTHERMALPWR MANAGEMENT

INETL_RPGA_989P-S

BCLK

BCLK#

DPLL_REF_CLK

DPLL_REF_CLK#

CLOCKS

CLOCKS

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

DDR3

MISC

DDR3

MISC

PRDY#

PREQ#

TCK
TMS

TRST#

TDI

TDO

DBR#

BPM#[0]

JTAG & BPM

JTAG & BPM

BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

A28
A27

A16
A15

R8

AK1
A5
A4

AP29
AP27

AR26
AR27
AP30

AR28
AP26

AL35

AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32

CLK_CPU_DMI_R
CLK_CPU_DMII#_R

CLK_DP_R
CLK_DP#_R

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

XDP_PRDY#_R
XDP_PREQ#_R

XDP_TCK_R
XDP_TMS_R
XDP_TRST#_R

XDP_TDI_R
XDP_TDO_R

XDP_BPM#0_R
XDP_BPM#1_R
XDP_BPM#2_R
XDP_BPM#3_R
XDP_BPM#4_R
XDP_BPM#5_R
XDP_BPM#6_R
XDP_BPM#7_R

2

R3 0_0402_5%R3 0_0402_5%

1 2

R4 0_0402_5%R4 0_0402_5%

1 2

R362 1K_0402_5%R362 1K_0402_5%

1 2

R363 1K_0402_5%R363 1K_0402_5%

1 2

H_DRAMRST# 6

T86PAD T86PAD
T87PAD T87PAD

R361 0_0402_5%R361 0_0402_5%

1 2

T38PAD T38PAD
T39PAD T39PAD
T40PAD T40PAD
T41PAD T41PAD
T42PAD T42PAD
T43PAD T43PAD
T44PAD T44PAD
T45PAD T45PAD

1

CLK_CPU_DMI 14
CLK_CPU_DMI# 14H_SNB_IVB#17

+1.05VS_VCCP

CLK_DP_R
CLK_DP#_R

eDP enable:
TX:mount C2114, C2115,
AUX: mount C2118, C2119
HPD: mount R2112, Q2103, R2114
CFG4: mount R55
CLK: mount R6,R7, unmount R362, R363

XDP_DBRESET#DBRESET#_R

XDP_DBRESET# 15

R6 0_0402_5%@R6 0_0402_5%@
R7 0_0402_5%@R7 0_0402_5%@

1 2
1 2

CLK_DP 14
CLK_DP# 14

DDR3 Compensation Signals

SM_RCOMP0

R21 140_0402_1%R21 140_0402_1%

SM_RCOMP1

R22 25.5_0402_1%R22 25.5_0402_1%

SM_RCOMP2

R24 200_0402_1%R24 200_0402_1%

PU/PD for JTAG signals

XDP_TMS_R

R31 51_0402_5%@R31 51_0402_5%@

XDP_TDI_R

R34 51_0402_5%@R34 51_0402_5%@

XDP_TDO_R

R37 51_0402_5%@R37 51_0402_5%@

XDP_TCK_R

R39 51_0402_5%@R39 51_0402_5%@

XDP_TRST#_R

R42 51_0402_5%@R42 51_0402_5%@

12
12
12

12
12
12
12
12

+1.05VS_VCCP

+3VS

XDP_DBRESET#

B B

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01 2010/12/31

2009/12/01 2010/12/31

2009/12/01 2010/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Title

Title

Title

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

4019BI

4019BI

4019BI

Date: Sheet

Date: Sheet

Date: Sheet

R48 1K_0402_5%R48 1K_0402_5%

12

557Tuesday, December 14, 2010

557Tuesday, December 14, 2010

1

557Tuesday, December 14, 2010

A

A

A

of

of

of

5

JCPU1C

JCPU1C

4

3

JCPU1D

JCPU1D

2

1

DDR_A_D[0..63]11

D D

C C

B B

DDR_A_BS011
DDR_A_BS111
DDR_A_BS211

DDR_A_CAS#11
DDR_A_RAS#11
DDR_A_WE#11

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AP11
AN11

AL12
AM12
AM11

AL11

AP12
AN12

AJ14
AH14

AL15

AK15

AL14

AK14

AJ15
AH15

AE10

AF10

F10
G10

N10

M10

AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8

AE8
AD9
AF9

C5
D5
D3
D2
D6
C6
C2
C3

F8

G9

F9

F7
G8
G7

K4

K5

K1

J1

J5

J4

J2

K2
M8

N8

N7
M9

N9
M7

V6

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

RSVD_TP[10]

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_CLK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CLK[1]

SA_CLK#[1]

SA_CKE[1]

RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]

RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]

SA_CS#[0]

SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]

SA_ODT[0]

SA_ODT[1]
RSVD_TP[9]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]

SA_DQS[1]

SA_DQS[2]

SA_DQS[3]

SA_DQS[4]

SA_DQS[5]

SA_DQS[6]

SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AB6
AA6
V9

AA5
AB5
V10

AB4
AA4
W9

AB3
AA3
W10

AK3
AL3
AG1
AH1

AH3
AG3
AG2
AH2

C4
G6
J3
M6
AL6
AM8
AR12
AM15

D4
F6
K3
N6
AL5
AM9
AR11
AM14

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

M_CLK_DDR0 11
M_CLK_DDR#0 11
DDR_CKE0_DIMMA 11

M_CLK_DDR1 11
M_CLK_DDR#1 11
DDR_CKE1_DIMMA 11

DDR_CS0_DIMMA# 11
DDR_CS1_DIMMA# 11

M_ODT0 11
M_ODT1 11

DDR_A_DQS#[0..7] 11

DDR_A_DQS[0..7] 11

DDR_A_MA[0..15] 11 DDR_B_MA[0..15] 12

DDR_B_D[0..63]12

DDR_B_BS012
DDR_B_BS112
DDR_B_BS212

DDR_B_CAS#12
DDR_B_RAS#12
DDR_B_WE#12

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AM5
AM6
AR3

AN3
AN2
AN1

AN9

AN8
AR6
AR5
AR9

AJ11

AH11

AR8

AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15

AA10

C9

SB_DQ[0]

A7

SB_DQ[1]

D10

SB_DQ[2]

C8

SB_DQ[3]

A9

SB_DQ[4]

A8

SB_DQ[5]

D9

SB_DQ[6]

D8

SB_DQ[7]

G4

SB_DQ[8]

F4

SB_DQ[9]

F1

SB_DQ[10]

G1

SB_DQ[11]

G5

SB_DQ[12]

F5

SB_DQ[13]

F2

SB_DQ[14]

G2

SB_DQ[15]

J7

SB_DQ[16]

J8

SB_DQ[17]

K10

SB_DQ[18]

K9

SB_DQ[19]

J9

SB_DQ[20]

J10

SB_DQ[21]

K8

SB_DQ[22]

K7

SB_DQ[23]

M5

SB_DQ[24]

N4

SB_DQ[25]

N2

SB_DQ[26]

N1

SB_DQ[27]

M4

SB_DQ[28]

N5

SB_DQ[29]

M2

SB_DQ[30]

M1

SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]

AP3

SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]

AP2

SB_DQ[39]

AP5

SB_DQ[40]
SB_DQ[41]

AT5

SB_DQ[42]

AT6

SB_DQ[43]

AP6

SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]

AT8

SB_DQ[50]

AT9

SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

AA9

SB_BS[0]

AA7

SB_BS[1]

R6

SB_BS[2]

SB_CAS#

AB8

SB_RAS#

AB9

SB_WE#

RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]

RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]

RSVD_TP[17]
RSVD_TP[18]

RSVD_TP[19]
RSVD_TP[20]

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

SB_CLK[0]

SB_CLK#[0]

SB_CKE[0]

SB_CLK[1]

SB_CLK#[1]

SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

AE2
AD2
R9

AE1
AD1
R10

AB2
AA2
T9

AA1
AB1
T10

AD3
AE3
AD6
AE6

AE4
AD4
AD5
AE5

D7
F3
K6
N3
AN5
AP9
AK12
AP15

C7
G3
J6
M3
AN6
AP8
AK11
AP14

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

M_CLK_DDR2 12
M_CLK_DDR#2 12
DDR_CKE2_DIMMB 12

M_CLK_DDR3 12
M_CLK_DDR#3 12
DDR_CKE3_DIMMB 12

DDR_CS2_DIMMB# 12
DDR_CS3_DIMMB# 12

M_ODT2 12
M_ODT3 12

DDR_B_DQS#[0..7] 12

DDR_B_DQS[0..7] 12

Sandy Bridge_rPGA_Rev1p0

Sandy Bridge_rPGA_Rev1p0
CONN@

CONN@

R49

@R49

@
0_0402_5%

0_0402_5%

1 2

D

S

D

S

DDR3_DRAMRST#_R

1 2

13

Q2

Q2
BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

G

G

2

1

C35

C35

0.047U_0402_16V4Z

0.047U_0402_16V4Z

2

H_DRAMRST#5

R52

R52

4.99K_0402_1%

4.99K_0402_1%

A A

DRAMRST_CNTRL_PCH7,14

5

R53

R53

0_0402_5%

0_0402_5%

1 2

DRAMRST_CNTRL

R50

R50

1K_0402_5%

1K_0402_5%

+1.5V

12

1 2

4

R51

R51

1K_0402_5%

1K_0402_5%

DDR3_DRAMRST# 11,12

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01 2010/12/31

2009/12/01 2010/12/31

2009/12/01 2010/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Sandy Bridge_rPGA_Rev1p0

Sandy Bridge_rPGA_Rev1p0
CONN@

CONN@

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

4019BI

4019BI

4019BI

1

657Tuesday, December 14, 2010

657Tuesday, December 14, 2010

657Tuesday, December 14, 2010

A

A

A

5

4

3

2

1

JCPU1E

CFG Straps for Processor

JCPU1E

L7

RSVD28

AG7

T46 PADT46 PAD
T47 PADT47 PAD
T48 PADT48 PAD
T49 PADT49 PAD
T50 PADT50 PAD
T51 PADT51 PAD
T52 PADT52 PAD
T53 PADT53 PAD
T54 PADT54 PAD
T55 PADT55 PAD
T56 PADT56 PAD
T57 PADT57 PAD
T58 PADT58 PAD
T59 PADT59 PAD
T60 PADT60 PAD
T61 PADT61 PAD
T62 PADT62 PAD

R63

R63

1K_0402_1%

1K_0402_1%

CFG0

CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17

VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE

CPU_RSVD6
CPU_RSVD7

12

12

R64

R64
1K_0402_1%

1K_0402_1%

+3VS

12

R385

R385
10K_0402_5%@

10K_0402_5%@

VCCIO_SEL

12

R378

R378
10K_0402_5%@

10K_0402_5%@

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD5

B4

RSVD6

D1

RSVD7

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

A19

VCCIO_SEL

J15

RSVD27

Sandy Bridge_rPGA_Rev1p0

Sandy Bridge_rPGA_Rev1p0
CONN@

CONN@

INETL_RPGA_989P-S

RESERVED

RESERVED

T90 PADT90 PAD

D D

T82 PADT82 PAD
T83 PADT83 PAD
T84 PADT84 PAD
T85 PADT85 PAD

C C

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
For Future CPU M3 support,
Sandey bridge not supportM3,
Check list1.0&CRB say can NC

check +3VS or +3VALW

follow Module design

VCCIO_SEL For 2012 CPU support

1/NC : (Default) +1.05VS_VTT

A19

*

0: +1.0VS_VTT

B B

RSVD26 had changed the name to VCCIO_SEL
Need PH +3VALW 10K at +1.05VS_VTT source
for 2012 processor +1.05V and +1.0V select

RSVD29
RSVD30
RSVD31
RSVD32

RSVD33
RSVD34
RSVD35

RSVD37
RSVD38
RSVD39
RSVD40

RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

RSVD46
RSVD47
RSVD48
RSVD49
RSVD50

RSVD51
RSVD52

VCC_DIE_SENSE

RSVD54
RSVD55

RSVD56
RSVD57
RSVD58

KEY

AE7
AK2
W8

AT26
AM33
AJ27

T8
J16
H16
G16

AR35
AT34
AT33
AP35
AR34

B34
A33
A34
B35
C35

AJ32
AK32

AH27

AN35
AM35

AT2
AT1
AR1

B1

T4PAD T4PAD

T5PAD T5PAD
T6PAD T6PAD

10/2, From JM50, delete,
10/19, From checklist 1.2, add the path

PEG Static Lane Reversal - CFG2 is for the 16x

Display Port Presence Strap

PCIE Port Bifurcation Straps

CFG[6:5]

CFG2

CFG2

*

CFG4

*

11: (Default) x16 - Device 1 functions 1 and 2 disabled

*

10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

12

R54

R54
1K_0402_1%

1K_0402_1%

1: Normal Operation; Lane # definition matches
socket pin map definition

0:Lane Reversed

CFG4

1K_0402_1%

1K_0402_1%

12

@

@
R55

R55
1K_0402_1%

1K_0402_1%

1 : Disabled; No Physical Display Port
attached to Embedded Display Port

0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

CFG6
CFG5

@R61

@

12

12

R62

@R62

R61

@
1K_0402_1%

1K_0402_1%

R60 0_0402_5%@R60 0_0402_5%@

1 2

Q3

+V_DDR_M3_REFA

A A

+V_DDR_M3_REFB

1

R65 0_0402_5%@R65 0_0402_5%@

1 2

1

5

Q3

3

AP2302GN-HF_SOT23-3

AP2302GN-HF_SOT23-3
@

@

2

DRAMRST_CNTRL_PCH

Q13

Q13

3

AP2302GN-HF_SOT23-3

AP2302GN-HF_SOT23-3
@

@

2

9/16, SM50

CPU_RSVD6

CPU_RSVD7

DRAMRST_CNTRL_PCH 6,14

PEG DEFER TRAINING

CFG7

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01 2010/12/31

2009/12/01 2010/12/31

2009/12/01 2010/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

CFG7

1: (Default) PEG Train immediately following xxRESETB
de assertion

12

@R66

@

R66
1K_0402_1%

1K_0402_1%

0: PEG Wait for BIOS for training

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

4019BI

4019BI

4019BI

1

A

A

757Tuesday, December 14, 2010

757Tuesday, December 14, 2010

757Tuesday, December 14, 2010

A

5

+CPU_CORE

Bottom Socket Cavity

C36

10U_0805_6.3V6M

C36

10U_0805_6.3V6M

1

D D

+CPU_CORE

2

C48

10U_0805_6.3V6M

C48

10U_0805_6.3V6M

1

2

C37

10U_0805_6.3V6M

C37

10U_0805_6.3V6M

1

2

C49

10U_0805_6.3V6M

C49

10U_0805_6.3V6M

1

2

Top Socket Cavity

C59

22U_0805_6.3V6M

C59

22U_0805_6.3V6M

1

2

C C

+CPU_CORE

22U_0805_6.3V6M

22U_0805_6.3V6M

1

2

C60

22U_0805_6.3V6M

C60

22U_0805_6.3V6M

1

1

2

2

Top Socket Edge

C77

22U_0805_6.3V6M

C77

22U_0805_6.3V6M

C76

C76

1

1

2

2

C61

22U_0805_6.3V6M

C61

22U_0805_6.3V6M

C78

22U_0805_6.3V6M

C78

22U_0805_6.3V6M

Bottom Socket Edge

C85

330U_D2_2.5VY_R9M+C85

330U_D2_2.5VY_R9M

C84

330U_D2_2.5VY_R9M+C84

330U_D2_2.5VY_R9M

1

1

+

+

2

2

B B

A A

1

+

+

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

2

1

2

1

2

470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M

C86

C86

4

SV type CPU

QC 94A
DC 53A

C39

10U_0805_6.3V6M

C39

10U_0805_6.3V6M

C38

C38

1

2

10U_0805_6.3V6M

10U_0805_6.3V6M

C50

C50

1

2

C62

22U_0805_6.3V6M

C62

22U_0805_6.3V6M

1

2

C79

22U_0805_6.3V6M

C79

22U_0805_6.3V6M

1

2

470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M

1

C87

C87

+

+

2

C40

10U_0805_6.3V6M

C40

10U_0805_6.3V6M

1

2

C51

C51

C52

10U_0805_6.3V6M

C52

10U_0805_6.3V6M

1

2

C64

22U_0805_6.3V6M

C64

22U_0805_6.3V6M

C63

22U_0805_6.3V6M

C63

22U_0805_6.3V6M

1

2

C80

22U_0805_6.3V6M

C80

22U_0805_6.3V6M

C81

22U_0805_6.3V6M

C81

22U_0805_6.3V6M

1

2

9/16

PDDG says 470u*4

C65

22U_0805_6.3V6M

C65

22U_0805_6.3V6M

C66

22U_0805_6.3V6M

C66

22U_0805_6.3V6M

1

1

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C82

22U_0805_6.3V6M

C82

22U_0805_6.3V6M

1

2

C83

C83

1

2

AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26

AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26

3

POWER

JCPU1F

JCPU1F

POWER

8.5A

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

CORE SUPPLY

CORE SUPPLY

PEG AND DDR

PEG AND DDR

VCC_SENSE

VCCIO_SENSE

VSSIO_SENSE

SENSE LINES SVID

SENSE LINES SVID

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8

VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

VCCIO40

VIDALERT#

VIDSCLK
VIDSOUT

VSS_SENSE

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

J23

AJ29
AJ30
AJ28

AJ35
AJ34

B10
A10

VCCSENSE_R
VSSSENSE_R

2

+1.05VS_VCCP

1

2

1

2

1

2

1

2

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

VCCIO_SENSE
VSSIO_SENSE

22U_0805_6.3V6M

C43

C43

22U_0805_6.3V6M

22U_0805_6.3V6M

@

@

C53

C53

1

1

2

1

2

C45

C45

C44

C44

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

@

@

@

@

C54

C54

C55

C55

2

MB Bottom Socket Cavity

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

MB Top Socket Cavity

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

C67

C67

22U_0805_6.3V6M

22U_0805_6.3V6M

C71

C71

R73 0_0402_5%R73 0_0402_5%
R74 0_0402_5%R74 0_0402_5%

1

1

2

1

2

12

1 2
1 2

@

@

C69

C69

C68

C68

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C72

C72

C73

C73

2

R67

R67
130_0402_5%

130_0402_5%

R69 43_0402_1%R69 43_0402_1%

1 2

R70 0_0402_5%R70 0_0402_5%

1 2

R71 0_0402_5%R71 0_0402_5%

1 2

VCCIO_SENSE 53
VSSIO_SENSE 53

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C46

C46

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

@

@

C56

C56

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

@

@

C70

C70

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C74

C74

2

+CPU_CORE

22U_0805_6.3V6M

22U_0805_6.3V6M

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

@

@

2

330U_D2_2V_Y

330U_D2_2V_Y

1

+

+

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

2

+1.05VS_VCCP+1.05VS_VCCP

12

R72

R72
100_0402_1%

100_0402_1%

12

R75

R75
100_0402_1%

100_0402_1%

C47

C47

C57

C57

C58

C58

C75

C75

+

2

12

R68

R68
75_0402_5%

75_0402_5%

@

@

C42

C42

2

Place the PU
resistors close to CPU

VCCSENSE 54
VSSSENSE 54

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y

1

1

C41

C41

+

+

+

1

+1.05VS_VCCP

2012 compatible

VR_SVID_ALRT# 54
VR_SVID_CLK 54
VR_SVID_DAT 54

Place the PU
resistors close to VR

Sandy Bridge_rPGA_Rev1p0

Sandy Bridge_rPGA_Rev1p0
CONN@

CONN@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01 2010/12/31

2009/12/01 2010/12/31

2009/12/01 2010/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

4019BI

4019BI

4019BI

1

857Tuesday, December 14, 2010

857Tuesday, December 14, 2010

857Tuesday, December 14, 2010

A

A

A

5

D D

4

3

2

1

DELETE

+VGFX_CORE

Top Socket Cavity

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C91

C91

C C

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

2

1

C92

C92

C93

C93

2

Top Socket Edge

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C95

C95

2

22U_0805_6.3V6M

1

1

C96

C96

C97

C97

2

2

Bottom Socket Cavity

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C100

C100

2

Bottom Socket Edge

B B

22U_0805_6.3V6M

22U_0805_6.3V6M

@

@

1

C111

C111

2

22U_0805_6.3V6M

1

2

1

2

1

C101

C101

C102

C102

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

@

@

@

@

1

C113

C113

C112

C112

2

Bottom Socket Edge

330U_D2_2V_Y

330U_D2_2V_Y

1

+1.8VS_VCCPLL

C122

330U_D2_2V_Y+C122

330U_D2_2V_Y

1

+

2

+

+

C115

C115

2

C125

10U_0805_6.3V6M

C125

10U_0805_6.3V6M

1

2

Vaxg

Can connect to GND if motherboard only‧
supports external graphics and if GFX VR is not
stuffed in a common motherboard design,

VAXG can be left floating in a common‧
motherboard design (Gfx VR keeps VAXG from
floating) if the VR is stuffed

A A

+1.8VS

R88

R88

0_0805_5%

0_0805_5%

1 2

EDS1.3

QC DC 33A

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C94

C94

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C98

C98

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C103

C103

2

22U_0805_6.3V6M

22U_0805_6.3V6M

@

@

1

C114

C114

2

330U_D2_2V_Y

330U_D2_2V_Y

1

@

@

+

+

C116

C116

2

AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17

AL24
AL23
AL21
AL20
AL18

AL17
AK24
AK23
AK21
AK20
AK18
AK17

AJ24

AJ23

AJ21

AJ20

AJ18

AJ17
AH24
AH23
AH21
AH20
AH18
AH17

JCPU1G

JCPU1G

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54

1.2A

B6

VCCPLL1

C124

1U_0402_6.3V6K

C124

1U_0402_6.3V6K

C123

1U_0402_6.3V6K

C123

1U_0402_6.3V6K

1

1

2

2

A6

VCCPLL2

A2

VCCPLL3

Sandy Bridge_rPGA_Rev1p0

Sandy Bridge_rPGA_Rev1p0
CONN@

CONN@

POWER

POWER

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

VREFMISC

VREFMISC

GRAPHICS

GRAPHICS

DDR3 -1.5V RAILS

DDR3 -1.5V RAILS

SA RAIL

SA RAIL

VCCSA_SENSE

1.8V RAIL

1.8V RAIL

VAXG_SENSE

SM_VREF

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

FC_C22

VCCSA_VID1

AK35
AK34

AL1

AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

M27
M26
L26
J26
J25
J24
H26
H25

H23

C22
C24

VCC_AXG_SENSE 54
VSS_AXG_SENSE 54

+V_SM_VREF should
have 20 mil trace width

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10A

6A

H_FC_C22

1 2

C99

C99

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C105

C105

2

+VCCSA
10U_0805_6.3V6M

10U_0805_6.3V6M

1

C117

C117

2

R89

R89
10K_0402_5%

10K_0402_5%

+1.5V_CPU_VDDQ

10/2

R84 0_0402_5%R84 0_0402_5%

1

2

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

C106

C106

C118

C118

12

1

2

1

2

R90

@R90

@

0_0402_5%

0_0402_5%

1

C107

C107

2

10U_0805_6.3V6M

10U_0805_6.3V6M

C119

C119

1

2

1

2

1 2

+1.5V_CPU_VDDQ

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

1

1

C108

C108

C109

C109

2

2

+VCCSA

10U_0603_6.3V6M

10U_0603_6.3V6M

@

@

1

C120

C120

1

+

+

C121

2

C121
330U_D2_2V_Y

330U_D2_2V_Y

2

R87 0_0402_5%R87 0_0402_5%

VCCSA_SENSE 52

VCCSA_VID1 52

1 2

PAD-OPEN 4x4m

PAD-OPEN 4x4m

10U_0805_6.3V6M

10U_0805_6.3V6M

1

+

+

C110

C110

330U_D2_2V_Y

330U_D2_2V_Y

2

R86 100_0402_5%R86 100_0402_5%

1 2

1 2

C104

C104

9/16, SM50

+V_SM_VREF+V_SM_VREF_CNT

+1.5VS

JP1

@JP1

@

VCCSA_SENSE

12

R83

R83
1K_0402_1%

1K_0402_1%

12

R85

R85
1K_0402_1%

1K_0402_1%

VSSSA_SENSE 52

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01 2010/12/31

2009/12/01 2010/12/31

2009/12/01 2010/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

4019BI

4019BI

4019BI

1

957Tuesday, December 14, 2010

957Tuesday, December 14, 2010

957Tuesday, December 14, 2010

A

A

A

of

5

D D

C C

B B

4

JCPU1H

JCPU1H

AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10

AR25
AR22
AR19
AR16
AR13
AR10

AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10

AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10

AM29
AM25
AM22
AM19
AM16
AM13
AM10

AM7
AM4
AM3
AM2

AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10

AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10

AJ25

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10

AT7

VSS11

AT4

VSS12

AT3

VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19

AR7

VSS20

AR4

VSS21

AR2

VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31

AP7

VSS32

AP4

VSS33

AP1

VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42

AN7

VSS43

AN4

VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

AL7

VSS66

AL4

VSS67

AL2

VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77

AK7

VSS78

AK4

VSS79
VSS80

VSS

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

3

JCPU1I

JCPU1I

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186

M34

VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204

H33

VSS205

H30

VSS206

H27

VSS207

H24

VSS208

H21

VSS209

H18

VSS210

H15

VSS211

H13

VSS212

H10

VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222

G35

VSS223

G32

VSS224

G29

VSS225

G26

VSS226

G23

VSS227

G20

VSS228

G17

VSS229

G11

VSS230

F34

VSS231

F31

VSS232

F29

VSS233

VSS

VSS

2

VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

1

F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

Sandy Bridge_rPGA_Rev1p0

Sandy Bridge_rPGA_Rev1p0

Sandy Bridge_rPGA_Rev1p0
CONN@

CONN@

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01 2010/12/31

2009/12/01 2010/12/31

2009/12/01 2010/12/31

Sandy Bridge_rPGA_Rev1p0
CONN@

CONN@

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

4019BI

4019BI

4019BI

1

10 57Tuesday, December 14, 2010

10 57Tuesday, December 14, 2010

10 57Tuesday, December 14, 2010

A

A

A

5

+V_DDR_M3_REFA

D D

C C

B B

A A

R2016

R2016

1 2

0_0402_5%

0_0402_5%
@

@

+1.5V

12

R2001

R2001
1K_0402_1%

1K_0402_1%

12

R2002

R2002
1K_0402_1%

1K_0402_1%

All VREF traces should
have 10 mil trace width

<Address: 00>

DIMM_A Reserve H:4mm

5

4

+1.5V

JDIMM1

R2014

R2014

JDIMM1

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

FOX_AS0A621-U4RG-7H

FOX_AS0A621-U4RG-7H
CONN@

CONN@

RESET#

VREF_CA

EVENT#

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2.2U_0603_6.3V6K
C2000

C2000

12

DDR_CKE0_DIMMA6

DDR_A_BS26

M_CLK_DDR06
M_CLK_DDR#06

DDR_A_BS06
DDR_A_WE#6

DDR_A_CAS#6

DDR_CS1_DIMMA#6

+3VS

+0.75VS +0.75VS

C2020

0.1U_0402_16V4Z

C2020

0.1U_0402_16V4Z

12

4

DDR_A_D0

C2001

C2001

DDR_A_D1

12

DDR_A_DM0
DDR_A_D2

DDR_A_D3
DDR_A_D8

DDR_A_D9
DDR_A_DQS#1

DDR_A_DQS1
DDR_A_D10

DDR_A_D11
DDR_A_D16

DDR_A_D17
DDR_A_DQS#2

DDR_A_DQS2
DDR_A_D18

DDR_A_D19
DDR_A_D24 DDR_A_D29

DDR_A_D25
DDR_A_DM3
DDR_A_D26

DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9 DDR_A_MA7

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

M_CLK_DDR0 M_CLK_DDR1

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13

DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D48

DDR_A_D49
DDR_A_DQS#6

DDR_A_DQS6
DDR_A_D50

DDR_A_D51
DDR_A_D56

DDR_A_D57
DDR_A_DM7
DDR_A_D58

DDR_A_D59

R2013

10K_0402_5%

R2013

10K_0402_5%

C2021

2.2U_0603_6.3V6K

C2021

2.2U_0603_6.3V6K

12

10K_0402_5%

10K_0402_5%

12

1 2

+DIMM0_VREF

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2.2U_0603_6.3V6K

VSS
DQ4
DQ5
VSS

DQS0#

DQS0

VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS
DQ14
DQ15

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

CKE1

VDD

A15
A14

VDD

A11

A7

VDD

A6
A4

VDD

A2
A0

VDD

CK1

CK1#

VDD

BA1

RAS#

VDD

S0#

ODT0

VDD
ODT1

NC

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SDA

SCL
VTT

GND2

BOSS2

Issued Date

Issued Date

Issued Date

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206
208

3

+1.5V

DDR_A_D4
DDR_A_D5

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D6
DDR_A_D7

DDR_A_D12
DDR_A_D13

DDR_A_DM1
DDR3_DRAMRST#

DDR_A_D14
DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_DM2
DDR_A_D22

DDR_A_D23
DDR_A_D28

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D31

DDR_CKE1_DIMMA
DDR_A_MA15

DDR_A_MA14
DDR_A_MA11

DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

M_CLK_DDR#1M_CLK_DDR#0
DDR_A_BS1

DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
M_ODT1

DDR_A_D36
DDR_A_D37

DDR_A_DM4
DDR_A_D38

DDR_A_D39
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D47
DDR_A_D52

DDR_A_D53
DDR_A_DM6
DDR_A_D54

DDR_A_D55
DDR_A_D60

DDR_A_D61
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

D_CK_SDATA
D_CK_SCLK

3

SP07000NZ00

2009/12/01

2009/12/01

2009/12/01

DDR3_DRAMRST# 6,12

DDR_CKE1_DIMMA 6

M_CLK_DDR1 6
M_CLK_DDR#1 6

DDR_A_BS1 6
DDR_A_RAS# 6

DDR_CS0_DIMMA# 6
M_ODT0 6

M_ODT1 6

+VREF_CA

12

D_CK_SDATA 12,14
D_CK_SCLK 12,14

Compal Secret Data

Compal Secret Data

Compal Secret Data

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K
C2014

C2014

0.1U_0402_16V4Z

0.1U_0402_16V4Z

12

Deciphered Date

Deciphered Date

Deciphered Date

C2015

C2015

+1.5V

12

12

R2003

R2003
1K_0402_1%

1K_0402_1%

JM50

R2004

R2004
1K_0402_1%

1K_0402_1%

2

2010/12/31

2010/12/31

2010/12/31

2

1

DDR_A_DQS#[0..7] 6

DDR_A_DQS[0..7] 6

DDR_A_D[0..63] 6

DDR_A_MA[0..15] 6

Layout Note:

+1.5V

1U_0402_6.3V6K

1U_0402_6.3V6K

12

+1.5V

10U_0603_6.3V6M

10U_0603_6.3V6M

12

+0.75VS

1U_0402_6.3V6K

1U_0402_6.3V6K

12

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Place near JDIMM1

C2004

1U_0402_6.3V6K

C2004

1U_0402_6.3V6K

C2005

1U_0402_6.3V6K

C2005

12

C2009

C2009

12

1U_0402_6.3V6K

12

C2010

10U_0603_6.3V6M

C2010

10U_0603_6.3V6M

12

C2018

1U_0402_6.3V6K

C2018

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

C2011

10U_0603_6.3V6M

C2011

10U_0603_6.3V6M

12

12

C2019

1U_0402_6.3V6K

C2019

1U_0402_6.3V6K

12

C2003

1U_0402_6.3V6K

C2003

1U_0402_6.3V6K

C2002

C2002

12

10U_0603_6.3V6M

10U_0603_6.3V6M12C2008

10U_0603_6.3V6M

C2008

10U_0603_6.3V6M

C2007

C2007

12

Layout Note:
Place near JDIMM1.203,204

C2016

C2016

C2017

1U_0402_6.3V6K

C2017

1U_0402_6.3V6K

12

Compal Electronics, Inc.

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

4019BI

4019BI

4019BI

Tuesday, December 14, 2010

Tuesday, December 14, 2010

Tuesday, December 14, 2010

1

C2012

C2012

10U_0603_6.3V6M

10U_0603_6.3V6M

@

@

C2013

C2013

12

11

11

11

330U_D2_2V_Y

330U_D2_2V_Y

C2006

C2006

12

+

+

A

A

A

57

57

57

5

+V_DDR_M3_REFB

D D

C C

B B

A A

R2040

R2040

1 2

0_0402_5%

0_0402_5%
@

@

+1.5V

12

R2015

R2015
1K_0402_1%

1K_0402_1%

12

R2017

R2017
1K_0402_1%

1K_0402_1%

10K_0402_5%

10K_0402_5%

+0.75VS

R2028

R2028

4

C2022

2.2U_0603_6.3V6K

C2022

2.2U_0603_6.3V6K

12

All VREF traces should
have 10 mil trace width

DDR_CKE2_DIMMB6

DDR_B_BS26

M_CLK_DDR26
M_CLK_DDR#26

DDR_B_BS06
DDR_B_WE#6

DDR_B_CAS#6

DDR_CS3_DIMMB#6

+3VS

C2043

2.2U_0603_6.3V6K

C2043

2.2U_0603_6.3V6K

C2042

0.1U_0402_16V4Z

C2042

0.1U_0402_16V4Z

12

12

12

3

+1.5V

+DIMM1_VREF

C2023

0.1U_0402_16V4Z

C2023

0.1U_0402_16V4Z
DDR_B_D0

12

DDR_B_D1
DDR_B_DM0
DDR_B_D2

DDR_B_D3
DDR_B_D8

DDR_B_D9
DDR_B_DQS#1

DDR_B_DQS1
DDR_B_D10

DDR_B_D11
DDR_B_D16

DDR_B_D17
DDR_B_DQS#2

DDR_B_DQS2
DDR_B_D18

DDR_B_D19
DDR_B_D24

DDR_B_D25
DDR_B_DM3
DDR_B_D26

DDR_B_D27

DDR_CKE2_DIMMB DDR_CKE3_DIMMB

DDR_B_BS2

DDR_B_MA9
DDR_B_MA8

M_CLK_DDR2 M_CLK_DDR3
M_CLK_DDR#2 M_CLK_DDR#3

DDR_B_MA10
DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

DDR_B_MA13
DDR_CS3_DIMMB#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49
DDR_B_DQS#6

DDR_B_DQS6
DDR_B_D50

+3VS

DDR_B_D51
DDR_B_D56

DDR_B_D57
DDR_B_DM7
DDR_B_D58

DDR_B_D59

12

R2029

R2029

10K_0402_5%

10K_0402_5%

JDIMM2

3
5
7

9
11
13
15
17
19
21
23
25
27

33
35

39
41

45
47
49
51
53
55
57
59

63
67

69

73
75
77
79
81
83
85
87
89
91
93
95
97
99

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

205

FOX_AS0A621-U4SG-7H

FOX_AS0A621-U4SG-7H

CONN@JDIMM2

CONN@

VREF_DQ1VSS1
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS129RESET#
VSS1131VSS12
DQ10
DQ11
VSS1337VSS14
DQ16
DQ17
VSS1543VSS16
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS2261DQS#3
DM3
VSS2365VSS24
DQ26
DQ27
VSS2571VSS26

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

G1

DQ4
DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6

DQ7
VSS8
DQ12
DQ13

VSS10

DM1

DQ14
DQ15

DQ20
DQ21

DM2

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3

DQ30
DQ31

CKE1

VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA
VTT2

CK1

BA1

S0#

NC2

SCL

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78

A15

80

A14

82
84

A11

86

A7

88
90

A6

92

A4

94
96

A2

98

A0

100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

G2

+1.5V

DDR_B_D4
DDR_B_D5

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D6
DDR_B_D7

DDR_B_D12
DDR_B_D13

DDR_B_DM1
DDR3_DRAMRST#

DDR_B_D14
DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31

DDR_B_MA15
DDR_B_MA14

DDR_B_MA11DDR_B_MA12
DDR_B_MA7

DDR_B_MA6
DDR_B_MA4DDR_B_MA5

DDR_B_MA2DDR_B_MA3
DDR_B_MA0DDR_B_MA1

DDR_B_BS1
DDR_B_RAS#

DDR_CS2_DIMMB#
M_ODT2

M_ODT3

+VREF_CB
DDR_B_D36

DDR_B_D37
DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_D61
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63

D_CK_SDATA
D_CK_SCLK

+0.75VS

DDR3_DRAMRST# 6,11

DDR_CKE3_DIMMB 6

M_CLK_DDR3 6
M_CLK_DDR#3 6

DDR_B_BS1 6
DDR_B_RAS# 6

DDR_CS2_DIMMB# 6
M_ODT2 6

M_ODT3 6

12

D_CK_SDATA 11,14
D_CK_SCLK 11,14

SP07000NN00

2

+1.5V

C2025

1U_0402_6.3V6K

C2025

1U_0402_6.3V6K

C2024

1U_0402_6.3V6K

C2024

1U_0402_6.3V6K

12

12

+1.5V

C2029

10U_0603_6.3V6M

C2029

10U_0603_6.3V6M

12

+1.5V

12

R2018

R2018
1K_0402_1%

1K_0402_1%

C2040

2.2U_0603_6.3V6K

C2040

2.2U_0603_6.3V6K

C2041

0.1U_0402_16V4Z

C2041

0.1U_0402_16V4Z

12

12

R2019

R2019
1K_0402_1%

1K_0402_1%

JM50

+0.75VS

C2036

1U_0402_6.3V6K

C2036

1U_0402_6.3V6K

12

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

12

Layout Note:
Place near JDIMM2

C2031

10U_0603_6.3V6M

C2031

10U_0603_6.3V6M

C2030

10U_0603_6.3V6M

C2030

10U_0603_6.3V6M

12

12

Layout Note:
Place near JDIMM2.203,204

C2037

1U_0402_6.3V6K

C2037

1U_0402_6.3V6K

12

12

C2026

1U_0402_6.3V6K

C2026

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

12

C2038

1U_0402_6.3V6K

C2038

1U_0402_6.3V6K

1

DDR_B_DQS#[0..7] 6

DDR_B_DQS[0..7] 6

DDR_B_D[0..63] 6

DDR_B_MA[0..15] 6

C2027

1U_0402_6.3V6K

C2027

1U_0402_6.3V6K

12

C2032

C2032

C2033

10U_0603_6.3V6M

C2033

10U_0603_6.3V6M

12

12

C2039

1U_0402_6.3V6K

C2039

1U_0402_6.3V6K

12

C2034

10U_0603_6.3V6M

C2034

10U_0603_6.3V6M

330U_D2_2V_Y

330U_D2_2V_Y

10U_0603_6.3V6M

10U_0603_6.3V6M

@

@

@

@

C2028

C2028

C2035

C2035

12

12

+

+

Security Classification

Security Classification

<Address: 01>

DIMM_B Standard type H:4mm

5

4

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01

2009/12/01

2009/12/01

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2010/12/31

2010/12/31

2010/12/31

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

4019BI

4019BI

4019BI

Tuesday, December 14, 2010

Tuesday, December 14, 2010

Tuesday, December 14, 2010

12

12

12

1

57

57

57

A

A

A

5

PCH_RTCX1

32.768KHZ_12.5PF_Q13MC14610002Y132.768KHZ_12.5PF_Q13MC14610002

R105

@R105

@

1K_0402_5%

1K_0402_5%

R108

R108

0_0402_5%

0_0402_5%

12

1 2

1 2

1 2

1

C129

C129
18P_0402_50V8J

18P_0402_50V8J

2

12

12

R119

R119

33_0402_5%

33_0402_5%

R125

R125

33_0402_5%

33_0402_5%

R128

R128

33_0402_5%

33_0402_5%

PCH_RTCX2

SM_INTRUDER#
PCH_INTVRMEN

HDA_SPKR

HDA_SDOUT

HDA_SYNC

HDA_BIT_CLK

HDA_RST#

HDA_SDOUT_R

+RTCVCC

1U_0603_10V4Z

1U_0603_10V4Z

1 2

R93 20K_0402_5%R93 20K_0402_5%

1 2

R94 20K_0402_5%R94 20K_0402_5%

1U_0603_10V4Z

1U_0603_10V4Z

HDA_SPKR46

HDA_SDIN046

PADT1PAD
PADT2PAD
PADT9PAD

1 2

R91 10M_0402_5%R91 10M_0402_5%

1

Y1

18P_0402_50V8J

18P_0402_50V8J

D D

+RTCVCC

R96 1M_0402_5%R96 1M_0402_5%
R98 330K_0402_5%R98 330K_0402_5%

*

(INTVRMEN should always be pull high.)

+3VS

*

HDA_SDO41

C C

HDA_SDO

ME debug mode,this signal has a weak internal PD
Low = Disabled (Default)

*

High = Enabled [Flash Descriptor Security Overide]

+3VALW_PCH

R112 1K_0402_5%R112 1K_0402_5%

OSC4OSC

1

NC3NC

C128

C128

2

2

1 2
1 2

INTVRMEN

H：Integrated VRM enable
L：Integrated VRM disable

R102 1K_0402_5%@R102 1K_0402_5%@

1 2

HIGH= Enable ( No Reboot )
LOW= Disable (Default)

+3VALW_PCH

This signal has a weak internal pull-down
On Die PLL VR Select is supplied by

1.5V when sampled high

*

1.8V when sampled low
Needs to be pulled High for Huron River platfrom

HDA_BITCLK_AUDIO46

B B

HDA_RST#_AUDIO46

HDA_SDOUT_AUDIO46

C126

C126

C130

C130

ME

R113

R113

51_0402_5%

51_0402_5%

T1
T2
T9

1

2

1

2

12

CMOS

12

@

12

@

PCH_RTCX1
PCH_RTCX2
PCH_RTCRST#
PCH_SRTCRST#
SM_INTRUDER#
PCH_INTVRMEN

HDA_BIT_CLK
HDA_SYNC
HDA_SPKR
HDA_RST#

HDA_SDIN0

PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO

PCH_SPI_CLK
PCH_SPI_CS#

PCH_SPI_SI
PCH_SPI_SO

JCMOS1

SHORT PADS@JCMOS1

SHORT PADS

JME1

SHORT PADS@JME1

SHORT PADS

HDA_SDOUT

4

PCH_RTCRST#
PCH_SRTCRST#

A20
C20
D20
G22
K22
C17

N34
L34
T10
K34

E34
G34
C34
A34

A36

C36
N32

J3

H7

K5

H1

T3

Y14

T1

V4

U3

U3A

U3A

RTCX1
RTCX2
RTCRST#
SRTCRST#
INTRUDER#
INTVRMEN

HDA_BCLK
HDA_SYNC
SPKR
HDA_RST#

HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3

HDA_SDO

HDA_DOCK_EN# / GPIO33
HDA_DOCK_RST# / GPIO13

JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO

SPI_CLK
SPI_CS0#
SPI_CS1#

SPI_MOSI
SPI_MISO

COUGARPOINT_FCBGA989~D

COUGARPOINT_FCBGA989~D

JTAG

JTAG

RTCIHDA

RTCIHDA

SPI

SPI

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

LPC

LPC

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN

SATA 6G

SATA 6G

SATA1RXP
SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN

SATA

SATA

SATA4TXP
SATA5RXN

SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#
SATA0GP / GPIO21
SATA1GP / GPIO19

C38
A38
B37
C37

D36
E36

K36
V5

AM3
AM1
AP7
AP5

AM10
AM8
AP11
AP10

AD7
AD5
AH5
AH4

AB8
AB10
AF3
AF1

Y7
Y5
AD3
AD1

Y3
Y1
AB3
AB1

Y11
Y10

AB12
AB13

AH1

P3
V14
P1

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#

SERIRQ

SATA_COMP

SATA3_COMP

RBIAS_SATA3

PCH_SATALED#
PCH_GPIO21
PCH_GPIO19

3

For re-chareable RTC

RTC BAT and 1K ohm
are at Power page

LPC_AD0 41
LPC_AD1 41
LPC_AD2 41
LPC_AD3 41

LPC_FRAME# 41

SERIRQ 41

SATA_DTX_C_PRX_N0 38
SATA_DTX_C_PRX_P0 38
SATA_PTX_DRX_N0 38
SATA_PTX_DRX_P0 38

+1.05VS_VCC_SATA

R114

R114

37.4_0402_1%

37.4_0402_1%
1 2

+1.05VS_SATA3

R116

R116

49.9_0402_1%

49.9_0402_1%

1 2

1 2

R117 750_0402_1%R117 750_0402_1%

PCH_SATALED# 42

PADT7PAD

T7

+RTCBATT

HDD

2

1U_0603_10V4Z

1U_0603_10V4Z

12
12
12
12

+RTCVCC

C127

C127

W=20milstrace width 10milW=20mils

1

2

+CHGRTC

D1

D1

2

1

3

BAS40-04_SOT23-3

BAS40-04_SOT23-3

Place C127 close to PCH.

SERIRQ
PCH_SATALED#
PCH_GPIO21
PCH_GPIO19

R97 10K_0402_5%R97 10K_0402_5%
R99 10K_0402_5%R99 10K_0402_5%
R129 10K_0402_5%R129 10K_0402_5%
R394 4.7K_0402_5%R394 4.7K_0402_5%

Debug Port DG 1.2 PH 4.7K +3VS

SPI ROM FOR ME ( 4MByte )

C131

C131

PCH_SPI_WP#

PCH_SPI_HOLD#
PCH_SPI_CS#_R
PCH_SPI_CLK_R
PCH_SPI_SI_R

R115

@R115

@

PCH_SPI_CLK_R

PCH_SPI_WP#

PCH_SPI_HOLD#

+3V_DSW_SPI

If use SPI programmer,
R854 should be open
(Normal is pop)

+3VS

R106

R106

Please short PJP35

0_0402_5%

0_0402_5%
1 2

D6

D6

12

@

@

RB751V-40_SOD323-2

RB751V-40_SOD323-2

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

9/06 SM50

PCH_SPI_CS#

1 2

R109 0_0402_5%R109 0_0402_5%

PCH_SPI_CLK

1 2

R110 0_0402_5%R110 0_0402_5%

PCH_SPI_SI

1 2

R111 0_0402_5%R111 0_0402_5%

C132

@C132

@

22P_0402_50V8J

22P_0402_50V8J

Reserve for EMI please close to UH1

12

33_0402_5%

33_0402_5%

1 2

+3VS

need to check

R103 3.3K_0402_5%R103 3.3K_0402_5%

1 2

R104 3.3K_0402_5%R104 3.3K_0402_5%

1 2

PCH_SPI_SO PCH_SPI_SO_R

U4

8
3
7
1
6
5

SP07000OJ00

SPI ROM Socket

R107 0_0402_5%R107 0_0402_5%

CONN@U4

CONN@

VCC

VSS
W
HOLD
S
C

Q

D

WIESO_G6179-100000

WIESO_G6179-100000

45@

45@

1 2

4

PCH_SPI_SO_R

2

&U1

&U1

S IC FL 32M W25Q32BVSSIG SOIC 8P SPI ROM

S IC FL 32M W25Q32BVSSIG SOIC 8P SPI ROM

SA00003K800

+3VS

1

HDA_BITCLK_AUDIO

@

@

SM50

1 2

C133 22P_0402_50V8J

C133 22P_0402_50V8J

HDA_SDOUT_AUDIO

@

@

1 2

C134 22P_0402_50V8J

C134 22P_0402_50V8J

Prevent back drive issue.

From JM50
Prevent back drive issue.

HDA_SDOUT_R HDA_SDOUT

A A

+3VS

G

G

S

S

1 2

R100@

R100@
0_0402_5%

0_0402_5%

Q4

Q4
BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

123

D

D

5

HDA_SYNC_AUDIO46

4

+3VS

G

G

2

Q7

Q7
BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

HDA_SYNC

13

D

S

D

S

1 2

R123

@R123

@

0_0402_5%

0_0402_5%

DG1.5, potential leakage concern

10/11 move 33 ohm and 1M ohm to sub board

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01 2010/12/31

2009/12/01 2010/12/31

2009/12/01 2010/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Title

Title

Title

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

4019BI

4019BI

4019BI

Date: Sheet

Date: Sheet

Date: Sheet

1

of

13 57Tuesday, December 14, 2010

of

13 57Tuesday, December 14, 2010

of

13 57Tuesday, December 14, 2010

A

A

A

5

12
12

12
12

PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1

PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2

PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3
PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P3

PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4

PCH_GPIO73

CLK_MINI1#
CLK_MINI1

CLK_USB30#
CLK_USB30

CLK_LAN#

CLK_CARD#
CLK_CARD

PCH_GPIO26

PCH_GPIO44

CLK_VGA#
CLK_VGA

PEG_CLKREQ#_R

PCH_GPIO45 XTAL25_OUT

PCH_GPIO46
CLK_BCLK_ITP#

CLK_BCLK_ITP

PEG_CLKREQ#_R

PCIE_PRX_DTX_N146

PCIE LAN

Wireless LAN

Card Reader

D D

USB3.0

Wireless LAN

C C

USB3.0

PCIE LAN

Card Reader

B B

+3VS

R174 10K_0402_5%R174 10K_0402_5%
R176 10K_0402_5%R176 10K_0402_5%

+3VALW_PCH

R180 10K_0402_5%R180 10K_0402_5%
R181 10K_0402_5%R181 10K_0402_5%
R182 10K_0402_5%R182 10K_0402_5%
R183 10K_0402_5%R183 10K_0402_5%
R184 10K_0402_5%R184 10K_0402_5%

A A

R185 10K_0402_5%R185 10K_0402_5%

PCIE_PRX_DTX_P146
PCIE_PTX_C_DRX_N146
PCIE_PTX_C_DRX_P146

PCIE_PRX_DTX_N239
PCIE_PRX_DTX_P239
PCIE_PTX_C_DRX_N239
PCIE_PTX_C_DRX_P239

PCIE_PRX_DTX_N340

PCIE_PRX_DTX_P340
PCIE_PTX_C_DRX_N340
PCIE_PTX_C_DRX_P340

PCIE_PRX_DTX_N444

PCIE_PRX_DTX_P444
PCIE_PTX_C_DRX_N444
PCIE_PTX_C_DRX_P444

CLK_PCIE_MINI1#39
CLK_PCIE_MINI139

MINI1_CLKREQ#39

CLK_PCIE_USB30#44
CLK_PCIE_USB3044

USB30_CLKREQ#44

CLK_PCIE_LAN#46
CLK_PCIE_LAN46

LAN_CLKREQ#46

CLK_PCIE_CARD#40
CLK_PCIE_CARD40

CARD_CLKREQ#40

CLK_PEG_VGA#22

CLK_PEG_VGA22

12
12

12
12
12
12
12
12

C135 0.1U_0402_10V7KC135 0.1U_0402_10V7K
C136 0.1U_0402_10V7KC136 0.1U_0402_10V7K

C137 0.1U_0402_10V7KC137 0.1U_0402_10V7K
C138 0.1U_0402_10V7KC138 0.1U_0402_10V7K

C212 0.1U_0402_10V7KC212 0.1U_0402_10V7K
C213 0.1U_0402_10V7KC213 0.1U_0402_10V7K

C214 0.1U_0402_10V7KC214 0.1U_0402_10V7K
C215 0.1U_0402_10V7KC215 0.1U_0402_10V7K

R149 0_0402_5%R149 0_0402_5%
R150 0_0402_5%R150 0_0402_5%

R151 0_0402_5%R151 0_0402_5%
R152 0_0402_5%R152 0_0402_5%

R153 0_0402_5%R153 0_0402_5%
R154 0_0402_5%R154 0_0402_5%

R333 0_0402_5%R333 0_0402_5%
R334 0_0402_5%R334 0_0402_5%

R338 0_0402_5%R338 0_0402_5%

MINI1_CLKREQ#
USB30_CLKREQ#

PCH_GPIO73
LAN_CLKREQ#
PCH_GPIO26
PCH_GPIO44
PCH_GPIO45
PCH_GPIO46

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2

R159 0_0402_5%R159 0_0402_5%

1 2

R160 0_0402_5%R160 0_0402_5%

1 2

T88PAD T88PAD
T89PAD T89PAD

4

BG34
AV32

AU32
BE34

BF34
BB32
AY32

BG36
AV34

AU34
BF36

BE36
AY34
BB34

BG37
BH37
AY36
BB36

BG38
AU36
AV36

BG40
AY40

BB40
BE38

BC38

AW38

AY38

AB49
AB47

AA48
AA47

AB42
AB40

AK14
AK13

+3VALW_PCH

12

R179

R179
10K_0402_5%

10K_0402_5%

for safe

BJ34

BJ36

BJ38

BJ40

Y40
Y39

J2

M1

V10

Y37
Y36

A8

Y43
Y45

L12

V45
V46

L14

E6

V40
V42

T13
V38

V37
K12

U3B

U3B

PERN1
PERP1
PETN1
PETP1

PERN2
PERP2
PETN2
PETP2

PERN3
PERP3
PETN3
PETP3

PERN4
PERP4
PETN4
PETP4

PERN5
PERP5
PETN5
PETP5

PERN6
PERP6
PETN6
PETP6

PERN7
PERP7
PETN7
PETP7

PERN8
PERP8
PETN8
PETP8

CLKOUT_PCIE0N
CLKOUT_PCIE0P

PCIECLKRQ0# / GPIO73

CLKOUT_PCIE1N
CLKOUT_PCIE1P

PCIECLKRQ1# / GPIO18

CLKOUT_PCIE2N
CLKOUT_PCIE2P

PCIECLKRQ2# / GPIO20

CLKOUT_PCIE3N
CLKOUT_PCIE3P

PCIECLKRQ3# / GPIO25

CLKOUT_PCIE4N
CLKOUT_PCIE4P

PCIECLKRQ4# / GPIO26

CLKOUT_PCIE5N
CLKOUT_PCIE5P

PCIECLKRQ5# / GPIO44

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

PEG_B_CLKRQ# / GPIO56

CLKOUT_PCIE6N
CLKOUT_PCIE6P

PCIECLKRQ6# / GPIO45
CLKOUT_PCIE7N

CLKOUT_PCIE7P
PCIECLKRQ7# / GPIO46
CLKOUT_BCLK0_N / CLKOUT_PCIE8N

CLKOUT_BCLK0_P / CLKOUT_PCIE8P

COUGARPOINT_FCBGA989~D

COUGARPOINT_FCBGA989~D

1 3

12

R381

R381
@

@

2.2K_0402_5%

2.2K_0402_5%

2

D

D

Q16

Q16

G

G

2N7002H_SOT23-3

2N7002H_SOT23-3
OPT@

OPT@

S

S

12

PCI-E*

PCI-E*

VGA_ON 17,45,55

R380

R380
@

@

2.2K_0402_5%

2.2K_0402_5%

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SMBUSController

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

Link

Link

PEG_A_CLKRQ# / GPIO47

CLOCKS

CLOCKS

CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P

CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P

CLKIN_PCILOOPBACK

CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

FLEX CLOCKS

R379

R379

1 2

0_0402_5%

0_0402_5%

OPT@

OPT@

E12
H14

SMBCLK

C9

SMBDATA

A12
C8

SML0CLK

G12

SML0DATA

C13

SML1CLK / GPIO58

SML1DATA / GPIO75

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKIN_DOT_96N

CLKIN_DOT_96P

E14
M16

M7

CL_CLK1

T11

CL_DATA1

P10

CL_RST1#

M10

AB37
AB38

AV22
AU22

AM12
AM13

BF18

CLKIN_DMI_N

BE18

CLKIN_DMI_P

BJ30

CLKIN_DMI2_N

BG30

CLKIN_DMI2_P

G24
E24

AK7
AK5

K45

REFCLK14IN

H45

V47

XTAL25_IN

V49

XTAL25_OUT

Y47

XCLK_RCOMP

K43
F47
H47
K49

Pull high at VGA side

PEG_CLKREQ# 22

3

LID_SW_OUT#
PCH_SMBCLK
PCH_SMBDATA

DRAMRST_CNTRL_PCH

PCH_SML0CLK
PCH_SML0DATA

PCH_GPIO74
PCH_SML1CLK
PCH_SML1DATA

PCH_GPIO47

CLK_CPU_DMI#
CLK_CPU_DMI

CLK_DP#
CLK_DP

CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI

CLKIN_DMI2#
CLKIN_DMI2CLK_LAN

CLK_BUF_DREF_96M#
CLK_BUF_DREF_96M

CLK_BUF_PCIE_SATA#
CLK_BUF_PCIE_SATA

CLK_BUF_ICH_14M

CLK_PCI_LPBACK

XTAL25_IN
XTAL25_OUT

XCLK_RCOMP

CLK_FLEX0
CLK_27M_TCLK_R
CLK_48M_USB3_PCH_R
DGPU_PRSNT#

LID_SW_OUT# 41
PCH_SMBCLK 39
PCH_SMBDATA 39

DRAMRST_CNTRL_PCH 6,7

check: no need to pull high?

CLK_CPU_DMI# 5
CLK_CPU_DMI 5

CLK_DP# 5
CLK_DP 5

CLK_PCI_LPBACK 17

+1.05VS_VCCDIFFCLKN

R168

R168

90.9_0402_1%

90.9_0402_1%
1 2

T8 PADT8 PAD
R170 22_0402_5%@R170 22_0402_5%@

R173 22_0402_5%@R173 22_0402_5%@

DGPU_PRSNT#

12

12

OPTIMUS

UMA

+3VS

12

1 2

R382

R382
10K_0402_5%

10K_0402_5%
UMA@

UMA@

R383

R383
10K_0402_5%

10K_0402_5%
OPT@

OPT@

CLK_27M_TCLK 22
CLK_48M_USB3_PCH 44

GPIO67

DGPU_PRSNT#

0
1

2

PCH_SMBCLK
PCH_SMBDATA
PCH_SML0CLK
PCH_SML0DATA
PCH_SML1CLK
PCH_SML1DATA
PCH_GPIO74
PCH_GPIO47
LID_SW_OUT#
DRAMRST_CNTRL_PCH

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

PCH_SMBDATA

6 1

R396 0_0402_5%

R396 0_0402_5%

PCH_SMBCLK

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

PCH_SML1DATA

R398 0_0402_5%

R398 0_0402_5%

PCH_SML1CLK EC_SMB_CK2

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI

CLKIN_DMI2#
CLKIN_DMI2

CLK_BUF_DREF_96M#
CLK_BUF_DREF_96M

CLK_BUF_PCIE_SATA#
CLK_BUF_PCIE_SATA

CLK_BUF_ICH_14M

XTAL25_IN

C143

C143
18P_0402_50V8J

18P_0402_50V8J

CLK_BUF_ICH_14M

CLK_PCI_LPBACK

R137 2.2K_0402_5%R137 2.2K_0402_5%
R138 2.2K_0402_5%R138 2.2K_0402_5%
R139 2.2K_0402_5%R139 2.2K_0402_5%
R140 2.2K_0402_5%R140 2.2K_0402_5%
R141 2.2K_0402_5%R141 2.2K_0402_5%
R142 2.2K_0402_5%R142 2.2K_0402_5%
R143 10K_0402_5%R143 10K_0402_5%
R144 10K_0402_5%R144 10K_0402_5%
R145 10K_0402_5%R145 10K_0402_5%
R146 1K_0402_5%R146 1K_0402_5%

+3VS

Q8A

Q8A

2

1 2

@

@

5

3 4

Q8B

Q8B

1 2

R397 0_0402_5%

R397 0_0402_5%

@

@

+3VS

Q9A

Q9A

2

6 1

1 2

@

@

3 4

Q9B

Q9B

1 2

R399 0_0402_5%

R399 0_0402_5%

@

@

R155 10K_0402_5%R155 10K_0402_5%
R156 10K_0402_5%R156 10K_0402_5%

R157 10K_0402_5%R157 10K_0402_5%
R158 10K_0402_5%R158 10K_0402_5%

R161 10K_0402_5%R161 10K_0402_5%
R162 10K_0402_5%R162 10K_0402_5%

R163 10K_0402_5%R163 10K_0402_5%
R164 10K_0402_5%R164 10K_0402_5%

R167 10K_0402_5%R167 10K_0402_5%

1 2

R169 1M_0402_5%R169 1M_0402_5%

25MHZ_20PF_7A25000012

25MHZ_20PF_7A25000012

1

2

R175

@R175

@

33_0402_5%

33_0402_5%

R178

@R178

@
33_0402_5%

33_0402_5%

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

R147

R147

4.7K_0402_5%

4.7K_0402_5%

1 2

D_CK_SDATA

R148

R148

4.7K_0402_5%

4.7K_0402_5%

1 2

D_CK_SCLK

EC_SMB_DA2

5

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2

Y2

Y2

12

12

12

Reserve for EMI please close to U60

Compal Electronics, Inc.

+3VS

D_CK_SDATA 11,12

+3VS

D_CK_SCLK 11,12

Pull up at EC side.

1

C144

C144
18P_0402_50V8J

18P_0402_50V8J

2

C145

@C145

@

22P_0402_50V8J

22P_0402_50V8J

1 2

C146

@C146

@

22P_0402_50V8J

22P_0402_50V8J

1 2

1

+3VALW_PCH

EC_SMB_DA2 22,41

EC_SMB_CK2 22,41

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01 2010/12/31

2009/12/01 2010/12/31

2009/12/01 2010/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Title

Title

Title

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

4019BI

4019BI

4019BI

Date: Sheet

Date: Sheet

Date: Sheet

1

of

14 57Tuesday, December 14, 2010

of

14 57Tuesday, December 14, 2010

of

14 57Tuesday, December 14, 2010

A

A

A

5

4

3

2

1

D D

U3C

DMI_CTX_PRX_N04
DMI_CTX_PRX_N14
DMI_CTX_PRX_N24
DMI_CTX_PRX_N34

DMI_CTX_PRX_P04
DMI_CTX_PRX_P14
DMI_CTX_PRX_P24

PBTN_OUT#41

DMI_CTX_PRX_P34
DMI_CRX_PTX_N04

DMI_CRX_PTX_N14
DMI_CRX_PTX_N24
DMI_CRX_PTX_N34

DMI_CRX_PTX_P04
DMI_CRX_PTX_P14
DMI_CRX_PTX_P24
DMI_CRX_PTX_P34

+1.05VS_VCCP

PCH_PWROK

ACIN41,45,48

1 2

R189 49.9_0402_1%R189 49.9_0402_1%

1 2

R190 750_0402_1%R190 750_0402_1%

4mil width and place
within 500mil of the PCH

R194 0_0402_5%R194 0_0402_5%

R199 0_0402_5%R199 0_0402_5%

R202 0_0402_5%R202 0_0402_5%

R205 0_0402_5%R205 0_0402_5%

R186

@R186

@

0_0402_5%

0_0402_5%

12

+3VS

5

U7

10/11

PCH_PWROK41

VGATE54

C C

R191 10K_0402_5%R191 10K_0402_5%

+3VS

R203 200_0402_5%R203 200_0402_5%

B B

+3VALW_PCH

R206 10K_0402_5%R206 10K_0402_5%
R207 200K_0402_5%R207 200K_0402_5%
R208 10K_0402_5%R208 10K_0402_5%
R209 10K_0402_5%R209 10K_0402_5%

1
2

R197

R197

0_0402_5%

0_0402_5%

@

@

U7

VCC

IN1

OUT

IN2

GND

MC74VHC1G08DFT2G_SC70-5

MC74VHC1G08DFT2G_SC70-5

3

12

SUSWARN#_RSUSACK#_R

12

12

12
12
12
12

SYS_PWROK

4

SYS_PWROK

PM_DRAM_PWRGD

SUSWARN#_R
PCH_ACIN
PCH_GPIO72
RI#

XDP_DBRESET#5

PM_DRAM_PWRGD5

PCH_RSMRST#41

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

RBIAS_CPY

1 2

1 2

1 2

1 2

D3

D3

1 2

RB751V-40_SOD323-2

RB751V-40_SOD323-2

DMI_IRCOMP

SUSACK#_R

XDP_DBRESET#_R

SYS_PWROK

PCH_PWROK_R

PM_DRAM_PWRGD

PCH_RSMRST#_R

SUSWARN#_R

PBTN_OUT#_R

PCH_ACIN

PCH_GPIO72

RI#

U3C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN# / SUS_PWR_DN_ACK / GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

COUGARPOINT_FCBGA989~D

COUGARPOINT_FCBGA989~D

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5

DMI

DMI

System Power Management

System Power Management

FDI_RXP6

FDI

FDI

FDI_RXP7

FDI_INT
FDI_FSYNC0
FDI_FSYNC1

FDI_LSYNC0
FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

AY14
BE14
BH13
BC12
BJ12
BG10
BG9

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

AW16
AV12
BC10
AV14
BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1

DSWODVREN

PCH_RSMRST#_R

WAKE#

PCH_GPIO32

SUS_STAT#

SUSCLK

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

SLP_A#

T14 PADT14 PAD

H_PM_SYNC

PCH_GPIO29

FDI_CTX_PRX_N0

BJ14

R195

R195
0_0402_5%

0_0402_5%

1 2

R201 0_0402_5%R201 0_0402_5%

T91 PADT91 PAD

FDI_CTX_PRX_N0 4
FDI_CTX_PRX_N1 4
FDI_CTX_PRX_N2 4
FDI_CTX_PRX_N3 4
FDI_CTX_PRX_N4 4
FDI_CTX_PRX_N5 4
FDI_CTX_PRX_N6 4
FDI_CTX_PRX_N7 4

FDI_CTX_PRX_P0 4
FDI_CTX_PRX_P1 4
FDI_CTX_PRX_P2 4
FDI_CTX_PRX_P3 4
FDI_CTX_PRX_P4 4
FDI_CTX_PRX_P5 4
FDI_CTX_PRX_P6 4
FDI_CTX_PRX_P7 4

FDI_INT 4
FDI_FSYNC0 4
FDI_FSYNC1 4
FDI_LSYNC0 4
FDI_LSYNC1 4

not support Deep S4,S5 DPWROK mux with PWROK
check list1.0 P.42

PCH_PCIE_WAKE# 39,44,46

T10 PADT10 PAD

12

T11 PADT11 PAD

T12 PADT12 PAD

T13 PADT13 PAD

T15 PADT15 PAD

PM_SLP_S5# 41

PM_SLP_S4# 41

PM_SLP_S3# 41

H_PM_SYNC 5

SUSCLK_R 41

Can be left NC when IAMT is not
support on the platfrom

not support Deep S4,S5 can NC
PCH EDS1.2 P.74

DSWODVREN

*

WAKE#
PCH_GPIO29

PCH_GPIO32

EC team suggestion
South Bridge side must have
pull-low 10K on this pin(GPIO32)

R187 330K_0402_5%R187 330K_0402_5%
R188 330K_0402_5%@R188 330K_0402_5%@

DSWODVREN - On Die DSW VR Enable
H

：

Enable

L

：

Disable

R193 10K_0402_5%R193 10K_0402_5%
R196 10K_0402_5%R196 10K_0402_5%

R389 8.2K_0402_5%R389 8.2K_0402_5%

R198 10K_0402_5%

R198 10K_0402_5%

1 2
1 2

1 2

@

@

1 2

12
12

+RTCVCC

+3VALW_PCH

+3VS

R210 10K_0402_5%R210 10K_0402_5%

A A

12

5

PCH_RSMRST#_R

No30

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01 2010/12/31

2009/12/01 2010/12/31

2009/12/01 2010/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

4019BI

4019BI

4019BI

1

15 57Tuesday, December 14, 2010

15 57Tuesday, December 14, 2010

15 57Tuesday, December 14, 2010

A

A

A

5

D D

4

3

2

1

Pull high at LVDS conn side.

PCH_ENVDD34
DPST_PWM34

PCH_LCD_CLK34
PCH_LCD_DATA34

IGPU_BKLT_EN

C C

B B

+3VS

+3VS

R222 2.2K_0402_5% R222 2.2K_0402_5%
R223 2.2K_0402_5% R223 2.2K_0402_5%

R215 0_0402_5% R215 0_0402_5%

R211

R211
100K_0402_5%

100K_0402_5%

1 2

R220 2.2K_0402_5% R220 2.2K_0402_5%
R221 2.2K_0402_5% R221 2.2K_0402_5%

R224 150_0402_1% R224 150_0402_1%
R227 150_0402_1% R227 150_0402_1%
R228 150_0402_1% R228 150_0402_1%

1 2

1 2
1 2

1 2
1 2

1 2
1 2
1 2

ENBKL

CTRL_CLK
CTRL_DATA

PCH_CRT_CLK
PCH_CRT_DATA

PCH_CRT_B
PCH_CRT_G
PCH_CRT_R

ENBKL 41

R212

R212

R214

R214

PCH_TXCLK-34
PCH_TXCLK+34

PCH_TXOUT0-34
PCH_TXOUT1-34
PCH_TXOUT2-34

PCH_TXOUT0+34
PCH_TXOUT1+34
PCH_TXOUT2+34

PCH_CRT_B35
PCH_CRT_G35
PCH_CRT_R35

PCH_CRT_CLK35

PCH_CRT_DATA35

PCH_CRT_HSYNC35
PCH_CRT_VSYNC35

2.37K_0402_1%

2.37K_0402_1%

0_0402_5%

0_0402_5%

1K_0402_0.5%

1K_0402_0.5%

IGPU_BKLT_EN

12

12

PCH_TXCLK­PCH_TXCLK+

PCH_TXOUT0­PCH_TXOUT1­PCH_TXOUT2-

PCH_TXOUT0+
PCH_TXOUT1+
PCH_TXOUT2+

PCH_CRT_B
PCH_CRT_G
PCH_CRT_R

PCH_CRT_CLK
PCH_CRT_DATA

PCH_CRT_HSYNC
PCH_CRT_VSYNC

R225

R225

CTRL_CLK
CTRL_DATA

LVDS_IBG

LVD_VREF

CRT_IREF

12

12

R226

R226
0_0402_5%

0_0402_5%

AF37
AF36

AE48
AE47

AK39
AK40

AN48

AM47

AK47

AJ48

AN47

AM49

AK49

AJ47

AF40
AF39

AH45
AH47
AF49
AF45

AH43
AH49
AF47
AF43

J47

M45

P45
T40

K47
T45

P39

N48

P49
T49

T39

M40

M47
M49

T43
T42

U3D

U3D

L_BKLTEN
L_VDD_EN

L_BKLTCTL
L_DDC_CLK

L_DDC_DATA
L_CTRL_CLK

L_CTRL_DATA
LVD_IBG

LVD_VBG
LVD_VREFH

LVD_VREFL

LVDSA_CLK#
LVDSA_CLK

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

LVDSB_CLK#
LVDSB_CLK

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED

CRT_DDC_CLK
CRT_DDC_DATA

CRT_HSYNC
CRT_VSYNC

DAC_IREF
CRT_IRTN

COUGARPOINT_FCBGA989~D

COUGARPOINT_FCBGA989~D

LVDS

LVDS

CRT

CRT

SDVO_INTN
SDVO_INTP

DDPB_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_HPD

DDPC_0N

DDPC_0P

DDPC_1N

DDPC_1P

DDPC_2N

DDPC_2P

DDPC_3N

DDPC_3P

DDPD_HPD

DDPD_0N

DDPD_0P

DDPD_1N

DDPD_1P

DDPD_2N

DDPD_2P

DDPD_3N

DDPD_3P

AP43
AP45

AM42
AM40

AP39
AP40

P38
M39

AT49
AT47
AT40

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

P46
P42

AP47
AP49
AT38

AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

M43
M36

AT45
AT43
BH41

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

SDVO_CTRLDATA strap pull high
at level shift page

SDVO_SCLK
SDVO_SDATA

PCH_DPB_HPD

PCH_DPB_N0
PCH_DPB_P0
PCH_DPB_N1
PCH_DPB_P1
PCH_DPB_N2
PCH_DPB_P2
PCH_DPB_N3
PCH_DPB_P3

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN
DDPB_AUXP

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN
DDPC_AUXP

Digital Display Interface

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN
DDPD_AUXP

SDVO_SCLK 36
SDVO_SDATA 36

PCH_DPB_HPD 36

PCH_DPB_N0 36
PCH_DPB_P0 36
PCH_DPB_N1 36
PCH_DPB_P1 36
PCH_DPB_N2 36
PCH_DPB_P2 36
PCH_DPB_N3 36
PCH_DPB_P3 36

HDMI D2
HDMI D1
HDMI D0
HDMI CLK

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01 2010/12/31

2009/12/01 2010/12/31

2009/12/01 2010/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

4019BI

4019BI

4019BI

1

A

A

16 57Tuesday, December 14, 2010

16 57Tuesday, December 14, 2010

16 57Tuesday, December 14, 2010

A

5

footprint should change to RP_0804_8P4R

+3VS

because RP_8P4R doesn't exist

R229

R229

PCI_PIRQA#

18

PCI_PIRQD#

27

PCI_PIRQC#

D D

R233 8.2K_0402_5%R233 8.2K_0402_5%

8.2K_8P4R_5%

8.2K_8P4R_5%
R230

R230

8.2K_8P4R_5%

8.2K_8P4R_5%
R231

R231

8.2K_8P4R_5%

8.2K_8P4R_5%

1 2

36
45

18
27
36
45

18
27
36
45

PCI_PIRQB#

PCH_GPIO55
PCH_GPIO51
PCH_GPIO5
PCH_GPIO52

PCH_GPIO2
PCH_GPIO4

PCH_GPIO3

No28

PCH_GPIO53

10/2

R234 8.2K_0402_5%R234 8.2K_0402_5%

1 2

C C

R388 100K_0402_5%R388 100K_0402_5%

1 2

DGPU_HOLD_RST#

PLT_RST#

Boot BIOS Strap bit1 BBS1

Boot BIOS

Bit10

1

1
0

C217

C217
10P_0402_50V8J

10P_0402_50V8J
@

@

Destination

Reserved

PCI
SPI
LPC

CLK_PCI_LPBACK14

CLK_PCI_LPC41

VGA_ON14,45,55

CLK_PCI_LPC

No14

Bit11

GNT1#/
GPIO51

0
110

0

RF Boris Tsai suggests

B B

CLK_PCI_LPBACK
CLK_PCI_LPC

C216

C216

10P_0402_50V8J

10P_0402_50V8J

@

@

2

2

1

1

4

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

12

12

T17PAD T17PAD
T18PAD T18PAD
T19PAD T19PAD

DGPU_HOLD_RST#
PCH_GPIO52
VGA_ON_R

PCH_GPIO51
PCH_GPIO53
PCH_GPIO55

PCH_GPIO2
PCH_GPIO3
PCH_GPIO4
PCH_GPIO5

PLT_RST#

R241

R241

0_0402_5%

0_0402_5%

T16PAD T16PAD

PLT_RST#5,40,41,44,46

R247 22_0402_5%R247 22_0402_5%
R248 22_0402_5%R248 22_0402_5%

1 2

CLK_PCI0
CLK_PCI1
CLK_PCI2
CLK_PCI3
CLK_PCI4

U3E

U3E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

TP25

BC30

TP26

BE32

TP27

BJ32

TP28

BC28

TP29

BE30

TP30

BF32

TP31

BG32

TP32

AV26

TP33

BB26

TP34

AU28

TP35

AY30

TP36

AU26

TP37

AY26

TP38

AV28

TP39

AW30

TP40

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

COUGARPOINT_FCBGA989~D

COUGARPOINT_FCBGA989~D

RSVD

RSVD

PCI

PCI

3

NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9

NV_DQ10 / NV_IO10

NVRAM

NVRAM

NV_DQ11 / NV_IO11
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15

NV_RE#_WRB0
NV_RE#_WRB1

NV_WE#_CK0
NV_WE#_CK1

USB

USB

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3

NV_DQS0
NV_DQS1

NV_ALE
NV_CLE

NV_RCOMP

NV_RB#

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USBP10N

USBP10P

USBP11N

USBP11P

USBP12N

USBP12P

USBP13N

USBP13P

USBRBIAS#

USBRBIAS

AY7
AV7
AU3
BG4

AT10
BC8

AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6

AV5

DF_TVS

AY1
AV10
AT8
AY5

BA2
AT12

BF3

USB20_N0

C24

USB20_P0

A24

USB20_N1

C25

USB20_P1

B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28

PCH HM65 config not support USB port 6 & 7.

M28

USB20_N8

L30

USB20_P8

K30

USB20_N9

G30

USB20_P9

E30

USB20_N10

C30

USB20_P10

A30
L32
K32

USB20_N12

G32

USB20_P12

E32

USB20_N13

C32

USB20_P13

A32

USBRBIAS

C33

B33

USB_OC0#

A14

USB_OC1#

K20

USB_OC2#

B17

USB_OC3#

C16

USB_OC4#

L16

USB_OC5#

A16

USB_OC6#

D14

USB_OC7#

C14

USB20_N0 46
USB20_P0 46
USB20_N1 37
USB20_P1 37

USB20_N8 39
USB20_P8 39
USB20_N9 39
USB20_P9 39
USB20_N10 34
USB20_P10 34

USB20_N12 39
USB20_P12 39
USB20_N13 40
USB20_P13 40

Within 500 mils

1 2

R246 22.6_0402_1%R246 22.6_0402_1%

USB_OC0# 46
USB_OC1# 37

2

USB conn (left)
USB conn (left)

Mini Card(WLAN)
Mini Card(WWAN)
CMOS Camera (LVDS)

Mini Card(SIM reserved)
Bluetooth

(For USB Port0)
(For USB Port1)

DMI Termination Voltage

DF_TVS

Set to Vcc when HIGH
Set to Vss when LOW

DG1.2

DF_TVS

R236

R236

1K_0402_5%

1K_0402_5%

CLOSE TO THE BRANCHING POINT

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#

R237 10K_0402_5%R237 10K_0402_5%

1 2

R238 10K_0402_5%R238 10K_0402_5%

1 2

R239 10K_0402_5%R239 10K_0402_5%

1 2

R240 10K_0402_5%R240 10K_0402_5%

1 2

R242 10K_0402_5%R242 10K_0402_5%

1 2

R243 10K_0402_5%R243 10K_0402_5%

1 2

R244 10K_0402_5%R244 10K_0402_5%

1 2

R245 10K_0402_5%R245 10K_0402_5%

1 2

OC[0..3] use for EHCI 1
OC[4..7] use for EHCI 2

1

+1.8VS

12

2.2K_0402_5%

2.2K_0402_5%
R235

R235

12

H_SNB_IVB# 5

+3VALW_PCH

R250

R250

No40

0_0402_5% @

0_0402_5% @

No40

+3VS

U10

U10

5

OPT@
PLT_RST#
DGPU_HOLD_RST#

A A

R232

R232

12

0_0402_5% OPT@

0_0402_5% OPT@

MC74VHC1G08DFT2G_SC70-5

MC74VHC1G08DFT2G_SC70-5

5

OPT@

1

VCC

IN1

2

IN2

4

OUT

GND

3

100_0402_5%

100_0402_5%
1 2

12

100K_0402_5%

100K_0402_5%
OPT@

OPT@

R253

R253

OPT@

OPT@

R252

R252

PLTRST_VGA# 22

PLT_RST#

MC74VHC1G08DFT2G_SC70-5

MC74VHC1G08DFT2G_SC70-5

4

1
2

12

+3VS

5

U11

U11

VCC

IN1
IN2

4

OUT

GND

3

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

R254

R254

100K_0402_5%

100K_0402_5%

3

PLT_RST_BUF# 39

Compal Secret Data

Compal Secret Data

2009/12/01 2010/12/31

2009/12/01 2010/12/31

2009/12/01 2010/12/31

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Title

Title

Title

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

4019BI

4019BI

4019BI

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

17 57Tuesday, December 14, 2010

17 57Tuesday, December 14, 2010

17 57Tuesday, December 14, 2010

A

A

A

5

+3VS

R264 10K_0402_5%

UMA@

R264 10K_0402_5%

UMA@

R393 10K_0402_5%OPT@R393 10K_0402_5%OPT@

1 2

GPIO28

On-Die PLL Voltage Regulator
This signal has a weak internal pull up

D D

：

On-Die voltage regulator enable

H

*

L：On-Die PLL Voltage Regulator disable

+3VALW_PCH

R395 4.7K_0402_5%@R395 4.7K_0402_5%@

1 2

R260 1K_0402_5%@R260 1K_0402_5%@

1 2

PCH_GPIO28

* OPTIMUS

Non-OPTIMUS

Debug Port DG 1.2 PH 4.7K +3VALW_PCH

Can be configured as wake input to
allow wakes from Deep Sleep.
If not used then use 8.2-kΩ to 10-kΩ
pull-down to GND.

WWAN_OFF#

PCH_GPIO36

PCH_GPIO0

PCH_GPIO1
PCH_GPIO6
PCH_GPIO16

PCH_GPIO22

PCH_GPIO39

BT_ON#
PCH_GPIO48
WL_OFF#

PCH_GPIO12
SMIB
PCH_GPIO57
PCH_GPIO24

PCH_GPIO35

PCH_GPIO27

No26
No34

+VRAM_1.5VS

R130

10K_0402_5%

10K_0402_5%
1 2

1U_0402_6.3V6K

1U_0402_6.3V6K

OPT@

OPT@

CRB1.0 PH10K to +3VALW
GPIO24 Unmultiplexed
NOTE: GPIO24 configuration
register bits are not cleared by
CF9h reset event.

C218

C218

OPT@R130

OPT@

R273

R273

10K_0402_5%

10K_0402_5%

OPT@

OPT@

2

Q5

Q5

1

OPT@

OPT@
AP2302GN-HF_SOT23-3

AP2302GN-HF_SOT23-3

2

R262 10K_0402_5%R262 10K_0402_5%

1 2

+3VS

C C

R275 100K_0402_5%R275 100K_0402_5%

1 2

R391 10K_0402_5%@R391 10K_0402_5%@

R277 200K_0402_5%@R277 200K_0402_5%@

1 2

+3VS

R255 10K_0402_5%R255 10K_0402_5%

R270 10K_0402_5%R270 10K_0402_5%

B B

+3VALW_PCH

A A

1 2

R271 10K_0402_5%R271 10K_0402_5%

1 2

R272 10K_0402_5%R272 10K_0402_5%

1 2

No20

R274 10K_0402_5%R274 10K_0402_5%

1 2

R276 10K_0402_5%R276 10K_0402_5%

1 2

R278 10K_0402_5%R278 10K_0402_5%

1 2

R279 10K_0402_5%R279 10K_0402_5%

1 2

R280 10K_0402_5%R280 10K_0402_5%

1 2

R281 10K_0402_5%R281 10K_0402_5%

1 2

R282 1K_0402_5%R282 1K_0402_5%

1 2

R283 10K_0402_5%R283 10K_0402_5%

1 2

R284 10K_0402_5%R284 10K_0402_5%

1 2

R285 10K_0402_5%R285 10K_0402_5%

1 2

1 2

R392 10K_0402_5%R392 10K_0402_5%

1 2

GPIO36: CRB1.0 PH200K to +3VS,
but CHK1.2 says pull down when not used

12

JM50 install, SM50 uninstall10/2

5

12

+3VALW

1 2
1

3

4

OPTIMUS_EN#

GPIO38

OPTIMUS_EN#

0
1

+3VS

R267

R267
10K_0402_5%

10K_0402_5%
1 2
13

D

D

Q17

Q17

2

OPT@

OPT@

G

G

S

S

2N7002H_SOT23-3

2N7002H_SOT23-3

4

3

U3F
PCH_GPIO0
PCH_GPIO1
PCH_GPIO6

EC_SCI#41
EC_SMI#41

SMIB44

BT_ON#39,40

WWAN_OFF#39

WL_OFF#39

EC_SCI#
EC_SMI#
PCH_GPIO12
SMIB

PCH_GPIO16

DGPU_PWROK

PCH_GPIO22
PCH_GPIO24
PCH_GPIO27
PCH_GPIO28
BT_ON#
PCH_GPIO35
PCH_GPIO36
WWAN_OFF#
OPTIMUS_EN#
PCH_GPIO39
PCH_GPIO48
WL_OFF#
PCH_GPIO57

T73PAD T73PAD
T74PAD T74PAD T24 PADT24 PAD
T75PAD T75PAD
T76PAD T76PAD
T77PAD T77PAD
T78PAD T78PAD
T79PAD T79PAD
T80PAD T80PAD
T27PAD T27PAD
T28PAD T28PAD
T29PAD T29PAD
T30PAD T30PAD
T31PAD T31PAD
T32PAD T32PAD

U3F

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24 / MEM_LED

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

COUGARPOINT_FCBGA989~D

COUGARPOINT_FCBGA989~D

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

TACH4 / GPIO68
TACH5 / GPIO69
TACH6 / GPIO70
TACH7 / GPIO71

A20GATE

RCIN#

PROCPWRGD

GPIO

GPIO

THRMTRIP#

CPU/MISC

CPU/MISC

INIT3_3V#

NC_1
NC_2
NC_3
NC_4
NC_5

VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23

NCTF

NCTF

VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32

2009/12/01 2010/12/31

2009/12/01 2010/12/31

2009/12/01 2010/12/31

PCH_GPIO68

C40

PCH_GPIO69

B41

PCH_GPIO70

C41

PCH_GPIO71

A40

P4

PCH_PECI_R

AU16

PECI

EC_KBRST#

P5
AY11

PCH_THRMTRIP#_R

AY10
T14

AH8
AK11
AH10
AK10
P37

BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

T20 PADT20 PAD
T21 PADT21 PAD
T22 PADT22 PAD
T23 PADT23 PAD
T63 PADT63 PAD

T25 PADT25 PAD
T26 PADT26 PAD
T64 PADT64 PAD
T65 PADT65 PAD
T81 PADT81 PAD
T66 PADT66 PAD
T67 PADT67 PAD
T68 PADT68 PAD
T69 PADT69 PAD
T70 PADT70 PAD
T71 PADT71 PAD
T72 PADT72 PAD

2

check: pull high?

@

1 2

R2650_0402_5%@R2650_0402_5%

1 2

R268 390_0402_5%R268 390_0402_5%

INIT3_3V

This signal has weak internal
PU, can't pull low

Intel schematic reviwe recommand.

2

H_PECI 5,41
EC_KBRST# 41
H_CPUPWRGD 5

H_THRMTRIP#

1

PCH_GPIO68
PCH_GPIO69

PCH_GPIO70
PCH_GPIO71

EC_KBRST#

+3VS

R263

R263
10K_0402_5%

10K_0402_5%

1 2

GATEA20 41

H_THRMTRIP# 5

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

SCHEMATIC,MB LA-A7121

4019BI

4019BI

4019BI

R256 10K_0402_5%R256 10K_0402_5%

1 2

R257 10K_0402_5%R257 10K_0402_5%

1 2

R258 10K_0402_5%R258 10K_0402_5%

1 2

R259 10K_0402_5%R259 10K_0402_5%

1 2

R261 10K_0402_5%R261 10K_0402_5%

1 2

18 57Tuesday, December 14, 2010

18 57Tuesday, December 14, 2010

1

18 57Tuesday, December 14, 2010

+3VS

+3VS

A

A

A