Compal LA-7092P P5WE6, Aspire 5253G, LA-7092P P5WH6, LA-7092P P5WS6, LA-7092P JE50 Schematic
...
A
1 1
B
C
D
E
Compal Confidential
2 2
JE50/HM50/SJV50_BZ
P5WE6/P5WH6/P5WS6 Schematics Document
AMD Brazos
Brazos with Zacate / Hudson M1 / Seymour XT
3 3
DIS only / UMA only / PX Muxless / PX Muxless with BACO
ZZZ
2010-10-28
LA-7092P REV: 0.3
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010/08/20 2011/08/20
2010/08/20 2011/08/20
2010/08/20 2011/08/20
Compal Secret Data
Compal Secret Data
Compal Secret Data
ZZZ
PCB
PCB
Part Number = DA60000L000
Part Number = DA60000L000
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Cover Page
Cover Page
Cover Page
LA-7092P P5WE6/H6/S6
LA-7092P P5WE6/H6/S6
LA-7092P P5WE6/H6/S6
E
0.3
0.3
1 46Friday, October 29, 2010
1 46Friday, October 29, 2010
1 46Friday, October 29, 2010
0.3
A
B
C
D
E
Compal Confidential
Model Name : P5WE6/P5WH6/P5WS6
JE50/HM50/SJV50_BZ
1 1
PCB PN : DA60000L000
VRAM 512M/1G
64M16/128M16 x 4
page 23
DDR3
Brazos
Vancuver Seymour
ATI
Thermal Sensor
ADM1032
page 19
Page 18,19,20,21,22
LVDS
page 10
uFCBGA-962
2 2
CRT
page 12
PCI-Express x 4
Gen2
DP0
DP1
AMD Brazos APU
FT1
BGA 413-Ball
19mm x 19mm
page 5,6,7
UMI Gen.1 x4
PCI-Express
HDMI
Conn.
page 11
2.5GT/s per lane
Memory BUS(DDR3)
Single Channel
1.5V DDRIII 800~1066MHz
USB port 0,1,2
USB
Conn x 3
page 33 page 10 page 33
USB port 5 USB port 7
CMOS
Camera
204pin DDRIII-SO-DIMM X2
USB port6
Card
Reader
RT5137
page 29
page 8,9
USB port 8
BANK 0, 1, 2, 3
Bluetooth
Conn
Mini
card
(WL)X1
page 29
FCH
Hudson-M1
BGA 605-Ball
3.3V 48MHz
3.3V 24.576MHz/48Mhz
23mm x 23mm
page 30
port 0
Gen2
SATA ODD
Su
LED
3 3
page 32
MINI Card
WLAN
page 29
RTC CKT.
page 13
LAN(GbE)
Atheros
AR8151
page 26
GPP2GPP3
RJ45
page 26
LPC BUS
Power On/Off CKT.
page 34
page 13,14,15,16,17
ENE KB930
page 31
S-ATA
SATA HDD
Conn.
b/B
port 1
USB
HD Audio
page 30
HDA Codec
CX20584
page 27
MIC Jack x 1
HP Jack x 1
Int MIC x 1
Int SPK x 1
page 28
Power sequence
VGA
DC/DC
page 24,25
DC/DC Interface CKT.
4 4
page 35
Fan Control
page 34
Touch Pad
page 32
EC I/O Buffer
page 32
Int.KBD
page 32
BIOS
page 32
Extend Card/B
Security Classification
Security Classification
Power Circuit
page 36,37,38,39,40,41
42,43,44,45
A
1. USB X2
2. ODD X1
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010/08/20 2011/08/20
2010/08/20 2011/08/20
2010/08/20 2011/08/20
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Block Diagrams
Block Diagrams
Block Diagrams
LA-7092P P5WE6/H6/S6
LA-7092P P5WE6/H6/S6
LA-7092P P5WE6/H6/S6
E
0.3
0.3
2 46Friday, October 29, 2010
2 46Friday, October 29, 2010
2 46Friday, October 29, 2010
0.3
A
Voltage Rails
Power Plane Description
VIN
B+
+VSB VSB always on power rail ON ON*ON
1 1
+APU_CORE_NB
+1.5V
+0.75VS 0.75VS switched power rail for DDR terminator
+1.05VS
+1.1VS 1.1VS switched power rail ON OFF OFF
+VGA_CORE Core voltage for GPU ON OFF OFF
+1.5VSG 1.5V switched power rail for GPU ON OFF OFF
+1.0VSG 1.0V switched power rail for GPU ON OFF OFF
2 2
+3V_LAN 3.3V power rail for LAN ON ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
EC SM Bus1 address
Device
SM Bus Controller 0
Device Address
APU SIC/SID (FCH_SMB3)
3 3
H_THERMTRIP# (FCH_ALERT#)
SM Bus Controller 1
Device Address HEX
DDR DIMM1 (FCH_SMB0)
DDR DIMM2 (FCH_SMB0)
WLAN (FCH_SMB0 )
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU (0.7-1.2V) ON+APU_CORE
1.0V switched power rail
1.5V power rail for CPU VDDIO and DDRIII
1.05V switched power rail for APU VDD10 ON OFF OFF
EC SM Bus2 address
Address Address
(FCH_SMB1 ~ FCH_SMB4, SMB_AL ERT#)
(FCH_SMB0)
1001-000xb
1001-001xb
DeviceHEX
ADM1032 (GPU)
HEX
90
92
B
S1 S3 S5
N/A N/A N/A
ON ON ON*+3VALW 3.3V always on power rail
ON ON ON*+5VALW 5V always on power rail
ON OFF
ON OFF
ON OFF
ON OFF+1.8VS 1.8V switched power rail OFF
ON+RTCVCC RT C power ON ON
1001-101xb
N/AN/AN/A
ON ON*+1.1VALW 1.1V always on power rail ON
OFF
OFF
OFF
ON
OFF
OFFON OFF+3VS 3. 3V switched power rail
OFFON OFF+5VS 5V switched power rail
OFF+3VSG 3.3V switched power rail for GPU ON OFF
OFF+1.8VSG 1.8V switched power rail for GPU ON OFF
ON
HEX
9AH
C
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SIGNAL
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
HIGH HIGH HIGH HIGH
LOW
LOW
LOW
LOW LOW LOW LOW
HIGH
LOWLOWLOW
HIGHHIGHHIGH
HIGH
HIGH
Board ID / SKU ID Table for AD channel
Vcc 3.3V +/- 5%
Board ID
0
1
2
3
4
5
6
7 NC
100K +/- 5%Ra/Rc/Re
Rb / Rd / Rf V min
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
AD_BID
0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
BOARD ID Table
Board ID
0
1
2
3
4
5
6
7
PCB Revision
EVT / DVT
Project ID Table
Board ID
0
1
2
3
4
5
6
7
PCB Revision
ON
ON
ON
ON
ON
ON
ON
OFF
ON
OFF
V typ
AD_BID
V
AD_BID
0 V 0 V
0.503 V
0.819 V
0.538 V
0.875 V
1.185 V 1.264 V
2.200 V
3.300 V
2.341 V
3.300 V
*UMA only :
D
BOARD ID Table
ON ON
ON
OFF
OFF
OFF
LOW
OFF
OFF
OFF
Board ID
0
1
2
3
4
5
6
7
Project ID Table
max
Board ID
0
1
2
3
4
5
6
7
BTO Option Table
BTO Item BOM Structure
Display from APU
Display from VGA
Use VGA
Muxless w/BACO
Muxless wo/BACO WOBACO@
Muxless
w/Vancouver Serise
w/Manhttan Serise MAN@
Bluetooth BT@
AR8151 8151@
Seymour
wo/Muxless
wo/VGA WOVGA@
APU 1.5G
APU 1.6G
UMA@
BT@ 8151@
WOVGA@ WOPX@
E
PCB Revision
PCB Revision
UMA@
DISO@
VGA@
BACO@
PX@
VAN@
Seymour@
WOPX@
15G@
16G@
VGA Chip SEL:
1. Seymour@ + Van@
2. Robson@ + Man@
*DIS only :
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010/08/20 2011/08/20
2010/08/20 2011/08/20
2010/08/20 2011/08/20
Compal Secret Data
Compal Secret Data
Compal Secret Data
*Muxless w/BACO :
Muxless wo/BACO :
Deciphered Date
Deciphered Date
Deciphered Date
D
APU Chip SEL:
1. 16G@
2. 15G@
DISO@VGA@
UMA@
UMA@
WOBACO@
VGA@ BACO@PX@
VGA@ WOBACO@PX@
Date: Sheet of
Date: Sheet of
Date: Sheet of
BT@ 8151@
WOPX@
BT@ 8151@
BT@ 8151@
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Compal Electronics, Inc.
Notes List
Notes List
Notes List
LA-7092P P5WE6/H6/S6
LA-7092P P5WE6/H6/S6
LA-7092P P5WE6/H6/S6
E
3 4 6Friday, October 29, 2010
3 4 6Friday, October 29, 2010
3 4 6Friday, October 29, 2010
0.3
0.3
0.3
5
Power-Up/Down Sequence
1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up
sequence, though a shorter ramp-up duration is preferred.
2. VDDR3 should ramp-up before or simultaneously with VDDC.
3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before
D D
DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10.
4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and
VDD_CT have ramped up.
5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to
ramp-up (or vice versa).)
4
3
2
1
Without BACO option :
PE_GPIO0 : Low -> Reset dGPU ; High ->Normal operation
PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON
BACO option :
PE_GPIO0 : High ->Normal operation (dGPU is not reseton BACO mode)
PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)
dGPU Power Pins Max current
PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT,
DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD,
DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI,
DPLL_PVDD, MPV18, and SPV18
DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and
Voltage
1.8V
1.0V
PX 3.0
OFF
OFF
BACO Mode
ON
ON
1679mA
575mA
SPV10
VDDR3(3.3VSG)
Note: Do not drive any IOs before VDDR3 is ramped up.
PCIE_VDDC
VDDR3 , and A2VDD
BIF_VDDC (current consumption = 55mA@1.0V, in
PCIE_VDDC(1.0V)
BACO mode)
VDDR1
C C
VDDR1(1.5VSG)
VDDC/VDDCI
1.0V
3.3V
Same as
VDDC
1.5V
1.12V
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
Same as
PCIE_VDDC
OFF
OFF
2A
190mA
70mA
2.8A
12.9A
VDDC/VDDCI(1.12V)
VDD_CT(1.8V)
iGPU
PERSTb
REFCLK
B B
Straps Reset
Straps Valid
PE_GPIO0 PE_EN
dGPU
BIF_VDDC
PE_GPIO1
+3.3VALW
+1.0V
MOS
Regulator
+3.3VSG
1
+1.0VSG
2
PX_mode
+1.5V
BACO Switch
SI4800
+1.5VSG
3
Global ASIC Reset
+B
+1.8V
T4+16clock
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.
2010/08/20 2011/08/20
2010/08/20 2011/08/20
2010/08/20 2011/08/20
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
SI4800
2
+1.8VSG
5
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
B
B
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
LA-7092P P5WE6/H6/S6
LA-7092P P5WE6/H6/S6
LA-7092P P5WE6/H6/S6
Regulator
dGPU Block Diagram
dGPU Block Diagram
dGPU Block Diagram
4
1
+VGA_CORE
PWRGOOD
4 46Friday, October 29, 2010
4 46Friday, October 29, 2010
4 46Friday, October 29, 2010
0.3
0.3
0.3
5
4
3
2
1
+1.8VS
APU_HDMI_TX2P<11>
APU_RST#<13>
APU_PWRGD<13>
APU_HDMI_TX2N<11>
APU_HDMI_TX1P<11>
APU_HDMI_TX1N<11>
APU_HDMI_TX0P<11>
APU_HDMI_TX0N<11>
APU_HDMI_CLKP<11>
APU_HDMI_CLKN<11>
APU_TXOUT2+<10>
APU_TXOUT2-<10>
APU_TXOUT1+<10>
APU_TXOUT1-<10>
APU_TXOUT0+<10>
APU_TXOUT0-<10>
APU_TXCLK+<10>
APU_TXCLK-<10>
T93PADT93PAD
T94PADT94PAD
Close to APU
APU_SIC
APU_SID
APU_PROCHOT#
APU_THERMTRIP#
APU_ALERT#_R
APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#
T77PADT77PAD
APU : SA00004DO60 (S IC ZACATE 2M151 132B1240 1.5G BGA)
APU : SA000046G80 (S IC ZACATE 2M161232B2240 1.6G BGA )
U22
16G@U22
16G@
Zacate FT1 B0
Zacate FT1 B0
R399 1K_0402_5%R399 1K_0402_5%
1 2
R400 1K_0402_5%R400 1K_0402_5%
D D
C C
B B
1 2
R142 300_0402_5%
R142 300_0402_5%
R401 300_0402_5%R401 300_0402_5%
R402 510_0402_1%R402 510_0402_1%
R141 1K_0402_5%R141 1K_0402_5%
+3VS
R410 1K_0402_5%R410 1K_0402_5%
R109 4.7K_0402_5%UMA@R109 4.7K_0402_5%UMA@
R155 4.7K_0402_5%UMA@R155 4.7K_0402_5%UMA@
R411 1K_0402_5%R411 1K_0402_5%
R143 1K_0402_5%R143 1K_0402_5%
R414 1K_0402_5%R414 1K_0402_5%
APU_THERMTRIP#
If FCH internal pull-up disable d, level-shifte r could be dele ted.
Need BIOS to dis able internal p ull-up!!
12
12
1 2
1 2
C237 0.01U_0402_25V7K
C237 0.01U_0402_25V7K
@
@
1 2
C238 0.01U_0402_25V7K
C238 0.01U_0402_25V7K
@
@
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R425
R425
1K_0402_5%
1K_0402_5%
APU_SVC
APU_SVD
APU_RST#
APU_PWRGD
TEST_25_L
TEST36
APU_RST#
APU_PWRGD
APU_PROCHOT#
APU_CRT_DDC_SCL
APU_CRT_DDC_SDA
APU_ALERT#_R
APU_SIC
APU_SID
+3VS
12
R424
R424
10K_0402_5%
10K_0402_5%
B
B
2
1 2
Q79
Q79
E
E
3 1
C
C
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
1 2
R427 0_0402_5%@R427 0_0402_5%@
For DVT 1011
EC_THERM#<31>
FCH_PROCHOT#<13>
H_THERMTRIP# <1 4>
APU_CLKP<13>
APU_CLKN<13>
APU_DISP_CLKP<13>
APU_DISP_CLKN<13>
APU_SVC<44>
APU_SVD<44>
R169 0_0402_5%R169 0_0402_5%
1 2
R168 0_0402_5%@R168 0_0402_5%@
1 2
APU_VDDNB_RUN_FB _H<44>
APU_VDD0_RUN_FB_H<44>
APU_VDD0_RUN_FB_L<44>
CPU TSI interface level shift
@
@
C236 0.1U_0402_10V7K
C236 0.1U_0402_10V7K
@
@
R428
R428
1 2
+3VS
31.6K_0402_1%
31.6K_0402_1%
A A
1 2
@
@
R160
R160
1 2
30K_0402_1%
30K_0402_1%
G
G
2
13
D
S
D
S
@
@
Q22
Q22
BSH111 1N_SOT23-3
BSH111 1N_SOT23-3
1 2
R431 0_0402_5%R431 0_0402_5%
G
G
2
13
D
S
D
S
@
@
Q23
Q23
BSH111 1N_SOT23-3
BSH111 1N_SOT23-3
1 2
R434 0_0402_5%R434 0_0402_5%
5
EC_SMB_DAAPU_SID
EC_SMB_CKAPU_SIC
BSH111, the Vgs is:
min = 0.4V
Typ = 1.0V
Max = 1.3V
1.607V for Gate
@
@
1 2
R429 0_0402_5%
R429 0_0402_5%
1 2
R430 0_0402_5%R430 0_0402_5%
@
@
1 2
R432 0_0402_5%
R432 0_0402_5%
1 2
R433 0_0402_5%R433 0_0402_5%
FDV301N, the Vgs is:
min = 0.65V
Typ = 0.85V
Max = 1.5V
If use level shi ft, EC_SMB need pull up
(pop R747 & R74 8)
FCH_SID
EC_SMB_DA2
FCH_SIC
EC_SMB_CK2
FCH_SID <14>
EC_SMB_DA2 <19,31>
FCH_SIC <14>
EC_SMB_CK2 <19,31>
4
T0 FCH
TO EC
T0 FCH
TO EC
U22B
U22B
A8
TDP1_TXP0
B8
TDP1_TXN0
B9
TDP1_TXP1
A9
TDP1_TXN1
D10
TDP1_TXP2
C10
TDP1_TXN2
A10
TDP1_TXP3
B10
TDP1_TXN3
B5
LTDP0_TXP0
A5
LTDP0_TXN0
D6
LTDP0_TXP1
C6
LTDP0_TXN1
A6
LTDP0_TXP2
B6
LTDP0_TXN2
D8
LTDP0_TXP3
C8
LTDP0_TXN3
V2
CLKIN_H
V1
CLKIN_L
D2
DISP_CLKIN_H
D1
DISP_CLKIN_L
J1
SVC
J2
SVD
P3
SIC
P4
SID
T3
RESET_L
T4
PWROK
U1
PROCHOT_L
U2
THERMTRIP_L
T2
ALERT_L
N2
TDI
N1
TDO
P1
TCK
P2
TMS
M4
TRST_L
M3
DBRDY
M1
DBREQ_L
F4
VDDCR_NB_SENSE
G1
VDDCR_CPU_SENSE
F3
VDDIO_MEM_S_SENSE
F1
VSS_SENSE
B4
RSVD_1
W11
RSVD_2
V5
RSVD_3
ONTARIO-2M161000-1.6G_BGA413
ONTARIO-2M161000-1.6G_BGA413
15G@
15G@
DP_ZVSS
DP_BLON
DP_DIGON
DP_VARY_BL
DP MISC
DP MISC
TDP1_AUXP
VGA DAC
VGA DAC
TEST
TEST
TDP1_AUXN
TDP1_HPD
LTDP0_AUXP
LTDP0_AUXN
LTDP0_HPD
DAC_RED
DAC_REDB
DAC_GREEN
DAC_GREENB
DAC_BLUE
DAC_BLUEB
DAC_HSYNC
DAC_VSYNC
DAC_SCL
DAC_SDA
DAC_ZVSS
TEST4
TEST5
TEST6
TEST14
TEST15
TEST16
TEST17
TEST18
TEST19
TEST25_H
TEST25_L
TEST28_H
TEST28_L
TEST31
TEST33_H
TEST33_L
TEST34_H
TEST34_L
TEST35
TEST36
TEST37
TEST38
DMAACTIVE_L
DISPLAYPORT 1
DISPLAYPORT 1
DISPLAYPORT 0
DISPLAYPORT 0
CLK
CLK
SER
SER
JTAG CTRL
JTAG CTRL
R398 150_0402_1%R398 150_0402_1%
H3
1 2
G2
H2
H1
APU_HDMI_CLK
B2
APU_HDMI_DATA
C2
C1
APU_LCD_CLK
A3
APU_LCD_DATA
B3
R406 100K_0402_5%R406 100K_0402_5%
D3
1 2
C12
R407 150_0402_1%R407 150_0402_1%
D13
A12
B12
A13
B13
E1
E2
F2
D4
D12
R1
R2
R6
T5
E4
K4
L1
L2
M2
K1
K2
L5
M5
M21
J18
J19
U15
T15
H4
N5
R5
K3
T1
1 2
R408 150_0402_1%R408 150_0402_1%
1 2
R409 150_0402_1%R409 150_0402_1%
1 2
R144 499_0402_1%R144 499_0402_1%
1 2
T66
T66
PAD
PAD
T67
T67
PAD
PAD
T68
T68
PAD
PAD
TEST15
TEST18
TEST19
TEST25_H
TEST_25_L
TEST31
TEST33_H
TEST33_L
Delete Test point for layout limitation
20100917
TEST35
TEST36
TEST37
R423 1K_0402_5%R423 1K_0402_5%
R415 1K_0402_5%@R415 1K_0402_5%@
R416 1K_0402_5%R416 1K_0402_5%
R417 1K_0402_5%R417 1K_0402_5%
R418 510_0402_1%R418 510_0402_1%
T73
T73
PAD
PAD
C516 0.1U_0402_16V4ZC516 0.1U_0402_16V4Z
1 2
C517 0.1U_0402_16V4ZC517 0.1U_0402_16V4Z
1 2
R422 1K_0402_5%@R422 1K_0402_5%@
R958 1K_0402_5%R958 1K_0402_5%
T76
T76
PAD
PAD
1 2
1 2
1 2
1 2
1 2
1 2
1 2
AMD Debug
+1.8VS +1.8VS
R842
R842
1K_0402_5%
1K_0402_5%
1 2
APU_TRST#
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/08/20 2011/08/20
2010/08/20 2011/08/20
2010/08/20 2011/08/20
0_0402_5%
0_0402_5%
R846
R846
R847 10K_0402_5%R847 10K_0402_5%
R176 10K_0402_5%R176 10K_0402_5%
R177 10K_0402_5%R177 10K_0402_5%
APU_TRST#_R
1 2
12
12
12
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
JHDT1
JHDT1
1
1
2
3
3
4
5
5
6
7
7
8
9
9
10
11
11
12
13
13
14
15
15
16
17
17
18
19
19
20
SAMTE_ASP-136446-07-B
SAMTE_ASP-136446-07-B
CONN@
CONN@
2
APU_ENBKL <10>
APU_ENVDD <10>
APU_BLPWM <10>
APU_HDMI_CLK <11>
APU_HDMI_DATA <11>
APU_HDMI_HPD <11>
APU_LCD_CLK <10>
APU_LCD_DATA <10>
APU_CRT_R <12>
APU_CRT_G <12>
APU_CRT_B <12>
APU_CRT_HSYNC <12>
APU_CRT_VSYNC <12>
APU_CRT_DDC_SCL <12>
APU_CRT_DDC_SDA <12>
ALLOW_STOP# <13>
+1.8VS
APU_TCK
2
APU_TMS
4
APU_TDI
6
APU_TDO
8
APU_PWRGD
10
APU_RST#
12
APU_DBRDY
14
APU_DBREQ#
16
J108_PLLTST0
18
J108_PLLTST1
20
R420 51_0402_1%R420 51_0402_1%
1 2
R421 51_0402_1%R421 51_0402_1%
1 2
+1.8VS
R843 1K_0402_5%R843 1K_0402_5%
R840 1K_0402_5%R840 1K_0402_5%
R798 1K_0402_5%R798 1K_0402_5%
R178 300_0402_5%R178 300_0402_5%
R799 0_0402_5%R799 0_0402_5%
R863 0_0402_5%R863 0_0402_5%
1 2
1 2
1 2
12
12
12
+1.8VS
TEST19
TEST18
Please be noted about TEST_18 and TEST_19
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
FT1 CTRL/DP/CRT
FT1 CTRL/DP/CRT
FT1 CTRL/DP/CRT
LA-7092P P5WE6/H6/S6
LA-7092P P5WE6/H6/S6
LA-7092P P5WE6/H6/S6
5 46Friday, October 29, 2010
5 46Friday, October 29, 2010
5 46Friday, October 29, 2010
1
0.3
0.3
0.3
A
U22E
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
4 4
3 3
2 2
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDR_A_BS0<8,9>
DDR_A_BS1<8,9>
DDR_A_BS2<8,9>
DDR_A_DQS0<8,9>
DDR_A_DQS#0<8,9>
DDR_A_DQS1<8,9>
DDR_A_DQS#1<8,9>
DDR_A_DQS2<8,9>
DDR_A_DQS#2<8,9>
DDR_A_DQS3<8,9>
DDR_A_DQS#3<8,9>
DDR_A_DQS4<8,9>
DDR_A_DQS#4<8,9>
DDR_A_DQS5<8,9>
DDR_A_DQS#5<8,9>
DDR_A_DQS6<8,9>
DDR_A_DQS#6<8,9>
DDR_A_DQS7<8,9>
DDR_A_DQS#7<8,9>
DDR_A_CLK0<8>
DDR_A_CLK#0<8>
DDR_A_CLK1<8>
DDR_A_CLK#1<8>
DDR_B_CLK2<9>
DDR_B_CLK#2<9>
DDR_B_CLK3<9>
DDR_B_CLK#3<9>
DDR_RST#<8,9>
DDR_EVENT#<8,9>
DDR_CKE0<8,9>
DDR_CKE1<8,9>
DDR_A_ODT0< 8>
DDR_A_ODT1< 8>
DDR_B_ODT0< 9>
DDR_B_ODT1< 9>
DDR_CS0_DIMMA#<8>
DDR_CS1_DIMMA#<8>
DDR_CS0_DIMMB#<9>
DDR_CS1_DIMMB#<9>
DDR_A_RAS#<8,9>
DDR_A_CAS#<8,9>
DDR_A_WE#<8,9>
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1
DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK3
DDR_B_CLK#3
DDR_RST#
DDR_EVENT#
DDR_CKE0
DDR_CKE1
DDR_A_ODT0
DDR_A_ODT1
DDR_B_ODT0
DDR_B_ODT1
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMB#
DDR_CS1_DIMMB#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
U22E
R17
M_ADD0
H19
M_ADD1
J17
M_ADD2
H18
M_ADD3
H17
M_ADD4
G17
M_ADD5
H15
M_ADD6
G18
M_ADD7
F19
M_ADD8
E19
M_ADD9
T19
M_ADD10
F17
M_ADD11
E18
M_ADD12
W17
M_ADD13
E16
M_ADD14
G15
M_ADD15
R18
M_BANK0
T18
M_BANK1
F16
M_BANK2
D15
M_DM0
B19
M_DM1
D21
M_DM2
H22
M_DM3
P23
M_DM4
V23
M_DM5
AB20
M_DM6
AA16
M_DM7
A16
M_DQS_H0
B16
M_DQS_L0
B20
M_DQS_H1
A20
M_DQS_L1
E23
M_DQS_H2
E22
M_DQS_L2
J22
M_DQS_H3
J23
M_DQS_L3
R22
M_DQS_H4
P22
M_DQS_L4
W22
M_DQS_H5
V22
M_DQS_L5
AC20
M_DQS_H6
AC21
M_DQS_L6
AB16
M_DQS_H7
AC16
M_DQS_L7
M17
M_CLK_H0
M16
M_CLK_L0
M19
M_CLK_H1
M18
M_CLK_L1
N18
M_CLK_H2
N19
M_CLK_L2
L18
M_CLK_H3
L17
M_CLK_L3
L23
M_RESET_L
N17
M_EVENT_L
F15
M_CKE0
E15
M_CKE1
W19
M0_ODT0
V15
M0_ODT1
U19
M1_ODT0
W15
M1_ODT1
T17
M0_CS_L0
W16
M0_CS_L1
U17
M1_CS_L0
V16
M1_CS_L1
U18
M_RAS_L
V19
M_CAS_L
V17
M_WE_L
ONTARIO-2M161000-1.6 G_BGA413
ONTARIO-2M161000-1.6 G_BGA413
15G@
15G@
DDR SYSTEM MEMORY
DDR SYSTEM MEMORY
B
M_DATA0
M_DATA1
M_DATA2
M_DATA3
M_DATA4
M_DATA5
M_DATA6
M_DATA7
M_DATA8
M_DATA9
M_DATA10
M_DATA11
M_DATA12
M_DATA13
M_DATA14
M_DATA15
M_DATA16
M_DATA17
M_DATA18
M_DATA19
M_DATA20
M_DATA21
M_DATA22
M_DATA23
M_DATA24
M_DATA25
M_DATA26
M_DATA27
M_DATA28
M_DATA29
M_DATA30
M_DATA31
M_DATA32
M_DATA33
M_DATA34
M_DATA35
M_DATA36
M_DATA37
M_DATA38
M_DATA39
M_DATA40
M_DATA41
M_DATA42
M_DATA43
M_DATA44
M_DATA45
M_DATA46
M_DATA47
M_DATA48
M_DATA49
M_DATA50
M_DATA51
M_DATA52
M_DATA53
M_DATA54
M_DATA55
M_DATA56
M_DATA57
M_DATA58
M_DATA59
M_DATA60
M_DATA61
M_DATA62
M_DATA63
M_VREF
M_ZVDDIO_MEM_S
B14
A15
A17
D18
A14
C14
C16
D16
C18
A19
B21
D20
A18
B18
A21
C20
C23
D23
F23
F22
C22
D22
F20
F21
H21
H23
K22
K21
G23
H20
K20
K23
N23
P21
T20
T23
M20
P20
R23
T22
V20
V21
Y23
Y22
T21
U23
W23
Y21
Y20
AB22
AC19
AA18
AA23
AA20
AB19
Y18
AC17
Y16
AB14
AC14
AC18
AB18
AB15
AC15
M23
M22
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
+MEM_VREF
R437
R437
39.2_0402_1%
39.2_0402_1%
15 mils
12
C
DDR_A_D[0..63]
DDR_A_MA[0..15]
DDR_A_DM[0..7]
PCIE_GTX_C_FRX_P0<18>
PCIE_GTX_C_FRX_N0<18>
PCIE_GTX_C_FRX_P1<18>
PCIE_GTX_C_FRX_N1<18>
PCIE_GTX_C_FRX_P2<18>
PCIE_GTX_C_FRX_N2<18>
PCIE_GTX_C_FRX_P3<18>
PCIE_GTX_C_FRX_N3<18>
+1.5V
+1.05VS
UMI_RX0P<13>
UMI_RX0N<1 3>
UMI_RX1P<13>
UMI_RX1N<1 3>
UMI_RX2P<13>
UMI_RX2N<1 3>
UMI_RX3P<13>
UMI_RX3N<1 3>
R435 2K_0402_1%R435 2K_0402_1%
Less than 1"
1 2
DDR_A_D[0..63] <8,9>
DDR_A_MA[0..15] <8,9>
DDR_A_DM[0..7] <8,9>
PCIE_GTX_C_FRX_P0
PCIE_GTX_C_FRX_N0
PCIE_GTX_C_FRX_P1
PCIE_GTX_C_FRX_N1
PCIE_GTX_C_FRX_P2
PCIE_GTX_C_FRX_N2
PCIE_GTX_C_FRX_P3
PCIE_GTX_C_FRX_N3
P_ZVDD_10
U22A
U22A
AA6
P_GPP_RXP0
Y6
P_GPP_RXN0
AB4
P_GPP_RXP1
AC4
P_GPP_RXN1
AA1
P_GPP_RXP2
AA2
P_GPP_RXN2
Y4
P_GPP_RXP3
Y3
P_GPP_RXN3
Y14
P_ZVDD_10
AA12
P_UMI_RXP0
Y12
P_UMI_RXN0
AA10
P_UMI_RXP1
Y10
P_UMI_RXN1
AB10
P_UMI_RXP2
AC10
P_UMI_RXN2
AC7
P_UMI_RXP3
AB7
P_UMI_RXN3
ONTARIO-2M161000-1.6 G_BGA413
ONTARIO-2M161000-1.6 G_BGA413
15G@
15G@
PCIE I/F
PCIE I/F
UMI I/F
UMI I/F
P_GPP_TXP0
P_GPP_TXN0
P_GPP_TXP1
P_GPP_TXN1
P_GPP_TXP2
P_GPP_TXN2
P_GPP_TXP3
P_GPP_TXN3
P_ZVSS
P_UMI_TXP0
P_UMI_TXN0
P_UMI_TXP1
P_UMI_TXN1
P_UMI_TXP2
P_UMI_TXN2
P_UMI_TXP3
P_UMI_TXN3
D
PCIE_FTX_GRX_P0
AB6
PCIE_FTX_GRX_N0
AC6
PCIE_FTX_GRX_P1
AB3
PCIE_FTX_GRX_N1
AC3
PCIE_FTX_GRX_P2
Y1
PCIE_FTX_GRX_N2
Y2
PCIE_FTX_GRX_P3
V3
PCIE_FTX_GRX_N3
V4
P_ZVSS
AA14
AB12
AC12
AC11
AB11
AA8
Y8
AB8
AC8
C518 0.1U_0402_16V7KVGA@C518 0.1U_0402_16V7KVGA@
C519 0.1U_0402_16V7KVGA@C519 0.1U_0402_16V7KVGA@
C520 0.1U_0402_16V7KVGA@C520 0.1U_0402_16V7KVGA@
C521 0.1U_0402_16V7KVGA@C521 0.1U_0402_16V7KVGA@
C522 0.1U_0402_16V7KVGA@C522 0.1U_0402_16V7KVGA@
C523 0.1U_0402_16V7KVGA@C523 0.1U_0402_16V7KVGA@
C524 0.1U_0402_16V7KVGA@C524 0.1U_0402_16V7KVGA@
C525 0.1U_0402_16V7KVGA@C525 0.1U_0402_16V7KVGA@
R436 1.27K_0402_1%R436 1.27K_0402_1%
1 2
Less than 1"
UMI_TX0P_C
UMI_TX0N_C
UMI_TX1P_C
UMI_TX1N_C
UMI_TX2P_C
UMI_TX2N_C
UMI_TX3P_C
UMI_TX3N_C
C526 0.1U_0402_16V7KC526 0.1U_0402_16V7K
C527 0.1U_0402_16V7KC527 0.1U_0402_16V7K
C528 0.1U_0402_16V7KC528 0.1U_0402_16V7K
C529 0.1U_0402_16V7KC529 0.1U_0402_16V7K
C530 0.1U_0402_16V7KC530 0.1U_0402_16V7K
C531 0.1U_0402_16V7KC531 0.1U_0402_16V7K
C532 0.1U_0402_16V7KC532 0.1U_0402_16V7K
C533 0.1U_0402_16V7KC533 0.1U_0402_16V7K
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
E
PCIE_FTX_C_GRX_P0 <18>
PCIE_FTX_C_GRX_N0 <1 8>
PCIE_FTX_C_GRX_P1 <18>
PCIE_FTX_C_GRX_N1 <1 8>
PCIE_FTX_C_GRX_P2 <18>
PCIE_FTX_C_GRX_N2 <1 8>
PCIE_FTX_C_GRX_P3 <18>
PCIE_FTX_C_GRX_N3 <1 8>
UMI_TX0P <13>
UMI_TX0N < 13>
UMI_TX1P <13>
UMI_TX1N < 13>
UMI_TX2P <13>
UMI_TX2N < 13>
UMI_TX3P <13>
UMI_TX3N < 13>
+1.5V
+1.5V
R149
R149
1 2
1K_0402_5%
1K_0402_5%
1 1
DDR_EVENT#
A
R438
R438
1K_0402_1%
1K_0402_1%
R439
R439
1K_0402_1%
1K_0402_1%
1 2
1
C534
C534
1000P_0402_50V7K
1000P_0402_50V7K
2
1 2
Place within 1000 mils to APU
20100526
B
C535
C535
+MEM_VREF
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010/08/20 2011/08/20
2010/08/20 2011/08/20
2010/08/20 2011/08/20
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
FT1 DDRIII/UMI/PCIE
FT1 DDRIII/UMI/PCIE
FT1 DDRIII/UMI/PCIE
LA-7092P P5WE6/H6/S6
LA-7092P P5WE6/H6/S6
LA-7092P P5WE6/H6/S6
E
6 46Friday, October 29, 2010
6 46Friday, October 29, 2010
6 46Friday, October 29, 2010
0.3
0.3
0.3
5
4
3
2
1
+APU_CORE
U22C
U22C
1
C539
C539
D D
10U_0603_6.3V6M
10U_0603_6.3V6M
2
1
C550
C550
1U_0402_6.3V6K
1U_0402_6.3V6K
2
1
C559
C559
0.1U_0402_16V7K
0.1U_0402_16V7K
2
+APU_CORE_NB
C C
C575
C575
10U_0603_6.3V6M
10U_0603_6.3V6M
C582
C582
1U_0402_6.3V6K
1U_0402_6.3V6K
C591
C591
0.1U_0402_16V7K
0.1U_0402_16V7K
B B
1
2
1
2
1
2
1
C536
C536
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C551
C551
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C560
C560
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C576
C576
10U_0603_6.3V6M
10U_0603_6.3V6M
2
1
C583
C583
1U_0402_6.3V6K
1U_0402_6.3V6K
2
1
C592
C592
0.1U_0402_16V7K
0.1U_0402_16V7K
2
POWER
1
C620
C620
@
@
10U_0603_6.3V6M
10U_0603_6.3V6M
2
+APU_CORE
1
1
330U_D2E_2.5VM_R9M
330U_D2E_2.5VM_R9M
+
+
+
C605
C605
@
@
330U_D2E_2.5VM_R9M
330U_D2E_2.5VM_R9M
+APU_CORE_NB
A A
C617
C617
390U_2.5V_10M
390U_2.5V_10M
+
C606
C606
2
2
1
+
+
2
C541
C541
10U_0603_6.3V6M
10U_0603_6.3V6M
C552
C552
1U_0402_6.3V6K
1U_0402_6.3V6K
C561
C561
0.1U_0402_16V7K
0.1U_0402_16V7K
C577
C577
10U_0603_6.3V6M
10U_0603_6.3V6M
C584
C584
1U_0402_6.3V6K
1U_0402_6.3V6K
C593
C593
0.1U_0402_16V7K
0.1U_0402_16V7K
+1.05VS
1
+
+
C621
C621
@
@
390U_2.5V_10M
390U_2.5V_10M
2
1
+
+
C607
C607
@
@
330U_D2E_2.5VM_R9M
330U_D2E_2.5VM_R9M
2
1
+
+
C618
C618
330U_D2_2.5VY_R9M
330U_D2_2.5VY_R9M
2
1
2
1
2
1
2
1
2
1
2
1
2
1
C542
C542
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C553
C553
1U_0402_6.3V6K
1U_0402_6.3V6K
2
1
C562
C562
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C578
C578
10U_0603_6.3V6M
10U_0603_6.3V6M
2
1
C585
C585
1U_0402_6.3V6K
1U_0402_6.3V6K
2
1
C594
C594
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
390U_2.5V_10M
390U_2.5V_10M
+
+
C1104
C1104
2
Near CPU Socket
1
C619
C619
10U_0603_6.3V6M
10U_0603_6.3V6M
2
C543
C543
10U_0603_6.3V6M
10U_0603_6.3V6M
C563
C563
C579
C579
C586
C586
1U_0402_6.3V6K
1U_0402_6.3V6K
1
+
+
C1105
C1105
390U_2.5V_10M
390U_2.5V_10M
2
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
180P_0402_50V8J
180P_0402_50V8J
1
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
10U_0603_6.3V6M
10U_0603_6.3V6M
2
1
2
POWER
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C616
C616
@
@
2
1
C544
C544
2
1
C554
C554
2
1
C587
C587
180P_0402_50V8J
180P_0402_50V8J
2
1
C540
C540
10U_0603_6.3V6M
10U_0603_6.3V6M
2
1
C555
C555
180P_0402_50V8J
180P_0402_50V8J
2
1
C588
C588
180P_0402_50V8J
180P_0402_50V8J
2
+1.5V +1.8VS
1
C622
C622
390U_2.5V_10M
390U_2.5V_10M
2
+APU_CORE
+APU_CORE_NB
+1.5V
change 0603 for DVT
1
C623
C623
+
+
10U_0603_6.3V6M
10U_0603_6.3V6M
2
Near CPU Socket Near CPU Socket
11A
E5
VDDCR_CPU_1
E6
VDDCR_CPU_2
F5
VDDCR_CPU_3
F7
VDDCR_CPU_4
G6
VDDCR_CPU_5
G8
VDDCR_CPU_6
H5
VDDCR_CPU_7
H7
VDDCR_CPU_8
J6
VDDCR_CPU_9
J8
VDDCR_CPU_10
L7
VDDCR_CPU_11
M6
VDDCR_CPU_12
M8
VDDCR_CPU_13
N7
VDDCR_CPU_14
R8
VDDCR_CPU_15
A
10
E8
VDDCR_NB_1
E11
VDDCR_NB_2
E13
VDDCR_NB_3
F9
VDDCR_NB_4
F12
VDDCR_NB_5
G11
VDDCR_NB_6
G13
VDDCR_NB_7
H9
VDDCR_NB_8
H12
VDDCR_NB_9
K11
VDDCR_NB_10
K13
VDDCR_NB_11
L10
VDDCR_NB_12
L12
VDDCR_NB_13
L14
VDDCR_NB_14
M11
VDDCR_NB_15
M12
VDDCR_NB_16
M13
VDDCR_NB_17
N10
VDDCR_NB_18
N12
VDDCR_NB_19
N14
VDDCR_NB_20
P11
VDDCR_NB_21
P13
VDDCR_NB_22
2A
G16
VDDIO_MEM_S_1
G19
VDDIO_MEM_S_2
E17
VDDIO_MEM_S_3
J16
VDDIO_MEM_S_4
L16
VDDIO_MEM_S_5
L19
VDDIO_MEM_S_6
N16
VDDIO_MEM_S_7
R16
VDDIO_MEM_S_8
R19
VDDIO_MEM_S_9
W18
VDDIO_MEM_S_10
U16
VDDIO_MEM_S_11
ONTARIO-2M161000-1.6G_BGA413
ONTARIO-2M161000-1.6G_BGA413
15G@
15G@
+1.5V
C589
C589
10U_0603_6.3V6M
10U_0603_6.3V6M
C595
C595
1U_0402_6.3V6K
1U_0402_6.3V6K
C599
C599
0.1U_0402_16V7K
0.1U_0402_16V7K
+1.5V
2
1
1
2
1
2
1
2
C101
C101
0.1U_0402_16V7K
0.1U_0402_16V7K
1
C590
C590
10U_0603_6.3V6M
10U_0603_6.3V6M
2
1
C596
C596
1U_0402_6.3V6K
1U_0402_6.3V6K
2
1
C600
C600
0.1U_0402_16V7K
0.1U_0402_16V7K
2
180PF Qt'y follow the distance between
CPU socket and DIMM0. <2.5inch>
2
1
C102
C102
0.1U_0402_16V7K
0.1U_0402_16V7K
GPU AND NB CORE
GPU AND NB CORE
DDR3
DDR3
1
C597
C597
1U_0402_6.3V6K
1U_0402_6.3V6K
2
1
C601
C601
0.1U_0402_16V7K
0.1U_0402_16V7K
2
TSense/PLL/DP/PCIE/IO
TSense/PLL/DP/PCIE/IO
VDD_18_1
VDD_18_2
VDD_18_3
VDD_18_4
VDD_18_5
VDD_18_6
CPU CORE
CPU CORE
VDD_18_7
DAC
DAC
VDD_18_DAC
POWER
POWER
DIS PLL
DIS PLL
VDDPL_10
PCIE/IO/DDR3 Phy
PCIE/IO/DDR3 Phy
VDD_10_1
VDD_10_2
VDD_10_3
VDD_10_4
DP Phy/IO
DP Phy/IO
180P_0402_50V8J
180P_0402_50V8J
1
C103
C103
180P_0402_50V8J
180P_0402_50V8J
2
POWER POWER
1
1
C685
C685
2
10U_0603_6.3V6M
10U_0603_6.3V6M
C624
C624
390U_2.5V_10M
390U_2.5V_10M
Near CPU Socket
+
+
2
1
C625
C625
@
@
10U_0603_6.3V6M
10U_0603_6.3V6M
2
(390uF_2.5V_6.3x5.7_ESR10m)*1=(SF000002O00)
5
4
U8
W8
U6
U9
W6
T7
V7
W9
U11
U13
W13
V12
T12
A4
VDD_33
1
C598
C598
1U_0402_6.3V6K
1U_0402_6.3V6K
2
1
C602
C602
2
2A
0.15A
0.2A
5.5A
0.5A
+VDD_18
C545
C545
+VDD_18_DAC
C556
C556
+VDDL_10
C564
C564
+VDD_10
C568
C568
C580
C580
1
1
1
C546
C546
C537
C537
2
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
180P_0402_50V8J
180P_0402_50V8J
add Cap. for CRT DVT
1
1
2
1
2
1
2
1
2
1
C557
C557
C558
C558
2
2
180P_0402_50V8J
180P_0402_50V8J
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
C566
C566
C565
C565
2
2
180P_0402_50V8J
180P_0402_50V8J
0.1U_0402_16V7K
0.1U_0402_16V7K
1
1
C570
C570
C569
C569
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
180P_0402_50V8J
180P_0402_50V8J
+3VS
1
C581
C581
2
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
1
1
C538
C538
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C604
C604
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C567
C567
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C571
C571
2
0.1U_0402_16V7K
0.1U_0402_16V7K
Power Cap. Summary
APU
S POLY C 330U 2.5V M D2E TPE LESR9M H1.8 --->+APU_CORE(Qty : 3) Unpop:2
S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU --->+APU_CORE(Qty : 2)
S POLY C 330U 2.5V Y D2 LESR9M EEFS H1.9 --->+APU_CORE_NB(Qty : 1)
S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU--->+APU_CORE_NB(Qty : 1)
1
C547
C547
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
@
@
C684
C684
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C572
C572
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C548
C548
C549
C549
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
L30
L30
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
Change from SM010014520 to SD002000080
20100816
10U_0603_6.3V6M
10U_0603_6.3V6M
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
1
1
C574
C574
C573
C573
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
L31
L31
10U_0603_6.3V6M
10U_0603_6.3V6M
S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU --->+1.5V(Qty : 1)
S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU --->1.05VS(Qty : 1)
S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU --->+1.8VS(Qty : 1)
DDR3 Socket
S POLY C 330U 2V M X LESR6M SX H1.9 --->1.5V(Qty : 1)
FCH
S POLY C 330U 2.5V Y D2 LESR9M EEFS H1.9 --->1.1VS(Qty : 1) UMA unpop
1
C603
C603
180P_0402_50V8J
180P_0402_50V8J
2
GPU
S POLY C 330U 2V M X LESR6M SX H1.9 --->VGA_CORE(Qty : 2) Unpop:1
S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU --->+VGA_CORE(Qty : 1)
S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU --->+1.5VSG(Qty : 1)
USB
1
C104
C104
180P_0402_50V8J
180P_0402_50V8J
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
3
S_A-P_CAP 220U 6.3V M C45 R17M SVPE H4.4 --->+USB_VCCA(Qty : 1)
Compal Secret Data
Compal Secret Data
2010/08/20 2011/08/20
2010/08/20 2011/08/20
2010/08/20 2011/08/20
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
+1.8VS
L29
L29
12
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
Change from SM010014520 to SD002000080
20100816
+1.8VS
12
+1.05VS
12
L32
L32
12
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
Change from SM010014520 to SD002000080
20100816
By case (Along split)
+1.5V
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
2
U22D
U22D
A7
VSS_1
B7
VSS_2
B11
VSS_3
B17
VSS_4
B22
VSS_5
C4
VSS_6
D5
VSS_7
D7
VSS_8
D9
VSS_9
D11
VSS_10
D14
VSS_11
B15
VSS_12
D17
VSS_13
D19
VSS_14
E7
VSS_15
E9
VSS_16
E12
VSS_17
E20
VSS_18
F8
VSS_19
F11
VSS_20
F13
VSS_21
G4
VSS_22
G5
VSS_23
G7
VSS_24
G9
VSS_25
G12
VSS_26
G20
VSS_27
G22
VSS_28
H6
VSS_29
H11
VSS_30
H13
VSS_31
J4
VSS_32
J5
VSS_33
J7
VSS_34
J20
VSS_35
K10
VSS_36
K14
VSS_37
L4
VSS_38
L6
VSS_39
L8
VSS_40
L11
VSS_41
L13
VSS_42
L20
VSS_43
L22
VSS_44
M7
VSS_45
N4
VSS_46
N6
VSS_47
N8
VSS_48
N11
VSS_49
ONTARIO-2M161000-1.6G_BGA413
ONTARIO-2M161000-1.6G_BGA413
15G@
15G@
1
C608
C608
1
C609
C609
C610
C610
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
GND
GND
1
C611
C611
2
0.1U_0402_16V7K
0.1U_0402_16V7K
Compal Electronics, Inc.
P07-FT1 PWR/VSS
P07-FT1 PWR/VSS
P07-FT1 PWR/VSS
LA-7092P P5WE6/H6/S6
LA-7092P P5WE6/H6/S6
LA-7092P P5WE6/H6/S6
180P_0402_50V8J
180P_0402_50V8J
1
2
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSSBG_DAC
C612
C612
180P_0402_50V8J
180P_0402_50V8J
1
N13
N20
N22
P10
P14
R4
R7
R20
T6
T9
T11
T13
U4
U5
U7
U12
U20
U22
V8
V9
V11
V13
W1
W2
W4
W5
W7
W12
W20
Y5
Y7
Y9
Y11
Y13
Y15
Y17
Y19
AA4
AA22
AB2
AB5
AB9
AB13
AB17
AB21
AC5
AC9
AC13
A11
+APU_CORE
+APU_CORE_NB
+1.5V
+1.05VS
+1.8VS
+1.5V
+1.1VS
+GPU_CORE
+1.5VSG
+USB_VCCA
1
1
C613
C613
2
2
180P_0402_50V8J
180P_0402_50V8J
1
C615
C615
C614
C614
2
180P_0402_50V8J
180P_0402_50V8J
0.3
0.3
7 46Monday, November 01, 2010
7 46Monday, November 01, 2010
7 46Monday, November 01, 2010
0.3
5
+1.5V
JDIMM1
+VREF_DQ
1
C626
C626
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
D D
DDR_A_DQS#1<6,9>
DDR_A_DQS1<6,9>
DDR_A_DQS#2<6,9>
DDR_A_DQS2<6,9>
C C
DDR_CS1_DIMMA#<6>
B B
A A
+3VS
DDR_A_DQS#4<6,9>
DDR_A_DQS4<6,9>
DDR_A_DQS#6<6,9>
DDR_A_DQS6<6,9>
C646
C646
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
1000P_0402_50V7K
1000P_0402_50V7K
DDR_CKE0<6,9>
DDR_A_BS2<6,9>
DDR_A_CLK0<6>
DDR_A_CLK#0<6>
DDR_A_BS0<6,9>
DDR_A_WE#<6,9>
DDR_A_CAS#<6,9>
1
2
5
1
C627
C627
2
1
C647
C647
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
DDR_A_D0
DDR_A_D1
DDR_A_DM0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_MA13
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
1 2
R150 10K_0402_5%R150 10K_0402_5%
12
R151
R151
10K_0402_5%
10K_0402_5%
JDIMM1
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
FOX_AS0A626-U8SN-7F
FOX_AS0A626-U8SN-7F
CONN@
CONN@
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
DQ14
DQ15
DQ20
DQ21
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
4
+1.5V
2
DDR_A_D4
4
DDR_A_D5
6
8
10
12
14
DDR_A_D6
16
DDR_A_D7
18
20
DDR_A_D12
22
DDR_A_D13
24
26
DDR_A_DM1
28
30
32
DDR_A_D14
34
DDR_A_D15
36
38
DDR_A_D20
40
DDR_A_D21
42
44
DDR_A_DM2
46
48
DDR_A_D22
50
DDR_A_D23
52
54
DDR_A_D28
56
DDR_A_D29
58
60
62
64
66
DDR_A_D30
68
DDR_A_D31
70
72
74
76
DDR_A_MA15
78
A15
A14
A11
A7
A6
A4
A2
A0
S0#
G2
DDR_A_MA14
80
82
DDR_A_MA11
84
DDR_A_MA7
86
88
DDR_A_MA6
90
DDR_A_MA4
92
94
DDR_A_MA2
96
DDR_A_MA0
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR3 SO-DIMM A H:8mm
Standard Type
P/N:SP07000HA00
F/P:FOX_AS0A626-U8SN-7F_204P
4
+0.75VS
DDR_A_DQS#0 <6,9>
DDR_A_DQS0 <6,9>
DDR_RST# <6,9>
DDR_A_DQS#3 <6,9>
DDR_A_DQS3 <6,9>
DDR_CKE1 <6,9>
DDR_A_CLK1 <6>
DDR_A_CLK#1 <6>
DDR_A_BS1 <6,9>
DDR_A_RAS# <6,9>
DDR_CS0_DIMMA# <6>
DDR_A_ODT0 <6>
DDR_A_ODT1 <6>
1
C645
C645
1000P_0402_50V7K
1000P_0402_50V7K
2
DDR_A_DQS#5 <6,9>
DDR_A_DQS5 <6,9>
DDR_A_DQS#7 <6,9>
DDR_A_DQS7 <6,9>
DDR_EVENT# <6,9>
FCH_SMDAT0 <9 ,14,29>
FCH_SMCLK0 <9,14,29>
1
C644
C644
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
3
DDR_A_D[0..63]
DDR_A_MA[0..15]
DDR_A_DM[0..7]
+1.5V
2
C628
C628
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C629
C629
1
DDR_A_D[0..63] <6,9>
DDR_A_MA[0..15] <6,9>
DDR_A_DM[0..7] <6,9>
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C630
C630
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C631
C631
1
2
2
C632
C632
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CRB 0.1u X1 4.7u X1
+0.75VS
+VREF_CA
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/08/20 2011/08/20
2010/08/20 2011/08/20
2010/08/20 2011/08/20
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
C640
C640
@
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
Place near JDIMM1
2
C641
C641
2
1
2
2
C633
C633
1
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C642
C642
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
2
EMI For DVT 10/20
+1.5V
1
+1.5V
R145
R145
1K_0402_1%
2
C635
C635
1
1K_0402_1%
1 2
R147
R147
1K_0402_1%
1K_0402_1%
1 2
2
C636
C636
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C637
C637
1
+VREF_CA
2
C638
C638
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
15mil 15mil
+VREF_DQ
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C634
C634
CRB 100U X2
+1.5V
1
+
+
C1102
C1102
330U_D2E_2.5VM_R9M
330U_D2E_2.5VM_R9M
2
330U ESR:9m H:2
P/
N:SGA20331E10
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C676
C676
1
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
C643
C643
C675
1
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
C675
1
Compal Electronics, Inc.
DDR3 SODIMM-I Socket
DDR3 SODIMM-I Socket
DDR3 SODIMM-I Socket
LA-7092P P5WE6/H6/S6
LA-7092P P5WE6/H6/S6
LA-7092P P5WE6/H6/S6
C678
C678
+1.5V
R146
R146
1K_0402_1%
1K_0402_1%
1 2
R148
R148
1K_0402_1%
1K_0402_1%
1 2
2
C110
C110
1
8 46Friday, October 29, 2010
8 46Friday, October 29, 2010
8 46Friday, October 29, 2010
0.3
0.3
0.3
5
4
3
2
1
+1.5V
JDIMM2
11
13
15
17
19
21
23
25
27
33
35
39
41
45
47
49
51
53
55
57
59
63
67
69
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
1 2
JDIMM2
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS129RESET#
VSS1131VSS12
DQ10
DQ11
VSS1337VSS14
DQ16
DQ17
VSS1543VSS16
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS2261DQS#3
DM3
VSS2365VSS24
DQ26
DQ27
VSS2571VSS26
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
G1
FOX_AS0A626-U4SN-7F
FOX_AS0A626-U4SN-7F
CONN@
CONN@
DQS#0
DQS0
DQ12
DQ13
VSS10
DQ14
DQ15
DQ20
DQ21
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
+VREF_DQ
1
C681
2
DDR_A_DQS#1<6,8>
DDR_A_DQS1<6,8>
DDR_A_DQS#2<6,8>
DDR_A_DQS2<6,8>
DDR_A_BS2<6,8>
DDR_B_CLK2<6>
DDR_B_CLK#2<6>
DDR_A_BS0<6,8>
DDR_A_WE#<6,8>
DDR_A_CAS#<6,8>
DDR_A_DQS#4<6,8>
DDR_A_DQS4<6,8>
DDR_A_DQS#6<6,8>
DDR_A_DQS6<6,8>
1 2
1 2
C681
1000P_0402_50V7K
1000P_0402_50V7K
DDR_CKE0<6,8>
C667
C667
1
2
C680
C680
0.1U_0402_16V4Z
D D
C C
B B
A A
0.1U_0402_16V4Z
DDR_CS1_DIMMB#<6>
For DRAM strap pin reservation
20100817
R961 10K_0402_5%R961 10K_0402_5%
+3VS
R153 10K_0402_5%@R153 10K_0402_5%@
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
CRB only one 4.7k
5
1
2
1
C668
C668
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
DDR_A_D0
DDR_A_D1
DDR_A_DM0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_MA13
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
@
@
1 2
R154
R154
10K_0402_5%
10K_0402_5%
R962
R962
10K_0402_5%
10K_0402_5%
For DRAM strap pin reservation
20100817
DQ4
DQ5
VSS3
VSS6
DQ6
DQ7
VSS8
DM1
DM2
CK1
CK1#
BA1
NC2
DM4
DM6
SDA
SCL
VTT2
+1.5V
2
DDR_A_D4
4
DDR_A_D5
6
8
10
12
14
DDR_A_D6
16
DDR_A_D7
18
20
DDR_A_D12
22
DDR_A_D13
24
26
DDR_A_DM1
28
30
32
DDR_A_D14
34
DDR_A_D15
36
38
DDR_A_D20
40
DDR_A_D21
42
44
DDR_A_DM2
46
48
DDR_A_D22
50
DDR_A_D23
52
54
DDR_A_D28
56
DDR_A_D29
58
60
62
64
66
DDR_A_D30
68
DDR_A_D31
70
72
74
76
DDR_A_MA15
78
A15
A14
A11
A7
A6
A4
A2
A0
S0#
G2
DDR_A_MA14
80
82
DDR_A_MA11
84
DDR_A_MA7
86
88
DDR_A_MA6
90
DDR_A_MA4
92
94
DDR_A_MA2
96
DDR_A_MA0
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR3 SO-DIMM B H:4mm
Standard Type
P/N:SP07000H800
F/P:FOX_AS0A626-U4SN-7F_204P
4
+0.75VS
DDR_A_DQS#0 <6,8>
DDR_A_DQS0 <6,8>
DDR_RST# <6,8>
DDR_A_DQS#3 <6,8>
DDR_A_DQS3 <6,8>
DDR_CKE1 <6,8>
DDR_B_CLK3 <6>
DDR_B_CLK#3 <6>
DDR_A_BS1 <6,8>
DDR_A_RAS# <6,8>
DDR_CS0_DIMMB# <6>
DDR_B_ODT0 <6>
DDR_B_ODT1 <6>
1
C665
C665
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
DDR_A_DQS#5 <6,8>
DDR_A_DQS5 <6,8>
DDR_A_DQS#7 <6,8>
DDR_A_DQS7 <6,8>
DDR_EVENT# <6,8>
FCH_SMDAT0 <8,14,29>
FCH_SMCLK0 <8,14,29>
DDR_A_D[0..63]
DDR_A_MA[0..15]
DDR_A_DM[0..7]
+1.5V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
C44
C44
C45
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+VREF_CA
1
C666
C666
1000P_0402_50V7K
1000P_0402_50V7K
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
C45
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2010/08/20 2011/08/20
2010/08/20 2011/08/20
2010/08/20 2011/08/20
DDR_A_D[0..63] <6,8>
DDR_A_MA[0..15] <6,8>
DDR_A_DM[0..7] <6,8>
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
1
Compal Secret Data
Compal Secret Data
Compal Secret Data
C652
C652
Deciphered Date
Deciphered Date
Deciphered Date
C653
C653
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C654
C654
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C655
C655
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C682
C682
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C46
C46
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C683
C683
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C47
C47
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
C48
C48
1
1
CRB 0.1u X1 4,7uX1
+0.75VS
2
1
1
C664
C664
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
2
1
2
C51
C51
C50
C50
@
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
Place near JDIMM2
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
DDR3 SODIMM-II Socket
DDR3 SODIMM-II Socket
DDR3 SODIMM-II Socket
LA-7092P P5WE6/H6/S6
LA-7092P P5WE6/H6/S6
LA-7092P P5WE6/H6/S6
C49
C49
0.1U_0402_16V4Z
0.1U_0402_16V4Z
9 46Friday, October 29, 2010
9 46Friday, October 29, 2010
9 46Friday, October 29, 2010
0.3
0.3
0.3
5
4
3
2
1
LCD POWER CIRCUIT
+LCDVDD
D D
SSM3K7002F_SC59-3
SSM3K7002F_SC59-3
UMA@
UMA@
APU_ENVDD<5>
VGA_ENVDD<18>
+INVPWR_B+
FBMA-L11-201209-221LMA30T_0805
C C
W=60mils
C673
C673
680P_0402_50V7K
680P_0402_50V7K
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
1
1
C674
C674
68P_0402_50V8J
68P_0402_50V8J
2
2
C1007 220P_0402_50V7KC1007 220P_0402_50V7K
C677 220P_0402_50V7KC677 220P_0402_50V7K
C679 220P_0402_50V7KC679 220P_0402_50V7K
1 2
R963 0_0402_5%
R963 0_0402_5%
DISO@
DISO@
1 2
R964 0_0402_ 5%
R964 0_0402_ 5%
L2
L2
12
L1
L1
12
SM010014520 3000ma
220ohm@100mhz
DCR 0.04
12
12
12
12
R396
R396
300_0603_5%
300_0603_5%
13
D
D
Q81
Q81
S
S
LCDVDD_ON
12
1 2
L113
L113
1.2UH_1127AS-1R2N_2.4A_30%
1.2UH_1127AS-1R2N_2.4A_30%
EMI request for DVT
DAC_BRIG
INVT_PWM
DISPOFF#
2
G
G
13
D
D
2
G
G
S
S
R395
R395
100K_0402_5%
100K_0402_5%
+3VALW
12
R393
R393
10K_0402_5%
10K_0402_5%
R397
R397
1K_0402_5%
1K_0402_5%
0.047U_0402_16V7K
0.047U_0402_16V7K
Q83
Q83
SSM3K7002F_SC59-3
SSM3K7002F_SC59-3
Change 0603 size
For DVT
B+
For LCD flash
Change as 10k oh m
12
C670
C670
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
VGA_ENBKL<19>
APU_ENBKL<5>
BKOFF#<31>
1
2
2
C1005
C1005
G
G
+3VS
=
60mils
W
3
S
S
AO3413L_SOT23-3
AO3413L_SOT23-3
Q82
Q82
D
D
1
+LCDVDD
1
2
R1097 0_0402_5%DISO@R1097 0_0402_5%DISO@
1 2
R156 0_0402_5%UMA@R 156 0_0402_5%UMA@
1 2
R157 100K_0402_1%R157 100K_0402_1%
1
C669
C669
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
2
W=60mils
1
C1006
C1006
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1 2
R484 0_0402_5%R484 0_0402_5%
12
R48510K_0402_5% R48510K_0402_5%
Change 0603 size
For DVT
1 2
21
RB751V_SOD323
RB751V_SOD323
D4
@D4
@
+3VS
12
@
@
R483
R483
10K_0402_5%
10K_0402_5%
<NCQD0 use>
ENBKL <31>
DISPOFF#
LCD/LED PANEL Conn.
JLVDS1
JLVDS1
41
42
43
44
45
46
IPEX_20143-040E-20F
IPEX_20143-040E-20F
CONN@
CONN@
+LCDVDD
1
C671
C671
10U_0603_6.3V6M
10U_0603_6.3V6M
2
Change 0603 size
For DVT
1
1
2
2
G1
3
3
G2
4
4
G3
5
5
G4
6
6
G5
7
7
G6
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
Place closed to JLVDS1
1
C672
C672
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
+LCDVDD_L
INVT_PWM
DISPOFF#
I2CC_SCL
I2CC_SDA
TXOUT0ÂTXOUT0+
TXOUT1ÂTXOUT1+
TXOUT2ÂTXOUT2+
TXCLKÂTXCLK+
+INVPWR_B+
+LCDVDD
+3VS
R862 0_0402_5%@R862 0_0402_5%@
R860 0_0402_5%@R860 0_0402_5%@
+3VS
W=60mils
@
@
12
R841 0_0603_5%
R841 0_0603_5%
60mils
W=
DAC_BRIG <31>
12
12
+3VS
USB20_N5 <14>
USB20_P5 <14>
USB20_P5
+LCDVDD
LOCAL_DIM <31 >
COLOY_ENG_EN <31>
D15
@D15
@
6
CH3
5
Vp
4
CH4
CM1293-04SO_SOT23-6
CM1293-04SO_SOT23-6
CH2
CH1
USB20_N5
3
2
Vn
1
Change P/N as SC300000B00
B B
TXCLK+
TXCLK-
TXOUT2+
TXOUT2-
TXOUT1+ VGA_TXOUT1+
TXOUT1-
TXOUT0+
TXOUT0- VGA_TXOUT0-
I2CC_SDA
VGA ONLY
2 3
1 4
RP2 0_04 04_4P2R_5%DISO@RP2 0_0404_4P2R_5%DISO@
2 3
1 4
RP4 0_04 04_4P2R_5%DISO@RP4 0_0404_4P2R_5%DISO@
2 3
1 4
RP6 0_04 04_4P2R_5%DISO@RP6 0_0404_4P2R_5%DISO@
2 3
1 4
RP8 0_04 04_4P2R_5%DISO@RP8 0_0404_4P2R_5%DISO@
DISO@
DISO@
12
12
R2700_0402_5% DISO@ R2700_0402_5% DISO@
R2720_0402_5%
R2720_0402_5%
VGA_TXCLK+
VGA_TXCLK-
VGA_TXOUT2+
VGA_TXOUT2-
VGA_TXOUT1-
VGA_TXOUT0+
VGA_LCD_CLKI2CC_SCL
VGA_LCD_DAT
VGA_TXCLK+ <18>
VGA_TXCLK- <18>
VGA_TXOUT2+ <18>
VGA_TXOUT2- <18>
VGA_TXOUT1+ <18>
VGA_TXOUT1- <18>
VGA_TXOUT0+ <18>
VGA_TXOUT0- <18>
VGA_LCD_CLK <19>
VGA_LCD_DAT < 19>
APU_BLPWM<5>
EC_INVT_PWM<31>
VGA_INVT_PWM<18>
1 2
R1098 0_0402_5%UMA@R1098 0_0402_5%UMA@
1 2
R158 0_0402_5%DISO@R158 0_0402_5%DISO@
1 2
R1099 0_0402_5%@R1099 0_0402_5%@
INVT_PWMINVT_PWM
12
R1100
R1100
100K_0402_5%
100K_0402_5%
UMA ONLY
TXCLK+
TXCLK-
TXOUT2+
TXOUT2-
TXOUT0+
A A
TXOUT0- APU_TXOUT0-
I2CC_SDA
5
RP1 0_04 04_4P2R_5%UMA@RP1 0_0404_4P2R_5%UMA@
RP3 0_04 04_4P2R_5%UMA@RP3 0_0404_4P2R_5%UMA@
RP5 0_04 04_4P2R_5%UMA@RP5 0_0404_4P2R_5%UMA@
RP7 0_04 04_4P2R_5%UMA@RP7 0_0404_4P2R_5%UMA@
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
UMA@
UMA@
R2690_0402_5% UMA@ R2690_0402_5% UMA@
12
R2710_0402_5%
R2710_0402_5%
12
APU_TXCLK+
APU_TXCLK-
APU_TXOUT2+
APU_TXOUT2-
APU_TXOUT1+TXOUT1+
APU_TXOUT1-TXOUT1-
APU_TXOUT0+
APU_LCD_CLKI2CC_SCL
APU_LCD_DATA
APU_TXCLK+ <5>
APU_TXCLK- <5>
APU_TXOUT2+ <5>
APU_TXOUT2- <5>
APU_TXOUT1+ <5>
APU_TXOUT1- <5>
APU_TXOUT0+ <5>
APU_TXOUT0- <5>
APU_LCD_CLK <5>
APU_LCD_DATA <5>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/08/20 2011/08/20
2010/08/20 2011/08/20
2010/08/20 2011/08/20
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
2
Date: Sheet
LVDS/CAMERA
LVDS/CAMERA
LVDS/CAMERA
LA-7092P P5WE6/H6/S6
LA-7092P P5WE6/H6/S6
LA-7092P P5WE6/H6/S6
10 46Friday, October 29, 2010
10 46Friday, October 29, 2010
10 46Friday, October 29, 2010
1
0.3
0.3
0.3
of
5
D D
APU_HDMI_CLK<5>
VGA_HDMI_SCLK<19>
APU_HDMI_DATA<5>
VGA_HDMI_SDATA<19>
UMA@
UMA@
R970 0_0402_5%
R970 0_0402_5%
R971 0_0402_5%DISO@R971 0_0402_ 5%DISO@
R972 0_0402_5%
R972 0_0402_5%
R973 0_0402_5%DISO@R973 0_0402_ 5%DISO@
12
UMA@
UMA@
12
12
12
4
R966
R966
3
R521
@R521
@
0_0603_5%
0_0603_5%
+3VS
+3VS
0_0402_5%
R968
R968
1 2
1 2
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
0_0402_5%
G
G
S
S
G
G
2
BSH111 1N_SOT23-3
BSH111 1N_SOT23-3
13
D
S
D
S
Q128
Q128
BSH111 1N_SOT23-3
BSH111 1N_SOT23-3
@
@
R172 0_0402_5%
R172 0_0402_5%
@
@
R816 0_0402_5%
R816 0_0402_5%
+HDMI_5V_OUT
R965
R965
R522
R522
R161
1 2
2
13
D
D
Q86
Q86
12
12
R161
12
12
2K_0402_5%
2K_0402_5%
2K_0402_5%
2K_0402_5%
+5VS
Change P/N SCS00002000
HDMI_SCLK
HDMI_SDATA
1 2
D7
D7
+HDMI_5V
2 1
CH491DPT_SOT23-3
CH491DPT_SOT23-3
W=40mils
F2
F2
21
1.1A_6V_SMD1812P110TF
1.1A_6V_SMD1812P110TF
+HDMI_5V_OUT
1
C690
C690
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
1
HDMI connector
JHDMI1
JHDMI1
19
HP_DET
18
+5V
17
DDC/CEC_GND
16
SDA
15
SCL
14
Reserved
13
CEC
12
CK-
11
10
9
8
7
6
5
4
3
2
1
GND
CK_shield
GND
CK+
GND
D0-
GND
D0_shield
D0+
D1ÂD1_shield
D1+
D2ÂD2_shield
D2+
SUYIN_100042MR019S153ZL
SUYIN_100042MR019S153ZL
CONN@
CONN@
<NAV70 use>
20
21
22
23
+HDMI_5V_OUT
HDMI_HPD
HDMI_SDATA
HDMI_SCLK
HDMI_R_CK-
HDMI_R_CK+
HDMI_R_D0-
HDMI_R_D0+
HDMI_R_D1-
HDMI_R_D1+
HDMI_R_D2-
HDMI_R_D2+
Place closed to JHDMI1
C C
R524
R524
1 2
0_0402_5%
+3VS
R527
R527
0_0402_5%
Use common via on related pair
R974 0_0402_5%DISO@R 974 0_0402_ 5%DISO@
VGA_HDMI_TXD2-<19>
VGA_HDMI_TXD2+<19>
VGA_HDMI_TXD1-<19>
VGA_HDMI_TXD1+<19>
F
B B
rom VGA
From APU
VGA_HDMI_TXD0-<19>
VGA_HDMI_TXD0+<19>
VGA_HDMI_TXC-<19>
VGA_HDMI_TXC+< 19>
APU_HDMI_TX2N<5>
APU_HDMI_TX2P<5>
APU_HDMI_TX1N<5>
APU_HDMI_TX1P<5>
APU_HDMI_TX0N<5>
APU_HDMI_TX0P<5>
APU_HDMI_CLKN<5>
APU_HDMI_CLKP<5>
1 2
R975 0_0402_5%DISO@R 975 0_0402_ 5%DISO@
1 2
R976 0_0402_5%DISO@R 976 0_0402_ 5%DISO@
1 2
R978 0_0402_5%DISO@R 978 0_0402_ 5%DISO@
1 2
R979 0_0402_5%DISO@R 979 0_0402_ 5%DISO@
1 2
R980 0_0402_5%DISO@R 980 0_0402_ 5%DISO@
1 2
R982 0_0402_5%DISO@R 982 0_0402_ 5%DISO@
1 2
R983 0_0402_5%DISO@R 983 0_0402_ 5%DISO@
1 2
R984 0_0402_5%UMA@R984 0_0402_5%UMA@
1 2
R985 0_0402_5%UMA@R985 0_0402_5%UMA@
1 2
R986 0_0402_5%UMA@R986 0_0402_5%UMA@
1 2
R987 0_0402_5%UMA@R987 0_0402_5%UMA@
1 2
R988 0_0402_5%UMA@R988 0_0402_5%UMA@
1 2
R989 0_0402_5%UMA@R989 0_0402_5%UMA@
1 2
R990 0_0402_5%UMA@R990 0_0402_5%UMA@
1 2
R991 0_0402_5%UMA@R991 0_0402_5%UMA@
1 2
HDMI_C_TX2-_R
HDMI_C_TX2+_R
HDMI_C_TX1-_R
HDMI_C_TX1+_R
HDMI_C_TX0-_R
HDMI_C_TX0+_R
HDMI_C_CLK-_R
HDMI_C_CLK+_R
HDMI_C_TX2-_R
HDMI_C_TX2+_R
HDMI_C_TX1-_R
HDMI_C_TX1+_R
HDMI_C_TX0-_R
HDMI_C_TX0+_R
HDMI_C_CLK-_R
HDMI_C_CLK+_R
DISO@
DISO@
VGA_HDMI_DET<19>
APU_HDMI_HPD<5>
12
R977 0_0402_5%
R977 0_0402_5%
UMA@
UMA@
12
R981 0_0402_5%
R981 0_0402_5%
10K_0402_5%
10K_0402_5%
0_0402_5%
1 2
C
C
2
B
B
E
E
3 1
Q34
Q34
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
12
R530
R530
0_0402_5%
@
@
1 2
R525 150K_0402_5%R525 150K_0402_5%
HDMI_HPD
12
R528
R528
365K_0402_1%
365K_0402_1%
@
@
SM070001310 400ma 90ohm@100mhz DCR 0.3
HDMI_C_CLK-
L68
L68
WCM-2012-900T_0805
WCM-2012-900T_0805
@
@
HDMI_C_CLK+
HDMI_C_TX0- HDMI_R_D0-
L69
L69
WCM-2012-900T_0805
WCM-2012-900T_0805
@
@
HDMI_C_TX0+
HDMI_C_TX1-
L54
L54
WCM-2012-900T_0805
WCM-2012-900T_0805
@
@
HDMI_C_TX1+
HDMI_C_TX2-
L70
L70
WCM-2012-900T_0805
WCM-2012-900T_0805
@
@
R514 0_0402_5%R5 14 0_0402_5%
1 2
1
1
4
4
R513 0_0402_5%R5 13 0_0402_5%
1 2
R516 0_0402_5%R5 16 0_0402_5%
1 2
1
1
4
4
R515 0_0402_5%R5 15 0_0402_5%
1 2
R518 0_0402_5%R5 18 0_0402_5%
1 2
1
1
4
4
R517 0_0402_5%R5 17 0_0402_5%
1 2
R520 0_0402_5%R5 20 0_0402_5%
1 2
1
1
4
4
R519 0_0402_5%R5 19 0_0402_5%
1 2
2
2
3
3
2
2
3
3
2
2
3
3
2
2
3
3
HDMI_R_CK-
HDMI_R_CK+
HDMI_R_D0+
HDMI_R_D1-
HDMI_R_D1+
HDMI_R_D2-
HDMI_R_D2+HDMI_C_TX2+
Place closed to JHDMI1
HDMI_C_TX2-_R
HDMI_C_TX2+_R
HDMI_C_TX1-_R
HDMI_C_TX1+_R
HDMI_C_TX0-_R
HDMI_C_TX0+_R
A A
HDMI_C_CLK-_R
HDMI_C_CLK+_R
C508 0.1U_0402_16V7KC508 0.1U_0402_16V7K
C509 0.1U_0402_16V7KC509 0.1U_0402_16V7K
C510 0.1U_0402_16V7KC510 0.1U_0402_16V7K
C511 0.1U_0402_16V7KC511 0.1U_0402_16V7K
C512 0.1U_0402_16V7KC512 0.1U_0402_16V7K
C513 0.1U_0402_16V7KC513 0.1U_0402_16V7K
C514 0.1U_0402_16V7KC514 0.1U_0402_16V7K
C515 0.1U_0402_16V7KC515 0.1U_0402_16V7K
12
12
12
12
12
12
12
12
5
HDMI_C_TX2ÂHDMI_C_TX2+
HDMI_C_TX1ÂHDMI_C_TX1+
HDMI_C_TX0ÂHDMI_C_TX0+
HDMI_C_CLKÂHDMI_C_CLK+
R509 499_0402_1%R509 499_0402_1%
1 2
R508 499_0402_1%R508 499_0402_1%
1 2
R506 499_0402_1%R506 499_0402_1%
1 2
R505 499_0402_1%R505 499_0402_1%
1 2
R503 499_0402_1%R503 499_0402_1%
1 2
R502 499_0402_1%R502 499_0402_1%
1 2
R501 499_0402_1%R501 499_0402_1%
1 2
R500 499_0402_1%R500 499_0402_1%
1 2
+HDMI_5V_OUT
12
R512
R512
100K_0402_5%
100K_0402_5%
13
D
D
2N7002_SOT23
2N7002_SOT23
2
G
G
Q87
Q87
S
S
4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/08/20 2011/08/20
2010/08/20 2011/08/20
2010/08/20 2011/08/20
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
HDMI Connector
HDMI Connector
HDMI Connector
LA-7092P P5WE6/H6/S6
LA-7092P P5WE6/H6/S6
LA-7092P P5WE6/H6/S6
11 46Friday, October 29, 2010
11 46Friday, October 29, 2010
11 46Friday, October 29, 2010
1
of
0.3
0.3
0.3
A
B
C
D
E
2
3
2
D32
D32
@
@
C697
C697
1
2
3
1
C695
C695
10P_040 2_50V8J
10P_040 2_50V8J
L60
L60
1 2
FCM2012 CF-800T06_2P
FCM2012 CF-800T06_2P
L81
L81
1 2
FCM2012 CF-800T06_2P
FCM2012 CF-800T06_2P
1
2
D33
D33
PJDLC05 C_SOT23-3
PJDLC05 C_SOT23-3
@
@
1
1
C696
C696
2
10P_040 2_50V8J
10P_040 2_50V8J
C700
C700
10P_040 2_50V8J
10P_040 2_50V8J
CRT_R_1
CRT_G_1
CRT_B_1
1
2
CRT Connector
PJDLC05 C_SOT23-3
1 2
1 2
1 2
PJDLC05 C_SOT23-3
10P_040 2_50V8J
10P_040 2_50V8J
1 1
CRT_R
CRT_G
CRT_B
150_0402_1%
150_0402_1%
150_0402_1%
12
R533
R533
+CRT_VC C
150_0402_1%
A2Y
R537 10 K_0402_5% R537 10 K_0402_5%
5
P
G
3
1
OE#
150_0402_1%
150_0402_1%
12
12
R532
R532
R531
R531
+CRT_VC C
C699 0 .1U_0402_16V4 ZC699 0 .1U_0402_16V4 Z
2 2
1 2
CRT_HSYNC
C701 0 .1U_0402_16V4 Z C701 0 .1U_0402_16V4 Z
5
1
U23
U23
P
4
OE#
A2Y
G
74AHCT1 G125GW_SO T353-5
74AHCT1 G125GW_SO T353-5
3
1 2
CRT_VSYNC
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
C692
C692
C693
C693
1
1
2
2
12
CRT_HSYNC _1
U19
U19
CRT_VSYNC _1
4
74AHCT1 G125GW_SO T353-5
74AHCT1 G125GW_SO T353-5
L57 FCM2012 CF-800T06_2P
L57 FCM2012 CF-800T06_2P
L58 FCM2012 CF-800T06_2P
L58 FCM2012 CF-800T06_2P
L59 FCM2012 CF-800T06_2P
L59 FCM2012 CF-800T06_2P
10P_0402_50V8J
10P_0402_50V8J
C694
C694
1
2
+5VS
Change P/N SCS00002000
CRT_HSYNC _2
CRT_VSYNC _2
1
C702
C702
10P_040 2_50V8J
10P_040 2_50V8J
2
W=40mils
D14
D14
2 1
CH491DP T_SOT23-3
CH491DP T_SOT23-3
0.1U_040 2_16V4Z
0.1U_040 2_16V4Z
1
C698
C698
100P_04 02_50V8J
100P_04 02_50V8J
2
C703
C703
68P_040 2_50V8J
68P_040 2_50V8J
F1
F1
21
1.1A_6VD C_FUSE
1.1A_6VD C_FUSE
1
C691
C691
2
1
2
1
C704
C704
68P_040 2_50V8J
68P_040 2_50V8J
2
W=40mils
T95PA DT95PAD
T97PA DT97PAD
DSUB_12
DSUB_15
+CRT_VC C+R_CRT_VC C
JCRT1
JCRT1
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
C-H_13-12 201513CP
C-H_13-12 201513CP
CONN@
CONN@
16
G
G
17
G
G
P/N : DC060003V00
F/P : SUYIN_070546HR015M21MZR_15P-T
Close to Conn side
R549
R549
4.7K_040 2_5%
4.7K_040 2_5%
+CRT_VC C
12
D
12
R548
R548
4.7K_040 2_5%
4.7K_040 2_5%
BSH111 1 N_SOT23-3
BSH111 1 N_SOT23-3
R1009 0_0 402_5%
R1009 0_0 402_5%
R1010 0_0 402_5%
R1010 0_0 402_5%
+3VS
2
G
G
1 3
D
S
D
Q89
Q89
@
@
@
@
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
S
2
G
G
1 3
D
S
D
Q129
Q129
BSH111 1 N_SOT23-3
BSH111 1 N_SOT23-3
12
12
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
LA-7092P P5WE6/H6/S6
LA-7092P P5WE6/H6/S6
LA-7092P P5WE6/H6/S6
S
CRT Connector
CRT Connector
CRT Connector
CRT_DAT ADSUB_12
CRT_CLK
E
12 46Friday, October 29, 201 0
12 46Friday, October 29, 201 0
12 46Friday, October 29, 201 0
0.3
0.3
0.3
3 3
Use common via on related pair
APU_CRT _R<5>
APU_CRT _G< 5>
APU_CRT _B<5>
om APU
Fr
4 4
F
rom VGA
APU_CRT _HSYNC<5>
APU_CRT _VSYNC<5>
APU_CRT _DDC_SDA< 5>
APU_CRT _DDC_SCL<5 >
VGA_CRT _R<19>
VGA_CRT _G<19>
VGA_CRT _B<19>
VGA_CRT _HSYNC<19>
VGA_CRT _VSYNC<19>
VGA_CRT _DATA<19>
VGA_CRT _CLK<19>
A
APU_CRT _R
APU_CRT _G
APU_CRT _B
APU_CRT _HSYNC
APU_CRT _VSYNC
APU_CRT _DDC_SCL CRT_CLK
VGA_CRT _R
VGA_CRT _G
VGA_CRT _B
VGA_CRT _HSYNC
VGA_CRT _VSYNC
VGA_CRT _DATA
VGA_CRT _CLK
R995 0_ 0402_5%UMA@R9 95 0_0402_5%UMA@
R996 0_ 0402_5%UMA@R9 96 0_0402_5%UMA@
R997 0_ 0402_5%UMA@R9 97 0_0402_5%UMA@
R998 0_ 0402_5%UMA@R9 98 0_0402_5%UMA@
R999 0_ 0402_5%UMA@R9 99 0_0402_5%UMA@
R1000 0 _0402_5%UMA@R 1000 0_0402_ 5%UMA@
R1001 0 _0402_5%UMA@R 1001 0_0402_ 5%UMA@
R1002 0 _0402_5%DISO@R1 002 0_0402_5 %DISO@
R1003 0_0402_5 %DISO@R 1003 0_0402_ 5%DISO@
R1004 0 _0402_5%DISO@R1 004 0_0402_5 %DISO@
R1005 0 _0402_5%DISO@R1 005 0_0402_5 %DISO@
R1006 0 _0402_5%DISO@R1 006 0_0402_5 %DISO@
R1007 0 _0402_5%DISO@R1 007 0_0402_5 %DISO@
R1008 0 _0402_5%DISO@R1 008 0_0402_5 %DISO@
12
12
12
12
12
12
12
12
12
12
12
12
12
12
B
CRT_R
CRT_G
CRT_B
CRT_HSYNC
CRT_VSYNC
CRT_DAT A
CRT_R
CRT_G
CRT_B
CRT_HSYNC
CRT_VSYNC
CRT_DAT A
CRT_CLK
DSUB_15APU_CRT _DDC_SDA
Security Class ification
Security Class ification
Security Class ification
2010/08/ 20 2011/08/ 20
2010/08/ 20 2011/08/ 20
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2010/08/ 20 2011/08/ 20
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
A
B
C
D
E
For PCIE device reset on FS1 (GFX,GLAN,WLAN,LVDS Travis)
U31E
For DVT 1011
A_RST#<31>
UMI_RX0P<6>
UMI_RX0N<6>
UMI_RX1P<6>
+PCIE_VDDAN
PCIE_FTX_C_DRX_P2<26>
PCIE_FTX_C_DRX_N2<26>
PCIE_FTX_C_DRX_P3<29>
PCIE_FTX_C_DRX_N3<29>
PCIE_FRX_DTX_P2<26>
PCIE_FRX_DTX_N2<26>
PCIE_FRX_DTX_P3<29>
PCIE_FRX_DTX_N3<29>
UMI_RX1N<6>
UMI_RX2P<6>
UMI_RX2N<6>
UMI_RX3P<6>
UMI_RX3N<6>
UMI_TX0P<6>
UMI_TX0N<6>
UMI_TX1P<6>
UMI_TX1N<6>
UMI_TX2P<6>
UMI_TX2N<6>
UMI_TX3P<6>
UMI_TX3N<6>
1 1
LAN
WLAN
2 2
C53 0.1U_0402_16V7KC53 0.1U_0402_16V 7K
1 2
C54 0.1U_0402_16V7KC54 0.1U_0402_16V 7K
1 2
C55 0.1U_0402_16V7KC55 0.1U_0402_16V 7K
1 2
C56 0.1U_0402_16V7KC56 0.1U_0402_16V 7K
1 2
C57 0.1U_0402_16V7KC57 0.1U_0402_16V 7K
1 2
C58 0.1U_0402_16V7KC58 0.1U_0402_16V 7K
1 2
C59 0.1U_0402_16V7KC59 0.1U_0402_16V 7K
1 2
C60 0.1U_0402_16V7KC60 0.1U_0402_16V 7K
1 2
R560 590_0402_1%R560 590_0402_1%
R561 2K_0402_1%R 561 2K_0402_1%
12
12
C61 0.1U_0402_16V7KC61 0.1U_0402_16V7K
1 2
C62 0.1U_0402_16V7KC62 0.1U_0402_16V7K
1 2
C717 0.1U_0402_16V7KC717 0.1U_0402_16V7K
1 2
C63 0.1U_0402_16V7KC63 0.1U_0402_16V7K
1 2
PCIE_RST#
A_RST#
UMI_RX0P_C
UMI_RX0N_C
UMI_RX1P_C
UMI_RX1N_C
UMI_RX2P_C
UMI_RX2N_C
UMI_RX3P_C
UMI_RX3N_C
PCIE_FTX_DRX_P2
PCIE_FTX_DRX_N2
PCIE_FTX_DRX_P3
PCIE_FTX_DRX_N3
close to FCH within 1"
CLK_SD_48M<29>
1M_0603_5%
1M_0603_5%
R576
R576
APU_DISP_CLKP_R
APU_DISP_CLKN_R
APU_CLKP_R
APU_CLKN_R
CLK_PCIE_VGA_R
CLK_PCIE_VGA#_R
CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R
CLK_PCIE_MINI1_R
CLK_PCIE_MINI1#_R
25M_CLK_X1
25M_CLK_X2
FCH : SA000046H60 (S IC 218-0792001 A12 HUDSON-M1 FCBGA 605P)
FCH : SA000046H70 (S IC 218-0792006 A13 HUDSON-M1 FCBGA 605P)
B
R564 0_0402_5%R564 0_0402_5%
APU_DISP_CLKP<5>
APU_DISP_CLKN<5>
APU_CLKP<5>
APU_CLKN<5>
CLK_PCIE_VGA<18>
CLK_PCIE_VGA#<18>
LAN
WLAN
3 3
CLK_PCIE_LAN<2 6>
CLK_PCIE_LAN#<26>
CLK_PCIE_MINI1<29>
CLK_PCIE_MINI1#<29>
1 2
R565 0_0402_5%R565 0_0402_5%
1 2
R162 0_0402_5%R162 0_0402_5%
1 2
R163 0_0402_5%R163 0_0402_5%
1 2
R569 0_0402_5%R569 0_0402_5%
1 2
R570 0_0402_5%R570 0_0402_5%
1 2
R571 0_0402_5%R571 0_0402_5%
1 2
R572 0_0402_5%R572 0_0402_5%
1 2
R573 0_0402_5%R573 0_0402_5%
1 2
R574 0_0402_5%R574 0_0402_5%
1 2
Follow result by vender 10/11
1 2
C66
C66
27P_0402_50V8J
27P_0402_50V8J
C67
C67
27P_0402_50V8J
27P_0402_50V8J
1 2
4 4
C64
C64
1 2
22P_0402_50V8J
22P_0402_50V8J
20M_0603_5%
20M_0603_5%
C65
C65
22P_0402_50V8J
22P_0402_50V8J
R563
R563
1 2
12
Close to FCH
Y4
Y4
4
OSC
1
OSC
32.768KHZ_12.5PF_Q13MC14610050_10PPM
32.768KHZ_12.5PF_Q13MC14610050_10PPM
A
RTC_32KHI
3
NC
2
NC
RTC_32KHO
12
Y3
Y3
25MHZ_20PF_7A25000012
25MHZ_20PF_7A25000012
U31E
P1
PCIE_RST_L
L1
A_RST_L
AD26
UMI_TX0P
AD27
UMI_TX0N
AC28
UMI_TX1P
AC29
UMI_TX1N
AB29
UMI_TX2P
AB28
UMI_TX2N
AB26
UMI_TX3P
AB27
UMI_TX3N
AE24
UMI_RX0P
AE23
UMI_RX0N
AD25
UMI_RX1P
AD24
UMI_RX1N
AC24
UMI_RX2P
AC25
UMI_RX2N
AB25
UMI_RX3P
AB24
UMI_RX3N
AD29
PCIE_CALRP
AD28
PCIE_CALRN
AA28
GPP_TX0P
AA29
GPP_TX0N
Y29
GPP_TX1P
Y28
GPP_TX1N
Y26
GPP_TX2P
Y27
GPP_TX2N
W28
GPP_TX3P
W29
GPP_TX3N
AA22
GPP_RX0P
Y21
GPP_RX0N
AA25
GPP_RX1P
AA24
GPP_RX1N
W23
GPP_RX2P
V24
GPP_RX2N
W24
GPP_RX3P
W25
GPP_RX3N
M23
PCIE_RCLKP/NB_LNK_CLKP
P23
PCIE_RCLKN/NB_LNK_CLKN
U29
NB_DISP_CLKP
U28
NB_DISP_CLKN
T26
NB_HT_CLKP
T27
NB_HT_CLKN
V21
CPU_HT_CLKP
T21
CPU_HT_CLKN
V23
SLT_GFX_CLKP
T23
SLT_GFX_CLKN
L29
GPP_CLK0P
L28
GPP_CLK0N
N29
GPP_CLK1P
N28
GPP_CLK1N
M29
GPP_CLK2P
M28
GPP_CLK2N
T25
GPP_CLK3P
V25
GPP_CLK3N
L24
GPP_CLK4P
L23
GPP_CLK4N
P25
GPP_CLK5P
M25
GPP_CLK5N
P29
GPP_CLK6P
P28
GPP_CLK6N
N26
GPP_CLK7P
N27
GPP_CLK7N
T29
GPP_CLK8P
T28
GPP_CLK8N
L25
14M_25M_48M_OSC
L26
25M_X1
L27
25M_X2
21807-A11-HUDSON-M1_FCBGA605
21807-A11-HUDSON-M1_FCBGA605
PCI CLKS
PCI CLKS
PCI EXPRESS I/F
PCI EXPRESS I/F
CLOCK GENERATOR
CLOCK GENERATOR
CPU
CPU
ALLOW_LDTSTP/DMA_AC TIVE_L
RTC
RTC
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38
PCICLK4/14M_OSC/GPO39
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
LPC
LPC
INTRUDER_ALERT_L
C
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
REQ1_L/GPIO40
GNT1_L/GPO44
GNT2_L/GPO45
INTE_L/GPIO32
INTF_L/GPIO33
INTG_L/GPIO34
INTH_L/GPIO35
SERIRQ/GPIO48
VDDBT_RTC_G
PCI I/F
PCI I/F
REQ2_L/CLK_REQ8_L/GPIO41
REQ3_L/CLK_REQ5_L/GPIO42
GNT3_L/CLK_REQ7_L/GPIO46
LDRQ1_L/CLK_REQ6_L/GPIO49
W2
PCICLK0
W1
W3
W4
Y1
V2
PCIRST_L
AA1
AD0/GPIO0
AA4
AD1/GPIO1
AA3
AD2/GPIO2
AB1
AD3/GPIO3
AA5
AD4/GPIO4
AB2
AD5/GPIO5
AB6
AD6/GPIO6
AB5
AD7/GPIO7
AA6
AD8/GPIO8
AC2
AD9/GPIO9
AC3
AC4
AC1
AD1
AD2
AC6
AE2
AE1
AF8
AE3
AF1
AG1
AF2
AE9
AD9
AC11
AF6
AF4
AF3
AH2
AG2
AH3
AA8
CBE0_L
AD5
CBE1_L
AD8
CBE2_L
AA10
CBE3_L
AE8
FRAME_L
AB9
DEVSEL_L
AJ3
IRDY_L
AE7
TRDY_L
AC5
PAR
AF5
STOP_L
AE6
PERR_L
AE4
SERR_L
AE11
REQ0_L
AH5
AH4
AC12
AD12
GNT0_L
AJ5
AH6
AB12
AB11
CLKRUN_L
AD7
LOCK_L
AJ6
AG6
AG4
AJ4
H24
LPCCLK0
H25
LPCCLK1
J27
LAD0
J26
LAD1
H29
LAD2
H28
LAD3
G28
LFRAME_L
J25
LDRQ0_L
AA18
AB19
G21
H21
PROCHOT_L
K19
LDT_PG
G22
LDT_STP_L
J24
LDT_RST_L
C1
32K_X1
C2
32K_X2
D2
RTCCLK
B2
B1
2010/08/20 2011/08/20
2010/08/20 2011/08/20
2010/08/20 2011/08/20
T96PAD T96P AD
T92PAD T92P AD
1 2
R99 10K_0402_5%R99 10K_0402_5%
R853 0_0402_5%R853 0_0402_5%
1 2
R575 22_0402_5%R575 22_0402_5%
1 2
RTC_32KHI
RTC_32KHO
RTC_CLK <17,31>
C1272
C1272
1
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
PCI_CLK1 <17>
PCI_CLK2 <17>
PCI_CLK3 <17>
PCI_CLK4 <17>
VGA_PWRGD_R
LPC_CLK1 <17>
LPC_AD0 <31>
LPC_AD1 <31>
LPC_AD2 <31>
LPC_AD3 <31>
LPC_FRAME# <31>
ALLOW_STOP# <5>
FCH_PROCHOT# <5>
APU_PWRGD <5>
APU_RST# <5>
C1271
C1271
for Clear CMOS
1U_0402_6.3V4Z
1U_0402_6.3V4Z
A_RST#
PCI_AD23 <17>
PCI_AD24 <17>
PCI_AD25 <17>
PCI_AD26 <17>
PCI_AD27 <17>
VGA_PWRGD<24,43>
PE_GPIO0 <18>
PE_GPIO1 <24,35>
SERIRQ <31>
1 2
R864 510_0402_5%R864 510_0402_5%
W=20mils
R175 33_0402_5%R175 33_0402_5%
1 2
150P_0402_50V8J
150P_0402_50V8J
1
C1233
C1233
2
VGA_PWRGD VGA_PWRGD_R
For DVT 1011
LPC_CLK0 <17>
LPC_CLK0_EC <31>
R865
R865
@
@
0_0603_5%
0_0603_5%
1 2
D
+3VALW
C1234
C1234
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
5
2
P
B
4
Y
1
A
R174
R174
8.2K_0402_5%@
8.2K_0402_5%@
1 2
NC7SZ08P5X_NL_SC70-5
NC7SZ08P5X_NL_SC70-5
G
3
U28
U28
NC7SZ08P5X_NL_SC70-5
NC7SZ08P5X_NL_SC70-5
Need to check material?
APU_PWRGD
+3VALW
U33
U33
2
1
+1.8VS +3VS
S
S
FDV301N_NL_SOT23-3
FDV301N_NL_SOT23-3
C1199
C1199
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
5
P
B
4
Y
A
G
3
1 2
R839 0_0402_5%R839 0_0402_5%
10K_0402_5%
10K_0402_5%
G
G
2
13
D
D
Q90
Q90
1 2
R830 0_0402_5%
R830 0_0402_5%
1 2
R838 100K_0402_5%
R838 100K_0402_5%
RTC BATT Conn.
SUYIN_060003HA002G202ZL
P/N: SP07000OU00
F/P: SUYIN_060003HA002G202ZL_2P
+RTCVCC
1
C1270
C1270
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
SUYIN_060003HA002G202ZL
D23
D23
1
DAN202UT106_SC70-3
DAN202UT106_SC70-3
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
FCH PCIE/PCI/ACPI/LPC/RTC
FCH PCIE/PCI/ACPI/LPC/RTC
FCH PCIE/PCI/ACPI/LPC/RTC
LA-7092P P5WE6/H6/S6
LA-7092P P5WE6/H6/S6
LA-7092P P5WE6/H6/S6
PLT_RST# <18,26,29>
PCIE_RST#
@
@
1 2
R582 0_0402_5%
R582 0_0402_5%
12
R164
R164
@
@
@
@
+RTCBATT
+RTCBATT
12
R179
R179
1K_0402_5%
1K_0402_5%
2
3
E
H_PWRGD_L <44>
1
CONN@
CONN@
JBATT2
JBATT2
+
-
2
+CHGRTC
13 46Friday, October 29, 2010
13 46Friday, October 29, 2010
13 46Friday, October 29, 2010
0.3
0.3
0.3
+3VALW
1 2
R870 10K_0402_5%R870 10K_0402_5%
1 2
R871 10K_0402_5%R871 10K_0402_5%
1 2
R872 10K_0402_5%R872 10K_0402_5%
1 2
R603 10K_0402_5%R603 10K_0402_5%
1 2
R604 10K_0402_5%R604 10K_0402_5%
1 2
1 1
2 2
3 3
R605 10K_0402_5%R605 10K_0402_5%
1 2
R817 10K_0402_5%R817 10K_0402_5%
+3VS
1 2
R818 10K_0402_5%R818 10K_0402_5%
1 2
R597 4.7K_0402_5%R597 4.7K_0402_5%
1 2
R598 2.2K_0402_5%R598 2.2K_0402_5%
1 2
R599 2.2K_0402_5%R599 2.2K_0402_5%
FCH_PWRGD<44>
0.1U_0402_16V7K
0.1U_0402_16V7K
@
@
1 2
+3VS
R626 2.2K_0402_5%
R626 2.2K_0402_5%
@
@
1 2
R404 100K_0402_5%
R404 100K_0402_5%
@
@
1 2
R173 10K_0402_5%
R173 10K_0402_5%
1 2
R587 10K_0402_5%R587 10K_0402_5%
1 2
R588 10K_0402_5%R588 10K_0402_5%
1 2
R606 2.2K_0402_5%R606 2.2K_0402_5%
@
@
1 2
R607 10K_0402_5%
R607 10K_0402_5%
@
@
1 2
R608 10K_0402_5%
R608 10K_0402_5%
1 2
R609 10K_0402_5%R609 10K_0402_5%
Pull-down for en able high perfo rmance mode
20100527 (requir ed for M1)
12
12
PX@
PX@
VGA@
VGA@
R911
R911
R912
R912
10K_0402_5%
10K_0402_5%
BACO@
BACO@
R915
R915
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
12
WOPX@
WOPX@
R914
R914
10K_0402_5%
10K_0402_5%
R910
R910
10K_0402_5%
10K_0402_5%
12
WOVGA@
WOVGA@
R913
R913
10K_0402_5%
10K_0402_5%
A
USB_OC2#
USB_OC1#
USB_OC0#
FCH_SIC
FCH_SID
FCH_PCIE_WAKE#
LAN_CLKREQ#
MINI1_CLKREQ#
NB_PWRGD
FCH_SMCLK0
FCH_SMDAT0
R580 0_0402_5%@R580 0_0402_5%@
R581 0_0402_5%R581 0_0402_5%
4
2
@
@
C112
C112
1
VRAM_SEL
VGA_CLKREQ#_R
+3VALW+3VALW+3VALW
12
GPIO189
GPIO190
GPIO191
12
+3VS
@
@
C111 0.1U_0402_16V7K
C111 0.1U_0402_16V7K
1 2
5
2
P
B
Y
1
A
G
NC7SZ08P5X_NL_SC70-5
NC7SZ08P5X_NL_SC70-5
3
U30
U30
VRAM_Freq : 1->900Hz
0-> 800Hz*
FCH_SMCLK1
FCH_SMDAT1
EC_RSMRST#
HDA_BITCLK
HDA_SDIN0
HDA_SDOUT
12
12
@
@
1 2
R929 10K_0402_5%R929 10K_0402_5%
@
@
1 2
R930 10K_0402_5%
R930 10K_0402_5%
1 2
R931 10K_0402_5%R931 10K_0402_5%
1 2
R932 10K_0402_5%R932 10K_0402_5%
1 2
R933 10K_0402_5%R933 10K_0402_5%
+3VALW
HDA_BITCLK_AUDIO<27>
HDA_SDOUT_AUDIO<27>
HDA_SDIN0<27>
HDA_SYNC_AUDIO<27>
HDA_RST_AUDIO#<27>
ODD_DA#_FCH
ODD_DETECT#
EC_PWROK <31>
VGATE <31,44>
EC_LID_OUT#
R579 10K_0402_5%@R579 10K_0402_5%@
USB_OC7#
USB_OC5#
1 2
B
U31A
U31A
GPIO187
GPIO188
J2
PCI_PME_L/GEVENT4_L
K1
RI_L/GEVENT22_L
D3
SPI_CS3_L/GBE_STAT1/GEVENT21_L
F1
SLP_S3_L
H1
SLP_S5_L
F2
PWR_BTN_L
H5
PWR_GOOD
G6
SUS_STAT_L
B3
TEST0
C4
TEST1/TMS
F6
TEST2
AD21
GA20IN/GEVENT0_L
AE21
KBRST_L/GEVENT1_L
K2
LPC_PME_L/GEVENT3_L
J29
LPC_SMI_L/GEVENT23_L
H2
GEVENT5_L
J1
SYS_RESET_L/GEVENT19_L
H6
WAKE_L/GEVENT8_L
F3
IR_RX1/GEVENT20_L
J6
THRMTRIP_L/SMBALERT_L/GEVEN T2_L
AC19
NB_PWRGD
G1
RSMRST_L
AD19
CLK_REQ4_L/SATA_IS0_L/GPIO64
AA16
CLK_REQ3_L/SATA_IS1_L/GPIO63
AB21
SMARTVOLT1/SATA_IS2_L/GPIO50
AC18
CLK_REQ0_L/SATA_IS3_L/GPIO60
AF20
SATA_IS4_L/FANOUT3/GPIO55
AE19
SATA_IS5_L/FANIN3/GPIO59
AF19
SPKR_GPIO66
AD22
SCL0_GPIO43
AE22
SDA0_GPIO47
F5
SCL1_GPIO227
F4
SDA1_GPIO228
AH21
CLK_REQ2_L/FANIN4_GPIO62
AB18
CLK_REQ1_L/FANOUT4_GPIO61
E1
IR_LED_L/LLB_L/GPIO184
AJ21
SMARTVOLT2/SHUTDOWN _L/GPIO51
H4
DDR3_RST_L/GEVENT7_L
D5
GBE_LED0/GPIO183
D7
GBE_LED1/GEVENT9_L
G5
GBE_LED2/GEVENT10_L
K3
GBE_STAT0/GEVENT11_L
AA20
CLK_REQG_L/GPIO65_OSCIN
H3
BLINK/USB_OC7_L/GEVENT18_L
D1
USB_OC6_L/IR_TX1/GEVENT6_L
E4
USB_OC5_L/IR_TX0/GEVENT17_L
D4
USB_OC4_L/IR_RX0/GEVENT16_L
E8
USB_OC3_L/AC_PRES/TDO/GEVENT15_L
F7
USB_OC2_L/TCK/GEVENT14_L
E7
USB_OC1_L/TDI/GEVENT13_L
F8
USB_OC0_L/TRST_L/GEVENT12_L
M3
AZ_BITCLK
N1
AZ_SDOUT
L2
AZ_SDIN0/GPIO167
M2
AZ_SDIN1/GPIO168
M1
AZ_SDIN2/GPIO169
M4
AZ_SDIN3/GPIO170
N2
AZ_SYNC
P2
AZ_RST_L
T1
GBE_COL
T4
GBE_CRS
L6
GBE_MDCK
L5
GBE_MDIO
T9
GBE_RXCLK
U1
GBE_RXD3
U3
GBE_RXD2
T2
GBE_RXD1
U2
GBE_RXD0
T5
GBE_RXCTL/RXDV
V5
GBE_RXERR
P5
GBE_TXCLK
M5
GBE_TXD3
P9
GBE_TXD2
T7
GBE_TXD1
P7
GBE_TXD0
M7
GBE_TXCTL/TXEN
P4
GBE_PHY_PD
M9
GBE_PHY_RST_L
V7
GBE_PHY_INTR
E23
PS2_DAT/SDA4/GPIO187
E24
PS2_CLK/SCL4/GPIO188
F21
SPI_CS2_L/GBE_STAT2/GPIO166
G29
FC_RST_L/GPO160
D27
PS2KB_DAT/GPIO189
F28
PS2KB_CLK/GPIO190
F29
PS2M_DAT/GPIO191
E27
PS2M_CLK/GPIO192
21807-A11-HUDSON-M1_FCBGA605
21807-A11-HUDSON-M1_FCBGA605
EC_SWI#<31>
SLP_S3#<31>
SLP_S5#<31>
PBTN_OUT#<31>
EC_GA20<31>
EC_KBRST#<3 1>
EC_SCI#<31>
EC_SMI#< 31>
FCH_PCIE_WAKE#<26,29>
H_THERMTRIP#<5>
EC_RSMRST#<31>
LAN_CLKREQ#<26>
FCH_SPKR<27>
FCH_SMCLK0<8,9,29> USB20_P7 <33>
FCH_SMDAT0<8,9,29>
MINI1_CLKREQ#<29>
EC_LID_OUT#<31>
ODD_DA#_FCH< 30>
ODD_DETECT#< 30>
USB_OC2#<33>
USB_OC1#<33>
USB_OC0#<33>
R583 33_0402_5%R583 33_0402_5%
1 2
R165 33_0402_5%R165 33_0402_5%
1 2
R589 33_0402_5%R589 33_0402_5%
1 2
R590 33_0402_5%R590 33_0402_5%
1 2
R591 10K_0402_5%R591 10K_0402_5%
1 2
R592 10K_0402_5%R592 10K_0402_5%
1 2
R593 10K_0402_5%R593 10K_0402_5%
+3VALW
+3VALW
1 2
R596 10K_0402_5%R596 10K_0402_5%
1 2
R600 10K_0402_5%R600 10K_0402_5%
1 2
T85 PADT85 PAD
T86 PADT86 PAD
FCH_PWRGD
T82PADT82PAD
T83PADT83PAD
T84PADT84PAD
NB_PWRGD
FCH_SMCLK1
FCH_SMDAT1
VRAM_SEL
VGA_CLKREQ#_R
USB_OC7#
USB_OC5#
ODD_DA#_FCH
ODD_DETECT#
USB_OC2#
USB_OC1#
HDA_BITCLK
HDA_SDOUT
HDA_SDIN0
HDA_SYNC
HDA_RST#
GPIO189
GPIO190
GPIO191
C
USB MISC
USB MISC
ACPI/WAKE UP EVENTS
ACPI/WAKE UP EVENTS
GPIO
GPIO
USB OC
USB OC
HD AUDIO
HD AUDIO
GBE LAN
GBE LAN
USBCLK/14M_25M_48M_OSC
EC_PWM0/EC_TIMER 0/GPIO197
EC_PWM1/EC_TIMER 1/GPIO198
EC_PWM2/EC_TIMER 2/GPIO199
EC_PWM3/EC_TIMER 3/GPIO200
USB 1.1
USB 1.1
USB_FSD1P/GPIO186
USB_FSD0P/GPIO185
USB 2.0
USB 2.0
SCL3_LV/GPIO195
SDA3_LV/GPIO196
EMBEDDED CTRL
EMBEDDED CTRL
KSO_10/GPIO219
KSO_11/GPIO220
KSO_12/GPIO221
KSO_13/GPIO222
KSO_14/GPIO223
KSO_15/GPIO224
KSO_16/GPIO225
KSO_17/GPIO226
USB_RCOMP
USB_FSD1N
USB_FSD0N
USB_HSD13P
USB_HSD13N
USB_HSD12P
USB_HSD12N
USB_HSD11P
USB_HSD11N
USB_HSD10P
USB_HSD10N
USB_HSD9P
USB_HSD9N
USB_HSD8P
USB_HSD8N
USB_HSD7P
USB_HSD7N
USB_HSD6P
USB_HSD6N
USB_HSD5P
USB_HSD5N
USB_HSD4P
USB_HSD4N
USB_HSD3P
USB_HSD3N
USB_HSD2P
USB_HSD2N
USB_HSD1P
USB_HSD1N
USB_HSD0P
USB_HSD0N
SCL2/GPIO193
SDA2/GPIO194
KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208
KSO_0/GPIO209
KSO_1/GPIO210
KSO_2/GPIO211
KSO_3/GPIO212
KSO_4/GPIO213
KSO_5/GPIO214
KSO_6/GPIO215
KSO_7/GPIO216
KSO_8/GPIO217
KSO_9/GPIO218
D
A10
USB_RCOMP
G19
1 2
10mils and <1"
J10
H11
H9
USB_HSD[13:0]P/N:
J8
USB P/N pairs with trace lengths up to
10" and have a decoupling 5.6-pF capacitor
B12
footprint placed near the USB connector or device.
A12
F11
E11
E14
E12
J12
J14
A13
B13
D13
C13
G12
G14
G16
G18
D16
C16
B14
A14
E18
E16
J16
J18
B17
A17
A16
B16
GPIO193
D25
F23
B26
E26
F25
E22
F22
E21
G24
G25
E28
E29
D29
D28
C29
C28
B28
A27
B27
D26
A26
C26
A24
B25
A25
D24
B24
C24
B23
A23
D22
C22
A22
B22
R584 10K_0402_5%R584 10K_0402_5%
GPIO194
R586 10K_0402_5%R586 10K_0402_5%
EC_PWM2
EC_PWM3
R578
R578
11.8K_0402_1%
11.8K_0402_1%
USB20_P8 <29>
USB20_N8 <29>
USB20_N7 <33>
USB20_P6 <29>
USB20_N6 <29>
USB20_P5 <10>
USB20_N5 <10>
USB20_P2 <33>
USB20_N2 <33>
USB20_P1 <33>
USB20_N1 <33>
USB20_P0 <33>
USB20_N0 <33>
12
12
FCH_SIC <5>
FCH_SID <5>
EC_PWM2 <17>
EC_PWM3 <17>
MINI1-WLAN
BT
CardReader
Camera
USB/B (Right)
USB/B (Right)
USB Conn (Left)
E
Root
Root
EHCI CTL
DEV 19, Fn 2
Root
EHCI CTL
DEV 18, Fn 2
<Support Wakeup>
SKU_ID
4 4
(GPIO189)
PX_FN
(GPIO190)
PX_SEL
(GPIO191)
SKU_ID : 1->VGA*
0->UMA
PX_Function : 1->PX Enable*
0->PX D isable
PX_SEL : 1->PX 3.0*
0->PX 4.0
A
GPIO 189 190 191
UMA
0
DISO
PX3.0
PX4.0
0 1
1
0
1
1
1
1
1
1
0
B
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010/08/20 2011/08/20
2010/08/20 2011/08/20
2010/08/20 2011/08/20
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
FCH HDA/USB/ACPI
FCH HDA/USB/ACPI
FCH HDA/USB/ACPI
LA-7092P P5WE6/H6/S6
LA-7092P P5WE6/H6/S6
LA-7092P P5WE6/H6/S6
14 46Friday, October 29, 2010
14 46Friday, October 29, 2010
14 46Friday, October 29, 2010
E
0.3
0.3
0.3
A
1 1
C656 0.01U_0402_16V7KC656 0.01U_0402_16V7K
SATA_ITX_DRX_P0<30>
HDD
ODD
2 2
SATA_ITX_DRX_N0<30>
SATA_DTX_C_IRX_N0<30>
SATA_DTX_C_IRX_P0<30>
SATA_ITX_DRX_P1<30>
SATA_ITX_DRX_N1<30>
SATA_DTX_C_IRX_N1<30>
SATA_DTX_C_IRX_P1<30>
1 2
C658 0.01U_0402_16V7KC658 0.01U_0402_16V7K
1 2
C648 0.01U_0402_16V7KC648 0.01U_0402_16V7K
1 2
C649 0.01U_0402_16V7KC649 0.01U_0402_16V7K
1 2
10 mils and < 1"
R610 1K_0402_1%R610 1K_ 0402_1%
1 2
R611 931_0402_1%R611 931_0402_1%
+AVDD_SATA
SATA_LED#<32>
+3VS
3 3
1 2
R616 10K_0402_5%R616 10K_0402_5%
1 2
1 2
C107
C107
@
@
22P_0402_50V8J
22P_0402_50V8J
C106
C106
@
@
22P_0402_50V8J
22P_0402_50V8J
1 2
12
Y7
Y7
@
@
25MHZ_20PF_7A25000012
25MHZ_20PF_7A25000012
FCH_SI_SPI_SO
FCH_SO_SPI_SI
FCH_SPICLK
FCH_SPICS#/FSEL#
@
@
1M_0603_5%
1M_0603_5%
R861
R861
B
SATA_ITX_C_DRX_P0
SATA_ITX_C_DRX_N0
SATA_ITX_C_DRX_P1
SATA_ITX_C_DRX_N1
SATA_CALRP
SATA_CALRN
25M_SATA_X1
25M_SATA_X2
T78PADT78PAD
U31B
U31B
AH9
SATA_TX0P
AJ9
SATA_TX0N
AJ8
SATA_RX0N
AH8
SATA_RX0P
AH10
SATA_TX1P
AJ10
SATA_TX1N
AG10
SATA_RX1N
AF10
SATA_RX1P
AG12
SATA_TX2P
AF12
SATA_TX2N
AJ12
SATA_RX2N
AH12
SATA_RX2P
AH14
SATA_TX3P
AJ14
SATA_TX3N
AG14
SATA_RX3N
AF14
SATA_RX3P
AG17
SATA_TX4P
AF17
SATA_TX4N
AJ17
SATA_RX4N
AH17
SATA_RX4P
AJ18
SATA_TX5P
AH18
SATA_TX5N
AH19
SATA_RX5N
AJ19
SATA_RX5P
AB14
SATA_CALRP
AA14
SATA_CALRN
AD11
SATA_ACT_L/GPIO67
AD16
SATA_X1
AC16
SATA_X2
J5
SPI_DI/GPIO164
E2
SPI_DO/GPIO163
K4
SPI_CLK/GPIO162
K9
SPI_CS1_L/GPIO165
G2
ROM_RST_L/GPIO161
21807-A11-HUDSON-M1_FCBGA605
21807-A11-HUDSON-M1_FCBGA605
GPIOD
GPIOD
SERIAL ATA
SERIAL ATA
SPI ROM
SPI ROM
FC_CLK
FC_FBCLKOUT
FC_FBCLKIN
FC_OE_L/GPIOD145
FC_AVD_L/GPIOD146
FC_WE_L/GPIOD148
FC_CE1_L/GPIOD149
FC_CE2_L/GPIOD150
FC_INT1/GPIOD144
FC_INT2/GPIOD147
FC_ADQ0/GPIOD128
FC_ADQ1/GPIOD129
FC_ADQ2/GPIOD130
FC_ADQ3/GPIOD131
FC_ADQ4/GPIOD132
FC_ADQ5/GPIOD133
FC_ADQ6/GPIOD134
FC_ADQ7/GPIOD135
FC_ADQ8/GPIOD136
FC_ADQ9/GPIOD137
FC_ADQ10/GPIOD138
FC_ADQ11/GPIOD139
FC_ADQ12/GPIOD140
FC_ADQ13/GPIOD141
FC_ADQ14/GPIOD142
FC_ADQ15/GPIOD143
HW MONITOR
HW MONITOR
FANOUT0/GPIO52
FANOUT1/GPIO53
FANOUT2/GPIO54
FANIN0/GPIO56
FANIN1/GPIO57
FANIN2/GPIO58
TEMPIN0/GPIO171
TEMPIN1/GPIO172
TEMPIN2/GPIO173
TEMPIN3/TALERT_L/GPIO174
TEMP_COMM
VIN0/GPIO175
VIN1/GPIO176
VIN2/GPIO177
VIN3/GPIO178
VIN4/GPIO179
VIN5/GPIO180
VIN6/GBE_STAT3/GPIO181
VIN7/GBE_LED3/GPIO182
NC1
NC2
C
AH28
AG28
AF26
AF28
AG29
AG26
AF27
AE29
AF29
AH27
AJ27
AJ26
AH25
AH24
AG23
AH23
AJ22
AG21
AF21
AH22
AJ23
AF23
AJ24
AJ25
AG25
AH26
W5
W6
Y9
W7
V9
W8
B6
A6
A5
B5
C7
A3
B4
A4
C5
A7
B7
B8
A8
G27
Y2
ODD_PWR
TEMPIN0
R612 10K_0402_5%R612 10K_0402_5%
TEMPIN1
R613 10K_0402_5%R613 10K_0402_5%
TEMPIN2
R614 10K_0402_5%R614 10K_0402_5%
R615 10K_0402_5%R615 10K_0402_5%
GPIO175
R617 10K_0402_5%R617 10K_0402_5%
GPIO176
R618 10K_0402_5%R618 10K_0402_5%
GPIO177
R619 10K_0402_5%R619 10K_0402_5%
GPIO178
R620 10K_0402_5%R620 10K_0402_5%
GPIO179
R621 10K_0402_5%R621 10K_0402_5%
GPIO180
R622 10K_0402_5%R622 10K_0402_5%
GPIO181
R623 10K_0402_5%@R623 10K_0402_5%@
GPIO182
R624 10K_0402_5%R624 10K_0402_5%
ODD_PWR <30>
12
12
12
12
12
12
12
12
12
12
12
12
D
VIN6/GBE_STAT3/G PIO181
Enable integrate d pull-down/up and leave uncon nected
E
@
@
@
1 2
+3VS
R504 0_0603_5%
R504 0_0603_5%
R507 4.7K_0402_5%@R5 07 4.7K_0402_5 %@
1 2
R491 4.7K_0402_5%@R4 91 4.7K_0402_5 %@
+3VS
4 4
1 2
FCH_SPICS#/FSEL#
A
FCH_SPI_WP#
FCH_SPI_HOLD#
@
C784 0.1U_0402_16V4Z
C784 0.1U_0402_16V4Z
1 2
FCH_+SPI_VCC
U32
U32
1
CS#
3
WP#
7
HOLD#
4
GND
MX25L1605DM2I-12G SOP 8P
MX25L1605DM2I-12G SOP 8P
SA00002TO00
SA00002TO00
@
@
SCLK
VCC
8
6
5
SI
2
SO
FCH_SPICLK_R
FCH_SO_SPI_SI
FCH_SI_SPI_SO
B
R510 0_0402_5%@R510 0_0402_5%@
1 2
FCH_SPICLK
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010/08/20 2011/08/20
2010/08/20 2011/08/20
2010/08/20 2011/08/20
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
FCH-SATA/SPI
FCH-SATA/SPI
FCH-SATA/SPI
LA-7092P P5WE6/H6/S6
LA-7092P P5WE6/H6/S6
LA-7092P P5WE6/H6/S6
15 46Friday, October 29, 2010
15 46Friday, October 29, 2010
15 46Friday, October 29, 2010
E
0.3
0.3
0.3
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