Compal LA-7072P P0VE6, Aspire One AO522 Schematic

A

ZZZ1

ZZZ2

PCB

M/B

M/B DAZ@

DAZ@

11/18 ZZZ2 for DAZ P/N:DAZ0IV00101

1 1

ZZZ1

LA-7072P

M/B

M/B DA@

DA@

ZZZ3

LS-7072P

LED/B

LED/B DA@

DA@

ZZZ4

LS-7073P

TP/B

TP/B DA@

DA@

B

11/18 LA-7072P P/N from DA60000LA00 to DA60000LA10 LS-7072P P/N from DA40000Z300 to DA40000Z310 LS-7073P P/N from DA40000Z400 to DA40000Z410

11/22 LS-7073P P/N from DA40000Z410 to DA20000Z410

C

D

E

Compal Confidential

2 2

P0VE6 LA7072P Schematics Document

AMD Ontario Processor with DDRIII + Hudson M1

10.1" M/B

3 3

2010-11-18

Rev : 1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/08/12 2012/08/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

P0VE6 Schematics

1 36Monday, November 22, 2010

E

1.0

A

Compal Confidential

B

C

D

E

Model Name : P0VE6 / P0VH6

Brazos Platform

File Name : LA-7072P

1 1

HDMI RGB LVDS

HDMI Conn.

Page 9

2 2

Fan Circuit

PWM

D-Sub Conn.

Page 10

Page 26

LVDS Conn.

Page 8

PCI-Express X3

100MHz

Port 1

WWAN

JMINI1

WLAN

JMINI2

Media processor Wireless Card

Port 1

Page 19

3 3

Port 3 Port 2

Page 20

PCIE Gen1 2.5GT/S

Port 2Port 3

LAN(10/100mbE)

AR8152

Page 17

RJ-45

Page 17

AMD

Ontario FT1

APU

BGA 413-Ball

19mm X 19mm

UMI x4 Gen.1

2.5GT/s per Lane

AMD

Hudson M1

FCH

BGA 605-Ball

23mm X 23mm

Page 11,12,13,14,15

LPC

33MHz

ENE KB930

Page 25

Page 4,5,6

Memory Bus (DDRIII)

Single Channel

1.5V DDRIII 800/1066

6.4G/8.5G

100M/133M

USB Conn.x1

(Right Side) Port 2

Page 24

USB

HD Audio

SATA

Gen1 1.5GT/S ,Gen2 3GT/S

USB Conn.x2

(Left Side) Port 0, 1

3.3V 48MHz

3.3V 24MHz

HDD

Small Board

204 Pin DDRIII SO-DIMM x1

BANK 0, 1, 2, 3

Page 7

Camera Bluetooth

Port 5

Page 24 Page 19 Page 18

Page 8

100MHz

Port 7

Card Reader

ENE 6250 / 6252

Port 6

3G Card

Port 3

(2.5") Port 0

Page 21

HDA Codec+AMP

CX20584

Page 19

Page 16

LED/B

LS-7072P

TP BTN/B

LS-7073P

HP Jack x1 MIC Jack x1

Page 23

RTC Ckt.

Page 11

BIOS ROM

4 4

Power Button

Page 22

DC/DC Interface Ckt.

Page 27

A

B

2MB

Page 26

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/12 2012/08/12

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Block Diagrams

P0VE6 Schematics

2 36Monday, November 15, 2010

E

1.0

A

Voltage Rails

Power Plane Description

VIN

B+

+APU_CORE

1 1

2 2

+APU_CORE_NB 1.0V switched power rail ON OFF

+1.5V

+0.75VS 0.75VS switched power rail for DDR terminator

+1.05VS

+1.1VS 1.1VS switched power rail ON OFF OFF

+1.8VS 1.8V switched power rail

+3VALW

+3VS

+1.5VS 1.5VS switched power rail ON OFF OFF

+5VALW

+5VS

+VSB VSB always on power rail ON ON*

+RTCBATT

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

EC SM Bus1 address

Device

Smart Battery

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU (0.7-1.2V)

1.5V power rail for CPU VDDIO and DDRIII

1.05V switched power rail for NB VDDC & VGA

3.3V always on power rail

3.3V switched power rail

5V always on power rail

5V switched power rail

RTC power

EC SM Bus2 address

Address Address

0001-011xb

HEX

16H

Device

SB-TSI

B

S1 S3 S5

N/A N/A N/A

ON OFF

ON

ON OFF OFF

ON

1001-100xb

N/AN/AN/A

OFF

ON

OFF

ON ON*

ON ON*ON+1.1VALW 1.1V always on power rail

OFF

ON ON*

OFF

OFFON

ONON

HEX

98H

C

FCH Hudson-M1 USB Port List

USB1.1

Port0

Port1

USB2.0

Port0

Port1

Port2

Port3

Port4

Port5

Port6

Port7

Port8

Port9

Port10

Port11

Port12

Port13

NC

Right USB2

Right USB3

WWAN

SIM

USB Camera

CardReader

BT

WiMax

NC

D

Brazos PCIE Port List

PCIE0

APUFCH

PCIE1

PCIE2

PCIE3

PCIE0

PCIE1

PCIE2

PCIE3

NC

WWAN

LANLeft USB1

WLAN

FCH Hudson-M1 SATA Port List

SATA0

SATA1

SATA2

SATA3

SATA4

SATA5

HDD

NC

E

SM Bus Controller 0

Device Address

APU SIC/SID (FCH_SMB3)

H_THERMTRIP# (FCH_ALERT#)

3 3

SM Bus Controller 1

Device Address HEX

DDR DIMM1 (FCH_SMB0)

(FCH_SMB1 ~ FCH_SMB4, SMB_AL ERT#)

HEX

(FCH_SMB0)

1001-000xb

90

Board ID / SKU ID Table for AD channel

Vcc +3VALW

Board ID

0

*

1 2 3 4 5 6 7 NC

100K +/- 5%Ra

Rb V min

AD_BID

0

8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

0 V

V typ

AD_BID

V

AD_BID

0 V 0 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

max

PCB Revision

0.1

0.2

SMBUS Control Table

BOM Structure

EC_SMB_CK1

HDMI@ : HDMI function BT@ : BT function CONN@ : Connetors 45@ : 45 Level 3G@ : 3G function

4 4

3G_MP@: 3G & Media processor function

CHARGE@: Charge BATT

NONCHARGE@: nonCharge BATT

A

B

EC_SMB_DA1

EC_SMB_CK2 EC_SMB_DA2

HDMI_DATA HDMI_CLK

EDID_DATA EDID_CLK

FCH_SMDAT0 FCH_SMCLK0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Source BATT DIMM MINI Card LCD DDC ROM HDMI DDC ROM APU

KB930

V

KB930

APU FT1

FCH M1

Compal Secret Data

2010/08/12 2012/08/12

Compal Secret Data

Deciphered Date

VV

D

V

Title

Size Document Number Rev

B

Date: Sheet of

V

Compal Electronics, Inc.

Notes List

P0VE6 Schematics

V

1.0

3 36Monday, November 15, 2010

E

1.0

5

U1

S IC ONTARIO ZMC50AFPB22GT 1G BGA 413P ABO !

+1.8VS

D D

R3 1K_0402_5%R3 1K_0402_5%

1 2

R4 1K_0402_5%R4 1K_0402_5%

1 2

R8 510_0402_1%R8 510_0402_1%

1 2

R6 1K_0402_5%R6 1K_0402_5%

1 2

SA00004KD40

C50@

APU_SVC APU_SVD

TEST_25_L

TEST36

10/08 Add U1(C50@) SA00004BM30 S IC ONTARIO ZM101034B2238 1G BGA ABO!

11/03 APU P/N update to SA00004DF60(C30) SA00004BM80(C50)

11/29 Change U1 from SA00004BM80 to SA00004KD40

+3VS

R10 10K_0402_5%R10 10K_0402_5%

1 2

R11 10K_0402_5%R11 10K_0402_5%

1 2

R13 1K_0402_5%R13 1K_0402_5%

1 2

R14 1K_0402_5%R14 1K_0402_5%

1 2

R16 1K_0402_5%R16 1K_0402_5%

1 2

R17 1K_0402_5%R17 1K_0402_5%

1 2

C405 100P_0402_50V8JC405 100P_0402_50V8J

1 2

10/05 Add 100p(C405) on LDT_RST#

HDMI_DATA

HDMI_CLK APU_PROCHOT# APU_ALERT#_R

APU_SIC APU_SID

LDT_RST#

Power Circuit

9/9 Change R24 from @ to mount R26 from mount to @

C C

R23 0_0402_5%@R23 0_0402_5%@

FCH_PROCHOT#<11>

EC_PROCHOT#<25>

1 2

R27 0_0402_5%R27 0_0402_5%

1 2

9/15 Change R24 from mount to @

APU_PROCHOT#

Connection to EC, FCH input need to pull-down

Power Circuit

+3VS

12

R32

R32 10K_0402_5%

10K_0402_5%

R33

1K_0402_5%

B B

If FCH internal pull-up disabl ed, level-shift er could be del eted. Need BIOS to di sable internal pull-up!!

DMN66D0LDW-7_SOT363-6

A A

DMN66D0LDW-7_SOT363-6

1K_0402_5%

APU_THERMTRIP#

S

@

S

@

B

2

1 2

Q2A

Q2B

Q1

E

3 1

C

MMBT3904_NL_SOT23-3

1 2

R34 0_0402_5%@R34 0_0402_5%@

+3VS

12

R39

R39 10K_0402_5%

10K_0402_5%

@

G

2

EC_SMB_DAAPU_SID

61

D

1 2

R49 0_0402_5%R49 0_0402_5%

G

5

EC_SMB_CKAPU_SIC

34

D

1 2

R52 0_0402_5%R52 0_0402_5%

5

R47 0_0402_5%

R48 0_0402_5%R48 0_0402_5%

8/19 Change Q2A Q2B SB00000DH00 (S TR DMN66D0LDW-7 2N SOT363-6)

R50 0_0402_5%

R51 0_0402_5%R51 0_0402_5%

Power Circuit

9/6 Add R379, R380 for APU_VDDNB_RUN_FB_L

H_THERMTRIP# <12>

2N7002DW-T/R7

Vgs(th): min 1.0V

If Q8 or R429, R432 implemented, EC side pull-up need to be mounted

@

1 2

@

1 2

Typ 1.6V Max 2.0V

FCH_SID

EC_SMB_DA2

FCH_SIC

EC_SMB_CK2

4

10/27 APU P/N update to B0 stepping

C1 .1U_0402_16V7KC1 .1U_0402_16V7K

HDMI_TX2P<9> HDMI_TX2N<9>

HDMI_TX1P<9> HDMI_TX1N<9>

HDMI_TX0P<9> HDMI_TX0N<9>

HDMI_CLKP<9> HDMI_CLKN<9>

APU_ALERT#_FCH<13> APU_ALERT#_EC<25>

APU_CLK<11> APU_CLK#<11>

DISP_CLK<11> DISP_CLK#<11>

APU_SVC<35>

APU_SVD<35>

APU_VDDNB_RUN_FB_ H<35> APU_VDD0_RUN_FB_H<35>

APU_VDD0_RUN_FB_L<35>

FCH_SID <12>

EC_SMB_DA2 <25>

FCH_SIC <12>

EC_SMB_CK2 <25>

4

1 2

C6 .1U_0402_16V7KC6 .1U_0402_16V7K

1 2

C2 .1U_0402_16V7KC2 .1U_0402_16V7K

1 2

C3 .1U_0402_16V7KC3 .1U_0402_16V7K

1 2

C7 .1U_0402_16V7KC7 .1U_0402_16V7K

1 2

C8 .1U_0402_16V7KC8 .1U_0402_16V7K

1 2

C4 .1U_0402_16V7KC4 .1U_0402_16V7K

1 2

C5 .1U_0402_16V7KC5 .1U_0402_16V7K

1 2

LVDS_A2<8> LVDS_A2#<8>

LVDS_A1<8> LVDS_A1#<8>

LVDS_A0<8> LVDS_A0#<8>

LVDS_ACLK<8> LVDS_ACLK#<8>

LDT_RST#<11> APU_PWRGD<11>

R24 0_0402_5%@R24 0_0402_5 %@

1 2

R26 0_0402_5%@R26 0_0402_5 %@

1 2

T9 PADT9 PAD T10PADT10PAD

Close to APU

T14PADT14PAD

R379 0_0402_5%R379 0_0402_5%

1 2

R380 0_0402_5%R380 0_0402_5%

1 2

T0 FCH

TO EC

T0 FCH

TO EC

3

2

10/08 Change U1 P/N to SA00004DF20 S IC ONTARIO ZM121034B1238 1.2G BGA ABO!

SA00004DF60

U1B

HDMI_TX2P_C HDMI_TX2N_C

HDMI_TX1P_C HDMI_TX1N_C

HDMI_TX0P_C HDMI_TX0N_C

HDMI_CLKP_C HDMI_CLKN_C

APU_SIC APU_SID

APU_PROCHOT# APU_THERMTRIP#

APU_ALERT#_R

APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBRDY APU_DBREQ#

8/31 Change U1 P/N to SA00004DF00 S IC ONTARIO ZM121034B1238 1.2G BGA 413P

U1B

A8

TDP1_TXP0

B8

TDP1_TXN0

B9

TDP1_TXP1

A9

TDP1_TXN1

D10

TDP1_TXP2

C10

TDP1_TXN2

A10

TDP1_TXP3

B10

TDP1_TXN3

B5

LTDP0_TXP0

A5

LTDP0_TXN0

D6

LTDP0_TXP1

C6

LTDP0_TXN1

A6

LTDP0_TXP2

B6

LTDP0_TXN2

D8

LTDP0_TXP3

C8

LTDP0_TXN3

V2

CLKIN_H

V1

CLKIN_L

D2

DISP_CLKIN_H

D1

DISP_CLKIN_L

J1

SVC

J2

SVD

P3

SIC

P4

SID

T3

RESET_L

T4

PWROK

U1

PROCHOT_L

U2

THERMTRIP_L

T2

ALERT_L

N2

TDI

N1

TDO

P1

TCK

P2

TMS

M4

TRST_L

M3

DBRDY

M1

DBREQ_L

F4

VDDCR_NB_SENSE

G1

VDDCR_CPU_SENSE

F3

VDDIO_MEM_S_SENSE

F1

VSS_SENSE

B4

RSVD_1

W11

RSVD_2

V5

RSVD_3

S IC ONTARIO 2M121134B1240 1.2G BGA 413P ABO !

C30@

DISPLAYPORT 1

DISPLAYPORT 0

CLK

SER

JTAG CTRL

DP MISC

VGA DAC

TEST

DP_ZVSS

DP_BLON

DP_DIGON

DP_VARY_BL

TDP1_AUXP

TDP1_AUXN

TDP1_HPD

LTDP0_AUXP LTDP0_AUXN

LTDP0_HPD

DAC_RED

DAC_REDB

DAC_GREEN

DAC_GREENB

DAC_BLUE

DAC_BLUEB

DAC_HSYNC DAC_VSYNC

DAC_SCL DAC_SDA

DAC_ZVSS

TEST14 TEST15 TEST16 TEST17 TEST18 TEST19

TEST25_H

TEST25_L

TEST28_H

TEST28_L

TEST31

TEST33_H

TEST33_L

TEST34_H

TEST34_L

TEST35 TEST36 TEST37

TEST38

DMAACTIVE_L

TEST4 TEST5 TEST6

DP_ZVSS

H3

G2 H2 H1

HDMI_CLK

B2

HDMI_DATA

C2

C1

EDID_CLK

A3

EDID_DATA

B3

LTDP0_HPD

D3

C12

R12 150_0402_1%R12 150_0402_1%

D13 A12 B12 A13 B13

E1 E2

F2 D4

D12

R1 R2 R6 T5 E4 K4 L1 L2 M2 K1 K2 L5 M5 M21 J18 J19 U15 T15 H4 N5 R5

K3 T1

1 2

R15 150_0402_1%R15 150_0402_1%

1 2

R18 150_0402_1%R18 150_0402_1%

1 2

DAC_ZVSS

TEST15

TEST18 TEST19 TEST25_H TEST_25_L

TEST31 TEST33_H TEST33_L

TEST35 TEST36 TEST37

R31 1K_0402_5%R31 1K_0402_5%

PADT2PAD

PADT8PAD

PAD

1 2

9/17 Remove JHDT1 R40, R44, R45, R46 , Add T26~T32

AMD Debug

9/20 Delete R41~R43

+1.8VS

1K_0402_5%

R37

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/08/12 2012/08/12

APU_TRST#

12

Compal Secret Data

Deciphered Date

2

1

Display

LVDS

eDP

+3VS

R1 150_0402_1%R1 150_0402_1%

1 2

APU_ENBKL <25> APU_ENVDD <8> APU_BLPWM <8>

HDMI_CLK <9>

HDMI_DATA <9>

HDMI_DET <9>

EDID_CLK <8>

R9 100K_0402_5%R9 100K_0402_5%

1 2

R19 499_0402_1%R19 499_0402_1%

1 2

T2

R20 1K_0402_5%R20 1K_0402_5%

1 2

R21 1K_0402_5%R21 1K_0402_5%

1 2

R22 1K_0402_5%R22 1K_0402_5%

1 2

R25 510_0402_1%R25 510_0402_1%

1 2

T8

C9 0.1U_0402_16V4ZC9 0.1U_0402_16V4Z

1 2

C10 0.1U_0402_16V4ZC10 0.1U_0402_16V4Z

1 2

R30 1K_0402_5%@R30 1K_0402_5%@

1 2

R386 1K_0402_5%R386 1K_0402_5%

1 2

T13

EDID_DATA <8>

DAC_RED <10>

DAC_GRN <10>

DAC_BLU <10>

CRT_HSYNC <10> CRT_VSYNC <10>

CRT_DDC_CLK <10> CRT_DDC_DATA <10>

10/01 Remove T1,T3~T7,T11,T12,T31,T32

R9 R352

mount

*

R28 51_0402_1%R28 51_0402_1% R29 51_0402_1%R29 51_0402_1%

@

8/25 Pull-up 100k(@ R352) to +3VS on LTDP0_HPD for eDP

R352 100K_0402_5%@R352 100K_04 02_5%@

1 2

1 2 1 2

+1.8VS

mount

@

9/9 Add R386 (1k@) to +1.8VS on TEST35

9/13 Change R30 from mount to @, R386 from @ to mount (AMD Recommend)

T29

PAD

T30

PAD

ALLOW_STOP# <11>APU_VDDNB_RUN_FB_ L<35>

+1.8VS

APU_TCK

APU_TMS

APU_TDI

APU_TDO

APU_PWRGD

LDT_RST#

APU_DBRDY

APU_DBREQ#

Custom

Date: Sheet of

R35 1K_0402_5%R35 1K_0402_5%

R36 1K_0402_5%R36 1K_0402_5%

R38 1K_0402_5%R38 1K_0402_5%

R5 300_0402_5%R5 300_0402_5%

R7 300_0402_5%R7 300_0402_5%

R2 300_0402_5%R2 300_0402_5%

Compal Electronics, Inc.

Title

Size Document Number Rev

Compal Electronics, Inc.

12

FT1 CTRL/DP/CRT

P0VE6 Schematics

1

+1.8VS

4 36Monday, November 29, 2010

1.0

A

U1E

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6

4 4

3 3

2 2

DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDR_A_BS0<7> DDR_A_BS1<7> DDR_A_BS2<7>

DDR_A_DQS0<7> DDR_A_DQS#0<7> DDR_A_DQS1<7> DDR_A_DQS#1<7> DDR_A_DQS2<7> DDR_A_DQS#2<7> DDR_A_DQS3<7> DDR_A_DQS#3<7> DDR_A_DQS4<7> DDR_A_DQS#4<7> DDR_A_DQS5<7> DDR_A_DQS#5<7> DDR_A_DQS6<7> DDR_A_DQS#6<7> DDR_A_DQS7<7> DDR_A_DQS#7<7>

DDR_A_CLK0<7> DDR_A_CLK#0<7> DDR_A_CLK1<7> DDR_A_CLK#1<7>

DDR_RST#<7>

DDR_EVENT#< 7>

DDR_CKE0<7> DDR_CKE1<7>

DDR_A_ODT0< 7> DDR_A_ODT1< 7>

DDR_CS0_DIMMA#<7> DDR_CS1_DIMMA#<7>

DDR_A_RAS#<7> DDR_A_CAS#<7> DDR_A_WE#<7>

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1

DDR_RST# DDR_EVENT#

DDR_CKE0 DDR_CKE1

DDR_A_ODT0 DDR_A_ODT1

DDR_CS0_DIMMA# DDR_CS1_DIMMA#

DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

U1E

R17

M_ADD0

H19

M_ADD1

J17

M_ADD2

H18

M_ADD3

H17

M_ADD4

G17

M_ADD5

H15

M_ADD6

G18

M_ADD7

F19

M_ADD8

E19

M_ADD9

T19

M_ADD10

F17

M_ADD11

E18

M_ADD12

W17

M_ADD13

E16

M_ADD14

G15

M_ADD15

R18

M_BANK0

T18

M_BANK1

F16

M_BANK2

D15

M_DM0

B19

M_DM1

D21

M_DM2

H22

M_DM3

P23

M_DM4

V23

M_DM5

AB20

M_DM6

AA16

M_DM7

A16

M_DQS_H0

B16

M_DQS_L0

B20

M_DQS_H1

A20

M_DQS_L1

E23

M_DQS_H2

E22

M_DQS_L2

J22

M_DQS_H3

J23

M_DQS_L3

R22

M_DQS_H4

P22

M_DQS_L4

W22

M_DQS_H5

V22

M_DQS_L5

AC20

M_DQS_H6

AC21

M_DQS_L6

AB16

M_DQS_H7

AC16

M_DQS_L7

M17

M_CLK_H0

M16

M_CLK_L0

M19

M_CLK_H1

M18

M_CLK_L1

N18

M_CLK_H2

N19

M_CLK_L2

L18

M_CLK_H3

L17

M_CLK_L3

L23

M_RESET_L

N17

M_EVENT_L

F15

M_CKE0

E15

M_CKE1

W19

M0_ODT0

V15

M0_ODT1

U19

M1_ODT0

W15

M1_ODT1

T17

M0_CS_L0

W16

M0_CS_L1

U17

M1_CS_L0

V16

M1_CS_L1

U18

M_RAS_L

V19

M_CAS_L

V17

M_WE_L

S IC ONTARIO 2M121134B1240 1.2G BGA 413P ABO !

C30@

DDR SYSTEM MEMORY

B

M_DATA0 M_DATA1 M_DATA2 M_DATA3 M_DATA4 M_DATA5 M_DATA6 M_DATA7

M_DATA8

M_DATA9 M_DATA10 M_DATA11 M_DATA12 M_DATA13 M_DATA14 M_DATA15

M_DATA16 M_DATA17 M_DATA18 M_DATA19 M_DATA20 M_DATA21 M_DATA22 M_DATA23

M_DATA24 M_DATA25 M_DATA26 M_DATA27 M_DATA28 M_DATA29 M_DATA30 M_DATA31

M_DATA32 M_DATA33 M_DATA34 M_DATA35 M_DATA36 M_DATA37 M_DATA38 M_DATA39

M_DATA40 M_DATA41 M_DATA42 M_DATA43 M_DATA44 M_DATA45 M_DATA46 M_DATA47

M_DATA48 M_DATA49 M_DATA50 M_DATA51 M_DATA52 M_DATA53 M_DATA54 M_DATA55

M_DATA56 M_DATA57 M_DATA58 M_DATA59 M_DATA60 M_DATA61 M_DATA62 M_DATA63

M_VREF

M_ZVDDIO_MEM_S

B14 A15 A17 D18 A14 C14 C16 D16

C18 A19 B21 D20 A18 B18 A21 C20

C23 D23 F23 F22 C22 D22 F20 F21

H21 H23 K22 K21 G23 H20 K20 K23

N23 P21 T20 T23 M20 P20 R23 T22

V20 V21 Y23 Y22 T21 U23 W23 Y21

Y20 AB22 AC19 AA18 AA23 AA20 AB19 Y18

AC17 Y16 AB14 AC14 AC18 AB18 AB15 AC15

M23

M22

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7

DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15

DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23

DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31

DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39

DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47

DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55

DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

+MEM_VREF

+M_ZVDDIO

R55

39.2_0402_1%

12

DDR_A_MA[0..15]

DDR_A_DM[0..7]

+1.05VS

UMI_RX0P<11> UMI_RX0N<1 1>

UMI_RX1P<11> UMI_RX1N<1 1>

UMI_RX2P<11> UMI_RX2N<1 1>

UMI_RX3P<11> UMI_RX3N<1 1>

+1.5V

DDR_A_D[0..63]

Less than 1"

C

DDR_A_D[0..63] <7>

DDR_A_MA[0..15] <7>

DDR_A_DM[0..7] <7>

1 2

R53 2 K_0402_1%R53 2K_0402_1%

P_ZVDD_10

8/22 Delete C11~C18 (No VGA)

9/6 Change PCI-E from FCH to APU

9/6 Update PCI-E port List

9/15 Change PCI-E from APU to FCH

U1A

AA6

P_GPP_RXP0

Y6

P_GPP_RXN0

AB4

P_GPP_RXP1

AC4

P_GPP_RXN1

AA1

P_GPP_RXP2

AA2

P_GPP_RXN2

Y4

P_GPP_RXP3

Y3

P_GPP_RXN3

Y14

P_ZVDD_10

AA12

P_UMI_RXP0

Y12

P_UMI_RXN0

AA10

P_UMI_RXP1

Y10

P_UMI_RXN1

AB10

P_UMI_RXP2

AC10

P_UMI_RXN2

AC7

P_UMI_RXP3

AB7

P_UMI_RXN3

S IC ONTARIO 2M121134B1240 1.2G BGA 413P ABO !

C30@

PCIE I/F

UMI I/F

P_GPP_TXP0 P_GPP_TXN0

P_GPP_TXP1 P_GPP_TXN1

P_GPP_TXP2 P_GPP_TXN2

P_GPP_TXP3 P_GPP_TXN3

P_UMI_TXP0 P_UMI_TXN0

P_UMI_TXP1 P_UMI_TXN1

P_UMI_TXP2 P_UMI_TXN2

P_UMI_TXP3 P_UMI_TXN3

P_ZVSS

D

AB6 AC6

AB3 AC3

Y1 Y2

V3 V4

AA14

AB12 AC12

AC11 AB11

AA8 Y8

AB8 AC8

P_ZVSS

R54 1.27K_0402_1%R54 1.27K_0402_1%

1 2

Less than 1"

UMI_TX0P_C UMI_TX0N_C

UMI_TX1P_C UMI_TX1N_C

UMI_TX2P_C UMI_TX2N_C

UMI_TX3P_C UMI_TX3N_C

C19 .1U_0402_16V7KC19 .1U_0402_16V7K C20 .1U_0402_16V7KC20 .1U_0402_16V7K

C21 .1U_0402_16V7KC21 .1U_0402_16V7K C22 .1U_0402_16V7KC22 .1U_0402_16V7K

C23 .1U_0402_16V7KC23 .1U_0402_16V7K C24 .1U_0402_16V7KC24 .1U_0402_16V7K

C25 .1U_0402_16V7KC25 .1U_0402_16V7K C26 .1U_0402_16V7KC26 .1U_0402_16V7K

1 2 1 2

E

UMI_TX0P <11> UMI_TX0N <1 1>

UMI_TX1P <11> UMI_TX1N <1 1>

UMI_TX2P <11> UMI_TX2N <1 1>

UMI_TX3P <11> UMI_TX3N <1 1>

9/11 Delete DDR Signal link to JDIMM2

+1.5V

R57

1 2

1K_0402_5%

1 1

DDR_EVENT#

A

R56

1K_0402_1%

R58

1K_0402_1%

1 2

1

C27

1000P_0402_50V7K

2

1 2

Place within 1000 mils to APU 20100526

B

C28

+MEM_VREF

1

0.1U_0402_16V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/08/12 2012/08/12

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

FT1 DDRIII/UMI/PCIE

P0VE6 Schematics

E

5 36Wednesday, November 17, 2010

1.0

5

4

3

2

1

+APU_CORE

1

D D

C31

2

1

C43

2

1

C52

2

+APU_CORE_NB

C C

C68

C75

C84

B B

1

C29

2

10U_0603_6.3V6M

1

C44

2

1U_0402_6.3V6K

1

C53

2

.1U_0402_16V7K

1

C69

2

10U_0603_6.3V6M

1

C76

2

1U_0402_6.3V6K

1

C85

2

.1U_0402_16V7K

POWER

1

C92

@

2

10U_0603_6.3V6M

+APU_CORE

1

+

C99

C99 470U_X_2VM_R6M

470U_X_2VM_R6M

2

SGA00003K00

A A

SGA20331E10

10U_0603_6.3V6M

1U_0402_6.3V6K

.1U_0402_16V7K

10U_0603_6.3V6M

1U_0402_6.3V6K

.1U_0402_16V7K

+1.05VS

1

+

C93

C93 220U_D2_2VY_R15M

220U_D2_2VY_R15M

SGA00004L00

2

1

+

2

+APU_CORE_NB

1

+

C114

2

1

C32

2

1

C45

2

1

C54

2

1

C70

2

1

C77

2

1

C86

2

C100

C100 470U_X_2VM_R6M

470U_X_2VM_R6M

330U_D2_2V_Y

1

C41

2

10U_0603_6.3V6M

1

C46

2

1U_0402_6.3V6K

1

C55

2

.1U_0402_16V7K

1

C71

2

10U_0603_6.3V6M

1

C78

2

1U_0402_6.3V6K

1

C87

2

.1U_0402_16V7K

9/20 Change C93 to SGA00004L00

8/25 Change C101 from mount to @

9/15 Remove C101, C113

9/15 Change C99,C100 to 470U(SGA00003K00)

1

C102

@

2

Near CPU Socket

1

C117

2

Near CPU Socket Near CPU Socket

5

1

C42

2

10U_0603_6.3V6M

1U_0402_6.3V6K

1

C56

2

.1U_0402_16V7K

1

C72

2

10U_0603_6.3V6M

1

C79

2

1U_0402_6.3V6K

.1U_0402_16V7K

1

C30

2

10U_0603_6.3V6M

.1U_0402_16V7K

10U_0603_6.3V6M

1U_0402_6.3V6K

10U_0603_6.3V6M

1

C47

2

180P_0402_50V8J

1

C80

2

180P_0402_50V8J

POWER

10U_0603_6.3V6M

SGA20331E10

4500 mA

1

C33

2

1

C48

2

1

C81

2

330U_D2_2V_Y

+APU_CORE

10U_0603_6.3V6M

8000 mA

+APU_CORE_NB

180P_0402_50V8J

2000 mA

+1.5V

180P_0402_50V8J

8/22 Change C111~C113 from E-Cap to Poly-Cap (SGA20331E10)

8/25 Change C111 from poly-cap to E-cap (SF000002Z00)

9/11 Change C111 to SGA20331E10

C111

+1.5V

1

C82

2

10U_0603_6.3V6M

1

C88

2

1U_0402_6.3V6K

1

C94

2

.1U_0402_16V7K

+1.5V +1.8VS

POWER POWER

1

2

1

+

C115

2

22U_0805_6.3V6M

U1C

E5

VDDCR_CPU_1

E6

VDDCR_CPU_2

F5

VDDCR_CPU_3

F7

VDDCR_CPU_4

G6

VDDCR_CPU_5

G8

VDDCR_CPU_6

H5

VDDCR_CPU_7

H7

VDDCR_CPU_8

J6

VDDCR_CPU_9

J8

VDDCR_CPU_10

L7

VDDCR_CPU_11

M6

VDDCR_CPU_12

M8

VDDCR_CPU_13

N7

VDDCR_CPU_14

R8

VDDCR_CPU_15

E8

VDDCR_NB_1

E11

VDDCR_NB_2

E13

VDDCR_NB_3

F9

VDDCR_NB_4

F12

VDDCR_NB_5

G11

VDDCR_NB_6

G13

VDDCR_NB_7

H9

VDDCR_NB_8

H12

VDDCR_NB_9

K11

VDDCR_NB_10

K13

VDDCR_NB_11

L10

VDDCR_NB_12

L12

VDDCR_NB_13

L14

VDDCR_NB_14

M11

VDDCR_NB_15

M12

VDDCR_NB_16

M13

VDDCR_NB_17

N10

VDDCR_NB_18

N12

VDDCR_NB_19

N14

VDDCR_NB_20

P11

VDDCR_NB_21

P13

VDDCR_NB_22

G16

VDDIO_MEM_S_1

G19

VDDIO_MEM_S_2

E17

VDDIO_MEM_S_3

J16

VDDIO_MEM_S_4

L16

VDDIO_MEM_S_5

L19

VDDIO_MEM_S_6

N16

VDDIO_MEM_S_7

R16

VDDIO_MEM_S_8

R19

VDDIO_MEM_S_9

W18

VDDIO_MEM_S_10

U16

VDDIO_MEM_S_11

S IC ONTARIO 2M121134B1240 1.2G BGA 413P ABO !

C30@

1

C83

2

10U_0603_6.3V6M

1U_0402_6.3V6K

.1U_0402_16V7K

C112

330U_D2_2V_Y

1

C90

2

1

C96

2

1

+

2

1

C89

2

1

C95

2

SGA20331E10

Near CPU Socket

4

2000 mA

TSense/PLL/DP/PCIE/IO

VDD_18_1 VDD_18_2 VDD_18_3 VDD_18_4 VDD_18_5 VDD_18_6

CPU CORE

VDD_18_7

DAC

VDD_18_DAC

GPU AND NB CORE

POWER

DIS PLL

VDDPL_10

PCIE/IO/DDR3 Phy

VDD_10_1 VDD_10_2 VDD_10_3 VDD_10_4

DDR3

DP Phy/IO

VDD_33

1

C91

2

1U_0402_6.3V6K

.1U_0402_16V7K

1U_0402_6.3V6K

1

C97

2

180P_0402_50V8J

1

C116

@

2

10U_0603_6.3V6M

+VDD_18

U8 W8 U6 U9 W6 T7 V7

W = 20 mil / Spcae = 20 mil

W9

W = 15 mil / Spcae = 20 mil

U11

5500 mA

U13 W13 V12 T12

500 mA

A4

1

C98

2

180P_0402_50V8J

3

1

C34

2

+VDD_18_DAC

1

C49

2

+VDDL_10

1

C57

2

+VDD_10

1

C61

2

+VDD_33

1

C73

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

1

C35

2

180P_0402_50V8J

1

C50

2

180P_0402_50V8J

1

C58

2

180P_0402_50V8J

1

C62

2

180P_0402_50V8J

1

C74

2

.1U_0402_16V7K

1

C36

C37

2

1U_0402_6.3V6K

.1U_0402_16V7K

1

C51

2

10U_0603_6.3V6M

1U_0402_6.3V6K

1

C59

C60

2

1U_0402_6.3V6K

.1U_0402_16V7K

1

C64

C63

2

.1U_0402_16V7K

R333

1 2

0_0603_5%

1U_0402_6.3V6K

8/22 Reserve R333 ( 0 ohm 0603 )

2010/08/12 2012/08/12

1

C38

2

1U_0402_6.3V6K

L2

FBMA-L11-201209-221LMA30T_0805

10U_0603_6.3V6M

1

C65

2

1U_0402_6.3V6K

+3VS

1

C39

C40

2

1U_0402_6.3V6K

+1.8VS

12

FBMA-L11-201209-221LMA30T_0805

1

C67

C66

2

1U_0402_6.3V6K

10U_0603_6.3V6M

Compal Secret Data

Deciphered Date

10U_0603_6.3V6M

8/25 Change +1.0VS to +1.05VS

L3

10U_0603_6.3V6M

+1.8VS

L1

12

FBMA-L11-201209-221LMA30T_0805

+1.05VS

12

L4

12

FBMA-L11-201209-221LMA30T_0805

2

U1D

A7

VSS_1

B7

VSS_2

B11

VSS_3

B17

VSS_4

B22

VSS_5

C4

VSS_6

D5

VSS_7

D7

VSS_8

D9

VSS_9

D11

VSS_10

D14

VSS_11

B15

VSS_12

D17

VSS_13

D19

VSS_14

E7

VSS_15

E9

VSS_16

E12

VSS_17

E20

VSS_18

F8

VSS_19

F11

VSS_20

F13

VSS_21

G4

VSS_22

G5

VSS_23

G7

VSS_24

G9

VSS_25

G12

VSS_26

G20

VSS_27

G22

VSS_28

H6

VSS_29

H11

VSS_30

H13

VSS_31

J4

VSS_32

J5

VSS_33

J7

VSS_34

J20

VSS_35

K10

VSS_36

K14

VSS_37

L4

VSS_38

L6

VSS_39

L8

VSS_40

L11

VSS_41

L13

VSS_42

L20

VSS_43

L22

VSS_44

M7

VSS_45

N4

VSS_46

N6

VSS_47

N8

VSS_48

N11

VSS_49

S IC ONTARIO 2M121134B1240 1.2G BGA 413P ABO !

By case (Along split)

+1.5V

1

C103

2

.1U_0402_16V7K

1

C104

C105

2

.1U_0402_16V7K

Title

Size Document Number Rev

C

Date: Sheet of

N13

VSS_50

N20

VSS_51

N22

VSS_52

P10

VSS_53

P14

VSS_54

R4

VSS_55

R7

VSS_56

R20

VSS_57

T6

VSS_58

T9

VSS_59

T11

VSS_60

T13

VSS_61

U4

VSS_62

U5

VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97

VSSBG_DAC

C107

180P_0402_50V8J

U7 U12 U20 U22 V8 V9 V11 V13 W1 W2 W4 W5 W7 W12 W20 Y5 Y7 Y9 Y11 Y13 Y15 Y17 Y19 AA4 AA22 AB2 AB5 AB9 AB13 AB17 AB21 AC5 AC9 AC13 A11

1

C109

C108

2

180P_0402_50V8J

GND

1

C106

2

180P_0402_50V8J

Compal Electronics, Inc.

P07-FT1 PWR/VSS

P0VE6 Schematics

1

6 36Wednesday, November 17, 2010

1

C110

2

180P_0402_50V8J

1.0

5

4

3

2

1

+1.5V

3500 mA

DDR_A_D4 DDR_A_D5

DDR_A_D6 DDR_A_D7

DDR_A_D12 DDR_A_D13

DDR_A_DM1

DDR_A_D14 DDR_A_D15

DDR_A_D20 DDR_A_D21

DDR_A_DM2

DDR_A_D22 DDR_A_D23

DDR_A_D28 DDR_A_D29

DDR_A_D30 DDR_A_D31

R397

1 2

100_0402_1%

DDR_A_MA15 DDR_A_MA14

DDR_A_MA11 DDR_A_MA7

DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

DDR_A_D36 DDR_A_D37

DDR_A_DM4

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_DM6

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_D62 DDR_A_D63

DDR_A_DQS#0 <5> DDR_A_DQS0 <5>

DDR_RST# <5>

8/19 Change JDIMM1 to SP07000LT00(LCN_DAN06-K4406-0103_204P)

9/13 Update JDIMM1 to LCN_DAN06-K4406-0102_204P

9/23 Reserve R396,R397 on CKE0 & CKE1(S3 hang Issue)

DDR_A_DQS#3 <5> DDR_A_DQS3 <5>

+1.5V

DDR_CKE1 <5>

2

C120

1

0.1U_0402_16V4Z

10/11 Change R396 R397 from @ to mount (For A1 APU,B0 APU no Need)

DDR_A_CLK1 <5> DDR_A_CLK#1 <5>

DDR_A_BS1 <5> DDR_A_RAS# <5>

DDR_CS0_DIMMA# <5> DDR_A_ODT0 <5>

DDR_A_ODT1 <5>

W=20mil

+VREF_CA

+0.75VS

1

C132

2

DDR_A_DQS#5 <5> DDR_A_DQS5 <5>

DDR_A_DQS#7 <5> DDR_A_DQS7 <5>

DDR_EVENT# <5> FCH_SMDAT0 <12,19,20> FCH_SMCLK0 <12,19,20>

1

C133

2

1000P_0402_50V7K

0.1U_0402_16V4Z

100 mA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/08/12 2012/08/12

DDR_A_D[0..63]

DDR_A_MA[0..15]

DDR_A_DM[0..7]

0.1U_0402_16V4Z

2

C121

1

0.1U_0402_16V4Z

Compal Secret Data

Deciphered Date

DDR_A_D[0..63] <5>

DDR_A_MA[0..15] <5>

DDR_A_DM[0..7] <5>

0.1U_0402_16V4Z

2

C122

1

2

C123

1

2

C124

1

0.1U_0402_16V4Z

2

+1.5V

R59

R59 1K_0402_1%

1K_0402_1%

0.1U_0402_16V4Z

2

C125

1

+VREF_DQ

2

1

0.1U_0402_16V4Z

C126

@

1 2

2

C127

@

1

R61

R61 1K_0402_1%

1K_0402_1%

2

C128

@

1

0.1U_0402_16V4Z

+VREF_CA

0.1U_0402_16V4Z

2

@

1

9/11 Change C137 to SGA00004L00

CRB 0.1u X1 4.7u X1

+0.75VS

1

2

C134

@

1

0.1U_0402_16V4Z

Place near JDIMM1

8/25 Change C137 from poly-cap to E-cap (SF000002Y00) 8/25 Reserve C381 E-cap (SF000002Y00) on +1.5V

C136

C135

2

1

0.1U_0402_16V4Z

CRB 100U X2

4.7U_0603_6.3V6K

9/11 Remove C381

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

DDR3 SODIMM-I Socket

P0VE6 Schematics

2

C129

1

0.1U_0402_16V4Z

+1.5V

SGA00004L00

1

+1.5V

R60

R60 1K_0402_1%

1K_0402_1%

1 2

R62

R62 1K_0402_1%

1K_0402_1%

1 2

0.1U_0402_16V4Z

2

C130

@

1

+

C137

C137 220U_D2_2VY_R15M

220U_D2_2VY_R15M

2

7 36Wednesday, November 17, 2010

C131

@

1.0

DDR_A_D0 DDR_A_D1

DDR_A_DM0

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D27

R396

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

DDR_A_MA10

DDR_A_MA13

DDR_A_D32 DDR_A_D33

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_DM7

DDR_A_D58 DDR_A_D59

12

R64

10K_0402_5%

+1.5V

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4406-0102

CONN@

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6

DQ7 VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1 CK1#

VDD12

BA1

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35 DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47 DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

SCL VTT2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78

A15

80

A14

82 84

A11

86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100 102 104 106 108 110 112 114

S0#

116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

G2

4

W=20mil

+VREF_DQ

1

C118

D D

C C

B B

A A

+3VS

2

DDR_CS1_DIMMA#<5 >

C138

1

C119

2

0.1U_0402_16V4Z

DDR_A_DQS#1<5> DDR_A_DQS1<5>

DDR_A_DQS#2<5> DDR_A_DQS2<5>

DDR_CKE0<5>

DDR_A_BS2<5>

DDR_A_CLK0<5> DDR_A_CLK#0<5>

DDR_A_BS0<5>

DDR_A_WE#<5> DDR_A_CAS#<5>

DDR_A_DQS#4<5> DDR_A_DQS4<5>

DDR_A_DQS#6<5> DDR_A_DQS6<5>

1

2

1000P_0402_50V7K

1 2

100_0402_1%

R63 10K_0402_5%R63 10K_0402_5%

1 2

1

C139

2

0.1U_0402_16V4Z

2.2U_0603_6.3V6K

5

4

3

2

1

LCD POWER CIRCUIT

12

R67

D D

470_0402_5%

R67

W=40mils

Q32A

DMN66D0LDW-7_SOT363-6

Q32A

+3VALW

R68

100K_0402_5%

2

G

1 2

R69 4.7K_0402_5%R69 4.7K_0402_5%

+LCDVDD_R

61

D

S

W=40mils W=40mils

0.1U_0402_16V4Z

1

C165

2

0.047U_0402_16V4Z

12

8/31 Change R68.2 link to +3VALW

9/24 Change Q3 to SB000007H10

11/02 Change Q3 PN to SB934130020

Q3

+LCDVDD

C162

1

2

Q3

AP2301GN-HF_SOT23-3

C163

1

2

4.7U_0603_6.3V6K

31

2

+3VS+LCDVDD

@

1

C164

4.7U_0603_6.3V6K

2

9/15 Remove D1 L5 R71 R72 C166 C167 for layout spacing

9/23 Add D1 L5 R71 R72 C166 C167 for ESD

About Camera

+3VS

J1

112

JUMP_43X39

@

2

+CAM_VCC

0.1U_0402_16V4Z

C161

1

2

9/23 Remove D1 C166 C167

INVT_PWM <25>

APU_BLPWM <4>

R73

2.2K_0402_5%

1 2

R383

12

9/24 Swap L5

EC

APU

100K_0402_5%

@R383

@

1 2

C169

1000P_0402_50V7K

3G@

For RF

12

R710_0402_5% R710_0402_5%

L5

@L5

USB20_N5_1 USB20_N5

USB20_P5_1

@

1

2

4

WCM2012F2S-900T04_0805

3

4

12

R720_0402_5% R720_0402_5%

2

3

USB20_P5

10/04 Add 100p(C401) on INVT_PWM

C401

INVTPWM

C401

12

100P_0402_50V8J

10/04 Change C401 on INVTPWM

*

Display

R331 0 ohm

R332

R381

R382

R383

R73

R75 2.2k ohm 100k ohm

LVDS eDP

0 ohm

@ 100k ohm

2.2k ohm @

USB20_N5 <12>

USB20_P5 <12>

0.1uF

8/26 Change Q4 Q5 to Q32A Q32B (SB00000DH00) Standard Part

34

D

Q32B

APU_ENVDD<4>

C C

100K_0402_5%

5

G

R70

1 2

9/9 Reserve 100k PD to GND on INVTPWM

CMOS & LCD/PANEL BD. Conn.

8/25 JLVDS1.5 change to INT_MIC0 JLVDS1.6 change to GNDA

Q32B DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

S

8/26 Change Q3 to SB934130020 Standard Part

9/17 Change R387 from @ to mount

100K_0402_5%

1 2

INVTPWM

R387

R3100_0402_5% @ R3100_0402_5% @

12

R3110_0402_5% R3110_0402_5 %

12

8/31 Update JLVDS1 Pin definition Delete R74 R76

9/13 Update LVDS Pin definition, Add R74,R76

9/13 Add Net Name +3VS_DMIC

JLVDS1

1 2

B B

A A

3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

36

293033

32

ACES_88341-3000B001

CONN@

USB20_P5_1 USB20_N5_1

LVDS_ACLK_R LVDS_ACLK#_R

LVDS_A2_R LVDS_A2#_R

LVDS_A1_R LVDS_A1#_R

LVDS_A0_R LVDS_A0#_R

EDID_DATA_R EDID_CLK_R BKOFF# INVTPWM +3VS_LVDS +LCDVDD_L

FBMA-L11-201209-221LMA30T_0805

+LEDVDD

1 2

10/01 Remove R74,R76

camera

W=20mil

+CAM_VCC

12 12

BKOFF# < 25>

12

L6

+LCDVDD

L7

FBMA-L11-201209-221LMA30T_0805

2

C170

C170 330P_0402_50V7K

330P_0402_50V7K

1

3G@

8/22 Reserve R327~R332( 0 ohm) for eDP

8/31 Reserve R353 R354 on LVDS_ACLK

R3530_0402_5% R3530_0402_5% R3540_0402_5% R3540_0402_5%

R3270_0402_5% R3270_0402_5% R3280_0402_5% R3280_0402_5%

R3290_0402_5% R3290_0402_5% R3300_0402_5% R3300_0402_5%

R3310_0402_5% R3310_0402_5% R3320_0402_5% R3320_0402_5%

R3810_0402_5% R3810_0402_5% R3820_0402_5% R3820_0402_5%

R3340_0402_5% R3340_0402_5%

12

EDID_DATA EDID_CLK

+3VS

W=20mil

LVDS_ACLK <4> LVDS_ACLK# <4 >

LVDS_A2 <4> LVDS_A2# <4>

LVDS_A1 <4> LVDS_A1# <4>

LVDS_A0 <4> LVDS_A0# <4>

EDID_DATA <4> EDID_CLK <4>

8/22 Reserve R334(0402 0 ohm)

W=20mil

B+

1

C171

C171 100P_0402_50V8J

100P_0402_50V8J

2

3G@

EDID_CLK_R

EDID_DATA_R

9/7 Reserve R381,R382( 0 ohm)R383(100k@) for eDP

+3VS

R75

2.2K_0402_5%

INVT_PWM

BKOFF#

C168

220P_0402_50V7K

3G@

1 2

9/3 Pull-Down 10k(R377) to GND on BKOFF#

BKOFF#

5

R377 10K_0402_5%R377 10K_0402_5%

1 2

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/08/12 2012/08/12

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

Compal Electronics, Inc.

LVDS / Camera

P0VE6 Schematics

8 36Wednesday, November 17, 2010

1

1.0

5

R77 0_0 402_5%HDMI@R77 0_0402_5%HDM I@

HDMI_CLKP<4> HDMI_CLKN<4> HDMI_TX0P<4> HDMI_TX0N<4> HDMI_TX1P<4> HDMI_TX1N<4> HDMI_TX2P<4> HDMI_TX2N<4>

D D

1 2

R78 0_0 402_5%HDMI@R78 0_0402_5%HDM I@

1 2

R79 0_0 402_5%HDMI@R79 0_0402_5%HDM I@

1 2

R80 0_0 402_5%HDMI@R80 0_0402_5%HDM I@

1 2

R81 0_0 402_5%HDMI@R81 0_0402_5%HDM I@

1 2

R82 0_0 402_5%HDMI@R82 0_0402_5%HDM I@

1 2

R83 0_0 402_5%HDMI@R83 0_0402_5%HDM I@

1 2

R84 0_0 402_5%HDMI@R84 0_0402_5%HDM I@

1 2

HDMI_CLK+_CONN

HDMI_CLK-_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_TX2+_CONN

HDMI_TX2-_CONN

4

3

2

1

@

D2

D2 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

3

2

1

@

D3

D3 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

2

+5VS+5VS +5VS

3

2

HDMI_HPDHDMICLK_RHDMIDAT_R

1

@

D4

D4 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

1

EMI/ESD

+3VS

G

2

L8

@L8

HDMI_CLKP

HDMI_CLKN

HDMI_TX0P

HDMI_TX0N

HDMI_TX1P

C C

HDMI_TX1N

HDMI_TX2P

HDMI_TX2N

@

1

4

WCM-2012-900T_4P

L9

@L9

@

1

4

WCM-2012-900T_4P

L10

@L10

@

1

4

WCM-2012-900T_4P

L11

@L11

@

1

4

WCM-2012-900T_4P

2

3

2

3

2

3

2

3

HDMI_CLK+_CONN

HDMI_CLK-_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_TX2+_CONN

HDMI_TX2-_CONN

HDMI_CLK+_CONN

HDMI_CLK-_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_TX2+_CONN

HDMI_TX2-_CONN

R85 499 _0402_1%HDMI@R85 499_0402_1%HDMI@

R86 499 _0402_1%HDMI@R86 499_0402_1%HDMI@

R87 499 _0402_1%HDMI@R87 499_0402_1%HDMI@

R88 499 _0402_1%HDMI@R88 499_0402_1%HDMI@

R89 499 _0402_1%HDMI@R89 499_0402_1%HDMI@

R90 499 _0402_1%HDMI@R90 499_0402_1%HDMI@

R91 499 _0402_1%HDMI@R91 499_0402_1%HDMI@

R93 499 _0402_1%HDMI@R93 499_0402_1%HDMI@

+5VS

NEAR CONNECT

1 2

12

@

R95

R95 100K_0402_5%

100K_0402_5%

2

G

13

D

Q7

Q7 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

HDMI@

10/29 Add C409~C412(0.1U) on +5VS_HDMI 10/29 Add C415~C416(0.1U) on +5VS_HDMI_F

8/26 Change Q7 to SB000009610 Standard Part

10/27 Change D5 P/N from SC1B491D000 to SCS00003H00

10/27 Change F2 P/N from SP04301P120 to SP040001B00

B B

R99

1 2

0_0402_5%

@

HDMI@

MMBT3904_NL_SOT23-3

HDMI_DET<4>

A A

9/20 Change R99 from HDMI@ to @

9/20 Change Q8,R100 from @ to HDMI@

+3VS

C

Q8

C

E

3 1

12

R103

R103 100K_0402_5%

100K_0402_5%

HDMI@

R100

1 2

2

B

150K_0402_5%

HDMI@

R101

200K_0402_5%

@

HDMI_HPD

1 2

10/28 Change JHDMI1 footprint from ACON_HMR2E-AK120D_19P-T to ACON_HMR2E-AK120D_19P-S

12

@

R102

R102 100K_0402_5%

100K_0402_5%

10/07 Update JHDMI1 footprint from ACON_HMR2E-AK120D_19P to ACON_HMR2E-AK120D_19P-T

HDMI_CLK<4>

G

5

S

HDMI_DATA<4>

S

Q9B

Q9B DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

HDMI@

1 2

R92

1 2

R94

8/19 Change Q9A Q9B to SB00000DH00 (S TR DMN66D0LDW-7 2N SOT363-6)

+5VS_HDMI +5VS_HDMI_F

C4090.1U_0402_16V4Z

HDMI@

C4090.1U_0402_16V4Z

12

C4100.1U_0402_16V4Z

12

C4110.1U_0402_16V4Z

12

C4120.1U_0402_16V4Z

12

@

R96

0_0805_5%

+5VS

21

+5VS_HDMI

W=60mil

HDMI@

2.2K_0402_5%

8/23 Update JHDMI1 Symbol (SUYIN_100042GR019S268ZR_19P-T) 8/23 Update JHDMI1 Symbol (SUYIN_100042GR019M23DZL_19P-T)

HDMI@

R98

R97

2.2K_0402_5%

21

1 2

F2

1.1A_6V_SMD1812P110TF

HDMI_CLK-_CONN

HDMI_CLK+_CONN HDMI_TX0-_CONN

HDMI_TX0+_CONN HDMI_TX1-_CONN

HDMI_TX1+_CONN HDMI_TX2-_CONN

HDMI_TX2+_CONN

12

HDMI@

12

HDMI@

W=60mil

9/20 Add F2 on HDMI

HDMI@

D5

D5 RB491D_SC59-3

RB491D_SC59-3

1

2

HDMI@F2

HDMI@

HDMI_HPD +5VS_HDMI_F

HDMIDAT_R HDMICLK_R

61

D

S

Q9A

Q9A DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

HDMI@

34

D

0_0402_5%@

C4150.1U_0402_16V4Z

C4160.1U_0402_16V4Z

C172

0.1U_0402_16V4Z

HDMI@

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

ACON_HMR2E-AK120D

CONN@

GND GND GND GND

20 21 22 23

HDMICLK_R

HDMIDAT_R

9/7 Update JHDMI1 Symbol (ACON_HMR2E-AK120D_19P)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/08/12 2012/08/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HDMI Connector

P0VE6 Schematics

9 36Wednesday, November 17, 2010

1

1.0

A

B

C

D

E

Close to CRT CONN for ESD.

2

3

D6

@

Modify C31- C308 C303 C307 C306 C304 BOM Structure 0615

1 1

DAC_RED<4>

DAC_GRN<4>

DAC_BLU<4>

2 2

CRT_HSYNC<4>

8/21 Change U2 U3 to SA00000RZ00 (TC7SET125FUF_SC70-5)

CRT_VSYNC<4>

3 3

8/21 Reserve R325 R326 for CRT buffer cost down

2.2K_0402_5%

CRT_DDC_DATA<4>

4 4

CRT_DDC_CLK<4>

R104

R109

+3VS

150_0402_1%

12

R105

12

2.2K_0402_5%

R108

150_0402_1%

12

R106

150_0402_1%

1 2

C179 0.1U_0402_16V4ZC179 0.1U_0402_16V4Z

U2

1

G

2

IN A

GND3OUT Y

TC7SET125FUF_SC70-5

R325 0_0402_5%@R325 0_0402_5%@

1 2

C180 0.1U_0402_16V4ZC180 0.1U_0402_16V4Z

U3

1

G

2

IN A

GND3OUT Y

TC7SET125FUF_SC70-5

R326 0_0402_5%@R326 0_0402_5%@

1 2

2.2K_0402_5%

G

5

34

D

S

Q11B

G

2

DMN66D0LDW-7_SOT363-6

61

D

S

Q11A

Q11A DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

Vcc

10/4 Change from +CRT_VCC to +CRT_VCC_F

R110

8/19 Change Q11A Q11B to SB00000DH00 (S TR DMN66D0LDW-7 2N SOT363-6)

A

B

Change L12. L14, L15 to SM01000C600 2010/04/06

1

C176

C177

2

10P_0402_50V8J

+5VS

5

4

+5VS

5

4

CRT_HSYNC_R

CRT_VSYNC_R

+CRT_VCC_F+3VS

12

R111

2.2K_0402_5%

VGA_DDC_DAT

VGA_DDC_CLK

R375 39_0402_5%R375 39_0402_5%

R376 39_0402_5%R376 39_0402_5%

10P_0402_50V8J

1 2

8/26 Update D8 P/N to SCS00003H00

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

L12

CHENG-HANN MBK1005470YZF 0402

1 2

L13

CHENG-HANN MBK1005470YZF 0402

1 2

L14

CHENG-HANN MBK1005470YZF 0402

1 2

1

C178

2

10P_0402_50V8J

C173

10P_0402_50V8J

1

2

C174

C174 10P_0402_50V8J

10P_0402_50V8J

8/31 Delete Net Name: CRT_HSYNC_1, CRT_VSYNC_1

9/3 Add R375 R376 for CRT

CRT PORT

+CRT_VCC

+5VS

F1

D8

W=40mils

2 1

RB491D_SC59-3

8/26 Update F1 P/N to SP040001B00

2010/08/12 2012/08/12

C

F1

1.1A_6VDC_FUSE

CRT11 RED

VGA_DDC_DAT GREEN

JVGA_HS BLUE

JVGA_VS CRT4

VGA_DDC_CLK

Compal Secret Data

Deciphered Date

1

2

+CRT_VCC_F

21

@

1

PJDLC05C_SOT23-3

1

C175

10P_0402_50V8J

2

CRT_DET

8/22 Update JCRT1 Symbol from database (SUYIN_070546FR015M21TZR_15P)

0.1U_0402_16V4Z

C181

1 2

JCRT1

6

11

1 7

12

2 8

G

13

G

3 9

14

4 10 15

5

SUYIN_070546FR015M21TZR

CONN@

CRT_DET#

R112

R112 100K_0402_5%

100K_0402_5%

1 2

+CRT_VCC

D

2

3

D7

@

1

RED

PJDLC05C_SOT23-3

GREEN

BLUE

JVGA_HS

JVGA_VS

+3VS

R107

R107 10K_0402_5%

2

G

10K_0402_5%

@

1 2

13

D

Q10

Q10 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

@

High: CRT Plugged

CRT_DET

CRT_DET#

8/26 Change Q10 to SB000009610 Standard Part

11/01 Add Net CRT4, CRT11 on JCRT.4 , JCRT.11

16 17

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

Compal Electronics, Inc.

CRT PORT

P0VE6 Schematics

E

1.0

10 36Wednesday, November 17, 2010

1.0

A

+3VALW

C182

12

5

U4

0.1U_0402_16V4Z

A_RST#

R114

8.2K_0402_5%

@

1 2

1 1

NC7SZ08P5X_NL_SC70-5

R120 0_0402_5%@R120 0_0402_5%@

2

B

1

A

1 2

U4

P

PLT_RST#

4

Y

G

3

12

R115

R115 100K_0402_5%

100K_0402_5%

9/2 Change R120 from 0603 to 0402

9/16 Change U4,C182 from @ to mount, R120, R115 from mount to @

9/27 Change R115 from @ to mount

2 2

9/9 Add R384(@ 0 ohm) R385(0 ohm) on PCI-E RST

9/20 C183.2 link to R119.2 Follow CRB

PLT_RST# <17,19,20,25>

A_RST#

R119 33_0402_5%R119 33_0402_5%

UMI_RX0P<5> UMI_RX0N<5> UMI_RX1P<5> UMI_RX1N<5> UMI_RX2P<5> UMI_RX2N<5> UMI_RX3P<5> UMI_RX3N<5>

UMI_TX0P<5> UMI_TX0N<5> UMI_TX1P<5> UMI_TX1N<5> UMI_TX2P<5> UMI_TX2N<5> UMI_TX3P<5> UMI_TX3N<5>

+PCIE_VDDAN

PCIE_FTX_C_DRX_P1<19> PCIE_FTX_C_DRX_N1<19> PCIE_FTX_C_DRX_P2<17> PCIE_FTX_C_DRX_N2<17> PCIE_FTX_C_DRX_P3<20> PCIE_FTX_C_DRX_N3<20>

9/6 Change PCI-E from FCH to APU

9/15 Change PCI-E from APU to FCH

8/25 Update JBATT1 Symbol (LOTES_AAA-BAT-019-K01_2P)

+RTCBATT1

1

CONN@

JBATT1

+

LAN

-

LOTES_AAA-BAT-019-K01

2

3 3

WLAN

WWAN

DISP_CLK<4> DISP_CLK#<4>

APU_CLK<4> APU_CLK#<4>

CLK_PCIE_LAN<17> CLK_PCIE_LAN#<17>

CLK_PCIE_WLAN<20> CLK_PCIE_WLAN#<20>

CLK_PCIE_WW AN<19> CLK_PCIE_WW AN#<19>

9/6 Change D10 to SC600000B00 Standard Part

2

+RTCBATT1_R

3

W=20mil

+CHGRTC

D10

1

BAV70W_SOT323-3

NONCHARGE@

9/13 Add Net Name +RTCBATT1_RR

1 2

R244 1K_0402_5%

NONCHARGE@

+RTCBATT1+RTCBATT

9/13 Add NONCHARGE@ for D10 R244

CLK_48M_CR<18>

9/13 Change Net Name +RTCBATT1 to +RTCBATT2

+RTCBATT2_R

CHARGE@

+RTCBATT

1

2

CHARGE@

C392

0.1U_0402_16V4Z

4 4

1

D23

2

3

BAS40-04_SOT23-3

A

10/07 Change R392 from 1k to 0 ohm

10/08 Change R392 from 0 ohm to 1k ohm

9/13 Add C392,R392,D23(CHARGE@) for RTC Charge Circuit

12

+RTCBATT2

R3920_0402_5%

CHARGE@

+CHGRTC

11/01 Change R392 from 1k to 0 ohm

B

150P_0402_50V8J

R121 590_0402_1%R121 590_0402_1% R118 2K_0402_1%R118 2K_0402_1%

C183

12

C184 .1U_0402_16V7KC184 .1U_0402_16V7K

1 2

C185 .1U_0402_16V7KC185 .1U_0402_16V7K

1 2

C188 .1U_0402_16V7KC188 .1U_0402_16V7K

1 2

C186 .1U_0402_16V7KC186 .1U_0402_16V7K

1 2

C187 .1U_0402_16V7KC187 .1U_0402_16V7K

1 2

C189 .1U_0402_16V7KC189 .1U_0402_16V7K

1 2

C190 .1U_0402_16V7KC190 .1U_0402_16V7K

1 2

C191 .1U_0402_16V7KC191 .1U_0402_16V7K

1 2

C192 .1U_0402_16V7KC192 .1U_0402_16V7K

1 2

C193 .1U_0402_16V7KC193 .1U_0402_16V7K

1 2

C194 .1U_0402_16V7KC194 .1U_0402_16V7K

1 2

C195 .1U_0402_16V7KC195 .1U_0402_16V7K

1 2

C379 .1U_0402_16V7KC379 .1U_0402_16V7K

1 2

C380 .1U_0402_16V7KC380 .1U_0402_16V7K

1 2

WWAN LAN WLAN

12 12

PCIE_FRX_DTX_P1<19> PCIE_FRX_DTX_N1<19> PCIE_FRX_DTX_P2<17> PCIE_FRX_DTX_N2<17> PCIE_FRX_DTX_P3<20> PCIE_FRX_DTX_N3<20>

R384 0_0402_5%@R384 0_0402_5%@ R385 0_0402_5%R385 0_0402_5%

1 2 1 2

PCIE_CALRP PCIE_CALRN

PCIE_FTX_DRX_P1 PCIE_FTX_DRX_N1 PCIE_FTX_DRX_P2 PCIE_FTX_DRX_N2 PCIE_FTX_DRX_P3 PCIE_FTX_DRX_N3

close to FCH within 1"

R125 0_0402_5%R125 0_0402_5%

1 2

R126 0_0402_5%R126 0_0402_5%

1 2

R127 0_0402_5%R127 0_0402_5%

1 2

R128 0_0402_5%R128 0_0402_5%

1 2

8/21 Delete R130,R131(No VGA)

R132 0_0402_5%R132 0_0402_5%

1 2

R133 0_0402_5%R133 0_0402_5%

1 2

R134 0_0402_5%R134 0_0402_5%

1 2

R135 0_0402_5%R135 0_0402_5%

1 2

R348 0_0402_5%R348 0_0402_5%

1 2

R349 0_0402_5%R349 0_0402_5%

1 2

DISP_CLK_R DISP_CLK#_R

APU_CLK_R APU_CLK#_R

CLK_PCIE_LAN_R CLK_PCIE_LAN#_R

CLK_PCIE_WLAN_R CLK_PCIE_WLAN#_R

CLK_PCIE_WW AN_R CLK_PCIE_WW AN#_R

8/23 Add R348 R349 for WWAN PCIE

9/1 Add R372 on CLK_48M_CR

9/7 Change R372 to 22 ohm

R372 22_0402_5%R372 22_0402_5%

1 2

C198

22P_0402_50V8J

C199

22P_0402_50V8J

1 2

12

1M_0603_5%

Y2

R139

25MHZ_20PF_7A25000012

B

C

D

10/08 Update U5 to SA000046H70 S IC 218-0792006 A13 HUDSON-M1 605P ABO!

U5E

P1

PCIE_RST_L

L1

UMI_RX0P_C UMI_RX0N_C UMI_RX1P_C UMI_RX1N_C UMI_RX2P_C UMI_RX2N_C UMI_RX3P_C UMI_RX3N_C

CLK_48M_CR_R

25M_CLK_X1

25M_CLK_X2 +RTCBATT_R

A_RST_L

AD26

UMI_TX0P

AD27

UMI_TX0N

AC28

UMI_TX1P

AC29

UMI_TX1N

AB29

UMI_TX2P

AB28

UMI_TX2N

AB26

UMI_TX3P

AB27

UMI_TX3N

AE24

UMI_RX0P

AE23

UMI_RX0N

AD25

UMI_RX1P

AD24

UMI_RX1N

AC24

UMI_RX2P

AC25

UMI_RX2N

AB25

UMI_RX3P

AB24

UMI_RX3N

AD29

PCIE_CALRP

AD28

PCIE_CALRN

AA28

GPP_TX0P

AA29

GPP_TX0N

Y29

GPP_TX1P

Y28

GPP_TX1N

Y26

GPP_TX2P

Y27

GPP_TX2N

W28

GPP_TX3P

W29

GPP_TX3N

AA22

GPP_RX0P

Y21

GPP_RX0N

AA25

GPP_RX1P

AA24

GPP_RX1N

W23

GPP_RX2P

V24

GPP_RX2N

W24

GPP_RX3P

W25

GPP_RX3N

M23

PCIE_RCLKP/NB_LNK_CLKP

P23

PCIE_RCLKN/NB_LNK_CLKN

U29

NB_DISP_CLKP

U28

NB_DISP_CLKN

T26

NB_HT_CLKP

T27

NB_HT_CLKN

V21

CPU_HT_CLKP

T21

CPU_HT_CLKN

V23

SLT_GFX_CLKP

T23

SLT_GFX_CLKN

L29

GPP_CLK0P

L28

GPP_CLK0N

N29

GPP_CLK1P

N28

GPP_CLK1N

M29

GPP_CLK2P

M28

GPP_CLK2N

T25

GPP_CLK3P

V25

GPP_CLK3N

L24

GPP_CLK4P

L23

GPP_CLK4N

P25

GPP_CLK5P

M25

GPP_CLK5N

P29

GPP_CLK6P

P28

GPP_CLK6N

N26

GPP_CLK7P

N27

GPP_CLK7N

T29

GPP_CLK8P

T28

GPP_CLK8N

L25

14M_25M_48M_OSC

L26

25M_X1

L27

25M_X2

S IC 218-0792006 A13 HUDSON-M1 FCBGA 0FA

PCI EXPRESS I/F

CLOCK GENERATOR

PCI CLKS

PCICLK4/14M_OSC/GPO39

PCI I/F

REQ2_L/CLK_REQ8_L/GPIO41 REQ3_L/CLK_REQ5_L/GPIO42

GNT3_L/CLK_REQ7_L/GPIO46

LPC

LDRQ1_L/CLK_REQ6_L/GPIO49

CPU

ALLOW_LDTSTP/DMA_AC TIVE_L

RTC

INTRUDER_ALERT_L

PCICLK1/GPO36 PCICLK2/GPO37 PCICLK3/GPO38

AD10/GPIO10 AD11/GPIO11 AD12/GPIO12 AD13/GPIO13 AD14/GPIO14 AD15/GPIO15 AD16/GPIO16 AD17/GPIO17 AD18/GPIO18 AD19/GPIO19 AD20/GPIO20 AD21/GPIO21 AD22/GPIO22 AD23/GPIO23 AD24/GPIO24 AD25/GPIO25 AD26/GPIO26 AD27/GPIO27 AD28/GPIO28 AD29/GPIO29 AD30/GPIO30 AD31/GPIO31

REQ1_L/GPIO40

GNT1_L/GPO44 GNT2_L/GPO45

INTE_L/GPIO32

INTF_L/GPIO33 INTG_L/GPIO34 INTH_L/GPIO35

SERIRQ/GPIO48

PROCHOT_L

VDDBT_RTC_G

PCICLK0

PCIRST_L

AD0/GPIO0 AD1/GPIO1 AD2/GPIO2 AD3/GPIO3 AD4/GPIO4 AD5/GPIO5 AD6/GPIO6 AD7/GPIO7 AD8/GPIO8 AD9/GPIO9

CBE0_L CBE1_L CBE2_L CBE3_L

FRAME_L

DEVSEL_L

IRDY_L

TRDY_L

PAR STOP_L PERR_L SERR_L REQ0_L

GNT0_L

CLKRUN_L

LOCK_L

LPCCLK0 LPCCLK1

LAD0 LAD1 LAD2 LAD3

LFRAME_L

LDRQ0_L

LDT_PG

LDT_STP_L LDT_RST_L

32K_X1

32K_X2

RTCCLK

W2 W1 W3 W4 Y1

V2

AA1 AA4 AA3 AB1 AA5 AB2 AB6 AB5 AA6 AC2 AC3 AC4 AC1 AD1 AD2 AC6 AE2 AE1 AF8 AE3 AF1 AG1 AF2 AE9 AD9 AC11 AF6 AF4 AF3 AH2 AG2 AH3 AA8 AD5 AD8 AA10 AE8 AB9 AJ3 AE7 AC5 AF5 AE6 AE4 AE11 AH5 AH4 AC12 AD12 AJ5 AH6 AB12 AB11 AD7

AJ6 AG6 AG4 AJ4

H24 H25 J27 J26 H29 H28 G28 J25 AA18 AB19

G21 H21 K19 G22 J24

C1

C2

D2 B2 B1

SA000046HA0

8/25 Change FCH(U5) PN to SA000046H30

11/04 Change U5 PN to SA000046HA0 (S IC 218-0792006 A13 HUDSON-M1 FCBGA 0FA)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/12 2012/08/12

C

Compal Secret Data

Deciphered Date

T16PADT16PAD

PCI_CLK2

T17PADT17PAD

PE_GPIO0

10/05 PD 10k(R405) on CLKRUN

GPIO42

GPIO46

RTC_32KHI

RTC_32KHO

T18

PAD

PE_GPIO1

T19

PAD

1 2

R136 0_0402_5%R136 0_0402_5%

1 2

R137 22_0402_5%R137 22_0402_5%

1 2

R138 0_0402_5%R138 0_0402_5%

1 2

SUSCLK <25>

1

C200

2

1U_0402_6.3V6K

D

+3VS

Watchdog timer on NB_PWRGD

12

@

enable for pull-up disable for pull-down 20100527

R113

PCI_CLK1 <15>

PCI_CLK3 <15> PCI_CLK4 <15>

R113

10K_0402_5%

12

R116

10K_0402_5%

9/9 Change R117 R122 from mount to @ 9/15 PU PE_GPIO1 100k to +5VALW

PE_GPIO1

PE_GPIO0

10/11 Change Y1 from SJ100006600 to SJ132P7KW10

PCI_AD23 <15> PCI_AD24 <15> PCI_AD25 <15> PCI_AD26 <15> PCI_AD27 <15>

R405

10K_0402_5%

LPC_AD0 <25> LPC_AD1 <25> LPC_AD2 <25> LPC_AD3 <25> LPC_FRAME# <25>

SERIRQ <25>

ALLOW_STOP# <4> FCH_PROCHOT# <4> APU_PWRGD <4>

LDT_RST# <4>

R123 20M _0402_5%@R123 20 M_0402_5%@

1 2

C196

1 2

22P_0402_50V8J

R124

20M_0603_5%

C197

1 2

22P_0402_50V8J

APU_PWRGD

LPCCLK0 <15>

LPC_CLK0_EC <25> CLK_PCI_DB <15>

11/15 Delete net U5_G22

10/07 Change R140 from 560 to 1k ohm

11/01 Add Net U5_G22 on U5.G22

1 2

R140 1K_0402_5%R140 1K_0402_5%

+RTCBATT

for Clear CMOS

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

E

R117 100K_0402_5%R117 100K_0402_5%

1 2

R122 100K_0402_5%@R122 100K_0402_5%@

1 2

Close to FCH

RTC_32KHO

Y1

12

+1.8VS +3VS

G

2

S

FDV301N_NL_SOT23-3

Q12

Y1

4

OSC

1

OSC

32.768KHZ_12.5PF_9H03200413

RTC_32KHI

12

R129

10K_0402_5%

13

D

2

C396

C396 100P_0402_50V8J

100P_0402_50V8J

1

3

NC

2

NC

H_PWRGD_L <35>

10/04 Add 100p(C396) on H_PWRGD_L

W=20mil

12

CLRP1

@CLRP1

@

SHORT PADS

FCH PCIE/PCI/ACPI/LPC/RTC

P0VE6 Schematics

11 36Wednesday, November 17, 2010

E

+5VALW

1.0

C397

12

A

FCH_PCIE_WAKE#

WWAN_CLK REQ#

WLAN_CLKREQ#

R159 0_0402_5%@R159 0_0402_5%@

R160 0_0402_5%R160 0_0402_5%

4

2

@

C202

1

.1U_0402_16V7K

12

R409

@R409

@

R411

10K_0402_5%

USB_OC2#

USB_OC1#

USB_OC0#

FCH_SIC

FCH_SID

LAN_CLKREQ#

NB_PWRGD

FCH_SMCLK0

FCH_SMDAT0

+3VS

1 2

5

P

Y

G

3

FCH_SMCLK1

FCH_SMDAT1

EC_RSMRST#

HDA_BITCLK

HDA_SDIN0

HDA_SDOUT

12

@R411

@

1 2

R142 10K_0402_5%R142 10K_0402_5%

@

1 2

R144 10K_0402_5%

1 2

R151 10K_0402_5%R151 10K_0402_5%

1 2

R152 10K_0402_5%R152 10K_0402_5%

1 2

R153 10K_0402_5%R153 10K_0402_5%

9/20 Change R145,R147 from @ to mount

12

C417

+3VALW

H_THERMTRIP#

150P_0402_50V8J

11/15 Add C417(150p) on H_THERMTRIP#

12

@

C201 .1U_0402_16V 7K

2

B

1

A

NC7SZ08P5X_NL_SC70-5

@

U6

8/31 Delete Net : SATA_DET#

ICH_POK <25>

VGATE <25,35>

9/6 Change ODD_DA#_FCH to USB_OC4#

9/6 Change ODD_DETECT# to USB_OC3#

HDA_BITCLK_AUDIO<16> HDA_SDOUT_AUDIO<16>

HDA_SDIN0<16>

HDA_SYNC_AUDIO<16> HDA_RST_AUDIO#<16>

+3VALW

GPIO189 GPIO190

10/07 Add R406~R410 (GPIO189~190) for Board ID

USB_OC7#

EC_LID_OUT#

USB_OC5#

USB_OC4#

USB_OC3#

R148 10K_040 2_5%@R148 10K_0402_5%@

+3VALW

1 2

R141 10K_0402_5%R141 10K_0402_5%

1 2

R143 10K_0402_5%R143 10K_0402_5%

1 2

R150 10K_0402_5%R150 10K_0402_5%

1 2

R145 10K_0402_5%R145 10K_0402_5%

1 2

R147 10K_0402_5%R147 10K_0402_5%

1 2

1 1

R154 10K_0402_5%R154 10K_0402_5%

+3VS

1 2

R359 10K_0402_5%R359 10K_0402_5%

1 2

R155 10K_0402_5%R155 10K_0402_5%

1 2

R156 10K_0402_5%R156 10K_0402_5%

1 2

R157 4.7K_0402_5%R157 4.7K_0402_5%

1 2

R149 2.2K_0402_5%R149 2.2K_0402_5%

1 2

R158 2.2K_0402_5%R158 2.2K_0402_5%

8/31 Pull up 10k(R359) to +3VS on WWAN_CLKREQ#

FCH_PWRGD<35>

2 2

100P_0402_50V8J

10/04 Add 100p(C397) on FCH_PWRGD

1 2

R163 10K_0402_5%R163 10K_0402_5%

1 2

R164 10K_0402_5%R164 10K_0402_5%

1 2

R165 2.2K_0402_5%R165 2.2K_0402_5%

@

1 2

R170 10K_0402_5%

@

1 2

R171 10K_0402_5%

1 2

R172 10K_0402_5%R172 10K_0402_5%

Pull-down for e nable high perf ormance mode 20100527 (requi red for M1)

3 3

+3VALW +3VALW +3VA LW+3VALW

12

R414

@R414

@

R406

10K_0402_5%

E6@

10/07 Add E6@(R406) & S6@(R407) for Board ID

12

R413

R407

R408

10K_0402_5%

S6@

R408 1K_0402_5%

1K_0402_5%

4 4

12

R410

R410 1K_0402_5%

1K_0402_5%

10/27 Change R408 R410 from @ to mount

10/28 Add R413 R414 on GPIO192 for project ID

11/15 Change R408,R410,R413 P/N from 10k to 1k SD028100280 to SD028100180

R406 R407

mount

@

A

B

8/21 Delete Net : KILL_SW#

PCI_PME#<25>

SLP_S3#<25> SLP_S5#<25> PBTN_OUT#<25>

GATEA20<25> KB_RST#<25> EC_SCI#<25>

1 2

EC_SMI#<25>

FCH_PCIE_WAKE#<17,19,20>

H_THERMTRIP#<4>

EC_RSMRST#<25>

LAN_CLKREQ#<17>

FCH_SPKR<16> FCH_SMCLK0<7,19,20> FCH_SMDAT0<7,19,20>

WWAN_CLK REQ#<19> WLAN_CLKREQ#<20>

8/22 Delete Net : R161 R162

EC_LID_OUT#<25>

USB_OC1#<24>

USB_OC0#<24>

R166 33_0402_5%R166 33_0402_5%

1 2

R168 33_0402_5%R168 33_0402_5%

1 2

R173 33_0402_5%R173 33_0402_5%

1 2

R174 33_0402_5%R174 33_0402_5%

1 2

R175 10K_04 02_5%R175 10K_04 02_5%

1 2

R176 10K_04 02_5%R176 10K_04 02_5%

R177 10K_0402_5%R177 10K_0402_5%

1 2

R180 10K_0402_5%R180 10K_0402_5%

1 2

R181 10K_0402_5%R181 10K_0402_5%

1 2

Board ID

P0VE6

@

mount

P0VS6

B

T23 PADT23 PAD T24 PADT24 PAD

FCH_PWRGD

T20PADT20PAD T21PADT21PAD T22PADT22PAD

NB_PWRGD

FCH_SMCLK1 FCH_SMDAT1

USB_OC7#

USB_OC5# USB_OC4# USB_OC3# USB_OC2#

HDA_BITCLK HDA_SDOUT HDA_SDIN0

HDA_SYNC HDA_RST#

GPIO187 GPIO188

GPIO189 GPIO190 GPIO191GPIO191 GPIO192GPIO192

C

U5A

J2

PCI_PME_L/GEVENT4_L

K1

RI_L/GEVENT22_L

D3

SPI_CS3_L/GBE_STAT1/GEVENT21_L

F1

SLP_S3_L

H1

SLP_S5_L

F2

PWR_BTN_L

H5

PWR_GOOD

G6

SUS_STAT_L

B3

TEST0

C4

TEST1/TMS

F6

TEST2

AD21

GA20IN/GEVENT0_L

AE21

KBRST_L/GEVENT1_L

K2

LPC_PME_L/GEVENT3_L

J29

LPC_SMI_L/GEVENT23_L

H2

GEVENT5_L

J1

SYS_RESET_L/GEVENT19_L

H6

WAKE_L/GEVENT8_L

F3

IR_RX1/GEVENT20_L

J6

THRMTRIP_L/SMBALERT_L/GEVEN T2_L

AC19

NB_PWRGD

G1

RSMRST_L

AD19

CLK_REQ4_L/SATA_IS0_L/GPIO64

AA16

CLK_REQ3_L/SATA_IS1_L/GPIO63

AB21

SMARTVOLT1/SATA_IS2_L/GPIO50

AC18

CLK_REQ0_L/SATA_IS3_L/GPIO60

AF20

SATA_IS4_L/FANOUT3/GPIO55

AE19

SATA_IS5_L/FANIN3/GPIO59

AF19

SPKR_GPIO66

AD22

SCL0_GPIO43

AE22

SDA0_GPIO47

F5

SCL1_GPIO227

F4

SDA1_GPIO228

AH21

CLK_REQ2_L/FANIN4_GPIO62

AB18

CLK_REQ1_L/FANOUT4_GPIO61

E1

IR_LED_L/LLB_L/GPIO184

AJ21

SMARTVOLT2/SHUTDOWN _L/GPIO51

H4

DDR3_RST_L/GEVENT7_L

D5

GBE_LED0/GPIO183

D7

GBE_LED1/GEVENT9_L

G5

GBE_LED2/GEVENT10_L

K3

GBE_STAT0/GEVENT11_L

AA20

CLK_REQG_L/GPIO65_OSCIN

H3

BLINK/USB_OC7_L/GEVENT18_L

D1

USB_OC6_L/IR_TX1/GEVENT6_L

E4

USB_OC5_L/IR_TX0/GEVENT17_L

D4

USB_OC4_L/IR_RX0/GEVENT16_L

E8

USB_OC3_L/AC_PRES/TDO/GEVENT15_L

F7

USB_OC2_L/TCK/GEVENT14_L

E7

USB_OC1_L/TDI/GEVENT13_L

F8

USB_OC0_L/TRST_L/GEVENT12_L

HD AUDIO

M3

AZ_BITCLK

N1

AZ_SDOUT

L2

AZ_SDIN0/GPIO167

M2

AZ_SDIN1/GPIO168

M1

AZ_SDIN2/GPIO169

M4

AZ_SDIN3/GPIO170

N2

AZ_SYNC

P2

AZ_RST_L

T1

GBE_COL

T4

GBE_CRS

L6

GBE_MDCK

L5

GBE_MDIO

T9

GBE_RXCLK

U1

GBE_RXD3

U3

GBE_RXD2

T2

GBE_RXD1

U2

GBE_RXD0

T5

GBE_RXCTL/RXDV

V5

GBE_RXERR

P5

GBE_TXCLK

M5

GBE_TXD3

P9

GBE_TXD2

T7

GBE_TXD1

P7

GBE_TXD0

M7

GBE_TXCTL/TXEN

P4

GBE_PHY_PD

M9

GBE_PHY_RST_L

V7

GBE_PHY_INTR

E23

PS2_DAT/SDA4/GPIO187

E24

PS2_CLK/SCL4/GPIO188

F21

SPI_CS2_L/GBE_STAT2/GPIO166

G29

FC_RST_L/GPO160

D27

PS2KB_DAT/GPIO189

F28

PS2KB_CLK/GPIO190

F29

PS2M_DAT/GPIO191

E27

PS2M_CLK/GPIO192

S IC 218-0792006 A13 HUDSON-M1 FCBGA 0FA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

HD AUDIO

GBE LAN

2010/08/12 2012/08/12

ACPI/WAKE UP EVENTS

GPIO

USB OC

USB MISC

USBCLK/14M_25M_48M_OSC

EC_PWM0/EC_TIMER 0/GPIO197 EC_PWM1/EC_TIMER 1/GPIO198 EC_PWM2/EC_TIMER 2/GPIO199 EC_PWM3/EC_TIMER 3/GPIO200

Compal Secret Data

USB 1.1

USB_FSD1P/GPIO186

USB_FSD0P/GPIO185

USB 2.0

SCL3_LV/GPIO195

SDA3_LV/GPIO196

EMBEDDED CTRL

KSO_10/GPIO219 KSO_11/GPIO220 KSO_12/GPIO221 KSO_13/GPIO222 KSO_14/GPIO223 KSO_15/GPIO224 KSO_16/GPIO225 KSO_17/GPIO226

Deciphered Date

USB_RCOMP

USB_FSD1N

USB_FSD0N

USB_HSD13P USB_HSD13N

USB_HSD12P USB_HSD12N

USB_HSD11P USB_HSD11N

USB_HSD10P USB_HSD10N

USB_HSD9P USB_HSD9N

USB_HSD8P USB_HSD8N

USB_HSD7P USB_HSD7N

USB_HSD6P USB_HSD6N

USB_HSD5P USB_HSD5N

USB_HSD4P USB_HSD4N

USB_HSD3P USB_HSD3N

USB_HSD2P USB_HSD2N

USB_HSD1P USB_HSD1N

USB_HSD0P USB_HSD0N

SCL2/GPIO193 SDA2/GPIO194

KSI_0/GPIO201 KSI_1/GPIO202 KSI_2/GPIO203 KSI_3/GPIO204 KSI_4/GPIO205 KSI_5/GPIO206 KSI_6/GPIO207 KSI_7/GPIO208

KSO_0/GPIO209 KSO_1/GPIO210 KSO_2/GPIO211 KSO_3/GPIO212 KSO_4/GPIO213 KSO_5/GPIO214 KSO_6/GPIO215 KSO_7/GPIO216 KSO_8/GPIO217 KSO_9/GPIO218

D

A10

G19

J10 H11

H9 J8

B12 A12

F11 E11

E14 E12

J12 J14

A13 B13

D13 C13

G12 G14

G16 G18

D16 C16

B14 A14

E18 E16

J16 J18

B17 A17

A16 B16

D25 F23 B26 E26 F25 E22 F22 E21

G24 G25 E28 E29 D29 D28 C29 C28

B28 A27 B27 D26 A26 C26 A24 B25 A25 D24 B24 C24 B23 A23 D22 C22 A22 B22

D

USB_RCOMP

GPIO193 GPIO194

EC_PWM2 EC_PWM3

R146

1 2

11.8K_0402_1%

10mils and <1"

9/15 Update USB Port List

9/1 Update USB Port List

8/23 USB port8 link to SIM

R167 10K_040 2_5%R167 10K_0402_5% R169 10K_040 2_5%R169 10K_0402_5%

8/31 Change R182 from mount to @ Change R183 from @ to mount

12 12

FCH_SIC <4> FCH_SID <4>

9/15 Change R178 from @ to mount

EC_PWM3 EC_PWM2 ROM TYPE

NC

NC NC

L

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

E

USB20_P9 <19> USB20_N9 <19>

USB20_P8 <20> USB20_N8 <20>

USB20_P7 <19> USB20_N7 <19>

USB20_P6 <18> USB20_N6 <18>

USB20_P5 <8> USB20_N5 <8>

USB20_P4 <19> USB20_N4 <19>

USB20_P3 <19> USB20_N3 <19>

USB20_P2 <24> USB20_N2 <24>

USB20_P1 <24> USB20_N1 <24>

USB20_P0 <24> USB20_N0 <24>

WWAN

WiMax

Bluetooth

Card Reader

Camera

SIM

WWAN

USB Conn.(LS) JUSB1

USB Conn.(RS) JUSB3

USB Conn.(RS) JUSB2

Internal Pull-Up available

+3VALW

R178

1 2

10K_0402_5%

EC_PWM3 EC_PWM2

12

R182

@

2.2K_0402_5%

SPI ROM

L

Reserved

L

LPC ROM

H

FCH HDA/USB/ACPI

P0VE6 Schematics

12 36Thursday, November 18, 2010

E

R179

@

R183

*

1.0

A

1 1

SATA_ITX_C_DRX_P0 SATA_ITX_C_DRX_N0

HDD

C203 0.01U_0402_ 16V7KC203 0.01U_0402_16V7K

SATA_ITX_DRX_P0<21> SATA_ITX_DRX_N0<21>

SATA_DTX_C_IRX_N0<21> SATA_DTX_C_IRX_P0<21>

1 2

C204 0.01U_0402_ 16V7KC204 0.01U_0402_16V7K

1 2

8/21 Delete C205~C208 (No ODD ESATA function)

2 2

9/7 Change SATA_CALRN from +1.1VS to +AVDD_SATA

10 mils and < 1"

R184 1K_0402_1%R184 1K_0402_1%

1 2

R185 931_0402_1%R185 931_0402_1%

+AVDD_SATA

HDD_LED#<21>

+3VS

3 3

1 2

R190 10K_0402_5%R190 10K_0402_5%

1 2

C209

@

22P_0402_50V8J

C210

@

22P_0402_50V8J

1 2

12

Y3

@

25MHZ_20PF_7A25000012

T25 PADT25 PAD

@

1M_0603_5%

1M_0603_5% R195

R195

SATA_CALRP SATA_CALRN

25M_SATA_X1

25M_SATA_X2

GPIO161

B

U5B

AH9

SATA_TX0P

AJ9

SATA_TX0N

AJ8

SATA_RX0N

AH8

SATA_RX0P

AH10

SATA_TX1P

AJ10

SATA_TX1N

AG10

SATA_RX1N

AF10

SATA_RX1P

AG12

SATA_TX2P

AF12

SATA_TX2N

AJ12

SATA_RX2N

AH12

SATA_RX2P

AH14

SATA_TX3P

AJ14

SATA_TX3N

AG14

SATA_RX3N

AF14

SATA_RX3P

AG17

SATA_TX4P

AF17

SATA_TX4N

AJ17

SATA_RX4N

AH17

SATA_RX4P

AJ18

SATA_TX5P

AH18

SATA_TX5N

AH19

SATA_RX5N

AJ19

SATA_RX5P

AB14

SATA_CALRP

AA14

SATA_CALRN

AD11

SATA_ACT_L/GPIO67

AD16

SATA_X1

AC16

SATA_X2

J5

SPI_DI/GPIO164

E2

SPI_DO/GPIO163

K4

SPI_CLK/GPIO162

K9

SPI_CS1_L/GPIO165

G2

ROM_RST_L/GPIO161

S IC 218-0792006 A13 HUDSON-M1 FCBGA 0FA

SERIAL ATA

SPI ROM

FC_CLK

FC_FBCLKOUT

FC_FBCLKIN

FC_OE_L/GPIOD145

FC_AVD_L/GPIOD146

FC_WE_L/GPIOD148 FC_CE1_L/GPIOD149 FC_CE2_L/GPIOD150

FC_INT1/GPIOD144

GPIOD

FC_INT2/GPIOD147

FC_ADQ0/GPIOD128 FC_ADQ1/GPIOD129 FC_ADQ2/GPIOD130 FC_ADQ3/GPIOD131 FC_ADQ4/GPIOD132 FC_ADQ5/GPIOD133 FC_ADQ6/GPIOD134 FC_ADQ7/GPIOD135 FC_ADQ8/GPIOD136

FC_ADQ9/GPIOD137 FC_ADQ10/GPIOD138 FC_ADQ11/GPIOD139 FC_ADQ12/GPIOD140 FC_ADQ13/GPIOD141 FC_ADQ14/GPIOD142 FC_ADQ15/GPIOD143

HW MONITOR

FANOUT0/GPIO52 FANOUT1/GPIO53 FANOUT2/GPIO54

FANIN0/GPIO56 FANIN1/GPIO57 FANIN2/GPIO58

TEMPIN0/GPIO171 TEMPIN1/GPIO172 TEMPIN2/GPIO173

TEMPIN3/TALERT_L/GPIO174

TEMP_COMM

VIN0/GPIO175 VIN1/GPIO176 VIN2/GPIO177 VIN3/GPIO178 VIN4/GPIO179 VIN5/GPIO180

VIN6/GBE_STAT3/GPIO181

VIN7/GBE_LED3/GPIO182

C

AH28 AG28 AF26

AF28 AG29 AG26 AF27 AE29 AF29 AH27

AJ27 AJ26 AH25 AH24 AG23 AH23 AJ22 AG21 AF21 AH22 AJ23 AF23 AJ24 AJ25 AG25 AH26

8/21 Delete Net : ODD_EN 8/22 Delete Net : BT_OFF#, WL_OFF#

W5 W6 Y9

GPIO56

W7 V9 W8

TEMPIN0

R186 10K_040 2_5%R186 10K_0402_5%

TEMPIN1

R187 10K_040 2_5%R187 10K_0402_5%

TEMPIN2

R188 10K_040 2_5%R188 10K_0402_5% R189 10K_040 2_5%R189 10K_0402_5%

GPIO175

R191 10K_040 2_5%R191 10K_0402_5%

GPIO176

R192 10K_040 2_5%R192 10K_0402_5%

GPIO177

R193 10K_040 2_5%R193 10K_0402_5%

GPIO178

R194 10K_040 2_5%R194 10K_0402_5%

GPIO179

R196 10K_040 2_5%R196 10K_0402_5%

GPIO180

R197 10K_040 2_5%R197 10K_0402_5%

GPIO181

R198 10K_040 2_5%@R198 10K_0402_5%@

GPIO182

R199 10K_040 2_5%R199 10K_0402_5%

NC1 NC2

B6 A6 A5 B5 C7

A3 B4 A4 C5 A7 B7 B8 A8

G27 Y2

D

11/01 Add Net U5_AE29 on U5.AE29

11/15 Delete net U5_AE29

12 12 12 12

12 12 12 12 12 12 12 12

9/9 Change R189 from mount to @

9/15 Change R189 from @ to mount

VIN6/GBE_STAT3/ GPIO181 Enable integrat ed pull-down/up and leave unco nnected

+3VS

12

R415

@

10K_0402_5%

GPIO56

12

R416

@

10K_0402_5%

10/29 Add R415(@), R416(@) on GPIO56

APU_ALERT#_FCH <4>

C406 100P_0402_50 V8JC406 100P_0402_50V8J

1 2

APU_ALERT#_FCH

10/05 Add 100p(C406) on APU_ALERT#_FCH

E

8/31 remove FCH SPI ROM

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/08/12 2012/08/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

FCH-SATA/SPI

P0VE6 Schematics

13 36Wednesday, November 17, 2010

E

1.0

A

B

C

D

E

+3VS

R346

1 2

0_0603_5%

C213

1 1

+1.8VS

R207

1 2

0_0603_5%

+1.1VS

L17

FBMA-L11-201209-221LMA30T_0805

2 2

L18

+3VALW

FBMA-L11-201209-221LMA30T_0805

+1.1VALW

3 3

L18

L20

FBMA-L11-160808-221LMT_2P

GPIO I/F implem ented: tied to +1.8V_S0 GPIO I/F not im plemented: tied to

+1.8V_S0 or 0 o hm to ground

12

R208

@

+3VS

12

C241

12

2

1

C214

C215

1

2

.1U_0402_16V7K

22U_0805_6.3V6M

2

C229

C230

1

0_0402_5%

4.7U_0603_6.3V6K

L16

FBMA-L11-160808-221LMT_2P

C233

1

2

10U_0603_6.3V6M

12

1

C234

2

22U_0805_6.3V6M

1U_0402_6.3V6K

1

C243

C242

2

10U_0603_6.3V6M

2

1

.1U_0402_16V7K

2

1

.1U_0402_16V7K

2

C235

1

C244

2

1U_0402_6.3V6K

1

C249

2

42mA

+VDDIO_33

2

C216

1

.1U_0402_16V7K

+VDDIO_18_FC

0.15mA

2

C231

1

.1U_0402_16V7K

22mA

+VDDPL33_PCIE

1

C232

1115mA

2

+PCIE_VDDAN

2.2U_0603_6.3V6K

2

C236

15mA

1

.1U_0402_16V7K

+VDDPL_33_SATA

+AVDD_SATA

1354mA

534mA

+AVDD_USB

1

C245

2

.1U_0402_16V7K

1U_0402_6.3V6K

88mA

+VDDAN_11_USB

2

C250

1

.1U_0402_16V7K

2.2U_0603_6.3V6K

U5C

AH1

VDDIO_33_PCIGP_1

V6

VDDIO_33_PCIGP_2

Y19

VDDIO_33_PCIGP_3

AE5

VDDIO_33_PCIGP_4

AC21

VDDIO_33_PCIGP_5

AA2

VDDIO_33_PCIGP_6

AB4

VDDIO_33_PCIGP_7

AC8

VDDIO_33_PCIGP_8

AA7

VDDIO_33_PCIGP_9

AA9

VDDIO_33_PCIGP_10

AF7

VDDIO_33_PCIGP_11

AA19

VDDIO_33_PCIGP_12

AF22

VDDIO_18_FC_1

AE25

VDDIO_18_FC_2

AF24

VDDIO_18_FC_3

AC22

VDDIO_18_FC_4

AE28

VDDPL_33_PCIE

U26

VDDAN_11_PCIE_1

V22

VDDAN_11_PCIE_2

V26

VDDAN_11_PCIE_3

V27

VDDAN_11_PCIE_4

V28

VDDAN_11_PCIE_5

V29

VDDAN_11_PCIE_6

W22

VDDAN_11_PCIE_7

W26

VDDAN_11_PCIE_8

AD14

VDDPL_33_SATA

AJ20

VDDAN_11_SATA_1

AF18

VDDAN_11_SATA_4

AH20

VDDAN_11_SATA_2

AG19

VDDAN_11_SATA_3

AE18

VDDAN_11_SATA_5

AD18

VDDAN_11_SATA_6

AE16

VDDAN_11_SATA_7

A18

VDDAN_33_USB_S_1

A19

VDDAN_33_USB_S_2

A20

VDDAN_33_USB_S_3

B18

VDDAN_33_USB_S_4

B19

VDDAN_33_USB_S_5

B20

VDDAN_33_USB_S_6

C18

VDDAN_33_USB_S_7

C20

VDDAN_33_USB_S_8

D18

VDDAN_33_USB_S_9

D19

VDDAN_33_USB_S_10

D20

VDDAN_33_USB_S_11

E19

VDDAN_33_USB_S_12

C11

VDDAN_11_USB_S_1

D11

VDDAN_11_USB_S_2

S IC 218-0792006 A13 HUDSON-M1 FCBGA 0FA

POWER

PCI/GPIO I/O

FLASH I/O

PCI EXPRESS

SERIAL ATA

USB I/O

VDDCR_11_1 VDDCR_11_2 VDDCR_11_3 VDDCR_11_4 VDDCR_11_5 VDDCR_11_6 VDDCR_11_7 VDDCR_11_8 VDDCR_11_9

VDDAN_11_CLK_1 VDDAN_11_CLK_2 VDDAN_11_CLK_3 VDDAN_11_CLK_4 VDDAN_11_CLK_5 VDDAN_11_CLK_6 VDDAN_11_CLK_7 VDDAN_11_CLK_8

VDDRF_GBE_S

VDDIO_33_GBE_S

GBE LAN

VDDCR_11_GBE_S_1 VDDCR_11_GBE_S_2

VDDIO_GBE_S_1 VDDIO_GBE_S_2

VDDIO_33_S_1 VDDIO_33_S_2 VDDIO_33_S_3 VDDIO_33_S_4 VDDIO_33_S_5 VDDIO_33_S_6 VDDIO_33_S_7 VDDIO_33_S_8

CORE S5CORE S0 CLKGEN I/O 3.3V_S5 I/O

VDDCR_11_S_1 VDDCR_11_S_2

VDDIO_AZ_S

VDDCR_11_USB_S_1 VDDCR_11_USB_S_2

VDDPL_33_SYS

PLL

VDDPL_11_SYS_S

VDDPL_33_USB_S

VDDAN_33_HWM _S

VDDXL_33_S

N13 R15 N17 U13 U17 V12 V18 W12 W18

+VDDAN_11_CLK

K28 K29 J28 K26 J21 J20 K21 J22

V1

M10

L7 L9

M6 P8

A21 D21 B21 K10 L10 J9 T6 T8

F26 G26

M8

A11 B11

M21

L22

F19

D6

+VDDXL_33_S

L20

5mA

790mA

382mA

49mA

58mA

+VDDCR_11_USB

1

C217

2

1

C224

2

+VDDIO_33_S

15mA

+VDDIO_AZ

+VDDPL33

+VDDPL11

+AVDD_USB

+VDDAN33_HWM

1

C251

2

1

C218

2

.1U_0402_16V7K

1

C225

2

.1U_0402_16V7K

1

C237

2

2.2U_0603_6.3V6K

1

C239

2

1U_0402_6.3V6K

46mA

65mA

16mA

12mA

FBMA-L11-160808-221LMT_2P

2.2U_0603_6.3V6K

+1.1VS

1

C219

C220

2

1U_0402_6.3V6K

1

C226

C227

2

1U_0402_6.3V6K

1

C221

2

1U_0402_6.3V6K

10U_0603_6.3V6M

L15

1

C228

2

1U_0402_6.3V6K

L15

FBMA-L11-201209-221LMA30T_0805

22U_0805_6.3V6M

8/23 Add R346 R347, +VDDIO_33, +VDDIO_33_S

R347

1 2

0_0603_5%

1

C238

2

2.2U_0603_6.3V6K

0_0603_5%

165mA

1

C240

2

1U_0402_6.3V6K

L21

+1.1VALW

1

C248

C246

2

.1U_0402_16V7K

12

+3VS

C248

C247

2

.1U_0402_16V7K

+1.1VS

1

+

C222

C222 330U_2.5V_M

330U_2.5V_M

12

+1.1VS

2

SF000002Z00

8/25 Change C222 from poly-cap to E-cap (SF000002Z00)

+3VALW

L19

1

2

1 2

0_0805_5%

10U_0603_6.3V6M

+1.1VALW

1

C223

2

10U_0603_6.3V6M

+AVDD_SATA

1

C257

2

.1U_0402_16V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

A

+VDDPL_33_SATA

+VDDPL11

+VDDPL33

+1.1VS

+3VALW

L23

+3VS

+1.1VALW

4 4

+3VS

L23

FBMA-L11-160808-221LMT_2P

C252 2.2U_0603_6.3V6KC252 2.2U_0603_6.3V6K

1 2

L24

FBMA-L11-160808-221LMT_2P

C259 2.2U_0603_6.3V6KC259 2.2U_0603_6.3V6K

1 2

L27

FBMA-L11-160808-221LMT_2P

C262 2.2U_0603_6.3V6KC262 2.2U_0603_6.3V6K

1 2

L22

L25

HWM@

12

B

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-160808-221LMT_2P

L25

0_0603_5%

SD013000080

NONHWM@

C253

1

C260

2

HWM@ C260

HWM@

2

22U_0805_6.3V6M

1U_0402_6.3V6K

+VDDAN33_HWM

2

9/3 Change L26 to L25(NONHWM@)

C261

1

.1U_0402_16V7K

2.2U_0603_6.3V6K

1

C254

C253

1

C256

C255

2

1U_0402_6.3V6K

+VDDIO_AZ +3VALW

1 2

R209 0_0603_5%R209 0_0603_5%

1

C258

2.2U_0603_6.3V6K

2

2010/08/12 2012/08/12

C

1 2

R210 0_0603_5%@R210 0_0603_5%@

For 3V AZ device

Compal Secret Data

Deciphered Date

+1.5V

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

FCH PWR

P0VE6 Schematics

14 36Wednesday, November 17, 2010

E

1.0

5

U5D

Y14

VSSIO_SATA_1

Y16

VSSIO_SATA_2

AB16

VSSIO_SATA_3

AC14

VSSIO_SATA_4

AE12

VSSIO_SATA_5

AE14

VSSIO_SATA_6

AF9

VSSIO_SATA_7

AF11

VSSIO_SATA_8

AF13

D D

C C

B B

A A

VSSIO_SATA_9

AF16

VSSIO_SATA_10

AG8

VSSIO_SATA_11

AH7

VSSIO_SATA_12

AH11

VSSIO_SATA_13

AH13

VSSIO_SATA_14

AH16

VSSIO_SATA_15

AJ7

VSSIO_SATA_16

AJ11

VSSIO_SATA_17

AJ13

VSSIO_SATA_18

AJ16

VSSIO_SATA_19

A9

VSSIO_USB_1

B10

VSSIO_USB_2

K11

VSSIO_USB_3

B9

VSSIO_USB_4

D10

VSSIO_USB_5

D12

VSSIO_USB_6

D14

VSSIO_USB_7

D17

VSSIO_USB_8

E9

VSSIO_USB_9

F9

VSSIO_USB_10

F12

VSSIO_USB_11

F14

VSSIO_USB_12

F16

VSSIO_USB_13

C9

VSSIO_USB_14

G11

VSSIO_USB_15

F18

VSSIO_USB_16

D9

VSSIO_USB_17

H12

VSSIO_USB_18

H14

VSSIO_USB_19

H16

VSSIO_USB_20

H18

VSSIO_USB_21

J11

VSSIO_USB_22

J19

VSSIO_USB_23

K12

VSSIO_USB_24

K14

VSSIO_USB_25

K16

VSSIO_USB_26

K18

VSSIO_USB_27

H19

VSSIO_USB_28

Y4

EFUSE

D8

VSSAN_HWM

M19

VSSXL

P21

VSSIO_PCIECLK_1

P20

VSSIO_PCIECLK_2

M22

VSSIO_PCIECLK_3

M24

VSSIO_PCIECLK_4

M26

VSSIO_PCIECLK_5

P22

VSSIO_PCIECLK_6

P24

VSSIO_PCIECLK_7

P26

VSSIO_PCIECLK_8

T20

VSSIO_PCIECLK_9

T22

VSSIO_PCIECLK_10

T24

VSSIO_PCIECLK_11

V20

VSSIO_PCIECLK_12

J23

VSSIO_PCIECLK_13

S IC 218-0792006 A13 HUDSON-M1 FCBGA 0FA

GND

VSSIO_PCIECLK_14 VSSIO_PCIECLK_15 VSSIO_PCIECLK_16 VSSIO_PCIECLK_17 VSSIO_PCIECLK_18 VSSIO_PCIECLK_19 VSSIO_PCIECLK_20 VSSIO_PCIECLK_21 VSSIO_PCIECLK_22 VSSIO_PCIECLK_23 VSSIO_PCIECLK_24 VSSIO_PCIECLK_25 VSSIO_PCIECLK_26 VSSIO_PCIECLK_27

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8

VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52

VSSPL_SYS

AJ2 A28 A2 E5 D23 E25 E6 F24 N15 R13 R17 T10 P10 V11 U15 M18 V19 M11 L12 L18 J7 P3 V4 AD6 AD4 AB7 AC9 V8 W9 W10 AJ28 B29 U4 Y18 Y10 Y12 Y11 AA11 AA12 G4 J4 G8 G9 M12 AF25 H7 AH29 V10 P6 N4 L4 L8

M20

H23 H26 AA21 AA23 AB23 AD23 AA26 AC26 Y20 W21 W20 AE26 L21 K20

4

REQUIRED STRAPS

PULL HIGH

PULL LOW

3

PCI_CLK1

ALLOW PCIE GEN2

*

FORCE PCIE GEN1

PCI_CLK3

USE DEBUG STRAP

IGNORE DEBUG STRAP

Check Internal PU/PD

PCI_CLK4

Reserved

CLKGEN Mode

Internal

LPC_CLK0

internal EC ENABLE

internal EC DISABLE

2

CLK_PCI_DB

Internal CLKGEN Mode

*

External CLKGEN Mode

1

* * *

+3VS +3VS +3VS +3VALW +3VALW

12

R212

R213

R211

10K_0402_5%

R213

@

10K_0402_5%

12

R214

@

10K_0402_5%

12

R215

10K_0402_5%

9/13 Change R211 from mount to @, R216 from @ to mount

9/13 Change R211 from @ to mount, R216 from mount to @

PCI_CLK1<11> PCI_CLK3<11> PCI_CLK4<11> LPCCLK0<11> CLK_PCI_DB< 11>

12

R217

R216

@

10K_0402_5%

R218

10K_0402_5%

12

R219

10K_0402_5%

12

R220

@

10K_0402_5%

DEBUG STRAPS

FCH M1 HAS 15K INTERNAL PU FOR PCI_AD[27:23]

PCI_AD25 PCI_AD24

Selects FC PLL

PULL HIGH

PCI_AD27

USE internal PLL generated PLL CLK

PCI_AD26

ILA AUTORUN Disabled

* * * * *

PULL LOW

BYPASS PCI PLL

ILA AUTORUN

Enabled

FC PLL bypassed

check defaultCheck AD29,AD28 strap function

Getting Value from I2C EPROM

Disable I2C ROM

PCI_AD23 Enable ROM Straps

Required Setting

Reserved

PCI_AD27<11> PCI_AD26<11> PCI_AD25<11> PCI_AD24<11> PCI_AD23<11>

12

R221

R222

R223

2.2K_0402_5%

@

12

R225

R224

2.2K_0402_5%

@

Security Classification

2010/08/12 2012/08/12

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

2010/08/12 2012/08/12

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Nu mber Rev

B

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

FCH-VSS/Strap

P0VE6 Schematics

15 36Wednesday, November 17, 2010

1

1.0

5

Port Configuration

Port A: H eadphone j ack (jack shared wit h S/PDIF) Port B: I nternal MI C (mono or stereo) Port C: M icrophone/ LI/LO jack Port D: L ine Out ja ck (Option al) Port E: L ine In jac k (Optiona l) Port F: N ot used. Port G: I nternal st ereo speak ers Port J: I nternal st ereo digit al mic (Op tional)

D D

Port H: S /PDIF (jac k shared w ith headph one)

RA55 0_0603_5%RA55 0_0603_5%

1 2

+3VS

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

1U_0402_6.3V6K

HP_LEFT

HP_RIGHT

1

2

MIC1_C_L

MIC1_C_R

MONO_IN

SENSEA

1 2

+AVEE

1

CA11

CA11 10U_0805_10V6K

10U_0805_10V6K

2

0.1U_0402_16V4Z

1

CA21

2

1

CA3

2

0.1U_0402_16V4Z

20 mil

+3VS_VAUX

UA1

25

26

27

28

33

34

41

42

22

23

35

36

37

13

12

44 43

47

48

24

49

CX20584-11Z_QFN48_7X7

SA000034010

08/25 Add UA1 PN:SA000034010

10/11 Update UA1 PN:SA000034020

10/12 Update UA1 PN:SA000034010

10U_0805_10V6K

CA19

1

2

HP_LEFT<23>

HP_RIGHT<23>

CA19

CA23

CA23 10U_0805_10V6K

10U_0805_10V6K

@

RA31

+1.5VS

9/3 Change CA38~ CA43 from 4.7U to 2.2U Change RA16 from 1k to 100 ohm

RA56 0_0603_5%RA56 0_0603_5%

1 2

+3VS

C C

1 2

+3VS

RA32 0_0603_5%RA32 0_0603_5%

0_0603_5%

0.1U_0402_16V4Z

1

CA22

2

9/3 Change RA17 from 1k to 0 ohm

CA2

1U_0402_6.3V6K

MIC1_L

CA38

12

EAPD<25>

1 2

CA39

1 2

+MIC1_VREFO

20 mil

EC_MUTE#<25>

2.2U_0603_6.3V6K

RA29 0_0402_5%RA29 0_0402_5%

MIC1_L<23>

B B

MIC_PLUG#<23>

MIC1_R<23>

+3VS

HP_PLUG#

MIC_PLUG#

COM_MIC_PLUG#

11/17 Change RA33 from mount to @

MIC1_R

RA7

1 2

5.11K_0402_1%

RA34 39.2K_0402_1%RA34 39.2K_0402_1%

1 2

RA18 10K_0402_1%RA18 10K_0402_1%

@

RA33 20K_0402_1%

9/7 Add 0.1U (CA50) between GND & GNDA

20 mil

1

CA10

0.1U_0402_16V4Z

1 2

CA50 0.1U_0402_16V4ZCA50 0.1U_0402_16V4Z

A A

1 2

RA39 0_0402_5%RA39 0_0402_5%

1 2

RA36 0_0402_5%RA36 0_0402_5%

1 2

RA37 0_0402_5%RA37 0_0402_5%

1 2

RA38 0_0402_5%RA38 0_0402_5%

0.1U_0402_16V4Z

2

08/25 Change CA1,CA2,CA3,CA4 to SE000000K80 Standard Part

GND GNDA

5

4

08/19 Follow NTUC0

40 mil

+3VS_DVDD

CA20

20 mil

+VDD_IO

1

CA24

2

4

PORTA_L

PORTA_R

VAUX_3.3

PORTD_L

PORTD_R

PORTE_L

PORTE_R

PORTF_L

PORTF_R

FLY_P

FLY_N

PORTC_L

PORTC_R

C_BIAS

PCBEEP

EXT_MUTE#

SENSE A SENSE B

GPIO0/EAPD#

SPDIFO

AVEE

EP_GND

4

3

11/04 Change RA19 RA20 from 47k to 10k

CA33

RA19 10K_0402_5%RA19 10K_0402_5%

BEEP#<25>

FCH_SPKR<12>

1 2

RA20 10K_0402_5%RA20 10K_0402_5%

1 2

RA21

10K_0402_5%

12

1 2

0.1U_0402_16V4Z

1

CA32

@

0.1U_0402_16V4Z

2

CA33

MONO_IN

2

CA34

@ CA34

@

100P_0402_50V8J

1

Int. Speaker Conn.

SPKL+ SPKL-

SPKR-

20mil

08/21 Follow PAV70

9/25 Add RA54~RA56

RA54 0_0805_5%RA54 0_0805_5%

1 2

+5VS

60 mil

+5VS_AVDD

12

RA40

0.1_1206_1%

0.1U_0402_16V4Z

CA12

08/25 Change CA5,CA8,CA11,CA13,CA17,CA18,CA19,CA23,CA25,CA26 to SE000004880 Standard Part

1

CA13

CA13 10U_0805_10V6K

10U_0805_10V6K

2

9/6 Update QA2 symbol

Combo Jack

10/26 Remove DA4 CA46 CA47 RA23 RA24

10/28 Add JSPK1 (2 pin)

10/28 Add DA4 CA46 CA47 RA23 RA24

10/11 Change RA40 to 0 ohm (1206)

60 mil

+CLASSD_5V

1

CA14

2

0.1U_0402_16V4Z

18

21

29

9

VDD_IO

AVDD_HP

DVDD_3.3

GPIO1/SPK_MUTE#

15

31

LPWR5.0

AVDD_5V

SPK_OUT_L+

SPK_OUT_L-

SPK_OUT_R+

SPK_OUT_R-

SDATA_OUT

DMIC_CLK0

GPIO2/SPDIF2

20

RPWR5.0

CLASSDREF

PORTB_L

PORTB_R

B_BIAS

SDATA_IN

SYNC

RESET#

BIT_CLK

GND

DMIC_1/2

FILT_1.8

FILT_1.65

AVDD_3.3

0.1U_0402_16V4Z

14

16

19

17

MIC2_C_L

39

MIC2_C_R

40

38

HDA_SDIN0_AUDIO

8

6

10

11

HDA_BITCLK_AUDIO_R

7

1

DMIC_CLK_R

2

3

46 45

5

32

+LDO_OUT_3.3V

30

CA6

10/12 Change RA40 to 0.1 ohm (1206)

0.1U_0402_16V4Z

1

CA15

2

0.1U_0402_16V4Z

1

CA16

2

10U_0805_10V6K

1

CA17

CA18

CA18 10U_0805_10V6K

2

10U_0805_10V6K

2

0.1U_0402_16V4Z

10/26 Remove SPKR+ SPKR- function

SPKL+

SPKL-

SPKR+

11/17 Change CA40,CA41,RA16 from mount to @

SPKR-

1 2

2.2U_0603_6.3V6K

1 2

2.2U_0603_6.3V6K

+B_BIAS

HDA_SDOUT_AUDIO <12>

HDA_SYNC_AUDIO <12>

HDA_RST_AUDIO# < 12>

RA28 0_0402_5%RA28 0_0402_5%

1 2

@

1 2

90.9_0402_1%

MIC2_R

CA40

@CA40

@

CA41

@CA41

@

1 2

RA27 33_0402_5%RA27 33_0402_5%

1 2

CA31

22P_0402_50V8J

RA49

1 2

DMIC_CLK0

DMIC_DATA0

9/6 UA1 Pin 1 link to GNDA

9/7 Change UA1 Pin1 to GND

+FILT_1.8V

+FILT_1.65V

1

2

20 mil

1U_0402_6.3V6K

CA1

+LDO_OUT_3.3V

1

20 mil

CA5

CA5 10U_0805_10V6K

10U_0805_10V6K

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CA1

3

HP_SENSE<23>

RA16

COM_MIC

@

1 2

100_0402_1%

HDA_SDIN0 <12>

@

CA48

1 2

22P_0402_50V8J

CA36

22P_0402_50V8J

HDA_BITCLK_AUDIO <12>

22P_0402_50V8J

@

Layout Note: close to UA1

RA51 0_0402_5%RA51 0_0402_5%

RA53 0_0402_5%RA53 0_0402_5%

9/13 Add RA50~RA53 for DMIC

10/01 Remove RA50,R52

0.1U_0402_16V4Z

1

CA7

2

0.1U_0402_16V4Z

2010/08/12 2012/08/12

HP_SENSE

RA10 20K_0402_5%RA10 20K_040 2_5%

RA41

47K_0402_5%

1

2

1 2

9/1 Add CA49 RA41 on HP_SENSE

08/31 Reserve CA48(22P) on HDA_SDOUT_AUDIO

1 2

10U_0805_10V6K

1

CA8

CA9

2

Compal Secret Data

12

1

2

10K_0402_5%

Deciphered Date

2

RA22 0_0603_5%RA22 0_0603_5%

1 2

RA25 0_0603_5%RA25 0_0603_5%

1 2

RA23 0_0603_5%RA23 0_0603_5%

1 2

RA24 0_0603_5%RA24 0_0603_5%

1 2

PJDLC05C_SOT23-3

11/17 Change RA11, RA9, CA4, QA1 from mount to @

@

1 2

RA11 20K_0402_5%

1 2

CA49

0.1U_0402_16V4Z

RA26

2

G

DMIC_CLK <23>

DMIC_DATA <2 3>

Combo Jack

2

1

JSPK2

SPK_L+

1

SPK_L-

2

SPK_R+SPKR+

3

5

3

SPK_L-

@

4

G1

6

4

G2

ACES_88266-04001

CONN@

JSPK1

1

2

3

G1

4

G2

ACES_88266-02001

CONN@

COM_MIC

2

3

DA5

@

1

HP_PLUG#

61

D

QA2A

QA2A DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

S

2

3

DA4

DA4 PJDLC05C_SOT23-3

PJDLC05C_SOT23-3

@

1

1000P_0402_50V7K

5

G

QA1

BSS138_NL_SOT23-3

@

1

CA44

2

1000P_0402_50V7K

COM_MIC_PLUG#

34

D

QA2B

QA2B DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

S

13

D

2

G

S

SPK_R-

SPK_L+

1000P_0402_50V7K

1

CA45

2

1

CA46

CA47

1000P_0402_50V7K

2

1 2

RA9

RA9 10K_0402_5%

10K_0402_5%

1

@

CA4

CA4 1U_0402_6.3V6K

1U_0402_6.3V6K

2

10/28 Reserve CA57 CA58 for EMI

11/01 Change CA57, CA58 from @ to mount

+3VALW

1

CA58

220P_0402_50V7K

2

1

CA57

220P_0402_50V7K

2

9/13 Remove Analog MIC circuit9/13 Add RA49 for DMIC

11/17 Change RA12,RA14,CA25 from mount to @

RA12

COM_MIC

@

1 2

2.2K_0402_5%

RA14

@

+LDO_OUT_3.3V +B_BIAS

1 2

1K_0402_5%

Title

Size Document Number Rev

Custom

Date: Sheet of

2.2K_0402_5%

COM_MIC_R

1

@

CA25

CA25 10U_0805_10V6K

10U_0805_10V6K

2

Compal Electronics, Inc.

RA35 0_0402_5%

1 2

@

Audio Codec CX20584

P0VE6 Schematics

1

COM_MIC <23>

16 36Wednesday, November 17, 2010

1.0

5

+3V_LAN

RL15 4.7K_0402_5%@RL15 4.7K_0402_5%@ RL16 4.7K_0402_5%@RL16 4.7K_0402_5%@

D D

12 12

LAN_CLKREQ#_R PLT_RST#

PCIE_FRX_DTX_P2<11>

PCIE_FRX_DTX_N2<11>

PCIE_FTX_C_DRX_P2<11>

PCIE_FTX_C_DRX_N2<11>

CLK_PCIE_LAN<11> CLK_PCIE_LAN#<11>

LAN_CLKREQ#<12>

PLT_RST#<11,19,20,25>

LAN_WAKE#<25>

FCH_PCIE_WAKE#<12,19,20>

8/23 Reserve 4.7k(RL15) to +3V_LAN on PLT_RST# Reserve 4.7k(RL16) to +3V_LAN on LAN_CLKREQ#_R

PCIE_C_RXP1

12

CL6 .1U_0402_16V7KCL6 .1U_0402_16V7K

CL9 .1U_0402_16V7KCL9 .1U_0402_16V7K

1 2

RL12 0_0402_5%RL12 0_0402_5%

1 2

RL14 0_0402_5%RL14 0_0402_5%

12

CLK_PCIE_LAN CLK_PCIE_LAN#

LAN_CLKREQ#_R

PLT_RST#

PCIE_C_RXN1

2010.08.21 Follow PAWGC

Change YL1 to SJ100003300 2010/04/06

YL1

1 2

25MHZ_20PF_7A25000012

2

CL10

CL10 27P_0402_50V8J

27P_0402_50V8J

1

C C

LAN Power circuit refer to NAU00

RL13 0_0603_5%RL13 0_0603_5%

+3VALW

B B

1 2

@

QL1

AP2301GN-HF_SOT23-3

3 1

2

RL18 10K_040 2_5%@RL18 10K_0402_5%@

1 2

2

CL41

@

0.1U_0402_16V4Z

1

9/21 Change QL1 from SB934130000 to SB934130020

9/25 Change QL1 to SB000007H10

LL2

+VDDCT +VDDCT_L

MURATA_BLM18AG601SN1D _0603

LL2

12

close to LL2

1U_0402_6.3V6K

A A

AR8152 Pin No. Description

LED[0] 38

LED[1]

39

5

9/9 Change RL14 from @ to mount

DL8

@DL8

LAN_X2LAN_X1

2

10/11 Change DL8 to SCS00000Z00

CL11

CL11 27P_0402_50V8J

27P_0402_50V8J

1

@

12

RB751V-40_SOD323-2

9/23 Reserve DL8 on LAN_CLKREQ#

W=40mils

CL5

+3V_LAN

1

2

1000P_0402_50V7K

1A

1

CL8

CL7

2

0.1U_0402_16V4Z

close to LAN Pin 1

EN_WOL# <25 >

9/2 Reserve Q36, R374, C387 for EN_WOL#

9/2 Change R374 to RL18, C387 to CL41 Q36 to QL1

LAN_MDI1+ LAN_MDI1-

LAN_MDI0+

LAN_MDI0-

1

CL25

CL35

@

2

1

CL31

2

1000P_0402_50V7K

1

CL36

CL29

@

2

0.1U_0402_16V4Z

1000P_0402_50V7K

close to TL1

PU/PD

L

un-overclocking

H

overclocking

L

LDO mode

H

SWR mode

LAN_CLKREQ#_RLAN_CLKREQ#

1

2

1U_0402_6.3V6K

SMF10A_SOD-123FL2

LAN_WAKE#

LAN_X1 LAN_X2

CL1

@

DL2

@

DL3

@

DL4

@

DL5

4

UL1

30

TX_P

29

35

36

33 32

23

2

3

25 26

28 27 41

7 8

16 17 18 19 20 21 13

AR8152-AL1E

TX_N

RX_P

RX_N

REFCLK_P REFCLK_N

CLKREQ#

PERST#

WAKE#

SMCLK SMDATA

TEST_RST TESTMODE GND

XTLO XTLI

NC NC NC NC NC NC NC

LED_LINK10_100#

VDDCT_REG

DVDDL_REG

AVDDH_REG

AR8152L PN:SA00003JW30

8/25 Change UL1 P/N to SA00003JW30

+AVDDL +AVDDH

1

CL34

2

10U_0603_6.3V6M

8/26 Change TL1 P/N to SP050003N00

TL1

1

RD+

2

RD-

3

CT

4

NC

5

NC

6

CT

7

TD+ TD-8TX-

350uH_NS0013LF

SP050003N00

9/2 Reserve DL2~7 for EMI(Need Update)

9/7 Update DL2~DL5 symbol from database

RJ45_MIDI1+

12

RJ45_MIDI1-

12

RJ45_MIDI0+

12

RJ45_MIDI0-

12

4

16

RX+

15

RX-

14

CT

13

NC

12

NC

11

CT

10

TX+

9

B88069X9231T203_4P5X3P2-2

RJ45_MIDI1+ RJ45_MIDI1RJ45_CT0

RJ45_CT1 RJ45_MIDI0+ RJ45_MIDI0-

DL6

@

DL7

@

3

LAN_ACTIVITY#

38

LED_ACT#

TRXP0 TRXN0 TRXP1 TRXN1

RBIAS

VDD33

VDDCT

DVDDL

AVDDH

AVDDL AVDDL

AVDDL_REG

LX

LAN_SK_LAN_LINK#

39

LAN_MDI0+

11

LAN_MDI0-

12

LAN_MDI1+

14

LAN_MDI1-

15

10

W=40mils

1

40

5

+VDDCT_REG

4

24 37

22 9

31 34 6

RL1 49.9_0402_1%RL1 49.9_0402_1% RL2 49.9_0402_1%RL2 49.9_0402_1% RL3 49.9_0402_1%RL3 49.9_0402_1% RL4 49.9_0402_1%RL4 49.9_0402_1%

RL5 2.37K_0402_1%RL5 2.37K_0402_1 %

12

+LX

+DVDDL

+AVDDH

+AVDDL

+3V_LAN

W=40mils

+VDDCT

W=40mils

close to Lan chip

1 2 1 2 1 2 1 2

4.7UH_1008HC-472EJFS-A_5%_1008

close to Lan pin6 close to Lan pin31

CL24

1

2

1U_0402_6.3V6K

RL7

1 2

RL6

1 2

1000P_1206_2KV7K

CL12

75_0402_5%

RJ45_GND

1

2

CL15

1

CL20

2

0.1U_0402_16V4Z

1

2

1

CL16

2

0.1U_0402_16V4Z

9/2 Change R399 to RL17

RJ45_CT0

12

9/3 Remove RL17

9/9 Update DL6~DL7 symbol from database

RJ45_CT1

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

CL3 0.1U_0402_ 16V4ZCL3 0.1U_0402_ 16V4Z

1 2

CL4 0.1U_0402_ 16V4ZCL4 0.1U_0402_ 16V4Z

1 2

RL5 keep away other singal (25mil)

* If SWR mode applied,

Mount LL1, CL30, CL14, CL2, CL13 and CL27. No mount RL11 and CL26. Place LL1 close to LAN Pin40.

* If LDO mode applied,

Mount CL30, CL2, RL11, CL26 and CL27. No mount LL1, CL14 and CL13.

LL1

SWR@ LL1

SWR@

+LX

1 2

+VDDCT +VDDCT_REG

1

CL30

2

0.1U_0402_16V4Z

close to Lan pin5

CL14

SWR@

1

2

1

CL13

CL2

1000P_0402_50V7K

CL13

SWR@

2

10U_0603_6.3V6M

close to Lan pin40

Change CL17, CL21, CL24, CL26 to SE000000K80 2010/04/06

CL21

12

RL10

5.1K_0402_5%

1

2

1

CL22

2

1U_0402_6.3V6K

RL9 511_0402_1%RL9 511_0402_1%

CL23

0.1U_0402_16V4Z

@

CL28

CL28 470P_0402_50V7K

470P_0402_50V7K

12

1

2

0.1U_0402_16V4Z

close to JRJ45

12

LAN_ACTIVITY#_RLAN_ACTIVITY#

RJ45_MIDI1-

For EMI.

@

CL32

CL32 470P_0402_50V7K

470P_0402_50V7K

+3V_LAN

LAN_SK_LAN_LINK#

12

CL33

CL33 470P_0402_50V7K

470P_0402_50V7K

@

511_0402_1%

12

RJ45_MIDI1+

RJ45_MIDI0-

RJ45_MIDI0+

LAN_SK_LAN_LINK#_1

RL8

12

CL38

1000P_1206_2KV7K

RJ45_GND LANGND

1 2

9/2 Reserve R399(0 ohm) on LAN_SK_LAN_LINK#

9/1 Add DL1, CL38~40,LL3 for EMI

9/2 Change RJ45_GND to LANGND on DL1

Compal Secret Data

2010/08/12 2012/08/12

Compal Secret Data

Deciphered Date

2

1

LDO@

1 2

RL11 0_0603_5%

1

2

0.1U_0402_16V4Z

CL26

LDO@

1

2

1

CL27

2

0.1U_0402_16V4Z

1U_0402_6.3V6K

0.1U_0402_16V4Z

close to Lan pin4

+DVDDL

CL17

1

2

1

CL18

2

1U_0402_6.3V6K

0.1U_0402_16V4Z

CL19

1

2

0.1U_0402_16V4Z

close to Lan pin24close to Lan pin37close to Lan pin22close to Lan pin9 close to Lan pin34

JRJ45

11

Yellow LED+

12

Yellow LED-

8

PR4-

7

6

5

4

3

2

1

9

10

DETECT PIN1

PR4+

PR2-

PR3-

PR3+

PR2+

PR1-

PR1+

Green LED+

Green LED-

SANTA_130452-3

CONN@

1

CL39

CL40

2

0.1U_0402_16V4Z

Title

Size Document Number Rev

Custom

Date: Sheet of

15

SHLD1

13

14

SHLD1

LL3 MCK3225201YZF_2PLL3 MCK3225201YZF_2P

1 2

Compal Electronics, Inc.

LAN AR8152

P0VE6 Schematics

LANGND

2

3

1

DL1

DL1 PJDLC05C_SOT23-3

PJDLC05C_SOT23-3

17 36Wednesday, November 17, 2010

1.0

5

+3VS

+3VALW

D D

+VCC_4IN1 +VCC18

20mils 20mils

1

@

C C

B B

A A

@

CC3

CC3 10P_0402_50V8J

10P_0402_50V8J

2

CLK_48M_CR<11>

1

CC4

CC4 10U_0603_6.3V6M

10U_0603_6.3V6M

2

+VCC33

12

RC9

@

33_0402_5%

1

CC13

@ CC13

@

22P_0402_50V8J

2

EMI

2

@

1

091020 change JUMP J2/J3 to RC1/RC2 0ohm

1

@

CC5

0.1U_0402_16V4Z

2

20mils

1

CC8

CC7

0.01U_0402_16V7K

CC8

0.1U_0402_16V4Z

2

RC8

6250@R C8

6250@

1 2

0_0402_5%

CC11

1 2

18P_0402_50V8J

6252@

12MHZ_16PF_7A12000026

CC15

1 2

18P_0402_50V8J

6252@

1 2

YC1

6252@

1

2

4

RC1

0_0603_5%

@

RC2

0_0603_5%

CC4 close to UC1.28 CC9 close to UC1.15

1

CC6

4.7U_0603_6.3V6K

2

CC9

4.7U_0603_6.3V6K

ByPass Cap acitors

XTLI

12

Only UB625 2 need to us e XTLI and XTLO

0911 change YC1 to SJ100005900

XTLO

1

CC1

CC1 10U_0603_6.3V6M

10U_0603_6.3V6M

2

20mils

+3VS_READER

1

CC2

0.1U_0402_16V4Z

2

@

3

UC1

UB6250NF-A1-110_QFN3 2_5X5

SA00003FJ00

6250@

8/25 Co-lay UB6252 (6252@)

RC3

RC3 12K_0402_1%

12K_0402_1%

1 2

+VCC_4IN1

+3VS_READER

+VCC33 +VCC18

USB20_P6<12> USB20_N6<12>

XTLI

Clock from M/B

2

REXT

CARD_D0 CARD_D1 CARD_D2 CARD_D3 CARD_D4 CARD_D5 CARD_D6 CARD_D7

8/26 Change UC1 to UB6252 (SA00003K010)

If use external crystal (YC1),

8/24 Card_LED# Follow PAV70

+VCC33

12

@

RC10

10K_0402_5%

CARD_LED_R#

RC11

+VCC_4IN1

12

@

UC1 will change to UB6252

@

RC12

0_0402_5%

S

Card Reader Connector

JREAD1

+VCC_4IN1 +VCC_4IN1

CARD_D0 CARD_D1 CARD_D2 CARD_D3 CARD_D4 CARD_D5 CARD_D6 CARD_D7

PIN3 SMWPZ SMALE_CLK SMCDZ_MSINSZ SMBSYZ_SDCMD SMREZ_C SMCEZ_C SMCLE

22

XD-VCC

30

XD10-D0

29

XD11-D1

28

XD12-D2

27

XD13-D3

26

XD14-D4

25

XD15-D5

24

XD16-D6

23

XD17-D7

33

XD07-WE

32

XD08-WP

34

XD06-ALE

39

XD01-CD

38

XD02-R/B

37

XD03-RE

36

XD04-CE

35

XD05-CLE

31

XD GND

40

XD GND

41

SD CD/WP GND

42

SD CD/WP GND

T-SOL_144-1300302600_NR CONN@

2010.08.19 Copy Symbol from NCQF0

SD4-VDD MS9-VCC

SD5-CLK SD7-DAT0 SD8-DAT1 SD9-DAT2 SD1-DAT3

SD2-CMD

SD-CD SD-WP

SD6-VSS

SD3-VSS

MS8-SCLK MS4-DATA0 MS3-DATA1 MS5-DATA2 MS7-DATA3

MS6-INS

MS2-BS

MS1-VSS

MS10-VSS

11 18

9 4 3 21 19 16 1 2

6 13

17 10 8 12 15 14 7 5 20

SMALE_CLK

SMBSYZ_SDCMD

SMALE_CLK

SMCDZ_MSINSZ

10/28 Add RC14 RC15(@) RC16 on SMALE_CLK for EMI

11/04 Change RC15 from @ to mount

1

11/15 Change RC16 P/N from SD028000080 to SM010009E00

UC1 close to JREAD1

UC1

28

CrdVcc

29

SysVcc

30

Vcc33O

31

Vcc18O

33

Thermo Pad

14

D+

13

D-

12

Rref

8

EClkin

17

xDData0

18

xDData1

20

xDData2

21

xDData3

19

xDData4

4

xDData5

5

xDData6

6

xDData7

UB6252NF-A1-110_QFN32_5X5

6252@

+VCC33

12

G

2

13

D

RB751V-40_SOD323-2

QC1

QC1 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

1 2

0_0402_5%

0_0402_5% RC7

RC7

@

VddA

VccA

xDCeZ

xDCle xDAle

xDBsyZ

xDWeZ xDReZ xDWpZ SdCdZ xDCdZ

LedZ

ResetZ

VssA

GndA

NC

0_0402_5%

0_0402_5% RC5

RC5

8/26 Change DC1 to SCS00002G00 Standard Part 8/26 Change QC1 to SB000009610 Standard Part

RC13

0_0402_5%

1 2

DC1

1 2

@

15 10

7 23 24 22

3 25 32 26 27

1

2

16 11 9

+VCC33

SMCEZ_C

SMALE_CLK_R

SMBSYZ_SDCMD

SMREZ_C

SMCDZ_MSINSZ

CARD_LED_R#

XTLO

+3VS

12

RC6

RC6 10K_0402_5%

10K_0402_5%

SMCLE

1 2

FBMA-11-100505-900T 0402

PIN3

RC16

SMWPZ SDCDZ

1 2

SMALE_CLK

RC4

4.7K_0402_5%

@

CARD_LED# <21>

+VCC33

10/08 Change DC1 to SCS00000Z00

CARD_D0 CARD_D1 CARD_D2 CARD_D3

SDCDZ

PIN3

1 2

0_0402_5%

0_0402_5% RC14

RC14

1 2

CC10 4.7P_0402_50V8JCC 10 4.7P_0402_50V8J

11/15 Change CC10 P/N from 22p to 4.7p SE071220J80 to SE07147AC80

11/15 Change P/N CC12, RC15 from mount to @.

@

PIN3

1 2

0_0402_5%

0_0402_5% RC15

RC15

CARD_D0 CARD_D1 CARD_D2 CARD_D3

@

1 2

CC12 22P_0402_50V8 J

SMCDZ_MSINSZ

1

CC14

0.1U_0402_16V4Z

2

11/04 Change CC10 CC12 from 4.7p to 22p

9/2 Change CC11 CC15 from 27P to 18P

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/08/12 2012/08/12

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

CARD READER UB6250/6252

P0VE6 Schematics

18 36Wednesday, November 17, 2010

1

1.0

A

+1.5VS +1.5VS_WWAN

1 1

1 2

R335 0_0805_5%R335 0_0805_5%

8/22 Reserve R335 (0 ohm 0805) Add net +1.5VS_WWAN

8/25 Change C269,C275 to SE000004880 Standard Part

Change JMINI1 to FOX_AS0B246-S50U-7F_52P-T 06/29

10/27 Add R412 (0 ohm) on FCH_PCOE_WAKE#

9/2 Change ICH_PCIE_WAKE# to FCH_PCIE_WAKE#

FCH_PCIE_WAKE#<12,17,20>

WWAN_CLK REQ#<12>

2 2

FCH_PCIE_WAKE#

WWAN_CLK REQ#

CLK_PCIE_WW AN#<11> CLK_PCIE_WW AN<11>

PCIE_FRX_DTX_N1<11> PCIE_FRX_DTX_P1<11>

PCIE_FTX_C_DRX_N1<11> PCIE_FTX_C_DRX_P1<11>

+3VS_WWAN

C275 10U _0805_10V6K 3G_MP@C275 10U_0805_10V6K 3G_MP@

@

1 2

R412 0_0402_5%

1 2

WWAN_W AKEUP_R#

9/9 Remove D9

JSIM1

4

3 3

3G@

3G@ 1

C276

2

56P_0402_50V8

+UIM_PWR

UIM_VPP UIM_DATA

1

12

USB20_P4<12>

C277

2

@

22P_0402_50V8J

10K_0402_5%

USB20_N4<12>

R233

@

Modifiy 05/11

GND

5

VPP

6

I/O

7

DET

8

D+

9

D-

TAITW_PMPAT7-08GLBS1N14H 0

CONN@

VCC

RST CLK

GND GND

B

W=40mil

3G_MP@

1

C263

2

0.1U_0402_16V4Z

W=40mil

3G_MP@

1

C268

0.1U_0402_16V4Z

2

+3VS

R227 0_1206_5%R227 0_1206_5%

JMINI1

1

3

5

7

9

9 111112 131314 151516

171718 191920 212122 232324 252526 272728 292930 313132 333334 353536 373738 393940 414142 434344 454546 474748 494950 515152

53

GND1

55

NC

BELLW_80052-1021

CONN@

W=20mil

+UIM_PWR

1

UIM_RST

2

UIM_CLK

3

1

10 11

1

C278100P_0402_50V8J C278100P_0402_50V8J

C279

2

@

2

+3VS_WWAN

1 2

2 4 6 8

10

GND2

NC

1

C280

2

@

22P_0402_50V8J

+1.5VS_WWAN

3G_MP@

1

2

3G_MP@

1

C269

2

10U_0805_10V6K

+3VS_WWAN

2 4 6 8 10 12 14 16

18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

54 56

1

3G@

2

22P_0402_50V8J

3G_MP@

C264

0.01U_0402_25V7K

8/31 Change MCP@ to 3G_MP@

3G_MP@

0.1U_0402_16V4Z

1

C270

2

@

1 2

R228 0_1206_5%

+UIM_PWR

UIM_DATA UIM_CLK UIM_RST UIM_VPP

WXMIT_OFF#

R229 0_0402_5%R229 0_0402_5%

1 2

WLAN_LED#_R

C28122P_0402_50V8J

3G@

1

2

C282

3G@

1

2

1U_0402_6.3V6K

R232 0_0402_5%R232 0_0402_5%

R230 0_0402_5%R230 0_0402_5%

R231 0_0402_5%R231 0_0402_5%

1 2

C283

C

3G_MP@

1

C265

2

47P_0402_50V8J

3G_MP@

1

C271

0.01U_0402_25V7K

2

+3VALW

1

C266

2

3G_MP@

150U_B_6.3VM_R40M

+1.5VS_WWAN

4.7U_0603_6.3V6K

1

C272

C272 47P_0402_50V8J

47P_0402_50V8J

2

C274

@+C274

@

10/04 Add 100p(C402) on BT_ON#

+3VS_WWAN

1

+

2

Close to WWAN CONN

10/04 Add 100p(C398) on UIM_RST

10/06 Remove C398

WXMIT_OFF# <25> PLT_RST# <11,17,20,25>

9/1 Change R230 R231 from NON3G@ to mount

1 2 1 2

USB20_MINI_N USB20_MINI_P

FCH_SMCLK0 <7,12,20> FCH_SMDAT0 <7,12,20>

WWAN_LED # <20,21> WLAN_LED# <20,21>

(9~16mA)

10/31 Add R417~R420 for co-lay USB port3 & port9

1

C28556P_0402_50V8

1 3G@

3G@

2

C284

0.1U_0402_16V4Z

56P_0402_50V8

WWAN_W AKEUP#<25>

D

BT@

R226

BT_ON#<20,25>

2

BT@ C402

BT@

1

10K_0402_5%

C402 100P_0402_50V8J

100P_0402_50V8J

12

8/26 Change Q13 to SB934130020 Standard Part

USB20_P7<12> USB20_N7<12>

USB20_MINI_N USB20_MINI_P

11/01 Change R417 R418 from mount to @ Change R419 R420 from mount to @ SW request (P0VE6-0045)

9/1 Change R234 from mount to @

+3VALW

12

R234

10K_0402_5% @

1 2

R235 0_0402_5%

@

E

+3VS

1

C267

0.1U_0402_16V4Z

2

BT@C267

BT@

+3VALW +3VS

9/3 Reserver +3VALW for BT (R378 R374)

9/25 Change Q13 to SB000007H10

BT MODULE CONN

R378

R374

0_0603_5%

USB20_P7 USB20_N7

8/22 Update JBT1 Symbol from database (ACES_88266-04001_4P)

1 2

R417 0_0402_5%

1 2

R418 0_0402_5%

1 2

R419 0_0402_5%R419 0_0402_5%

1 2

R420 0_0402_5%R420 0_0402_5%

WWAN_W AKEUP_R#

R378

11/02 Change Q3 PN to SB934130020

0_0603_5%

@

1 2

@

@ @

@

AP2301GN-HF_SOT23-3

+3V_BT

3 1

BT@

2

Q13

+3VS_BT

C273

0.1U_0402_16V4Z

+3VS_BT

USB20_N3 <12> USB20_P3 <12>

USB20_N9 <12> USB20_P9 <12>

BT@

12

JBT1

1

2

3

G1

4

G2

ACES_88266-04001

CONN@

5 6

10/06 Change C278 to 100p

Reserve for SIM card does not meet rise time and pull-up is needed.

8/22 Update JP1 Symbol from database (TAITW_PMPAT7-08GLBS1N14H0_9P)

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/08/12 2012/08/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Mini-Card/BT CONN

P0VE6 Schematics

19 36Wednesday, November 17, 2010

E

1.0

5

Mini-Express Card for WWAN

4

3

2

1

D D

C C

B B

EC_TX_P80_DATA<25> EC_RX_P80_CLK<25>

EC_TX_P80_DATA EC_RX_P80_CLK

0_0402_5%

R236

R237 0_0402_5%R237 0_0402_5%

1 2 1 2

EC_TX_P80_DATA_R EC_TX_P80_CLK_R

+3VS_WLAN

1

C286

4.7U_0603_6.3V6K

2

W=40mil W=40mil

9/2 Change ICH_PCIE_WAKE# to FCH_PCIE_WAKE#

FCH_PCIE_WAKE#<12,17,19>

WLAN_CLKREQ#<12>

PCIE_FRX_DTX_N3<11> PCIE_FRX_DTX_P3<11>

PCIE_FTX_C_DRX_N3<11> PCIE_FTX_C_DRX_P3<11>

BT_ON#<19,25>

CLK_PCIE_WLAN#<11> CLK_PCIE_WLAN<11>

10U_0603_6.3V6M

+3VS_WLAN

Mini-Express Card for WLAN

+1.5VS_WLAN

C292

1

C287

0.1U_0402_16V4Z

2

1

2

R238

R238 0_0402_5%@

0_0402_5%@

1

C288

C288 47P_0402_50V8J

47P_0402_50V8J

2

12

EC_TX_P80_DATA_R EC_TX_P80_CLK_R

12

R243

R243 100K_0402_5%

100K_0402_5%

JMINI2

1

3

5

7

9

9 111112 131314 151516

171718 191920 212122 232324 252526 272728 292930 313132 333334 353536 373738 393940 414142 434344 454546 474748 494950 515152

53

G1

54

G2

BELLW_80052-1021

CONN@

2

4

6

8

10

12 14 16

18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 55

G3

56

G4

1

C289

4.7U_0603_6.3V6K

2

+3VS_WLAN

WWAN_LED #_R

1

C290

0.1U_0402_16V4Z

2

J2

J2 JUMP_43X79

JUMP_43X79

@

2

112

R393 0_0402_5%R393 0_0402_5%

1 2 1 2

R394 0_0402_5%R394 0_0402_5%

R242

0_0402_5%

1 2

1

C291

C291 47P_0402_50V8J

47P_0402_50V8J

2

+3VS

+1.5VS_WLAN

WL_OFF# <25> PLT_RST# <11,17,19,25>

FCH_SMCLK0 <7,12,19> FCH_SMDAT0 <7,12,19>

R241

1 2

0_0402_5%

@

1 2

R336 0_0805_5%R336 0_0805_5%

8/22 Reserve R336 (0 ohm 0805) Add net +1.5VS_WLAN

9/20 Add R393 R394 for SMBus

USB20_N8 <12> USB20_P8 <12>

WWAN_LED # <19,21>

9/17 Remove R239,R240

(9~16mA)

WLAN_LED# <19,21>

+1.5VS_WLAN+1.5VS

5/12 Update WLAN connector(the same as KAV60) 6/1 Revised 37

、、、、39、、、、41、、、、42、、、、

43 to NC 6/12 Update connector to DC040006S00 6/26 Update JMINI1 footprint 7/01 update pin 23,25,31,33

A A

Title

Size D ocument Number Rev

Custom

Date: Sheet of

5

4

3

2

Date: Sheet of

Compal Electronics, Inc.

WLAN

P0VE6 Schematics 1.0

WLAN

LA-6222P

20 36Wednesday, November 17, 2010

1

A

B

C

D

E

F

G

H

10K_0402_5%

4

Y

R373

2

G

+3VS

12

13

D

S

Q35

Q35 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

2

G

MEDIA_LED#

13

D

Q34

S

SSM3K7002FU_SC70-3

LED PCB CONN

JLED1

W=40mil

PWR_LED#<25>

1 1

PWR_SUSP_LED#<25> BATT_BLUE_LED#<25> BATT_AMB_LED#<25>

WWAN_LED #<19,20> WLAN_LED#<19,20>

W=40mil

+3VALW

+3VS

MEDIA_LED#

JLED1

1

2

3

4

5

6

7

8

9

10

11

GND

12

GND

ACES_85201-1205N

CONN@

8/22 Update JP2 Symbol from database (ACES_85201-1605N_16P)

8/24 Update JLED1 Symbol from database (ACES_85201-1205N_12P) & Update pin definition

13 14

9/1 Add LED Circuit (LED2~4(SC597UDB000)LED5(SC51 91NB000), R360~R369, Q3 3)

9/1 Change All LED power to 5V

+3VS

5

U8

2

CARD_LED#<18>

HDD_LED#<13>

HDD_LED#

NC7SZ08P5X_NL_SC70-5

P

B

1

A

G

3

9/1 Add R373, Q34, Q35 for MEDIA_LED#

9/9 Change LED2~4 footprint to LED_HT-297DQ-GQ_4P

2 2

9/11 Remove LED portion

3 3

SATA HDD Conn.

8/22 Reserve R337 R338 Add net +3VS_HDD,+5VS_HDD

JHDD1

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

V33

9

V33

10

V33

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

Reserved

19

GND

20

V12

21

V12

22

V12

SUYIN_127043FR022G263ZR_NR

CONN@

GND

+3VS

+5VS

24

23

1 2

R337 0_0805_5%R337 0_0805_5%

1 2

R338 0_0805_5%R338 0_0805_5%

+3VS_HDD

+5VS_HDD

W=100mil

Security Classification

W=40mil

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2010/08/12 2012/08/12

E

C293

SATA_ITX_DRX_P0 SATA_ITX_DRX_N0

SATA_DTX_IRX_N0

SATA_DTX_IRX_P0

+3VS_HDD

+5VS_HDD

SATA_ITX_DRX_P0<13>

1

C296

2

SATA_DTX_C_IRX_N0

SATA_DTX_C_IRX_P0

1

2

1U_0402_6.3V6K

SATA_DTX_C_IRX_N0<13>

SATA_DTX_C_IRX_P0<13>

+5VS_HDD

0.1U_0402_16V4Z

1

C295

4 4

2

1000P_0402_50V7K

C297

SATA_ITX_DRX_N0<13>

0.01U_0402_16V7K

10U_0805_10V6K

1

C298

2

1 2

C294

0.01U_0402_16V7K

8/22 Change C298 from 10U 6.3V to 10U 10V

A

B

C

9/1 Change Q33 to SB000009610(SSM3K7002FU_SC70-3)

Compal Secret Data

Deciphered Date

F

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

Compal Electronics, Inc.

SATA CONN./LED/B CONN./BATT CONN.

P0VE6 Schematics

G

P0VE6 Schematics

21 36Wednesday, November 17, 2010

H

1.0

ON/OFF Button

SW1

3

1

EVQPLMA15 SPST PANASONIC H1.5

FOR EMI

PWR_LED1#

ON/OFFBTN#

9/6 Change D13 from mount to @

10/05 Remove D13

4

2

C299 100P_0402_50V8J@C299 100P_0402_50V8J@

1 2

C301 100P_0402_50V8J@C301 100P_0402_50V8J@

1 2

ON/OFFBTN#

8/26 Change D11 to SC600000B00 Standard Part

+3VALW

9/20 Remove R245,R248,D12

D11

ON/OFFBTN#

EC_ON<25>

EC_ON

R249

10K_0402_5%

BAV70W_SOT323-3

2

1

3

2

G

1 2

8/26 Change Q14 to SB000009610 Standard Part

R247

100K_0402_5%

1 2

ON/OFF#

51_ON#

2

C300

1000P_0402_50V7K

1

13

D

Q14

Q14 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

ON/OFF# <25>

51_ON# <28>

9/1 Remove LED2 LED3 circuit, Change 70@ to mount

9/20 Add LED2 LED3 Circuit

9/21 Remove LED2 LED3 Circuit

+3VS

(BLUE)

12

51_0402_5%

51_0402_5% R251

R251

21

LED1

LED1 HT-191NB5-DT BLUE 0603

HT-191NB5-DT BLUE 0603

PWR_LED1#

10mil

PWR_LED1# <25>

9/24 Change U9 to SA00001TC00

LID Switch

W=20mil

+3VALW

1

C302

0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/12 2012/08/12

Compal Secret Data

2

Deciphered Date

1

GND

OUTPUT

VDD

U9

AH180WG-7_SC59-3

2

3

C303

1

2

10P_0402_50V8J

LID_SW# <25>

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

Compal Electronics, Inc.

ON/OFF / PWR SW/ LID SW

P0VE6 Schematics

22 36Wednesday, November 17, 2010

1.0

5

4

3

2

1

To TP/B Conn.

D D

KSI[0..7]

KSO[0..15]

KSI0

C304 100P_04 02_50V8JC304 100P_04 02_50V8J

KSI1

C306 100P_04 02_50V8JC306 100P_04 02_50V8J

KSI2

C308 100P_04 02_50V8JC308 100P_04 02_50V8J

KSI3

C310 100P_04 02_50V8JC310 100P_04 02_50V8J

KSI4

C312 100P_04 02_50V8JC312 100P_04 02_50V8J

KSI5

C314 100P_04 02_50V8JC314 100P_04 02_50V8J

KSI6

C316 100P_04 02_50V8JC316 100P_04 02_50V8J

KSI7

C318 100P_04 02_50V8JC318 100P_04 02_50V8J

KSO0

C C

C320 100P_04 02_50V8JC320 100P_04 02_50V8J

KSO1

C322 100P_04 02_50V8JC322 100P_04 02_50V8J

KSO2

C324 100P_04 02_50V8JC324 100P_04 02_50V8J

KSO3

C326 100P_04 02_50V8JC326 100P_04 02_50V8J

1 2

KSI[0..7] <25>

KSO[0..15] <25>

KSO4

KSO5

KSO6

KSO7

KSO8

KSO9

KSO10

KSO11

KSO12

KSO13

KSO14

KSO15

INT_KBD Conn.

JKB1

26

G2

25

KSI0 KSI1

C305 100P_04 02_50V8JC305 100P_04 02_50V8J

1 2

C307 100P_04 02_50V8JC307 100P_04 02_50V8J

1 2

C309 100P_04 02_50V8JC309 100P_04 02_50V8J

1 2

C311 100P_04 02_50V8JC311 100P_04 02_50V8J

1 2

C313 100P_04 02_50V8JC313 100P_04 02_50V8J

1 2

C315 100P_04 02_50V8JC315 100P_04 02_50V8J

1 2

C317 100P_04 02_50V8JC317 100P_04 02_50V8J

1 2

C319 100P_04 02_50V8JC319 100P_04 02_50V8J

1 2

C321 100P_04 02_50V8JC321 100P_04 02_50V8J

1 2

C323 100P_04 02_50V8JC323 100P_04 02_50V8J

1 2

C325 100P_04 02_50V8JC325 100P_04 02_50V8J

1 2

C327 100P_04 02_50V8JC327 100P_04 02_50V8J

1 2

8/22 Update JKB1 Symbol from database (ACES_85202-24051_24P) 8/23 Update KB pin definition

KSI2 KSO0 KSO1 KSO2 KSI3 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSI4 KSO9 KSI5 KSI6 KSO10 KSO11 KSI7 KSO12 KSO13 KSO14 KSO15

G1

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

ACES_85 202-24051

CONN@

8/22 Update JP3 Symbol from database (ACES_85201-0605N_6P)

8/22 Reserve R339 (0 ohm 0402) Add Net name +5VS_TP

W=20mil

TP_DATA<25> TP_CLK<25>

+5VS

0_0402_ 5%

8/24 Update JTP1 Symbol from database (ACES_85201-0405N_4P) & Update pin definition

TP_DATA TP_CLK

12

R339

D14

@

PJDLC05 C_SOT23-3

+5VS_TP

2

3

1

JTP1

1

2

3

4

5

G1

6

G2

ACES_85 201-0405N

CONN@

10/06 Change Jacks GND to GNDA

11/01 Change DA8 from @ to mount

2

CA52

330P_04 02_50V7K

1

HP_SENS E

1

CA56

2

CA52

1

HPOUT_L _2

HPOUT_R _2

+5VS

DA1

@

+3VS

COM_MIC

1 2

RA44 1K_0603_ 5%RA44 1K_0603_ 5%

2

3

1

1 2 3 4

ACES_88 266-04001

CONN@

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CA51

330P_04 02_50V7K

AZ5125-0 2S.R7G_SOT23-3

22P_040 2_50V8J

4

1 2

DA2

HP_SENS E

COM_MIC

2

1

HPOUT_L _1

HPOUT_R _1

2

3

DA8

PJDLC05 C_SOT23-3

1

1 2

LA1 FB MA-L11-160808-7 00LMT_2PLA1 FB MA-L11-160808-7 00LMT_2P

1 2

LA2 FB MA-L11-160808-7 00LMT_2PLA2 FB MA-L11-160808-7 00LMT_2P

9/13 Change AMIC to DMIC

3

22P_040 2_50V8J

CA55

1

2

HP_SENS E<16>

HP_LEFT

B B

HP_LEFT<16>

HP_RIGHT<16 >

RA42 39_0402 _1%RA 42 39_ 0402_1%

HP_RIGHT

RA43 39_0402 _1%RA 43 39_ 0402_1%

10/01 Change RA42 RA43 to 39 ohm 1%

COM_MIC<16>

10/29 Reserve DA8(SCA00001100) on COM_MIC

DMIC_CLK<16 > DMIC_DATA<16>

A A

DMIC_CLK DMIC_DATA

@

PJDLC05 C_SOT23-3

5

Headphone Out (combo jack)

JHP1

3 6

1

2 4

5

SINGA_2SJ 2326-001111

CONN@

MIC1_L< 16>

MIC1_R< 16>

JMIC2

1 2

5

3

G1

6

4

G2

RA45 100_0402 _5%RA45 100_040 2_5%

1 2

RA46

1 2

100_040 2_5%

SM010004010 300ma 70ohm@100mhz DCR 0.3

2010/08/ 12 2012/08/ 12

3

9/28 Change Jacks AGND to GND

9/13 Combine LS-7071PR01_USB_0908.DSN Audio Jack Portion

+MIC1_VRE FO

DA6

RA47

3K_0402 _5%

CA53

220P_04 02_50V7K

1 2

12

MIC1_L_R

MIC1_R_R

1

2

CA54

220P_04 02_50V7K

MIC1_L_1MIC1_L

MIC1_R_1MIC1_R

RB751V-4 0_SOD323-2

LA3

1 2

FBMA-L11 -160808-700LMT _2P

FBMA-L11 -160808-700LMT _2P LA4

LA4

1 2

FBMA-L11 -160808-700LMT _2P

9/14 Update JMIC1 to DC230007700(SUYIN_010030HR006G129ZR_6P)

9/17 Update JMIC1 to DC230004K00(SINGA_2SJ-A960-C01_6P)

Compal Secret Data

Deciphered Date

2

MIC_PLUG#<16 >

MIC_PLUG#

10/08 Change DA6,DA7 to SCS00000Z00

DA7

DA7 RB751V-4 0_SOD323-2

RB751V-4 0_SOD323-2

1 2

+MIC1_VRE FOL+MIC1_VRE FOR

12

RA48

3K_0402 _5%

2

3

1

2

Title

Size Document N umber Rev

B

Date: Sheet of

MIC_PLUG#

@

DA3

PJDLC05 C_SOT23-3

1

Compal Electronics, Inc.

KB Conn/TP/CR Conn

P0VE6 Schematics

MIC JACK

JMIC1

1 6

2

3

4

5

SINGA_2SJ -A960-C01

CONN@

23 36Wednesd ay, November 17, 201 0

1

1.0

A

B

C

D

E

USB Charge Follow PAWGC

9/1 Add R370 R371 for OC circuit

9/15 remove R370 R371 for OC circuit

1 1

C3870.1U_0402_16V4Z C3870.1U_040 2_16V4Z

12

C3940.1U_0402_16V4Z C3940.1U_040 2_16V4Z

12

C3950.1U_0402_16V4Z C3950.1U_040 2_16V4Z

12

+5VALW

W=80mils W=80mils

U18

1

GND

2

VIN VIN3VOUT

4

EN

USB_ON#

+USB_VCCC

8

VOUT

7

VOUT

6 5

FLG

EPAD

AP2301MPG-13_MSOP8

9

SA00003XM00

1

2

9/29 Add C394,C395(0.1U) Close to U18

9/11 Combine USB/B circuit

+USB_VCCC

C4130.1U_04 02_16V4Z C4130.1U_0402_16V4Z

2 2

12

C4140.1U_04 02_16V4Z C4140.1U_0402_16V4Z

12

10/29 Add C413~C414(0.1U) on +USB_VCCC

9/11 Change C340 C389 to SGA00002N80

9/24 Change U11,U18 to SA00003XM00

8/25 Remove Charge USB Circuit

SGA00002N80

USB_OC0# <12>

C388

1000P_0402_50V7K@

C389

150U_B2_6.3VM_R35M

C389

USB20_N1_1 USB20_P1_1

PJDLC05C_SOT23-3

USB20_N0_1 USB20_P0_1

PJDLC05C_SOT23-3

+USB_VCCC

1

2

D21

+USB_VCCC

D22

+

+USB_VCCC

3

@

1

+USB_VCCC

3

@

1

2

W=80mils

1

C390

470P_0402_50V7K

2

W=80mils

1

C391

470P_0402_50V7K

2

Left Side USB CONN.

JUSB3

1

VCC

2

D-

3

D+

4

GND

5

GND1

6

GND2

7

GND3

8

GND4

SUYIN_020133GB004M25MZL

CONN@

JUSB2

1

VCC

2

D-

3

D+

4

GND

5

GND1

6

GND2

7

GND3

8

GND4

SUYIN_020133GB004M25MZL

CONN@

R388

R388 0_0402_5%

0_0402_5%

@

1 2

L31

USB20_N1_1

USB20_N1<12>

USB20_P1<12>

2

3

WCM-2012-900T_4P

1 2

R389

R389 0_0402_5%

0_0402_5%

1

USB20_P1_1

4

@

9/28 Swap L31 L32

R390

R390 0_0402_5%

0_0402_5%

@

1 2

L32

USB20_N0_1

2

USB20_N0<12>

USB20_P0<12>

2

3

WCM-2012-900T_4P

1 2

R391

R391 0_0402_5%

0_0402_5%

1

USB20_P0_1

4

@

10/28 Change R388,R389,R390,R391,R257,R258 from mount to un-mount

10/28 Change L28,L31,L32 (SM070000K00) from un-mount to mount

9/27 Change L28,L31,L32 to SM070000K00

+USB_VCCC1+5VALW

3 3

0.1U_0402_16V4Z

4 4

W=80mils W=80mils

USB_ON#<25>

+USB_VCCC1

A

C338

1

2

USB20_N2_1

U11

1

GND

2

VIN VIN3VOUT

4

EN

SA00003XM00

8

VOUT

7

VOUT

6 5

FLG

EPAD

AP2301MPG-13_MSOP8

9

USB_OC1# <12>

1

C339

1000P_0402_50V7K@

2

8/25 Change C340 from poly-cap to E-cap (SF000001500)

D17

@D17

@

6

CH3

5

Vp

4

CH4

CM1293-04SO_SOT23-6

CH2

CH1

3

2

Vn

USB20_P2_1

1

B

150U_B2_6.3VM_R35M

SGA00002N80

+USB_VCCC1

W=80mils

1

+

C340

2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

USB20_N2_1 USB20_P2_1

Issued Date

1

C341

470P_0402_50V7K

2

C

JUSB1

1 2 3 4

5 6 7 8

SUYIN_020133GB004M25MZL

CONN@

2010/08/12 2012/08/12

Right Side USB CONN.

VCC DD+ GND

GND1 GND2 GND3 GND4

Compal Secret Data

Deciphered Date

9/28 Swap L28

R257

R257 0_0402_5%

0_0402_5%

@

1 2

L28

USB20_N2_1

2

USB20_N2<12>

USB20_P2<12>

D

2

3

WCM-2012-900T_4P

1 2

R258 0_0402_5%

Title

Size Document Number Rev

B

Date: Sheet of

1

USB20_P2_1

4

@

Compal Electronics, Inc.

USB PORTS

P0VE6 Schematics

1.0

24 36Wednesday, November 17, 2010

E

1.0

5

4

3

2

1

11/15 Change L29,L30 P/N from SM010015410 to SM010004010

8/21 Change R262 from 0 ohm 0805 to 0 ohm 0603

L29

R262

+3VALW

0_0603_5%

1 2

D D

+3VALW

C C

C349

@C349

@

22P_0402_50V8J

12

R267 47K_040 2_5%R267 47K_0402_5%

C350 0.1U_0402_16V4ZC350 0.1U_0402_16V4Z

10/1 ENE Recomm and

R269 47K_0402_5%R269 47K_0402_5%

1 2

R270 47K_0402_5%R270 47K_0402_5%

1 2

R271 1K_0402_5%@R271 1K_0402_5%@

1 2

R266 2.2K_0402_5%R266 2.2K_0402_5%

1 2

R272 2.2K_0402_5%R272 2.2K_0402_5%

1 2

C353

C353 10P_0402_50V8J

10P_0402_50V8J

12

Reserve for EMI please close to U12

+3VS

R276 2.2K_0402_5%@R276 2.2K_0402_5%@

+3VALW

1 2

R277 2.2K_0402_5%@R277 2.2K_0402_5%@

1 2

R279 10K_0402_5%@R279 10K_0402_5%@

1 2

12

R275

22_0402_5%

1 2

R265

@R265

@

33_0402_5%

LPC_CLK0_EC

12

EC_RST#

KSO1

KSO2

EC_SMI#

EC_SMB_DA1

EC_SMB_CK1

11/02 Change C353 to 10p R275 to 22 ohm

8/23 Change R271 R279 from mount to @

EC_SMB_CK2

EC_SMB_DA2

EC_SCI#

9/5 Change R276 R277 from mount to @

GATEA20<12>

SERIRQ<11> LPC_FRAME#<11>

LPC_CLK0_EC<11>

PLT_RST#<11,17,19,20>

EC_SCI#<12>

KSI[0..7]<2 3>

KSO[0..15]<23>

8/31 EC_SCI# Pull up to +3VALW

8/25 Delete KSO16 KSO17

8/23 Delete R280

C407 100P_0402_50 V8JC407 100P_0402_50V8J

1 2

B B

15P_0402_50V8J

+3VALW

A A

Ra

Rb

EC_XCLK1

EC_XCLK0

1

C354

8/23 Change R282 from mount to @

X1 C354 C355 from @ to mount 8/26 Change R282 from @ to mount X1 C354 C355 from mount @

R283

R283 0_0402_5%

0_0402_5%

1 2

AD_BID0

12

R284

1

2

OSC4OSC

NC3NC

2

X1

32.768KHZ_12.5PF_Q13MC14610002

Board ID

Analog Board ID definition, Please see page 3.

8/21 Change R283 from 100k to 0 ohm

1

C357

0.1U_0402_16V4Z

2

8.2K_0402_5%

5

10/05 Add 100p(C407) on APU_ALERT#_EC

1

C355

15P_0402_50V8J

2

10/11 Change C354,C355, X1 from @ to mount

Battery

APU

8/24 Delete Net FAN_SPEED1

10/11 Change R282 R358 from mount to @

SLP_S5#<12>

PBTN_OUT#<12>

KB_RST#<12>

EC_SMB_CK1<29>

EC_SMB_DA1<29>

EC_SMB_CK2<4>

EC_SMB_DA2<4>

APU_ALERT#_EC<4>

INVT_PWM<8> FAN_SPEED1< 26>

EC_TX_P80_DATA<20> EC_RX_P80_CLK<20>

ON/OFF#<22>

PWR_SUSP_LED#<21>

SUSCLK<11>

R358

@

100K_0402_5%

8/31 Add 100k(R358) pull-down on SUSCLK

W=40mils W=20mils

C346

1000P_0402_50V7K

C346

1000P_0402_50V7K

C343

0.1U_0402_16V4Z

C343

0.1U_0402_16V4Z

C342

0.1U_0402_16V4Z

C342

0.1U_0402_16V4Z

1

2

GATEA20 KB_RST#_R SERIRQ LPC_FRAME#

KSI[0..7]

KSO[0..15]

1 2

LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

LPC_CLK0_EC PLT_RST# EC_RST# EC_SCI#

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

SLP_S3#_R SLP_S5#_R EC_SMI# APU_ALERT#_EC

INVT_PWM FAN_SPEED1 BT_ON# EC_TX_P80_DATA EC_RX_P80_CLK ON/OFF# PWR_SUSP_LED#

R282

@

LPC_AD3<11> LPC_AD2<11> LPC_AD1<11> LPC_AD0<11>

EC_SMI#<12>

BT_ON#<19,20>

12

0.1U_0402_16V4Z

1

2

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15

0_0402_5%

C344

1

2

EC_XCLK1

C345

0.1U_0402_16V4Z

C345

0.1U_0402_16V4Z

1000P_0402_50V7K

2

1

U12

1

GA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LFRAME#

5

LAD3

7

LAD2

8

LAD1

10

LPC & MISC

LAD0

12

PCICLK

13

PCIRST#/GPIO05

37

ECRST#

20

SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

SCL1/GPIO44

78

SDA1/GPIO45

79

SCL2/GPIO46

80

SDA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

LID_SW#/GPIO0A

17

SUSP#/GPIO0B

18

PBTN_OUT#/GPIO0C

19

EC_PME#/GPIO0D

25

EC_THERM#/GPIO11

28

FAN_SPEED1/FANFB1/GPIO14

29

FANFB2/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

ON_OFF/GPIO18

34

PWR_LED#/GPIO19

36

NUMLED#/GPIO1A

122

XCLK1

123

XCLK0

SA00003QQ10

SLP_S3#_R

R3400_0402_5% R3400_0402_5%

12

SLP_S5#_R

R3410_0402_5% R3410_0402_5%

12

PBTN_OUT#_R

R3420_0402_5% R3420_0402_5%

12

KB_RST#_R

R3430_0402_5% R3430_0402_5%

12

8/22 Add R340~R343 (0 ohm)

4

L29 FBMA-L11-160808-800LMT_0603

+3VALW_EC

C347

Int. K/B

Int. K/B Matrix

Matrix

SM Bus

FBMA-L11-160808-800LMT_0603

1 2

9

22

VCC

PS2 Interface

GND

11

+EC_VCCA

33

67

96

111

125

VCC

AVCC

INVT_PWM/PWM 1/GPIO0F

BEEP#/PWM2/GPIO10

ACOFF/FANPWM2/GPIO13

PWM Output

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

AD Input

SELIO2#/AD5/GPIO43

DAC_BRIG/DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

DA Output

TP_CLK/PSCLK3/GPIO4E

TP_DATA/PSDAT3/GPIO4F

SPI Device Interface

SPI Flash ROM

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

BATT_CHGI_LED#/GPIO52

CAPS_LED#/GPIO53

GPIO

BATT_LOW_LED#/GPIO54

SUSP_LED#/GPIO55

VR_ON/XCLK32K/GPIO57

EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04

ICH_PWROK/GPXO06

GPO

GPIO

PM_SLP_S4#/GPXID1

GPI

GND

AGND

GND

KB930QF A1 LQFP 128P

24

KB930QF A1 LQFP 128P

35

69

94

20mil

113

ECAGND

FBMA-L11-160808-800LMT_0603

1

C348

0.1U_0402_16V4Z

2

ECAGND

FANPWM1/GPIO12

ADP_I/AD2/GPIO3A

AD3/GPIO3B AD4/GPIO42

IREF/DA2/GPIO3E

DA3/GPIO3F

PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D

SDICS#/GPXOA00 SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICLK/GPIO58

SPICS#

CIR_RX/GPIO40

SYSON/GPIO56

AC_IN/GPIO59

EC_ON/GPXO05

EC_SWI#/GPXO06

BKOFF#/GPXO08

WL_OFF#/GPXO09

GPXO10 GPXO11

ENBKL/GPXID2

GPXID3 GPXID4 GPXID5 GPXID6 GPXID7

V18R

L30

8/31 Change EC_FAN_PWM from pin 34 to pin 26

8/31 Change PWR_SUSP_LED from pin 36 to pin 34

8/31 Change EC_PME# from pin 118 to pin 103

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/08/12 2012/08/12

8/23 Pull up 10k (R345) to +3VALW on USB_ON#

8/31 Change EC_MUTE# Pull-up to +3VS(@)

9/23 Update EC pin definition follow P5WE6

10/04 Add 100p(C399) on ACOFF

21

BEEP#

23

EC_FAN_PWM

26

ACOFF

27

BATT_TEMP

63 64

ADP_I

65

AD_BID0

66

AD_PID0

75 76

68

EN_FAN1

70

IREF

71

CHGVADJ

72

EC_MUTE#

83

USB_ON#

84 85

PWR_LED1#

86

TP_CLK

87

TP_DATA

88

97

EN_WOL#

98

VLDT_EN#

99

LID_SW#

109

EC_SI_SPI_SO

119

EC_SO_SPI_SI

120

EC_SPICLK

126

EC_SPICS#/FSEL#

128

73 74

FSTCHG

89

BATT_BLUE_LED#

90 91

BATT_AMB_LED#

92

PWR_LED#

93

SYSON

95

VR_ON

121

EC_ACIN

127

EC_RSMRST#

100

EC_LID_OUT#

101

EC_ON

102

EC_PME#

103

ICH_POK_EC

104

BKOFF#

105

WL_OFF#

106

WXMIT_OFF#

107 108

VGATE

110

APU_ENBKL

112

EAPD

114

EC_PROCHOT#

115

SUSP#

116

PBTN_OUT#_R

117

WWAN_W AKEUP#

118

V18REC_XCLK0

124

12

1

2

Compal Secret Data

ACOFF

BEEP# <16> EC_FAN_PWM <26>

C351 100P_0402_50 V8JC351 100P_0402_50V8J

C356

4.7U_0603_6.3V6K

ACOFF <30>

12

8/23 Delete DAC_BRIG 8/25 Delete CHG_ON#

EN_FAN1 <26> IREF <30>

CHGVADJ <30>

EC_MUTE# <16> USB_ON# <24>

PWR_LED1# <22>

EN_WOL# <17 > VLDT_EN# <27>

EC_SO_SPI_SI <26> EC_SPICLK <26> EC_SPICS#/FSEL# <26 >

FSTCHG <30> BATT_BLUE_LED# <21>

BATT_AMB_LED# <21> PWR_LED# <21> SYSON <27,32> VR_ON <35>

EC_RSMRST# <12> EC_LID_OUT# <12> EC_ON <22>

BKOFF# < 8> WL_OFF# <20> WXMIT_OFF# <19>

VGATE <12,35>

EC_PROCHOT# <4>

SUSP# <27,32,33>

WWAN_W AKEUP# <19>

10/27 Change C356 from 10V_0805 to 6.3V_0603

Deciphered Date

TP_CLK <23> TP_DATA <23>

LID_SW# <22>

EC_SI_SPI_SO <26>

EAPD <16>

VR_ONAPU_ALERT#_EC

2

C399

100P_0402_50V8J

EC_MUTE#

USB_ON#

TP_CLK

TP_DATA

R259 10K_0402_5%@R259 10K_0402_5%@

R345 10K_0402_5%R345 10K_0402_5%

R263 4.7K_0402_5%R263 4.7K_0402_5%

1 2

R264 4.7K_0402_5%R264 4.7K_0402_5%

1 2

8/26 Change D18 to SCS00002G00 Standard Part

9/23 Reserve R395 on ACIN

10/08 Change D18 to SCS00000Z00

12

ECAGND

BATT_TEMP <29>

ADP_I <30>

R268 200K_0402_5%R268 200K_0402_5%

EC_ACIN

C352 100P_0402_50V8JC352 100P_0402_50V8J

1 2

R395 0_0402_5%

12

D18

12

RB751V-40_SOD323-2

12

@

Follow PAWGC

@

D19 RB751V_S OD323

8/31 Add EN_FAN1 on U12.70

ICH_POK_EC

D19 RB751V_S OD323

1 2

R273 0_0402_5%R273 0_0402_5%

21

@

1 2

R274 10K_0402_5%

9/25 Change VLDT_EN to VLDT_EN#

LID_SW#

R278 100K_0402_5%R278 100K_0402_5%

9/17 Change Net Name from BATT_GRN_LED# to BATT_BLUE_LED#

8/23 Delete W_DISABLE#_2

10/04 Add 100p(C400) on VR_ON

C400

12

100P_0402_50V8J

APU_ENBKL <4>

R281

R281 100K_0402_5%

100K_0402_5%

1 2

+3VALW

R398

R398 0_0402_5%

0_0402_5%

Ra

1 2

AD_PID0

12

Rb

R399

Project ID

1

C393

0.1U_0402_16V4Z

2

8.2K_0402_5%

9/9 Change R323 from mount to @

PME Follow PAWGC

9/21 Change Q29 from SB000008J00 to SB000009610

@

LAN_WAKE#<17>

PCI_PME#<12>SLP_S3#<12>

Title

EC ENE-KB930

Size Document Number Rev

Custom

P0VE6 Schematics

Date: Sheet of

1 2

R323 0_0402_5%

1 2

R324 0_0402_5%@R324 0_0402_5%@

D

S

D

S

13

Q29

G

SSM3K7002FU_SC70-3

+3VALW

2

@

Compal Electronics, Inc.

1

12

ICH_POK <12>

12

+3VALW

+3VS

+3VALW

ACIN <30>

+3VS

R322

R322 10K_0402_5%

10K_0402_5%

1 2

25 36Wednesday, November 17, 2010

+5VS

+3VALW

EC_PME#

+3VALW

1.0

+3VALW

1 2

SPI_WP#

3.3K_0402_5%

SPI_HOLD#

3.3K_0402_5%

R203

0_0402_5%

1 2 1 2

33_0402_5%

R204

Layout Note: R204 close to U7

EC_SPICS#/FSEL#_R

R201

R202

EC_SPICS#/FSEL#<25>

EC_SI_SPI_SO<25>

EC_SPICS#/FSEL# EC_SI_SPI_SO EC_SPI_SO

2MB SPI ROM Share ROM.

U7

1

CS#

2

SPI_WP#

SO

3

WP#

4

GND

MX25L1605AM2C-12G_SO8

SA00003FO00

VCC

HOLD#

SCLK

W=20mil

+3VALW

C212

1 2

0.1U_0402_16V4Z

8

SPI_HOLD#

7

EC_SPICLK_R

6

EC_SPI_SI

5

SI

Layout Note: R203 R205 R206 close to U12

8/31 Remove EC ROM , Add SPI ROM

R2060_0402_5% R 2060_0402_ 5%

EC_SPICLK

1 2 1 2

33_0402_5%

EC_SO_SPI_SI

R205

EC_SPICLK <25> EC_SO_SPI_SI <25>

9/2 Change EC_SPICLK to EC_SPICLK_R

EC_SPICLK_R

12

R200

33_0402_5%

@

C211

22P_0402_50V8J

@

EMI

3P2 x 3 (APU)

2P6 x 5

2P8 x 3

3P2N x 1

3P3N x 1

H1

H1 H_3P2

H_3P2

1

@

H6

H6 H_2P6

H_2P6

1

@

H11

H11 H_2P8

H_2P8

1

@

H15

H15 H_3P2N

H_3P2N

1

H16

H16 H_3P3N

H_3P3N

1

H3

H2

H_3P2

1

@

H7

H8

H_2P6

1

@

H12

H13

H_2P8

1

@

H_3P2X3P5N x 1

H_3P4X3P2N x 2

40mil

+VCC_FAN1

40mil

+VCC_FAN1+VCC_FAN1

R3560_0402_5% R3560_0402_5%

+5VS

3

@

EC_FAN_PWM_R

R357

@

0_0402_5%

1 2

2

D20

D20 DAN217_SC59

DAN217_SC59

@

1

1 2

4.7U_0603_6.3V6K

@

C384

1 2

4.7U_0603_6.3V6K

C385

1000P_0402_50V7K

1 2

@

ACES_85205-04001

1 2 3 4 5 6

C383

1 2 3 4 G5 G6

CONN@

JFAN1

FAN Conn.

+5VS

+VCC_FAN1

1

9/15 Update the Screw Hole

EN_FAN1<25>

1 2

R355 330_0402_5%

@

9/20 Add H20 (H_3P4X3P2N)

H10

H9

H_2P6

1

@

+5VS

1 2

R289 0_0603_5%R289 0_0603_5%

10/07 Change H13 from GND to LANGND

1

10/07 Change H13 from LANGND to GND

H17

H17 H_3P2X3P5N

H_3P2X3P5N

1

H18

H18 H_3P4X3P2N

H_3P4X3P2N

1

H_3P2X3P7N x 1

H20

H20 H_3P4X3P2N

H_3P4X3P2N

1

H19

H19 H_3P2X3P7N

H_3P2X3P7N

1

EN_FAN1_R

1

C386

@ C386

@

0.01U_0402_16V7K

2

1

C360

@

10U_0805_10V6K

2

8/24 Update JFAN1 Symbol from database (ACES_85205-03001_3P) & Update pin definition 8/24 Delete R290

8/25 Update JFAN1 Symbol from database (ACES_85205-04001_4P) & Update pin definition 8/25 Add R290 10k pull-up tp +3VS

8/31 Reserve U17,C382~C386, R355~R357, D20 (Fan Drive Circuit)

@

C382 2.2U_0603_10V6K

1 2

U17

1

EN

2

VIN

3

VOUT

4

VSET

APL5607KI-TRG_SO8

@

EC_FAN_PWM<25>

FM1@FM1

8

GND

7

GND

6

GND

5

GND

FAN_SPEED1< 25>

FM2@FM2

@

1

@

+3VS

12

EC_FAN_PWM

FM3@FM3

@

1

R290

R290 10K_0402_5%

10K_0402_5%

1 2

FM4@FM4

1

@

FIDUCIAL_C40M80

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/12 2012/08/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

Compal Electronics, Inc.

Screw / EC ROM /FAN

P0VE6 Schematics

26 36Wednesday, November 17, 2010

1.0

A

B

C

D

E

+3VALW TO +3VS+5VALW TO +5VS

+5VALW

U14

DMN3030LSS-13_SOP8L-8

8

1

10U_0805_10V6K

1 1

2

+VSB

12

+5VS_GATE

13

D

2

G

S

7

C364

5

R294

R294 82K_0402_5%

82K_0402_5%

R297

1 2

20K_0402_5%

SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3 Q19

Q19

SB00000GV00 SB00000GV00

4

+5VS_GATE_R

+5VS

1 2

1

36

C365

C365 10U_0805_10V6K

10U_0805_10V6K

2

1

C370

0.1U_0603_25V7K

2

1

C366

C366 1U_0603_10V6K

1U_0603_10V6K

2

12

R292

R292 470_0603_5%

470_0603_5%

@

13

D

SUSP

2

G

Q16

@

Q16

@

S

SSM3K7002FU_SC70-3

C367

10U_0805_10V6K

SUSP

2

Q20 SSM3K7002FU_SC70-3

+3VALW

U15

DMN3030LSS-13_SOP8L-8

8

1

2

+VSB

G

7

5

12

R295

R295 120K_0402_5%

120K_0402_5%

+3VS_GATE +3VS_GATE_R

13

D

S

R350

1 2

0_0402_5%

4

+3VS

1 2

1

36

C368

C368 10U_0805_10V6K

10U_0805_10V6K

2

11/18 Change R295 from 200k to 120k

1

C371

0.1U_0603_25V7K

2

1

C369

C369 1U_0603_10V6K

1U_0603_10V6K

2

9/27 Change Q21.2 from SUSP# to SUSP

12

R293

R293 470_0603_5%

470_0603_5%

@

13

D

SUSP

2

G

Q17

S

SSM3K7002FU_SC70-3

@

+1.5V to +1.5VS

1

C361

@ C361

@

2

10U_0805_10V6K

+5VALW

12

+1.5VS_GATE +1.5VS_GATE_R

13

D

SUSP#SUSP

D

2

G

Q21 SSM3K7002FU_SC70-3

S

+1.5V

R296

R296 200K_0402_5%

200K_0402_5%

SB934130020

R298

12

100K_0402_5%

9/27 Change R296.1 from +5VALW to +VSB

9/27 Change Q15 to U19(SB00000GV00)

+1.1ALW to +1.1VS

2 2

10U_0805_10V6K

+VSB

+1.1VS_ON#

2

G

Q24

SSM3K7002FU_SC70-3

3 3

9/27 Change R304.1 from +5VALW to +VSB

12

R306

R306 470_0603_5%

470_0603_5%

@

13

D

2

G

Q25

S

SSM3K7002FU_SC70-3

+1.1VALW +1.1VS

U16

DMN3030LSS-13_SOP8L-8

8

C374

7

5

4

1

2

SB00000GV00

12

R304

R304 47K_0402_5%

47K_0402_5%

+1.1VS_GATE +1.1VS_GATE_R

13

D

S

@

R351

12

0_0402_5%

+1.5V+1.8VS +0.75VS

12

R307

R307 470_0603_5%

470_0603_5%

@

13

D

SYSON# SUSPSUSP

2

G

Q26

@

Q26

@

S

SSM3K7002FU_SC70-3

1 2

1

36

C375

C375 10U_0805_10V6K

10U_0805_10V6K

2

1

C378

0.1U_0603_25V7K

2

+1.05VS

12

R308

R308 470_0603_5%

470_0603_5%

@

13

D

2

G

Q27

S

SSM3K7002FU_SC70-3

1

C376

C376 1U_0603_10V6K

1U_0603_10V6K

2

SUSP

@

10/12 Change R402 from mount to @

10/12 Change R400 R403 from @ to mount

12

R300

R300 470_0603_5%

470_0603_5%

@

13

D

S

+1.1VS_ON#

2

G

Q22SSM3K7002FU_SC70-3 @

+1.1VS_ON# SUSP SUSP

C404 100P_0402_50V8JC404 100P_0402_50V8J

1 2

10/12 Change R294 to 100k

10/12 Change R295, R296 to 200k

10/12 Change R304 to 47k

10/12 Change R294 to 82k

10/12 Change R297 to 20k

12

R309

R309 470_0603_5%

470_0603_5%

@

13

D

2

G

Q28

@

Q28

@

S

SSM3K7002FU_SC70-3

@

1 2

R402 0_0402_5%

1 2

R403 0_0402_5%R403 0_0402_5%

VLDT_EN#

10/04 Add 100p(C404) on VLDT_EN#

10/06 Change C404 on +1.1VS_ON#

10/27 Add C408(100P) on SUSP# close to PR70

8/19 Change Q16~Q22 Q24~Q28 toSB000009610(SSM3K7002FU_SC70-3)

8/19 Change Q29 Q30 to Q23A Q23B (SB00000DH00 S TR DMN66D0LDW-7 2N SOT363-6)

8/21 Change U14~U16 to SB548000310 (SI4800BDY-T1-E3_SO8)

8/23 Remove R305 R299 Add R350 R351 for Sequence

8/24 Change Q23A Q23B to Q30 Q31(@) (SB000009610 SSM3K7002FU_SC70-3)

8/25 Change C363,C366,C369,C376 to SE080105K80 Standard Part

8/25 Change C361,C362,C364,C365,C367,C368,C374,C375 to SE000004880 Standard Part

8/26 Change U14, U15, U16 to SB00000GV00 Standard Part

9/3 Delete C377(DIS@)

9/23 Reserve R400~403, Q36 for VLDT_EN

+5VALW

12

9/28 Change Q21.2 from SUSP to SUSP#

9/28 Change R296.1 from +VSB to +5VALW

9/28 Change U19 to Q15(SB934130020)

9/28 Remove C372

R400

R400 100K_0402_5%

100K_0402_5%

VLDT_EN# <25>

SUSP#<25,32,33> SYSON<25,32>

C408 100P_0402_50V8JC408 100P_0402_50V8J

SUSP<34>

1 2

12

R404

R404 10K_0402_5%

10K_0402_5%

+5VALW

12

R302

R302 100K_0402_5%

100K_0402_5%

10/04 Add 100p(C403) on SUSP

10/06 Remove C403

13

D

2

G

Q30

S

SSM3K7002FU_SC70-3

9/27 Change R302 from @ to mount, remove R301

10/27 Change R291 Q18 from @ to mount

Q15

Q15 AO3413L_SOT23-3

AO3413L_SOT23-3

3

+1.5VS

1

DGS

1

C362

@ C362

@

2

10U_0805_10V6K

2

1

10/29 Change R298 from 0 ohm to 100k

C373

0.1U_0402_16V4Z

2

1

C363

C363 1U_0603_10V6K

1U_0603_10V6K

2

Q18

SSM3K7002FU_SC70-3

Q18

12

13

D

S

10/31 Change C373 from 0603_25V to 0402_16V

8/26 Change Q15 to SB934130020 Standard Part

9/25 Change Q15 to SB000007H10

SYSON#

SYSON

SSM3K7002FU_SC70-3

@

R303

100K_0402_5%

@

@ 2

G

Q31

+5VALW

10/31 Change C361 C362 from mount to @

R291

R291 470_0603_5%

470_0603_5%

SUSP

2

G

12

13

D

S

9/25 Remove R401 Q36 on VLDT_EN

4 4

9/25 Add 10k(R404) PD on SUSP#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2010/08/12 2012/08/12

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

DC Interface

P0VE6 Schematics

27 36Thursday, November 18, 2010

E

1.0

A

B

C

D

VIN

PD1

RLS4148_LL34-2

68_1206_5%

13

PR1

1 2

12

PR2

PR2 68_1206_5%

68_1206_5%

12

PC5

0.1U_0603_25V7K

VS

1 1

PR142

VIN

12

PC4

100P_0402_50V8J

+RTCBATT2

BATT+

51_ON#<22>

PD2

RLS4148_LL34-2

100K_0402_1%

1 2

22K_0402_1%

PR4

PQ1

TP0610K-T1-E3_SOT23- 3

12

PR3

N1

12

PC6

0.22U_0603_25V7K

2

PL1

HCB2012KF-121T50_0805

PR5

+-

12

HCB2012KF-121T50_0805

1 2

12

PC2

100P_0402_50V8J

+RTCBATT2P

+3VLP

PR141

1 2

560_0603_5%

12

PC3

1000P_0402_50V7K

1 2

560_0603_5%

DC_IN_S1

SP02000GC00

PJP1

4

6

4

GND

3

5

3

GND

2

1

ACES 88266-04001

CONN@

2 2

+CHGRTC

12

PC1

1000P_0402_50V7K

PBJ1

ML1220T13RE

45@

0_0603_5%

1 2

PJ2

@ PJ 2

@

PJ1

+3VALWP

3 3

+5VALWP

+VSBP +VSB

4 4

+1.5VP

2

JUMP_43X118

PJ3

@ PJ3

@

2

JUMP_43X118

PJ5

@

2

JUMP_43X39

PJ7

@ PJ 7

@

2

JUMP_43X118

@

PJ9

2

JUMP_43X118

12

PC241

PC241 .1U_0402_16V7K

.1U_0402_16V7K

12

PC243

PC243 .1U_0402_16V7K

.1U_0402_16V7K

12

PC245

PC245 .1U_0402_16V7K

.1U_0402_16V7K

12

PC247

PC247 .1U_0402_16V7K

.1U_0402_16V7K

12

PC249

PC249 .1U_0402_16V7K

.1U_0402_16V7K

+3VALW

+5VALW

+0.75VSP

+1.8VS+1.8VSP

+1.5V

112

A

@

2

JUMP_43X118

PJ4

@ PJ 4

@

2

JUMP_43X118

PJ6

@ PJ6

@

2

JUMP_43X79

112

+1.1VALW+1.1VALW P

12

PC242

PC242 .1U_0402_16V7K

.1U_0402_16V7K

+1.05VS+1.05VSP

12

PC244

PC244 .1U_0402_16V7K

.1U_0402_16V7K

12

PC246

PC246 .1U_0402_16V7K

.1U_0402_16V7K

B

+0.75VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

C

2012/08/122010/08/12

Compal Electronics, Inc.

Title

Size D ocument Number Rev

Date: Sheet of

Compal Electronics, Inc.

DCIN/VIN DECTOR

28 36Wednesday, November 17, 2010

D

28 36Wednesday, November 17, 2010

1.0

A

B

C

D

1 1

PJP2

1

2

3

4

5

6

7

8

9

GND

10

GND

@

SUYIN_200275MR008G15QZR

2 2

3 3

100K_0402_1%

POK<31,33>

VMB

B/I TS

EC_SMDA

PR12

100_0402_1%

PR18

1 2

EC_SMCA

PR13

100_0402_1%

1 2

VL

1 2

PR19

1 2

0_0402_5%

PC12

.1U_0402_16V7K

PC12

12

PR6

PR6 1K_0402_1%

1K_0402_1%

PR9

6.49K_0402_1%

12

PR14

1K_0402_1%

B+

12

PC10

PR16

@

100K_0402_1%

0.22U_0603_25V7K

PR17

1 2

22K_0402_1%

13

D

PQ3

2

SSM3K7002FU_SC70-3

G

S

12

0.22U_0603_25V7K

VMB

12

PC7

PC7 1000P_0402_50V7K

1000P_0402_50V7K

+3VALW

BATT_TEMP <25>

EC_SMB_CK1 <25>

EC_SMB_DA1 <25>

PQ2

TP0610K-T1-E3_SOT23- 3

2

HCB2012KF-121T50_0805

1 2

13

12

PL2

PC11

@PC11

@

0.1U_0603_25V7K

+VSBP

12

PC8

0.01U_0402_25V7K

BATT+

PC9

0.1U_0402_10V7K

PH1 under CPU botten side :

CPU thermal protection at 92 degree C Recovery at 72 degree C

VL

12

VL

PU1

PR10

@PR1 0

@

100K_0402_1%

MAINPWO N<31>

1 2

PU1

1

VCC

TMSNS1

2

GND

RHYST1

3

OT1

TMSNS2

4

RHYST2

OT2

G718TM1U_SOT23-8

100K_0402_1%_NCP15W F104F03RC

8

7

6

5

PR7

10K_0402_1%

@

PR15

47K_0402_1%

PH2

PR7

12

PR8

22.1K_0402_1%

1 2

12

PR11

15K_0402_1%

12

@PH2

@

12

PH1

100K_0402_1%_NCP15W F104F03RC

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

2012/08/122010/08/12

Title

Size D ocument Number Rev

Date: Sheet of

Compal Electronics, Inc.

BATTERY CONN / OTP

29 36Wednesday, November 17, 2010

D

29 36Wednesday, November 17, 2010

1.0

5

4

3

2

1

Iada=0~2.105A(40W/19V=2.105A)

ADP_I = 19.9*Iadapter*Rsense

CP = 85%*Iada ; CP = 1.789A

P2

PQ4

PD3

VIN

D D

12

PR22

PR22 200K_0402_1%

200K_0402_1%

2

13

BATT_ON ACPRN

C C

2

61

D

2

G

PQ9A

S

DMN66D0LDW -7_SOT363-6

ACOFF<25>

PQ8

PQ8 DTC115EUA_SC70-3

DTC115EUA_SC70-3

PACIN

DTC115EUA_SC70-3

ACOFF

12

B340A_SMA2

PQ6

1 3

DTA144EUA_SC70-3

DMN66D0LDW -7_SOT363-6

PR40

47K_0402_1%

1 2

PQ12

2

12

PC17

0.1U_0603_25V7K

PQ9B

5

G

13

PQ4 SI7121DN-T1-GE3_POW ERPAK8-5

SI7121DN-T1-GE3_POW ERPAK8-5

1 2 3 5

4

12

PR23

PR23 200K_0402_1%

200K_0402_1%

12

PR30

PR30 150K_0402_1%

150K_0402_1%

34

D

ADP_I<25>

S

62K_0402_1%

IREF<25>

100K_0402_1%

FSTCHG<25>

PR39

1 2

0.01U_0402_25V7K

12

PR44

P3

PC13

PC13 5600P_0402_25V7K

5600P_0402_25V7K

10K_0402_1%

PC24

12

PC31

0.01U_0402_25V7K

1

2

ACSETIN

PR29

12

100K_0402_1%

PR35

1 2

10K_0402_1%

PC26

1 2

.1U_0402_16V7K

1 2

4.7K_0402_1%

PR20

0.05_1206_1%

12

PR31

PC23

1 2

6800P_0402_25V7K

PR43

12

PC238

PC237

PC250

PC251

B+

@

10U_0805_25V6K

4

3

6251VDD

12

PC18

2.2U_0603_6.3V6K

6251_EN CSO N

PR37

1 2

47K_0402_1%

6251VREF

6251ACLIM6251VR EF

12

PR46

20K_0402_1%

10U_0805_25V6K

RB751V-40_SOD323-2

PU2

1

VDD

2

ACSET

3

EN

4

CELLS

5

ICOMP

6

VCOMP

7

ICM

8

VREF

9

CHLIM

10

ACLIM

11

VADJ

12

GND

G5209S31U_SSOP24

@

10U_0805_25V6K

PD4

10_1206_5%

DCIN

ACPRN

CSON

CSOP

CSIN

CSIP

PHASE

UGATE

BOOT

VDDP

LGATE

PGND

PC251

@

10U_0805_25V6K

VIN

1 2 12

PR26

DCIN

24

0.1U_0603_25V7K

23

22

21

PR34 20_0402_5%PR34 20_0402_5%

20

PC25

0.1U_0603_25V7K

19

1 2

LX_CHG

18

DH_CHG

17

BST_CHG

16

6251VDDP

15

DL_CHG

14

13

PL3

HCB2012KF-121T50_0805

12

PR24

PR24 191K_0402_1%

191K_0402_1%

12

PR28

PC19

14.3K_0402_1%

1000P_0402_25V8J

PC20

12

PR32 2 0_0402_5%PR32 20_0402_5%

PC22

0.047U_0402_16V7K

1 2

PR33

1 2

PR36 2_0402_5%PR36 2_0402_5%

PR42

1 2

0_0603_5%

PC32

4.7U_0603_6.3V6M

1 2

12

CSIN

CSIP

ACSETIN

1 2

20_0402_5%

12

BST_CHGA

12

PD5

PD5 RB751V-40_SOD323-2

RB751V-40_SOD323-2

1 2

PR45 4.7_0603_5%PR45 4.7_0603_5%

PC14

CSOP

PC27

12

0.1U_0603_25V7K

6251VDD

CHG_B+

12

4.7U_0805_25V6-K

12

PC16

PC15

4.7U_0805_25V6-K

PC234

@

10U_0805_25V6K

4.7U_0805_25V6-K

1 2 13

PQ7

DTC115EUA_SC70-3

PQ10

PQ10 AON7408L_DFN8-5

AON7408L_DFN8-5

5

4

PL4

1 2

12

PR41

@ PR41

@

4.7_1206_5%

12

@

PC28

680P_0603_50V7K

PL4

8.2UH_VMPI0703AR-8R2M -Z01_4A_20%

123

5

4

PQ11

AON7408L_DFN8-5

123

PQ5

PQ5 SI7121DN-T1-GE3_POW ERPAK8-5

SI7121DN-T1-GE3_POW ERPAK8-5

1 2 3 5

PR25

10K_0402_1%

2

12

CHGCH G

4

1 2

47K_0402_1%

PR27

PR27 100K_0402_1%

100K_0402_1%

BATT_ON

1 2

@

PC21

PC21 2200P_0402_50V7K

2200P_0402_50V7K

PR38

1

2

0.05_1206_1%

4

3

PR21

VIN

BATT+

12

PC29

10U_0805_25V6K

12

PC30

10U_0805_25V6K

PC204

PC205

@

10U_0805_25V6K

B B

CHGVADJ<25>

BATT Type

Charging Voltage (0x15)

CV mode

CC=0.25~3.52A

IREF=0.7224*Icharge

Normal 3S LI-ON Cells

Ki Vchlim=Iref*(PR 39/(PR39+PR44)) =Iref*(100K/(80 .6K+100K)) =Iref*0.617 Ichanrge=(165mV/PR38)*(Vchlim/3.3V) =(165m/50m)*(1/ 3.3V)*Iref*0.61 7 =0.617*Iref Iref=1.62*Ichan rge =>Ki=1.62

Kv Rinternal ic=514K Rec=3K R1=PR379=15.4K R2=PR381=31.6K

A A

R=514K//31.6K// (15.4K+3k)=11.3 72K r=514K//514K//3 1.6K=28.14K Vcell=0.175*Vad j+3.99v

4.2V=0.175*Vadj +3.99V =>Vadj=1 .2V Vadj=Vref*(R/(R +514K))+CALIBRA TE*(r/(r=514K))

1.1483=CALIBRAT E*0.6046 =>CALI BRATE=1.899

1.899=(4.2-(Vce ll+A*0.175))*Kv =(4.2-(4.2+A*0. 175))*Kv A=Vref*(R/(R+51 4K))=0.052 Kv=9.451

5

12600mV

12.60V

IREF=0.43V~3.24V

4

PR47

1 2

15.4K_0402_1%

ACPRN

PR48

31.6K_0402_1%

1 2

PR49

47K_0402_1%

6251VDD

Vth,rise(typical) = ((191K/14.3K)+1)*1.26

Vth,fall(typical) = ((191K/14.3K)+1)*1.26 -3.4uA*191K

PR51

12

PR50

PR50 10K_0402_1%

10K_0402_1%

13

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PR51

10K_0402_1%

1 2

PQ13

PQ13 DTC115EUA_SC70-3

DTC115EUA_SC70-3

12

PR52

14.3K_0402_1%

3

ACIN <25>

PACIN

Compal Secret Data

2010/08/12 2012/08/12

Compal Secret Data

Deciphered Date

2

= 18.089V

= 17.44V

Title

Size D ocument Number Rev

Date: Sheet of

Compal Electronics, Inc.

CHARGER

30 36Wednesday, November 17, 2010

1

1.0

5

4

3

2

1

2VREF

D D

1U_0402 _6.3V6K

PC33

12

+5VALW Vo= (2*30K/19.1K)+2=5.141V+3VALW Vo= (2*13.7K/20K)+2=3.37V

PR54

PR53

13.7K_04 02_1%

1 2

PR55

BST_3V

UG_3V

LX_3V

LG_3V

PR55

20K_040 2_1%

1 2

PR57

130K_04 02_1%

1 2

PU3

25

P PAD

7

VO2

8

VREG3

9

BOOT2

10

UGATE2

11

PHASE2

12

LGATE2

12

PR64

100K_0402_5%

2VREF

ENTRIP2

6

ENTRIP2

EN

13

B++

3

4

5

FB2

REF

TONSEL

SKIPSEL

VIN16GND

14

15

12

B++

PL5

HCB2012 KF-121T50_080 5

1 2

B+

PQ14

PR61

4.7_1206 _5%

PC45

PR65

100K_04 02_1%

PR67

@

PQ18A

12

PQ14

42.2K_0402_1%

12

5

4

123

5

123

61

D

S

12

PC50

@

0.1U_0402_10V7K

0.1U_060 3_25V7K

4

PQ16

PQ16 FDMC769 2S_MLP8-5

FDMC769 2S_MLP8-5

ENTRIP1 ENTRIP2

2

G

13

2

B+

5

G

PQ19

PQ19 DTC115E UA_SC70-3

DTC115E UA_SC70-3

12

PC35

PC34

C C

PC34

0.1U_0603_25V7K

PC239

4.7U_0805_25V6-K

+3VALWP

PC43

220U_6.3 V_M

B B

12

PC36

4.7U_0805_25V6-K

4.7U_0805_25V6-K 2200P_0402_50V7K

2200P_0402_50V7K

4.7UH_FD VE0630-H-4R7M= P3_5.5A_20%

1

+

2

AON7408 L_DFN8-5

PL6

1 2

680P_06 03_50V7K

DMN66D0 LDW-7_SOT3 63-6

VL

MAINPW ON<29 >

PR66

VS

A A

1 2

100K_04 02_1%

12

PC38

4.7U_0603_6.3V6K

PC41

1 2

499K_04 02_1%

1 2

1U_0402 _6.3V6K

34

D

PQ18B

DMN66D0 LDW-7_SOT3 63-6

S

+3VLP

PR59

1 2

0_0603_ 5%

PR63

12

PC47

+3.3VALWP Imax=4.214A ; Ipeak=6.02A ; Iocp=1.2*Ipeak=7.224A f=375KHz, L=4.7UH,Rentrip2=130K ohm Rdson=14.5~17.9m ohm (IRFH3707) 1/2Delta I = 1/2 *(19-3.3)*(3.3/19)/(375KHz*4.7UH)=0.773A Vtrip2=(10*10^-6*150Kohm/9)-24mV=0.143V Ilimit=0.143/(17.9m*1.2)~0.143/(14.5m)=6.642A~9.839A Iocp=7.415A~10.613A (7.415A>7.224A -> OK)

PR54

30K_040 2_1%

1 2

PR56

19.1K_04 02_1%

1 2

ENTRIP1

PR58

143K_04 02_1%

1 2

2

1

FB1

ENTRIP1

VO1

PGOOD

BOOT1

UGATE1

PHASE1

LGATE1

NC18VREG5

RT8205E GQW_W QFN24_4X4

17

12

PC48

4.7U_060 3_6.3V6K

PC49

0.1U_060 3_25V7K

B++

12

PC39

PC40

PC240

4.7U_0805_25V6-K

2200P_0402_50V7K

24

23

22

21

20

19

BST_5V

UG_5V

LX_5V

LG_5V

PR60

1 2

0_0603_ 5%

POK <2 9,33>

1 2

PC42

0.1U_060 3_25V7K

FDMC769 2S_MLP8-5

12

PC37

0.1U_0603_25V7K

4.7U_0805_25V6-K

PQ17

4

PQ15

5

AON7408 L_DFN8-5

123

4.7UH_FD VE0630-H-4R7M= P3_5.5A_20%

5

123

1 2

12

@

PR62

4.7_1206 _5%

12

@

PC46

PC46 680P_06 03_50V7K

680P_06 03_50V7K

PL7

+5VALWP

1

+

PC44

2

220U_6.3V_M

VL

TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP) (2)SMPS2=375KHZ (+3VALWP)

+5VALWP Imax=4.9A ; Ipeak=7A ; Iocp=1.2*Ipeak=8.4A f=300KHz, L=4.7UH,Rentrip1=143K ohm Rdson=14.5~17.9m ohm (IRFH3707) 1/2Delta I = 1/2 *(19-5)*(5/19)/(300KHz*4.7UH)=1.306A Vtrip1=(10*10^-6*162Kohm/9)-24mV=0.156V Ilimit=0.156/(17.9m*1.2)~0.156/(15m)=7.263~10.759A Iocp=8.569~12.065A (8.569>8.4 -> OK)

Security Class ification

2010/08/ 12 2012/08/ 12

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/ 12 2012/08/ 12

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

3VALWP/5VALWP

Wednesday, November 17, 2010

1

31 36

1.0

A

PJ10

@ PJ10

@

2

112

JUMP_43X39

SUSP#<25,27,33>

12

@

PC63

.1U_0402_16V7K

12

PC51

PC51 22U_0805_6.3VAM

22U_0805_6.3VAM

PR70

1 2

200K_0402_1%

499K_0402_1%

EN_1.8VS

PR72

PU5

2

TON

3

OUT

4

VCC

5

FB

6

PGOOD

@

PR75

1 2

0_0402_5%

PR78

1 2

100_0603_5%

4.7U_0603_6.3V6K

+5VALW

30K_0402_5%

PC58

PR76

1 1

2 2

SYSON<25,27>

+5VALW

3 3

B

SY8033BDBC_DFN10_3X3

12

1

14TP15

EN_SKIP

VFB=0.75V

AGND7PGND

G5603RU1U_TQFN14_3P5X3 P5

8

12

PC56

0.22U_0402_10V6K

PR74

255K_0402_1%

1 2

BST_1.5V

BST

13

DH

12

LX

11

ILIM

10

VDD

9

DL

PU4

10

9

8

5

1 2

0_0603_5%

DH_1.5V

LX_1.5V

4

PVIN

SVIN

EN

TP

11

PR77

PR73

1 2

15K_0402_1%

C

PL8

1UH_FDV0630-1R0M-P 3_10.3A_20%

LX_1.8VS

2

LX

PG

3

LX

FB=0.6Volt

6

FB

NC

7

1

PC64

BST_1.5V-1

PC64

1 2

0.1U_0603_25V7K

+5VALW

DL_1.5V

PC67

4.7U_0603_6.3V6K

1 2

1UH_FDV0630-1R0M-P 3_10.3A_20%

12

PR68

4.7_1206_5%

12

PC55

680P_0603_50V7K

AON7408L_DFN8-5

FDMC7692S_MLP8-5

12

PR69

20.5K_0402_1%

FB_1.8VS

PQ20

4

PQ21

12

PR71

10K_0402_1%

5

123

5

123

+1.8VSP

12

PC52

68P_0402_50V8J

12

PC59

4.7U_0805_25V6-K

12

PC53

22U_0805_6.3VAM

12

PC61

PC60

0.1U_0603_25V7K

4.7U_0805_25V6-K

2.2UH_FDVE0630-H- 2R2M=P3_8.3A_20%

PR79

@PR7 9

@

4.7_1206_5%

PC66

@PC6 6

@

680P_0603_50V7K

<Vo=1.8V> VFB=0.6V Vo=VFB*(1+PR69/PR71)=0.6*(1+20.5K/10K)=1.83V

Ipeak=2A, Imax=1.4A

PC54

22U_0805_6.3VAM

PL9

HCB2012KF-121T50_0805

1 2

12

PC62

2200P_0402_50V7K

PL10

12

1

+

PC65

PC65 330U_2.5V_M

330U_2.5V_M

2

D

B+

+1.5VP

PR80

1 2

5.36K_0402_1%

12

PR81

5.1K_0402_1%

4 4

Temperature Compensated

Vtrip_min (SPEC)

Vtrip_max (SPEC)

G5603 TPS51117 RT8209MRT8209B

-1180ppm/

℃℃℃℃

1600ppm/

℃℃℃℃

4500ppm/

℃℃℃℃

4800ppm/

30mV 50mV 30mV 50mV

200mV 200mV 200mV 200mV

A

℃℃℃℃

<Vo=1.5V> VFB=0.75V V=0.75*(1+5.36K/5.1K)=1.538V

Cout ESR=25m ohm Rdson(max)=17.9 mohm Rdson(typ)=14.5 mohm. (IRFH3707) Ipeak=6.5A, Imax=4.55A, Iocp > 7.8A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/12 2012/08/12

Compal Secret Data

Deciphered Date

C

RT8209BG5603 RT8209MTPS51117

6.821A 7.235A 8.000A 8.178AOCP setting

Title

Size D ocument Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

1.8VSP/1.5VP

1.0

32 36Wednesday, November 17, 2010

D

32 36Wednesday, November 17, 2010

1.0

A

PR82

PU6

TON

OUT

VCC

FB

PGOOD

PR82

255K_0402_1%

1 2

1

EN_SKIP

VFB=0.75V

AGND7PGND

8

PR85

0_0603_5%

1 2

14TP15

BST

DH

LX

ILIM

VDD

DL

G5603RU1U_TQFN14_3P5X3 P5

1 1

PR83

0_0402_5%

POK<29,31>

+5VALW

2 2

1 2

30K_0402_5%

PR87

100_0603_1%

1 2

PC75

4.7U_0603_6.3V6K

PR84

12

PC72

PC72 .1U_0402_16V7K

@

12

.1U_0402_16V7K

@

PR89

4.99K_0402_1%

1 2

12

PR90

PR90 10K_0402_1%

10K_0402_1%

2

3

4

5

6

13

12

11

10

9

B

BST_1.1V ALW

DH_1.1VALW

LX_1.1VALW

1 2

PR88

13K_0402_1%

DL_1.1VALW

PC73

1 2

0.1U_0603_25V7K

+5VALW

12

PC76

4.7U_0603_6.3V6K

C

PL11

HCB2012KF-121T50_0805

1.1VALW _B+

12

PQ22

123

AON7408L_DFN8-5

PQ23

FDMC7692S_MLP8-5

123

12

5

4

5

4

PC69

PC68

4.7U_0805_25V6-K

PL12

2.2UH_FDVE0630-H- 2R2M=P3_8.3A_20%

1 2

12

PR86

4.7_1206_5%

@ PR86

@

12

PC77

@ PC77

@

680P_0603_50V7K

12

PC70

PC71

0.1U_0603_25V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K 2200P_0402_50V7K

2200P_0402_50V7K

1

+

PC74

2

330U_2.5V_M

+1.1VALW P

1.05VALW _B+

12

B+

<Vo=1.1V> VFB=0.75V V=0.75*(1+4.99K/10K)=1.124V

Cout ESR=25m ohm Rdson(max)=17.9 mohm Rdson(typ)=14.5 mohm. (IRFH3707) Ipeak=4.02A, Imax=2.814A, Iocp > 4.824A

G5603 RT8209B TPS51117 RT8209M

OCP setting 5.799A 6.183A 6.845A 6.976A

PL13

HCB2012KF-121T50_0805

12

B+

D

12

5

PR91

255K_0402_1%

PR92

200K_0402_1%

SUSP#<25,27,32>

3 3

+5VALW

4 4

1 2

30K_0402_5%

PR95

100_0603_1%

1 2

PC85

4.7U_0603_6.3V6K

PR94

12

PC82

PC82 .1U_0402_16V7K

@

.1U_0402_16V7K

12

PR98

3.57K_0402_1%

1 2

12

PR99

8.25K_0402_1%

1 2

1

PU7

2

TON

EN_SKIP

3

OUT

VFB=0.75V

4

VCC

5

FB

6

PGOOD

AGND7PGND

PR93

0_0603_5%

1 2

14TP15

BST

ILIM

VDD

G5603RU1U_TQFN14_3P5X3 P5

8

BST_1.05V ALW

DH_1.05VALW

13

DH

LX_1.05VALW

12

LX

11

1 2

PR96

15K_0402_1%

10

DL_1.05VALW

9

DL

PC83

1 2

0.1U_0603_25V7K

+5VALW

12

PC86

4.7U_0603_6.3V6K

4

5

4

12

PQ24

123

AON7408L_DFN8-5

PQ25

FDMC7692S_MLP8-5

123

PC78

4.7U_0805_25V6-K

2.2UH_FDVE0630-H- 2R2M=P3_8.3A_20%

1 2

12

PR97

4.7_1206_5%

@ PR97

@

12

PC87

@ PC87

@

680P_0603_50V7K

12

PC79

4.7U_0805_25V6-K

PL14

PC81

PC80

0.1U_0603_25V7K

0.1U_0603_25V7K 2200P_0402_50V7K

2200P_0402_50V7K

+1.05VSP

1

<Vo=1.05V> VFB=0.75V

+

PC84

V=0.75*(1+3.57K/8.25K)=1.074V

2

Cout ESR=25m ohm

220U_D2_2VY_R15M

Rdson(max)=17.9m ohm Rdson(typ)=14.5 mohm.(IRFH3707) Ipeak=5.5A, Imax=3.85A, Iocp > 6.6A

G5603 RT8209B TPS51117 RT8209M

OCP setting

6.524A 7.003A 7.768A 7.881A

G5603 TPS51117 RT8209MRT8209B

Temperature Compensated

Vtrip_min (SPEC)

Vtrip_max (SPEC)

-1180ppm/

℃℃℃℃

1600ppm/

℃℃℃℃

4500ppm/

℃℃℃℃

4800ppm/

30mV 50mV 30mV 50mV

200mV 200mV 200mV 200mV

A

℃℃℃℃

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/12 2012/08/12

Compal Secret Data

Deciphered Date

C

Title

Size D ocument Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

1.1VALWP/1.0VSP

33 36Wednesday, November 17, 2010

D

33 36Wednesday, November 17, 2010

1.0

5

D D

4

3

2

1

+1.5V

1

PJ11

1

JUMP_43X118

@

2

C C

4.7U_0603_6.3V6K

PR101

300K_0402_5%

SUSP<27 >

1 2

PC92

.1U_0402_16V7K

2

G

12

2

PC88

1 2

13

D

S

PQ26

PQ26 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

PR100

1K_0402_1%

PR102

1K_0402_1%

12

PC90

For shortage changed

PU8

1

VIN

2

GND

3

VREF

4

VOUT

APL5336KAI-TRL_SOP8P8

12

.1U_0402_16V7K

+0.75VSP

12

PC91

PC91 10U_0603_6.3V6M

10U_0603_6.3V6M

VCNTL

8

NC

7

NC

6

5

NC

9

TP

+3VALW

12

PC89

PC89 1U_0402_6.3V6K

1U_0402_6.3V6K

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/08/12 2012/08/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

0.75VSP

34 36Wednesday, November 17, 2010

1

1.0

A

1 1

+5VS +3VS

PR126

12

@

PR116

PR116 10K_0402_1%

10K_0402_1%

12

10_0402_1%

PC117

1000P_0402_50V7K

PR137

6.81K_0402_1%

+3VS

12

PR115

105K_0402_1%

2 2

FCH_PWRGD<12>

H_PWRGD_L<11>

APU_SVD<4>

APU_SVC <4>

@

12

PC123

100P_0402_50V8J

3 3

DIFF_0

PR134

PC115

255_0402_1%

4 4

PC115

4700P_0402_25V7K

12

PR135

1K_0402_5%

12

VR_ON<25>

12

VGATE<12,25>

PC124

@PC124

@

100P_0402_50V8J

PR125

90.9K_0402_1%

PR136

54.9K_0402_1%

12

PR138

@ PR138

@

36.5K_0402_1%

A

1 2

PR119 100K_0402_5%@ PR119 100K_0402_5%@

1 2

PR120 100K_0402_5%PR120 100K_0402_5%

12

26.1K_0402_1%

12

+APU_CORE

APU_VDD0_RUN_FB_H<4>

APU_VDD0_RUN_FB_L<4>

VW0

12

PC116

100P_0402_50V8J

PC118

12

1200P_0402_50V7K

COMP0

PR113

PR113 0_0402_5%

0_0402_5%

PR121

0_0402_5%

PR128

10_0402_1%

12

+5VALW

CPU_B+

12

PR114

@PR114

@

105K_0402_1%

12

PR117

@PR117

@

105K_0402_1%

ISL6265_PWROK

12

PR124

0_0402_5%

12

PR130

0_0402_5%

PR131

12

0.1U_0603_25V7K

12

B

PR104

2_0603_5%

1 2

PC101

0.1U_0603_16V7K

1 2

PR109

2_0603_5%

PC105

PU9

1

OFS/VFIXEN

2

PGOOD

3

PWROK

4

SVD

5

SVC

6

ENABLE

7

RBIAS

8

OCSET

9

VDIFF0

10

FB0

11

COMP0

12

VW0

ISP0

VSEN1

ISN0

PR129

PR129 0_0402_5%

0_0402_5%

1 2

12

PC119

@PC119

@

100P_0402_50V8J

12

PC120

@PC120

@

100P_0402_50V8J

0_0402_5%

PR132

+3VS

B

12

47

48

VIN

VCC

ISN0

ISP0

14

13

VSEN0

RTN0

12

7.87K_0402_1%

7.87K_0402_1% PR133

PR133

46

FB_NB

VSEN0

15

PC93

33P_0402_50V8J

12

PR103

44.2K_0402_1%

44

45

FSET_NB

COMP_NB

ISL6265CHRTZ-T_TQFN48_6X6

RTN1

RTN0

17

16

12

PC94

1000P_0402_50V7K

PC100

1000P_0402_50V7K

12

PR106

22K_0402_1%

12

PR110

0_0402_5%

PC121

@PC121

@

100P_0402_50V8J

PC122

@PC122

@

100P_0402_50V8J

PR111

PR111 0_0402_5%

0_0402_5%

40

41

42

43

RTN_NB

VSEN_NB

OCSET_NB

VDIFF1

FB1

VSEN1

19

20

18

VSEN1

6.49K_0402_1%

6.49K_0402_1% PR140

PR140

12

PGND_NB

COMP121ISP1

C

CPU_B+

PQ27

AON7408L_DFN8-5

12

PHASE_NB

PR108

10_0402_5%

12

39

LGATE_NB

VW1

22

+APU_CORE_NB

1 2

PR139

10_0402_5%

1 2

PR112

12

23.7K_0402_1%

37

38

BOOT_NB

PHASE_NB

UGATE_NB

BOOT0

UGATE0

PHASE0

PGND0

LGATE0

PVCC

LGATE1

PGND1

PHASE1

UGATE1

BOOT1

ISN1

TP

23

24

49

ISN0

ISP0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BOOT_NB

LGATE_NB

APU_VDDNB_RUN_FB_ H <4>

APU_VDDNB_RUN_FB_ L <4>

PHASE_NB

LGATE_NB

PHASE_NB

UGATE_NB

BOOT_NB

36

BOOT0

35

UGATE0

34

PHASE0

33

32

LGATE0

31

30

29

28

27

26

25

C

AON7408L_DFN8-5

UGATE_NB

PR105

2.2_0603_1%

1 2

PC102

0.22U_0603_10V7K

UGATE0

PHASE0

BOOT0

+5VALW

12

PC114

PC114 1U_0603_16V6K

1U_0603_16V6K

2010/08/12 2012/08/12

5

4

5

4

AON7408L_DFN8-5

PR118

2.2_0603_1%

1 2

PC111

0.22U_0603_10V7K

LGATE0

Compal Secret Data

PC95

123

PQ28

PQ28 FDMC7692S_MLP8-5

FDMC7692S_MLP8-5

PQ29

4

1 2

4

Deciphered Date

12

PC97

PC96

4.7U_0805_25V6-K

2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%

12

@

PR107

4.7_1206_5%

12

@

PC104

PC104 680P_0603_50V7K

680P_0603_50V7K

5

123

5

123

PQ30

PQ30 FDMC7692S_MLP8-5

FDMC7692S_MLP8-5

D

12

0.1U_0603_25V7K

1 2

PC106

4.7U_0805_25V6-K

D

E

PL15

HCB2012KF-121T50_0805

12

PC98

2200P_0402_50V7K

PL16

12

PC107

1

+

PC99

2

@

68U_25V_M_R0.44

1

2

12

PC109

PC108

4.7U_0805_25V6-K

12

+APU_CORE_NB

+

PC103

220U_D2_2VY_R15M

CPU_B+

12

PC110

0.1U_0603_25V7K

0.1U_0603_25V7K 2200P_0402_50V7K

2200P_0402_50V7K

12

@

PR122

4.7_1206_5%

12

PC112

@PC112

@

680P_0603_50V7K

Title

Size Document Number Rev

Date: Sheet of

B+

PL17

2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%

1 2

PR123

6.98K_0402_1%

1 2

PC113

12

0.1U_0603_16V7K

12

PR127

1.87K_0402_1%

ISP0

Compal Electronics, Inc.

ISN0

CPU_CORE

E

35 36Wednesday, November 17, 2010

+APU_CORE

1.0

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 1 for PWR

Reason for change Rev. PG# Modify List Date PhaseFixed IssueItem

D D

1

2

3

4

5

6

7

C C

8

9

10

11

12

13

Modify CP point for 40W adapter (40W*0.85=34W) 1 30

Modify Outpot current sensor follow PAV70 design 1 30

Modify KI =1.62 follow PAV70 design 1 30

Modify 1.5V OCP (there is only one dimm for 10.1")

1 32

Modify 1.1V OCP for G5603 1 33

Modify 1.05V OCP for G5603 1 33 20101011 EVT

Modify +APU CORE OCP setting 1 35

+APU CORE power sequence concern

Modify RTC schematic 1 28 add PR141 & PR142 =560 ohm 20101011 EVT

Modify SY8033B Enable pin pull down resistor 1 32 Change PR72 to non-pop 20101011 EVT

Modify 1.8VS power sequence 1 32 Change PR70 to 200K ohm , add PC56 =0.22uF 20101012 EVT

Modify 1.05VSP power sequence 1 33 Change PR92 to 200K ohm , add PC82 =0.1uF 20101012 EVT

Modify 0.75VSP power sequence 1 34 Change PR101 to 300K ohm , add PC92 =0.1uF 20101012 EVT

Change PR43 from SD034249280 (S RES 1/16W 24.9K +-1%

0402) to SD034470180 (S RES 1/16W 4.7K +-1% 0402)

Change PR38 from SD012200D80 (S RES 1/2W 0.02 +-1%

1206) to SD00000CI10 (S RES 1/2W 0.05 +-1% 1206 )

Change PR39 from SD034309380 (S RES 1/16W 309K +1%

0402) to SD034620280 (S RES 1/16W 62K +-1% 0402)

Change PR73 from SD034787180 (S RES 1/16W 7.87K +-1%

0402) to SD034150280 (S RES 1/16W 15K +-1% 0402)

Change PR88 from SD034100280 (S RES 1/16W 10K +-1%

0402) to SD034130280 (S RES 1/16W 13K +-1% 0402)

Change PR96 from SD034140280 (S RES 1/16W 14K +-1%

0402) to SD034150280 (S RES 1/16W 15K +-1% 0402)

Change PR123 to 6.98K ohm , PR127 to 1.87K ohm, PR125 to 90.9K ohm, PR126 to 26.1K ohm

20101011 EVT

change PR116 to non-pop1 35 20101011 EVT

14

15

B B

16

17

18

19

20

21

22

A A

23

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/12 2012/08/12

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PIR (PWR)

36 36Monday, November 15, 2010

1

1.0

Compal LA-7072P P0VE6, Aspire One AO522 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual