COMPAL LA-7012P Schematics

A

ZZZ3

ZZZ2

ZZZ1

ZZZ1

PCB

PCB

15"DAZ@

1 1

15"DAZ@

ZZZ2

LA-7012P

LA-7012P

15"DA@

15"DA@

ZZZ3

LS-7012P

LS-7012P

15"DA@

15"DA@

ZZZ4

ZZZ4

LS-7013P

LS-7013P

15"DA@

15"DA@

ZZZ5

ZZZ5

LS-7014P

LS-7014P

15"DA@

15"DA@

B

C

D

E

Compal Confidential

Schematics Document

2 2

PAW20

Montevina

3 3

4 4

with Intel Cantiga + ICH9 core logic

REV:1.0A

2010-12-24

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/09/10 2010/08/19

2010/09/10 2010/08/19

2010/09/10 2010/08/19

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics,Ltd.

Compal Electronics,Ltd.

Compal Electronics,Ltd.

Title

Title

Title

Cover Sheet

Cover Sheet

Cover Sheet

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA7012P

LA7012P

LA7012P

Date: Sheet

Date: Sheet

D

Date: Sheet

141Friday, December 24, 2010

141Friday, December 24, 2010

141Friday, December 24, 2010

of

of

E

of

1.0

1.0

1.0

A

Compal confidential

File Name :

1 1

Clock Generator

SLG8SP556VTR

B

page16

C

Mobile Penryn

uPGA-478 CPU

page4,5,6

D

For 14"
LS-7011P 4PIN PWR/B
LS7013P Audio/B
LS7014P Touch/B

E

For 15"
LS-7012P 8PIN PWR/B
LS7013P Audio/B
LS7014P Touch/B

H_A#(3..35)
H_D#(0..63)

FSB
667/800MHz

CRT Connector

page21

LVDS
Connector

2 2

page22

Intel Cantiga GMCH

GM45

uFCBGA 1329

page 7,8,9,10,11,12,13

DMI

点点点点

4

C-Link

Dual Channel

DDR3-667/800(1.5V)

AZALIA

DDR3-SO-DIMM X2

BANK 0, 1, 2, 3

up to 4G

page 14,15

Audio Codec

CONEXTAN
CX20671

page26

2Channel Speaker

Analog MIC_Int

page26

page26

Wire Less Mini
card Slot 1

6*PCI-E BUS

page23

SPI ROM

Intel ICH9-M

page 17,18,19,20

14*USB2.0

6*SATA serial

CMOS Camera

BlueTooth CONN

page22

page30

BIOS

USB CONN X1(Right)

LPC BUS

3 3

AR8151/8152

10/100/Giga LAN

RJ45 CONN

page25

page24

EC

ENE KB926 E0

page27

Int.KBD

page32

USB PORT X1(Left)

USB PORT X1(Left)

page29

page29

page29

Audio Jack SB CONN

HP X 1+
MIC_Ext X1

page30

Card Reader RTS5139

SPI ROM
BIOS

4 4

A

B

Touch Pad

page32

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Issued Date

Issued Date

C

page28

Compal Secret Data

Compal Secret Data

2010/09/10 2010/08/19

2010/09/10 2010/08/19

2010/09/10 2010/08/19

Compal Secret Data

SATA HDD CONN

SATA ODD CONN

Deciphered Date

Deciphered Date

Deciphered Date

D

page28

page32

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

MB Block Diagram

MB Block Diagram

MB Block Diagram

LA7012P

LA7012P

LA7012P

E

of

of

of

241Friday, December 24, 2010

241Friday, December 24, 2010

241Friday, December 24, 2010

1.0

1.0

1.0

A

DDR3 Voltage Rails

B

C

D

E

SMBUS Control Table

X
X

+3VS

HEX

A0

D2

WLAN
WWAN

+3VALW

+5VS

power
plane

1 1

+B

State

S0

S3

2 2

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
d

on't exist

O

O

O

O

X

+5VALW

+3VALW

O

O

O

X

XX X

+1.5V

O

XX

X

+3VS

+1.5VS

+CPU_CORE

+VGA_CORE

+1.8VS

+0.75VS

+1.05VS

OO

X

X

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
ICH_SMBCLK
ICH_SMBDATA

SOURCE

KB926

+3VALW

KB926

+3VALW

ICH

+3VALW

BATT KB926 SODIMM CLK CHIP

V

+3VALW

X
X

X
X
X

X
X

VV

+3VS

I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM
0

DDR SO-DIMM
1

CLOCK GENERATOR (EXT.)

X
X

V

ADDRESS

1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0A4
1 1 0 1 0 0 1 0

ICH9

X
X
X

Therml

X

V

+3VS

X

@ FUNCTION

DescriptionStructure

45@ 45 BOM
BT@

CMOS@

3 3

4 4

Blue Tooth function
CMOS CAMERA function

NON-USE

PCIE PORT LIST

DEVICEPORT

LAN

1
2

WLAN

3
4
5
6
7
8

USB PORT LIST

DEVICEPORT

0

RIGHT SIDE
LEFT SIDE

1

CMOS

2
3

CARD READER

4
5

WIRELESS
BT6

7

USB PORT(ESATA)
8
9
10
11
12
13

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/09/10 2010/08/19

2010/09/10 2010/08/19

2010/09/10 2010/08/19

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

MB Notes List

MB Notes List

MB Notes List

LA7012P

LA7012P

LA7012P

E

of

of

of

341Friday, December 24, 2010

341Friday, December 24, 2010

341Friday, December 24, 2010

1.0

1.0

1.0

A

B

C

D

E

ME@

ME@

JCPU1A

H_A#[3..16]<7>

1 1

H_ADSTB#0<7>

H_REQ#0<7>
H_REQ#1<7>
H_REQ#2<7>
H_REQ#3<7>
H_REQ#4<7>

H_A#[17..35]<7>

2 2

H_ADSTB#1<7>

H_A20M#<18>

H_FERR#<18>

H_IGNNE#<18>

H_STPCLK#<18>
H_INTR<18>

H_NMI<18>
H_SMI#<18>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

RSVD pins on the CPU
should be left as NO
CONNECT

JCPU1A

J4

ADDR GROUP_0

ADDR GROUP_0

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]

N5

RSVD[02]

T2

RSVD[03]

V3

RSVD[04]

B2

RSVD[05]

D2

RSVD[06]

D22

RSVD[07]

D3

RSVD[08]

F6

RSVD[09]

ADDR GROUP_1

ADDR GROUP_1

THERMAL

THERMAL

ICH

ICH

THERMTRIP#

RESERVED

RESERVED

ADS#
BNR#
BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK

TDO
TMS

TRST#

DBR#

XDP/ITP SIGNALS

XDP/ITP SIGNALS

PROCHOT#

THERMDA
THERMDC

H CLK

H CLK

BCLK[0]
BCLK[1]

TDI

H_ADS#

H1

H_BNR#

E2

H_BPRI#

G5

H_DEFER#

H5

H_DRDY#

F21

H_DBSY#

E1

H_BR0#

F1

H_IERR#

D20

H_INIT#

B3

H_LOCK#

H4

H_RESET#

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3

H_TRDY#

G2

H_HIT#

G6

H_HITM#

E4

AD4
AD3
AD1
AC4
AC2
AC1

XDP_TCK

AC5

XDP_TDI

AA6

XDP_TDO

AB3

XDP_TMS

AB5

XDP_TRST#

AB6

XDP_DBRESET#

C20

H_PROCHOT#

D21

H_THERMDA

A24

H_THERMDC

B25

H_THERMTRIP#

C7

CLK_CPU_BCLK

A22

CLK_CPU_BCLK#

A21

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

H_ADS# <7>
H_BNR# <7>

H_BPRI# <7>

H_DEFER# <7>

H_DRDY# <7>
H_DBSY# <7>

H_BR0# <7>

H_INIT# <18>

H_LOCK# <7>

H_RESET# <7>
H_RS#0 <7>
H_RS#1 <7>
H_RS#2 <7>
H_TRDY# <7>

H_HIT# <7>
H_HITM# <7>

XDP_DBRESET# <19>

H_THERMTRIP# <8,18>

CLK_CPU_BCLK <16>
CLK_CPU_BCLK# <16>

H_IERR#

H_PROCHOT#

1 2

C832 2200P_0402_50V7KC832 2200P_0402_50V7K

+3VS

R714 56_0402_5%R714 56_0402_5%

1 2

R715 68_0402_5%R715 68_0402_5%

1 2

1

C831

C831

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

H_THERMDA

H_THERMDC

THERM#

1 2

R716 10K _0402_5%R716 10K _0402_5%

+1.05VS +1.05VS

U1

U1

1

VDD

2

DP

3

DN

4

THERM#

EMC1402-1-ACZL-TR_MSOP8

EMC1402-1-ACZL-TR_MSOP8

Address:100_1100

PVT ESD solution.
Please close to R715

+3VS+3VS

12

R713
10K_0402_5%

10K_0402_5%

EC_SMB_CK2

8

SMCLK

SMDATA

ALERT#

GND

EC_SMB_DA2

7

6

5

1

C864

C864

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

R713

EC_SMB_CK2 <27>

EC_SMB_DA2 <27>

Penryn

Penryn

10/01 Add for reduce noise

H_RESET#

3 3

4 4

XDP Reserve for debug , Please close to CPU side

XDP_DBRESET#

XDP_TDI

XDP_TMS

XDP_TDO

XDP_TRST#

XDP_TCK

A

R718 1K_0402_5%@R718 1K_0402_5%@

1 2

R8 54.9_0402_1%R8 54.9_0402_1%

1 2

R9 54.9_0402_1%R9 54.9_0402_1%

1 2

R10 54.9_0402_1%@R10 54.9_0402_1%@

1 2

R11 54.9_0402_1%R11 54.9_0402_1%

1 2

R12 54.9_0402_1%R12 54.9_0402_1%

1 2

+3VS

+1.05VS

Place closely pin C1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/09/10 2010/08/19

2010/09/10 2010/08/19

2010/09/10 2010/08/19

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

C651

C651

1

@

@

2

100P_0402_50V8J

100P_0402_50V8J

D

09/16 Add C834 For ESD

XDP_DBRESET#

1

C834

C834

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

Place closely pin C20

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Penryn(1/3)-AGTL+THM,FAN

Penryn(1/3)-AGTL+THM,FAN

Penryn(1/3)-AGTL+THM,FAN

LA7012P

LA7012P

LA7012P

E

of

of

of

441Friday, December 24, 2010

441Friday, December 24, 2010

441Friday, December 24, 2010

1.0

1.0

1.0

5

ME@

ME@

JCPU1B

H_D#[0..15]<7>

D D

H_DSTBN#0<7>
H_DSTBP#0<7>
H_DINV#0<7>

H_D#[16..31]<7>

H_DSTBN#1<7>
H_DSTBP#1<7>

C C

FSB

533

667

800

B B

A A

1067 266 000

Layout note: Z0=55 ohm

0.5" max for GTLREF.

Close to CPU pin AD26
within 500mils.

H_DINV#1<7>

R14 1K_0402_5%@R14 1K_0402_5%@

1 2

R16 1K_0402_5%@R16 1K_0402_5%@

1 2

CPU_BSEL0<16>
CPU_BSEL1<16>
CPU_BSEL2<16>

BCLK BSEL2 BSEL1 BSEL0

133

001

166

200

+CPU_GTLREF

+1.05VS

12

R19

R19
1K_0402_1%

1K_0402_1%

12

R20

R20
2K_0402_1%

2K_0402_1%

100

T1T1
T2T2
T3T3
T4T4
T157T157

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

+CPU_GTLREF

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

TEST7
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

110

JCPU1B

E22

D[0]#

F24

D[1]#

AD26

AF26

E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25

N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24

C23
D25
C24

AF1
A26

C3
B22
B23
C21

D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL[0]
BSEL[1]
BSEL[2]

Penryn

Penryn

MISC

MISC

DATA GRP 0

DATA GRP 0

DATA GRP 1

DATA GRP 1

DATA GRP 2DATA GRP 3

DATA GRP 2DATA GRP 3

DSTBN[2]#
DSTBP[2]#

DINV[2]#

DSTBN[3]#
DSTBP[3]#

DINV[3]#

COMP[0]
COMP[1]
COMP[2]
COMP[3]

DPRSTP#

PWRGOOD

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

4

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#

DPSLP#
DPWR#

SLP#

PSI#

TRACE CLOSELY CPU < 0.5'

COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms)
COMP1, COMP3 layout : Width 5mils and Space 25mils (55Ohms)

AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

COMP0
COMP1
COMP2
COMP3

H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#

R719 27.4_0402_1%R719 27.4_0402_1%

1 2

R15 54.9_0402_1%R15 54.9_0402_1%

1 2

R720 27.4_0402_1%R720 27.4_0402_1%

1 2

R18 54.9_0402_1%R18 54.9_0402_1%

1 2

H_D#32

Y22

H_D#[32..47] <7>

H_DSTBN#2 <7>
H_DSTBP#2 <7>
H_DINV#2 <7>

H_D#[48..63] <7>

H_DSTBN#3 <7>
H_DSTBP#3 <7>
H_DINV#3 <7>

H_DPRSTP# <8,18,40>
H_DPSLP# <18>
H_DPWR# <7>
H_PWRGOOD <18>
H_CPUSLP# <7>

H_PSI# <40>

09/29 Add for power nois e

1

C652

C652
470P_0402_50V7K

470P_0402_50V7K

2

Close to Power IC
(PU9.12) within
500mils.

3

H_DPRSTP# H_DPSLP# H_PSI#H_DPRSTP#

1

C630

C630
470P_0402_50V7K

470P_0402_50V7K

2

Close to CPU pin E5
within 500mils.

ME@

ME@

JCPU1D

JCPU1D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]
VSS[081]P3VSS[162]

Penryn

Penryn

2

P6

VSS[082]

P21

VSS[083]

P24

VSS[084]

R2

VSS[085]

R5

VSS[086]

R22

VSS[087]

R25

VSS[088]

T1

VSS[089]

T4

VSS[090]

T23

VSS[091]

T26

VSS[092]

U3

VSS[093]

U6

VSS[094]

U21

VSS[095]

U24

VSS[096]

V2

VSS[097]

V5

VSS[098]

V22

VSS[099]

V25

VSS[100]

W1

VSS[101]

W4

VSS[102]

W23

VSS[103]

W26

VSS[104]

Y3

VSS[105]

Y6

VSS[106]

Y21

VSS[107]

Y24

VSS[108]

AA2

VSS[109]

AA5

VSS[110]

AA8

VSS[111]

AA11

VSS[112]

AA14

VSS[113]

AA16

VSS[114]

AA19

VSS[115]

AA22

VSS[116]

AA25

VSS[117]

AB1

VSS[118]

AB4

VSS[119]

AB8

VSS[120]

AB11

VSS[121]

AB13

VSS[122]

AB16

VSS[123]

AB19

VSS[124]

AB23

VSS[125]

AB26

VSS[126]

AC3

VSS[127]

AC6

VSS[128]

AC8

VSS[129]

AC11

VSS[130]

AC14

VSS[131]

AC16

VSS[132]

AC19

VSS[133]

AC21

VSS[134]

AC24

VSS[135]

AD2

VSS[136]

AD5

VSS[137]

AD8

VSS[138]

AD11

VSS[139]

AD13

VSS[140]

AD16

VSS[141]

AD19

VSS[142]

AD22

VSS[143]

AD25

VSS[144]

AE1

VSS[145]

AE4

VSS[146]

AE8

VSS[147]

AE11

VSS[148]

AE14

VSS[149]

AE16

VSS[150]

AE19

VSS[151]

AE23

VSS[152]

AE26

VSS[153]

A2

VSS[154]

AF6

VSS[155]

AF8

VSS[156]

AF11

VSS[157]

AF13

VSS[158]

AF16

VSS[159]

AF19

VSS[160]

AF21

VSS[161]

A25
AF25

VSS[163]

.

.

1

C636

C636

100P_0402_50V8J

100P_0402_50V8J

Close to CPU pin B5
within 500mils.

2

1

C642

C642
470P_0402_50V7K

470P_0402_50V7K

2

Close to Power IC

1

PVT for ESD s olution

H_PWRGOOD

1

C637

C637
330P_0402_50V7K

330P_0402_50V7K

2

Close to CPU pin D6
within 500mils.

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/10 2010/08/19

2010/09/10 2010/08/19

2010/09/10 2010/08/19

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Doc ument Number Rev

Size Doc ument Number Rev

Size Doc ument Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Penryn(2/3)-AGTL+GND

Penryn(2/3)-AGTL+GND

Penryn(2/3)-AGTL+GND

LA7012P

LA7012P

LA7012P

1

of

of

of

541Friday, December 24, 2010

541Friday, December 24, 2010

541Friday, December 24, 2010

1.0

1.0

1.0

5

+CPU_CORE +CPU_CORE

D D

C C

B B

AA10
AA12
AA13
AA15
AA17
AA18
AA20

AC10
AB10
AB12
AB14
AB15
AB17
AB18

ME@

ME@

JCPU1C

JCPU1C

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]

AB9

VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]

Penryn

Penryn

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18

+1.05VS

AF20

G21
V6

1
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

.

.

+

+

C60

C60
330U_D2E_2.5VM_R9M

330U_D2E_2.5VM_R9M

2

CPU_VID0 <40>
CPU_VID1 <40>
CPU_VID2 <40>
CPU_VID3 <40>
CPU_VID4 <40>
CPU_VID5 <40>
CPU_VID6 <40>

VCCSENSE

VSSSENSE

330U_D2E_2.5VM_R9M

330U_D2E_2.5VM_R9M

NEAR PIN B26

20mils

1

C52

C52

C51

C51

2

10U_0805_10V4Z

10U_0805_10V4Z

VCCSENSE <40>

VSSSENSE <40>

1

2

The trace width/space/other is 18/7/25.

Layout Note:
Route VCCSENSE and VSSSENSE traces at

27.4 Ohms with 50 mil spacing.
Place PU and PD within 1 inch of CPU.
Length matched to within 25 mils.

4

+CPU_CORE

330U_D2E_2.5VM_R9M

1

C81

C81

2

330U_D2E_2.5VM_R9M

1

+

+

+

+

2

C86

C86

@

@

330U_D2E_2.5VM_R9M

330U_D2E_2.5VM_R9M

330U_D2E_2.5VM_R9M

330U_D2E_2.5VM_R9M

1

+

+

C82

C82

2

1

+

+

C94

C94

2

PVT Change C82 and C94 from SF000002O00 to SGA19331D10

+CPU_CORE

1

C18

Place these capacitors on L1
(North side,Secondary Layer)

Place these capacitors on L1
(North side,Secondary Layer)

Place these capacitors on L1
(South side,Secondary Layer)

+1.5VS

Place these capacitors on L1
(South side,Secondary Layer)

0.01U_0402_16V7K

0.01U_0402_16V7K

Mid Frequence Decoupling

2

+CPU_CORE

1

2

+CPU_CORE

1

2

+CPU_CORE

1

2

C18

10U_0805_6.3V6M

10U_0805_6.3V6M

C26

C26

10U_0805_6.3V6M

10U_0805_6.3V6M

C35

C35

10U_0805_6.3V6M

10U_0805_6.3V6M

C43

C43

10U_0805_6.3V6M

10U_0805_6.3V6M

3

+1.05VS

Place these inside socket cavity on L8
(North side Secondary)

1

C8

C8

0.1U_0402_10V6K

0.1U_0402_10V6K

2

1

C19

C19

10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C27

C27

10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C36

C36

10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C44

C44

10U_0805_6.3V6M

10U_0805_6.3V6M

2

09/29 Add for power noise

Close to Power IC

1

C20

C20

10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C28

C28

10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C37

C37

10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C45

C45

10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C9

C9

0.1U_0402_10V6K

0.1U_0402_10V6K

2

1

C21

C21

10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C29

C29

10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C38

C38

10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C46

C46

10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C10

C10

0.1U_0402_10V6K

0.1U_0402_10V6K

2

1

C22

C22

10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C30

C30

10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C39

C39

10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C47

C47

10U_0805_6.3V6M

10U_0805_6.3V6M

2

2

1

C11

C11

0.1U_0402_10V6K

0.1U_0402_10V6K

2

1

C23

C23

10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C31

C31

10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C40

C40

10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C48

C48

10U_0805_6.3V6M

10U_0805_6.3V6M

2

CPU_VID0

CPU_VID1

CPU_VID2

CPU_VID3

CPU_VID4

CPU_VID5

CPU_VID6

1

C12

C12

0.1U_0402_10V6K

0.1U_0402_10V6K

2

1

C24

C24

10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C32

C32

10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C41

C41

10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C49

C49

10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C835

C835

0.1U_0402_10V6K

0.1U_0402_10V6K

2

1

C836

C836

10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C837

C837

10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C42

C42

10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

C50

C50

10U_0805_6.3V6M

10U_0805_6.3V6M

2

1

1

1

C644

C644

C643

C643

2

100P_0402_50V8J

+CPU_CORE

A A

R21

R21
100_0402_1%

100_0402_1%

1 2

R22

R22
100_0402_1%

100_0402_1%

1 2

VCCSENSE

VSSSENSE

100P_0402_50V8J

C646

C646

2

100P_0402_50V8J

100P_0402_50V8J

1

1

C647

C647

2

100P_0402_50V8J

100P_0402_50V8J

1

C649

C649

C648

C648

2

2

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

1

1

C650

C650

2

2

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

Close to CPU pin
within 500mils.

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/10 2010/08/19

2010/09/10 2010/08/19

2010/09/10 2010/08/19

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Penryn(3/3)-PWR+Bypass

Penryn(3/3)-PWR+Bypass

Penryn(3/3)-PWR+Bypass

LA7012P

LA7012P

LA7012P

1

of

of

of

641Friday, December 24, 2010

641Friday, December 24, 2010

641Friday, December 24, 2010

1.0

1.0

1.0

5

4

3

2

1

U3A

AD14

AA13

AA11
AD11
AD10
AD13
AE12

AE14

AE11

F2

G8
F8
E6
G2
H6
H2
F6
D4
H3
M9

M11

J1

J2

N12

J6

P2

L2

R2
N9

L6

M5

J3

N2
R1
N5
N6

P13

N8

L7

N10

M3
Y3

Y6
Y10
Y12
Y14

Y7

W2

AA8

Y9

AA9

AE9
AA2
AD8
AA3
AD3
AD7

AF3
AC1
AE3
AC3

AE8
AG2
AD6

C5

E3

C12
E11

A11
B11

U3A

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_SWING
H_RCOMP

H_CPURST#
H_CPUSLP#

H_AVREF
H_DVREF

CANTIGA ES_FCBGA 1329

CANTIGA ES_FCBGA 1329

GM45@

GM45@

H_ADSTB#_0
H_ADSTB#_1

H_DEFER#

HOST

HOST

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_BREQ#

H_DBSY#

H_DRDY#

H_HIT#
H_HITM#

H_LOCK#
H_TRDY#

H_RS#_0
H_RS#_1
H_RS#_2

H_D#[0..63]<5>

D D

C C

B B

H_RESET#<4>
H_CPUSLP#<5>

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWNG
H_RCOMP

H_RESET#
H_CPUSLP#

H_VREF

U3

U3

GL40

GL40

GL40@

GL40@

A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20

H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9

J8
L3
Y13
Y1

L10
M7
AA5
AE6

L9
M8
AA6
AE5

B15
K13
F13
B13
B14

B6
F12
C8

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

H_A#[3..35] <4>

H_ADS# <4>
H_ADSTB#0 <4>
H_ADSTB#1 <4>
H_BNR# <4>
H_BPRI# <4>
H_BR0# <4>
H_DEFER# <4>
H_DBSY# <4>
CLK_MCH_BCLK <16>
CLK_MCH_BCLK# <16>
H_DPWR# <5>
H_DRDY# <4>
H_HIT# <4>
H_HITM# <4>
H_LOCK# <4>
H_TRDY# <4>

H_DINV#0 <5>
H_DINV#1 <5>
H_DINV#2 <5>
H_DINV#3 <5>

H_DSTBN#0 <5>
H_DSTBN#1 <5>
H_DSTBN#2 <5>
H_DSTBN#3 <5>

H_DSTBP#0 <5>
H_DSTBP#1 <5>
H_DSTBP#2 <5>
H_DSTBP#3 <5>

H_REQ#0 <4>
H_REQ#1 <4>
H_REQ#2 <4>
H_REQ#3 <4>
H_REQ#4 <4>

H_RS#0 <4>
H_RS#1 <4>
H_RS#2 <4>

Layout Note:
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20

12

R23

R23
1K_0402_1%

1K_0402_1%

12

R25

R25
2K_0402_1%

2K_0402_1%

H_VREF

1

C53

C53

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

within 100 mils from NB

PVT ESD solution.

Please close to R23

+1.05VS

1

C70

C70

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

12

R26

R26

24.9_0402_1%

24.9_0402_1%

H_RCOMP

+1.05VS+1.05VS

12

R24

R24
221_0603_1%

221_0603_1%

12

R27

R27
100_0402_1%

100_0402_1%

H_SWNG

1

C54

C54

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

Near B3 pin

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/10 2010/08/19

2010/09/10 2010/08/19

2010/09/10 2010/08/19

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Doc ument Number Rev

Size Doc ument Number Rev

Size Doc ument Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Cantiga(1/7)-AGTL+

Cantiga(1/7)-AGTL+

Cantiga(1/7)-AGTL+

LA7012P

LA7012P

LA7012P

1

of

of

of

741Friday, December 24, 2010

741Friday, December 24, 2010

741Friday, December 24, 2010

1.0

1.0

1.0

5

Strap Pin Table

011 = FSB667

CFG[2:0]

Internal pull-up

CFG5

Internal pull-up

CFG6

D D

C C

B B

Internal pull-up

CFG7

Internal pull-up

CFG9

Internal pull-up

CFG10

CFG[13:12]

Internal pull-up

Internal pull-up

CFG16

Internal pull-down

CFG19

CFG20

Internal pull-down

(PCIE/SDVO select)

+1.05VS

12

R722

R722

54.9_0402_1%

54.9_0402_1%

@

@

MCH_TSATN# TSATN#

+3VS

12

ICH_POK<19,27>

VGATE<19,40>

PLT_RST#<17,23,24>

Place closely p in U3.R32 Place closely pin PR132.2

DPRSLPVR DPRSLPVR

1

C861

C861
1000P_0402_50V7K

1000P_0402_50V7K

2

09/16 Add C838 For noise

Place closely pin AT11

A A

PLT_RST#_R

1

C838

C838

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

010 = FSB800
000 = FSB1067

0 = DMI x 2
1 = DMI x 4

0 = iTPM Host Interface is enabled

1 = iTPM Host Interface is Disabled

0 = Intel Management Engine Crypto Transport Layer Security
(TLS) cipher s uite with no confidentiality

1 = Intel Management Engine Crypto TLS cipher suite with
confidentiality

0 = Lane Reversal Enable
1 = Normal Operation (Default)

0 = PCIe Loopback Enable
1 = Disable

01 = All Z Mode Enabled
00 = Reserved
10 = XOR Mode Enabled
11 = Normal Operation

0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled

0 = Normal Operation
1 = DMI Lane Reversal Enable

(Default)

*

(Default)

*

(Default)

*

*

(Default)

*

can support disble by SW.

(Default)

*

(Default)

*

0 = Only PCIE or [SDVO/ DP/HDMI] is operational.

1 = PCIE/[SDVO/DP/ HDMI] are operating sim u.

12

+3VS

R33

R33
1K_0402_5%

1K_0402_5%

@

@

12

R723

R723
1K_0402_5%

12

R48

R48
10K_0402_5%

10K_0402_5%

1

2

1K_0402_5%

@

@

PM_EXTTS#0
PM_EXTTS#1

C862

C862
1000P_0402_50V7K

1000P_0402_50V7K

TSATN# <27>

+3VS

PM_POK_R

PLT_RST#_R

B

B

2

E

E

3 1

C

C

Q42

Q42
MMBT3904_SOT23-3

MMBT3904_SOT23-3

@

@

R47

R47
10K_0402_5%

10K_0402_5%

R51 0_0402_5%R51 0_0402_5%

1 2

R727 0_0402_5%@R727 0_0402_5%@

1 2

R728 100_0402_5%R728 100_0402_5%

1 2

Place closely pin B7 Place closely pin AR36

H_DPRSTP# SM_PWROK

5

1

C631

C631
470P_0402_50V7K

470P_0402_50V7K

2

C638

C638

1

2

100P_0402_50V8J

100P_0402_50V8J

(Default)

*

MCH_CLKSEL0<16>
MCH_CLKSEL1<16>
MCH_CLKSEL2<16>

R725 2.21K_0402_1%@R725 2.21K_0402_1%@

1 2

R39 2.21K_0402_1%@R39 2.21K_0402_1%@

1 2

R40 2.21K_0402_1%@R40 2.21K_0402_1%@

1 2

R41 2.21K_0402_1%@R41 2.21K_0402_1%@

1 2

R42 2.21K_0402_1%@R42 2.21K_0402_1%@

1 2

R44 2.21K_0402_1%@R44 2.21K_0402_1%@

1 2

R45 2.21K_0402_1%@R45 2.21K_0402_1%@

1 2

R46 2.21K_0402_1%@R46 2.21K_0402_1%@

1 2

R49 4.02K_0402_1%@R49 4.02K_0402_1%@

1 2

R50 4.02K_0402_1%@R50 4.02K_0402_1%@

1 2

PM_BMBUSY#<19>

H_DPRSTP#<5,18,40>

PM_EXTTS#0<14,15>

H_THERMTRIP#<4,18>

DPRSLPVR<19,40>

*

4

(Default)

4

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2

MCH_CFG_5
MCH_CFG_6
MCH_CFG_7

MCH_CFG_9
MCH_CFG_10

MCH_CFG_12
MCH_CFG_13

MCH_CFG_16

MCH_CFG_19
MCH_CFG_20

PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_POK_R
PLT_RST#_R
H_THERMTRIP#
DPRSLPVR

AH10
AH12
AH13

AL34
AK34
AN35
AM35

AY21

BG23

BF23
BH18

BF18

AT40

AT11

BG48

BF48
BD48
BC48
BH47
BG47
BE47
BH46

BF46
BG45
BH44
BH43

M36
N36
R33

T33

AH9

K12

T24

B31

B2
M1

T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21

T21
R20
M20

L21
H21
P29
R28

T28

R29

B7
N33
P32

T20

R32

BH6
BH5
BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1

F1
A47

GM45@

GM45@

U3B

U3B

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14

RSVD15
RSVD16
RSVD17

RSVD20

RSVD22
RSVD23
RSVD24
RSVD25

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

PM_SYNC#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26

CANTIGA ES_FCBGA 1329

CANTIGA ES_FCBGA 1329

RSVD CFG PM NC

RSVD CFG PM NC

DDR CLK/ CONTROL/ COMPENSATIONHDA

DDR CLK/ CONTROL/ COMPENSATIONHDA

CLKDMI

CLKDMI

GRAPHICS VID

GRAPHICS VID

MEMISC

MEMISC

SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1

SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1

SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1

SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1

SA_ODT_0
SA_ODT_1

SB_ODT_O

SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH
SM_RCOMP_VOL

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST#

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST#
CL_VREF

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK
HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

3

M_CLK_DDR0

AP24

M_CLK_DDR1

AT21

M_CLK_DDR2

AV24

M_CLK_DDR3

AU20

M_CLK_DDR#0

AR24

M_CLK_DDR#1

AR21

M_CLK_DDR#2

AU24

M_CLK_DDR#3

AV20

DDR_CKE0_DIMMA

BC28

DDR_CKE1_DIMMA

AY28

DDR_CKE2_DIMMB

AY36

DDR_CKE3_DIMMB

BB36

DDR_CS0_DIMMA#

BA17

DDR_CS1_DIMMA#

AY16

DDR_CS2_DIMMB#

AV16

DDR_CS3_DIMMB#

AR13

M_ODT0

BD17

M_ODT1

AY17

M_ODT2

BF15

M_ODT3

AY13

SMRCOMP

BG22

SMRCOMP#

BH21

SMRCOMP_VOH

BF28

SMRCOMP_VOL

BH28

+DDR_MCH_REF

AV42

SM_PWROK

AR36

SM_REXT

BF17

SM_DRAMRST#

BC36

CLK_MCH_DREFCLK

B38

CLK_MCH_DREFCLK#

A38

MCH_SSCDREFCLK

E41

MCH_SSCDREFCLK#

F41

CLK_MCH_3GPLL

F43

CLK_MCH_3GPLL#

E43

DMI_TXN0

AE41

DMI_TXN1

AE37

DMI_TXN2

AE47

DMI_TXN3

AH39

DMI_TXP0

AE40

DMI_TXP1

AE38

DMI_TXP2

AE48

DMI_TXP3

AH40

DMI_RXN0

AE35

DMI_RXN1

AE43

DMI_RXN2

AE46

DMI_RXN3

AH42

DMI_RXP0

AD35

DMI_RXP1

AE44

DMI_RXP2

AF46

DMI_RXP3

AH43

For independent Power Rail : connect to PWM CORE VID
For Common Power Rail : left it No Connect

B33
B32
G33
F33
E33

C34

For AMT function

CL_CLK0

AH37

CL_DATA0

AH36

M_PWROK

AN36

CL_RST#

AJ35

CL_VREF

AH34

N28
M28

SDVO_SCLK

G36
E36

MCH_CLKREQ#

K36

MCH_ICH_SYNC#

H36

MCH_TSATN#

B12

B28
B30
B29
C29
A28

R57 56_0402_5%R57 56_0402_5%

M_CLK_DDR0 <14>
M_CLK_DDR1 <14>
M_CLK_DDR2 <15>
M_CLK_DDR3 <15>

M_CLK_DDR#0 <14>
M_CLK_DDR#1 <14>
M_CLK_DDR#2 <15>
M_CLK_DDR#3 <15>

DDR_CKE0_DIMMA <14>
DDR_CKE1_DIMMA <14>
DDR_CKE2_DIMMB <15>
DDR_CKE3_DIMMB <15>

DDR_CS0_DIMMA# <14>
DDR_CS1_DIMMA# <14>
DDR_CS2_DIMMB# <15>
DDR_CS3_DIMMB# <15>

M_ODT0 <14>
M_ODT1 <14>
M_ODT2 <15>
M_ODT3 <15>

1 2

R29 80.6_0402_1%R29 80.6_0402_1%

SM_DRAMRST# <14,15>

CLK_MCH_DREFCLK <16>
CLK_MCH_DREFCLK# <16>
MCH_SSCDREFCLK <16>
MCH_SSCDREFCLK# <16>

CLK_MCH_3GPLL <16>
CLK_MCH_3GPLL# <16>

DMI_TXN0 <19>
DMI_TXN1 <19>
DMI_TXN2 <19>
DMI_TXN3 <19>

DMI_TXP0 <19>
DMI_TXP1 <19>
DMI_TXP2 <19>
DMI_TXP3 <19>

DMI_RXN0 <19>
DMI_RXN1 <19>
DMI_RXN2 <19>
DMI_RXN3 <19>

DMI_RXP0 <19>
DMI_RXP1 <19>
DMI_RXP2 <19>
DMI_RXP3 <19>

CL_CLK0 <19>
CL_DATA0 <19>

M_PWROK <19>
CL_RST# <19>

T110T110
T109T109

MCH_CLKREQ# <16>
MCH_ICH_SYNC# <19>

1 2

20mil

R30 0_0402_5%R30 0_0402_5%

1 2

R53 12K_0402_5%@R53 12K_0402_5%@

1 2

R721 10K_0402_5%@R721 10K_0402_5%@
R32 499_0402_1%R32 499_0402_1%

1

C59

C59

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

SDVO_CTRLDATA

(Internal pull-down)

(Internal pull-down)

+1.05VS

SM_DRAMRST# is only for DDR3.
DDR2 left it No Connect

1 2
1 2

SMRCOMP_VOH

SMRCOMP_VOL

+1.05VS

12

R726

R726
1K_0402_1%

1K_0402_1%

R729

R729
499_0402_1%

499_0402_1%

Strap Pin Table

2

For DDR3 : 1.5V power rail
For DDR2 : 1.8V power rail

+1.5V

12

R28

R28

80.6_0402_1%

80.6_0402_1%

1.5V_PGOOD <39>
DDR3_SM_PWROK <27>

1

2

1

2

0 = SDVO interface disabled
1 = SDVO interface enabled

0 = Digital display (iHDMI/DP) interface disabled
1 = Digital display (iHDMI/DP) interface enabled

Notice: Please check HDA power rail to select HDA controller.

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/10 2010/08/19

2010/09/10 2010/08/19

2010/09/10 2010/08/19

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

For Crestline: 20ohm
For Calero: 80.6ohm
For Cantiga: 80.6ohm

SDVO_SCLK

1

C56

C56

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

2

1

C58

C58

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

2

(Default)

*

R56

@R56

@

C55

C55

0.01U_0402_25V7K

0.01U_0402_25V7K

C57

C57

0.01U_0402_25V7K

0.01U_0402_25V7K

1

Layout Note:
+DDR_MCH_REF trace
width and spacing is 20/20.
CLOSE TO PIN.AV42

+DDR_MCH_REF

+1.5V

12

R34

R34
1K_0402_1%

1K_0402_1%

12

R724

R724

3.01K_0402_1%

3.01K_0402_1%

12

R43

R43
1K_0402_1%

1K_0402_1%

(Default)DDPC_CTRLDATA

*

+3VS

2.2K_0402_5%

2.2K_0402_5%

12

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Doc ument Number Rev

Size Doc ument Number Rev

Size Doc ument Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Cantiga(2/7)-DMI/DDR/STRP

Cantiga(2/7)-DMI/DDR/STRP

Cantiga(2/7)-DMI/DDR/STRP

LA7012P

LA7012P

LA7012P

1

1

2

C61

C61

0.1U_0402_16V4Z

0.1U_0402_16V4Z

841Friday, December 24, 2010

841Friday, December 24, 2010

841Friday, December 24, 2010

+1.5V

12

R58

R58
10K_0402_1%

10K_0402_1%

12

R64

R64
10K_0402_1%

10K_0402_1%

of

of

of

1.0

1.0

1.0

5

4

3

2

1

D D

C C

B B

DDR_A_D[0..63]<14> DDR_A_BS[0..2] <14>

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33 DDR_A_DQS#0
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AJ38
AJ41
AN38
AM38
AJ36
AJ40
AM44
AM42
AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36

AW36

BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12

AU10

BA11

AN10
AM11

AN12
AM13
AJ11
AJ12

BB9
BA9

AV9

BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5

AM5
AJ9
AJ8

U3D

U3D

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

CANTIGA ES_FCBGA 1329

CANTIGA ES_FCBGA 1329

GM45@

GM45@

SA_BS_0
SA_BS_1
SA_BS_2

SA_RAS#
SA_CAS#

SA_WE#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7

SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

BG18
AT25

BB20
BD20
AY20

AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5

AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7

AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8

BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25

DDR_A_BS1
DDR_A_BS2

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

DDR_A_RAS# <14>
DDR_A_CAS# <14>
DDR_A_WE# <14>

DDR_A_BS0

BD21

DDR_A_DM[0..7] <14>

DDR_A_DQS[0..7] <14>

DDR_A_DQS#[0..7] <14>

DDR_A_MA[0..14] <14>

DDR_B_D[0..63]<15> DDR_B_BS[0..2] <15>

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AK47
AH46
AP47
AP46

AM48
AP48
AU47
AU46
BA48
AY48

AT47
AR47
BA47
BC47
BC46
BC44
BG43

BF43
BE45
BC41

BF40

BF41
BG38

BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11

BH12

BF11

AJ46
AJ48

BG8

BG7

AM2
AM3

BF8

BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1

AH3
AJ3

U3E

U3E

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

CANTIGA ES_FCBGA 1329

CANTIGA ES_FCBGA 1329

GM45@

GM45@

SB_BS_0
SB_BS_1
SB_BS_2

SB_RAS#
SB_CAS#

SB_WE#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7

SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

BB17
BB33

AU17
BG16
BF14

AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2

AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6

AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5

AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33

DDR_B_BS1
DDR_B_BS2

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14

DDR_B_RAS# <15>
DDR_B_CAS# <15>
DDR_B_WE# <15>

DDR_B_BS0

BC16

DDR_B_DM[0..7] <15>

DDR_B_DQS[0..7] <15>

DDR_B_DQS#[0..7] <15>

DDR_B_MA[0..14] <15>

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/10 2010/08/19

2010/09/10 2010/08/19

2010/09/10 2010/08/19

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Doc ument Number Rev

Size Doc ument Number Rev

Size Doc ument Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Cantiga(3/7)-DDR3 A/B CH

Cantiga(3/7)-DDR3 A/B CH

Cantiga(3/7)-DDR3 A/B CH

LA7012P

LA7012P

LA7012P

1

941Friday, December 24, 2010

941Friday, December 24, 2010

941Friday, December 24, 2010

of

of

of

1.0

1.0

1.0

5

4

3

2

1

Place the resistor within 500mils
(1.27mm)of the (G)MCH

PEGCOMP trace width

U3C

+3VS

D D

R730 10K_0402_5%R730 10K_0402_5%

1 2

R731 10K_0402_5%R731 10K_0402_5%

1 2

1 2

R732 2.2K_0402_5%R732 2.2K_0402_5%

1 2

R734 2.2K_0402_5%R734 2.2K_0402_5%

ENBKL

R259

R259

100K_0402_1%

100K_0402_1%

1 2

C C

B B

L_CTRL_CLK

L_CTRL_DATA

EDID_CLK

EDID_DATA

For Cantiga:2.37kohm
For Crestline:2.4kohm
For Calero: 1.5Kohm

Note: All LVDS data
signals/and it's compliments
should be routed
Different ially

Layout Note: Place 150 ȍ termination
resistors close to GMCH

R736 150_0402_1%R736 150_0402_1%

1 2

R72 150_0402_1%R72 150_0402_1%

1 2

R73 150_0402_1%R73 150_0402_1%

1 2

CRT_HSYNC<21>

CRT_VSYNC<21>

10/01
change R74,R75 from 30ohm to 33ohm

DAC_RED
DAC_GRN
DAC_BLU

GMCH_PWM<22>

ENBKL<27>

EDID_CLK<22>
EDID_DATA<22>

GMCH_ENVDD<22>

LVDS_ACLK#<22>
LVDS_ACLK<22>

LVDS_A0#<22>
LVDS_A1#<22>
LVDS_A2#<22>

LVDS_A0<22>
LVDS_A1<22>
LVDS_A2<22>

R481 75_0402_5%R481 75_0402_5%

1 2

R482 75_0402_5%R482 75_0402_5%

1 2

R483 75_0402_5%R483 75_0402_5%

1 2

DAC_BLU<21>

DAC_GRN<21>

DAC_RED<21>

CRT_DDC_CLK<21>
CRT_DDC_DATA<21>

1 2

R74 33_0402_5%R74 33_0402_5%

1 2

R75 33_0402_5%R75 33_0402_5%

GMCH_PWM

ENBKL

L_CTRL_CLK

L_CTRL_DATA
EDID_CLK
EDID_DATA
GMCH_ENVDD

1 2

R735 2.37K_0402_1%R735 2.37K_0402_1%

LVDS_IBG

LVDS_ACLK#
LVDS_ACLK

LVDS_A0#
LVDS_A1#
LVDS_A2#

LVDS_A0
LVDS_A1
LVDS_A2

TVA_DAC
TVB_DAC
TVC_DAC

DAC_BLU

DAC_GRN

DAC_RED

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC_R

CRT_VSYNC_R

20mil

L32
G32
M32
M33
K33

J33
M29

C44
B43
E37
E38

C41
C40
B37
A37

H47
E46
G40
A40

H48
D45

F40
B40

A41
H38
G37

J37

B42
G38

F37
K37

F25
H25
K25

H24

C31
E32

E28

G28

J28

G29

H32

J32

J29
E29

L29

12

R78

R78

1.02K_0402_1%

1.02K_0402_1%

U3C

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN

LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL

LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3

TVA_DAC
TVB_DAC
TVC_DAC

TV_RTN

TV_DCONSEL_0
TV_DCONSEL_1

CRT_BLUE

CRT_GREEN

CRT_RED

CRT_IRTN

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF

CRT_VSYNC

GM45@

GM45@

LVDS TV VGA

LVDS TV VGA

PCI-EXPRESS GRAPHICS

PCI-EXPRESS GRAPHICS

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

PEG_COMPI

PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8

PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

and spacing is 20/25 mils.

T37
T36

H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39

H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40

J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46

J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46

PEGCOMP

1 2

R733 49.9_0402_1%R733 49.9_0402_1%

+VCC_PEG

Please check Power
source if want
support IAMT

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEE T OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEE T OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEE T OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

For Cantiga:1.02kohm
For Crestline:1.3kohm
For Calero: 255ohm

Compal Secret Data

Compal Secret Data

2010/09/10 2010/ 08/19

2010/09/10 2010/ 08/19

2010/09/10 2010/ 08/19

3

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Cantiga(4/7)-VGA/LVDS

Cantiga(4/7)-VGA/LVDS

Cantiga(4/7)-VGA/LVDS

LA7012P

LA7012P

LA7012P

10 41Friday, December 24, 2010

10 41Friday, December 24, 2010

10 41Friday, December 24, 2010

1

1.0

1.0

1.0

5

4

3

2

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C62

C62

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C71

C71

2

R743

R743

1 2

0_0603_5%

0_0603_5%

0.022U_0402_16V7K

0.022U_0402_16V7K

+3VS_DAC_CRT

0.022U_0402_16V7K

0.022U_0402_16V7K

1

C63

C63

2

+3VS_DAC_BG

0.022U_0402_16V7K

0.022U_0402_16V7K

1

C72

C72

2

+1.05VS

+3VS_TVDAC

1

C105

C105

2

10U_0805_10V4Z

10U_0805_10V4Z

C64

C64

10U_0805_10V4Z

10U_0805_10V4Z

C73

C73

1

2

220U_6.3V_M

220U_6.3V_M

1

C106

C106

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

C839

C839

1

2

10U_0805_10V4Z

10U_0805_10V4Z

1

2

1

C89

C89

2

R742

R742

0_0603_5%

0_0603_5%

C116

C116

1

2

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0805_10V4Z

10U_0805_10V4Z

12

0_0805_5%

0_0805_5%

10U_0805_10V4Z

10U_0805_10V4Z

VCC_AXF: 321.35mA
(10UF*1, 1UF*1)

+1.05VS

R81

R81

0_0603_5%

0_0603_5%

VCC_SM_CK: 119.85mA
(10UF*1, 0.1UF*1)

1

2

VCCD_TVDAC: 58.696mA
(0.1UF*1, 0.01UF*1)

+1.8V_TXLVDS: 118.8mA
(22UF*1, 1000PF*1)

R744

R744

R745

R745

0_0805_5%

0_0805_5%

R737

R737

1 2

0_0805_5%

0_0805_5%

C80

C80

R739

R739

0_0603_5%

0_0603_5%

+1.8VS

12

12

+1.5V

+1.5VS

12

+1.05VS

+1.05VS

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9

U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1

B22
B21
A21

BF21
BH20
BG20
BF20

K47

C35
B35
A35

V48
U48
V47
U47
U46

AH48
AF48
AH47
AG47

A8
L1
AB2

+1.05VS

440mA

149.5mA

80mA

1782mA

456mA

1

2

OSCON

220U_6.3V_M

220U_6.3V_M

C65

C65

1

+

+

2

1

C740.47U_0402_6.3V6K C740.47U_0402_6.3V 6K

2

+V1.05VS_AXF

+1.5V_SM_CK

+1.8V_TXLVDS

+3VS_HV

105.3mA

+VCC_PEG

+VCC_DMI

VCC_DMI: 456mA
(0.1UF*1)

20mils

0.47U_0402_6.3V6K

0.47U_0402_6.3V6K

0.47U_0402_6.3V6K

0.47U_0402_6.3V6K

1

1

C112

C112

C111

C111

2

2

852mA

C75

C75

C103

C103

C113

C113

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

C66

C66

2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

0.47U_0402_6.3V6K

0.47U_0402_6.3V6K

+1.05VS_DPLLA

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C67

C67

2

+1.05VS_DPLLB

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C77

C77

2

+1.05VS_HPLL

1

C84

C84

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.05VS

RB751V_SOD323

RB751V_SOD323

+3VS

10/01 Danson

Change D38 from SC1H751H010 to SCS00000Z00 .

+1.05VS_MPLL

C99

C99

0.1U_0402_16V4Z

0.1U_0402_16V4Z

D38

D38

@

@

2 1

2

1

2

C107

C107

1

2

+VCCP_D

R80

R80

1 2

10U_0805_10V4Z

10U_0805_10V4Z

MCK3225151YZF 1210

MCK3225151YZF 1210

1

C68

C68

2

+1.05VS_DPLLA
+1.05VS_DPLLB: 64.8mA
(470UF*1, 0.1UF*1)

R83

R83

1 2

10U_0805_10V4Z

10U_0805_10V4Z

MCK3225151YZF 1210

MCK3225151YZF 1210

1

C78

C78

2

+1.05VS_HPLL: 24mA
(4.7UF*1, 0.1UF*1)

L33

L33

MBK2012121YZF_2P

MBK2012121YZF_2P

1

C85

C85

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

2

1.05VS_MPLL: 139.2mA

L34

L34

(22UF*1, 0.1UF*1)

MBK2012121YZF_2P

MBK2012121YZF_2P

1

C100

C100

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

2

L1

L1

BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

1

C108

C108

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

2

R746

@R746

@

12

10_0402_5%

10_0402_5%

+1.05VS

+1.05VS

12

+1.05VS

12

+1.05VS

+1.5VS_PEG_PLL: 50mA
(0.1UF*1)

12

+1.05VS

R747

R747

12

0_0402_5%

0_0402_5%

+3VS_HV

U3H

1

2

VCCA_CRT_DAC: 73mA (0.1UF*1, 0.01UF*1)

+3VS_DAC_CRT

VCCA_DAC_BG: 2.68mA (0.1UF*1, 0.01UF*1)

+3VS_DAC_BG

+1.05VS_DPLLA

+1.05VS_DPLLB

+1.05VS_HPLL

+1.05VS_MPLL

1

C76

C76

2

20 mils

+1.05VS_PEGPLL

747.5mA

1U_0603_10V4Z

1U_0603_10V4Z

37.95mA

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C98

C98

2

+1.5VS_TVDAC

+1.5VS_QDAC

+1.05VS_HPLL

+1.05VS_PEGPLL

+1.8V_LVDS

139.2mA

1

2

157.2mA

30mA

+1.5VS_PEG_BG: 0.414mA
(0.1UF*1)

OSCON

1

+

+

C90

C90

2

+1.5VS

R740

R740

1 2

0_0805_5%

0_0805_5%

10U_0805_10V4Z

10U_0805_10V4Z

R741

R741

0_0603_5%

0_0603_5%

12

R738

R738

0_0603_5%

0_0603_5%

C91

C91

C95

C95

1

2

+1.5VS_PEG_BG

12

1

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

+1.05VS_A_SM_CK

1U_0402_6.3V4Z

1U_0402_6.3V4Z

10U_0805_10V4Z

10U_0805_10V4Z

1

C96

C96

2

+1.8V_TXLVDS

1000P_0402_50V7K

1000P_0402_50V7K

0.41mA

1

C83

C83

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

+1.05VS_A_SM

1

C92

C92

2

1U_0603_10V4Z

1U_0603_10V4Z

C97

C97

1

2

+3VS_TVDAC: 40mA
(0.1UF*1, 0.01UF*1 for
each DAC)

+3VS_TVDAC

73mA

5mA

32.4mA

32.4mA

24mA

10mA

50mA

C93

C93

79mA

35mA

1mA

50mA

U3H

B27

VCCA_CRT_DAC_1

A26

VCCA_CRT_DAC_2

A25

VCCA_DAC_BG

B25

VSSA_DAC_BG

F47

VCCA_DPLLA

L48

VCCA_DPLLB

AD1

VCCA_HPLL

AE1

VCCA_MPLL

J48

VCCA_LVDS

J47

VSSA_LVDS

AD48

VCCA_PEG_BG

AA48

VCCA_PEG_PLL

AR20

VCCA_SM_1

AP20

VCCA_SM_2

AN20

VCCA_SM_3

AR17

VCCA_SM_4

AP17

VCCA_SM_5

AN17

VCCA_SM_6

AT16

VCCA_SM_7

AR16

VCCA_SM_8

AP16

VCCA_SM_9

AP28

VCCA_SM_CK_1

AN28

VCCA_SM_CK_2

AP25

VCCA_SM_CK_3

AN25

VCCA_SM_CK_4

AN24

VCCA_SM_CK_5

AM28

VCCA_SM_CK_NCTF_1

AM26

VCCA_SM_CK_NCTF_2

AM25

VCCA_SM_CK_NCTF_3

AL25

VCCA_SM_CK_NCTF_4

AM24

VCCA_SM_CK_NCTF_5

AL24

VCCA_SM_CK_NCTF_6

AM23

VCCA_SM_CK_NCTF_7

AL23

VCCA_SM_CK_NCTF_8

B24

VCCA_TV_DAC_1

A24

VCCA_TV_DAC_2

A32

VCC_HDA

M25

VCCD_TVDAC

L28

VCCD_QDAC

AF1

VCCD_HPLL

AA47

VCCD_PEG_PLL

M38

VCCD_LVDS_1

L37

VCCD_LVDS_2

GM45@

GM45@

CRTPLLA LVDSA PEG

CRTPLLA LVDSA PEG

VTT

VTT

POWER

POWER

A SM

A SM

AXF

AXF

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

SM CK

VCC_TX_LVDS

A CK

A CK

HV

HV

TV

TV

HDA

HDA

DMI PEG

DMI PEG

VTTLF

VTTLF

LVDS D TV/CRT

LVDS D TV/CRT

CANTIGA ES_FCBGA1329

CANTIGA ES_FCBGA1329

VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25

VCC_AXF_ 1
VCC_AXF_ 2
VCC_AXF_ 3

VCC_HV_1
VCC_HV_2
VCC_HV_3

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5

VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4

VTTLF1
VTTLF2
VTTLF3

20 mils

OSCON

C104

C104

220U_6.3V_M

220U_6.3V_M

20 mils

+V1.05VS_AXF

10U_0805_10V4Z

10U_0805_10V4Z

+1.5VS_TVDAC

C87

C87

1000P_0402_50V7K

1000P_0402_50V7K

C101

C101

1

2

+VCC_PEG+1.05VS_PEGPLL

1

+

+

2

+VCC_DMI

1U_0603_10V4Z

1U_0603_10V4Z

C114

C114

1

2

C69

C69

1

2

+1.5V_SM_CK

0.022U_0402_16V7K

0.022U_0402_16V7K

1

1

C88

C88

2

2

+1.8V_TXLVDS

C102

C102

1

2

C109

C109

1

2

C115

C115

1

2

1U_0603_10V4Z

1U_0603_10V4Z

C79

C79

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0805_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z

+3VS

1 2

R79

R79
0_0603_5%

0_0603_5%

D D

+3VS

1 2

R82

R82
10_0603_5%

10_0603_5%

VCCA_SM:720mA
(22UF*2, 4.7UF*1, 1UF*1)

C C

VCCA_SM_CK: 220mA
(22UF*1, 2.2UF*1, 0.1UF*1)

+3VS

B B

VCCD_QDAC: 48.363mA

1

C118

C118

2

(0.1UF*1, 0.01UF*1)

0_0603_5%

0_0603_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0805_10V4Z

10U_0805_10V4Z

1

1

C119

C119

2

2

5

R748

R748

+1.8V_LVDS

12

+1.5VS

10U_0805_10V4Z

10U_0805_10V4Z

1

C120

C120

2

+1.5VS_QDAC

1U_0402_6.3V4Z

1U_0402_6.3V4Z

C117

A A

C117

1.8V_LVDS: 60.311111mA
(1UF*1)

R98

R98

0_0603_5%

0_0603_5%
1U_0603_10V4Z

1U_0603_10V4Z

C840

C840

1

2

12

+1.8VS

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CON FIDENTIAL
AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTH ORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CON TAINS

DEPARTMENT EXCEPT AS AUTH ORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CON TAINS

DEPARTMENT EXCEPT AS AUTH ORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/10 2010/08/19

2010/09/10 2010/08/19

2010/09/10 2010/08/19

Compal Secret Dat a

Compal Secret Dat a

Compal Secret Dat a

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Cantiga(6/7)-VCC-1

Cantiga(6/7)-VCC-1

Cantiga(6/7)-VCC-1

LA7012P

LA7012P

LA7012P

1

1.0

1.0

1.0

of

11 41Friday, December 24, 2010

of

11 41Friday, December 24, 2010

of

11 41Friday, December 24, 2010

5

+1.05VS

D D

3060mA

0.22U_0402_10V4Z

0.22U_0402_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z

1

C843

C843

2

C C

B B

A A

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

C849

C849

C848

C848

C847

C847

1

1

1

2

2

2

AG34
AC34
AB34
AA34

AM33
AK33

AJ33

AG33

AF33

AE33
AC33
AA33

W33

AH28

AF28
AC28
AA28

AJ26
AG26
AE26
AC26
AH25
AG25

AF25
AG24

AJ23
AH23

AF23

U3G

U3G

VCC_1
VCC_2
VCC_3
VCC_4

Y34

VCC_5

V34

VCC_6

U34

VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13
VCC_14
VCC_15

Y33

VCC_16
VCC_17

V33

VCC_18

U33

VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34

T32

VCC_35

GM45@

GM45@

VCC CORE

VCC CORE

POWER

POWER

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8

VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28

VCC NCTF

VCC NCTF

VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44

CANTIGA ES_FCBGA 1329

CANTIGA ES_FCBGA 1329

AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23

4

+1.05VS

4140mA

+1.5V

1U_0603_10V4Z

1U_0603_10V4Z

OSCON

C844

C844

220U_6.3V_M

220U_6.3V_M

C850

C850

0.1U_0402_16V4Z

0.1U_0402_16V4Z

EMI +1.5V decoupling

1

C851

C851

2

C852

C852

220U_6.3V_M

220U_6.3V_M

OSCON

1

2

1

2

@

@

10U_0805_10V4Z

10U_0805_10V4Z

1

+

+

C853

C853

2

+

+

1

2

10U_0805_10V4Z

10U_0805_10V4Z

C842

C842

1

2

1

C139

C139

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

@

@

1

C854

C854

2

10U_0805_10V4Z

10U_0805_10V4Z

T11T11
T12T12

0.01U_0402_16V7K

0.01U_0402_16V7K

2

1

+1.05VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C138

C138

2

VCC_AXG_SENSE
VSS_AXG_SENSE

C846

C846

3

U3F

U3F

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16

AV44
BA37
AM40
AV21
AY5
AM10
BB13

AP33
AN33
BH32
BG32

BF32
BD32
BC32
BB32
BA32
AY32

AW32

AV32
AU32

AT32
AR32
AP32
AN32
BH31
BG31

BF31
BG30
BH29
BG29

BF29
BD29
BC29
BB29
BA29
AY29

AW29

AV29
AU29

AT29
AR29
AP29

BA36
BB24
BD16
BB21

AW16
AW13

AT13

AE25
AB25
AA25
AE24
AC24
AA24

AE23
AC23
AB23
AA23

AJ21
AG21
AE21
AC21
AA21

AH20

AF20
AE20
AC20
AB20
AA20

AM15

AL15
AE15

AJ15
AH15
AG15

AF15
AB15
AA15

AN14
AM14

AJ14
AH14

Y26

Y24

Y21

T17
T16

Y15
V15
U15

U14

T14

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35

VCC_SM_36/NC
VCC_SM_37/NC
VCC_SM_38/NC
VCC_SM_39/NC
VCC_SM_40/NC
VCC_SM_41/NC
VCC_SM_42/NC

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42

VCC_AXG_SENSE
VSS_AXG_SENSE

GM45@

GM45@

VCC_AXG_NTCF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC SM

VCC SM

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43

VCC GFX NCTF

VCC GFX NCTF

VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52

POWER

POWER

VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60

VCC GFX

VCC GFX

VCC SM LF

VCC SM LF

CANTIGA ES_FCBGA 1329

CANTIGA ES_FCBGA 1329

+1.05VS

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

2

Check : power

C845

C845

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

PLACE AS CLOSE PIN AS COULD.

C140 0.1U_0402_16V4ZC140 0.1U_0402_16V4Z

C141 0.1U_0402_16V4ZC141 0.1U_0402_16V4Z

1

1

1

2

2

2

C129

C129

0.22U_0402_10V4Z

0.22U_0402_10V4Z

1

2

C142 0.22U_0402_10V4ZC142 0.22U_0402_10V4Z

1

2

1

8000mA

C841

C841

1

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

2

C857 1U_0402_6.3V4ZC857 1U_0402_6.3V4Z

C856 1U_0402_6.3V4ZC856 1U_0402_6.3V4Z

C143 0.22U_0402_10V4ZC143 0.22U_0402_10V4Z

C855 0.47U_0402_6.3V6KC855 0.47U_0402_6.3V6K

1

1

1

2

2

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/10 2010/08/19

2010/09/10 2010/08/19

2010/09/10 2010/08/19

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Doc ument Number Rev

Size Doc ument Number Rev

Size Doc ument Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Cantiga(6/7)-VCC-1

Cantiga(6/7)-VCC-1

Cantiga(6/7)-VCC-1

LA7012P

LA7012P

LA7012P

1

of

12 41Friday, December 24, 2010

of

12 41Friday, December 24, 2010

of

12 41Friday, December 24, 2010

1.0

1.0

1.0

5

U3I

U3I

AU48

VSS_1

AR48

VSS_2

AL48

VSS_3

BB47

VSS_4

AW47

VSS_5

AN47

VSS_6

AJ47

VSS_7

AF47

VSS_8

AD47

D D

C C

B B

A A

AB47

G47

BD46

BA46
AY46

AV46
AR46
AM46

BF44
AH44
AD44

AA44

M44

BC43

AV43
AU43
AM43

BG42

AY42

AT42
AN42

AJ42

AE42

BD41
AU41
AM41
AH41
AD41

AA41

M41
G41

BG40

BB40

AV40
AN40

AT39
AM39

AJ39

AE39

BH38
BC38

BA38
AU38
AH38
AD38

AA38

BF37

BB37
AW37

AT37
AN37

AJ37

BG36
BD36

AK15
AU36

Y47
T47
N47
L47

V46
R46
P46
H46
F46

Y44
U44
T44

F44

J43
C43

N42
L42

Y41
U41
T41

B41

H40
E40

N39
L39
B39

Y38
U38
T38
J38
F38
C38

H37
C37

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

CANTIGA ES_FCBGA 1329

CANTIGA ES_FCBGA 1329

GM45@

GM45@

VSS

VSS

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199

AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6

4

BG21

L12

AW21

AU21
AP21
AN21
AH21
AF21
AB21

R21

M21

J21

G21
BC20
BA20

AW20

AT20
AJ20

AG20

Y20

N20

K20

F20
C20
A20

BG19

A18

BG17

BC17

AW17

AT17

R17
M17
H17
C17

BA16

AU16
AN16

N16
K16
G16
E16

BG15

AC15

W15

A15

BG14

AA14

C14

BG13

BC13
BA13

AN13
AJ13
AE13

N13

L13
G13
E13

BF12
AV12
AT12

AM12

AA12

J12
A12

BD11
BB11
AY11
AN11
AH11

Y11
N11
G11
C11

BG10

AV10
AT10
AJ10
AE10
AA10

M10
BF9

BC9
AN9
AM9
AD9

G9
B9

BH8

BB8
AV8
AT8

U3J

U3J

VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233

VSS_235

VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252

VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273

VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296

CANTIGA ES_FCBGA 1329

CANTIGA ES_FCBGA 1329

GM45@

GM45@

VSS

VSS

VSS NCTF

VSS NCTF

VSS SCB

VSS SCB

NC

NC

VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325

VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350

VSS_351
VSS_352
VSS_353
VSS_354

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16

VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5

NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42

AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4

BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1

U24
U28
U25
U29

AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17

BH48
BH1
A48
C1
A3

E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48

3

2

1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/10 2010/08/19

2010/09/10 2010/08/19

2010/09/10 2010/08/19

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Doc ument Number Rev

Size Doc ument Number Rev

Size Doc ument Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Cantiga(7/7)-GND

Cantiga(7/7)-GND

Cantiga(7/7)-GND

LA7012P

LA7012P

LA7012P

1

of

of

of

13 41Friday, December 24, 2010

13 41Friday, December 24, 2010

13 41Friday, December 24, 2010

1.0

1.0

1.0