COMPAL LA-6931P Schematics
A
www.bufanxiu.com
1 1
B
C
D
E
Compal Confidential
2 2
Schematics Document
Intel Huron River
Sandy Bridge with Couger Point core logic
3 3
4 4
A
B
2010-10-27
REV:1.0
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2009/08/25 2010/08/25
2009/08/25 2010/08/25
2009/08/25 2010/08/25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Cover Page
Cover Page
Cover Page
LA-6931P
LA-6931P
LA-6931P
E
1 58Wednesday, October 27, 2010
1 58Wednesday, October 27, 2010
1 58Wednesday, October 27, 2010
1.0
1.0
1.0
A
www.bufanxiu.com
B
C
D
E
Compal
Mode
Fil
e Name : LA-6931P
1 1
Confidential
l Name : P5LM0
ATI
Granville-Pro/Whistler-Pro
page
22,23,24,25,26,27,28
PEG
(DIS)
Fan Control
PCI
p
age 43
-E 2.0x16 5GT/s PER LANE100MHz
133MHz
Intel
Sandy Bridge (DIS)
Processor
Memo
ry BUS(DDRIII)
Dual Channel
1.5V DDRIII: 1066MT/S
1333MT/S
204pin DDRIII-SO-DIMM X4
BANK 0, 1, 2, 3
page 10,11
rPGA989
LVDS(DIS)
HDMI(DIS)
CRT(DIS)
LVDS Conn.
page 29
(UMA)
HDMI Conn.
2 2
page 31
CRT
page 30
CRT Conn.
page 30
PCI-Express x 8 (PCIE1/2 2.5/5GT/S)
port 5
CardReader
R5U232
page 37
port 4
USB3.0 conn x 1
NEC UPD720200F1
page 36
port 2 port 1
MINI Card x1
WLAN
page 38
LVDS
page 29
LAN(GbE)
RTL8111E
100MHz
2.7GT/s
LVDS(UMA)
CRT(UMA)
100MHz
page 33
37.5mm*37.5mm
page 4,5,6,7,8,9,10
Cougar Point-M
PCH
989pins
25mm*25mm
page 13,14,15,16,17
18,19,20,21
DMI x4FDI x8
USB conn x2
USB port 0,1
USB Port 2 (eSATA)
100MHz
1GB/s x4
USBx14
HD Audio
3.3V 48MHz
3.3V 24MHz
SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S)
SPI
port 0
SPI ROM x1
page 13
SATA HDD
Conn.
page 32
Bluetooth
CMOS Camera
Conn
USB port 10
page 42page 35 page 29
100MHz
port 1
SATA ODD
Conn.
page 32
USB port 3
port 4
eSATA
Conn.
page 35
TV Tuner
USB port 5
HDA Codec
ALC669X
page 41
Audio AMP
TPA6017
page 42
page 38
3 3
Sub-board
LS-6931P
RTC CKT.
page 13
Power On/Off CKT.
page 40
DC/DC Interface CKT.
4 4
page 44,45
Power Circuit DC/DC
page 46~55
A
Power/B
page 41
LS-6932P
ARCADE/B
page29
LS-6933P
FP/B
page 44
LS-6934P
USB/B
page 43
LS-6935P
TP/B
page 35
B
RJ45
page 33
Touch Pad
EC I/O Buffer
ENE KB930
page 34
page 39
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LPC BUS
33MHz
page 39
C
Int.KBD
page 40
BIOS ROM
page 40
Compal Secret Data
Compal Secret Data
2009/08/25 2010/08/25
2009/08/25 2010/08/25
2009/08/25 2010/08/25
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
E
Phone Jack x 3
+SubWoofer
page 42
2 58Wednesday, October 27, 2010
2 58Wednesday, October 27, 2010
2 58Wednesday, October 27, 2010
Int. Speaker
page 42
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Block Diagrams
Block Diagrams
Block Diagrams
LA-6931P
LA-6931P
LA-6931P
1.0
1.0
1.0
A
www.bufanxiu.com
Vol
tage Rails
Power Plane Description
VIN
B
+
T+ Battery power supply (12.6V) N/A N/A N/A
BAT
1 1
2 2
+CPU_CORE
+0.
75VS 0.75V switched power rail for DDR terminator
+1.05VS_VCCP
+1.5V ON ON OFF
+1.5VS
+1.8VS 1.8V switched power rail
+3VALW 3.3V always on power rail
+3VALW_PCH
+LAN_IO
+3VS
+5VALW
+5VS
+VSB VSB always on power rail ON ON*
+RTCVCC RTC power
+VGA_CORE
+1.5VSDGPU
+1.8VSDGPU
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
1.05V switched power rail for CPU (PCH)
Core voltage for IGPU+VGFX_CORE
1.5V power rail for DDRIII
1.5V switched power rail
3.3V power rail for PCH
3.3V power rail for LAN
3.3V switched power rail
5V always on power rail
5V switched power rail
5V power rail for GPU
1.5V power rail for VRAM
1.8V switched power rail for GPU
External PCI Devices
Device IDSEL#
EC SM Bus1 address
Device
Address Address
REQ#/GNT#
EC SM Bus2 address
Device
B
S1S
3 S5
N/A N/A N/A
ON
ON OFF
ON OFF
ON OFF OFF
ON OFF OFF
ON
ON
ON ON
ON ON
ON
ON
ON
ON
Interrupts
N/AN/AN/A
O
OFF
OFF
OFF
OFF
OFF
ON ON*
ON*
ON*
OFF
OFF
ON ON*
OFF
OFFON
ONON
OFFON OFF
OFFON OFF
OFFON OFF
FF
DGPU
(DIS)
ON
ONONOFF
IGP
(SG)
OFF
ON
C
TE
U
STA
Full ON
S1(Power On Suspend)
S3
(Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SIGNAL
LOW
SLP
HIGH
SLP_S1# SLP_S3#
HIGH HIGH HIGH HIGH
LOW
LOW
LOW LOW LOW LOW
_S4#
LOWLOWLOW
SLP
D
_S5#
HIGHHIGHHIGH
HIGH
HIGH
+VA
E
V
LW
+
+VS Clo
N
ON
ON
ON
OFF
OFF
ON ON
ON
OFF
OFF
OFF
O
O
N
N
O
ON
ON
ck
LOW
OFF
OFF
OFF
Board ID / SKU ID Table for AD channel
Vcc 3.3V +/- 5%
Board ID
0
1
2
3
4
5
6
7 NC
BOARD ID Table
Board ID
*
100K +/- 5%Ra/Rc/Re
Rb / Rd / Rf V min
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
PCB Revision
0
0.1
1
2
3
0.4
4
5
6
7
AD_BID
0 V
V typ
AD_BID
0 V 0 V
V
AD_BID
max
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
0.503 V
0.819 V
0.538 V
0.875 V
1.185 V 1.264 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
2.200 V
3.300 V
2.341 V
3.300 V
BTO Option Table
BTO Item BOM Structure
Switchable
Graphics
Granville GRA@
Whistler WHI@
DDR M1
DDR M3
DIS@DIS Only
SG@
CIR@For CIR
USB2@USB2.0 bus
M1@
M3@
45@For 45 level
USB Port Table
0
1
2
3
4
5
6
7
8
9
10
11
12
13
4 External
USB Port
USB/B
USB Conn.
Mini Card 1
Mini Card 2
USB Conn.
eSATA USB
CMOS Camera
Finger Print
USB3.0 @
Blue Tooth
43 Level BOM Config
Granville DIS:
Whistler SG:
45 Level BOM Config
45@
DIS@GRA@ CIR@ M1@
WHI@ SG@ CIR@ M1@
VRAM BOM Config
X76255BOL01:
X76255BOL02
X76255BOL04
HYNIX 1G (old die)
HYNIX 1G (new die)
HYNIX 2G
3 3
Ibex SM Bus address
Device Address
USB 2.0 USB 1.1 Port
UHCI0
UHCI1
EHCI1
UHCI2
UHCI3
UHCI4
EHCI2
4 4
UHCI5
UHCI6
A
B
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2009/08/25 2010/08/25
2009/08/25 2010/08/25
2009/08/25 2010/08/25
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Notes List
Notes List
Notes List
LA-6931P
LA-6931P
LA-6931P
E
3 58Wednesday, October 27, 2010
3 58Wednesday, October 27, 2010
3 58Wednesday, October 27, 2010
1.0
1.0
1.0
5
www.bufanxiu.com
4
3
2
1
D D
JCPU1A
JCPU1A
EDP_COMP
B27
DMI_RX#[0]
B25
DMI_RX#[1]
A25
DMI_RX#[2]
B24
DMI_RX#[3]
B28
DMI_RX[0]
B26
DMI_RX[1]
A24
DMI_RX[2]
B23
DMI_RX[3]
G21
DMI_TX#[0]
E22
DMI_TX#[1]
F21
DMI_TX#[2]
D21
DMI_TX#[3]
G22
DMI_TX[0]
D22
DMI_TX[1]
F20
DMI_TX[2]
C21
DMI_TX[3]
A21
FDI0_TX#[0]
H19
FDI0_TX#[1]
E19
FDI0_TX#[2]
F18
FDI0_TX#[3]
B21
FDI1_TX#[0]
C20
FDI1_TX#[1]
D18
FDI1_TX#[2]
E17
FDI1_TX#[3]
A22
FDI0_TX[0]
G19
FDI0_TX[1]
E20
FDI0_TX[2]
G18
FDI0_TX[3]
B20
FDI1_TX[0]
C19
FDI1_TX[1]
D19
FDI1_TX[2]
F17
FDI1_TX[3]
J18
FDI0_FSYNC
J17
FDI1_FSYNC
H20
FDI_INT
J19
FDI0_LSYNC
H17
FDI1_LSYNC
A18
eDP_COMPIO
A17
eDP_ICOMPO
B16
eDP_HPD
C15
eDP_AUX
D15
eDP_AUX#
C17
eDP_TX[0]
F16
eDP_TX[1]
C16
eDP_TX[2]
G15
eDP_TX[3]
C18
eDP_TX#[0]
E16
eDP_TX#[1]
D16
eDP_TX#[2]
F15
eDP_TX#[3]
Sandy Bridge_rPGA_Rev1p0
Sandy Bridge_rPGA_Rev1p0
CONN@
CONN@
DMI
DMI
Intel(R) FDI
Intel(R) FDI
eDP
eDP
DMI_CRX_PTX_N0<15>
DMI_CRX_PTX_N1<15>
DMI_CRX_PTX_N2<15>
DMI_CRX_PTX_N3<15>
DMI_CRX_PTX_P0<15>
DMI_CRX_PTX_P1<15>
DMI_CRX_PTX_P2<15>
DMI_CRX_PTX_P3<15>
DMI_CTX_PRX_N0<15>
DMI_CTX_PRX_N1<15>
DMI_CTX_PRX_N2<15>
DMI_CTX_PRX_N3<15>
DMI_CTX_PRX_P0<15>
DMI_CTX_PRX_P1<15>
DMI_CTX_PRX_P2<15>
DMI_CTX_PRX_P3<15>
C C
FDI_CTX_PRX_N0<15>
FDI_CTX_PRX_N1<15>
FDI_CTX_PRX_N2<15>
FDI_CTX_PRX_N3<15>
FDI_CTX_PRX_N4<15>
FDI_CTX_PRX_N5<15>
FDI_CTX_PRX_N6<15>
FDI_CTX_PRX_N7<15>
FDI_CTX_PRX_P0<15>
FDI_CTX_PRX_P1<15>
FDI_CTX_PRX_P2<15>
FDI_CTX_PRX_P3<15>
FDI_CTX_PRX_P4<15>
FDI_CTX_PRX_P5<15>
FDI_CTX_PRX_P6<15>
+1.05VS_VCCP
12
R296
R296
24.9_0402_1%
24.9_0402_1%
B B
eDP_COMPIO and ICOMPO signals
should be shorted near balls
and routed with typical
impedance <25 mohms
FDI_CTX_PRX_P7<15>
FDI_FSYNC0<15>
FDI_FSYNC1<15>
FDI_INT<15>
FDI_LSYNC0<15>
FDI_LSYNC1<15>
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PCI EXPRESS* - GRAPHICS
PCI EXPRESS* - GRAPHICS
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
PEG_COMP
J22
J21
H22
PEG_HRX_GTX_N15
K33
PEG_HRX_GTX_N14
M35
PEG_HRX_GTX_N13
L34
PEG_HRX_GTX_N12
J35
PEG_HRX_GTX_N11
J32
PEG_HRX_GTX_N10
H34
PEG_HRX_GTX_N9
H31
PEG_HRX_GTX_N8
G33
PEG_HRX_GTX_N7
G30
PEG_HRX_GTX_N6
F35
PEG_HRX_GTX_N5
E34
PEG_HRX_GTX_N4
E32
PEG_HRX_GTX_N3
D33
PEG_HRX_GTX_N2
D31
PEG_HRX_GTX_N1
B33
PEG_HRX_GTX_N0
C32
PEG_HRX_GTX_P15
J33
PEG_HRX_GTX_P14
L35
PEG_HRX_GTX_P13
K34
PEG_HRX_GTX_P12
H35
PEG_HRX_GTX_P11
H32
PEG_HRX_GTX_P10
G34
PEG_HRX_GTX_P9
G31
PEG_HRX_GTX_P8
F33
PEG_HRX_GTX_P7
F30
PEG_HRX_GTX_P6
E35
PEG_HRX_GTX_P5
E33
PEG_HRX_GTX_P4
F32
PEG_HRX_GTX_P3
D34
PEG_HRX_GTX_P2
E31
PEG_HRX_GTX_P1
C33
PEG_HRX_GTX_P0
B32
PEG_HTX_GRX_N15 PEG_HTX_C_GRX_N15
M29
PEG_HTX_GRX_N14 PEG_HTX_C_GRX_N14
M32
PEG_HTX_GRX_N13 PEG_HTX_C_GRX_N13
M31
PEG_HTX_GRX_N12 PEG_HTX_C_GRX_N12
L32
PEG_HTX_GRX_N11 PEG_HTX_C_GRX_N11
L29
PEG_HTX_GRX_N10 PEG_HTX_C_GRX_N10
K31
PEG_HTX_GRX_N9 PEG_HTX_C_GRX_N9
K28
PEG_HTX_GRX_N8 PEG_HTX_C_GRX_N8
J30
PEG_HTX_GRX_N7 PEG_HTX_C_GRX_N7
J28
PEG_HTX_GRX_N6 PEG_HTX_C_GRX_N6
H29
PEG_HTX_GRX_N5 PEG_HTX_C_GRX_N5
G27
PEG_HTX_GRX_N4 PEG_HTX_C_GRX_N4
E29
PEG_HTX_GRX_N3 PEG_HTX_C_GRX_N3
F27
PEG_HTX_GRX_N2 PEG_HTX_C_GRX_N2
D28
PEG_HTX_GRX_N1 PEG_HTX_C_GRX_N1
F26
PEG_HTX_GRX_N0 PEG_HTX_C_GRX_N0
E25
PEG_HTX_GRX_P15 PEG_HTX_C_GRX_P15
M28
PEG_HTX_GRX_P14 PEG_HTX_C_GRX_P14
M33
PEG_HTX_GRX_P13 PEG_HTX_C_GRX_P13
M30
PEG_HTX_GRX_P12 PEG_HTX_C_GRX_P12
L31
PEG_HTX_GRX_P11 PEG_HTX_C_GRX_P11
L28
PEG_HTX_GRX_P10 PEG_HTX_C_GRX_P10
K30
PEG_HTX_GRX_P9 PEG_HTX_C_GRX_P9
K27
PEG_HTX_GRX_P8 PEG_HTX_C_GRX_P8
J29
PEG_HTX_GRX_P7 PEG_HTX_C_GRX_P7
J27
PEG_HTX_GRX_P6 PEG_HTX_C_GRX_P6
H28
PEG_HTX_GRX_P5 PEG_HTX_C_GRX_P5
G28
PEG_HTX_GRX_P4 PEG_HTX_C_GRX_P4
E28
PEG_HTX_GRX_P3 PEG_HTX_C_GRX_P3
F28
PEG_HTX_GRX_P2 PEG_HTX_C_GRX_P2
D27
PEG_HTX_GRX_P1 PEG_HTX_C_GRX_P1
E26
PEG_HTX_GRX_P0 PEG_HTX_C_GRX_P0
D25
Typ- suggest 220nF. The change in AC capacitor
value from 100nF to 220nF is to enable
compatibility with future platforms having PCIE
Gen3 (8GT/s)
+1.05VS_VCCP
12
R1
R1
24.9_0402_1%
24.9_0402_1%
C1 0.22U_0402_10V6KC1 0.22U_0402_10V6K
1 2
C2 0.22U_0402_10V6KC2 0.22U_0402_10V6K
1 2
C3 0.22U_0402_10V6KC3 0.22U_0402_10V6K
1 2
C4 0.22U_0402_10V6KC4 0.22U_0402_10V6K
1 2
C5 0.22U_0402_10V6KC5 0.22U_0402_10V6K
1 2
C6 0.22U_0402_10V6KC6 0.22U_0402_10V6K
1 2
C7 0.22U_0402_10V6KC7 0.22U_0402_10V6K
1 2
C8 0.22U_0402_10V6KC8 0.22U_0402_10V6K
1 2
C9 0.22U_0402_10V6KC9 0.22U_0402_10V6K
1 2
C10 0.22U_0402_10V6KC10 0.22U_0402_10V6K
1 2
C11 0.22U_0402_10V6KC11 0.22U_0402_10V6K
1 2
C12 0.22U_0402_10V6KC12 0.22U_0402_10V6K
1 2
C13 0.22U_0402_10V6KC13 0.22U_0402_10V6K
1 2
C14 0.22U_0402_10V6KC14 0.22U_0402_10V6K
1 2
C15 0.22U_0402_10V6KC15 0.22U_0402_10V6K
1 2
C16 0.22U_0402_10V6KC16 0.22U_0402_10V6K
1 2
C17 0.22U_0402_10V6KC17 0.22U_0402_10V6K
1 2
C18 0.22U_0402_10V6KC18 0.22U_0402_10V6K
1 2
C19 0.22U_0402_10V6KC19 0.22U_0402_10V6K
1 2
C20 0.22U_0402_10V6KC20 0.22U_0402_10V6K
1 2
C21 0.22U_0402_10V6KC21 0.22U_0402_10V6K
1 2
C22 0.22U_0402_10V6KC22 0.22U_0402_10V6K
1 2
C23 0.22U_0402_10V6KC23 0.22U_0402_10V6K
1 2
C24 0.22U_0402_10V6KC24 0.22U_0402_10V6K
1 2
C25 0.22U_0402_10V6KC25 0.22U_0402_10V6K
1 2
C26 0.22U_0402_10V6KC26 0.22U_0402_10V6K
1 2
C27 0.22U_0402_10V6KC27 0.22U_0402_10V6K
1 2
C28 0.22U_0402_10V6KC28 0.22U_0402_10V6K
1 2
C29 0.22U_0402_10V6KC29 0.22U_0402_10V6K
1 2
C30 0.22U_0402_10V6KC30 0.22U_0402_10V6K
1 2
C31 0.22U_0402_10V6KC31 0.22U_0402_10V6K
1 2
C32 0.22U_0402_10V6KC32 0.22U_0402_10V6K
1 2
PEG_HRX_GTX_N[0..15] <22>
PEG_HRX_GTX_P[0..15] <22>
PEG_HTX_C_GRX_N[0..15] <22>
PEG_HTX_C_GRX_P[0..15] <22>
A A
Security Classification
Security Classification
5
4
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/12/01 2010/12/31
2009/12/01 2010/12/31
2009/12/01 2010/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet
Compal Electronics, Inc.
PROCESSOR(1/7) DMI,FDI,PEG
PROCESSOR(1/7) DMI,FDI,PEG
PROCESSOR(1/7) DMI,FDI,PEG
LA-6931P
LA-6931P
LA-6931P
1
of
4 58Wednesday, October 27, 2010
4 58Wednesday, October 27, 2010
4 58Wednesday, October 27, 2010
1.0
1.0
1.0
5
www.bufanxiu.com
4
JCPU1B
JCPU1B
3
2
1
CLK_CPU_DMI_R
A28
DPLL_REF_CLK
DPLL_REF_CLK#
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
MISC
MISC
BCLK
BCLK#
PRDY#
PREQ#
TRST#
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
C26
PROC_SELECT#
AN34
SKTOCC#
AL33
CATERR#
AN33
PECI
AL32
PROCHOT#
AN32
THERMTRIP#
AM34
PM_SYNC
AP33
UNCOREPWRGOOD
V8
SM_DRAMPWR OK
AR33
RESET#
Sandy Bridge_rPGA_Rev1p0
Sandy Bridge_rPGA_Rev1p0
CONN@
CONN@
MISCTHERMALPWR MANAGEMENT
MISCTHERMALPWR MANAGEMENT
CLOCKS
CLOCKS
DDR3
DDR3
JTAG & BPM
JTAG & BPM
H_PECI<18,40>
12
@
@
R19
R19
0_0402_5%
0_0402_5%
H_SNB_IVB#<17>
T1 PADT1 PAD
R7
R7
0_0402_5%
0_0402_5%
1 2
R9
R9
56_0402_5%
56_0402_5%
1 2
R10
R10
0_0402_5%
0_0402_5%
1 2
R11
R11
0_0402_5%
0_0402_5%
1 2
R15
R15
0_0402_5%
0_0402_5%
1 2
R18
R18
130_0402_5%
130_0402_5%
1 2
H_CATERR#
H_PECI_ISO
H_PROCHOT#_R
H_THEMTRIP#_R
H_PM_SYNC_R
H_CPUPWRGD_R
PM_DRAM_PWR GD_RPM _SYS_PWRGD_BUF
BUF_CPU_RST#
+1.05VS_VCCP
D D
C C
Bu
Processor Pullups
R6 62_0402_5%R6 62_0402_5%
R8 10K_0402_5%R8 10K_0402_5%
C916 220P_0402_50V7KC916 220P_0402_50V7K
12
12
12
10/11
For ESD
ffered reset to CPU
PLT_RST#<17,34,37,39,40>
PLT_RST#
H_PROCHOT# CLK_DP_R
H_CPUPWRGD_R
H_PROCHOT#<40,50>
H_THRMTRIP#<18>
H_PM_SYNC<15>
H_CPUPWRGD<18>
+3VS
+1.05VS_VCCP
12
R13
R13
75_0402_5%
75_0402_5%
R17
R17
43_0402_1%
43_0402_1%
1 2
5
1
P
NC
2
A
G
3
1
C35
C35
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
U1
U1
BUFO_CPU_RST# BUF_CPU_RST#
4
Y
SN74LVC1G07DCKR_SC70-5
SN74LVC1G07DCKR_SC70-5
TCK
TMS
TDO
TDI
A27
A16
A15
R8
AK1
A5
A4
AP29
AP27
AR26
AR27
AP30
AR28
AP26
AL35
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
CLK_CPU_DMII#_R
CLK_DP#_R
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
XDP_PRDY#
XDP_PREQ#
XDP_TCK
XDP_TMS
XDP_TRST#
XDP_TDO
XDP_DBRESET#
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7
R2 0_0402_5%R2 0_0402_5%
1 2
R3 0_0402_5%R3 0_0402_5%
1 2
R4 0_0402_5%R4 0_0402_5%
1 2
R5 0_0402_5%R5 0_0402_5%
1 2
H_DRAMRST# <6>
T31PAD T31PAD
T32PAD T32PAD
T33PAD T33PAD
T38PAD T38PAD
R902 51_0402_5%R902 51_0402_5%
R25 51_0402_5%R25 51_0402_5%
12
T39PAD T39PAD
12
XDP_DBRESET# <15>
T40PAD T40PAD
T42PAD T42PAD
T44PAD T44PAD
T46PAD T46PAD
T47PAD T47PAD
T48PAD T48PAD
T49PAD T49PAD
T50PAD T50PAD
PM_DRAM_PWR GD<15>
+1.05VS_VCCP
+3VS
CLK_CPU_DMI <14>
CLK_CPU_DMI# <14>
CLK_DP <14>
CLK_DP# <14>
C36
C36
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R29
R29
10K_0402_5%
10K_0402_5%
1 2
+3VALW
1
2
5
1
B
2
A
3
SUSP<45,53>
U3
U3
74AHC1G09GW_TSSOP5
74AHC1G09GW_TSSOP5
P
PM_SYS_PWRGD_BUF
4
O
G
SUSP
2
G
G
+1.5V_CPU_VDDQ
12
@
@
R30
R30
39_0402_5%
39_0402_5%
13
D
D
@
@
Q1
Q1
2N7002H_SOT23-3
2N7002H_SOT23-3
S
S
12
R26
R26
200_0402_5%
200_0402_5%
B B
DDR3 Compe nsation Si gnals
SM_RCOMP0
R20 14 0_0402_1%R20 14 0_0402_1%
SM_RCOMP1
R21 25 .5_0402_1%R21 25 .5_0402_1%
SM_RCOMP2
R22 20 0_0402_1%R22 20 0_0402_1%
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
10/18 Remove XDP Connector
Compal Secret Data
Compal Secret Data
2009/12/01 2010/12/31
2009/12/01 2010/12/31
2009/12/01 2010/12/31
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet
XDP_DBRESET#
R31 1K_0402_5%R31 1K_0402_5%
Compal Electronics, Inc.
PROCESSOR(2/7) PM,XDP,CLK
PROCESSOR(2/7) PM,XDP,CLK
PROCESSOR(2/7) PM,XDP,CLK
LA-6931P
LA-6931P
LA-6931P
12
12
12
+3VS
12
1.0
1.0
1.0
of
5 58Wednesday, October 27, 2010
5 58Wednesday, October 27, 2010
1
5 58Wednesday, October 27, 2010
5
www.bufanxiu.com
JCPU1C
JCPU1C
4
3
JCPU1D
JCPU1D
2
1
DDR_A_D[0..63]<11>
D D
C C
B B
DDR_A_BS0<11>
DDR_A_BS1<11>
DDR_A_BS2<11>
DDR_A_CAS#<11>
DDR_A_RAS#<11>
DDR_A_WE#<11>
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
G10
N10
M10
AG6
AG5
AK6
AK5
AH5
AH6
AK8
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
AE10
AF10
AE8
AD9
AF9
F10
AJ5
AJ6
AJ8
AJ9
C5
D5
D3
D2
D6
C6
C2
C3
F8
G9
F9
F7
G8
G7
K4
K5
K1
K2
M8
N8
N7
M9
N9
M7
V6
J1
J5
J4
J2
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
RSVD_TP[10]
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]
SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]
RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]
RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]
SA_CS#[0]
SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]
SA_ODT[0]
SA_ODT[1]
RSVD_TP[9]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AB6
AA6
V9
AA5
AB5
V10
AB4
AA4
W9
AB3
AA3
W10
AK3
AL3
AG1
AH1
AH3
AG3
AG2
AH2
C4
G6
J3
M6
AL6
AM8
AR12
AM15
D4
F6
K3
N6
AL5
AM9
AR11
AM14
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDR_A_CLK0 <11>
DDR_A_CLK0# <11>
DDR_A_CKE0 <11>
DDR_A_CLK1 <11>
DDR_A_CLK1# <11>
DDR_A_CKE1 <11>
DDR_A_CLK2 <11>
DDR_A_CLK2# <11>
DDR_A_CKE2 <11>
DDR_A_CLK3 <11>
DDR_A_CLK3# <11>
DDR_A_CKE3 <11>
DDR_A_CS0# <11>
DDR_A_CS1# <11>
DDR_A_CS2# <11>
DDR_A_CS3# <11>
DDR_A_ODT0 <11>
DDR_A_ODT1 <11>
DDR_A_ODT2 <11>
DDR_A_ODT3 <11>
DDR_A_DQS#[0..7] <11>
DDR_A_DQS[0..7] <11>
DDR_A_MA[0..15] <11> DDR_B_MA[0..15] <12>
DDR_B_D[0..63]<12>
DDR_B_BS0<12>
DDR_B_BS1<12>
DDR_B_BS2<12>
DDR_B_CAS#<12>
DDR_B_RAS#<12>
DDR_B_WE#<12>
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
D10
K10
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA9
AA7
AA10
AB8
AB9
C9
A7
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
K9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
R6
J7
J8
J9
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]
RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]
RSVD_TP[17]
RSVD_TP[18]
RSVD_TP[19]
RSVD_TP[20]
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_CLK[0]
SB_CLK#[0]
SB_CKE[0]
SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]
SB_CS#[0]
SB_CS#[1]
SB_ODT[0]
SB_ODT[1]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
AE2
AD2
R9
AE1
AD1
R10
AB2
AA2
T9
AA1
AB1
T10
AD3
AE3
AD6
AE6
AE4
AD4
AD5
AE5
D7
F3
K6
N3
AN5
AP9
AK12
AP15
C7
G3
J6
M3
AN6
AP8
AK11
AP14
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
DDR_B_CLK0 <12>
DDR_B_CLK0# <12>
DDR_B_CKE0 <12>
DDR_B_CLK1 <12>
DDR_B_CLK1# <12>
DDR_B_CKE1 <12>
DDR_B_CLK2 <12>
DDR_B_CLK2# <12>
DDR_B_CKE2 <12>
DDR_B_CLK3 <12>
DDR_B_CLK3# <12>
DDR_B_CKE3 <12>
DDR_B_CS0# <12>
DDR_B_CS1# <12>
DDR_B_CS2# <12>
DDR_B_CS3# <12>
DDR_B_ODT0 <12>
DDR_B_ODT1 <12>
DDR_B_ODT2 <12>
DDR_B_ODT3 <12>
DDR_B_DQS#[0..7] <12>
DDR_B_DQS[0..7] <12>
Sandy Bridge_rPGA_Rev1p0
Deciphered Date
Deciphered Date
Deciphered Date
Sandy Bridge_rPGA_Rev1p0
CONN@
CONN@
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(3/7) DDRIII
PROCESSOR(3/7) DDRIII
PROCESSOR(3/7) DDRIII
LA-6931P
LA-6931P
LA-6931P
1
6 58Wednesday, October 27, 2010
6 58Wednesday, October 27, 2010
6 58Wednesday, October 27, 2010
1.0
1.0
1.0
Sandy Bridge_rPGA_Rev1p0
Sandy Bridge_rPGA_Rev1p0
CONN@
CONN@
R839
@R839
@
0_0402_5%
0_0402_5%
1 2
D
S
D
S
DDR3_DRAMRST#_R
1 2
13
Q2
Q2
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
G
G
2
1
C37
C37
0.047U_0402_16V4Z
0.047U_0402_16V4Z
2
H_DRAMRST#<5>
R35
R35
4.99K_0402_1%
4.99K_0402_1%
A A
DRAMRST_CNTRL_PC H<7,14>
5
R36
R36
0_0402_5%
0_0402_5%
1 2
DRAMRST_CNTRL
+1.5V
R33
R33
1K_0402_5%
1K_0402_5%
12
1 2
R34
R34
1K_0402_5%
1K_0402_5%
4
DDR3_DRAMRST# <11,12>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/12/01 2010/12/31
2009/12/01 2010/12/31
2009/12/01 2010/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
5
www.bufanxiu.com
4
3
2
1
CFG Straps for Processor
CFG2
D D
JCPU1E
JCPU1E
L7
RSVD28
AG7
T2 PADT2 PAD
T3 PADT3 PAD
T4 PADT4 PAD
T5 PADT5 PAD
T6 PADT6 PAD
T7 PADT7 PAD
T8 PADT8 PAD
T9 PADT9 PAD
T10 PADT10 PAD
T11 PADT11 PAD
T12 PADT12 PAD
T13 PADT13 PAD
T51 PADT51 PAD
T52 PADT52 PAD
T54 PADT54 PAD
T58 PADT58 PAD
T61 PADT61 PAD
T64 PADT64 PAD
C C
R322 49.9_0402_1%R322 49.9_0402_1%
+VGFX_CORE
+CPU_CORE
R915 0_0402_5%@R915 0_0402_5%@
1 2
M3@
M3@
Q22 AP2302GN_SOT23-3
R916 0_0402_5%@R916 0_0402_5%@
9/06
Q22 AP2302GN_SOT23-3
D
S
D
S
1 3
G
G
2
DRAMRST_CNTRL_PC H
1 2
M3@
M3@
Q23 AP2302GN_SOT23-3
Q23 AP2302GN_SOT23-3
D
S
D
S
1 3
G
G
2
+V_DDR_M3_REFA
B B
+V_DDR_M3_REFB
1 2
R323 49.9_0402_1%R323 49.9_0402_1%
R320 49.9_0402_1%R320 49.9_0402_1%
R321 49.9_0402_1%R321 49.9_0402_1%
DRAMRST_CNTRL_PC H <6,14>
1 2
CPU_RSVD6
CPU_RSVD7
12
12
1K_0402_1%
1K_0402_1%
R41
R41
M1@
M1@
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE
CPU_RSVD6
CPU_RSVD7
12
12
R42
R42
1K_0402_1%
1K_0402_1%
M1@
M1@
AK28
CFG[0]
AK29
CFG[1]
AL26
CFG[2]
AL27
CFG[3]
AK26
CFG[4]
AL29
CFG[5]
AL30
CFG[6]
AM31
CFG[7]
AM32
CFG[8]
AM30
CFG[9]
AM28
CFG[10]
AM26
CFG[11]
AN28
CFG[12]
AN31
CFG[13]
AN26
CFG[14]
AM27
CFG[15]
AK31
CFG[16]
AN29
CFG[17]
AJ31
VAXG_VAL_SENSE
AH31
VSSAXG_VAL_SENSE
AJ33
VCC_VAL_SENSE
AH33
VSS_VAL_SENSE
AJ26
RSVD5
B4
RSVD6
D1
RSVD7
F25
RSVD8
F24
RSVD9
F23
RSVD10
D24
RSVD11
G25
RSVD12
G24
RSVD13
E23
RSVD14
D23
RSVD15
C30
RSVD16
A31
RSVD17
B30
RSVD18
B29
RSVD19
D30
RSVD20
B31
RSVD21
A30
RSVD22
C29
RSVD23
J20
RSVD24
B18
RSVD25
A19
VCCIO_SEL
J15
RSVD27
Sandy Bridge_rPGA_Rev1p0
Sandy Bridge_rPGA_Rev1p0
CONN@
CONN@
RESERVED
RESERVED
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
VCC_DIE_SENSE
RSVD54
RSVD55
RSVD56
RSVD57
RSVD58
KEY
AE7
AK2
W8
AT26
AM33
AJ27
T8
J16
H16
G16
AR35
AT34
AT33
AP35
AR34
B34
A33
A34
B35
C35
AJ32
AK32
AH27
AN35
AM35
AT2
AT1
AR1
B1
T14PAD T14PAD
CLK_RES_ITP <14 >
CLK_RES_ITP# <1 4>
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
*
Display Port Presence Strap
CFG4
*
PCIE Port Bifurcation Straps
11: (Default) x16 - Device 1 functions 1 and 2 disabled
*
CFG[6:5]
10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
01: Reserved - (Device 1 function 1 disabled ; function
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
12
R37
R37
1K_0402_1%
1K_0402_1%
1: Normal Operation; Lane # definition matches
socket pin map definition
0:Lane Reversed
CFG4
1K_0402_1%
1K_0402_1%
12
@
@
R38
R38
1K_0402_1%
1K_0402_1%
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
CFG6
CFG5
@R39
@
12
12
R40
@R40
R39
@
1K_0402_1%
1K_0402_1%
2 enabled)
CFG7
12
@R43
@
R43
1K_0402_1%
1K_0402_1%
PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB
CFG7
de assertion
A A
Security Classification
Security Classification
5
4
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/12/01 2010/12/31
2009/12/01 2010/12/31
2009/12/01 2010/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
0: PEG Wait for BIOS for training
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(4/7) RSVD,CFG
PROCESSOR(4/7) RSVD,CFG
PROCESSOR(4/7) RSVD,CFG
LA-6931P
LA-6931P
LA-6931P
1
7 58Wednesday, October 27, 2010
7 58Wednesday, October 27, 2010
7 58Wednesday, October 27, 2010
1.0
1.0
1.0
5
www.bufanxiu.com
+CPU_CORE
Bottom Socket Cavity
C38
10U_0805_6.3V6M
C38
10U_0805_6.3V6M
1
D D
+CPU_CORE
2
C788
10U_0805_6.3V6M
C788
10U_0805_6.3V6M
1
2
C39
10U_0805_6.3V6M
C39
10U_0805_6.3V6M
1
2
C789
10U_0805_6.3V6M
C789
10U_0805_6.3V6M
1
2
Top Socket Cavity
C799
22U_0805_6.3V6M
C799
22U_0805_6.3V6M
1
2
C C
+CPU_CORE
22U_0805_6.3V6M
22U_0805_6.3V6M
1
2
C800
22U_0805_6.3V6M
C800
22U_0805_6.3V6M
1
1
2
2
Top Socket Edge
C74
22U_0805_6.3V6M
C74
22U_0805_6.3V6M
C73
C73
1
1
2
2
C801
22U_0805_6.3V6M
C801
22U_0805_6.3V6M
C805
22U_0805_6.3V6M
C805
22U_0805_6.3V6M
Bottom Socket Edge
C812
330U_D2_2.5VY_R9M+C812
330U_D2_2.5VY_R9M
C811
330U_D2_2.5VY_R9M+C811
330U_D2_2.5VY_R9M
1
1
+
+
2
2
B B
A A
4
SV type CPU
C40
10U_0805_6.3V6M
C40
10U_0805_6.3V6M
10U_0805_6.3V6M
1
2
1
2
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
1
+
+
2
10U_0805_6.3V6M
1
2
C790
10U_0805_6.3V6M
C790
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
1
2
C68
22U_0805_6.3V6M
C68
22U_0805_6.3V6M
1
1
2
2
C806
22U_0805_6.3V6M
C806
22U_0805_6.3V6M
1
1
2
2
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
1
C813
C813
C814
C814
+
+
2
C42
10U_0805_6.3V6M
C42
10U_0805_6.3V6M
C41
C41
1
2
C791
C791
C792
10U_0805_6.3V6M
C792
10U_0805_6.3V6M
1
2
C803
22U_0805_6.3V6M
C803
22U_0805_6.3V6M
C802
22U_0805_6.3V6M
C802
22U_0805_6.3V6M
C907
22U_0805_6.3V6M
C907
22U_0805_6.3V6M
C807
22U_0805_6.3V6M
C807
22U_0805_6.3V6M
1
1
2
2
C808
22U_0805_6.3V6M
C808
22U_0805_6.3V6M
1
1
2
2
C804
22U_0805_6.3V6M
C804
22U_0805_6.3V6M
1
2
22U_0805_6.3V6M
22U_0805_6.3V6M
C809
22U_0805_6.3V6M
C809
22U_0805_6.3V6M
1
2
09/10
53A
C810
C810
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
3
POWER
JCPU1F
JCPU1F
POWER
18A
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
Y29
VCC57
Y28
VCC58
Y27
VCC59
Y26
VCC60
V35
VCC61
V34
VCC62
V33
VCC63
V32
VCC64
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
V26
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32
VCC84
R31
VCC85
R30
VCC86
R29
VCC87
R28
VCC88
R27
VCC89
R26
VCC90
P35
VCC91
P34
VCC92
P33
VCC93
P32
VCC94
P31
VCC95
P30
VCC96
P29
VCC97
P28
VCC98
P27
VCC99
P26
VCC100
CORE SUPPLY
CORE SUPPLY
PEG AND DDR
PEG AND DDR
VCC_SENSE
VSS_SENSE
VCCIO_SENSE
VSSIO_SENSE
SENSE LINES SVID
SENSE LINES SVID
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
VCCIO40
VIDALERT#
VIDSCLK
VIDSOUT
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
J23
AJ29
AJ30
AJ28
AJ35
AJ34
B10
A10
VCCSENSE_R
VSSSENSE_R
2
+1.05VS_VCCP
1
2
1
2
1
2
1
2
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
VCCIO_SENSE
VSSIO_SENSE
22U_0805_6.3V6M
C43
C43
22U_0805_6.3V6M
22U_0805_6.3V6M
@
@
C48
C48
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
C44
C44
C785
C785
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
2
@
@
@
@
C50
C50
C49
C49
2
MB Bottom Socket Cavity
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
MB Top Socket Cavity
22U_0805_6.3V6M
22U_0805_6.3V6M
C795
C795
22U_0805_6.3V6M
22U_0805_6.3V6M
C910
C910
R50 0_0402_5%R50 0_0402_5%
1 2
R51 0_0402_5%R51 0_0402_5%
1 2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
2
1
2
12
@
@
C797
C797
C796
C796
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C904
C904
C209
C209
2
R44
R44
130_0402_5%
130_0402_5%
R46
R46
43_0402_1%
43_0402_1%
1 2
R842 0_0402_5%R842 0_0402_5%
1 2
R843 0_0402_5%R843 0_0402_5%
1 2
VCCIO_SENSE <53>
VSSIO_SENSE <53>
22U_0805_6.3V6M
22U_0805_6.3V6M
1
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
@
@
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
@
@
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
2
+1.05VS_VCCP+1.05VS_VCCP
+CPU_CORE
C786
C786
C51
C51
C798
C798
C211
C211
12
R903
R903
75_0402_5%
75_0402_5%
12
12
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C47
C47
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
@
@
C787
C787
2
330U_D2_2V_Y
330U_D2_2V_Y
1
C793
C793
+
+
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C212
C212
2
R844
R844
100_0402_1%
100_0402_1%
R52
R52
100_0402_1%
100_0402_1%
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
1
1
C794
C794
+
+
+
+
2
C906
C906
2
@
@
Place the PU
re
Place the PU
res
istors clo se to CPU
VCCSENSE <56>
VSSSENSE <56>
1
+1.05VS_VCCP
VR_SVID_ALRT# <56>
VR_SVID_CLK <56>
VR_SVID_DAT <56>
sistors cl ose to VR
5
4
Sandy Bridge_rPGA_Rev1p0
Sandy Bridge_rPGA_Rev1p0
CONN@
CONN@
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/12/01 2010/12/31
2009/12/01 2010/12/31
2009/12/01 2010/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(5/7) PWR,BYPASS
PROCESSOR(5/7) PWR,BYPASS
PROCESSOR(5/7) PWR,BYPASS
LA-6931P
LA-6931P
LA-6931P
1
8 58Wednesday, October 27, 2010
8 58Wednesday, October 27, 2010
8 58Wednesday, October 27, 2010
1.0
1.0
1.0
5
www.bufanxiu.com
4
3
2
1
+1.5V_CPU_VDDQ Source
+1.5V +1.5V_CPU_VDDQ
+VSB
+3VALW
12
@
@
R2302
R2302
100K_0402_5%
D D
R2304
@R2304
@
0_0402_5%
0_0402_5%
CPU1.5V_S3_GATE<40>
SUSP#<40,45,46,51,53>
+VGFX_CORE
1 2
R2305
@R2305
@
0_0402_5%
0_0402_5%
1 2
100K_0402_5%
RUN_ON_CPU1.5VS3#
34
@
@
Q2301B
Q2301B
DMN66D0LDW-7 2N_SOT363-6
DMN66D0LDW-7 2N_SOT363-6
5
Top Socket Cavity
R845
0_0402_5%
R845
0_0402_5%
DIS@
DIS@
C C
1 2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
SG@
SG@
SG@
SG@
1
1
2
C818
C818
C817
C817
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
SG@
SG@
SG@
SG@
1
1
2
C820
C820
C819
C819
2
Top Socket Edge
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
SG@
SG@
SG@
SG@
1
1
2
C822
C822
C821
C821
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
SG@
SG@
SG@
SG@
1
1
2
C824
C824
C823
C823
2
Bottom Socket Cavity
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
SG@
SG@
SG@
SG@
1
1
2
Bottom Socket Edge
1
B B
2
C826
C826
C825
C825
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
@
@
@
@
1
C828
C828
C829
C829
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
SG@
SG@
SG@
SG@
1
1
2
1
2
C101
C101
C100
C100
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
@
@
@
@
1
C113
C113
C830
C830
2
Bottom Socket Edge
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
1
1
SG@
SG@
@
Vaxg
Can connect to GND if motherboard only
‧‧‧‧
supports external graphics and if GFX VR is not
stuffed in a common motherboard design,
VAXG can be left floating in a common
‧‧‧‧
motherboard design (Gfx VR keeps VAXG from
floating) if the VR is stuffed
A A
+1.8VS
R66
R66
0_0805_5%
0_0805_5%
1 2
330U_D2_2V_Y+C908
330U_D2_2V_Y
1
+
2
+
+
2
+1.8VS_VCCPLL
C908
@
+
+
C103
C103
C104
C104
2
C836
10U_0805_6.3V6M
C836
10U_0805_6.3V6M
1
2
C837
1U_0402_6.3V6K
C837
1U_0402_6.3V6K
1
2
12
61
2
26A
C838
1U_0402_6.3V6K
C838
1U_0402_6.3V6K
1
2
@
@
R2300
R2300
100K_0402_5%
100K_0402_5%
RUN_ON_CPU1.5VS3
@
@
Q2301A
Q2301A
DMN66D0LDW-7 2N_SOT363-6
DMN66D0LDW-7 2N_SOT363-6
330K_0402_5%
330K_0402_5%
JCPU1G
JCPU1G
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
B6
A6
A2
Sandy Bridge_rPGA_Rev1p0
Sandy Bridge_rPGA_Rev1p0
CONN@
CONN@
@R2303
@
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54
VCCPLL1
VCCPLL2
VCCPLL3
R2303
Q2300
@Q2300
@
AO4728L_SO8
AO4728L_SO8
8
7
6
5
12
1
2
3
4
D
1
@
@
C2300
C2300
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
POWER
POWER
GRAPHICS
GRAPHICS
1.8V RAIL
1.8V RAIL
D
S
S
VSSAXG_SENSE
SENSE
LINES
SENSE
LINES
VREFMISC
VREFMISC
DDR3 -1.5V RAILS
DDR3 -1.5V RAILS
SA RAIL
SA RAIL
VCCSA_SENSE
@
@
R2301
R2301
220_0603_5%
220_0603_5%
1 2
8/31 Intel
13
2
G
G
Q2310
@
Q2310
@
2N7002H_SOT23-3
2N7002H_SOT23-3
VAXG_SENSE
SM_VREF
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
FC_C22
VCCSA_VID1
RUN_ON_CPU1.5VS3#
AK35
AK34
+V_SM_VREF should
have 20 mil trace width
+VREF_DDR_CPU
AL1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
5A
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
6A
M27
M26
L26
J26
J25
J24
H26
H25
H23
H_FC_C22
C22
C24
+1.5V_CPU_VDDQ +1.5V
C815 0.1U_0402_10V7KC815 0.1U_0402_10V7K
C816 0.1U_0402_10V7KC816 0.1U_0402_10V7K
C914 0.1U_0402_10V7KC914 0.1U_0402_10V7K
C915 0.1U_0402_10V7KC915 0.1U_0402_10V7K
8/31 Intel
VCC_AXG_SENSE <56>
VSS_AXG_SENSE <56>
R917 0_0402_5%R917 0_0402_5%
1
C909
C909
2
10U_0805_6.3V6M
1
2
1
2
R67
R67
10K_0402_5%
10K_0402_5%
1 2
10U_0805_6.3V6M
C105
C105
+VCCSA
10U_0805_6.3V6M
10U_0805_6.3V6M
C831
C831
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C106
C106
2
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C832
C832
2
12
1
2
1
2
R847
@R847
@
0_0402_5%
0_0402_5%
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
C107
C107
C833
C833
1
C108
C108
2
10U_0603_6.3V6M
10U_0603_6.3V6M
@
@
1
2
1
2
+VCCSA
C834
C834
VCCSA_SENSE <52>
VCCSA_SEL <52>
12
12
12
12
1 2
+1.5V_CPU_VDDQ
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C827
C827
2
R846 100_0402_5%R846 100_0402_5%
1
+
+
C835
C835
330U_D2_2V_Y
330U_D2_2V_Y
2
R65 0_0402_5%R65 0_0402_5%
10U_0805_6.3V6M
10U_0805_6.3V6M
C110
C110
1 2
PAD-OPEN 4x4m
PAD-OPEN 4x4m
@JP3
@
1 2
PAD-OPEN 4x4m
PAD-OPEN 4x4m
1
+
+
C102
C102
330U_D2_2V_Y
330U_D2_2V_Y
2
1 2
1 2
JP6
JP6
JP3
+1.5VS
+1.5V
8/31 Intel
+1.5V_CPU_VDDQ
VCCSA_SENSE
R919
R919
100_0402_5%
100_0402_5%
1 2
R918
R918
100_0402_5%
100_0402_5%
1 2
VSSSA_SENSE <52>
5
4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/12/01 2010/12/31
2009/12/01 2010/12/31
2009/12/01 2010/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(6/7) PWR
PROCESSOR(6/7) PWR
PROCESSOR(6/7) PWR
LA-6931P
LA-6931P
LA-6931P
1
9 58Wednesday, October 27, 2010
9 58Wednesday, October 27, 2010
9 58Wednesday, October 27, 2010
1.0
1.0
1.0
5
www.bufanxiu.com
D D
C C
B B
4
JCPU1H
JCPU1H
AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AR25
AR22
AR19
AR16
AR13
AR10
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AJ25
AR7
AR4
AR2
AP7
AP4
AP1
AN7
AN4
AK7
AK4
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
AT7
VSS11
AT4
VSS12
AT3
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
AL7
VSS66
AL4
VSS67
AL2
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
3
JCPU1I
JCPU1I
T35
VSS161
T34
VSS162
T33
VSS163
T32
VSS164
T31
VSS165
T30
VSS166
T29
VSS167
T28
VSS168
T27
VSS169
T26
VSS170
P9
VSS171
P8
VSS172
P6
VSS173
P5
VSS174
P3
VSS175
P2
VSS176
N35
VSS177
N34
VSS178
N33
VSS179
N32
VSS180
N31
VSS181
N30
VSS182
N29
VSS183
N28
VSS184
N27
VSS185
N26
VSS186
M34
VSS187
L33
VSS188
L30
VSS189
L27
VSS190
L9
VSS191
L8
VSS192
L6
VSS193
L5
VSS194
L4
VSS195
L3
VSS196
L2
VSS197
L1
VSS198
K35
VSS199
K32
VSS200
K29
VSS201
K26
VSS202
J34
VSS203
J31
VSS204
H33
VSS205
H30
VSS206
H27
VSS207
H24
VSS208
H21
VSS209
H18
VSS210
H15
VSS211
H13
VSS212
H10
VSS213
H9
VSS214
H8
VSS215
H7
VSS216
H6
VSS217
H5
VSS218
H4
VSS219
H3
VSS220
H2
VSS221
H1
VSS222
G35
VSS223
G32
VSS224
G29
VSS225
G26
VSS226
G23
VSS227
G20
VSS228
G17
VSS229
G11
VSS230
F34
VSS231
F31
VSS232
F29
VSS233
VSS
VSS
2
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
1
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
Sandy Bridge_rPGA_Rev1p0
Sandy Bridge_rPGA_Rev1p0
Sandy Bridge_rPGA_Rev1p0
CONN@
CONN@
A A
Security Classification
Security Classification
5
4
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/12/01 2010/12/31
2009/12/01 2010/12/31
2009/12/01 2010/12/31
Sandy Bridge_rPGA_Rev1p0
CONN@
CONN@
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(7/7) VSS
PROCESSOR(7/7) VSS
PROCESSOR(7/7) VSS
LA-6931P
LA-6931P
LA-6931P
1
1.0
1.0
10 58Wednesday, October 27, 2010
10 58Wednesday, October 27, 2010
10 58Wednesday, October 27, 2010
1.0
5
www.bufanxiu.com
+V_DDR_M3_REFA
12
M3@
M3@
R2016
R2016
0_0402_5%
0_0402_5%
D D
All VREF traces should
have 10 mil trace width
C C
B B
A A
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1
2
DDR_A_CKE0<6>
DDR_A_CLK0<6>
DDR_A_CLK0#<6>
DDR_A_CS1#<6>
8/30
+3VS
+V_DDR_M1_REFA_DQ
12
M1@
M1@
R2020
R2020
0_0402_5%
0_0402_5%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C2000
C2000
C2001
C2001
1
2
R2007 10K_0402_5%R2007 10K_0402_5%
1 2
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
1
C2023
C2023
2
5
VREF_DQA
DDR_A_D0
DDR_A_D1
DDR_A_DM0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_A_CKE0
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_CLK0
DDR_A_CLK0#
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_A_CS1#
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C2024
C2024
1
12
2
+1.5V +1.5V
JDIMM1
JDIMM1
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
31
VSS11
33
DQ10
35
DQ11
37
VSS13
39
DQ16
41
DQ17
43
VSS15
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
65
VSS23
67
DQ26
69
DQ27
71
VSS25
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
10K_0402_5%
10K_0402_5%
R2008
R2008
VTT1
205
G1
LCN_DAN06-K4406-0102
LCN_DAN06-K4406-0102
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
VSS24
DQ30
DQ31
VSS26
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
A15
80
A14
82
84
A11
86
A7
88
90
A6
92
A4
94
96
A2
98
A0
100
102
104
106
108
110
112
114
S0#
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
G2
4
DDR_A_D4
DDR_A_D5
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
DDR_A_DM1
DDR3_DRAMRST#
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_A_CKE1
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_CLK1
DDR_A_CLK1#
DDR_A_BS1
DDR_A_RAS#
DDR_A_CS0#
DDR_A_ODT0
DDR_A_ODT1
VREFA_CA
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
D_CK_SDATA
D_CK_SCLK
+0.75VS
4
DDR_A_CKE1 <6>
DDR_A_CLK1 <6>
DDR_A_CLK1# <6>
DDR_A_CS0# <6>
DDR_A_ODT0 <6>
DDR_A_ODT1 <6>
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C2015
C2015
1
1
2
2
M1@
M1@
0_0402_5%
0_0402_5%
C2016
C2016
M3@
M3@
0_0402_5%
0_0402_5%
DDR_A_CKE2<6>
DDR_A_BS2<6>
DDR_A_CLK2<6>
DDR_A_CLK2#<6>
DDR_A_BS0<6>
DDR_A_WE#<6>
DDR_A_CAS#<6>
DDR_A_CS3#<6>
+V_DDR_M1_REFA_CA
12
R2021
R2021
+V_DDR_M3_REFA
12
R2017
R2017
R2005 10K_0402_5%R2005 10K_0402_5%
+3VS
8/30
1 2
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
1
2
VREF_DQA
DDR_A_D0
DDR_A_D1
DDR_A_DM0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_A_CKE2
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_CLK2
DDR_A_CLK2#
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_A_CS3#
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C2022
C2022
1
C2021
C2021
2
3
+1.5V +1.5V
JDIMM2
JDIMM2
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
10K_0402_5%
10K_0402_5%
12
R2006
R2006
205
VTT1
G1
SUYIN_600023HB204G256ZL
SUYIN_600023HB204G256ZL
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
DQ14
DQ15
DQ20
DQ21
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
VTT2
CK1
BA1
NC2
SCL
A15
A14
A11
A7
A6
A4
A2
A0
S0#
G2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
DDR_A_D4
DDR_A_D5
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
DDR_A_DM1
DDR3_DRAMRST#
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_A_CKE3
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_CLK3
DDR_A_CLK3#
DDR_A_BS1
DDR_A_RAS#
DDR_A_CS2#
DDR_A_ODT2
DDR_A_ODT3
VREFA_CA
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
D_CK_SDATA
D_CK_SCLK
2
+0.75VS
DDR3_DRAMRST# <6,12>
DDR_A_CKE3 <6>
DDR_A_CLK3 <6>
DDR_A_CLK3# <6>
DDR_A_BS1 <6>
DDR_A_RAS# <6>
DDR_A_CS2# <6>
DDR_A_ODT2 <6>
DDR_A_ODT3 <6>
C2013
2.2U_0603_6.3V4Z
C2013
2.2U_0603_6.3V4Z
1
1
2
2
D_CK_SDATA <12,14,39>
D_CK_SCLK <12,14,39>
DDR3 SO-DIMM A
Standard Type
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/08/25 2010/08/25
2009/08/25 2010/08/25
2009/08/25 2010/08/25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
+1.5V
1K_0402_1%
1K_0402_1%
12
R2001
R2001
M1@
M1@
+V_DDR_M1_REFA_DQ
1K_0402_1%
1K_0402_1%
12
R2003
R2003
M1@
M1@
+1.5V
C2002
1U_0402_6.3V6K
C2002
1U_0402_6.3V6K
C2003
1U_0402_6.3V6K
C2003
1U_0402_6.3V6K
1
1
2
2
+1.5V
C2007
10U_0603_6.3V6M
C2007
10U_0603_6.3V6M
C2006
10U_0603_6.3V6M
C2006
10U_0603_6.3V6M
1
1
2
2
C2014
0.1U_0402_16V4Z
C2014
0.1U_0402_16V4Z
Layout Note:
Place near JDIMM1.203,204
+0.75VS
C2017
1U_0402_6.3V6K
C2017
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
2
2
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDRIII-SODIMM SLOT1
DDRIII-SODIMM SLOT1
DDRIII-SODIMM SLOT1
LA-6931P
LA-6931P
LA-6931P
1
+1.5V
1K_0402_1%
1K_0402_1%
12
M1@
M1@
1K_0402_1%
1K_0402_1%
12
M1@
M1@
DDR_A_DQS#[0..7] <6>
DDR_A_DQS[0..7] <6>
DDR_A_D[0..63] < 6>
DDR_A_MA[0..15] <6>
Layout Note:
Place near JDIMM1
C2005
1U_0402_6.3V6K
C2005
1U_0402_6.3V6K
C2004
1U_0402_6.3V6K
C2004
1U_0402_6.3V6K
1
1
2
2
C2009
10U_0603_6.3V6M
C2009
10U_0603_6.3V6M
C2008
10U_0603_6.3V6M
C2008
10U_0603_6.3V6M
1
2
C2018
C2018
1
2
C2010
10U_0603_6.3V6M
C2010
10U_0603_6.3V6M
1
1
2
2
C2019
1U_0402_6.3V6K
C2019
1U_0402_6.3V6K
C2020
1U_0402_6.3V6K
C2020
1U_0402_6.3V6K
1
2
1
R2002
R2002
+V_DDR_M1_REFA_CA
R2004
R2004
C2011
10U_0603_6.3V6M
C2011
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
2
2
11 58Wednesday, October 27, 2010
11 58Wednesday, October 27, 2010
11 58Wednesday, October 27, 2010
330U_D2_2V_Y
330U_D2_2V_Y
C2051
C2051
1
@
@
C2012
C2012
+
+
2
1.0
1.0
1.0
+V_DDR_M3_REFB
www.bufanxiu.com
12
M3@
M3@
R2018
R2018
0_0402_5%
0_0402_5%
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
C2025
C2025
1
1
D D
2
2
C C
DDR_B_CKE0<6>
DDR_B_CLK0<6>
DDR_B_CLK0#<6>
DDR_B_CS1#<6>
B B
A A
8/30
+3VS
C2049
2.2U_0603_6.3V4Z
C2049
2.2U_0603_6.3V4Z
1
1
2
2
10/9 Follow KAQ00, pin197
PU to +3VS
5
+V_DDR_M1_REFB_DQ
12
M1@
M1@
R2009
R2009
0_0402_5%
0_0402_5%
VREF_DQ_B
DDR_B_D0
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDR_B_D1
C2026
C2026
DDR_B_DM0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDR_B_CKE0
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_CLK0
DDR_B_CLK0#
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_B_CS1#
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
R2014
R2014
1 2
1 2
R2015 10K_0402_5%R2015 10K_0402_5%
C2050
0.1U_0402_16V4Z
C2050
0.1U_0402_16V4Z
5
+1.5V
10K_0402_5%
10K_0402_5%
JDIMM4
JDIMM4
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
SUYIN_600025HB204G256ZL
SUYIN_600025HB204G256ZL
CONN@
CONN@
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
DQ14
DQ15
DQ20
DQ21
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
+1.5V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
A15
80
A14
82
84
A11
86
A7
88
90
A6
92
A4
94
96
A2
98
A0
100
102
104
106
108
110
112
114
S0#
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
G2
4
DDR_B_D4
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR_B_DM1
DDR3_DRAMRST#
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_B_CKE1
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_CLK1
DDR_B_CLK1#
DDR_B_BS1
DDR_B_RAS#
DDR_B_CS0#
DDR_B_ODT0
DDR_B_ODT1
VREF_CAB
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
D_CK_SDATA
D_CK_SCLK
+0.75VS
4
DDR_B_CKE1 <6>
DDR_B_CLK1 <6>
DDR_B_CLK1# <6>
DDR_B_CS0# <6>
DDR_B_ODT0 <6>
DDR_B_ODT1 <6>
C2041
2.2U_0603_6.3V4Z
C2041
2.2U_0603_6.3V4Z
1
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C2042
C2042
8/30
+3VS
DDR_B_CKE2<6>
DDR_B_BS2<6>
DDR_B_CLK2<6>
DDR_B_CLK2#<6>
DDR_B_BS0<6>
DDR_B_WE#<6>
DDR_B_CAS#<6>
DDR_B_CS3#<6>
+V_DDR_M1_REFB_CA
M1@
M1@
12
R2019
R2019
0_0402_5%
0_0402_5%
+V_DDR_M3_REFB
M3@
M3@
12
R2022
R2022
0_0402_5%
0_0402_5%
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
C2048
C2048
C2047
C2047
1
1
2
2
3
+1.5V
VREF_DQ_B
DDR_B_D0
DDR_B_D1
DDR_B_DM0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDR_B_CKE2
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_CLK2
DDR_B_CLK2#
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_B_CS3#
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
R2012
R2012
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
1 2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R2013
R2013
1 2
JDIMM3
JDIMM3
1
VREF_DQ
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DM0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
DQ16
41
DQ17
43
VSS
45
DQS2#
47
DQS2
49
VSS
51
DQ18
53
DQ19
55
VSS
57
DQ24
59
DQ25
61
VSS
63
DM3
65
VSS
67
DQ26
69
DQ27
71
VSS
73
CKE0
75
VDD
77
NC
79
BA2
81
VDD
83
A12/BC#
85
A9
87
VDD
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VDD
101
CK0
103
CK0#
105
VDD
107
A10/AP
109
BA0
111
VDD
113
WE#
115
CAS#
117
VDD
119
A13
121
S1#
123
VDD
125
TEST
127
VSS
129
DQ32
131
DQ33
133
VSS
135
DQS4#
137
DQS4
139
VSS
141
DQ34
143
DQ35
145
VSS
147
DQ40
149
DQ41
151
VSS
153
DM5
155
VSS
157
DQ42
159
DQ43
161
VSS
163
DQ48
165
DQ49
167
VSS
169
DQS6#
171
DQS6
173
VSS
175
DQ50
177
DQ51
179
VSS
181
DQ56
183
DQ57
185
VSS
187
DM7
189
VSS
191
DQ58
193
DQ59
195
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
207
BOSS1
LCN_DAN06-K4406-0103
LCN_DAN06-K4406-0103
DQS0#
DQS0
DQ12
DQ13
RESET#
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQS3#
DQS3
DQ30
DQ31
CKE1
RAS#
ODT0
ODT1
VREF_CA
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQS5#
DQS5
DQ46
DQ47
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQS7#
DQS7
DQ62
DQ63
EVENT#
GND2
BOSS2
2009/08/25 2010/08/25
2009/08/25 2010/08/25
2009/08/25 2010/08/25
2
VSS
4
DQ4
6
DQ5
8
VSS
10
12
14
VSS
16
DQ6
18
DQ7
20
VSS
22
24
26
VSS
28
DM1
30
32
VSS
34
36
38
VSS
40
42
44
VSS
46
DM2
48
VSS
50
52
54
VSS
56
58
60
VSS
62
64
66
VSS
68
70
72
VSS
74
76
VDD
78
A15
80
A14
82
VDD
84
A11
86
A7
88
VDD
90
A6
92
A4
94
VDD
96
A2
98
A0
100
VDD
102
CK1
104
CK1#
106
VDD
108
BA1
110
112
VDD
114
S0#
116
118
VDD
120
122
NC
124
VDD
126
128
VSS
130
132
134
VSS
136
DM4
138
VSS
140
142
144
VSS
146
148
150
VSS
152
154
156
VSS
158
160
162
VSS
164
166
168
VSS
170
DM6
172
VSS
174
176
178
VSS
180
182
184
VSS
186
188
190
VSS
192
194
196
VSS
198
200
SDA
202
SCL
204
VTT
206
208
Compal Secret Data
Compal Secret Data
Compal Secret Data
+1.5V
DDR_B_D4
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR_B_DM1
DDR3_DRAMRST#
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_B_CKE3
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_CLK3
DDR_B_CLK3#
DDR_B_BS1
DDR_B_RAS#
DDR_B_CS2#
DDR_B_ODT2
DDR_B_ODT3
VREF_CAB
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
D_CK_SDATA
D_CK_SCLK
Deciphered Date
Deciphered Date
Deciphered Date
2
+0.75VS
2
DDR3_DRAMRST# <6,11>
DDR_B_CKE3 <6>
DDR_B_CLK3 <6>
DDR_B_CLK3# <6>
DDR_B_BS1 <6>
DDR_B_RAS# <6>
DDR_B_CS2# <6>
DDR_B_ODT2 <6>
DDR_B_ODT3 <6>
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
C2039
C2039
D_CK_SDATA <11,14,39>
C2040
0.1U_0402_16V4Z
C2040
0.1U_0402_16V4Z
1
1
2
2
D_CK_SCLK <11,14,39>
1
+1.5V
1K_0402_1%
1K_0402_1%
12
R2010
R2010
M1@
M1@
M1@
M1@
C2028
C2028
C2029
1U_0402_6.3V6K
C2029
1U_0402_6.3V6K
1
2
C2035
10U_0603_6.3V6M
C2035
10U_0603_6.3V6M
C2034
10U_0603_6.3V6M
C2034
10U_0603_6.3V6M
1
1
2
2
Layout Note:
Place near JDIMMB.203,204
C2044
1U_0402_6.3V6K
C2044
1U_0402_6.3V6K
C2045
1U_0402_6.3V6K
C2045
1U_0402_6.3V6K
1
2
+V_DDR_M1_REFB_CA
1K_0402_1%
1K_0402_1%
12
R2011
R2011
DDR_B_DQS#[0..7] <6>
DDR_B_DQS[0..7] <6>
DDR_B_D[0..63] <6>
DDR_B_MA[0..15] <6>
C2030
1U_0402_6.3V6K
C2030
1U_0402_6.3V6K
1
2
C2036
10U_0603_6.3V6M
C2036
10U_0603_6.3V6M
C2037
10U_0603_6.3V6M
C2037
10U_0603_6.3V6M
1
1
2
2
C2046
1U_0402_6.3V6K
C2046
1U_0402_6.3V6K
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
@
@
C2038
C2038
1
2
M1@
M1@
M1@
M1@
+1.5V
12
12
+1.5V
+1.5V
+0.75VS
1K_0402_1%
1K_0402_1%
R2023
R2023
1K_0402_1%
1K_0402_1%
R2024
R2024
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
1
2
+V_DDR_M1_REFB_DQ
1U_0402_6.3V6K
1U_0402_6.3V6K
C2027
C2027
1
2
Layout Note:
Place near JDIMMB
C2032
C2032
C2033
10U_0603_6.3V6M
C2033
10U_0603_6.3V6M
1
2
C2043
1U_0402_6.3V6K
C2043
1U_0402_6.3V6K
1
2
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR3 SO-DIMM B
Reverse Type
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDRIII-SODIMM SLOT2
DDRIII-SODIMM SLOT2
DDRIII-SODIMM SLOT2
LA-6931P
LA-6931P
LA-6931P
1
12 58Wednesday, October 27, 2010
12 58Wednesday, October 27, 2010
12 58Wednesday, October 27, 2010
330U_D2_2V_Y
330U_D2_2V_Y
@
@
1
C2031
C2031
+
+
2
1.0
1.0
1.0
5
www.bufanxiu.com
PCH_RTCX1
1 2
R69 10M_0402_5%R69 10M_0402_5%
32.768KHZ_12.5PF_Q13MC14610002Y132.768KHZ_12.5PF_Q13MC14610002
1
Y1
18P_0402_50V8J
18P_0402_50V8J
1
D D
2
+RTCVCC
R849 1M_0402_5%R849 1M_0402_5%
R850 330K_0402_5%R850 330K_0402_ 5%
*
OSC4OSC
C840
C840
NC3NC
2
1 2
1 2
INTVRMEN
H
：：：：
Integrated VRM enable
L
：：：：
Integrated VRM disable
PCH_RTCX2
1
C841
C841
18P_0402_50V8J
18P_0402_50V8J
2
SM_INTRUDER#
PCH_INTVRMEN
+RTCVCC
1U_0603_10V4Z
1U_0603_10V4Z
1 2
R71 20K_04 02_5%R71 20K_0402_5%
1 2
R848 20 K_0402_5%R848 20K_0402_5%
1U_0603_10V4Z
1U_0603_10V4Z
C839
C839
C843
C843
(INTVRMEN should always be pull high.)
+3VS
R79 1K_0402_5%@R79 1K_0402_5%@
1 2
HIGH= Enable ( No Reboot )
LOW= Disable (Default)
*
C C
+3VALW_PCH
HDA_SDO<40>
HDA_SDO
ME debug mode,this signal has a weak internal PD
Low = Disabled (Default)
*
High = Enabled [Flash Descriptor Security Overide]
+3VALW_PCH
R89 1K_0402_5%R89 1K_0402_5%
R853
@R853
@
1K_0402_5%
1K_0402_5%
R85
R85
0_0402_5%
0_0402_5%
12
HDA_SPKR
HDA_SPKR<42>
HDA_SDOUT
12
12
HDA_SYNC
HDA_SDIN0<42>
PAD
PAD
PAD
PAD
R90
R90
51_0402_5%
51_0402_5%
This signal has a weak internal pull-down
On Die PLL VR Select is supplied by
1.5V when sampled high
*
1.8V when sampled low
Needs to be pulled High for Huron River platfrom
B B
R95
R95
33_0402_5%
33_0402_5%
HDA_BIT_CLK
HDA_BITCLK_AUDIO<42>
HDA_SYNC_AUDIO<42>
HDA_RST#_AUDIO<42>
HDA_SDOUT_AUDIO<42>
1 2
R96
R96
33_0402_5%
33_0402_5%
1 2
R99
R99
33_0402_5%
33_0402_5%
1 2
R100
R100
33_0402_5%
33_0402_5%
1 2
HDA_SYNC_R
HDA_RST#
HDA_SDOUT
Prevent back drive issue.
+3VS
G
G
2
Q4
Q4
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
HDA_SYNC
13
D
S
D
S
R97
R97
1 2
0_0402_5%@
0_0402_5%@
12
R930
R930
1M_0402_5%
1M_0402_5%
ME
T19
T19
T18
T18
1
2
1
2
12
4
CMOS
JCMOS1
SHORT PADS@JCMOS1
SHORT PADS
12
@
10/21
PCH_RTCX1
PCH_RTCX2
PCH_RTCRST#
PCH_SRTCRST#
SM_INTRUDER#
PCH_INTVRMEN
HDA_BIT_CLK
HDA_SYNC
HDA_SPKR
HDA_RST#
HDA_SDIN0
HDA_SDOUT
GPIO33
GPIO13
PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_SPI_CLK
PCH_SPI_CS#
PCH_SPI_SI
PCH_SPI_SO
PCH_RTCRST#
PCH_SRTCRST#
A20
C20
D20
G22
K22
C17
N34
L34
T10
K34
E34
G34
C34
A34
A36
C36
N32
J3
H7
K5
H1
T3
Y14
T1
V4
U3
U60A
U60A
RTCX1
RTCX2
RTCRST#
SRTCRST#
INTRUDER#
INTVRMEN
HDA_BCLK
HDA_SYNC
SPKR
HDA_RST#
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
HDA_SDO
HDA_DOCK_EN# / GPIO33
HDA_DOCK_RST# / GPIO13
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
SPI_CLK
SPI_CS0#
SPI_CS1#
SPI_MOSI
SPI_MISO
COUGARPOINT_FCBGA989~D
COUGARPOINT_FCBGA989~D
JTAG
JTAG
RTCIHDA
RTCIHDA
SPI
SPI
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
LPC
LPC
FWH4 / LFRAME#
LDRQ0#
LDRQ1# / GPIO23
SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA 6G
SATA 6G
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA
SATA
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATAICOMPO
SATAICOMPI
SATA3RCOMPO
SATA3COMPI
SATA3RBIAS
SATALED#
SATA0GP / GPIO21
SATA1GP / GPIO19
3
C842
C842
1U_0603_10V4Z
Place C127 close to PCH.
C38
A38
B37
C37
D36
E36
K36
V5
AM3
AM1
AP7
AP5
AM10
AM8
AP11
AP10
AD7
AD5
AH5
AH4
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
Y11
Y10
AB12
AB13
AH1
P3
V14
P1
1U_0603_10V4Z
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
DCR_R DCR
1 2
R78 0_0402_5%R78 0_0402_5%
SERIRQ
SATA_DTX_C_PRX_N4
SATA_DTX_C_PRX_P4
SATA_PTX_DRX_N4
SATA_PTX_DRX_P4
37.4_0402_1%
SATA_COMP
SATA3_COMP
RBIAS_SATA3
PCH_SATALED#
PCH_GPIO21
PCH_GPIO19
37.4_0402_1%
1 2
49.9_0402_1%
49.9_0402_1%
1 2
1 2
R94 750_0402_1%R94 750_0402_1%
2
+RTCVCC +RTCBATT
1
1
2
LPC_AD0 <39,40>
LPC_AD1 <39,40>
LPC_AD2 <39,40>
LPC_AD3 <39,40>
LPC_FRAME# <39,40>
SERIRQ <40>
SATA_DTX_C_PRX_N0 <33>
SATA_DTX_C_PRX_P0 <33>
SATA_PTX_DRX_N0 <33>
SATA_PTX_DRX_P0 <33>
SATA_DTX_C_PRX_N2 <33>
SATA_DTX_C_PRX_P2 <33>
SATA_PTX_DRX_N2 <33>
SATA_PTX_DRX_P2 <33>
trace width 10milW=20mils
D1
D1
2
R70 1K_0402_5%R70 1K_0402_5%
3
BAV70W_SOT323-3
BAV70W_SOT323-3
DCR <30>
HDD
ODD
W=20mils
+3VLP
12
PCH_GPIO19
SERIRQ
PCH_SATALED#
DCR
SPI ROM FOR ME ( 4MByte )
If use SPI programme r,
R854 shoul d be open
(Normal is pop)
R854
R854
+3VS
0_0402_5%
0_0402_5%
1 2
D10
@ D1 0
@
2 1
CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
9/06
R91
R91
R93
R93
PCH_SATALED# < 41>
PAD
PAD
T15
T15
SATA for eSATA
SATA_DTX_C_PRX_N4 <36>
SATA_DTX_C_PRX_P4 <36>
SATA_PTX_DRX_N4 <36>
SATA_PTX_DRX_P4 <36>
+1.05VS_VCC_SATA
+1.05VS_SATA3
PCH_SPI_CS#
R86 0_0402_5%R86 0_0402_5%
PCH_SPI_CLK
R87 33_0402_5%R87 33_0402_5%
PCH_SPI_SI
R856 33_0402_5%R856 33_0402_5%
1 2
1 2
1 2
10/20
JBATT1
JBATT1
1
+
LOTES_AAA-BAT-019-K01_2P
LOTES_AAA-BAT-019-K01_2P
CONN@
CONN@
R224 10K_0402_5%R224 10K_0402_5%
R74 10K_0402_5%R74 10K_0402_5%
R851 10K_0402_5%R851 10K_0402_5%
R77 20K_0402_5%@R77 20K_0402_5%@
1 2
Please short PJP35
C844
C844
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PCH_SPI_WP#
PCH_SPI_HOLD#
PCH_SPI_CS#_R
PCH_SPI_CLK_R
PCH_SPI_SI_R
C845
@C845
@
22P_0402_50V8J
22P_0402_50V8J
12
PCH_SPI_WP#
PCH_SPI_HOLD#
-
12
12
12
R80 3.3K_0402_5%R80 3.3K_0402_5%
R852 3.3K_04 02_5%R852 3.3K_0402 _5%
+3V_DSW_SPI
PCH_SPI_SO PCH_SPI_SO_R
U4
U4
8
VCC
3
W
7
HOLD
1
S
6
C
5
D
32M MX25L3206EM2I-12G SOP 8P 3V
32M MX25L3206EM2I-12G SOP 8P 3V
R92
@R92
@
33_0402_5%
33_0402_5%
PCH_SPI_CLK_R
1 2
Reserve for EMI please close to UH1
1
2
+3VS
1 2
1 2
R855 33_0402_5%R855 33_0402_5%
4
VSS
PCH_SPI_SO_R
2
Q
+3VS
12
C905 22P_0402_50V8J
C214 22P_0402_50V8J
C214 22P_0402_50V8J
+3VALW_PCH +3VALW_PCH+3VALW_PCH
12
A A
R857
R857
200_0402_5%
200_0402_5%
PCH_JTAG_TDO PCH_JTAG_TDIPC H_JTAG_TMS
12
R859
R859
100_0402_1%
100_0402_1%
@
@
1 2
12
R858
R858
200_0402_5%
200_0402_5%
12
R860
R860
100_0402_1%
100_0402_1%
HDA_SDOUT_AUDIO
12
200_0402_5%
200_0402_5%
12
100_0402_1%
100_0402_1%
5
R104
R104
R861
R861
HDA_BITCLK_AUDIO
@
@
1 2
C905 22P_0402_50V8J
9/29
PCH_GPIO21
Project ID GPIO21
DIS
*
Muxless
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/12/01 2010/12/31
2009/12/01 2010/12/31
2009/12/01 2010/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
0
1
Title
Title
Title
PCH (1/8) SATA,HDA,SPI, LPC, XDP
PCH (1/8) SATA,HDA,SPI, LPC, XDP
PCH (1/8) SATA,HDA,SPI, LPC, XDP
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
LA-6931P
LA-6931P
LA-6931P
Date: Sheet of
Date: Sheet of
Date: Sheet of
R98 10K_0402_5%D IS@R98 10K _0402_5%DIS@
R101 10K_0402_5%SG@R101 10K_0402_5%SG@
12
12
Compal Electronics, Inc.
1
+3VS
1.0
1.0
13 58Wednesday, October 27, 2010
13 58Wednesday, October 27, 2010
13 58Wednesday, October 27, 2010
1.0
5
www.bufanxiu.com
PCIE_PRX_DTX_N1<34>
PCIE LAN
Wireless LAN
D D
USB3.0
Card Reader
C C
Wireless LAN
USB3.0
PCIE LAN
Card Reader
B B
+3VS
R148 10K_0402_5%R148 10K_0402_5%
R150 10K_0402_5%R150 10K_0402_5%
A A
+3VALW_PCH
R153 10K_0402_5%R153 10K_0402_5%
R154 10K_0402_5%R154 10K_0402_5%
R155 10K_0402_5%R155 10K_0402_5%
R879 10K_0402_5%R879 10K_0402_5%
R881 10K_0402_5%R881 10K_0402_5%
R161 10K_0402_5%R161 10K_0402_5%
R162 10K_0402_5%R162 10K_0402_5%
PCIE_PRX_DTX_P1<34>
PCIE_PTX_C_DRX_N1<34>
PCIE_PTX_C_DRX_P1<34>
PCIE_PRX_DTX_N2<39>
PCIE_PRX_DTX_P2<39>
PCIE_PTX_C_DRX_N2<39>
PCIE_PTX_C_DRX_P2<39>
PCIE_PRX_C_DTX_N4<37>
PCIE_PRX_C_DTX_P4<37>
PCIE_PTX_C_DRX_N4<37>
PCIE_PTX_C_DRX_P4<37>
PCIE_PRX_C_DTX_N5<38>
PCIE_PRX_C_DTX_P5<38>
PCIE_PTX_C_DRX_N5<38>
PCIE_PTX_C_DRX_P5<38>
CLK_PCIE_MINI1#<39>
CLK_PCIE_MINI1<39>
MINI1_CLKREQ#<39>
CLK_PCIE_USB30#<37>
CLK_PCIE_USB30<37>
USB30_CLKREQ#<37>
CLK_PCIE_LAN#<34>
CLK_PCIE_LAN<34>
LAN_CLKREQ#<34>
CLK_PCIE_READER#<38>
CLK_PCIE_READER<38>
CLK_PEG_VGA#<22>
CLK_PEG_VGA<22>
PEG_CLKREQ#<23>
CLK_RES_ITP#<7>
CLK_RES_ITP<7>
12
12
12
12
12
12
12
12
12
5
C846 0.1U_0402_10V7KC846 0.1U_0402_10V7K
C847 0.1U_0402_10V7KC847 0.1U_0402_10V7K
C848 0.1U_0402_10V7KC848 0.1U_0402_10V7K
C849 0.1U_0402_10V7KC849 0.1U_0402_10V7K
C850 0.1U_0402_10V7KC850 0.1U_0402_10V7K
C851 0.1U_0402_10V7KC851 0.1U_0402_10V7K
C852 .1U_0402_16V7KC852 .1U_0402_16V7K
C138 .1U_0402_16V7KC138 .1U_0402_16V7K
R867 0_0402_5%R867 0_0402_5%
R119 0_0402_5%R119 0_0402_5%
R868 0_0402_5%R868 0_0402_5%
R869 0_0402_5%R869 0_0402_5%
R124 0_0402_5%R124 0_0402_5%
R125 0_0402_5%R125 0_0402_5%
R143 0_0402_5%R143 0_0402_5%
R878 0_0402_5%R878 0_0402_5%
MINI1_CLKREQ#
USB30_CLKREQ#
PEG_D_CLKREQ#
PCH_GPIO73
LAN_CLKREQ#
PCH_GPIO26
PCH_GPIO44
PCH_GPIO45
PCH_GPIO46
1 2
1 2
1 2
1 2
1 2
1 2
12
12
12
12
12
12
1 2
1 2
R875 0_0402_5%R875 0_0402_5%
1 2
R132 0_0402_5%R132 0_0402_5%
1 2
R138 0_0402_5%R138 0_0402_5%
1 2
R139 0_0402_5%R139 0_0402_5%
1 2
12
12
4
U60B
PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1
PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2
PCIE_PRX_C_DTX_N4
PCIE_PRX_C_DTX_P4
PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4
PCIE_PRX_C_DTX_N5
PCIE_PRX_C_DTX_P5
PCIE_PTX_DRX_N5
PCIE_PTX_DRX_P5
PCH_GPIO73
CLK_MINI1#
CLK_MINI1
CLK_USB30#
CLK_USB30
USB30_CLKREQ#
CLK_LAN#
PCH_GPIO26
CLK_READER#
CLK_READER
PCH_GPIO44
CLK_VGA#
CLK_VGA
PCH_GPIO45 XTAL25_OUT
PCH_GPIO46
CLK_BCLK_ITP#
CLK_BCLK_ITP
R927 0_0402_5%R927 0_0402_5%
1 2
D11
@D11
@
CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
U60B
BG34
PERN1
BJ34
PERP1
AV32
PETN1
AU32
PETP1
BE34
PERN2
BF34
PERP2
BB32
PETN2
AY32
PETP2
BG36
PERN3
BJ36
PERP3
AV34
PETN3
AU34
PETP3
BF36
PERN4
BE36
PERP4
AY34
PETN4
BB34
PETP4
BG37
PERN5
BH37
PERP5
AY36
PETN5
BB36
PETP5
BJ38
PERN6
BG38
PERP6
AU36
PETN6
AV36
PETP6
BG40
PERN7
BJ40
PERP7
AY40
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW38
PETN8
AY38
PETP8
Y40
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P
J2
PCIECLKRQ0# / GPIO73
AB49
CLKOUT_PCIE1N
AB47
CLKOUT_PCIE1P
M1
PCIECLKRQ1# / GPIO18
AA48
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P
V10
PCIECLKRQ2# / GPIO20
Y37
CLKOUT_PCIE3N
Y36
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GPIO25
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P
L12
PCIECLKRQ4# / GPIO26
V45
CLKOUT_PCIE5N
V46
CLKOUT_PCIE5P
L14
PCIECLKRQ5# / GPIO44
AB42
CLKOUT_PEG_B_N
AB40
CLKOUT_PEG_B_P
E6
PEG_B_CLKRQ# / GPIO56
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
T13
PCIECLKRQ6# / GPIO45
V38
CLKOUT_PCIE7N
V37
CLKOUT_PCIE7P
K12
PCIECLKRQ7# / GPIO46
AK14
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
AK13
CLKOUT_BCLK0_P / CLKOUT_PCIE8P
COUGARPOINT_FCBGA989~D
COUGARPOINT_FCBGA989~D
PEG_CLKREQ#PEG_D_CLKREQ#
21
SMBUSController
SMBUSController
SML1ALERT# / PCHHOT# / GPIO74
PCI-E*
PCI-E*
CLOCKS
CLOCKS
CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P
9/06
4
3
LID_SW_OUT#
SMBCLK
SMBDATA
SML0CLK
SML0DATA
CL_CLK1
CL_DATA1
CL_RST1#
XTAL25_IN
E12
PCH_SMBCLK
H14
PCH_SMBDATA
C9
DRAMRST_CNTRL_PC H
A12
PCH_SML0CLK
C8
PCH_SML0DATA
G12
PCH_GPIO74
C13
PCH_SML1CLK
E14
PCH_SML1DATA
M16
M7
T11
P10
PCH_GPIO47
M10
AB37
AB38
CLK_CPU_DMI#
AV22
CLK_CPU_DMI
AU22
CLK_DP#
AM12
CLK_DP
AM13
CLK_BUF_CPU_DMI#
BF18
CLK_BUF_CPU_DMI
BE18
CLKIN_DMI2#
BJ30
CLKIN_DMI2CLK_LAN
BG30
CLK_BUF_DREF_96M#
G24
CLK_BUF_DREF_96M
E24
CLK_BUF_PCIE_SATA#
AK7
CLK_BUF_PCIE_SATA
AK5
CLK_BUF_ICH_14M
K45
CLK_PCI_LPBACK
H45
XTAL25_IN
V47
XTAL25_OUT
V49
XCLK_RCOMP
Y47
CLK_FLEX0
K43
CLK_27M_TCLK_R
F47
CLK_FLEX1
H47
CLK_48M_USB3_PCH_R
K49
12
2009/12/01 2010/12/31
2009/12/01 2010/12/31
2009/12/01 2010/12/31
SMBALERT# / GPIO11
SML0ALERT# / GPIO60
SML1CLK / GPIO58
SML1DATA / GPIO75
Link
Link
PEG_A_CLKRQ# / GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_DMI2_N
CLKIN_DMI2_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P
REFCLK14IN
CLKIN_PCILOOPBACK
XTAL25_OUT
XCLK_RCOMP
CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67
FLEX CLOCKS
FLEX CLOCKS
R145 100K_0402_5%R145 100K_0402_ 5%
+3VS
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
LID_SW_OUT# <40>
DRAMRST_CNTRL_PC H <6,7>
CLK_CPU_DMI# <5>
CLK_CPU_DMI <5>
CLK_DP# <5>
CLK_DP < 5>
CLK_PCI_LPBACK <17>
R141
R141
90.9_0402_1%
90.9_0402_1%
1 2
T16 PADT16 PAD
R906 22_0402_5%R906 22_0402_5%
T17 PADT17 PAD
2
G
G
Compal Secret Data
Compal Secret Data
Compal Secret Data
R307 22_0402_5%@R307 22_0402_5 %@
PCH_GPIO44
13
D
D
Q5
Q5
SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
S
S
Deciphered Date
Deciphered Date
Deciphered Date
12
CR_CLKREQ# <38>
12
2
+1.05VS_VCCDIFFCLKN
CLK_27M_TCLK <23>
CLK_48M_USB3_PCH <37>
2
1
PCH_SMBCLK
PCH_SMBDATA
PCH_SML0CLK
PCH_SML0DATA
PCH_SML1CLK
PCH_SML1DATA
PCH_GPIO74
PCH_GPIO47
LID_SW_OUT#
DRAMRST_CNTRL_PC H
6 1
DMN66D0LDW-7 2N_SOT363-6
DMN66D0LDW-7 2N_SOT363-6
PCH_SMBCLK
PCH_SML1DATA
DMN66D0LDW-7 2N_SOT363-6
DMN66D0LDW-7 2N_SOT363-6
PCH_SML1CLK
CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI
CLKIN_DMI2#
CLKIN_DMI2
CLK_BUF_DREF_96M#
CLK_BUF_DREF_96M
CLK_BUF_PCIE_SATA#
CLK_BUF_PCIE_SATA
CLK_BUF_ICH_14M
XTAL25_IN
C853
C853
27P_0402_50V8J
27P_0402_50V8J
CLK_BUF_ICH_14M
CLK_PCI_LPBACK
R110 2.2K_0402_5%R110 2.2K_0402_5%
1 2
R111 2.2K_0402_5%R111 2.2K_0402_5%
1 2
R146 2.2K_0402_5%R146 2.2K_0402_5%
1 2
R877 2.2K_0402_5%R877 2.2K_0402_5%
1 2
R113 2.2K_0402_5%R113 2.2K_0402_5%
1 2
R864 2.2K_0402_5%R864 2.2K_0402_5%
1 2
R112 10K_0402_5%R112 10K_0402_5%
1 2
R865 10K_0402_5%R865 10K_0402_5%
1 2
R862 10K_0402_5%R862 10K_0402_5%
1 2
R863 10K_0402_5%R863 10K_0402_5%
1 2
+3VS
Q8A
Q8A
3 4
DMN66D0LDW-7 2N_SOT363-6
DMN66D0LDW-7 2N_SOT363-6
6 1
Q3A
Q3A
DMN66D0LDW-7 2N_SOT363-6
DMN66D0LDW-7 2N_SOT363-6
1
2
R116
R116
4.7K_0402_5%
4.7K_0402_5%
2
1 2
D_CK_SDATAPCH_SMBDATA
R866
R866
4.7K_0402_5%
4.7K_0402_5%
5
1 2
D_CK_SCLK
Q8B
Q8B
+3VS
2
5
3 4
Q3B
Q3B
R871 10K_0402_5%R871 10K_0402_5%
1 2
R872 10K_0402_5%R872 10K_0402_5%
1 2
R873 10K_0402_5%R873 10K_0402_5%
1 2
R874 10K_0402_5%R874 10K_0402_5%
1 2
R876 10K_0402_5%R876 10K_0402_5%
1 2
R134 10K_0402_5%R134 10K_0402_5%
1 2
R136 10K_0402_5%R136 10K_0402_5%
1 2
R137 10K_0402_5%R137 10K_0402_5%
1 2
R140 10K_0402_5%R140 10K_0402_5%
1 2
1 2
R904 1M_0402_5%R904 1M _0402_5%
Y2
Y2
25MHZ_20PF_7A25000012
25MHZ_20PF_7A25000012
@R147
@
33_0402_5%
33_0402_5%
@R151
@
33_0402_5%
33_0402_5%
12
R147
12
R151
12
+3VS
+3VS
Pull up at EC side.
EC_SMB_DA2
EC_SMB_CK2
1
C854
C854
27P_0402_50V8J
27P_0402_50V8J
2
C855
@C855
@
22P_0402_50V8J
22P_0402_50V8J
1 2
C856
@C856
@
22P_0402_50V8J
22P_0402_50V8J
1 2
D_CK_SDATA <11,12,39>
D_CK_SCLK <11,12,39>
EC_SMB_DA2 <23,40>
EC_SMB_CK2 <23,40>
Reserve for EMI please close to U60
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (2/8) PCIE, SMBUS, CLK
PCH (2/8) PCIE, SMBUS, CLK
PCH (2/8) PCIE, SMBUS, CLK
LA-6931P
LA-6931P
LA-6931P
1
14 58Wednesday, October 27, 2010
14 58Wednesday, October 27, 2010
14 58Wednesday, October 27, 2010
+3VALW_PCH
10/11
1.0
1.0
1.0
5
www.bufanxiu.com
D D
R189
R189
0_0402_5%
0_0402_5%
12
+3VS
5
U5
@U5
@
PCH_PWROK<40>
VGATE<56>
C C
R167 10K_0402_5%R167 10K_0402_5%
SPOK<49,50>
+3VS
R883 200_0402_5%R883 200_0402_5%
B B
+3VALW_PCH
R183 10K_0402_5%R183 10K_0402_5%
R184 200K_0402_5%R184 200K_0402_5%
R185 10K_0402_5%R185 10K_0402_5%
R885 10K_0402_5%R885 10K_0402_5%
1
IN1
VCC
OUT
2
IN2
GND
MC74VHC1G08DFT2G_SC70-5
MC74VHC1G08DFT2G_SC70-5
3
12
R174
R174
0_0402_5%
0_0402_5%
SUSWARN#_RSUSACK#_R
@
@
12
D5
D5
CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
12
12
12
12
12
SYS_PWROK
4
SYS_PWROK
PCH_RSMRST#_R
21
PM_DRAM_PWR GD
SUSWARN#
PCH_ACIN
PCH_GPIO72
RI#
SYS_PWROK <27>
XDP_DBRESET#<5>
PCH_APWROK<40>
PM_DRAM_PWR GD<5>
PCH_RSMRST#<40>
PBTN_OUT#<40>
SUSWARN#<40>
DMI_CTX_PRX_N0<4>
DMI_CTX_PRX_N1<4>
DMI_CTX_PRX_N2<4>
DMI_CTX_PRX_N3<4>
DMI_CTX_PRX_P0<4>
DMI_CTX_PRX_P1<4>
DMI_CTX_PRX_P2<4>
DMI_CTX_PRX_P3<4>
DMI_CRX_PTX_N0<4>
DMI_CRX_PTX_N1<4>
DMI_CRX_PTX_N2<4>
DMI_CRX_PTX_N3<4>
DMI_CRX_PTX_P0<4>
DMI_CRX_PTX_P1<4>
DMI_CRX_PTX_P2<4>
DMI_CRX_PTX_P3<4>
+1.05VS_VCCP
PCH_PWROK
ACIN<40,45,48>
4
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
1 2
1 2
1 2
DMI_IRCOMP
RBIAS_CPY
SUSACK#_R
XDP_DBRESET#_R
SYS_PWROK
PCH_PWROK_R
PM_DRAM_PWR GD
PCH_RSMRST#_R
SUSWARN#_R
PBTN_OUT#_R
PCH_ACIN
21
APWROK
PCH_GPIO72
RI#
1 2
R165 49.9_0402_1%R165 49.9_0402_1%
1 2
R166 750_0402_1%R166 750_0402_1%
4mil width and place
within 500mil of the PCH
R171 0_0402_5%R171 0_0402_5%
R176 0_0402 _5%R176 0_0402_5%
R882 0_0402 _5%R882 0_0402_5%
1 2
R179 0_0402_5%R179 0_0402_5%
1 2
R884 0_0402_5%R884 0_0402_5%
1 2
R182 0_0402_5%R 182 0_0402_5%
D2 CH751H-40PT_SOD323-2D2 CH751H-40PT_SOD323-2
U60C
U60C
BC24
DMI0RXN
BE20
DMI1RXN
BG18
DMI2RXN
BG20
DMI3RXN
BE24
DMI0RXP
BC20
DMI1RXP
BJ18
DMI2RXP
BJ20
DMI3RXP
AW24
DMI0TXN
AW20
DMI1TXN
BB18
DMI2TXN
AV18
DMI3TXN
AY24
DMI0TXP
AY20
DMI1TXP
AY18
DMI2TXP
AU18
DMI3TXP
BJ24
DMI_ZCOMP
BG25
DMI_IRCOMP
BH21
DMI2RBIAS
C12
SUSACK#
K3
SYS_RESET#
P12
SYS_PWROK
L22
PWROK
L10
APWROK
B13
DRAMPWROK
C21
RSMRST#
K16
SUSWARN# / SUS_PW R_DN_ACK / GPIO30
E20
PWRBTN#
H20
ACPRESENT / GPIO31
E10
BATLOW# / GPIO72
A10
RI#
COUGARPOINT_FCBGA989~D
COUGARPOINT_FCBGA989~D
3
BJ14
FDI_RXN0
AY14
FDI_RXN1
BE14
FDI_RXN2
BH13
FDI_RXN3
BC12
FDI_RXN4
BJ12
FDI_RXN5
BG10
FDI_RXN6
BG9
FDI_RXN7
BG14
FDI_RXP0
BB14
FDI_RXP1
BF14
FDI_RXP2
BG13
FDI_RXP3
BE12
FDI_RXP4
BG12
FDI_RXP5
BJ10
DMI
DMI
System Power Management
System Power Management
FDI_RXP6
FDI
FDI
FDI_RXP7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWVRMEN
DPWROK
WAKE#
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
PMSYNCH
SLP_LAN# / GPIO29
BH9
AW16
AV12
BC10
AV14
BB10
A18
E22
B9
N3
G8
N14
D10
H4
F4
G10
G16
AP14
K14
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWODVREN
PCH_DPWROK
WAKE#
PCH_GPIO32
SUS_STAT#
SUSCLK
PM_SLP_S5#
PM_SLP_S4#
PM_SLP_S3#
T30 PADT30 PAD
T24 PADT24 PAD
H_PM_SYNC
PCH_GPIO29
R172
R172
0_0402_5%
0_0402_5%
1 2
R168
@R168
@
0_0402_5%
0_0402_5%
1 2
T20 PADT20 PAD
T21 PADT21 PAD
T22 PADT22 PAD
T23 PADT23 PAD
T25 PADT25 PAD
2
FDI_CTX_PRX_N0 <4>
FDI_CTX_PRX_N1 <4>
FDI_CTX_PRX_N2 <4>
FDI_CTX_PRX_N3 <4>
FDI_CTX_PRX_N4 <4>
FDI_CTX_PRX_N5 <4>
FDI_CTX_PRX_N6 <4>
FDI_CTX_PRX_N7 <4>
FDI_CTX_PRX_P0 <4>
FDI_CTX_PRX_P1 <4>
FDI_CTX_PRX_P2 <4>
FDI_CTX_PRX_P3 <4>
FDI_CTX_PRX_P4 <4>
FDI_CTX_PRX_P5 <4>
FDI_CTX_PRX_P6 <4>
FDI_CTX_PRX_P7 <4>
FDI_INT <4>
FDI_FSYNC0 <4>
FDI_FSYNC1 <4>
FDI_LSYNC0 <4>
FDI_LSYNC1 <4>
PCH_RSMRST#_R
PCH_DPWROK <40>
PCH_PCIE_WAKE# <34,37,39>
SUSCLK <40>
PM_SLP_S5# <4 0>
PM_SLP_S4# <4 0>
PM_SLP_S3# <4 0>
H_PM_SYNC <5>
DSWODVREN
*
WAKE#
PCH_GPIO29
PCH_GPIO32
Can be left NC
when IAMT is not
support on the
platfrom
R163 330K_0402_5%R163 330K_0402_5%
R164 330K_0402_5%@R164 330K_0402_5%@
DSWODVREN - On D ie DSW VR Enabl e
H：Enable
L：Disable
R170 10K_0402_5%R170 10K_0402_5%
R173 10K_0402_5%@R173 10K_0402_5%@
R175 8.2K_0402_5%R175 8.2K_0402_5%
1
1 2
1 2
1 2
+RTCVCC
12
12
+3VALW_PCH
+3VS
R187 10K_0402_5%R187 10K_0402_5%
A A
12
5
PCH_RSMRST#
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/12/01 2010/12/31
2009/12/01 2010/12/31
2009/12/01 2010/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet
Compal Electronics, Inc.
PCH (3/8) DMI,FDI,PM,
PCH (3/8) DMI,FDI,PM,
PCH (3/8) DMI,FDI,PM,
LA-6931P
LA-6931P
LA-6931P
1
1.0
1.0
1.0
of
15 58Wednesday, October 27, 2010
15 58Wednesday, October 27, 2010
15 58Wednesday, October 27, 2010
5
www.bufanxiu.com
D D
R188 100K_0402_5%R188 100K_0402_ 5%
1 2
ENBKL
Reserved for DIS Only
R193 0_0402_5%DIS@R193 0_0402_5%DIS@
DGPU_BKL_EN<23>
C C
B B
IGPU_BKLT_EN
+3VS
+3VS
R198 2.2K_0402_5%S G@R198 2.2K_0402_5%S G@
R200 2.2K_0402_5%S G@R200 2.2K_0402_5%S G@
R900 150_0402_1%SG@R900 150_0402 _1%SG@
R202 150_0402_1%SG@R202 150_0402 _1%SG@
R203 150_0402_1%SG@R203 150_0402 _1%SG@
R311 2.2K_0402_5%SG@R311 2 .2K_0402_5%SG@
1 2
R313 2.2K_0402_5%SG@R313 2 .2K_0402_5%SG@
1 2
R194 2.2K_0402_5%SG@R194 2 .2K_0402_5%SG@
1 2
R195 2.2K_0402_5%SG@R195 2 .2K_0402_5%SG@
1 2
R196 2.2K_0402_5%SG@R196 2 .2K_0402_5%SG@
1 2
R197 2.2K_0402_5%SG@R197 2 .2K_0402_5%SG@
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R905 0_0402_5%SG@R 905 0_0 402_5%SG@
1 2
PCH_HDMI_SCLK
PCH_HDMI_SDATA
PCH_CRT_CLK
PCH_CRT_DATA
PCH_CRT_B
PCH_CRT_G
PCH_CRT_R
ENBKLDGPU_BKL_EN
PCH_LCD_CLK
PCH_LCD_DATA
CTRL_CLK
CTRL_DATA
4
ENBKL <40>
3
U60D
12
R345
R345
0_0402_5%
0_0402_5%
AF37
AF36
AE48
AE47
AK39
AK40
AN48
AM47
AK47
AJ48
AN47
AM49
AK49
AJ47
AF40
AF39
AH45
AH47
AF49
AF45
AH43
AH49
AF47
AF43
M45
N48
M40
M47
M49
J47
P45
T40
K47
T45
P39
P49
T49
T39
T43
T42
U60D
L_BKLTEN
L_VDD_EN
L_BKLTCTL
L_DDC_CLK
L_DDC_DATA
L_CTRL_CLK
L_CTRL_DATA
LVD_IBG
LVD_VBG
LVD_VREFH
LVD_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN
COUGARPOINT_FCBGA989~D
COUGARPOINT_FCBGA989~D
LVDS
LVDS
CRT
CRT
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
SDVO_INTN
SDVO_INTP
SDVO_CTRLCLK
SDVO_CTRLDATA
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
Digital Display Interface
Digital Display Interface
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
SG@
SG@
2.37K_0402_1%
2.37K_0402_1%
SG@
SG@
0_0402_5%
0_0402_5%
1K_0402_0.5%
1K_0402_0.5%
IGPU_BKLT_EN
12
12
PCH_TXCLKPCH_TXCLK+
PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2-
PCH_TXOUT0+
PCH_TXOUT1+
PCH_TXOUT2+
PCH_TZCLKPCH_TZCLK+
PCH_TZOUT0PCH_TZOUT1PCH_TZOUT2-
PCH_TZOUT0+
PCH_TZOUT1+
PCH_TZOUT2+
PCH_CRT_B
PCH_CRT_G
PCH_CRT_R
PCH_CRT_CLK
PCH_CRT_DATA
PCH_CRT_HSYNC
PCH_CRT_VSYNC
R199
R199
CTRL_CLK
CTRL_DATA
LVDS_IBG
LVD_VREF
CRT_IREF
12
PCH_ENVDD<30>
DPST_PWM<30>
PCH_LCD_CLK<30>
PCH_LCD_DATA<30>
R886
R886
R192
R192
PCH_TXCLK-< 30>
PCH_TXCLK+<30>
PCH_TXOUT0-<30>
PCH_TXOUT1-<30>
PCH_TXOUT2-<30>
PCH_TXOUT0+<30>
PCH_TXOUT1+<30>
PCH_TXOUT2+<30>
PCH_TZCLK-<30>
PCH_TZCLK+<30>
PCH_TZOUT0-<30>
PCH_TZOUT1-<30>
PCH_TZOUT2-<30>
PCH_TZOUT0+<30>
PCH_TZOUT1+<30>
PCH_TZOUT2+<30>
PCH_CRT_B<31>
PCH_CRT_G<31>
PCH_CRT_R<31>
PCH_CRT_CLK<31>
PCH_CRT_DATA<31>
PCH_CRT_HSYNC<31>
PCH_CRT_VSYNC<31>
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
AP43
AP45
AM42
AM40
AP39
AP40
P38
M39
AT49
AT47
AT40
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
2
PCH_HDMI_SCLK
PCH_HDMI_SDATA
PCH_HDMI_SCLK < 32>
PCH_HDMI_SDATA <32>
PCH_HDMI_DET <32>
PCH_HDMI_TXD2-
PCH_HDMI_TXD2+
PCH_HDMI_TXD1-
PCH_HDMI_TXD1+
PCH_HDMI_TXD0-
PCH_HDMI_TXD0+
PCH_HDMI_TXC-
PCH_HDMI_TXC+
PCH_HDMI_TXD2- < 32>
PCH_HDMI_TXD2+ <32>
PCH_HDMI_TXD1- < 32>
PCH_HDMI_TXD1+ <32>
PCH_HDMI_TXD0- < 32>
PCH_HDMI_TXD0+ <32>
PCH_HDMI_TXC- <3 2>
PCH_HDMI_TXC+ <32>
1
A A
Security Classification
Security Classification
5
4
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/12/01 2010/12/31
2009/12/01 2010/12/31
2009/12/01 2010/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PCH (4/9) LVDS,CRT,DP,HDMI
PCH (4/9) LVDS,CRT,DP,HDMI
PCH (4/9) LVDS,CRT,DP,HDMI
LA-6931P
LA-6931P
LA-6931P
1
16 58Wednesday, October 27, 2010
16 58Wednesday, October 27, 2010
16 58Wednesday, October 27, 2010
1.0
1.0
1.0
5
www.bufanxiu.com
+3VS
R204
R204
PCI_PIRQA#
18
PCI_PIRQD#
27
PCI_PIRQC#
D D
R207 8.2K_0402_5%R207 8.2K_0402_5%
R208 8.2K_0402_5%@R208 8.2K_0402_5%@
R929 8.2K_0402_5%R929 8.2K_0402_5%
C C
R209 8.2K_0402_5%R209 8.2K_0402_5%
36
45
8.2K_0804_8P4R_5%
8.2K_0804_8P4R_5%
R205
R205
18
27
36
45
8.2K_0804_8P4R_5%
8.2K_0804_8P4R_5%
R206
R206
18
27
36
45
8.2K_0804_8P4R_5%
8.2K_0804_8P4R_5%
1 2
1 2
1 2
1 2
PCI_PIRQB#
BT_ON#
PCH_GPIO51
PCH_GPIO53
PCH_GPIO2
PCH_GPIO55
PCH_GPIO4
ODD_DA#
09/09
PCH_GPIO52
VGA_ON_R
DGPU_HOLD_RST#
Boot BIOS Strap bit1 BBS1
Boot BIOS
Bit10
1
1
0
Destination
Reserved
PCI
SPI
LPC
CLK_PCI_LPBACK<14>
CLK_PCI_LPC<40>
VGA_ON<23,46,54>
CLK_PCI_LPC
CLK_PCI_LPC_WLAN< 39>
Bit11
GNT1#/
GPIO51
0
110
0
B B
4
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
12
12
T27PAD T27PAD
T28PAD T28PAD
T29PAD T29PAD
DGPU_HOLD_RST#
PCH_GPIO52
VGA_ON_R
PCH_GPIO51
PCH_GPIO53
PCH_GPIO55
PCH_GPIO2
ODD_DA#
PCH_GPIO4
BT_ON#
PLT_RST#
R191
R191
0_0402_5%
0_0402_5%
ODD_DA#<33>
BT_ON#<44>
T26PAD T26PAD
PLT_RST#<5,34,37,39,40>
R889 22_0402_5%R889 22_0402_5%
R890 22_0402_5%R890 22_0402_5%
1 2
R908 22_0402_5%R908 22_0402_5%
1 2
CLK_PCI0
CLK_PCI1
CLK_PCI2
CLK_PCI3
CLK_PCI4
CLK_PCI1
U60E
U60E
BG26
TP1
BJ26
TP2
BH25
TP3
BJ16
TP4
BG16
TP5
AH38
TP6
AH37
TP7
AK43
TP8
AK45
TP9
C18
TP10
N30
TP11
H3
TP12
AH12
TP13
AM4
TP14
AM5
TP15
Y13
TP16
K24
TP17
L24
TP18
AB46
TP19
AB45
TP20
B21
TP21
M20
TP22
AY16
TP23
BG46
TP24
BE28
TP25
BC30
TP26
BE32
TP27
BJ32
TP28
BC28
TP29
BE30
TP30
BF32
TP31
BG32
TP32
AV26
TP33
BB26
TP34
AU28
TP35
AY30
TP36
AU26
TP37
AY26
TP38
AV28
TP39
AW30
TP40
K40
PIRQA#
K38
PIRQB#
H38
PIRQC#
G38
PIRQD#
C46
REQ1# / GPIO50
C44
REQ2# / GPIO52
E40
REQ3# / GPIO54
D47
GNT1# / GPIO51
E42
GNT2# / GPIO53
F46
GNT3# / GPIO55
G42
PIRQE# / GPIO2
G40
PIRQF# / GPIO3
C42
PIRQG# / GPIO4
D44
PIRQH# / GPIO5
K10
PME#
C6
PLTRST#
H49
CLKOUT_PCI0
H43
CLKOUT_PCI1
J48
CLKOUT_PCI2
K42
CLKOUT_PCI3
H40
CLKOUT_PCI4
COUGARPOINT_FCBGA989~D
COUGARPOINT_FCBGA989~D
RSVD
RSVD
PCI
PCI
3
NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NVRAM
NVRAM
NV_DQ11 / NV_IO11
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15
NV_RCOMP
NV_RE#_WRB0
NV_RE#_WRB1
NV_WE#_CK0
NV_WE#_CK1
USB
USB
USBRBIAS#
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3
NV_DQS0
NV_DQS1
NV_ALE
NV_CLE
NV_RB#
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS
AY7
AV7
AU3
BG4
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
NV_CLE
AY1
AV10
AT8
AY5
BA2
AT12
BF3
USB20_N0
C24
USB20_P0
A24
USB20_N1
C25
USB20_P1
B25
C26
A26
K28
H28
USB20_N4
E28
USB20_P4
D28
USB20_N5
C28
USB20_P5
A28
C29
B29
N28
PCH HM65 config not support USB port 6 & 7.
M28
L30
K30
USB20_N9
G30
USB20_P9
E30
USB20_N10
C30
USB20_P10
A30
USB20_N11
L32
USB20_P11
K32
USB20_N12
G32
USB20_P12
E32
USB20_N13
C32
USB20_P13
A32
USBRBIAS
C33
B33
USB_OC#1
A14
USB_OC#2
K20
PCH_GPIO41
B17
PCH_GPIO42
C16
PCH_GPIO43
L16
PCH_GPIO9
A16
PCH_GPIO10
D14
PCH_GPIO14
C14
USB20_N0 <43>
USB20_P0 <43>
USB20_N1 <36>
USB20_P1 <36>
USB20_N4 <39>
USB20_P4 <39>
USB20_N5 <39>
USB20_P5 <39>
USB20_N9 <36>
USB20_P9 <36>
USB20_N10 <30>
USB20_P10 <30>
USB20_N11 <44>
USB20_P11 <44>
USB20_N12 <37>
USB20_P12 <37>
USB20_N13 <43>
USB20_P13 <43>
Within 500 mils
1 2
R216 22.6_0402_1%R 216 22.6_0402_1%
USB_OC#1 <4 3>
USB_OC#2 <3 6>
2
USB/B
USB Conn.(HS) JUSB1
Mini Card(WLAN)
Mini Card(Mini2)
eSATA USB Conn.
CMOS Camera (LVDS)
Fingerprint
USB3.0 Conn reserve
Bluetooth
(For USB Port0)
(For USB Port1)
(For eSATA USB P ort)
DMI Termination Voltage
NV_CLE
8/31 Intel
NV_CLE
R211 1K_0402_5%R211 1K_0402_5%
CLOSE TO THE BRANCHING POINT
USB_OC#1
USB_OC#2
PCH_GPIO42
PCH_GPIO9
PCH_GPIO14
PCH_GPIO10
PCH_GPIO41
PCH_GPIO43
OC[0..3] use for EHCI 1
OC[4..7] use for EHCI 2
R314 10K_0402_5%R314 10K_0402_5%
R315 10K_0402_5%R315 10K_0402_5%
R887 10K_0402_5%R887 10K_0402_5%
R888 10K_0402_5%R888 10K_0402_5%
R214 10K_0402_5%R214 10K_0402_5%
R215 10K_0402_5%R215 10K_0402_5%
R287 10K_0402_5%R287 10K_0402_5%
R899 10K_0402_5%R899 10K_0402_5%
1
Set to Vcc when HIGH
Set to Vss when LOW
+1.8VS
12
R210
R210
2.2K_0402_5%
2.2K_0402_5%
12
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
H_SNB_IVB# <5>
+3VALW_PCH
R219
R219
0_0402_5%
0_0402_5%
R221 0_0402_5%@R221 0_0402_5%@
PLT_RST#
DGPU_HOLD_RST#
A A
NC7SZ08P5X_NL_SC70-5
NC7SZ08P5X_NL_SC70-5
12
+3VS
5
U7
U7
2
P
B
4
Y
1
A
G
3
5
100_0402_5%
100_0402_5%
1 2
12
100K_0402_5%
100K_0402_5%
R222
R222
R220
R220
PLTRST_VGA# <22>
PLT_RST#
SN74AHC1G08DCKR_SC70-5
SN74AHC1G08DCKR_SC70-5
4
1
2
12
+3VS
5
U8
@U8
@
P
IN1
4
O
IN2
G
3
PLT_RST_BUF# <38,39>
12
R223
R223
100K_0402_5%
100K_0402_5%
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/12/01 2010/12/31
2009/12/01 2010/12/31
2009/12/01 2010/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Title
Title
Title
PCH (5/9) PCI, USB, NVRAM
PCH (5/9) PCI, USB, NVRAM
PCH (5/9) PCI, USB, NVRAM
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
LA-6931P
LA-6931P
LA-6931P
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
17 58Wednesday, October 27, 2010
17 58Wednesday, October 27, 2010
17 58Wednesday, October 27, 2010
1.0
1.0
1.0
5
www.bufanxiu.com
D D
GPIO28
On-Die PLL Voltage Regulator
This signal has a weak internal pull up
：
On-Die voltage r egulator enable
H
*
L：On-Die PLL Volta ge Regulator di sable
R891 1K_0402_5%@R891 1K_0402_5%@
1 2
PCH_GPIO28
CRT_DET#<31>
4
2
G
G
+3VS
R225
R225
10K_0402_5%
10K_0402_5%
1 2
CRT_DET
13
D
D
@
@
Q14
Q14
2N7002H_SOT23-3
2N7002H_SOT23-3
S
S
High: CRT Plugged
3
2
PCH_GPIO68
PCH_GPIO69
PCH_GPIO70
PCH_GPIO71
1
R909 10K_0402_5%R909 10K_0402_5%
1 2
R910 10K_0402_5%R910 10K_0402_5%
1 2
R911 10K_0402_5%R911 10K_0402_5%
1 2
R912 10K_0402_5%R912 10K_0402_5%
1 2
+3VS
+3VS
PCH_GPIO27 (Have internal Pull-High)
High: VCCVRM VR Enable
*
Low: VCCVRM VR Disable
R228 10K_0402_5%@R228 10K_0402_5%@
1 2
PCH_GPIO37
C C
+3VS
R230 1K_0402_5%@R230 1K_0402_5%@
1 2
R232 100K_0402_5%R 232 100K_0402_5%
1 2
+3VS
R235 10K_0402_5%R235 10K_0402_5%
1 2
R894 10K_0402_5%R894 10K_0402_5%
1 2
R895 10K_0402_5%R895 10K_0402_5%
1 2
R238 10K_0402_5%R238 10K_0402_5%
1 2
R239 10K_0402_5%R239 10K_0402_5%
1 2
R240 10K_0402_5%R240 10K_0402_5%
1 2
R241 10K_0402_5%R241 10K_0402_5%
1 2
B B
R896 200K_0402_5%R 896 200K_0402_5%
1 2
R243 10K_0402_5%R243 10K_0402_5%
1 2
R244 10K_0402_5%R244 10K_0402_5%
1 2
R245 10K_0402_5%R245 10K_0402_5%
1 2
+3VALW_PCH
R246 10K_0402_5%R246 10K_0402_5%
1 2
R247 1K_0402_5%R247 1K_0402_5%
1 2
R897 10K_0402_5%R897 10K_0402_5%
1 2
R907 10K_0402_5%R907 10K_0402_5%
1 2
PCH_GPIO27
PCH_GPIO37
PCH_GPIO1
DGPU_HPD_INT#
PCH_GPIO16
DGPU_PWROK
PCH_GPIO22
PCH_GPIO38
PCH_GPIO39
ODD_DETECT#
PCH_GPIO34
PCH_GPIO48
PCH_GPIO49
PCH_GPIO12
SMIB_D
PCH_GPIO57
ODD_EN
EC_SCI#<40>
EC_SMI#<40>
SMIB<37>
R233 0_0402_5%R 233 0_ 0402_5%
ODD_EN<33>
ODD_DETECT#<33>
R920 0_0402_5%@R920 0_0402_5%@
1 2
1 2
VGA_PWROK<22,27,55>
COLOR_ENG_EN<30>
9/22
10/26
R931 10K_0402_5%@R931 10K_0402_5%@
1 2
R249 10K_0402_5%@R249 10K_0402_5%@
1 2
A A
R928 0_0402_5%R928 0_0402_5%
1 2
D12
@D12
@
CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
ODD_DETECT#
PCH_GPIO35
SMIBSMIB_D
21
CRT_DET
PCH_GPIO1
DGPU_HPD_INT#
EC_SCI#
EC_SMI#
PCH_GPIO12
SMIB
PCH_GPIO16
DGPU_PWROK
PCH_GPIO22
ODD_EN
PCH_GPIO27
PCH_GPIO28
PCH_GPIO34
PCH_GPIO35
ODD_DETECT#
PCH_GPIO37
PCH_GPIO38
PCH_GPIO39
PCH_GPIO48
PCH_GPIO49
PCH_GPIO57
T53PAD T53PAD
T55PAD T55PAD
T57PAD T57PAD
T59PAD T59PAD
T60PAD T60PAD
T62PAD T62PAD
9/06
5
4
U60F
U60F
T7
BMBUSY# / GPIO0
A42
TACH1 / GPIO1
H36
TACH2 / GPIO6
E38
TACH3 / GPIO7
C10
GPIO8
C4
LAN_PHY_PWR_CTRL / GPIO12
G2
GPIO15
U2
SATA4GP / GPIO16
D40
TACH0 / GPIO17
T5
SCLOCK / GPIO22
E8
GPIO24 / MEM_LED
E16
GPIO27
P8
GPIO28
K1
STP_PCI# / GPIO34
K4
GPIO35
V8
SATA2GP / GPIO36
M5
SATA3GP / GPIO37
N2
SLOAD / GPIO38
M3
SDATAOUT0 / GPIO39
V13
SDATAOUT1 / GPIO48
V3
SATA5GP / GPIO49
D6
GPIO57
A4
VSS_NCTF_1
A44
VSS_NCTF_2
A45
VSS_NCTF_3
A46
VSS_NCTF_4
A5
VSS_NCTF_5
A6
VSS_NCTF_6
B3
VSS_NCTF_7
B47
VSS_NCTF_8
BD1
VSS_NCTF_9
BD49
VSS_NCTF_10
BE1
VSS_NCTF_11
BE49
VSS_NCTF_12
BF1
VSS_NCTF_13
BF49
VSS_NCTF_14
COUGARPOINT_FCBGA989~D
COUGARPOINT_FCBGA989~D
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
TACH4 / GPIO68
TACH5 / GPIO69
TACH6 / GPIO70
TACH7 / GPIO71
A20GATE
RCIN#
PROCPWRGD
GPIO
GPIO
THRMTRIP#
CPU/MISC
CPU/MISC
INIT3_3V#
NC_1
NC_2
NC_3
NC_4
NC_5
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
NCTF
NCTF
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32
2009/12/01 2010/12/31
2009/12/01 2010/12/31
2009/12/01 2010/12/31
PCH_GPIO68
C40
PCH_GPIO69
B41
PCH_GPIO70
C41
PCH_GPIO71
A40
P4
PCH_PECI_R
AU16
PECI
EC_KBRST#
P5
AY11
PCH_THRMTRIP#_R
AY10
T14
AH8
AK11
AH10
AK10
P37
BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
T34 PADT34 PAD
T35 PADT35 PAD
T36 PADT36 PAD
T37 PADT37 PAD
T41 PADT41 PAD
T43 PADT43 PAD
T45 PADT45 PAD
@
1 2
R8930_0402_5%@R8930_0402_5%
1 2
R234 390_0402_5%R234 390_0402_5%
INIT3_3V
This signal has weak internal
PU, can't pull low
Intel schematic reviwe recommand.
2
H_PECI <5,40>
EC_KBRST# <40>
H_CPUPWRGD <5>
H_THRMTRIP#
+3VS
1 2
R229
R229
10K_0402_5%
10K_0402_5%
EC_KBRST#
GATEA20 <40>
H_THRMTRIP# <5>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (6/9) GPIO, CPU, MISC
PCH (6/9) GPIO, CPU, MISC
PCH (6/9) GPIO, CPU, MISC
LA-6931P
LA-6931P
LA-6931P
R892 10K_0402_5%R892 10K_0402_5%
1 2
of
18 58Wednesday, October 27, 2010
18 58Wednesday, October 27, 2010
1
18 58Wednesday, October 27, 2010
1.0
1.0
1.0
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