Compal LA-6921P PILP1, ThinkPad Edge E420s Schematic

Compal Confidential

1 1

Model Name :PILP1 File Name : LA-6921P

2 2

Compal Confidential

LA-6921 Edge Schematics Document

Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH + Whistler 128bit with BACO

2010-11-30

3 3

REV:1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

2012/08/252010/08/25

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

SCHEMATICS,MB A6921

4019A1

Thursday, January 20, 2011

Compal Confidential

Model Name :PILP1 File Name : LA-6921P

1 1

VRAM 128*16

AMD Whistler

PCI-E X16 DDR3*8 Page 26~27

Page 21~28

Intel

Sandy Bridge

BGA1023

31mm*24mm

Dual Channel

DDR3-1333(1.5V)

DDR3-SO-DIMM X2

Page 10~11

HDMI Connector

HDMI

Page 4~9

Page31

FDI

DMI

2Channel Speaker

Page 35

CRT Connector

Page30

2 2

LVDS Connector

Page 29

Card Reader

JBM 389

RGB

LVDS

PCI-E

Intel Cougar Point

FCBGA 989

USB2.0

HDA

Audio Codec

CX20671 CODEC

Page 35

CMOS Camera

Digital MIC

Page 29

Audio combo Jack

Page 36

Page 29

25mm*25mm

Page43

HM65

Page 12~20

SATA

BlueTooth CONN

Page 40

Realtek

RTL8111E(Giga)

Page 33

3 3

RJ45 CONN

Page 34

Track Point

PCI Express Mini card

WLAN/WiMAX

Slot 1

Page 32

USB(WiMAX) PCI-E(WLAN)

SPI ROM BIOS 4M

Page 12

Page 41

G-Sensor

Page 38

Touch Pad

ENE KBC930

Page 41

LPC BUS

Page 37

LED Page 29,43

Int.KBD

Page 41

SPI ROM 128K

Page 39

USB PORT 2.0 x2

Finger Printer

Page 40

Page 43

eSATA and USB CONN

SATA3.0 HDD CONN

SATA ODD CONN

Page 40

Page 42

4 4

PCI Express Mini card

WWAN/mSATA

Slot 2

SIM Card

Page 32

USB

SATA

Fintek 75303

Page 38

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

2012/08/252010/08/25

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

SCHEMATICS,MB A6921

4019A1

SCHEMATICS,MB A6921

Thursday, January 20, 2011

542

BCustom

Thermal Sensor

Voltage Rails

3.3V +/- 5%

BOARD ID Table

+5VS

power plane

1 1

+5VALW

+3VALW

+1.5V

State

S5 S4/AC

S5 S4/ Battery only

2 2

S5 S4/AC & Battery don't exist

STATE

SIGNAL

Full ON

S3 (Suspend to RAM)

O O O

SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS

HIGH HIGH HIGH

LOW

S4 (Suspend to Disk)

S5 (Soft OFF)

O O

XX X

ON ON

HIGH

LOWLOW

HIGH

ONONOFF

OFF

OFFLOW LOW LOW

+3VS +1.8VS +1.5VS +1.05VS +VGFX_CORE +CPU_CORE

+0.75VS +1.5VS_DISVGA +1.0VS +NVVDD +3VS_DISVGA +1.8VS_DISVGA

OFF

Board ID

0 1 2 3 4 5 6 7

PCB Revision

USB Port Table

USB 2.0 USB 1.1 Port

0 1 2 3 4 5 6 7 8

9 10 11 12 13

EHCI1

EHCI2

UHCI0

UHCI1

UHCI2

UHCI3

UHCI4

UHCI5

UHCI6

BOM Structure Table

Structure Function CPU1@ PX@ UMA@ 3G@ X76H1G@ PCB@

CPU type PX4.0 SKU UMA SKU 3G Sim card VRAM M/B

0.1

0.2

0.3

3 External USB Port

USB_COMBO USB_PORT NO USE NO USE WWAN CAMERA HM65 not support HM65 not support WLAN USB_CHARGER NO USE NO USE FINGER-PRINTER BLUETOOTH

i3-2310M 2.1G Q1RK

Vcc

100K +/- 5%

R613

Board ID

0K +/- 5%

8.2K +/- 5%

18K +/- 5%

33K +/- 5%

3 4

56K +/- 5% 1.036 V 1.185 V 1.264 V

PCH_GPIO69 PCH_GPIO70 PCH_GPIO71

0 1

ZZZ2

X76H2G@

HYNIX_2G

X7626039L01

UCPU1

CPU3@

i5-2410M 2.3G Q1R9

SA00004KT00

UCPU1

CPU2@

CPU2@ SA00004KP00

SA00004KP00

ZZZ1

PCB@

LA-6921P

DA80000L700

VR682

0.436 V

0.712 V

0 1

ZZZ3

X76S2G@

SAMSUNG_2G

X7626039L02

CPU4@

i5-2520M 2.5G Q1RA

SA00004EL20

AD_BID

0 V

UCPU1

0 0

min

0.503 V

0.819 V

Function

PX4.0

ZZZ4

X76H1G@

HYNIX_1G

X7626039L03

i5-2540M 2.6G Q1R7

AD_BID

UMA

X76S1G@

SAMSUNG_1G

X7626039L04

UCPU1

CPU5@

CPU5@ SA00004EM20

SA00004EM20

ZZZ5

typ

AD_BID

0 V0 V

0.289 V0.250 V0.216 V

0.538 V

0.875 V

CPU6@

i7-2620M 2.7G Q1R3

SA00004F010

UCPU1

max

SDV1 SDV2 FVT SIT SVT

3 3

EC SM Bus1 address

Device

Smart Battery 0001 011X b

4 4

Address Address

EC SM Bus2 address

Device

PCH 1001 0110 b Thermal sensor(U30) 1001 101x b GPU(U9) 1000_0010 b

PCH SM Bus address

Device Address

DDR DIMM0 DDR DIMM2

EEPROM(U32) 1010 100xb

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1010 000xb 1010 010xb

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

2012/08/252010/08/25

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

SCHEMATICS,MB A6921

4019A1

Thursday, January 20, 2011

354

UCPU1A

D D

DMI_CRX_PTX_N0(14) DMI_CRX_PTX_N1(14) DMI_CRX_PTX_N2(14) DMI_CRX_PTX_N3(14)

DMI_CRX_PTX_P0(14) DMI_CRX_PTX_P1(14) DMI_CRX_PTX_P2(14) DMI_CRX_PTX_P3(14)

DMI_CTX_PRX_N0(14) DMI_CTX_PRX_N1(14) DMI_CTX_PRX_N2(14) DMI_CTX_PRX_N3(14)

DMI_CTX_PRX_P0(14) DMI_CTX_PRX_P1(14) DMI_CTX_PRX_P2(14) DMI_CTX_PRX_P3(14)

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_FSYNC0 FDI_FSYNC1

FDI_INT FDI_LSYNC0

FDI_LSYNC1

+EDP_COM

FDI_CTX_PRX_N0(14) FDI_CTX_PRX_N1(14) FDI_CTX_PRX_N2(14) FDI_CTX_PRX_N3(14) FDI_CTX_PRX_N4(14) FDI_CTX_PRX_N5(14)

C C

B B

FDI_CTX_PRX_N6(14) FDI_CTX_PRX_N7(14)

FDI_CTX_PRX_P0(14) FDI_CTX_PRX_P1(14) FDI_CTX_PRX_P2(14) FDI_CTX_PRX_P3(14) FDI_CTX_PRX_P4(14) FDI_CTX_PRX_P5(14) FDI_CTX_PRX_P6(14) FDI_CTX_PRX_P7(14)

FDI_FSYNC0(14) FDI_FSYNC1(14)

FDI_INT(14) FDI_LSYNC0(14)

FDI_LSYNC1(14)

+1.05VS

1 2

R7 24.9_0402_1%R7 24.9_0402_1%

R19 1K_0402_5%

UCPU1A

DMI_RX#[0]

DMI_RX#[1]

DMI_RX#[2]

P10

DMI_RX#[3]

DMI_RX[0]

DMI_RX[1]

DMI_RX[2]

P11

DMI_RX[3]

DMI_TX#[0]

DMI_TX#[1]

DMI_TX#[2]

DMI_TX#[3]

DMI_TX[0]

DMI_TX[1]

DMI_TX[2]

DMI_TX[3]

FDI0_TX#[0]

W11

FDI0_TX#[1]

FDI0_TX#[2]

AA6

FDI0_TX#[3]

FDI1_TX#[0]

FDI1_TX#[1]

FDI1_TX#[2]

AC9

FDI1_TX#[3]

FDI0_TX[0]

W10

FDI0_TX[1]

FDI0_TX[2]

AA7

FDI0_TX[3]

FDI1_TX[0]

FDI1_TX[1]

AA3

FDI1_TX[2]

AC8

FDI1_TX[3]

AA11

FDI0_FSYNC

AC12

FDI1_FSYNC

U11

FDI_INT

AA10

FDI0_LSYNC

AG8

FDI1_LSYNC

AF3

eDP_COMPIO

AD2

eDP_ICOMPO

AG11

eDP_HPD

AG4

eDP_AUX#

AF4

eDP_AUX

AC3

eDP_TX#[0]

AC4

eDP_TX#[1]

AE11

eDP_TX#[2]

AE7

eDP_TX#[3]

AC1

eDP_TX[0]

AA4

eDP_TX[1]

AE10

eDP_TX[2]

AE6

eDP_TX[3]

SANDY-BRIDGE_BGA1023~D

SANDY-BRIDGE_BGA1023~D CPU1@

CPU1@

DMI Intel(R) FDI DP

+1.05VS

PEG_COMP

PCIE_CRX_GTX_N15 PCIE_CRX_GTX_N14 PCIE_CRX_GTX_N13 PCIE_CRX_GTX_N12 PCIE_CRX_GTX_N11 PCIE_CRX_GTX_N10 PCIE_CRX_GTX_N9 PCIE_CRX_GTX_N8 PCIE_CRX_GTX_N7 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_N0

PCIE_CRX_GTX_P15 PCIE_CRX_GTX_P14 PCIE_CRX_GTX_P13 PCIE_CRX_GTX_P12 PCIE_CRX_GTX_P11 PCIE_CRX_GTX_P10 PCIE_CRX_GTX_P9 PCIE_CRX_GTX_P8 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_P0

PCIE_CTX_GRX_C_N15 PCIE_CTX_GRX_C_N14 PCIE_CTX_GRX_C_N13 PCIE_CTX_GRX_C_N12 PCIE_CTX_GRX_C_N11 PCIE_CTX_GRX_C_N10 PCIE_CTX_GRX_C_N9 PCIE_CTX_GRX_C_N8 PCIE_CTX_GRX_C_N7 PCIE_CTX_GRX_C_N6 PCIE_CTX_GRX_C_N5 PCIE_CTX_GRX_C_N4 PCIE_CTX_GRX_C_N3 PCIE_CTX_GRX_C_N2 PCIE_CTX_GRX_C_N1 PCIE_CTX_GRX_C_N0

PCIE_CTX_GRX_C_P15 PCIE_CTX_GRX_C_P14 PCIE_CTX_GRX_C_P13 PCIE_CTX_GRX_C_P12 PCIE_CTX_GRX_C_P11 PCIE_CTX_GRX_C_P10 PCIE_CTX_GRX_C_P9 PCIE_CTX_GRX_C_P8 PCIE_CTX_GRX_C_P7 PCIE_CTX_GRX_C_P6 PCIE_CTX_GRX_C_P5 PCIE_CTX_GRX_C_P4 PCIE_CTX_GRX_C_P3 PCIE_CTX_GRX_C_P2 PCIE_CTX_GRX_C_P1 PCIE_CTX_GRX_C_P0

C1 0.1U_0402_10V6K

C1 0.1U_0402_10V6K C2 0.1U_0402_10V6K

C2 0.1U_0402_10V6K C3 0.1U_0402_10V6K

C3 0.1U_0402_10V6K C4 0.1U_0402_10V6K

C4 0.1U_0402_10V6K C5 0.1U_0402_10V6K

C5 0.1U_0402_10V6K C6 0.1U_0402_10V6K

C6 0.1U_0402_10V6K C7 0.1U_0402_10V6K

C7 0.1U_0402_10V6K C8 0.1U_0402_10V6K

C8 0.1U_0402_10V6K C9 0.1U_0402_10V6K

C9 0.1U_0402_10V6K C10 0.1U_0402_10V6K

C10 0.1U_0402_10V6K C11 0.1U_0402_10V6K

C11 0.1U_0402_10V6K C12 0.1U_0402_10V6K

C12 0.1U_0402_10V6K C13 0.1U_0402_10V6K

C13 0.1U_0402_10V6K C14 0.1U_0402_10V6K

C14 0.1U_0402_10V6K C15 0.1U_0402_10V6K

C15 0.1U_0402_10V6K C16 0.1U_0402_10V6K

C16 0.1U_0402_10V6K C17 0.1U_0402_10V6K

C17 0.1U_0402_10V6K C18 0.1U_0402_10V6K

C18 0.1U_0402_10V6K C19 0.1U_0402_10V6K

C19 0.1U_0402_10V6K C20 0.1U_0402_10V6K

C20 0.1U_0402_10V6K C21 0.1U_0402_10V6K

C21 0.1U_0402_10V6K C22 0.1U_0402_10V6K

C22 0.1U_0402_10V6K C23 0.1U_0402_10V6K

C23 0.1U_0402_10V6K C24 0.1U_0402_10V6K

C24 0.1U_0402_10V6K C25 0.1U_0402_10V6K

C25 0.1U_0402_10V6K C26 0.1U_0402_10V6K

C26 0.1U_0402_10V6K C27 0.1U_0402_10V6K

C27 0.1U_0402_10V6K C28 0.1U_0402_10V6K

C28 0.1U_0402_10V6K C29 0.1U_0402_10V6K

C29 0.1U_0402_10V6K C30 0.1U_0402_10V6K

C30 0.1U_0402_10V6K C31 0.1U_0402_10V6K

C31 0.1U_0402_10V6K C32 0.1U_0402_10V6K

C32 0.1U_0402_10V6K

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

G3 G1 G4

H22 J21 B22 D21 A19 D17 B14 D13 A11 B10 G8 A8 B6 H8 E5 K7

K22 K19 C21 D19 C19 D16 C13 D12 C11 C9 F8 C8 C5 H6 F6 K6

G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4

F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PCI EXPRESS -- GRAPHICS

PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PEG_ICOMPI and RCOMPO signals should be shorted and routed

24.9_0402_1%

with - max length = 500 mils - typical impedance = 43 mohms PEG_ICOMPO signals should be routed with - max length = 500 mils

- typical impedance = 14.5 mohms

PCIE_CRX_GTX_N[0..15] (21)

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2

PCIE_CRX_GTX_P[0..15] (21)

12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

PX@

PX@ PX@

PX@

PX@ PX@

PX@

PCIE_CTX_GRX_N15 PCIE_CTX_GRX_N14 PCIE_CTX_GRX_N13 PCIE_CTX_GRX_N12 PCIE_CTX_GRX_N11 PCIE_CTX_GRX_N10

PCIE_CTX_GRX_N9 PCIE_CTX_GRX_N8 PCIE_CTX_GRX_N7 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_N0

PCIE_CTX_GRX_P15 PCIE_CTX_GRX_P14 PCIE_CTX_GRX_P13 PCIE_CTX_GRX_P12 PCIE_CTX_GRX_P11 PCIE_CTX_GRX_P10

PCIE_CTX_GRX_P9 PCIE_CTX_GRX_P8 PCIE_CTX_GRX_P7 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_P0

PCIE_CTX_GRX_N[0..15] (21)

PCIE_CTX_GRX_P[0..15] (21)

UCPU1I

BG17

VSS[181]

BG21

VSS[182]

BG24

VSS[183]

BG28

VSS[184]

BG37

VSS[185]

BG41

VSS[186]

BG45

VSS[187]

BG49

VSS[188]

BG53

VSS[189]

BG9

VSS[190]

C29

VSS[191]

C35

VSS[192]

C40

VSS[193]

D10

VSS[194]

D14

VSS[195]

D18

VSS[196]

D22

VSS[197]

D26

VSS[198]

D29

VSS[199]

D35

VSS[200]

VSS[201]

D40

VSS[202]

D43

VSS[203]

D46

VSS[204]

D50

VSS[205]

D54

VSS[206]

D58

VSS[207]

VSS[208]

E25

VSS[209]

E29

VSS[210]

VSS[211]

E35

VSS[212]

E40

VSS[213]

F13

VSS[214]

F15

VSS[215]

F19

VSS[216]

F29

VSS[217]

F35

VSS[218]

F40

VSS[219]

F55

VSS[220]

G48

VSS[221]

G51

VSS[222]

VSS[223]

G61

VSS[224]

H10

VSS[225]

H14

VSS[226]

H17

VSS[227]

H21

VSS[228]

VSS[229]

H53

VSS[230]

H58

VSS[231]

VSS[232]

J49

VSS[233]

J55

VSS[234]

K11

VSS[235]

K21

VSS[236]

K51

VSS[237]

VSS[238]

L16

VSS[239]

L20

VSS[240]

L22

VSS[241]

L26

VSS[242]

L30

VSS[243]

L34

VSS[244]

L38

VSS[245]

L43

VSS[246]

L48

VSS[247]

L61

VSS[248]

M11

VSS[249]

M15

VSS[250]

SANDY-BRIDGE_BGA1023~D

SANDY-BRIDGE_BGA1023~D CPU1@

CPU1@

VSS

VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301]

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9

VSS_NCTF_10

NCTF

VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14

M4 M58 M6 N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61 P14 P16 P18 P21 P58 P59 P9 R17 R20 R4 R46 T1 T47 T50 T51 T52 T53 T55 T56 U13 U8 V20 V61 W13 W15 W18 W21 W46 W8 Y4 Y47 Y58 Y59

A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

2012/08/252010/08/25

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

SCHEMATICS,MB A6921

SCHEMATICS,MB A6921 4019A1

4019A1

Thursday, January 20, 2011

PROC_DETECT (Processor Detect): pulled to ground on the processor package. There is no connection to the processor silicon for this signal. System board designers may use this

D D

H_CPUPWRGD(17)

C C

B B

PM_DRAM_PWRGD(14)

signal to determine if the processor is present

H_PROCHOT#(37)

11/24

C33

0.1U_0402_16V4Z

+3VS

R31

10K_0402_5%

1 2

+3VALW

SUSP(9,44,51)

+1.05VS

R13

62_0402_5%

1 2

H_CPUPWRGD_R

R28

R28 10K_0402_5%

10K_0402_5%

1 2

PM_SYS_PWRGD_BUF

74AHC1G09GW_TSSOP5

SUSP

R11

H_PECI(17,37) H_DRAMRST# (6)

H_THRMTRIP#(17)

H_PM_SYNC(14)

VDDPWRGOOD

+1.5V_CPU_VDDQ

R33@

R33@ 39_0402_5%

39_0402_5%

Q3 2N7002_SOT23

2N7002_SOT23

H_SNB_IVB#(16)

R30

R30 200_0402_5%

200_0402_5%

10K_0402_5%R11

10K_0402_5%

T1 @PAD~D T1 @PAD~D

R15

1 2

56_0402_5%

R29

1 2

130_0402_1%

UCPU1B

MISC THERMAL PWR MANAGEMENT

F49

PROC_SELECT#

C57

PROC_DETECT#

H_CATERR#

R14

1 2

0_0402_5%

H_PROCHOT#_R

H_THERMTRIP#

11/24

H_PM_SYNC_R

VDDPWRGOOD_R XDP_BPM#0

BUF_CPU_RST#

C49

CATERR#

A48

PECI

C45

PROCHOT#

D45

THERMTRIP#

C48

PM_SYNC

B46

UNCOREPWRGOOD

BE45

SM_DRAMPWROK

D44

RESET#

SANDY-BRIDGE_BGA1023~D

SANDY-BRIDGE_BGA1023~D CPU1@

CPU1@

MISC THERMAL PWR MANAGEMENT

CLOCKS

DDR3

MISC

DDR3

MISC

JTAG & BPM

BCLK

BCLK#

DPLL_REF_CLK

DPLL_REF_CLK#

BCLK_ITP

BCLK_ITP#

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PRDY# PREQ#

TRST#

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

TCK TMS

TDO

TDI

Buffered reset to CPU

+3VS

BUF_CPU_RST#

0.1U_0402_16V4Z

+1.05VS

0.1U_0402_16V4Z

R32

75_0402_5%

R34

43_0402_5%

1 2

C38

C38 @

BUFO_CPU_RST#

SN74LVC1G07DCKR_SC70-5

C34

PLT_RST#

CLK_CPU_DMI_R

CLK_CPU_DMI#_R

R9 1K_0402_5%R9 1K_0402_5%

AG3

R10 1K_0402_5%R10 1K_0402_5%

AG1

N59 N58

H_DRAMRST#H_PECI_ISO

AT30

SM_RCOMP0

BF44

SM_RCOMP1

BE43

SM_RCOMP2

BG43

12 12

DDR3 Compensation Signals

XDP_PRDY#

N53

XDP_PREQ#

N55

XDP_TCK

L56

XDP_TMS

L55

XDP_TRST#

J58

XDP_TDI

M60

XDP_TDO

L59

K58

G58

XDP_BPM#1

E55

XDP_BPM#2

E59

XDP_BPM#3

G55

XDP_BPM#4

G59

XDP_BPM#5

H60

XDP_BPM#6

J59

XDP_BPM#7

J61

+3VS

PLT_RST# (16,21)

1 2 1 2 1 2

R27

R27 1K_0402_5%

1K_0402_5%

XDP_DBRESET#

R833_0402_5% R833_0402_5%

R1233_0402_5% R1233_0402_5%

R16140_0402_1% R16140_0402_1% R1725.5_0402_1% R1725.5_0402_1% R18200_0402_1% R18200_0402_1%

1 2 1 2

+1.05VS

XDP_DBRESET# (12,14)

H_CPUPWRGD(17)

PBTN_OUT#(12,14,37)

+1.05VS

PLT_RST#(16,21)

CLK_CPU_DMI (13) CLK_CPU_DMI# (13)

XDP_CFG0(7) SYS_PWROK(14) CLK_XDP_CLK(13) CLK_XDP_CLK#(13)

XDP_TDO XDP_TRST# XDP_TDI XDP_TMS

XDP_TCK

PU/PD for JTAG signals

XDP_TMS

R20 51_0402_5%R20 51_0402_5%

XDP_TDI

R21 51_0402_5%R21 51_0402_5%

XDP_TDO

R22 51_0402_5%R22 51_0402_5%

XDP_TCK

R24 51_0402_5%R24 51_0402_5%

XDP_TRST#

R25 51_0402_5%R25 51_0402_5%

XDP_PREQ# XDP_PRDY#

H_CPUPWRGD

R52 1K_0402_1%

1 2

R531 0_0402_5%

1 2

R54 1K_0402_1%

1 2

R284 0_0402_5%

1 2

R285 0_0402_5%

1 2

R286 0_0402_5%

PLT_RST# XDP_DBRESET#

1 2

R55 1K_0402_1%

1 2

12 12 12

12 12

CLK_XDP_CLK_R CLK_XDP_CLK#_R

+1.05VS

JDB1

ACES_88717-2601

ME@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/25 2012/08/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

SCHEMATICS,MB A6921

SCHEMATICS,MB A6921 4019A1

4019A1

5Thursday, January 20, 2011

UCPU1C

DDR_A_D[0..63](10)

D D

C C

B B

DDR_A_BS0(10) DDR_A_BS1(10) DDR_A_BS2(10)

DDR_A_CAS#(10) DDR_A_RAS#(10) DDR_A_WE#(10)

H_DRAMRST#(5)

A A

DRAMRST_CNTRL_PCH(13)

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

H_DRAMRST#

AG6

AJ6

AP11

AL6

AJ10

AJ8 AL8 AL7

AR11

AP6 AU6 AV9 AR6

AP8 AT13 AU13

BC7

BB7 BA13 BB11

BA7

BA9

BB9 AY13 AV14 AR14 AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43

AW48

BC48 BC45 AR45 AT48 AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56

BD37 BF36 BA28

BE39 BD39 AT41

4.99K_0402_1%

11/24

DRAMRST_CNTRL

UCPU1C

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

SANDY-BRIDGE_BGA1023~D

SANDY-BRIDGE_BGA1023~D CPU1@

CPU1@

R36@

0_0402_5%

1 2

R39

1 2

BSS138_NL_SOT23-3

C35

0.047U_0402_16V4Z

SA_CLK#[0]

SA_CLK#[1]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

DDR SYSTEM MEMORY A

1K_0402_5%

DDR3_DRAMRST#_R

SA_CLK[0]

SA_CKE[0]

SA_CLK[1]

SA_CKE[1]

SA_CS#[0] SA_CS#[1]

SA_ODT[0] SA_ODT[1]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

+1.5V

R37

AU36 AV36 AY26

AT40 AU40 BB26

BB40 BC41

AY40 BA41

AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55

AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54

BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26

1 2

M_CLK_DDR0 M_CLK_DDR#0 DDR_CKE0_DIMMA

M_CLK_DDR1 M_CLK_DDR#1 DDR_CKE1_DIMMA

DDR_CS0_DIMMA# DDR_CS1_DIMMA#

M_ODT0 M_ODT1

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

R38

R38 1K_0402_5%

1K_0402_5%

M_CLK_DDR0 (10) M_CLK_DDR#0 (10) DDR_CKE0_DIMMA (10) M_CLK_DDR2 (11)

M_CLK_DDR1 (10) M_CLK_DDR#1 (10) DDR_CKE1_DIMMA (10)

DDR_CS0_DIMMA# (10) DDR_CS1_DIMMA# (10)

M_ODT0 (10) M_ODT1 (10)

DDR_A_DQS#[0..7] (10)

DDR_A_DQS[0..7] (10)

DDR_A_MA[0..15] (10)

DDR3_DRAMRST# (10,11)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR_B_D[0..63](11)

DDR_B_BS0(11) DDR_B_BS1(11) DDR_B_BS2(11)

DDR_B_CAS#(11) DDR_B_RAS#(11) DDR_B_WE#(11)

2010/08/25 2012/08/25

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

Compal Secret Data

AW59 AW58

AM60

Deciphered Date

UCPU1D

AL4

SB_DQ[0]

AL1

SB_DQ[1]

AN3

SB_DQ[2]

AR4

SB_DQ[3]

AK4

SB_DQ[4]

AK3

SB_DQ[5]

AN4

SB_DQ[6]

AR1

SB_DQ[7]

AU4

SB_DQ[8]

AT2

SB_DQ[9]

AV4

SB_DQ[10]

BA4

SB_DQ[11]

AU3

SB_DQ[12]

AR3

SB_DQ[13]

AY2

SB_DQ[14]

BA3

SB_DQ[15]

BE9

SB_DQ[16]

BD9

SB_DQ[17]

BD13

SB_DQ[18]

BF12

SB_DQ[19]

BF8

SB_DQ[20]

BD10

SB_DQ[21]

BD14

SB_DQ[22]

BE13

SB_DQ[23]

BF16

SB_DQ[24]

BE17

SB_DQ[25]

BE18

SB_DQ[26]

BE21

SB_DQ[27]

BE14

SB_DQ[28]

BG14

SB_DQ[29]

BG18

SB_DQ[30]

BF19

SB_DQ[31]

BD50

SB_DQ[32]

BF48

SB_DQ[33]

BD53

SB_DQ[34]

BF52

SB_DQ[35]

BD49

SB_DQ[36]

BE49

SB_DQ[37]

BD54

SB_DQ[38]

BE53

SB_DQ[39]

BF56

SB_DQ[40]

BE57

SB_DQ[41]

BC59

SB_DQ[42]

AY60

SB_DQ[43]

BE54

SB_DQ[44]

BG54

SB_DQ[45]

BA58

SB_DQ[46] SB_DQ[47] SB_DQ[48]

AU58

SB_DQ[49]

AN61

SB_DQ[50]

AN59

SB_DQ[51]

AU59

SB_DQ[52]

AU61

SB_DQ[53]

AN58

SB_DQ[54]

AR58

SB_DQ[55]

AK58

SB_DQ[56]

AL58

SB_DQ[57]

AG58

SB_DQ[58]

AG59

SB_DQ[59] SB_DQ[60]

AL59

SB_DQ[61]

AF61

SB_DQ[62]

AH60

SB_DQ[63]

BG39

SB_BS[0]

BD42

SB_BS[1]

AT22

SB_BS[2]

AV43

SB_CAS#

BF40

SB_RAS#

BD45

SB_WE#

SANDY-BRIDGE_BGA1023~D

SANDY-BRIDGE_BGA1023~D CPU1@

CPU1@

SB_CLK[0]

SB_CLK#[0]

SB_CKE[0]

SB_CLK[1]

SB_CLK#[1]

SB_CKE[1]

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6]

DDR SYSTEM MEMORY B

SB_DQS[7]

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

M_CLK_DDR#2

AY34

DDR_CKE2_DIMMB

AR22

M_CLK_DDR3

BA36

M_CLK_DDR#3

BB36

DDR_CKE3_DIMMB

BF27

DDR_CS2_DIMMB#

BE41

DDR_CS3_DIMMB#

BE47

M_ODT2

AT43

M_ODT3

BG47

DDR_B_DQS#0

AL3

DDR_B_DQS#1

AV3

DDR_B_DQS#2

BG11

DDR_B_DQS#3

BD17

DDR_B_DQS#4

BG51

DDR_B_DQS#5

BA59

DDR_B_DQS#6

AT60

DDR_B_DQS#7

AK59

DDR_B_DQS0

AM2

DDR_B_DQS1

AV1

DDR_B_DQS2

BE11

DDR_B_DQS3

BD18

DDR_B_DQS4

BE51

DDR_B_DQS5

BA61

DDR_B_DQS6

AR59

DDR_B_DQS7

AK61

DDR_B_MA0

BF32

DDR_B_MA1

BE33

DDR_B_MA2

BD33

DDR_B_MA3

AU30

DDR_B_MA4

BD30

DDR_B_MA5

AV30

DDR_B_MA6

BG30

DDR_B_MA7

BD29

DDR_B_MA8

BE30

DDR_B_MA9

BE28

DDR_B_MA10

BD43

DDR_B_MA11

AT28

DDR_B_MA12

AV28

DDR_B_MA13

BD46

DDR_B_MA14

AT26

DDR_B_MA15

AU22

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

SCHEMATICS,MB A6921

SCHEMATICS,MB A6921 4019A1

4019A1

M_CLK_DDR2

BA34

M_CLK_DDR#2 (11) DDR_CKE2_DIMMB (11)

M_CLK_DDR3 (11) M_CLK_DDR#3 (11) DDR_CKE3_DIMMB (11)

DDR_CS2_DIMMB# (11) DDR_CS3_DIMMB# (11)

M_ODT2 (11) M_ODT3 (11)

DDR_B_DQS#[0..7] (11)

DDR_B_DQS[0..7] (11)

DDR_B_MA[0..15] (11)

6Thursday, January 20, 2011

CFG Straps for Processor

CFG2

D D

UCPU1E

XDP_CFG0(5)

+CPU_CORE

R43

49.9_0402_1%

C C

B B

+VGFX_CORE

R45

49.9_0402_1%

R44

49.9_0402_1%

1 2

R46

49.9_0402_1%

CFG0 CFG2 CFG4

CFG5 CFG6 CFG7

VCC_VAL_SENSE VSS_VAL_SENSE

VCC_AXG_VAL_SENSE VSS_AXG_VAL_SENSE

T20 @

PAD~D

+V_DDR_REFA_R +V_DDR_REFB_R

B50

CFG[0]

C51

CFG[1]

B54

CFG[2]

D53

CFG[3]

A51

CFG[4]

C53

CFG[5]

C55

CFG[6]

H49

CFG[7]

A55

CFG[8]

H51

CFG[9]

K49

CFG[10]

K53

CFG[11]

F53

CFG[12]

G53

CFG[13]

L51

CFG[14]

F51

CFG[15]

D52

CFG[16]

L53

CFG[17]

H43

VCC_VAL_SENSE

K43

VSS_VAL_SENSE

H45

VAXG_VAL_SENSE

K45

VSSAXG_VAL_SENSE

F48

VCC_DIE_SENSE

H48

RSVD6

K48

RSVD7

BA19

RSVD8

AV19

RSVD9

AT21

RSVD10

BB21

RSVD11

BB19

RSVD12

AY21

RSVD13

BA22

RSVD14

AY22

RSVD15

AU19

RSVD16

AU21

RSVD17

BD21

RSVD18

BD22

RSVD19

BD25

RSVD20

BD26

RSVD21

BG22

RSVD22

BE22

RSVD23

BG26

RSVD24

BE26

RSVD25

BF23

RSVD26

BE24

RSVD27

SANDY-BRIDGE_BGA1023~D

SANDY-BRIDGE_BGA1023~D CPU1@

CPU1@

RESERVED

DC_TEST_A4 DC_TEST_C4 DC_TEST_D3

DC_TEST_D1 DC_TEST_A58 DC_TEST_A59

DC_TEST_C59

DC_TEST_A61

DC_TEST_C61

DC_TEST_D61 DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59

DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58

DC_TEST_BG4

DC_TEST_BG3

DC_TEST_BE3

DC_TEST_BG1

DC_TEST_BE1 DC_TEST_BD1

RSVD28 RSVD29

RSVD30 RSVD31 RSVD32 RSVD33

RSVD34 RSVD35 RSVD36 RSVD37 RSVD38

RSVD39 RSVD40

RSVD41 RSVD42 RSVD43 RSVD44

RSVD45

BE7 BG7

N42 L42 L45 L47

M13 M14 U14 W14 P13

AT49 K24

AH2 AG13 AM14 AM15

N50

A4 C4 D3 D1 A58 A59 C59 A61 C61 D61 BD61 BE61 BE59 BG61 BG59 BG58 BG4 BG3 BE3 BG1 BE1 BD1

R47

1K_0402_1%

@ R48

R48

1K_0402_1%

PEG Static Lane Reversal - CFG2 is for the 16x

1:(Default) Normal Operation; Lane #

CFG2

definition matches socket pin map definition 0:Lane Reversed

Display Port Presence Strap

CFG4

1K_0402_1%~D

PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2 disabled

CFG[6:5]

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

R41

R41 1K_0402_1%~D

1K_0402_1%~D

CFG4

1 : Disabled; No Physical Display Port attached to Embedded Display Port

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

CFG6 CFG5

R42@

R42@ 1K_0402_1%~D

1K_0402_1%~D

R49@

R50@

R50@ 1K_0402_1%~D

1K_0402_1%~D

CFG7

R51@

R51@ 1K_0402_1%~D

1K_0402_1%~D

PEG DEFER TRAINING

1: (Default) PEG Train immediately

CFG7

following xxRESETB de assertion

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

0: PEG Wait for BIOS for training

Title

2012/08/252010/08/25

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

SCHEMATICS,MB A6921

SCHEMATICS,MB A6921 4019A1

4019A1

Thursday, January 20, 2011

D D

+CPU_CORE

C53

22U_0805_6.3V6M

C53

22U_0805_6.3V6M

C60

C74

22U_0805_6.3V6M

C71

22U_0805_6.3V6M

C71

22U_0805_6.3V6M

C C

+CPU_CORE

C72

C73

22U_0805_6.3V6M

C73

22U_0805_6.3V6M

C52

22U_0805_6.3V6M

C52

22U_0805_6.3V6M

C51

22U_0805_6.3V6M

C51

22U_0805_6.3V6M

C50

22U_0805_6.3V6M

C50

C54

22U_0805_6.3V6M

C54

22U_0805_6.3V6M

330U_X_2VM_R6M

C75

C76

High‐FrequencyDecoupling

10U_0603_6.3V6M

C90

C103

22U_0805_6.3V6M

C103

22U_0805_6.3V6M

C102

22U_0805_6.3V6M

C102

22U_0805_6.3V6M

B B

A A

10U_0603_6.3V6M

C92

C91

10U_0603_6.3V6M

C93

10U_0603_6.3V6M

C95

C94

10U_0603_6.3V6M

C96

C97

11/24

UCPU1F

+CPU_CORE

A26

VCC[1]

A29

VCC[2]

A31

VCC[3]

A34

VCC[4]

A35

VCC[5]

A38

VCC[6]

A39

VCC[7]

A42

VCC[8]

C26

VCC[9]

C27

VCC[10]

C32

VCC[11]

C34

VCC[12]

C37

VCC[13]

C61

22U_0805_6.3V6M

C61

22U_0805_6.3V6M

330U_X_2VM_R6M

C77

10U_0603_6.3V6M

C98

C99

330U_X_2VM_R6M

C78

C39

VCC[14]

C42

VCC[15]

D27

VCC[16]

D32

VCC[17]

D34

VCC[18]

D37

VCC[19]

D39

VCC[20]

D42

VCC[21]

E26

VCC[22]

E28

VCC[23]

E32

VCC[24]

E34

VCC[25]

E37

VCC[26]

E38

C124

VCC[27]

F25

VCC[28]

F26

VCC[29]

F28

VCC[30]

F32

VCC[31]

F34

VCC[32]

F37

VCC[33]

F38

VCC[34]

F42

VCC[35]

G42

VCC[36]

H25

VCC[37]

H26

VCC[38]

H28

VCC[39]

H29

VCC[40]

H32

VCC[41]

H34

VCC[42]

H35

VCC[43]

H37

VCC[44]

H38

VCC[45]

H40

VCC[46]

J25

VCC[47]

J26

VCC[48]

J28

VCC[49]

J29

VCC[50]

J32

VCC[51]

J34

VCC[52]

J35

VCC[53]

J37

VCC[54]

J38

VCC[55]

J40

VCC[56]

J42

VCC[57]

K26

VCC[58]

K27

VCC[59]

K29

VCC[60]

K32

VCC[61]

K34

VCC[62]

K35

VCC[63]

K37

VCC[64]

K39

VCC[66]

K42

VCC[67]

L25

VCC[68]

L28

VCC[69]

L33

VCC[70]

L36

VCC[71]

L40

VCC[72]

N26

VCC[73]

N30

VCC[74]

N34

VCC[75]

N38

VCC[76]

SANDY-BRIDGE_BGA1023~D

CPU1@

CORE SUPPLY

POWER

VCCIO[1] VCCIO[3] VCCIO[4] VCCIO[5] VCCIO[6] VCCIO[7] VCCIO[8]

VCCIO[9] VCCIO[10] VCCIO[11] VCCIO[12] VCCIO[13] VCCIO[14] VCCIO[15] VCCIO[16] VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20] VCCIO[21] VCCIO[22] VCCIO[23] VCCIO[24] VCCIO[25] VCCIO[26] VCCIO[27] VCCIO[28] VCCIO[29]

VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33]

PEG AND DDRSENSE LINES SVID QUIET RAILS

VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49]

VCCIO50

VCCIO51

VCCIO_SEL

VCCPQE[1] VCCPQE[2]

VIDALERT#

VIDSCLK

VIDSOUT

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

AF46 AG48 AG50 AG51 AJ17 AJ21 AJ25 AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48

AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15

W16 W17

BC22

AM25 AN22

A44 B43 C44

F43 G43

AN16 AN17

VCCSENSE_R VSSSENSE_R

10U_0603_6.3V6M

1U_0402_6.3V6K

330U_D2_2VM_R9M~D

H_VCCP_SEL

1 2

C106

C106 1U_0402_6.3V6K

1U_0402_6.3V6K

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

10U_0603_6.3V6M

C55

1U_0402_6.3V6K

C48

1U_0402_6.3V6K

C67

1U_0402_6.3V6K

C82

C88

VCCIO_SEL

Hgih

Low 1.05V

R58

43_0402_5%

1 2 1 2 1 2

VCCIO_SENSE (51)

10U_0603_6.3V6M

C37

1U_0402_6.3V6K

1.0V

C36

1U_0402_6.3V6K

C47

C44

1U_0402_6.3V6K

C66

C62

1U_0402_6.3V6K

C79

C81

330U_D2_2VM_R9M~D

C87

+1.05VS

R59 0_0402_5%~DR59 0_0402_5%~D R60 0_0402_5%~DR60 0_0402_5%~D

R62 0_0402_5%~DR62 0_0402_5%~D

1 2

R63 0_0402_5%~DR63 0_0402_5%~D

1 2

T51PAD T51PAD

C39

C57

C68

C83

130_0402_1%~D

10U_0603_6.3V6M

1U_0402_6.3V6K

+1.05VS

10U_0603_6.3V6M

C40

C69

C84

R56

C41

+1.05VS+1.05VS

+CPU_CORE

C43

R57

R57 75_0402_5%

75_0402_5%

R61

R61 100_0402_1%~D

100_0402_1%~D

R64

R64 100_0402_1%~D

100_0402_1%~D

Place the PU resistors close to CPU

VR_SVID_ALRT# (53) VR_SVID_CLK (53) VR_SVID_DAT (53)

Place the PU resistors close to CPU

VCCSENSE (53) VSSSENSE (53)

Place the PU resistors close to VR

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/25 2012/08/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

SCHEMATICS,MB A6921

SCHEMATICS,MB A6921 4019A1

4019A1

8Thursday, January 20, 2011

+1.5V

1 2

PAD-OPEN 4x4m

8 7 6 5

AO4430L_SO8

RUN_ON_CPU1.5VS3

Q7 2N7002_SOT23

2N7002_SOT23

SM_VREF

DDR3 - 1.5V RAILS

POWER

VCCDQ[1] VCCDQ[2]

QUIET RAILS

VDDQ_SENSE

VSS_SENSE_VDDQ

SENSE LINES

VCCSA_SENSE

VCCSA_VID[0] VCCSA_VID[1]

0_0402_5% R65

0_0402_5%

RUN_ON_CPU1.5VS3#

Q6 2N7002_SOT23

2N7002_SOT23

AA46 AB47 AB50 AB51 AB52 AB53 AB55 AB56 AB58 AB59 AC61 AD47 AD48 AD50 AD51 AD52 AD53 AD55 AD56 AD58 AD59 AE46

N45 P47 P48 P50 P51 P52 P53 P55 P56 P61 T48 T58 T59 T61 U46 V47 V48 V50 V51 V52 V53 V55 V56 V58

V59 W50 W51 W52 W53 W55 W56 W61

Y48

Y61

F45

G45

BB3 BC1 BC4

L17

L21

N16

N20

N22

P17

P20

R16

R18

R21

U15

V16

V17

V18

V21 W20

1 2

R65

15K_0402_1%

UCPU1G

VAXG[1] VAXG[2] VAXG[3] VAXG[4] VAXG[5] VAXG[6] VAXG[7] VAXG[8] VAXG[9] VAXG[10] VAXG[11] VAXG[12] VAXG[13] VAXG[14] VAXG[15] VAXG[16] VAXG[17] VAXG[18] VAXG[19] VAXG[20] VAXG[21] VAXG[22] VAXG[23] VAXG[24] VAXG[25] VAXG[26] VAXG[27] VAXG[28] VAXG[29] VAXG[30] VAXG[31] VAXG[32] VAXG[33] VAXG[34] VAXG[35] VAXG[36] VAXG[37] VAXG[38] VAXG[39] VAXG[40] VAXG[41] VAXG[42] VAXG[43] VAXG[44] VAXG[45] VAXG[46] VAXG[47] VAXG[48] VAXG[49] VAXG[50] VAXG[51] VAXG[52] VAXG[53] VAXG[54] VAXG[55] VAXG[56]

VAXG_SENSE VSSAXG_SENSE

VCCPLL[1] VCCPLL[2] VCCPLL[3]

VCCSA[1] VCCSA[2] VCCSA[3] VCCSA[4] VCCSA[5] VCCSA[6] VCCSA[7] VCCSA[8] VCCSA[9] VCCSA[10] VCCSA[11] VCCSA[12] VCCSA[13] VCCSA[14] VCCSA[15] VCCSA[16]

SANDY-BRIDGE_BGA1023~D

CPU1@

+VSB

R68

GRAPHICS

SENSE

LINES

SENSE

LINES

1.8V RAIL

SA RAIL

SUSP(5,44,51)

+3VALW

R67

D D

22U_0805_6.3V6M

C111

22U_0805_6.3V6M

C117

C135

1U_0402_6.3V6K

C135

1U_0402_6.3V6K

10U_0603_6.3V6M~D

C633

R77

R77 0_0402_5%~D

0_0402_5%~D

C164

1 2

0_0402_5% R70

0_0402_5%

C112

22U_0805_6.3V6M

C118

C136

1U_0402_6.3V6K

C136

1U_0402_6.3V6K

VCC_AXG_SENSE(53)

VSS_AXG_SENSE(53)

1U_0402_6.3V6K~D

C153

C154

10U_0603_6.3V6M~D

C165

1U_0402_6.3V6K

C165

1U_0402_6.3V6K

R710_0402_5% R710_0402_5%

R70

22U_0805_6.3V6M

C119

C137

1U_0402_6.3V6K

C137

1U_0402_6.3V6K12C138

1U_0402_6.3V6K~D

C159

CPU1.5V_S3_GATE(37)

SUSP#(28,37,44,49,51,52)

+VGFX_CORE

22U_0805_6.3V6M

C109

22U_0805_6.3V6M

C122

+1.8VS

+VCCSA

330U_D2_2VM_R9M~D

22U_0805_6.3V6M

C116

C123

330U_D2_2VM_R9M~D

C133

1U_0402_6.3V6K

C133

1U_0402_6.3V6K

22U_0805_6.3V6M

C158

C134

C C

B B

330U_D2_2VM_R9M~D

VSSSA_SENSE(50)

A A

100K_0402_5%

C114

22U_0805_6.3V6M

C120

1U_0402_6.3V6K

C138

1U_0402_6.3V6K

C155

10U_0603_6.3V6M~D

C160

C167

C166

1U_0402_6.3V6K

C166

1U_0402_6.3V6K

R67

22U_0805_6.3V6M

C121

VCC_AXG_SENSE VSS_AXG_SENSE

10U_0603_6.3V6M~D

C163

C168

1U_0402_6.3V6K

C168

1U_0402_6.3V6K

J1@

D D D

VDDQ[1] VDDQ[2] VDDQ[3] VDDQ[4] VDDQ[5] VDDQ[6] VDDQ[7] VDDQ[8]

VDDQ[9] VDDQ[10] VDDQ[11] VDDQ[12] VDDQ[13] VDDQ[14] VDDQ[15] VDDQ[16] VDDQ[17] VDDQ[18] VDDQ[19] VDDQ[20] VDDQ[21] VDDQ[22] VDDQ[23] VDDQ[24] VDDQ[25] VDDQ[26]

S G4D

R69

R69 330K_0402_5%

330K_0402_5% @

AY43

0.1U_0402_16V4Z

0.1U_0402_16V4Z AJ28

AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33

AM28 AN26

BC43 BA43

U10

D48 D49

+1.5V_CPU_VDDQ

C108

0.1U_0603_25V7K

+V_SM_VREF should have 10 mil trace width

C115

1 2

C149

C149 1U_0402_6.3V6K

1U_0402_6.3V6K

VCCSA_VID0

VCCSA_SEL (50)

220_0402_5%

2N7002_SOT23

100K_0402_5%

100K_0402_5% R74

R74 @

1 2

10U_0603_6.3V6M

C129

C139

1U_0402_6.3V6K

C139

1U_0402_6.3V6K

C140

R79

10K_0402_5%

R66

10U_0603_6.3V6M

C130

C141

1U_0402_6.3V6K

C141

1U_0402_6.3V6K

+1.5V_CPU_VDDQ

RUN_ON_CPU1.5VS3

+1.5V_CPU_VDDQ

C131

C142

1U_0402_6.3V6K

C142

1U_0402_6.3V6K

C143

C107@

0.1U_0402_10V6K

RUN_ON_CPU1.5VS3#

R72

0_0402_5%

C132

C132 330U_D2_2VM_R9M

330U_D2_2VM_R9M

C144

1U_0402_6.3V6K

C144

1U_0402_6.3V6K

R78@

0_0402_5%~D

123

Q8 AO3414_SOT23-3

AO3414_SOT23-3

C147

C146

1U_0402_6.3V6K

C146

1U_0402_6.3V6K

VCCSA_SENSE (50)

+1.5V_CPU_VDDQ

R73

R73 100_0402_1%

100_0402_1%

+V_SM_VREF+V_SM_VREF_CNT

R75

R75 100_0402_1%

100_0402_1%

1U_0402_6.3V6K

+1.5V_CPU_VDDQ +1.5V

C150 0.1U_0402_10V7K~DC150 0.1U_0402_10V7K~D

C151 0.1U_0402_10V7K~DC151 0.1U_0402_10V7K~D

C152 0.1U_0402_10V7K~DC152 0.1U_0402_10V7K~D

C157 0.1U_0402_10V7K~DC157 0.1U_0402_10V7K~D

VID[0] VID[1] 2011 2012 0 0 0.90 V Yes Yes 0 1 0.80 V Yes Yes 1 0 0.725 V No Yes 1 1 0.675 V No Yes

AC10 AC14 AC46

AD17 AD20

AD61

AG10 AG14 AG18 AG47 AG52 AG61

AH58

AM13 AM20 AM22 AM26 AM30 AM34

A13 A17 A21 A25 A28 A33 A37 A40 A45 A49 A53

AA1 AA13 AA50 AA51 AA52 AA53 AA55 AA56

AA8 AB16 AB18 AB21 AB48 AB61

AC6

AD4 AE13

AE8

AF1 AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58 AF59

AG7

AH4 AJ13

AJ16 AJ20 AJ22 AJ26 AJ30 AJ34 AJ38 AJ42 AJ45 AJ48

AJ7

AK1 AK52 AL10 AL13 AL17 AL21 AL25 AL28 AL33 AL36 AL40 AL43 AL47 AL61

UCPU1H

VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90]

SANDY-BRIDGE_BGA1023~D

VSS

VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]

VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180]

AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/25 2012/08/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

SCHEMATICS,MB A6921

Custom

4019A1

9Thursday, January 20, 2011

+VREF_DQ_DIMMA +1.5V

+VREF_DQ_DIMMA

0.1U_0402_10V6K

2.2U_0603_6.3V4Z

C169

C170

DDR_CKE0_DIMMA(6)

DDR_A_BS2(6)

M_CLK_DDR0(6) M_CLK_DDR#0(6)

DDR_A_BS0(6) DDR_A_WE#(6)

DDR_A_CAS#(6)

DDR_CS1_DIMMA#(6)

+3VS

2.2U_0603_6.3V4Z

D D

C C

B B

A A

DDR_A_D0 DDR_A_D1

DDR_A_DM0 DDR_A_D2

DDR_A_D3 DDR_A_D8

DDR_A_D9 DDR_A_DQS#1

DDR_A_DQS1 DDR_A_D10

DDR_A_D11 DDR_A_D16

DDR_A_D17 DDR_A_DQS#2

DDR_A_DQS2 DDR_A_D18

DDR_A_D19 DDR_A_D24

DDR_A_D25 DDR_A_DM3 DDR_A_D26

DDR_A_D27

DDR_CKE0_DIMMA DDR_CKE1_DIMMA

DDR_A_BS2

DDR_A_MA9 DDR_A_MA8

M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR#0 M_CLK_DDR#1

DDR_A_MA10 DDR_A_BS0

DDR_A_WE# DDR_A_CAS#

DDR_A_MA13 DDR_CS1_DIMMA#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5 DDR_A_D42

DDR_A_D43 DDR_A_D48

DDR_A_D49 DDR_A_DQS#6

DDR_A_DQS6 DDR_A_D50

DDR_A_D51 DDR_A_D56

DDR_A_D57 DDR_A_DM7 DDR_A_D58

DDR_A_D59

R90

1 2

10K_0402_5%

0.1U_0402_10V6K

C190

C191

+1.5V +1.5V

PN:SP07000NN00

H4.0 standard

JDIMM1

VREF_DQ1VSS1

R93

10K_0402_5%

R93

10K_0402_5%

VSS2

DQ0

DQ1

VSS4

DM0

VSS5

DQ2

DQ3

VSS7

DQ8

DQ9

VSS9

DQS#1 DQS129RESET#

VSS11

DQ10

DQ11

VSS13

DQ16

DQ17

VSS15

DQS#2

DQS2

VSS18

DQ18

DQ19

VSS20

DQ24

DQ25 VSS2261DQS#3

DM3

VSS23

DQ26

DQ27

VSS25

CKE0

VDD1

NC1

BA2

VDD3

A12/BC#

VDD5

VDD7

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

FOX_AS0A621-U4SG-7H

VSS3

DQS#0

DQS0

VSS6

VSS8 DQ12 DQ13

VSS10

VSS12

DQ14 DQ15

VSS14

DQ20 DQ21

VSS16 VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

VSS24

DQ30 DQ31

VSS26

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30 VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42 VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

VTT2

DQ4 DQ5

DQ6 DQ7

DM1

DM2

CK1

BA1

NC2

DM4

DM6

SDA SCL

DDR_A_D[0..63](6)

DDR_A_DQS[0..7](6) DDR_A_DQS#[0..7](6) DDR_A_MA[0..15](6)

10U_0603_6.3V6M

C171

+1.5V

R82

1K_0402_1%

+VREF_CA

C177

R83

1K_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C186

+0.75VS

1U_0402_6.3V6K

DDR3 SO-DIMM A/BOTTOM

DDR_A_D4

DDR_A_D5

6 8

DDR_A_DQS#0

DDR_A_DQS0

12 14

DDR_A_D6

DDR_A_D7

18 20

DDR_A_D12

DDR_A_D13

24 26

DDR_A_DM1

DDR3_DRAMRST#

30 32

DDR_A_D14

DDR_A_D15

36 38

DDR_A_D20

DDR_A_D21

42 44

DDR_A_DM2

46 48

DDR_A_D22

DDR_A_D23

52 54

DDR_A_D28

DDR_A_D29

58 60

DDR_A_DQS#3

DDR_A_DQS3

64 66

DDR_A_D30

DDR_A_D31

70 72

74 76

DDR_A_MA15

A15 A14

A11

A7 A6

A4 A2

S0#

80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_A_MA14 DDR_A_MA11DDR_A_MA12

DDR_A_MA7 DDR_A_MA6

DDR_A_MA4DDR_A_MA5 DDR_A_MA2DDR_A_MA3

DDR_A_MA0DDR_A_MA1

DDR_A_BS1 DDR_A_RAS#

DDR_CS0_DIMMA# M_ODT0

M_ODT1

DDR_A_D36 DDR_A_D37

DDR_A_DM4 DDR_A_D38

DDR_A_D39 DDR_A_D44

DDR_A_D45 DDR_A_DQS#5

DDR_A_DQS5 DDR_A_D46

DDR_A_D47 DDR_A_D52

DDR_A_D53 DDR_A_DM6 DDR_A_D54

DDR_A_D55 DDR_A_D60

DDR_A_D61 DDR_A_DQS#7

DDR_A_DQS7 DDR_A_D62

DDR_A_D63

SMB_DATA_S3 SMB_CLK_S3

+0.75VS

DDR3_DRAMRST# (6,11)

DDR_CKE1_DIMMA (6)

M_CLK_DDR1 (6) M_CLK_DDR#1 (6)

DDR_A_BS1 (6) DDR_A_RAS# (6)

DDR_CS0_DIMMA# (6) M_ODT0 (6)

M_ODT1 (6)

2.2U_0603_6.3V4Z

0.1U_0402_10V6K

0.1U_0402_10V6K C176

C176

SMB_DATA_S3 (11,13,32) SMB_CLK_S3 (11,13,32)

R80

1K_0402_1%

R81

1K_0402_1%

10U_0603_6.3V6M

C173

C172

C188

C187

1U_0402_6.3V6K

Compal Secret Data

Deciphered Date

+VREF_DQ_DIMMA

+1.5V

10U_0603_6.3V6M

C174

1U_0402_6.3V6K

C189

1U_0402_6.3V6K

C189

1U_0402_6.3V6K

0.1U_0402_10V6K

10U_0603_6.3V6M

C175

10U_0603_6.3V6M

C179

C178

2012/08/252010/08/25

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

0.1U_0402_10V6K

10U_0603_6.3V6M

C181

C180

C181

Title

Size Document Number Rev

Date: Sheet of

0.1U_0402_10V6K

C182

Compal Electronics, Inc.

Thursday, January 20, 2011

0.1U_0402_10V6K

C183

C184

SCHEMATICS,MB A6921

4019A1

C185

220U_2.5V_B2_R35

BCustom

5410

+VREF_DQ_DIMMB

0.1U_0402_10V6K

2.2U_0603_6.3V4Z

C193

C192

D D

+3VS

DDR_CKE2_DIMMB(6)

DDR_B_BS2(6)

M_CLK_DDR2(6) M_CLK_DDR#2(6)

DDR_B_BS0(6) DDR_B_WE#(6)

DDR_B_CAS#(6)

DDR_CS3_DIMMB#(6)

C212

2.2U_0603_6.3V4Z

C212

2.2U_0603_6.3V4Z

0.1U_0402_10V6K

C C

B B

A A

+VREF_DQ_DIMMB DDR_B_D0

DDR_B_D1 DDR_B_DM0 DDR_B_D2

DDR_B_D3 DDR_B_D8

DDR_B_D9 DDR_B_DQS#1

DDR_B_DQS1 DDR_B_D10

DDR_B_D11 DDR_B_D16

DDR_B_D17 DDR_B_DQS#2

DDR_B_DQS2 DDR_B_D18

DDR_B_D19 DDR_B_D24

DDR_B_D25 DDR_B_DM3 DDR_B_D26

DDR_B_D27

DDR_CKE2_DIMMB DDR_CKE3_DIMMB

DDR_B_BS2

DDR_B_MA9 DDR_B_MA8

M_CLK_DDR2 M_CLK_DDR3 M_CLK_DDR#2 M_CLK_DDR#3

DDR_B_MA10 DDR_B_BS0

DDR_B_WE# DDR_B_CAS#

DDR_B_MA13 DDR_CS3_DIMMB#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_DM5 DDR_B_D42

DDR_B_D43 DDR_B_D48

DDR_B_D49 DDR_B_DQS#6

DDR_B_DQS6 DDR_B_D50

DDR_B_D51 DDR_B_D56

DDR_B_D57 DDR_B_DM7 DDR_B_D58

DDR_B_D59

R103

1 2

10K_0402_5%

1 2

R107 10K_0402_5%R107 10K_0402_5%

C213

+1.5V

101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205

PN:SP07000IH00

H5.2 standard

JDIMM2

VREF_DQ1VSS1

VSS2

DQ0

DQ1

VSS4

DM0

VSS5

DQ2

DQ3

VSS7

DQ8

DQ9

VSS9

DQS#1 DQS129RESET#

VSS11

DQ10

DQ11

VSS13

DQ16

DQ17

VSS15

DQS#2

DQS2

VSS18

DQ18

DQ19

VSS20

DQ24

DQ25 VSS2261DQS#3

DM3

VSS23

DQ26

DQ27

VSS25

CKE0

VDD1

NC1

BA2

VDD3

A12/BC#

VDD5

VDD7

VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST

VREF_CA VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1

EVENT#

TYCO_2-2013289-1

DQ4 DQ5

VSS3

DQS#0

DQS0 VSS6

DQ6

DQ7 VSS8 DQ12 DQ13

VSS10

DM1

VSS12

DQ14 DQ15

VSS14

DQ20 DQ21

VSS16

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

VSS24

DQ30 DQ31

VSS26

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

BA1 RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

SDA

SCL

VTT2

A15 A14

A11

A7 A6

A4 A2

S0#

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

+1.5V

DDR3 SO-DIMM B/TOP

DDR_B_D4 DDR_B_D5

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D6 DDR_B_D7

DDR_B_D12 DDR_B_D13

DDR_B_DM1 DDR3_DRAMRST#

DDR_B_D14 DDR_B_D15

DDR_B_D20 DDR_B_D21

DDR_B_DM2 DDR_B_D22

DDR_B_D23 DDR_B_D28

DDR_B_D29 DDR_B_DQS#3

DDR_B_DQS3 DDR_B_D30

DDR_B_D31

DDR_B_MA15 DDR_B_MA14

DDR_B_MA11DDR_B_MA12 DDR_B_MA7

DDR_B_MA6 DDR_B_MA4DDR_B_MA5

DDR_B_MA2DDR_B_MA3 DDR_B_MA0DDR_B_MA1

DDR_B_BS1 DDR_B_RAS#

DDR_CS2_DIMMB# M_ODT2

M_ODT3

DDR_B_D36 DDR_B_D37

DDR_B_DM4 DDR_B_D38

DDR_B_D39 DDR_B_D44

DDR_B_D45 DDR_B_DQS#5

DDR_B_DQS5 DDR_B_D46

DDR_B_D47 DDR_B_D52

DDR_B_D53 DDR_B_DM6 DDR_B_D54

DDR_B_D55 DDR_B_D60

DDR_B_D61 DDR_B_DQS#7

DDR_B_DQS7 DDR_B_D62

DDR_B_D63

SMB_DATA_S3 SMB_CLK_S3

DDR3_DRAMRST# (6,10)

DDR_CKE3_DIMMB (6)

M_CLK_DDR3 (6) M_CLK_DDR#3 (6)

DDR_B_BS1 (6) DDR_B_RAS# (6)

DDR_CS2_DIMMB# (6) M_ODT2 (6)

M_ODT3 (6)

+VREF_CB

0.1U_0402_10V6K

2.2U_0603_6.3V4Z

C194

SMB_DATA_S3 (10,13,32) SMB_CLK_S3 (10,13,32)

+0.75VS

C195

DDR_B_D[0..63](6) DDR_B_DQS[0..7](6) DDR_B_DQS#[0..7](6) DDR_B_MA[0..15](6)

R96

1K_0402_1%

R97

1K_0402_1%

10U_0603_6.3V6M

C196

+1.5V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+0.75VS

C208

1U_0402_6.3V6K

2010/08/25 2012/08/25

C198

C197

C209 1U_0402_6.3V6KC209 1U_0402_6.3V6K

C210 1U_0402_6.3V6KC210 1U_0402_6.3V6K

C211 1U_0402_6.3V6KC211 1U_0402_6.3V6K

Compal Secret Data

Deciphered Date

R94

C199

+1.5V

R95

+1.5V

10U_0603_6.3V6M

C200

+VREF_DQ_DIMMB

10U_0603_6.3V6M

C201

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

10U_0603_6.3V6M

C202

10U_0603_6.3V6M

C203

0.1U_0402_10V6K

C206

4019A1

C207

11 54Thursday, January 20, 2011

0.1U_0402_10V6K

Title

Size Document Number Rev

Custom B

Date: Sheet of

C205

C204

Compal Electronics, Inc.

SCHEMATICS,MB A6921

W=20milsW=20mils

R111

1K_0402_5%

1 2

C216

C216 1U_0603_10V4Z

1U_0603_10V4Z

D D

+RTCVCC

R112 1M_0402_5%R112 1M_0402_5%

1 2

R113 330K_0402_5%R113 330K_0402_5%

1 2

INTVRMEN

H：Integrated VRM enable

L：Integrated VRM disable

+RTCBATT+RTCVCC

CLRP1

SHORT PADS

SM_INTRUDER# PCH_INTVRMEN

R109 10M_0402_5%R109 10M_0402_5%

18P_0402_50V8J

C214

1 2

OSC

NC2NC

CMOS

OSC

32.768KHZ_12.5PF_9H03200413

(INTVRMEN should always be pull high.)

+3VS

R117 @ 1K_0402_5%R117 @ 1K_0402_5%

1 2

HIGH= Enable ( No Reboot ) LOW= Disable (Default)

+3VALW

C C

R118 @ 1K_0402_5%R118 @ 1K_0402_5%

Low = Disabled (Default)

High = Enabled [Flash Descriptor Security Overide]

+3VALW

R120 1K_0402_5%R120 1K_0402_5%

This signal has a weak internal pull-down On Die PLL VR Select is supplied by

1.5V when smapled high

1.8V when sampled low Needs to be pulled High for Huron River platfrom

+3VALW

R243 1K_0402_5%R243 1K_0402_5%

1 2

B B

33_0402_5%

HDA_BITCLK_AUDIO(35)

HDA_SYNC_AUDIO(35)

HDA_RST_AUDIO#(35)

HDA_SDOUT_AUDIO(35)

A A

1 2

33_0402_5%

1 2

33_0402_5%

1 2

33_0402_5%

1 2

R124

R126

R128

R131

HDA_SPKR

HDA_SDOUT

HDA_SYNC

PCH_GPIO13

HDA_BIT_CLK

HDA_SYNC_R

HDA_RST#

HDA_SDOUT

HDA_SYNC_R

R282

R282 1M_0402_5%

1M_0402_5%

+3VALW +3VALW+3VALW

PCH_RTCX1 PCH_RTCX2

C215

C215 18P_0402_50V8J

18P_0402_50V8J

C848

33P_0402_50V8J

R134

200_0402_5%

R138

100_0402_1%

PCH_JTAG_TCK

R122

R122 51_0402_5%

51_0402_5%

+RTCVCC

ME_FLASH(37)

1 2

C217

1U_0603_10V4Z

1 2

R114 20K_0402_5%R114 20K_0402_5%

1 2

R115 20K_0402_5%R115 20K_0402_5%

C218

1U_0603_10V4Z

ME_FLASH

R121 @ 1K_0402_1%R121 @ 1K_0402_1%

+3VS

R714

R714 33K_0402_5%

33K_0402_5%

1 2

Q9 BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

HDA_SYNC

123

R129@

R129@ 0_0402_5%

0_0402_5%

R135

200_0402_5%

R139

R139 100_0402_1%

100_0402_1%

HDA_SPKR(35)

HDA_SDIN0(35)

1 2

R136

200_0402_5%

PCH_JTAG_TDIPCH_JTAG_TDO PCH_JTAG_TMS

R140

100_0402_1%

EC_RSMRST#(14,37)

XDP_DBRESET#(5,14)

CLRP2

SHORT PADS

CLRP2

SHORT PADS

CLRP3

SHORT PADS

CLRP3

SHORT PADS

R119

1 2

0_0402_5%

PBTN_OUT#(5,14,37)

+3VALW

PCH_RTCX1 PCH_RTCX2 PCH_RTCRST# PCH_SRTCRST# SM_INTRUDER# PCH_INTVRMEN

HDA_BIT_CLK HDA_SYNC HDA_SPKR HDA_RST#

HDA_SDIN0

HDA_SDOUT

PCH_GPIO33 PCH_GPIO13

PCH_JTAG_TCK PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TDO

SPI_CLK_PCH_R SPI_SB_CS0#

SPI_SI SPI_SO_R

EC_RSMRST#(14,37)

+1.05VS

+3VALW

EC_RSMRST#

XDP_DBRESET#

A20 C20 D20 G22 K22 C17

N34 L34 T10 K34

E34 G34 C34 A34

A36

C36 N32

J3 H7 K5 H1

Y14

V4 U3

R85 1K_0402_1%

R761

R290

R84 1K_0402_1%

PCH_JTAG_TDO PCH_JTAG_TDI

PCH_JTAG_TMS

PCH_JTAG_TCK

U6A

RTCX1 RTCX2 RTCRST# SRTCRST# INTRUDER# INTVRMEN

HDA_BCLK HDA_SYNC SPKR HDA_RST#

HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3

HDA_SDO

HDA_DOCK_EN# / GPIO33 HDA_DOCK_RST# / GPIO13

JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO

SPI_CLK SPI_CS0# SPI_CS1#

SPI_MOSI SPI_MISO

COUGARPOINT_FCBGA989

1 2 1 2

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0_0402_5%

JTAG

RTCIHDA

SPI

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

SERIRQ

SATA0RXN SATA0RXP SATA0TXN

SATA0TXP

SATA1RXN

SATA 6G

SATA1RXP SATA1TXN

SATA1TXP

SATA2RXN SATA2RXP SATA2TXN

SATA2TXP

SATA3RXN SATA3RXP SATA3TXN

SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA LPC

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN

SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED# SATA0GP / GPIO21 SATA1GP / GPIO19

JDB2

ACES_88717-2601

ME@

2010/08/25

LPC_AD0

C38

LPC_AD1

A38

LPC_AD2

B37

LPC_AD3

C37

LPC_FRAME#

D36 E36

K36

SERIRQSERIRQ

AM3 AM1

SATA_ITX_C_DRX_N0

AP7

SATA_ITX_C_DRX_P0

AP5 AM10

AM8 AP11 AP10

AD7 AD5

SATA_ITX_C_DRX_N2

AH5

SATA_ITX_C_DRX_P2

AH4 AB8

AB10

SATA_ITX_C_DRX_N3

AF3

SATA_ITX_C_DRX_P3

AF1 Y7

SATA_ITX_C_DRX_N4

AD3

SATA_ITX_C_DRX_P4

AD1 Y3

Y1 AB3 AB1

Y11

SATA_COMP

Y10

AB12

SATA3_COMP

AB13

RBIAS_SATA3

AH1

HDD_LED#

PCH_GPIO21

V14 P1

1201

PCH_GPIO19

Compal Secret Data

Deciphered Date

R116 10K_0402_5%R116 10K_0402_5%

SPI_SB_CS0#

LPC_AD0 (37,43) LPC_AD1 (37,43) LPC_AD2 (37,43) LPC_AD3 (37,43)

LPC_FRAME# (37,43)

R123

37.4_0402_1%

1 2

R125

49.9_0402_1%

1 2

R127 750_0402_1%R127 750_0402_1%

1 2

R130

@ 10K_0402_5%

R132

10K_0402_5%

R133

10K_0402_5%

EC and Mini card debug port

SERIRQ (37)

+1.05VS_VCC_SATA

+1.05VS_SATA3

+3VS +3VS

+3VS

12 12

4MB SPI ROM FOR ME & Non-share ROM.

+3VS

R141

1 2

R142

1 2

11/24

SPI_SO_LSPI_SO_R

1 2

SPI_WP#

33_0402_5%

R144

R144 <BOM Structure>

2012/08/25

SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0

SATA_ITX_DRX_N0

C2190.01U_0402_16V7K C2190.01U_0402_16V7K

SATA_ITX_DRX_P0

C2200.01U_0402_16V7K C2200.01U_0402_16V7K

SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2 SATA_ITX_DRX_N2_CONN

C2210.01U_0402_16V7K C2210.01U_0402_16V7K

SATA_ITX_DRX_P2_CONN

C2220.01U_0402_16V7K C2220.01U_0402_16V7K

SATA_DTX_C_IRX_N3 SATA_DTX_C_IRX_P3 SATA_ITX_DRX_N3_CONN

C2230.01U_0402_16V7K C2230.01U_0402_16V7K

SATA_ITX_DRX_P3_CONN

C2240.01U_0402_16V7K C2240.01U_0402_16V7K

SATA_DTX_C_IRX_N4 SATA_DTX_C_IRX_P4

SATA_ITX_DRX_N4

C2250.01U_0402_16V7K C2250.01U_0402_16V7K

SATA_ITX_DRX_P4

C2260.01U_0402_16V7K C2260.01U_0402_16V7K

SPI_WP#

3.3K_0402_5%

3.3K_0402_5% SPI_HOLD#

3.3K_0402_5%

CS#

WP# GND4SI

S IC FL 32M W25Q32BVSSIG SOIC 8P

VCC

HOLD#

SCLK

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

SATA_DTX_C_IRX_N0 (42) SATA_DTX_C_IRX_P0 (42) SATA_ITX_DRX_N0 (42) SATA_ITX_DRX_P0 (42)

SATA_DTX_C_IRX_N2 (42) SATA_DTX_C_IRX_P2 (42) SATA_ITX_DRX_N2_CONN (42) SATA_ITX_DRX_P2_CONN (42)

SATA_DTX_C_IRX_N3 (32) SATA_DTX_C_IRX_P3 (32) SATA_ITX_DRX_N3_CONN (32) SATA_ITX_DRX_P3_CONN (32)

SATA_DTX_C_IRX_N4 (40) SATA_DTX_C_IRX_P4 (40) SATA_ITX_DRX_N4 (40)

SATA_ITX_DRX_P4 (40)

SPI_CLK_PCH

R137

33_0402_5%

22P_0402_50V8J

R1450_0402_5% R1450_0402_5%

SPI_CLK_PCH_R SPI_SISPI_SI_R

+3VS

C228

1 2

0.1U_0402_16V4Z

SPI_HOLD# SPI_CLK_PCH

1 2 1 2

33_0402_5%

R146

SCHEMATICS,MB A6921

4019A1

Thursday, January 20, 2011

C227

HDD

ESATA

ODD

mSATA

PCIE_PRX_DTX_N2(32)

WLAN

D D

Card reader

LAN

C C

WLAN

Card reader

LAN

B B

PCIE_PRX_DTX_P2(32) PCIE_PTX_C_DRX_N2(32) PCIE_PTX_C_DRX_P2(32)

PCIE_PRX_DTX_N3(43)

PCIE_PRX_DTX_P3(43) PCIE_PTX_C_DRX_N3(43) PCIE_PTX_C_DRX_P3(43)

PCIE_PRX_DTX_N4(33)

PCIE_PRX_DTX_P4(33) PCIE_PTX_C_DRX_N4(33) PCIE_PTX_C_DRX_P4(33)

CLK_PCIE_WLAN1#(32) CLK_PCIE_WLAN1(32)

WLAN_CLKREQ1#(32)

CLK_PCIE_CR#(43) CLK_PCIE_CR(43)

CLKREQ_CR#(43)

CLK_PCIE_LAN#(33) CLK_PCIE_LAN(33)

CLKREQ_LAN#(33)

+3VALW

PE_GPIO0(16,21)

PE_GPIO1(16,28,52)

C233 0.1U_0402_10V7KC233 0.1U_0402_10V7K C229 0.1U_0402_10V7KC229 0.1U_0402_10V7K

C230 0.1U_0402_10V7KC230 0.1U_0402_10V7K C234 0.1U_0402_10V7KC234 0.1U_0402_10V7K

C231 0.1U_0402_10V7KC231 0.1U_0402_10V7K C232 0.1U_0402_10V7KC232 0.1U_0402_10V7K

R160 10K_0402_5%R160 10K_0402_5%

+3VALW

R162 0_0402_5%R162 0_0402_5%

1 2

R164 0_0402_5%R164 0_0402_5%

1 2

R166 0_0402_5%R166 0_0402_5%

1 2

R167 10K_0402_5%R167 10K_0402_5%

+3VS

R179 0_0402_5%R179 0_0402_5% R180 0_0402_5%R180 0_0402_5%

R169 10K_0402_5%R169 10K_0402_5%

+3VS

R182 0_0402_5%R182 0_0402_5%

1 2

R171 0_0402_5%R171 0_0402_5%

1 2

R173 0_0402_5%R173 0_0402_5%

1 2

R176 10K_0402_5%R176 10K_0402_5%

+3VALW

R175 0_0402_5%R175 0_0402_5%

1 2

R184 10K_0402_5%R184 10K_0402_5%

+3VALW

R186 10K_0402_5%R186 10K_0402_5%

+3VALW

R188 10K_0402_5%R188 10K_0402_5%

+3VALW

R195 R190 10K_0402_5%R190 10K_0402_5% 8/21

PE_GPIO0

+3VALW

PE_GPIO1

1 2

R191 0_0402_5%

R191 0_0402_5% R193 10K_0402_5%R193 10K_0402_5% 8/21

1 2

R194 0_0402_5%

1 2 1 2

CLK_XDP_CLK#(5) CLK_XDP_CLK(5)

10K_0402_5%R195

10K_0402_5%

12 12

CLK_PCIE_WLAN1#_R CLK_PCIE_WLAN1_R

PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2

PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3 PCIE_PTX_DRX_N3 PCIE_PTX_DRX_P3

PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4

PCH_GPIO73

WLAN_CLKREQ1#_R

CLK_PCIE_CR#_R CLK_PCIE_CR_R

CLKREQ_CR#_R

CLK_PCIE_LAN#_R CLK_PCIE_LAN_R

CLKREQ_LAN#_R

PCH_GPIO26

PCH_GPIO44

PCH_GPIO56

PCH_GPIO45

PCH_GPIO46

CLK_XDP_CLK# CLK_XDP_CLK

U6B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_BCLK0_N / CLKOUT_PCIE8N

AK13

CLKOUT_BCLK0_P / CLKOUT_PCIE8P

COUGARPOINT_FCBGA989

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

CLOCKS

CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P / CLKOUT_BCLK1_P

SMBALERT# / GPIO11

SMBCLK

SMBDATA

SML0ALERT# / GPIO60

SML0CLK

SML0DATA

SML1CLK / GPIO58

SML1DATA / GPIO75

CL_CLK1

CL_DATA1

Link

CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P

FLEX CLOCKS

CL_RST1#

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_DMI2_N CLKIN_DMI2_P

CLKIN_DOT_96N

CLKIN_DOT_96P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64 CLKOUTFLEX1 / GPIO65 CLKOUTFLEX2 / GPIO66 CLKOUTFLEX3 / GPIO67

EC_LID_OUT#

E12

PCH_SMBCLK

H14

PCH_SMBDATA

DRAMRST_CNTRL_PCH

A12

PCH_SML0CLK

PCH_SML0DATA

G12

PCH_GPIO74

C13

PCH_SML1CLK

E14

PCH_SML1DATA

M16

T11

P10

GPIO23_CLKREQB_R

M10

AB37

CLK_PCIE_VGA_R

AB38

CLK_CPU_DMI#

AV22

CLK_CPU_DMI

AU22

AM12 AM13

CLK_BUF_CPU_DMI#

BF18

CLK_BUF_CPU_DMI

BE18

CLKIN_DMI2#

BJ30

CLKIN_DMI2

BG30

CLK_BUF_DREF_96M#

G24

CLK_BUF_DREF_96M

E24

CLK_BUF_PCIE_SATA#

AK7

CLK_BUF_PCIE_SATA

AK5

CLK_BUF_ICH_14M

K45

CLK_PCI_LPBACK

H45

XTAL25_IN

V47

XTAL25_OUT

V49

XCLK_RCOMP

Y47

K43 F47 H47 K49

10K_0402_5%

R148

EC_LID_OUT# (37)

1K_0402_5%

1K_0402_5% R152

R152 10K_0402_5%

10K_0402_5%

R153

+3VALW

R156

R156 10K_0402_5%

10K_0402_5%

1 2

PX@

R159 0_0402_5%

1 2

R161 0_0402_5%

1 2

PX@

CLK_CPU_DMI# (5) CLK_CPU_DMI (5)

R168 10K_0402_5%R168 10K_0402_5%

1 2

R170 10K_0402_5%R170 10K_0402_5%

1 2

R172 10K_0402_5%R172 10K_0402_5%

1 2

R174 10K_0402_5%R174 10K_0402_5%

1 2

R177 10K_0402_5%R177 10K_0402_5%

1 2

R178 10K_0402_5%R178 10K_0402_5%

1 2

R181 10K_0402_5%R181 10K_0402_5%

1 2

R183 10K_0402_5%R183 10K_0402_5%

1 2

R185 10K_0402_5%R185 10K_0402_5%

1 2

CLK_PCI_LPBACK (16)

R189

90.9_0402_1%

1 2

+3VALW

DRAMRST_CNTRL_PCH (6)

+3VALW

+3VALW +3VS

PCH_SML0CLK PCH_SML0DATA

R157

0_0402_5%

1 2

R15810K_0402_5% R15810K_0402_5%

+1.05VS_VCCDIFFCLKN

2.2K_0402_5%

2.2K_0402_5% 1 2

+3VALW

1 2

2.2K_0402_5%

1 2 1 2

2.2K_0402_5%

2.2K_0402_5% R206

R206

2.2K_0402_5%

2.2K_0402_5% R250

R250

GPIO23_CLKREQB (23)

CLK_PCIE_VGA#CLK_PCIE_VGA#_R CLK_PCIE_VGA

BUF_PLT_RST#(16,32,33,37,43)

R149

R151

R154

R155

12 12

XTAL25_IN XTAL25_OUT

Q2A

Q2A 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

3 4

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6 Q2B

Q2B

Q10A

Q10A 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

3 4

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6 Q10B

Q10B +3VALW +3VALW

CLK_PCIE_VGA# (21)

CLK_PCIE_VGA (21)

ROM_A0 ROM_A1 ROM_A2

R187 1M_0402_5%R187 1M_0402_5%

25MHZ_20PF_7A25000012

C235

27P_0402_50V8J

SMB_CLK_S3

2.2K_0402_5%

2.2K_0402_5% 1 2

+3VS

1 2

2.2K_0402_5%

2.2K_0402_5% SMB_DATA_S3

EC_SMB_CK2

2 5

EC_SMB_DA2

R298

R298 10K_0402_5%

10K_0402_5%

R305

R305 10K_0402_5%

10K_0402_5%

U32

GND

AT24C08BN-SH-T_SO8

EEPROM ROHM PCA24S08D: SA00004ML00

+3VS

123

1 2

R204

R204 0_0402_5%

0_0402_5%

1 2

SMB_CLK_S3 (10,11,32)

DIMM1

R150

DIMM2

R147

MINI CARD

SMB_DATA_S3 (10,11,32)

EC_SMB_CK2 (23,37,38)

VGA EC thermal sensor

EC_SMB_DA2 (23,37,38)

+3VS +3VS+3VS

ROM_A1 ROM_A0ROM_A2

VCC

ROM_WP

SMB_CLK_S3

SCL

SMB_DATA_S3

SDA

Q80

@ 2N7002_SOT23

2N7002_SOT23

ROM_A2

C236

C236 27P_0402_50V8J

27P_0402_50V8J

R301

R301 10K_0402_5%

10K_0402_5%

R302

R302 10K_0402_5%

10K_0402_5%

1201

R304

R304 10K_0402_5%

10K_0402_5%

R303

R303 10K_0402_5%

10K_0402_5%

+3VS

C696

0.1U_0402_16V4Z

R196@

33_0402_5%

A A

CLK_PCI_LPBACK

33_0402_5%

C238@

22P_0402_50V8J

1 2

Reserve for EMI please close to PCH

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/25

Compal Secret Data

Deciphered Date

2012/08/25

Compal Electronics, Inc.

Title

SCHEMATICS,MB A6921

Size Document Number Rev

Custom

4019A1

Date: Sheet of

Thursday, January 20, 2011

D D

+3VS

PCH_POK(37)

VGATE(53)

C C

SYS_PWROK_EC(37)

+3VALW

B B

R216

R216 10K_0402_5%

10K_0402_5%

+3VALW

R256

R256 200_0402_5%

200_0402_5%

MC74VHC1G08DFT2G SC70 5P

1 2

R213

R213 10K_0402_5%

10K_0402_5%

R214

100K_0402_1%

SYS_PWROK

R200

R200 100K_0402_1%

100K_0402_1%

R255

R255 0_0402_5%

0_0402_5%

SYS_PWROK

SUSWARN# ACIN_R

PCH_RSMRST#_R

PM_DRAM_PWRGD

SYS_PWROK (5)

10/18

SUSACK# is only used on platform that support the Deep Sx state.

XDP_DBRESET#(5,12)

PCH_APWROK(37)

PM_DRAM_PWRGD(5)

EC_RSMRST#(12,37)

SUSWARN#(37)

PBTN_OUT#(5,12,37)

ACIN(23,37,43,45)

DMI_CTX_PRX_N0(4) DMI_CTX_PRX_N1(4) DMI_CTX_PRX_N2(4) DMI_CTX_PRX_N3(4)

DMI_CTX_PRX_P0(4) DMI_CTX_PRX_P1(4) DMI_CTX_PRX_P2(4) DMI_CTX_PRX_P3(4)

DMI_CRX_PTX_N0(4) DMI_CRX_PTX_N1(4) DMI_CRX_PTX_N2(4) DMI_CRX_PTX_N3(4)

DMI_CRX_PTX_P0(4) DMI_CRX_PTX_P1(4) DMI_CRX_PTX_P2(4) DMI_CRX_PTX_P3(4)

+1.05VS_PCH

1 2

R197 49.9_0402_1%R197 49.9_0402_1%

1 2

R199 750_0402_1%R199 750_0402_1%

4mil width and place within 500mil of the PCH

+3VS

PCH_POK PCH_POK_R

R210

1 2

@ 0_0402_5%

1 2 1 2

R218

R218 0_0402_5%

0_0402_5%

+3VALW

T52 PADT52 PAD

R203

R203 10K_0402_5%

10K_0402_5%

SYS_PWROK

11/24

D1 RB751V_SOD323

RB751V_SOD323

R219

1 2

8.2K_0402_5%

R220

R220 10K_0402_5%

10K_0402_5%

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

DMI_IRCOMP RBIAS_CPY

SUSACK#

APWROK

R209

R209 0_0402_5%

0_0402_5%

PM_DRAM_PWRGD

PCH_RSMRST#_R

SUSWARN#_R

PBTN_OUT#_R

ACIN_R

PCH_GPIO72

RI#

U6C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN# / SUS_PWR_DN_ACK / GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

COUGARPOINT_FCBGA989

FDI_CTX_PRX_N0

BJ14

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5

DMI

System Power Management

FDI_RXP6

FDI

FDI_RXP7

FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AW16 AV12 BC10 AV14 BB10

A18

PCH_DPWROK_R

E22

N14

D10

G10

G16

AP14

K14

FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

DSWODVREN

WAKE#XDP_DBRESET#

PM_CLKRUN#

SUS_STAT#

SUSCLK

SLP_S5#

SLP_S4#

SLP_S3#

PM_SLP_SUS#

H_PM_SYNC

PCH_GPIO29

11/24

1 2

R201

1 2

0_0402_5%

1 2

T55

T55 PAD

PAD

T56

T56 PAD

PAD

FDI_CTX_PRX_N0 (4) FDI_CTX_PRX_N1 (4) FDI_CTX_PRX_N2 (4) FDI_CTX_PRX_N3 (4) FDI_CTX_PRX_N4 (4) FDI_CTX_PRX_N5 (4) FDI_CTX_PRX_N6 (4) FDI_CTX_PRX_N7 (4)

FDI_CTX_PRX_P0 (4) FDI_CTX_PRX_P1 (4) FDI_CTX_PRX_P2 (4) FDI_CTX_PRX_P3 (4) FDI_CTX_PRX_P4 (4) FDI_CTX_PRX_P5 (4) FDI_CTX_PRX_P6 (4) FDI_CTX_PRX_P7 (4)

FDI_INT (4) FDI_FSYNC0 (4) FDI_FSYNC1 (4) FDI_LSYNC0 (4) FDI_LSYNC1 (4)

PCH_RSMRST#_R

R251

1 2

@ 0_0402_5%

R205

R205 10K_0402_5%

10K_0402_5%

R207

8.2K_0402_5%

T57

T57 PAD

PAD

T54PAD T54PADD1

H_PM_SYNC (5)

PCIE_WAKE# (32,33)

+3VALW

T53PAD T53PAD

+3VS

SUSCLK (37)

SLP_S5# (37)

SLP_S4# (37)

SLP_S3# (37)

+RTCVCC

R198

R198 330K_0402_5%

330K_0402_5%

R202

R202 330K_0402_5%

PCH_DPWROK (37)

Can be left NC when IAMT is not support on the platfrom

Can be left NC if no use integrated LAN.

330K_0402_5% @

DSWODVREN - On Die DSW VR Enable

：

Enable

：

Disable

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/25

Compal Secret Data

Deciphered Date

2012/08/25

Compal Electronics, Inc.

Title

SCHEMATICS,MB A6921

Size Document Number Rev

Custom

4019A1

Thursday, January 20, 2011

Date: Sheet of

D D

2.2K_0402_5%

EDID_CLK EDID_DATA

C C

B B

2.2K_0402_5%

CRT_DDC_CLK CRT_DDC_DATA

R232

R221

+3VS

R222

2.2K_0402_5%

DAC_BLU(30)

DAC_GRN(30)

DAC_RED(30)

R233

2.2K_0402_5%

+3VS

PCH_ENBKL(29,37) PCH_ENVDD(29)

PCH_PWM(29)

EDID_CLK(29)

R225 2.2K_0402_5%R225 2.2K_0402_5% R226 2.2K_0402_5%R226 2.2K_0402_5%

EDID_DATA(29)

1 2 1 2

R227

2.37K_0402_1%

R228

R228 0_0402_5%

0_0402_5%

LVDS_ACLK#(29) LVDS_ACLK(29)

LVDS_A0#(29) LVDS_A1#(29) LVDS_A2#(29)

LVDS_A0(29) LVDS_A1(29) LVDS_A2(29)

R229 150_0402_1%R229 150_0402_1%

R230 150_0402_1%R230 150_0402_1%

R231 150_0402_1%R231 150_0402_1%

CRT_DDC_CLK(30) CRT_DDC_DATA(30)

CRT_HSYNC(30) CRT_VSYNC(30)

DAC_BLU

DAC_GRN

DAC_RED

1K_0402_1%

PCH_ENBKL PCH_ENVDD

EDID_CLK EDID_DATA

R234

CTRL_CLK CTRL_DATA

LVDS_IBG

LVD_VREF

CRT_DDC_CLK CRT_DDC_DATA

CRT_IREF

U6D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

COUGARPOINT_FCBGA989

SDVO_INTN SDVO_INTP

DDPB_HPD

DDPB_0N

DDPB_0P

DDPB_1N

DDPB_1P

DDPB_2N

DDPB_2P

DDPB_3N

DDPB_3P

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN

CRT

DDPD_AUXP

R223

2.2K_0402_5%

HDMICLK_NB HDMIDAT_NB

TMDS_B_DATA2#_PCH TMDS_B_DATA2_PCH TMDS_B_DATA1#_PCH TMDS_B_DATA1_PCH TMDS_B_DATA0#_PCH TMDS_B_DATA0_PCH TMDS_B_CLK#_PCH TMDS_B_CLK_PCH

+3VS

R224

2.2K_0402_5%

TMDS_B_HPD# (31)

HDMICLK_NB (31) HDMIDAT_NB (31)

C239 0.1U_0402_10V6KC239 0.1U_0402_10V6K

1 2

C240 0.1U_0402_10V6KC240 0.1U_0402_10V6K

1 2

C241 0.1U_0402_10V6KC241 0.1U_0402_10V6K

1 2

C242 0.1U_0402_10V6KC242 0.1U_0402_10V6K

1 2

C243 0.1U_0402_10V6KC243 0.1U_0402_10V6K

1 2

C244 0.1U_0402_10V6KC244 0.1U_0402_10V6K

1 2

C245 0.1U_0402_10V6KC245 0.1U_0402_10V6K

1 2

C246 0.1U_0402_10V6KC246 0.1U_0402_10V6K

1 2

HDMI_TX2-_CK (31) HDMI_TX2+_CK (31) HDMI_TX1-_CK (31) HDMI_TX1+_CK (31) HDMI_TX0-_CK (31) HDMI_TX0+_CK (31) HDMI_CLK-_CK (31) HDMI_CLK+_CK (31)

HDMI

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/25

Compal Secret Data

Deciphered Date

2012/08/25

Compal Electronics, Inc.

Title

SCHEMATICS,MB A6921

Size Document Number Rev

Custom

4019A1

Thursday, January 20, 2011

Date: Sheet of

+3VS

RP1

PCI_PIRQA#

8 7 6

8.2K_0804_8P4R_5%

D D

WL_OFF#

C C

8.2K_0804_8P4R_5%

8 7 6

8.2K_0804_8P4R_5%

R235 8.2K_0402_5%R235 8.2K_0402_5%

1 2

R236 8.2K_0402_5%R236 8.2K_0402_5%

1 2

R237 8.2K_0402_5%R237 8.2K_0402_5%

1 2

R238 8.2K_0402_5%R238 8.2K_0402_5%

1 2

R239

1 2

R240 @ 1K_0402_5%R240 @ 1K_0402_5%

A16 swap overide Strap/Top-Block Swap Override jumper

PCI_GNT3#

GPIO53=This Signal has a weak internal pull-up. NOTE: The internal pull-up is disabled after PLTRST# deasserts.

B B

PCH_GPIO51

R247 @ 1K_0402_5%R247 @ 1K_0402_5%

PCI_PIRQD#

PCI_PIRQC#

PCI_PIRQB#

RP2

PCH_GPIO2

PCH_GPIO54

PCH_GPIO4

ODD_DA#

WL_OFF#

PCH_GPIO52 PCH_GPIO5 PCH_GPIO50

8.2K_0402_5%R239

8.2K_0402_5%

1 2

Low=A16 swap override/Top-Block Swap Override enabled High=Default

1 2

PCH_GPIO50

PE_GPIO0(13,21)

PE_GPIO1(13,28,52)

CLK_PCI_LPBACK(13)

CLK_PCI_LPC(37)

CLK_PCI_DB(43)

Boot BIOS Strap bit1 BBS1

GPIO19

Bit10

0 1 0

Boot BIOS Destination

Reserved Reserved SPI

LPC

(Default)

BUF_PLT_RST#(13,32,33,37,43)

GPIO51

Bit11

01 1 1 0

A A

11/24

PX@

1 2

R252 0_0402_5%

1 2

R254 0_0402_5%

PX@

WL_OFF#(32)

ODD_DA#(42)

PCI_PME#(37) PLT_RST#(5,21)

R245 22_0402_5%R245 22_0402_5%

1 2 1 2

R246 22_0402_5%R246 22_0402_5%

1 2

R192

R192 22_0402_5%

22_0402_5%

1U_0402_6.3V4Z

CLK_PCI_DB_R

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

PCH_GPIO50 PCH_GPIO52 PCH_GPIO54

PCH_GPIO51 PCH_GPIO53 WL_OFF#

PCH_GPIO2 ODD_DA# PCH_GPIO4 PCH_GPIO5

PLT_RST#

CLK_PCI_LPBACK_R CLK_PCI_LPC_R

C247

C247 @

BG26

BJ26

BH25

BJ16 BG16 AH38 AH37 AK43 AK45

C18 N30

AH12

AM4 AM5

Y13 K24

AB46 AB45

B21

M20 AY16 BG46

BE28 BC30 BE32

BJ32 BC28 BE30 BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28

AW30

K40 K38 H38 G38

C46 C44 E40

D47 E42

G42 G40 C42 D44

K10

H49 H43

K42 H40

R249

R249 100K_0402_5%

100K_0402_5%

L24

F46

J48

U6E

TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11

TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20

TP21 TP22 TP23 TP24

TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40

PIRQA# PIRQB# PIRQC# PIRQD#

REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54

GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55

PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5

PME#

PLTRST#

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

COUGARPOINT_FCBGA989

1 2

R248

R248 0_0402_5%

0_0402_5%

+3VS

NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8 NV_DQ9 / NV_IO9

NV_DQ10 / NV_IO10

NVRAM

NV_DQ11 / NV_IO11 NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14

PCI

USB

PLT_RST#

NV_DQ15 / NV_IO15

NV_RE#_WRB0 NV_RE#_WRB1

NV_WE#_CK0 NV_WE#_CK1

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43

OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

RSVD

2 1

MC74VHC1G08DFT2G SC70 5P

NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3

NV_DQS0 NV_DQS1

NV_ALE NV_CLE

NV_RCOMP

NV_RB#

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P

USBP10N

USBP10P

USBP11N

USBP11P

USBP12N

USBP12P

USBP13N

USBP13P

USBRBIAS#

USBRBIAS

AY7 AV7 AU3 BG4

AT10 BC8

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

AV5

NV_CLE

AY1 AV10 AT8 AY5

BA2 AT12

BF3

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

C33

B33

A14 K20 B17 C16 L16 A16 D14 C14

USB DEBUG=PORT1 AND PORT9

USB20_N0 USB20_P0 USB20_N1 USB20_P1

USB20_N4 USB20_P4 USB20_N5 USB20_P5

0715 Port6, Port7 HM65 doesn't support

USB20_N8 USB20_P8

USB20_N9 USB20_P9

USB20_N13 USB20_P13

USBRBIAS

USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4# USB_OC5# USB_OC6# USB_OC7#

USB20_N0 (40) USB20_P0 (40) USB20_N1 (40) USB20_P1 (40)

USB20_N5 (29) USB20_P5 (29)

USB20_N12 (43) USB20_P12 (43) USB20_N13 (40) USB20_P13 (40)

1 2

R244 22.6_0402_1%R244 22.6_0402_1%

USB20_N4 (32) USB20_P4 (32)

USB20_N8 (32) USB20_P8 (32)

USB20_N9 (40) USB20_P9 (40)

USB_OC0# (40)

USB_OC4# (40)

USB (COMBO)

USB

WWAN

USB Camera

WLAN

Finger Printer Bluetooth

USB charger

DMI Termination Voltage

NV_CLE

Set to Vcc when HIGH Set to Vss when LOW

R242

4.7K_0402_5%

4.7K_0402_5% 12

CLOSE TO THE BRANCHING POINT

USB_OC0# USB_OC2# USB_OC7# USB_OC5#

USB_OC1# USB_OC4# USB_OC3# USB_OC6#

10K_1206_8P4R_5%

+1.8VS

R241

R241 1K_0402_5%

1K_0402_5%

+3VALW

RP3

RP3 4 5 3

RP4

RP4 4 5 3

10K_1206_8P4R_5%

H_SNB_IVB# (5)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/25

Compal Secret Data

Deciphered Date

2012/08/25

Compal Electronics, Inc.

Title

SCHEMATICS,MB A6921

Size Document Number Rev

Custom

4019A1

Thursday, January 20, 2011

Date: Sheet of

D D

+3VS

R300

+3VALW

10/14

PCH_GPIO27

PCH_GPIO37

R300

+3VS

ODD_DETECT#(42)

+3VALW

+3VS

1 2

0_0402_5%

ICC_EN#

Integrated Clock Chip Enable

H ; Disable L ; Enable

R259

1 2

1K_0402_5%R259

1K_0402_5%

EC_SMI#

ESATA_DET#(40)

Weak internal pull-high

1 2

R557

10K_0402_5%

ESATA_DET#(40)

BT_OFF#(40)

R283

R283 0_0402_5%

0_0402_5%

GPIO28

On-Die PLL Voltage Regulator This signal has a weak internal pull up

：

On-Die voltage regulator enable

L：On-Die PLL Voltage Regulator disable

R270 @ 1K_0402_5%R270 @ 1K_0402_5%

1 2

C C

R280

R280 10K_0402_5%

10K_0402_5%

R295

1 2

mSATA_PH(37)

10K_0402_5%R295

10K_0402_5%

+3VS

B B

mSATA_DET#(32)

PCH_GPIO28

ODD_DETECT#

R275

R275 10K_0402_5%

10K_0402_5%

1 2

R253 10K_0402_5%R253 10K_0402_5%

1 2

R257 10K_0402_5%R257 10K_0402_5%

1 2

R258 10K_0402_5%R258 10K_0402_5%

1 2

R261 10K_0402_5%R261 10K_0402_5%

1 2

R262 1K_0402_5%R262 1K_0402_5%

1 2

R279

1 2

@ 0_0402_5%

R264 10K_0402_5%R264 10K_0402_5%

1 2

R268 10K_0402_5%R268 10K_0402_5%

1 2

+3VALW

R271

10K_0402_5%

1 2

10K_0402_5%

1 2

R272

R273 10K_0402_5%R273 10K_0402_5%

1 2

ODD_DETECT#

R274 10K_0402_5%

1 2

R276 10K_0402_5%R276 10K_0402_5%

1 2

R277 10K_0402_5%R277 10K_0402_5%

1 2

R278 10K_0402_5%R278 10K_0402_5%

1 2

R294 10K_0402_5%R294 10K_0402_5%

1 2

R281 10K_0402_5%R281 10K_0402_5%

1 2

PCH_GPIO69 PCH_GPIO70 PCH_GPIO71

TACH4 / GPIO68 TACH5 / GPIO69 TACH6 / GPIO70 TACH7 / GPIO71

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

INIT3_3V#

NC_1 NC_2 NC_3 NC_4 NC_5

VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31 VSS_NCTF_32

+3VS

PCH_GPIO68

C40

PCH_GPIO69

B41

PCH_GPIO70

C41

PCH_GPIO71

A40

PCH_PECI_R

AU16

KB_RST#

P5 AY11

PCH_THRMTRIP#_R

AY10 T14

AH8 AK11 AH10 AK10 P37

BG2 BG48 BH3 BH47 BJ4 BJ44 BJ45 BJ46 BJ5 BJ6 C2 C48 D1 D49 E1 E49 F1 F49

0 1

0_0402_5% R263

0_0402_5%

BT_DET#

R267 10K_0402_5%R267 10K_0402_5%

BT_DET#(40)

KB_RST#

PCH_GPIO0

PCH_GPIO1 PCH_GPIO6

10/13

EC_SCI# EC_SMI# CPUSB# PCH_GPIO15

ESATA_DET#_R

PCH_GPIO22 ODD_EN# PCH_GPIO27 PCH_GPIO28 BT_OFF# PCH_GPIO35

PCH_GPIO37 3G_DET#

11/30

PCH_GPIO39 PCH_GPIO48 PCH_GPIO49 PCH_GPIO57

BT_DET#

EC_SCI#(37) EC_SMI#(37)

ODD_EN#(42)

U6F

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

LAN_PHY_PWR_CTRL / GPIO12

GPIO15

SATA4GP / GPIO16

D40

TACH0 / GPIO17

SCLOCK / GPIO22

GPIO24 / MEM_LED

E16

GPIO27

GPIO28

STP_PCI# / GPIO34

GPIO35

SATA2GP / GPIO36

SATA3GP / GPIO37

SLOAD / GPIO38

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

SATA5GP / GPIO49

GPIO57

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

VSS_NCTF_5

VSS_NCTF_6

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

COUGARPOINT_FCBGA989

1 2

R266 10K_0402_5%R266 10K_0402_5%

1 2

GPIO

CPU/MISC

NCTF

0 1

1 2

R263

1 2

R269 390_0402_5%R269 390_0402_5%

0 0

H_PECI (5,37) KB_RST# (37) H_CPUPWRGD (5)

H_THRMTRIP#

+3VS

INIT3_3V

This signal has weak internal PU, can't pull low

Intel schematic reviwe recommand.

Function

UMA

PX4.0

R260

R260 10K_0402_5%

10K_0402_5%

1 2

PCH_GPIO68 PCH_GPIO69 PCH_GPIO70

PCH_GPIO71

GATEA20 (37)

H_THRMTRIP# (5) VGA_THRMTRIP# (23)

R1942

R1946

10K_0402_5%

1 2

R1945

1 2

10K_0402_5%

R1943

1 2 PX@

PX@

10K_0402_5%

1 2

UMA@

10K_0402_5%

R1947

UMA@

+3VS

R1944

1 2 PX@

PX@

10K_0402_5%

1 2

10K_0402_5%

R293

1 2

R287

10K_0402_5%

A A

3G_DET#(32)

11/30

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/25

Compal Secret Data

Deciphered Date

2012/08/25

Compal Electronics, Inc.

Title

SCHEMATICS,MB A6921

Size Document Number Rev

Custom

4019A1

Thursday, January 20, 2011

Date: Sheet of

+ 38 hidden pages