COMPAL LA-5251P Schematics

A

1 1

B

C

D

E

Compal Confidential

Schematics Document

2 2

INTEL Auburndale BGA with IBEX core logic

Swatch UMA

3 3

LA-5251P

2010-01-04

REV:0.9

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/09/15 2010/12/31

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

LA-5251P

E

1 47Tues day, January 05, 2010

0.9

A

Compal Confidential

File Name : LA-5251P

B

C

Swatch UMA

D

XDP Conn.

Page 4

E

Accelerometer

LI S30 2DLTR

1 1

Display port panel

Page 20

PEG-eDP

Mobile

Auburndale CPU

BG A 1288pins

DD R3-SO-DIMM X 2DDR3 1066/1333MHz 1.5V

BANK 0 , 1, 2, 3

Fan Control

Page 9,10

Page 24

Page 4

Dual Channel

VGA

Page 18

Display port

2 2

Express Card 54

PCIE *1 + USB *1

Page 23

10/100/1 000 LAN
Intel Hanksville GbE

PHY

Page 21

Page 18

WLAN Card

PCIE*1

Page 22

WWAN
+SIM Card

USB*1

Ri co R5C835

RGB

DDI_D

Page 23

USB2.0

PCI-E BUS

Controller

Page 25

DDI

PCI BUS

FDI

Intel Ibex Peak M

10 71pi ns

25mm*27mm

Page 12,13,14,15,16,17

Br aidwood

RJ45 CONN

3 3

Page 21

1394 port

Page 25

Smart Card

Page 25

SD/MM C Slot

Page 32

Page 4,5,6,7,8

DM I X4

ONFI Interface

Page 23

DDI_B

USB2.0

Azalia

SATA0

SATA1

SATA3

DP *1(Docking)

Page 29

USB *1(Docking)

Page 29

USB conn*1(Left side)

Page 24

FingerPrinter Validity VFS451
USB*1

Page 32

USB conn x 3(For I/O)-Rear side, Power USB

BT Conn USB x 1

USB x1(Camara)

MD C V1.5

Page 20

Page 28

Audio CKT

IDT 92HD75

SATA ODD Connector

Page 26

Page 22

AMP & Audio Jack

Thermal Se nsor
EMC 2 113

Page 4

CK505

Clock Generator
SL G8SP5 85V TR

Page 11

daughter board Module

Page 24

RJ11

Page 28

TPA6047A4RHBR

Page 27

NAND F lash Card

Page 23

LPC BUS

1.8" SAT A HDD Connector

Page 22

RTC CKT.

Page 12

Power OK CKT.

4 4

Power On/Off CKT.

Page 33

Page 28

LED

LED Board

Page 28

Touch Pad CONN.

Page 28

SMSC KBC 1098

page 30

Int.KBD

Page 28

TPM1.2

SLB9635TT

Page 32

SATA*1(Doc king)

Page 29

Page 29

Docking CONN.

(2) USB 1.channels
(1) Display Port Channels
(1) Line In
(1) Line Out
(1) RJ45 (10/100/1000)
(1) V GA
(1) 2 LAN indicator LED's
(1) Power Button
(1) SATA

TrackPoint CONN.

DC/DC Interface CKT.

Page 34

A

SP I ROM

Page 28

8 M B

Page 31

B

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/09/15 2010/12/31

Compal Secret Data

Deciphered Date

D

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

LA-5251P

E

2 47Tues day, January 05, 2010

0.9

A

Voltage Rails

State

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

1 1

( O MEANS ON X MEANS OFF )

+RTCVCC

power
plane

O

O

O

O

O

O

+B

+3VL +0.75V

O

O

O

O

O

X

+5VALW

+3VALW

O

O

O

O

X

X X X

+3VM

+1.05VM

O

O

O

O

X

X

+1.5V

O

X X

X

+5VS

+3VS

+1.5VS

+VCCP

+CPU_CORE

+1.05VS

+1.8VS

OO

OO

X

X

Symbol Note :

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build
CONN@ : means ME part.
SV@ : means just build on SV Sku. LV Sku no build.
LV@ : means just build on LV Sku. SV Sku no build.

Lay out Note s

L

01/ 04 up da te

: Q ues ti on Are a Mark. (Wa it ch eck )

Install below 45 level BOM structure for ver. 0.1

45@ : means just put it in the BOM of 45 level.

Install below 43 level BOM structure for ver. 0.1

DEBUG@ : means just build when PCIE port 80 CARD function enable.

Remove before MP

SMBUS Control Table

SOURCE

SMB_EC_CK1
SMB_EC_DA1

SMBCLK
SMBDATA

SML0CLK
SML0DATA

SML1CLK
SML1DATA

SMSC1098

Calpella

Calpella

Calpella

BATT

V

X
X
X

THERMAL

SODIMM CLK CHIP

XDP G-SENSOR

X

X X

V V

X

X

X X

MINI CARD

X

V V

X

X

X X

DOCK

X

V

X
X

SENSOR

NIC

X X
X

V

X

X
X

V

X

V

X

V

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/09/15 2010/12/31

A

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

Notes List

LA-5251P

3 47Tues day, January 05, 2010

0.9

1 2

1.5K _0402 _1%

1 2

1 2

1 2

1 2

1

1 2

1 2

1 2

1 2

T48PA D

R1 4

1 2

0_02 01_5%

R1 5

1 2

0_02 01_5%

R1 7

1 2

0_02 01_5%

R1 8

1 2

0_02 01_5%

R1 9

1 2

0_02 01_5%

R2 1

0_02 01_5%

R2 2

1 2

0_02 01_5%

R2 6

1 2

0_02 01_5%

R3 2

1 2

1 2

750_ 0402_1%

R2 01 K_02 01_5%@

H_CO MP3

R220_0 402_1%

H_CO MP2

R520_0 402_1%

H_CO MP1

R749.9 _0402 _1%

H_CO MP0

R949.9 _0402 _1%

TP_ SKTOCC#

H_ CATE RR#

H_P ECI_I SO

H_ PRO CHOT# _D

H_T HERM TRIP# _R

H_ CPUR ST#_ R

H_ PM_ SYNC _R

SYS _AGE NT_P WROK

VC CPW RGOO D_0

VD DPW RGO OD_R

0_02 01_5%

H_ PWRG D_XD P_RH_P WRGD _XDP

PLT _RST#_R

R3 3

12

R3 5

+VC CP

AD71

AC70

AD69

AE66

M71

N61

N19

N67

N17

N70

M17

AM7

Y67

AM5

H15

Y70

G3

VD DPW RGO OD_R

Processor Pullups

H_ PRO CHOT# _D

H_ CPUR ST#_ R

U1 B

COMP3

COMP2

COMP1

COMP0

PROC_DETECT

CATERR#

PECI

PROCHOT#

THERMTRIP#

RESET_OBS#

PM_SYNC

VCCPWRGOOD_1

VCCPWRGOOD_0

SM_DRAMPWROK

VTTPWRGOOD

TAPPWRGOOD

RSTIN#

INT EL_A UBURN DALE _1288

07 /08 u pda te fo r I NTEL S3 le aka ge issue.
07 /1 7 upd at e f or va lue chan ge back

1 2

R1 2 1.5K _0402_1%

1 2

R1 3 750_0 402_1%

R4 4 49.9_0 402_1%

1 2

1 2

R4 5 68_040 2_5%

1 2

R4 7 68_040 2_5%@

Misc

Thermal Power Management

Layout rule 1 0mil w idth ：trace
length < 0.5 ", spa cing 20mil

A A

H_ PECI15

to power; PU to VCCP at power side also

H_ PROCH OT#40

H_T HERM TRIP#15

H_ CPUR ST#

H_ PM_S YNC14

H_ CPU PW RGD

H_ CPU PW RGD1 5

B B

PM_ DRAM _PWR GD14

from power

VTT PWRG OOD32

BUF _PLT_R ST#1 5

PM_ PWRB TN#_R

C C

DDR3 Compensation Signals

SM_ RCOMP0

R5 2 100_02 01_1%

SM_ RCOMP1 H_C ATER R#

R5 6 24.9_0 402_1%

SM_ RCOMP2

R5 8 130_04 02_1%

Layout Note:Please these
resist ors near Processor

11 /06 Ca ncel REM OTE ther mal senso r res erve .

D D

1

2

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

Clocks

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

PM_EXT_TS#[0]
PM_EXT_TS#[1]

DDR3

Misc

JTAG & MBP

VC CP_1. 5VSP WRG D 32

+VC CP

2

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

PRDY#
PREQ#

TRST#

TDI_M

TDO_M

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

DBR#

CLK _CPU_ XDP

K71

CLK _CPU_ XDP#

J70

CLK_EX P

L21

CLK_ EXP#

J21

Y2
W4

SM_ DRAMR ST#

BJ12

SM_ RCOMP0

BV33

SM_ RCOMP1

BP39

SM_ RCOMP2

BV40

PM_EXTTS#0

AV66

PM_EXTTS#1

AV64

XDP _PRD Y#

U71

XDP _PREQ#

U69

XDP _TCK

T67

TCK

XDP_TMS

N65

TMS

XDP_TR ST#

P69

XDP _TDI

T69

TDI

XDP _TDO

T71

TDO

XDP _TDI_M

P71
T70

XDP _DBRES ET#

W71

XDP_B PM#0

J69

XDP_B PM#1

J67

XDP_B PM#2

J62

XDP_B PM#3

K65

XDP_B PM#4

K62

XDP_B PM#5

J64

XDP_B PM#6

K69

XDP_B PM#7

M69

C1 20

0.1U _0402 _16V4Z

CL K_CP U_BC LK

AK7

BCLK

CLK _CPU_ BCLK #

AK8

DDR Pullups

PM_EXTTS#0

1 2

R1 10K _0201_5%

PM_EXTTS#1

1 2

R3 10K _0201_5%

011 2 R em ove unin stall part s

XDP_TR ST#

1 2

R5 9 51_04 02_5%

Close to XDP

XDP _TDO

1 2

R1 0 51_04 02_5%

This s hall place near XDP

CLK _CPU_ BCLK 15
CLK _CPU_ BCLK # 15

CLK_EX P 13
CLK_EX P# 13

CL K_DP 13
CLK _DP# 1 3

T49 PAD

1 2

R1 60_0201_5%

C1

0.1U _0402 _16V4Z

@

1

1

2

2

Ad d C119 be twe en JP4 p in 37 an d 41;

L

Add C120 close to R 20.1

1

2

PM_ PWRB TN#_R

C1 19

0.1U _0402 _16V4Z

+V CCP

+V CCP

PM_EX TTS#1_R 9, 10

CF G125

CF G135

CF G145

CF G155

+VC CP

01/ 04 up dat e for ESD

3

from DDR

XDP_B PM#0

R2 3 0_02 01_5%
R2 4 0_02 01_5%@

XDP_B PM#1

R2 5 0_02 01_5%
R2 7 0_02 01_5%@

XDP_B PM#2

R2 8 0_02 01_5%
R2 9 0_02 01_5% @

XDP_B PM#3

R3 0 0_02 01_5%

XDP_B PM#4
XDP_B PM#5

XDP_B PM#6
XDP_B PM#7

R3 1 0_02 01_5% @

H_ CPU PW RGD

H_P WRGD _XDP

ESD re que st to add

PM_ PWRB TN#_R14

011 2 A dd test poin ts

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

4

07 /09 u pda te fo r I NTEL S3 le aka ge issue.

+1.5 V

R1 093

12

SM_ DRAMR ST#

R1 092

12

100K _0402_5 %@

07 /17 u pd ate

XDP _PREQ#

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

R3 6 1K_02 01_5%

+3VS

1 2

XDP _PRD Y#

CF G175
CF G165

1 2
1 2

1 2
1 2

1 2

1 2

R3 7 0 _0201 _5%

XDP _BPM#4_R

R4 30_02 01_5%

XDP _BPM#5_R

R4 80_02 01_5%

XDP _BPM#6_R

R4 00_02 01_5%

XDP _BPM#7_R

R4 10_02 01_5%

H_ CPU PW RGD_ R
PM_ PWRB TN#_R

T112PA D
T113PA D

XDP _TCK

Thermal Sensor EMC2113 with CPU PWM FAN

R5 0
68_0 402_5%

+3V S_THER

C4

1

0.1U _0402 _16V4Z

2

+3VS

H_T HERM TRIP#

C3 2200 P_0402_ 50V7K

+3VS

R7 1 10K_0 201_5%

THE RM_S CI#15

1 2

R6 2 10K_ 0201_5%

1 2

R6 3 0_020 1_5%

2008/09/15 2010/12/31

CPU XDP Connector

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

H_ THE RMDC

H_T HERM DA

1 2

FA N_PW M_R

1 2

@

Compal Secret Data

1K_ 0402_5%

61

Q52A

2N70 02DW H 2N SOT3 63-6

2

C6 .1U_ 0402_ 16V7K

1 2

08 /28 u pd ate

JP4

GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16

SAM TE_BSH- 030-01-L-D -A CO NN@

U2

1

DN

2

DP

3

VDD

4

PWM_IN

5

ADDR_SEL

6

ALERT#

7

SYS_SHDN#

8

SMDATA

Add 0 ohm and 0.1u

OBSFN_C0
OBSFN_C1

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND

EMC 2113- 1-AP -TR QFN 16P

17

DRA MRST# 9,10

PC H_D DR_RS T 15

GND1

GND3

GND5

GND7

GND9

GND11

GND13

GND15

TD0

TRST#

TMS

GND17

DP2/DN3

DN2/DP3

TRIP_SET

SHDN_SEL

SMCLK

Deciphered Date

4

TDI

GND

PWM

TACH

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38

CLK _CPU_ XDP

40

CLK _CPU_ XDP#

42
44

XDP _RST#_R

46

XDP _DBR ESET#_R

48
50

XDP _TDO

52

XDP_TR ST#

54

XDP _TDI

56

XDP_TMS

58
60

11 /06 u pd ate

L

REMOT E2+

16

REMOT E2-

15

14

13

12

FAN _PWM _OUT

11

TA CH

10

9

XDP _RST#_R

Clo se to U 2

R5 1

2.05K_0402_1%

R5 5

15K_0402_5%

SMB _CLK_S3 9 ,10, 11,13 ,24SMB_D ATA_S39,10 ,11, 13,24

5

CF G8 5
CF G9 5

CF G0 5
CF G1 5

CF G2 5
CF G3 5

CF G10 5
CF G11 5

CF G4 5
CF G5 5

CF G6 5
CF G7 5

+V CCP

1K_ 0201_5%

R3 8

1 2
1 2

R3 9 0_020 1_5%

1 2

R4 2 0 _0201_ 5%

2

1

R6 1

Title

Size D ocum ent N umber Re v

Cu stom

Da te: She et o f

PLT_ RST#

@

FA N_PW M_R

2

1

C5

2200 P_0402_ 50V7K

10K_0201_5%

Compal Electronics, Inc.

Auburndale(1/5)-Thermal/XDP

LA -5 251 P

H_ CPUR ST#
XDP _DBRES ET#

1 2

R4 6 0_02 01_5%

C2

0.1U _0402 _16V4Z@

+5VS

+3VS

+5VS

+3VS

R3 4
1K_ 0201_5%

1 2

XDP _DBRESE T# 12, 14

PLT_R ST# 12,1 5,21 ,22,2 3,31

FAN _PWM 30

R5 4
10K _0201_5%

1 2

1

1

2

2

3

3

4

4

5

G5

6

G6

ACE S_85 205-04001

CO NN@

5

4 4 7Tues day, Jan uary 05, 2010

JP 2

0. 9

1

2

3

4

5

U1 A

DMI _CRX_PTX _N014
DMI _CRX_PTX _N114
DMI _CRX_PTX _N214
DMI _CRX_PTX _N314

DMI_C RX_PTX_P 014

A A

B B

DMI_C RX_PTX_P 114
DMI_C RX_PTX_P 214
DMI_C RX_PTX_P 314

DMI _CTX_PRX _N014
DMI _CTX_PRX _N114
DMI _CTX_PRX _N214
DMI _CTX_PRX _N314

DMI_C TX_PRX_P 014
DMI_C TX_PRX_P 114
DMI_C TX_PRX_P 214
DMI_C TX_PRX_P 314

FDI _CTX_ PRX_N01 4
FDI _CTX_ PRX_N11 4
FDI _CTX_ PRX_N21 4
FDI _CTX_ PRX_N31 4
FDI _CTX_ PRX_N41 4
FDI _CTX_ PRX_N51 4
FDI _CTX_ PRX_N61 4
FDI _CTX_ PRX_N71 4

FDI _CTX_PRX _P014
FDI _CTX_PRX _P114
FDI _CTX_PRX _P214
FDI _CTX_PRX _P314
FDI _CTX_PRX _P414
FDI _CTX_PRX _P514
FDI _CTX_PRX _P614
FDI _CTX_PRX _P714

FD I_F SYN C014
FD I_F SYN C114

FD I_I NT14

FD I_L SYN C014
FD I_L SYN C114

FDI _CTX_ PRX_N0
FDI _CTX_ PRX_N1
FDI _CTX_ PRX_N2
FDI _CTX_ PRX_N3
FDI _CTX_ PRX_N4
FDI _CTX_ PRX_N5
FDI _CTX_ PRX_N6
FDI _CTX_ PRX_N7

FDI _CTX_PR X_P0
FDI _CTX_PR X_P1
FDI _CTX_PR X_P2
FDI _CTX_PR X_P3
FDI _CTX_PR X_P4
FDI _CTX_PR X_P5
FDI _CTX_PR X_P6
FDI _CTX_PR X_P7

FD I_F SYN C0
FD I_F SYN C1

FD I_I NT

FD I_L SY NC0
FD I_L SY NC1

F7

J8

K8

J4

F9

J6

K9

J2

H17
K15
J13
F10

G17

M15

G13
J11

L2
N7

M4

P1

N10

R7
U7

W8

K1
N5
N2
R2
N9
R8
U6

W10

AC7
AC9

AB5

AA1
AB2

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

FDI_TX#[0]
FDI_TX#[1]
FDI_TX#[2]
FDI_TX#[3]
FDI_TX#[4]
FDI_TX#[5]
FDI_TX#[6]
FDI_TX#[7]

FDI_TX[0]
FDI_TX[1]
FDI_TX[2]
FDI_TX[3]
FDI_TX[4]
FDI_TX[5]
FDI_TX[6]
FDI_TX[7]

FDI_FSYNC[0]
FDI_FSYNC[1]

FDI_INT

FDI_LSYNC[0]
FDI_LSYNC[1]

PEG_RCOMPO

DMI Intel(R) FDI

PCI EXPRESS -- GRAPHICS

C C

INT EL_A UBURN DALE _1288

PEG_ICOMPI

PEG_ICOMPO

PEG_RBIAS

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

B12
A13
D12
B11

G40
G38
H34
P34
G28
H25
H24
D29
B26
D26
B23
D22
A20
D19
A17
B14

F40
J38
G34
M34
J28
G25
K24
B28
A27
B25
A24
B21
B19

MB_ C_DP_A UXP

B18
B16
D15

N40
L38
M32
D40
A38
G32
B33
B35
L30
A31
B32
L28
N26
M24
G21
J20

L40
N38
N32
B39
B37
H32
A34
D36
J30
B30
D33
N28
M25
N24
F21
L20

49.9 _0402_1 %

EXP _ICOMPI

1 2

EXP _RBIAS

1 2

750_ 0402_1%

MB_ C_DP _AUXN

MB_ C_DP _DATA 0_N

0.1U _0402 _16V4Z

MB_ C_DP _DATA0_P

R6 4

R6 5

C9 03

1 2

0.1U _0402 _16V4Z

1 2

C9 04

0.1U _0402 _16V4Z

C9 05

1 2

C8 58

1 2

0.1U _0402 _16V4Z

MB_ DP_AUXN 20

MB_DP _AUXP 20

MB_ DP_DA TA0_N 2 0

MB_ DP_DATA 0_P 20

Q46A

2N70 02DW H 2N SOT3 63-6

+V CCP

12

61

R8 01

7.5K _0402 _1%

2

12

R8 00

100K _040 2_5%~D

MB_ DP_H PD 20

U1 E

CF G0

CF G04
CF G14
CF G24
CF G34
CF G44
CF G54
CF G64
CF G74
CF G84
CF G94
CF G104
CF G114
CF G124
CF G134
CF G144
CF G154
CF G164
CF G174

T50P AD

CF G1
CF G2
CF G3
CF G4
CF G5
CF G6
CF G7
CF G8
CF G9
CF G10
CF G11
CF G12
CF G13
CF G14
CF G15
CF G16
CF G17

AV71

AW70

AY69
BB69

AM2
AK1
AK2
AK4

AG7

AG2
AH1
AC2
AC4
AE2
AD1

AB7

AU1

AL4

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]

AJ2

CFG[5]

AT2

CFG[6]
CFG[7]

AF4

CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]

AF8

CFG[15]

AF6

CFG[16]
CFG[17]

RSVD_TP[0]

T4

RSVD15

T2

RSVD16

U1

RSVD17

V2

RSVD18

RSVD19
RSVD20

RSVD21
RSVD22

D8

RSVD23

B7

RSVD24

A10

RSVD26

B9

RSVD27

C5

RSVD_NCTF[7]

A6

RSVD_NCTF[8]

E3

RSVD_NCTF[6]

F1

RSVD_NCTF[5]

INT EL_A UBURN DALE _1288

RESERVED

RSVD_NCTF[3]
RSVD_NCTF[4]

RSVD_NCTF[2]
RSVD_NCTF[1]

DC_TEST_BV71
DC_TEST_BV69
DC_TEST_BV68

DC_TEST_BV5
DC_TEST_BV3

DC_TEST_BV1
DC_TEST_BT71
DC_TEST_BT69

DC_TEST_BT3

DC_TEST_BT1

DC_TEST_BR71

DC_TEST_BR1

DC_TEST_E71

DC_TEST_C71

DC_TEST_C69

DC_TEST_A71

DC_TEST_A69

DC_TEST_A68

RSVD32
RSVD33

RSVD34
RSVD35

RSVD36
RSVD37

RSVD38
RSVD39

RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD53
RSVD54
RSVD55
RSVD56
RSVD57
RSVD58

RSVD_TP[2]
RSVD_TP[1]

RSVD62
RSVD63

RSVD64
RSVD65

DC_TEST_E1

DC_TEST_C3

DC_TEST_A5

W66
W64

AC69
AC71

AA71
AA69

R66
R64

BT5
BR5

BV6
BV8

AV69
AK71
AN69
AP66
AH66
AK66
AR71
AM66
AK69
AU71
AT70
AR69
AU69
AT67

AP2
AN7

AV4
AU2

BE69
BE71

BV71
BV69
BV68
BV5
BV3
BV1
BT71
BT69
BT3
BT1
BR71
BR1
E71
E1
C71
C69
C3
A71
A69
A68
A5

T116 P AD
T117 P AD

04/ 20 IN TEL #4181 25 upda te

T118 P AD

T119 P AD

T120 P AD

T51 PAD
T52 PAD

VSS _NCT F2_R 8
VSS _NCT F6_R 8

VSS _NCT F1_R 8
VSS _NCT F7_R 8

CFG Straps for PROCESSOR

CF G0

R6 8 3.01 K_040 2_1%@

1 2

PCI-Ex press Configuration Select

1: Single PEG
0: Bif urcation enabled

CFG0

Not ap plica ble f or Clarksfield Processor

CF G3

R6 9 3.01 K_040 2_1%@

1 2

CFG3-P CI Ex press Static Lane Reversal

1: Nor mal Operation
0: Lan e Numbers Reversed

CFG3

15 -> 0, 14 ->1, .....

CF G4

R7 0 3.01K _0402_1%

D D

ES1 sa mple n eed ne gative voltage
ES2 sa mple c ontact to GND

1 2

CFG4-D isplay Port Presence

1: Dis abled ; No Physical Display Port
attach ed to Embedded Display Port

CFG4

0: Ena bled; An external Display Port
device is c onnected to the Embedded
Display Port

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2010/12/31

Compal Secret Data

Deciphered Date

4

Title

Size D ocum ent N umber Re v

Cu stom

Da te: She et o f

Compal Electronics, Inc.

Auburndale(2/5)-DMI/PEG/FDI

LA -5 251 P

5

5 4 7Tues day, Jan uary 05, 2010

0. 9

1

2

3

U1D

4

5

A A

DD R_A _D[0 ..63]1 0

B B

C C

DD R_A_B S010
DD R_A_B S110
DD R_A_B S210

DD R_A_ CAS#10
DD R_A_ RAS#10
DD R_A _WE#10

DD R_A _D0
DD R_A _D1
DD R_A _D2
DD R_A _D3
DD R_A _D4
DD R_A _D5
DD R_A _D6
DD R_A _D7
DD R_A _D8
DD R_A _D9
DD R_A _D10
DD R_A _D11
DD R_A _D12
DD R_A _D13
DD R_A _D14
DD R_A _D15
DD R_A _D16
DD R_A _D17
DD R_A _D18
DD R_A _D19
DD R_A _D20
DD R_A _D21
DD R_A _D22
DD R_A _D23
DD R_A _D24
DD R_A _D25
DD R_A _D26
DD R_A _D27
DD R_A _D28
DD R_A _D29
DD R_A _D30
DD R_A _D31
DD R_A _D32
DD R_A _D33
DD R_A _D34
DD R_A _D35
DD R_A _D36
DD R_A _D37
DD R_A _D38
DD R_A _D39
DD R_A _D40
DD R_A _D41
DD R_A _D42
DD R_A _D43
DD R_A _D44
DD R_A _D45
DD R_A _D46
DD R_A _D47
DD R_A _D48
DD R_A _D49
DD R_A _D50
DD R_A _D51
DD R_A _D52
DD R_A _D53
DD R_A _D54
DD R_A _D55
DD R_A _D56
DD R_A _D57
DD R_A _D58
DD R_A _D59
DD R_A _D60
DD R_A _D61
DD R_A _D62
DD R_A _D63

BF11
BE11

BH13

BN11

BG17
BK15

BG15
BH17
BK17
BN20
BN17
BK25
BH25

BJ20
BH21
BG24
BG25

BJ40
BM43
BF47
BF48
BN40
BH43
BN44
BN47
BN48
BN51
BH53

BJ55
BH48

BJ48
BM53
BN55
BF55
BN57
BN65

BJ61
BF57

BJ57
BK64
BK61

BJ63
BF64
BB64
BB66

BJ66
BF65
AY64
BC70

BT38
BH38
BF21

BK43

BL38
BF38

U1C

BM34

SA_CK[0]

BP35

SA_CK#[0]

BF20

AT8

SA_DQ[0]

AT6

SA_DQ[1]

BB5

SA_DQ[2]

BB9

SA_DQ[3]

AV7

SA_DQ[4]

AV6

SA_DQ[5]

BE6

SA_DQ[6]

BE8

SA_DQ[7]
SA_DQ[8]
SA_DQ[9]

BK5

SA_DQ[10]
SA_DQ[11]

BF9

SA_DQ[12]

BF6

SA_DQ[13]

BK7

SA_DQ[14]

BN8

SA_DQ[15]
SA_DQ[16]

BN9

SA_DQ[17]
SA_DQ[18]
SA_DQ[19]

BK9

SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

SA_CKE[0]

BK36

SA_CK[1]

BH36

SA_CK#[1]

BK24

SA_CKE[1]

BH40

SA_CS#[0]

BJ47

SA_CS#[1]

BF43

SA_ODT[0]

BL47

SA_ODT[1]

DD R_A_ DM0

BB10

SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]

DDR SYSTEM MEMORY A

SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

BJ10
BM15
BN24
BG44
BG53
BN62
BH59

AY5
BJ7
BN13
BL21
BH44
BK51
BP58
BE62

AY7
BJ5
BL13
BN21
BK44
BH51
BM60
BE64

BT36
BP33
BV36
BG34
BG32
BN32
BK32
BJ30
BN30
BF28
BH34
BH30
BJ28
BF40
BN28
BN25

DD R_A_ DM1
DD R_A_ DM2
DD R_A_ DM3
DD R_A_ DM4
DD R_A_ DM5
DD R_A_ DM6
DD R_A_ DM7

DD R_A_ DQS# 0
DD R_A_ DQS# 1
DD R_A_ DQS# 2
DD R_A_ DQS# 3
DD R_A_ DQS# 4
DD R_A_ DQS# 5
DD R_A_ DQS# 6
DD R_A_ DQS# 7

DD R_A _DQS 0
DD R_A _DQS 1
DD R_A _DQS 2
DD R_A _DQS 3
DD R_A _DQS 4
DD R_A _DQS 5
DD R_A _DQS 6
DD R_A _DQS 7

DDR_ A_M A0
DDR_ A_M A1
DDR_ A_M A2
DDR_ A_M A3
DDR_ A_M A4
DDR_ A_M A5
DDR_ A_M A6
DDR_ A_M A7
DDR_ A_M A8

DDR_ A_M A9
DDR_ A_MA 10
DDR_ A_MA 11
DDR_ A_MA 12
DDR_ A_MA 13
DDR_ A_MA 14
DDR_ A_MA 15

M_ CLK_D DR0 1 0
M_ CLK_D DR#0 1 0
DDR_ CKE0 _DIM MA 10

M_ CLK_D DR1 1 0
M_ CLK_D DR#1 1 0
DDR_ CKE1 _DIM MA 10

DDR_ CS0_ DIMM A# 10
DDR_ CS1_ DIMM A# 10

M_ODT 0 10
M_ODT 1 10

DD R_A_ DM[0 ..7] 1 0

DD R_A _DQS #[0.. 7] 10

DD R_A _DQS [0..7 ] 10

DDR_ A_MA [0.. 15] 10

DD R_B _D[0 ..63]9

DD R_B_B S09
DD R_B_B S19
DD R_B_B S29

DD R_B_ CAS#9
DD R_B_ RAS#9
DD R_B _WE#9

DD R_B _D0
DD R_B _D1
DD R_B _D2
DD R_B _D3
DD R_B _D4
DD R_B _D5
DD R_B _D6
DD R_B _D7
DD R_B _D8
DD R_B _D9
DD R_B _D10
DD R_B _D11
DD R_B _D12
DD R_B _D13
DD R_B _D14
DD R_B _D15
DD R_B _D16
DD R_B _D17
DD R_B _D18
DD R_B _D19
DD R_B _D20
DD R_B _D21
DD R_B _D22
DD R_B _D23
DD R_B _D24
DD R_B _D25
DD R_B _D26
DD R_B _D27
DD R_B _D28
DD R_B _D29
DD R_B _D30
DD R_B _D31
DD R_B _D32
DD R_B _D33
DD R_B _D34
DD R_B _D35
DD R_B _D36
DD R_B _D37
DD R_B _D38
DD R_B _D39
DD R_B _D40
DD R_B _D41
DD R_B _D42
DD R_B _D43
DD R_B _D44
DD R_B _D45
DD R_B _D46
DD R_B _D47
DD R_B _D48
DD R_B _D49
DD R_B _D50
DD R_B _D51
DD R_B _D52
DD R_B _D53
DD R_B _D54
DD R_B _D55
DD R_B _D56
DD R_B _D57
DD R_B _D58
DD R_B _D59
DD R_B _D60
DD R_B _D61
DD R_B _D62
DD R_B _D63

AW2

BV10
BR10

BT12

BT15
BV15
BV12
BP12
BV17
BU16
BP15
BU19
BV22

BT22
BP19
BV19
BV20

BT20

BT48
BV48
BV50
BP49

BT47
BV52
BV54

BT54
BP53
BU53

BT59

BT57
BP56

BT55
BU60
BV59
BV61
BP60
BR66
BR64
BR62

BT61
BN68

BL69

BJ71

BF70
BG71
BC67
BK70
BK67
BD71
BD69

BV43
BV41
BV24

BU46

BT40

BT41

BA2

SB_DQ[0]
SB_DQ[1]

BD1

SB_DQ[2]

BE4

SB_DQ[3]

AY1

SB_DQ[4]

BC2

SB_DQ[5]

BF2

SB_DQ[6]

BH2

SB_DQ[7]

BG4

SB_DQ[8]

BG1

SB_DQ[9]

BR6

SB_DQ[10]

BR8

SB_DQ[11]

BJ4

SB_DQ[12]

BK2

SB_DQ[13]

BU9

SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

DDR SYSTEM MEMORY - B

SB_CK[0]
SB_CK#[0]
SB_CKE[0]

SB_CK[1]
SB_CK#[1]
SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

SB_DM[0]

SB_DM[1]

SB_DM[2]

SB_DM[3]

SB_DM[4]

SB_DM[5]

SB_DM[6]

SB_DM[7]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]

SB_MA[1]

SB_MA[2]

SB_MA[3]

SB_MA[4]

SB_MA[5]

SB_MA[6]

SB_MA[7]

SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

BU33
BV34
BT26

BV38
BU39
BT24

BP46
BT43

BV45
BU49

BB4
BL4
BT13
BP22
BV47
BV57
BU65
BF67

BE2
BM3
BU12
BT19
BT52
BV55
BU63
BG69

BD4
BN4
BV13
BT17
BT50
BU56
BV62
BJ69

BT34
BP30
BV29
BU30
BV31
BT33
BT31
BP26
BV27
BT27
BU42
BU26
BT29
BT45
BV26
BU23

DD R_B_ DM0
DD R_B_ DM1
DD R_B_ DM2
DD R_B_ DM3
DD R_B_ DM4
DD R_B_ DM5
DD R_B_ DM6
DD R_B_ DM7

DD R_B_ DQS# 0
DD R_B_ DQS# 1
DD R_B_ DQS# 2
DD R_B_ DQS# 3
DD R_B_ DQS# 4
DD R_B_ DQS# 5
DD R_B_ DQS# 6
DD R_B_ DQS# 7

DD R_B _DQS 0
DD R_B _DQS 1
DD R_B _DQS 2
DD R_B _DQS 3
DD R_B _DQS 4
DD R_B _DQS 5
DD R_B _DQS 6
DD R_B _DQS 7

DDR_ B_M A0
DDR_ B_M A1
DDR_ B_M A2
DDR_ B_M A3
DDR_ B_M A4
DDR_ B_M A5
DDR_ B_M A6
DDR_ B_M A7
DDR_ B_M A8

DDR_ B_M A9
DDR_ B_MA 10
DDR_ B_MA 11
DDR_ B_MA 12
DDR_ B_MA 13
DDR_ B_MA 14
DDR_ B_MA 15

M_ CLK_D DR2 9
M_ CLK_D DR#2 9
DDR_ CKE2 _DIM MB 9

M_ CLK_D DR3 9
M_ CLK_D DR#3 9
DDR_ CKE3 _DIM MB 9

DDR_ CS2_ DIMM B# 9
DDR_ CS3_ DIMM B# 9

M_ODT 2 9
M_ODT 3 9

DD R_B_ DM[0 ..7] 9

DD R_B_ DQS# [0..7 ] 9

DD R_B_ DQS[ 0..7] 9

DDR_ B_MA [0.. 15] 9

INT EL_A UBURN DALE _1288

1

INT EL_A UBURN DALE _1288

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2010/12/31

Compal Secret Data

Deciphered Date

4

Title

Size D ocum ent N umber R ev

Cu sto m

Da te: She et o f

Compal Electronics, Inc.

Auburndale(3/5)-DDR3

LA -52 51P

5

6 4 7Tues day, Jan uary 05, 2010

0. 9

D D

C1 9

1U_0 402_6 .3V4Z

1U_0 402_6 .3V4Z

1U_0 402_6 .3V4Z

10U_ 0805_ 6.3V6M

C2 14

C2 18

C3 80

1

2

C3 5

1

2

10U_ 0805_ 6.3V6M

47P _0402_50 V8J

C6 1

1

+

2

1

2

1

2

1

2

10U_ 0805_ 6.3V6M@

1U_0 402_6 .3V4Z

+VC CP

C5 4

@

C9 73

1U_0 402_6 .3V4Z

1U_0 402_6 .3V4Z

1U_0 402_6 .3V4Z

C3 0

1

2

+GF X_CORE

09 /22 u pd ate

1

+

C9 74

2

330U _V_2VM _R6M

C2 13

C2 17

C2 21

1

2

1U_0 402_6 .3V4Z

C3 6

1

2

11 /13 u pd ate

22U_ 0805_ 6.3V6M

C6 2

1

2

47P _0402_50 V8J

U1 G

AN32

330U _V_2VM _R6M

VAXG1

AN30

VAXG2

AN28

VAXG3

AN26

VAXG4

AN24

VAXG5

AN23

VAXG6

AN21

VAXG7

AN19

VAXG8

AL32

VAXG9

AL30

VAXG10

AL28

VAXG11

AL26

VAXG12

AL24

VAXG13

AL23

VAXG14

AL21

VAXG15

AL19

VAXG16

AK14

VAXG17

AK12

VAXG18

AJ10

VAXG19

AH14

VAXG20

AH12

VAXG21

AF28

VAXG22

AF26

VAXG23

AF24

VAXG24

AF23

VAXG25

AF21

VAXG26

AF19

VAXG27

AF17

VAXG28

AF15

VAXG29

AF14

VAXG30

AD28

VAXG31

AD26

VAXG32

AD24

VAXG33

AD23

VAXG34

AD21

VAXG35

AD19

VAXG36

AD17

VAXG37

W21

VTT1_1

W19

VTT1_2

U21

10U_ 0805_ 6.3V6M

VTT1_3

U19

VTT1_4

U17

C3 1

VTT1_5

U15

VTT1_6

U14

VTT1_7

U12

VTT1_8

R21

VTT1_9

R19

VTT1_10

R17

VTT1_11

AK62

VCAP2_1

AK60

VCAP2_2

AK59

1

VCAP2_3

AH60

VCAP2_4

AH59

VCAP2_5

AF60

VCAP2_6

2

AF59

VCAP2_7

AD60

VCAP2_8

AD59

VCAP2_9

AB60

VCAP2_10

AB59

VCAP2_11

AA60

VCAP2_12

AA59

VCAP2_13

W60

VCAP2_14

W59

VCAP2_15

U60

VCAP2_16

U59

VCAP2_17

R60

VCAP2_18

R59

VCAP2_19

INT EL_A UBURN DALE _1288

04/ 29 Ch ang e C55, C56,C5 7 from
@47 P_0 402 to 1UF_ 040 2 by HP.

+C PU_C ORE

1U_0 402_6 .3V6K

1

1

C5 5

C5 6

2

+C PU_C ORE

1U_0 402_6 .3V6K

C6 16

1

2

2

1U_0 402_6 .3V6K

C6 23

1

2

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

C6 15

1

1

C5 7

2

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

C6 43

1

1

2

2

GRAPHI CS

PEG & DMI

POWER

47P _0402_50 V8J

C5 8

1

@

2

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

C6 45

C6 17

1

2

Follow SCH check list

VAXG_SENSE

VSSAXG_SENSE

SENSE

LINES

GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]

GFX_VR_EN

GFX_DPRSLPVR

GFX_IMON

GRA PHI CS VIDs

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23

DDR3 - 1.5V RAILS

VDDQ24
VDDQ25
VDDQ26
VDDQ27
VDDQ28
VDDQ29
VDDQ30
VDDQ31
VDDQ32
VDDQ33
VDDQ34
VDDQ35
VDDQ36

VTT0_DDR
VTT0_DDR[1]
VTT0_DDR[2]
VTT0_DDR[3]
VTT0_DDR[4]
VTT0_DDR[5]
VTT0_DDR[6]
VTT0_DDR[7]
VTT0_DDR[8]
VTT0_DDR[9]

VTT1_12
VTT1_13
VTT1_14
VTT1_15
VTT1_16
VTT1_17
VTT1_18
VTT1_19
VTT1_20
VTT1_21

+C PU_C ORE

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

C3 81

C3 82

1

2

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

C6 46

1

2

C6 47

C6 44

1

1

2

2

C1 7

C1 8

1U_0 402_6 .3V4Z

10U_ 0805_ 6.3V6M

C1 6

1

1

1

1

2

2

2

1U_0 402_6 .3V4Z

C2 12

1

2

1U_0 402_6 .3V4Z

C2 16

1

2

1U_0 402_6 .3V4Z

C2 20

1

2

0116 a dd

10U_ 0805_ 6.3V6M

C2 8

1

2

2

C1 79

1

2

C2 15

1

2

C2 19

1

2

22U_ 0805_ 6.3V6M

C2 9

1U_0 402_6 .3V4Z

1U_0 402_6 .3V4Z

A A

1

2

1U_0 402_6 .3V4Z

1

2

1U_0 402_6 .3V4Z

1

2

B B

+V CCP

1

2

11 /13 u pd ate

+VC AP2

1U_0 402_6 .3V4Z

C3 2

1U_0 402_6 .3V4Z

1U_0 402_6 .3V4Z

C3 4

C3 3

1

1

2

2

0112 c hange size

C C

10U_ 0805_ 6.3V6M

22U_ 0805_ 6.3V6M

C5 9

C6 0

1

1

1

2

2

2

11 /13 u pd ate

D D

+V CCP

47P _0402_50 V8J

47P _0402_50 V8J

C5 1

C5 2

1

@

2

C5 3

1

1

@

@

2

2

1

AF12
AF10

AF71
AG67
AG70
AH71
AN71
AM67
AM70

AH69
AL71
AL69

BU40
BU35
BU28
BN38
BM25
BL30
BJ38
BH32
BH28
BG43
BF16
BF15
BD35
BD33
BD32
BD30
BD28
BD26
BD24
BD23
BD21
BD19
BD17
BD15
BB35
BB33
BB32
BB30
BB28
BB26
BB24
BB23
BB21
BB19
BB17
BB15

AW32
AW30
AW28
AW26
AW24
AW23
AW21
AW19
AW17
AW15

AD15
AD14
AD12
AB12
AA12
W17
W15
W14
W12
R15

C5 33

1

2

0116 a dd

1U_0 402_6 .3V6K

1

2

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

C6 49

2

GFX VR_E N

1 2

R7 00 4.7K _0201 _5%

VCC _AXG_SE NSE 4 2
VSS_A XG_SENS E 42

GFX VR_V ID_0 42
GFX VR_V ID_1 42
GFX VR_V ID_2 42
GFX VR_V ID_3 42
GFX VR_V ID_4 42
GFX VR_V ID_5 42
GFX VR_V ID_6 42

1 2

GFX VR_EN 4 2
GFX VR_D PRSLPV R 42
GFX VR_IMO N 42

1U_0 402_6 .3V4Z

1U_0 402_6 .3V4Z

C2 1

C2 0

1

1

2

2

330U _B2_ 2.5VM_R15M

22U_ 0805_ 6.3V6M

C2 5

C2 6

1

1

+

@

2

2

11 /27 u pd ate

+VT T_DDR

1U_0 402_6 .3V4Z

1U_0 402_6 .3V4Z

C4 3

C4 2

C4 6

1

1

2

2

10U_ 0805_ 6.3V6M

10U_ 0805_ 6.3V6M

C4 7

1

1

2

2

0116 a dd

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

C5 34

1

2

1

2

C6 13

C3 83

1

1

2

2

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

C6 50

C6 48

1

1

2

2

2

R7 054.7 K_020 1_5%@

+1.5 VS_C PU_V DDQ

1U_0 402_6 .3V4Z

1U_0 402_6 .3V4Z

C2 2

1

1

2

2

22U_ 0805_ 6.3V6M

C2 7

1

2

0_06 03_5%

1U_0 402_6 .3V4Z

C4 4

1

2

22U_ 0805_ 6.3V6M

C4 8

1

2

11 /13 u pd ate

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

C6 14

1

2

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

C6 52

C6 53

1

2

0116 a dd

+V CCP

1U_0 402_6 .3V4Z

C2 3

1

2

+V CCP

12

L31

+V CCP

10U_ 0805_ 6.3V6M

C4 9

1

2

1U_0 402_6 .3V6K

C6 12

1

2

1U_0 402_6 .3V6K

C6 51

1

2

C2 4

1

2

1

2

+C PU_C ORE

AF57
AF55
AF53
AF51
AF50
AF48
AF46
AF44
AF42

AF41
AD55
AD51
AD48
AD44
AD41

AB55

AB51

AB48

AB44

AB41

AA55

AA51

AA48

AA44

AA41

W55
W51
W48
W44
W41

U55
U51
U48
U44
U41
R55
R51
R48
R44
R41
P60
N55
N51
N48
N44
N42
M60
M51
M44
L55
K60
K51
K44

J55
H60
H51
H44
G60
G55
G51
G44
F55
E60
E57
E53
E50
E46
E42
D59
D57
D55
D54
D52
D50
D48
D47
D45
D43
B60
B56
B53
B49
B46
B42
A57
A54
A50
A47
A43

2.2U _0402 _6.3V4M

3

U1H

VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25

POWER

VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34

CPU CO RE SUP PLY

VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79
VCC_80
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_86
VCC_87
VCC_88
VCC_89

INT EL_A UBURN DALE _1288

+VCA P0 +VCA P1

2.2U _0402 _6.3V4M

1

C6 8

2

0112 a dd 7pc s Caps to fo llow D esign guide 0112 a dd 7pc s Caps to fo llow D esign guide

2.2U _0402 _6.3V4M

1

1

C6 9

C7 0

2

2

2.2U _0402 _6.3V4M

3

2.2U _0402 _6.3V4M

1

1

C7 1

C7 2

2

2

2.2U _0402 _6.3V4M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

VCAP0_1
VCAP0_2
VCAP0_3
VCAP0_4
VCAP0_5
VCAP0_6
VCAP0_7
VCAP0_8

VCAP0_9
VCAP0_10
VCAP0_11
VCAP0_12
VCAP0_13
VCAP0_14
VCAP0_15
VCAP0_16
VCAP0_17
VCAP0_18
VCAP0_19
VCAP0_20
VCAP0_21
VCAP0_22
VCAP0_23
VCAP0_24
VCAP0_25
VCAP0_26
VCAP0_27

VCAP1_1

VCAP1_2

VCAP1_3

VCAP1_4

VCAP1_5

VCAP1_6

VCAP1_7

VCAP1_8

VCAP1_9
VCAP1_10
VCAP1_11
VCAP1_12
VCAP1_13
VCAP1_14
VCAP1_15
VCAP1_16
VCAP1_17
VCAP1_18
VCAP1_19
VCAP1_20
VCAP1_21
VCAP1_22
VCAP1_23
VCAP1_24
VCAP1_25
VCAP1_26
VCAP1_27

1

1

C9 3

C1 14

2

2

2.2U _0402 _6.3V4M

BD55
BD51
BD48
BB55
BB51
BB48
AY57
AY53
AY50
AW57
AW53
AW50
AU55
AU51
AU48
AR55
AR51
AR48
AN57
AN53
AN50
AL57
AL53
AL50
AK57
AK53
AK50

BD44
BD41
BD37
BB44
BB41
BB37
AY46
AY42
AY39
AW46
AW42
AW39
AU44
AU41
AU37
AR44
AR41
AR37
AN46
AN42
AN39
AL46
AL42
AL39
AK46
AK42
AK39

+VCA P0

+VCA P1

H_VTTVID1 = Low, 1.1V

H_VTTVID1 = High, 1.05V

PR OC_DP RSLP VR40

VCC SENS E40
VSS SENSE4 0

VCC SENS E

VSS SENSE

10 /01 u pd ate

Ch an ge + VCAP0 /+VCAP 1/ ML CC Cap s fro m

L

1U_ 040 2 t o 2.2 U_0 402 o n S I-2B SV &LV Sku
SM T bu ild.

2.2U _0402 _6.3V4M

2.2U _0402 _6.3V4M

1

1

C1 13

2

2

2.2U _0402 _6.3V4M

2008/09/15 2010/12/31

1

C9 4

2

1

C1 40

C9 2

2

2.2U _0402 _6.3V4M

Compal Secret Data

VTT_S ENSE37

VSS_S ENSE_VT T37

Close to CPU

1 2

R7 5 1 00_04 02_1%

1 2

R7 6 1 00_04 02_1%

+1.8V S

+1.5 VS_C PU_V DDQ

0_06 03_5%

1U_0 402_6 .3V4Z

2.2U _0402 _6.3V4M

1

C1 15

2.2U _0402 _6.3V4M

2

Deciphered Date

4

H_ VID [0..6 ]40

H_V TTVID1

IMV P_IMON40

VCC SENS E
VSS SENSE

L32

4

PSI #40

R7 2

0_02 01_5%

10U_ 0805_ 6.3V6M

1

C3 74.7U _0603 _6.3V6K

2

12

C5 0

C6 3

H_ VID 0
H_ VID 1
H_ VID 2
H_ VID 3
H_ VID 4
H_ VID 5
H_ VID 6

PM_ DPRS LPVR _R

12

0_02 01_5%

R7 3

R7 4

0_02 01_5%

+C PU_C ORE

1

C3 8

2

+V DDQ_ CK

1

2

2.2U _0402 _6.3V4M

1

1

C6 4

2

2

2.2U _0402 _6.3V4M

U1 F

F68

PSI#

A61

VID[0]

D61

VID[1]

D62

VID[2]

A62

VID[3]

B63

VID[4]

D64

VID[5]

D66

VID[6]

AN1

VTT_SELECT[1]

F66

PROC_DPRSLPVR

A41

ISENSE

12

F64

VCC_SENSE

12

F63

VSS_SENSE

N13

VTT_SENSE

R12

VSS_SENSE_VTT

W39

VCCPLL1

W37

VCCPLL2

U37

VCCPLL3

R39

VCCPLL4

R37

VCCPLL5

BB14

VDDQ_CK[1]

BB12

VDDQ_CK[2]

INT EL_A UBURN DALE _1288

04/ 28 Ch ang e P/N fr om SD0340 00080 to
SD0 280 00080

2.2U _0402 _6.3V4M

1

1

C6 5

2

2

1.8V

VTT0_72

R7 7 0_040 2_5%

VTT0_73

C6 6

2.2U _0402 _6.3V4M

1 2

R7 8 0_040 2_5%

1 2

2.2U _0402 _6.3V4M

1

1

C6 7

C8 6

2

2

2.2U _0402 _6.3V4M

Title

Size D ocum ent N umber Re v

Cu stom

LA -5 251 P

Da te: She et o f

5

AW14

VTT0_11

AW12

VTT0_12

AU60

VTT0_13

AU59

VTT0_14

AU12

VTT0_15

AR60

VTT0_16

AR59

VTT0_17

AR12

VTT0_18

AN60

VTT0_19

AN59

VTT0_20

AN35

VTT0_21

AN33

VTT0_22

AN17

VTT0_23

AN15

VTT0_24

AN14

VTT0_25

AN12

VTT0_26

AM10

VTT0_27

AL60

VTT0_28

AL59

VTT0_29

AL17

VTT0_30

AL15

VTT0_31

AL14

VTT0_32

AL12

VTT0_33

AK35

VTT0_34

SENSE LINESCPU VI DS

POWER

2.2U _0402 _6.3V4M

1

C8 9

2

1.1V R AIL PO WER

1

C8 8

2

2.2U _0402 _6.3V4M

VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42

VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8

VTT0_9
VTT0_10
VTT0_43
VTT0_44
VTT0_45
VTT0_46
VTT0_47
VTT0_48
VTT0_49
VTT0_50
VTT0_51
VTT0_52
VTT0_53
VTT0_54
VTT0_55
VTT0_56
VTT0_57
VTT0_58
VTT0_59
VTT0_60
VTT0_61
VTT0_62
VTT0_63
VTT0_64
VTT0_65
VTT0_66
VTT0_67
VTT0_68
VTT0_69
VTT0_70
VTT0_71
VTT0_72
VTT0_73

2.2U _0402 _6.3V4M

1

C8 7

2

AK33
AF39
AF37
AF35
AF33
AF32
AF30
AD39
BF60
BF59
BD60
BD59
BB60
BB59
AY60
AW60
AW35
AW33
AD37
AD35
AD33
AD32
AD30
W35
W33
W32
W30
W28
W26
W24
W23
U35
U33
U32
U30
U28
U26
U24
U23
R35
R33
R32
R30
R28
R26
R24
R23
AY10
AN9

+VC CP

1

1

C8 5

2

2

2.2U _0402 _6.3V4M

Compal Electronics, Inc.

Auburndale(4/5)-PWR

5

+V CCP

VTT0_72
VTT0_73

2.2U _0402 _6.3V4M

1

C9 1

C9 0

2

7 4 7Tues day, Jan uary 05, 2010

0. 9

1

2

3

4

5

U1 I

BU62

VSS1

BU58

VSS2

BU55

VSS3

BU51

VSS4

BU48

VSS5

BU44

VSS6

BU37

VSS7

BU32

A A

B B

C C

D D

VSS8

BU25

VSS9

BU21

VSS10

BU18

VSS11

BU14

VSS12

BU11

VSS13

BU7

VSS14

BP42

VSS15

BN64

VSS16

BN6

VSS17

BM70

VSS18

BM51

VSS19

BM44

VSS20

BM32

VSS21

BM24

VSS22

BM17

VSS23

BL57

VSS24

BL55

VSS25

BL48

VSS26

BL40

VSS27

BL28

VSS28

BL20

VSS29

BK63

VSS30

BK60

VSS31

BK53

VSS32

BK34

VSS33

BK10

VSS34

BJ64

VSS35

BJ21

VSS36

BJ9

VSS37

BJ1

VSS38

BH70

VSS39

BH57

VSS40

BH55

VSS41

BH47

VSS42

BH24

VSS43

BH20

VSS44

BH15

VSS45

BG51

VSS46

BG36

VSS47

BF62

VSS48

BF30

VSS49

BF13

VSS50

BF8

VSS51

BE70

VSS52

BE65

VSS53

BE9

VSS54

BE1

VSS55

BD57

VSS56

BD53

VSS57

BD50

VSS58

BD46

VSS59

BD42

VSS60

BD39

VSS61

BD14

VSS62

BB71

VSS63

BB62

VSS64

BB57

VSS65

BB53

VSS66

BB50

VSS67

BB46

VSS68

BB42

VSS69

BB39

VSS70

BB7

VSS71

BB1

VSS72

BA70

VSS73

AY71

VSS74

AY66

VSS75

AY62

VSS76

AY59

VSS77

AY55

VSS78

AY51

VSS79

AY48

VSS80

AR42

VSS140

AR39

VSS141

AR35

VSS142

AR33

VSS143

AR32

VSS144

AR30

VSS145

AR28

VSS146

AR26

VSS147

AR24

VSS148

AR23

VSS149

AR21

VSS150

AR19

VSS151

AR17

VSS152

AR15

VSS153

AR14

VSS154

AR4

VSS155

AR1

VSS156

AP70

VSS157

AP64

VSS158

AN62

VSS159

AN55

VSS160

AY44

VSS81

AY41

VSS82

AY37

VSS83

AY35

VSS84

AY33

VSS85

AY32

VSS86

AY30

VSS87

AY28

VSS88

AY26

VSS89

INT EL_A UBURN DALE _1288

VSS

1

VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220

AY24
AY23
AY21
AY19
AY17
AY15
AY14
AY12
AY8
AY4
AW67
AW62
AW59
AW55
AW51
AW48
AW44
AW41
AW37
AV9
AV1
AU70
AU62
AU57
AU53
AU50
AU46
AU42
AU39
AU35
AU33
AU32
AU30
AU28
AU26
AU24
AU23
AU21
AU19
AU17
AU15
AU14
AU4
AT64
AT10
AR62
AR57
AR53
AR50
AR46
AN51
AN48
AN44
AN41
AN37
AN5
AN4
AM64
AM8
AL62
AL55
AL51
AL48
AL44
AL41
AL37
AL35
AL33
AL1
AK70
AK64
AK55
AK51
AK48
AK44
AK41
AK37
AK32
AK30
AK28
AK26
AK24
AK23
AK21
AK19
AK17
AK15
AJ70
AH62
AH57
AH55
BV66
BV64
BT68
BR69
BR68
BR3
BN71
BN1
BL71
BL1
R14
H71
F71
E69
E68
A66
A64
E5
C68

U1J

AH53

VSS202

AH51

VSS203

AH50

VSS204

AH48

VSS205

AH46

VSS206

AH44

VSS207

AH42

VSS208

AH41

VSS209

AH39

VSS210

AH37

VSS211

AH35

VSS212

AH33

VSS213

AH32

VSS214

AH30

VSS215

AH28

VSS216

AH26

VSS217

AH24

VSS218

AH23

VSS219

AH21

VSS220

AH19

VSS221

AH17

VSS222

AH15

VSS223

AH4

VSS224

AG64

VSS225

AG9

VSS226

AG6

VSS227

AF69

VSS228

AF62

VSS229

AF1

VSS230

AE70

VSS231

AE64

VSS232

AD62

VSS233

AD57

VSS234

AD53

VSS235

AD50

VSS236

AD46

VSS237

AD42

VSS238

AD4

VSS239

AC67

VSS240

AC64

VSS241

AC10

VSS242

AC5

VSS243

AC1

VSS244

AB70

VSS245

AB62

VSS246

AB57

VSS247

AB53

VSS248

AB50

VSS249

AB46

VSS250

AB42

VSS251

AB39

VSS252

AB37

VSS253

AB35

VSS254

AB33

VSS255

AB32

VSS256

AB30

VSS257

AB28

VSS258

AB26

VSS259

AB24

VSS260

AB23

VSS261

AB21

VSS262

AB19

VSS263

AB17

VSS264

AB15

VSS265

AB14

VSS266

AB9

VSS267

AA66

VSS268

AA64

VSS269

AA62

VSS270

AA57

VSS271

AA53

VSS272

AA50

VSS273

AA46

VSS274

AA42

VSS275

AA39

VSS276

AA37

VSS277

AA35

VSS278

AA33

VSS279

AA32

VSS280

AA30

VSS281

AA28

VSS282

AA26

VSS283

AA24

VSS284

AA23

VSS285

AA21

VSS286

AA19

VSS287

F20

VSS374

F4

VSS375

E37

VSS376

E33

VSS377

E30

VSS378

E16

VSS379

E12

VSS380

D41

VSS381

D38

VSS382

D34

VSS383

D31

VSS384

D27

VSS385

D24

VSS386

D20

VSS387

D17

VSS388

D13

VSS389

D10

VSS390

D6

VSS391

B65

VSS392

B40

VSS415

INT EL_A UBURN DALE _1288

VSS

2

VSS404
VSS405
VSS406
VSS407
VSS408
VSS409
VSS410
VSS411
VSS412
VSS413
VSS393
VSS394
VSS395
VSS396
VSS397
VSS398
VSS399
VSS400
VSS401
VSS402
VSS403
VSS288
VSS289
VSS290
VSS291
VSS292
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360
VSS361
VSS362
VSS363
VSS364
VSS365
VSS366
VSS367
VSS368
VSS369
VSS370
VSS371
VSS372
VSS373

A40
A36
A33
A29
A26
A22
A19
A15
A12
A8
B62
B58
B55
B51
B48
B44
A59
A55
A52
A48
A45
AA17
AA15
AA14
AA4
W69
W62
W57
W53
W50
W46
W42
W6
W1
V70
U64
U62
U57
U53
U50
U46
U42
U39
U9
U4
T1
R70
R62
R57
R53
R50
R46
R42
R5
P4
N63
N57
N53
N50
N46
N30
N21
N15
M53
M42
M36
M1
L70
L57
L48
L47
L13
K64
K53
K43
K36
K34
K32
K25
K17
K11
K6
K4
J65
J57
J48
J47
J40
J9
H53
H43
H36
H1
G70
G57
G53
G48
G47
G43
G30
G24
G20
G15
F61
F48
F47
F28

+V CCP

1U_0 402_6 .3V6K

0112 Add to fo llow design guide

1U_0 402_6 .3V6K

1

C1 89

2

1

C3 04

2

1U_0 402_6 .3V6K

1

2

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

1

1

C1 42

C1 91

2

2

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

C5 10

1

C6 19

2

1U_0 402_6 .3V6K

1

1

C3 03

C3 02

2

2

1U_0 402_6 .3V6K

1

1

C5 09

C5 08

2

2

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

1

1

C6 18

C5 15

2

2

1U_0 402_6 .3V6K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

1

C1 41

C1 90

2

2

1U_0 402_6 .3V6K

1

1

C3 06

C1 92

2

2

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

1

1

C3 07

2

2

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

1

C5 13

2

1U_0 402_6 .3V6K

CPU CORE

1U_0 402_6 .3V6K

1

C2 01

2

1U_0 402_6 .3V6K

1

C3 05

2

1U_0 402_6 .3V6K

1

C5 11

C5 12

2

1U_0 402_6 .3V6K

1

1

C6 28

C6 36

2

2

+C PU_C ORE

22U_ 0805_ 6.3V6MS V@

C7 3

1

2

C9 5

470U _D2_2 VM_R4.5 MSV@

1

+

2

22U_ 0805_6. 3V6M

C1 01

1

2

BGA Ball Cracking Prevention and Detection

100K _0201_5 %

VSS _NCT F1_R5

100K _0201_5 %

VSS _NCT F6_R5 VSS _NCT F7_R5

2008/09/15 2010/12/31

Compal Secret Data

Deciphered Date

22U_ 0805_6. 3V6M

C7 4

1

2

22U_ 0805_6. 3V6M

22U_ 0805_6. 3V6M

C7 6

C7 5

1

1

2

2

22U_ 0805_6. 3V6M

22U_ 0805_6. 3V6M

C7 8

C7 7

1

1

2

2

Inside cavity

470U _D2_2 VM_R4.5 M

C9 7

C9 6

1

1

+

+

2

2

22U_ 0805_6. 3V6M

C1 03

22U_ 0805_ 6.3V6MS V@

C1 02

1

1

2

1

2

2

05 /0 6 upd ate t o c hange

C9 8

C95 ,C9 6,C 97,C98 f rom

1

SGA 000 02X 00( 330 U_7mR) to

+

SGA 000 042 00( 470U_4 .5mR)

2

1- SV BGA 4x 470uF bu lk on C95, C96,C 97,C98

L

2- LV BG A 3 x33 0uF 9mR (SG A20 331 E10 ) bul k on C96,C 97,C98

Under cavity

22U_ 0805_6. 3V6M

C1 05

C1 04

22U_ 0805_ 6.3V6MS V@

1

1

2

2

22U_ 0805_6. 3V6M

C1 06

22U_ 0805_ 6.3V6MS V@

1

2

470U _D2_2 VM_R4.5 M

470U _D2_2 VM_R4.5 M

Under cavity

+3VS

12

R8 0

+3VS +3VS

R8 1

4

12

CRA CK_B GA

3

Q3B

5

2N70 02DW -T/R7 _SOT363-6

4

CRA CK_B GA

61

Q4A
2N70 02DW -T/R7 _SOT363-6

2

VSS _NCT F2_R5

Title

Size D ocum ent N umber Re v

Cu stom

Da te: She et

22U_ 0805_6. 3V6M

C1 08

+3VS

22U_ 0805_6. 3V6M

22U_ 0805_6. 3V6M

C8 0

1

1

2

2

22U_ 0805_6. 3V6M

C1 09

1

2

12

2

12

5

C8 2

C8 1

1

2

22U_ 0805_6. 3V6M

C1 10

1

2

61

Q3A
2N70 02DW -T/R7 _SOT363-6

CRA CK_B GA

3

Q4B
2N70 02DW -T/R7 _SOT363-6

4

22U_ 0805_6. 3V6M

C7 9

1

2

22U_ 0805_ 6.3V6MS V@

C1 07

1

2

R7 9

100K _0201_5 %

R8 2

100K _0201_5 %

Compal Electronics, Inc.

Auburndale(5/5)-GND/Bypass

LA -5 251 P

5

22U_ 0805_6. 3V6M

SV@

22U_ 0805_ 6.3V6M

C8 3

1

1

2

2

CRA CK_B GA 17, 30

o f

8 4 7Tues day, Jan uary 05, 2010

C8 4

0. 9

1

DDR3 SO-DIMM B

+V _DD R_CP U_REF

0.1U _0402 _16V4Z

2.2U _0805 _16V4Z

C1 11

1

2

A A

B B

C C

D D

C1 12

1

2

DDR_ CKE2 _DIM MB6

DD R_B_B S26

M_ CLK_ DDR26
M_ CLK_D DR#26

DD R_B_B S06

DD R_B _WE#6
DD R_B_ CAS#6

DDR_ CS3_ DIMM B#6

+3VS

DD R_B _D0
DD R_B _D1

DD R_B_ DM0

DD R_B _D2
DD R_B _D3

DD R_B _D8
DD R_B _D9

DD R_B_ DQS# 1
DD R_B _DQS 1

DD R_B _D10
DD R_B _D11

DD R_B _D16
DD R_B _D17

DD R_B_ DQS# 2
DD R_B _DQS 2

DD R_B _D18
DD R_B _D19

DD R_B _D24
DD R_B _D25

DD R_B_ DM3

DD R_B _D26
DD R_B _D27

DDR_ CKE2 _DIM MB

DD R_B_ BS2

DDR_ B_MA 12
DDR_ B_M A9

DDR_B_MA8
DDR_ B_M A5

DDR_ B_M A3
DDR_ B_M A1

M _CLK_ DDR2
M _CLK_ DDR#2

DDR_ B_MA 10
DD R_B_ BS0

DD R_B _WE#
DD R_B_ CAS#

DDR_ B_MA 13
DDR_ CS3_ DIMM B#

DD R_B _D32
DD R_B _D33

DD R_B_ DQS# 4
DD R_B _DQS 4

DD R_B _D34
DD R_B _D35

DD R_B _D40
DD R_B _D41

DD R_B_ DM5

DD R_B _D42
DD R_B _D43

DD R_B _D48
DD R_B _D49

DD R_B_ DQS# 6
DD R_B _DQS 6

DD R_B _D50
DD R_B _D51

DD R_B _D56
DD R_B _D57

DD R_B_ DM7

DD R_B _D58
DD R_B _D59

1 2

10K _0201_5%

2.2U _0402 _6.3V6M

0.1U _0402 _16V4Z

C1 36

C1 37

1

1

2

2

+1.5 V + 1.5V

3A @

3A @ 1. 5 V

3A @3A @

JDI MB1

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

R9 5

1 2

10K _0201_5%

R9 6

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

GND2

FOX _AS0 A626-U4 SN-7F~D

CO NN@

Bo tt om S ide H :5. 2mm

L

1. 5 V

1. 5 V1. 5 V

DQS0#

DQS0

DQ12
DQ13

RESET#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3

DQ30
DQ31

CKE1

CK1#

RAS#

ODT0

ODT1

VREF_CA

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5

DQ46
DQ47

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7

DQ62
DQ63

EVENT#

BOSS1
BOSS2

VSS
DQ4
DQ5
VSS

VSS
DQ6
DQ7
VSS

VSS
DM1

VSS

VSS

VSS
DM2
VSS

VSS

VSS

VSS

VSS

VDD

A15
A14

VDD

A11

A7

VDD

A6
A4

VDD

A2

A0
VDD
CK1

VDD
BA1

VDD

S0#

VDD

NC

VDD

VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
DM6
VSS

VSS

VSS

VSS

VSS

SDA
SCL
VTT

Wai t u pdate t he sym bo l for co rrect (LTCX 001 HL00)

1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206
208

2

DD R_B _D4
DD R_B _D5

DD R_B_ DQS# 0
DD R_B _DQS 0

DD R_B _D6
DD R_B _D7

DD R_B _D12
DD R_B _D13

DD R_B_ DM1
DRA MRST#

DD R_B _D14
DD R_B _D15

DD R_B _D20
DD R_B _D21

DD R_B_ DM2

DD R_B _D22
DD R_B _D23

DD R_B _D28
DD R_B _D29

DD R_B_ DQS# 3
DD R_B _DQS 3

DD R_B _D30
DD R_B _D31

DDR_ CKE3 _DIM MB

DDR_ B_MA 15
DDR_ B_MA 14

DDR_B_MA 11
DDR_ B_M A7

DDR_B_MA6
DDR_ B_M A4

DDR_ B_M A2
DDR_ B_M A0

M _CLK_ DDR3
M _CLK_ DDR#3

DD R_B_ BS1
DD R_B_ RAS#

DDR_ CS2_ DIMM B#
M_OD T2

M_OD T3

DD R_B _D36
DD R_B _D37

DD R_B_ DM4

DD R_B _D38
DD R_B _D39

DD R_B _D44
DD R_B _D45

DD R_B_ DQS# 5
DD R_B _DQS 5

DD R_B _D46
DD R_B _D47

DD R_B _D52
DD R_B _D53

DD R_B_ DM6

DD R_B _D54
DD R_B _D55

DD R_B _D60
DD R_B _D61

DD R_B_ DQS# 7
DD R_B _DQS 7

DD R_B _D62
DD R_B _D63

PM_EX TTS#1_R
SMB _DATA_S3
SMB _CLK_S 3

0.

0. 65 A @0 . 75 V

65 A @0 . 75 V

0.0.

65 A @0 . 75 V6 5A @ 0. 7 5V

2

+0.7 5VS

DRA MRST# 4 ,10

DDR_ CKE3 _DIMM B 6

M_ CLK_D DR3 6
M_C LK_DD R#3 6

DDR_ B_BS 1 6
DD R_B_ RAS# 6

DDR_ CS2_ DIMM B# 6
M_ODT 2 6

M_ODT 3 6

0.1U _0402 _16V4Z

C1 16

1

2

2.2U _0805 _16V4Z

C1 17

1

2

SMB _DATA_S3
SMB _CLK_S 3

DD R_B_ DQS# [0..7 ]6

DD R_B _D[0 ..63]6

DD R_B_ DM[0 ..7]6

DD R_B_ DQS[ 0..7]6

DDR_ B_MA [0.. 15]6

R9 4 0_040 2_5%

3
2
1

ACE S_85 204-03001

For ME/AMT debug

PM_EX TTS#1_R 4,1 0
SMB_D ATA_S3 4 ,10,1 1,13,2 4
SMB _CLK_S3 4 ,10,1 1,13, 24

1 2

JP3

3
2
1

CO NN@

3

+1.5 V

12

R8 3

1K_ 0402_1%

+V _D DR_CP U_RE F

12

R8 6

1K_ 0402_1%

+V _DD R_CP U_REF+VR EF_C A

5

G2

4

G1

Lay ou t N ot e:
Pl ace near JDI MB1

+1.5 V

10U_ 0603_6. 3V6M

C1 21

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2010/12/31

10U_ 0603_6. 3V6M

10U_ 0603_6. 3V6M

C1 23

C1 22

1

2

1

1

2

2

Compal Secret Data

10U_ 0603_6. 3V6M

C1 24

1

2

Deciphered Date

4

330U _B2_ 2.5VM_R15M

C1 18

10U_ 0603_6. 3V6M

C1 25

4

0.1U _0402 _16V4Z

10U_ 0603_6. 3V6M

C1 27

C1 26

1

1

2

2

0.1U _0402 _16V4Z

0.1U _0402 _16V4Z
C1 29

C1 28

1

1

2

2

0.1U _0402 _16V4Z
C1 30

1

1

+

2

2

Title

Size D ocum ent N umber R ev

Cu sto m

Da te: She et o f

Compal Electronics, Inc.

LA -52 51P

5

Lay ou t N ot e:
Pl ace near JDI MB1

+0.7 5VS

C1 31

1U_0 402_6 .3V6K

C1 32

1U_0 402_6 .3V6K

1

2

C1 33

1

1

2

2

C1 35

C1 34

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

1

2

DDRIII-SODIMM SLOT1

5

9 4 7Tues day, Jan uary 05, 2010

10U_ 0805_6. 3V6M

1

2

0. 9

1

DDR3 SO-DIMM A

+V _DDR _CPU _REF _A

2.2U _0805 _16V4Z

0.1U _0402 _16V4Z

DD R_A _D0

C1 38

C1 61

0.1U _0402 _16V4Z

1

2

DD R_A _D1

1

C1 39

DD R_A_ DM0

2

DD R_A _D2
DD R_A _D3

DD R_A _D8
DD R_A _D9

DD R_A_ DQS# 1
DD R_A _DQS 1

DD R_A _D10
DD R_A _D11

DD R_A _D16
DD R_A _D17

DD R_A_ DQS# 2
DD R_A _DQS 2

DD R_A _D18
DD R_A _D19

DD R_A _D24
DD R_A _D25

DD R_A_ DM3

DD R_A _D26
DD R_A _D27

DDR_ CKE0 _DIM MA

DD R_A_ BS2

DDR_ A_MA 12
DDR_ A_M A9

DDR_ A_M A8
DDR_ A_M A5

DDR_ A_M A3
DDR_ A_M A1

M _CLK_ DDR0
M _CLK_ DDR#0

DDR_ A_MA 10
DD R_A_ BS0

DD R_A _WE#
DD R_A_ CAS#

DDR_ A_MA 13
DDR_ CS1_ DIMM A#

DD R_A _D32
DD R_A _D33

DD R_A_ DQS# 4
DD R_A _DQS 4

DD R_A _D34
DD R_A _D35

DD R_A _D40
DD R_A _D41

DD R_A_ DM5

DD R_A _D42
DD R_A _D43

DD R_A _D48
DD R_A _D49

DD R_A_ DQS# 6
DD R_A _DQS 6

DD R_A _D50
DD R_A _D51

DD R_A _D56
DD R_A _D57

DD R_A_ DM7

DD R_A _D58
DD R_A _D59

1 2

10K _0201_5%

C1 62

1

A A

B B

C C

D D

2

DDR_ CKE0 _DIM MA6

DD R_A_B S26

M_ CLK_D DR06

M_ CLK_D DR#06

DD R_A_B S06

DD R_A _WE#6
DD R_A_ CAS#6

DDR_ CS1_ DIMM A#6

2.2U _0402 _6.3V6M

+3VS

1

2

1

R1 04

R1 05

10K _0201_5%

1 2

+1.5 V

3A @

3A @ 1. 5 V

1. 5 V

3A @3A @

1. 5 V1. 5 V

JDI MA1

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

FOX _AS0 A626-U2SN -7F

CO NN@

DQS0#

DQS0

DQ12
DQ13

DM1

RESET#

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3

DQ30
DQ31

CKE1

VDD

VDD

VDD

VDD

VDD

CK1#

VDD

RAS#

VDD

ODT0

VDD

ODT1

VDD

VREF_CA

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5

DQ46
DQ47

DQ52
DQ53

DM6

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7

DQ62
DQ63

EVENT#

SDA

GND2

BOSS2

2

+1.5V

2

VSS
DQ4
DQ5
VSS

VSS
DQ6
DQ7
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

A15
A14

A11

A7

A6
A4

A2
A0

CK1

BA1

S0#

NC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

SCL
VTT

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206
208

2

DD R_A _D4
DD R_A _D5

DD R_A_ DQS# 0
DD R_A _DQS 0

DD R_A _D6
DD R_A _D7

DD R_A _D12
DD R_A _D13

DD R_A_ DM1
DRA MRST#

DD R_A _D14
DD R_A _D15

DD R_A _D20
DD R_A _D21

DD R_A_ DM2

DD R_A _D22
DD R_A _D23

DD R_A _D28
DD R_A _D29

DD R_A_ DQS# 3
DD R_A _DQS 3

DD R_A _D30
DD R_A _D31

DDR_ CKE1 _DIM MA

DDR_ A_MA 15
DDR_ A_MA 14

DDR_A_MA 11
DDR_ A_M A7

DDR_A_MA6
DDR_ A_M A4

DDR_ A_M A2
DDR_ A_M A0

M _CLK_ DDR1
M _CLK_ DDR#1

DD R_A_ BS1
DD R_A_ RAS#

DDR_ CS0_ DIMM A#
M_OD T0

M_OD T1

+VR EF_C A

DD R_A _D36
DD R_A _D37

DD R_A_ DM4

DD R_A _D38
DD R_A _D39

DD R_A _D44
DD R_A _D45

DD R_A_ DQS# 5
DD R_A _DQS 5

DD R_A _D46
DD R_A _D47

DD R_A _D52
DD R_A _D53

DD R_A_ DM6

DD R_A _D54
DD R_A _D55

DD R_A _D60
DD R_A _D61

DD R_A_ DQS# 7
DD R_A _DQS 7

DD R_A _D62
DD R_A _D63

PM_EX TTS#1_R
SMB _DATA_S3
SMB _CLK_S 3

0.

0. 65 A @0 . 75 V

0.0.

65 A @0 . 75 V

65 A @0 . 75 V6 5A @ 0. 7 5V

DRA MRST# 4 ,9

DDR_ CKE1 _DIMM A 6

To p S id e H:4 mm

L

Wai t u pdate t he sym bo l for co rrect (LTCX 001HH00)

M_ CLK_D DR1 6
M_C LK_DD R#1 6

DDR_ A_BS 1 6
DD R_A_ RAS# 6

DDR_ CS0_ DIMM A# 6
M_ODT 0 6

M_ODT 1 6

PM_EX TTS#1_R 4, 9
SMB_D ATA_S3 4 ,9,11 ,13,24
SMB _CLK_S3 4 ,9,11 ,13,24

+0.75 VS

+VR EF_C A_A

R1 096 0_04 02_5%

2.2U _0805 _16V4Z

0.1U _0402 _16V4Z

C1 44

C1 43

1

1

2

2

3

DD R_A _D[0 ..63]6

DD R_A_ DM[0 ..7]6

DD R_A _DQS [0..7 ]6

DD R_A_ DQS# [0..7 ]6

DDR_ A_MA [0.. 15]6

+V _DDR _CPU _REF _A

Pla ce R1094, R10 95 close to JDIM A1 pi n1 with C1 38,C13 9

L

4/ 24 Ne w add R1 094 , R10 95, R1 096 an d the V ref

cir cui t for DI MM A Ref V olt age.

+V _DDR _CPU_ REF_ A

1 2

Pla ce R1096 clo se to J DIM A1 pin12 6 w it h C 143,C 144

L

Lay ou t N ot e:
Pl ace near JDI MA1

10U_ 0603_ 6.3V6M

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

4

+1.5 V

12

R1 094

+V _DD R_CP U_REF _A

+1.5V

10U_ 0603_ 6.3V6M

C1 48

C1 47

1

1

2

2

2008/09/15 2010/12/31

1K_ 0402_1%

12

R1 095

1K_ 0402_1%

10U_ 0603_ 6.3V6M

10U_ 0603_ 6.3V6M

C1 49

C1 50

1

1

2

2

Compal Secret Data

Deciphered Date

10U_ 0603_ 6.3V6M

10U_ 0603_ 6.3V6M

C1 51

4

0.1U _0402 _16V4Z

C1 52

1

2

C1 53

1

2

5

Lay ou t N ot e:
Pl ace near JDI MA1

+0.7 5VS

0.1U _0402 _16V4Z
C1 54

1

1

2

2

C1 56

C1 55

1

2

Title

Size D ocum ent N umber Re v

Da te: She et o f

Compal Electronics, Inc.

1U_0 402_6 .3V6K

1

2

DDRIII-SODIMM SLOT2

LA -52 51P

0.1U _0402 _16V4Z

0.1U _0402 _16V4Z

1U_0 402_6 .3V6K

1U_0 402_6 .3V6K

C1 57

1

2

5

1U_0 402_6 .3V6K

C1 59

C1 58

C1 60

1

1

2

2

10 47T uesd ay, J anua ry 05 , 20 10

0. 9

1

A A

2

3

4

5

VDD_REF

XTAL_IN

XTAL_OUT

VSS_REF

VDD_CPU

CPU_0#

VSS_CPU

CPU_1#

VDD_SRC

0.1U _0402 _16V4Z
C1 67

+3V S_CK505

SMB _CLK_S 3
SMB _DATA_S3
RE F_0/ CPU_S EL

CLK _XTAL_IN
CLK_ XTAL_OUT

CK _P WRGD

R_ CLK_ BUF_B CLK CLK _BUF _BCL K
R_CL K_BU F_BC LK# CLK _BUF_ BCL K#

+3V S_CK505 _G +3VS +1.5V S

1 2

R1 43 0_06 03_5%@

1 2

R1 20 0_06 03_5%

0.1U _0402 _16V4Z

10U_ 0805_ 10V4Z

C1 69

C1 64

1

L

2

CPU_0

CPU_1

1

2

32

SCL

31

SDA

30
29
28
27
26
25

24
23
22
21
20
19
18
17

0.1U _0402 _16V4Z
C1 68

1

2

R1 07 33_0 402_5%

1 2

R1 10 0_02 01_5%

1 2

R1 12 0_02 01_5%

1 2

+1.0 5VS_ CK505
+3V S_CK5 05_G

1

2

C1 63

10P _0402 _50V8C@

CLK _14M_ PCH

09 /10 u pd ate

Lo w Po wer Chip : I nstal l R12 0 a nd re mov e R143 .
St an dard Po wer Ch ip: R emove R120 a nd In stall R1 43.

SMB _CLK_S3 4 ,9,10 ,13,24
SMB_D ATA_S3 4 ,9,10 ,13,24
CLK _14M_ PCH 13

CLK _BUF_ BCLK 13
CLK _BUF_ BCLK # 13

CK _P WRGD

09 /21 u pd ate

C1 77

33P _0402_50 V8J

R1 15

1 2

10K _0201_5%

61

Q55A

2

2N70 02DW H 2N SOT3 63-6

Y114.3 1818M HZ_2 0PF_ 7A14300038~ D

12

2

1

CLK_ XTAL_OUT

CLK _XTAL_IN

2

C1 78

33P _0402_50 V8J

1

+3V S_CK505

CL K_EN# 40

+3V S_CK505 _G

0.1U _0402 _16V4Z

1

2

0.1U _0402 _16V4Z

C1 74

1

2

CLK _BUF_ DOT96
CLK _BUF_ DOT 96#

CL K_B UF_CK SSCD
CL K_B UF_CK SSCD #

CLK _DMI
CLK _DMI#

C1 75

1

2

CLK _BUF_ DOT9613
CLK _BUF_ DOT96 #13

CL K_BU F_CK SSCD1 3
CL K_BU F_CK SSCD #13

CLK _DMI13
CLK _DMI#13

B B

+1.0 5VS_ CK505+1.0 5VS

1 2

R1 18 0_06 03_5%

C C

10U_ 0805_ 10V4Z

1

2

C1 71

10U_ 0805_ 10V4Z

1

2

Close to U6

0.1U _0402 _16V4Z

C1 72

C1 73

1

2

CPU _STOP #

47P _0402_5 0V8J

C1 76

R1 06 0_02 01_5%

1 2

R1 08 0_02 01_5%

1 2

+3V S_CK505

R1 09 0_02 01_5%

1 2

R1 11 0_02 01_5%

1 2

R1 13 0_02 01_5%

1 2

R1 14 0_02 01_5%

1 2

+1.0 5VS_ CK505

R1 16 10K_ 0201_5%

1 2

L_CL K_BU F_DO T96
L_CL K_BU F_DO T96#

L_ CLK_ BUF_C KSS CD
L_CL K_BU F_CK SSCD #

L_CL K_DM I
L_CL K_DM I#

CPU _STOP #

+3V S_CK505

U6

1

VDD_DOT

2

VSS_DOT

3

DOT_96

4

DOT_96#

5

VDD_27

6

27MHZ

7

27MHZ_SS

8

VSS_27

9

VSS_SATA

10

SRC_1/SATA

11

SRC_1#/SATA#

12

VSS_SRC

13

SRC_2

14

SRC_2#

15

VDD_SRC_IO

16

CPU_STOP#

ICS 9LVS 3197B KLFT MLF 32P

+3VS

1 2

R1 17 0_06 03_5%

+3V S_CK505

47P _0402_5 0V8J

1

2

TGND

33

07 /01 u pd ate

0.1U _0402 _16V4Z
C1 65

C1 70

1

2

0.1U _0402 _16V4Z

1

2

REF_0/CPU_SEL

CKPWRGD/PD#

VDD_CPU_IO

Close to U6

C1 66

1

2

Close to U2 within 500mil

D D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2010/12/31

Compal Secret Data

Deciphered Date

4

Title

Size D ocum ent N umber R ev

Da te: She et o f

Compal Electronics, Inc.

CLOCK GENERATOR

LA -52 51P

5

11 47T uesda y, J anuar y 05 , 201 0

0. 9

1

PCH _RTCX 1

32.7 68KH Z_12. 5PF_ Q13MC14 610002

PCH _RTCX 2

1

C1 82
18P _0402_5 0V8J

2

KBC _SPI _SI_R

PCH _JTA G_TCK

HDA _BIT _CLK_ MDC28
HDA _BIT _CLK_ CODE C26
HD A_S YNC _MDC28
HD A_S YNC _CO DEC2 6
HD A_SP KR2 6

HDA _RST #_MDC2 8
HD A_RS T#_CO DEC26

HD A_S DIN026

HD A_S DIN128

HD A_SD OUT_M DC28
HD A_S DOUT_ CODE C2 6

+R TCVC C

R1 26

R1 28

1U_0 603_1 0V4Z

1 2

20K _0201_1%

1 2

20K _0201_1%

1U_0 603_1 0V4Z

AQU AWHI TE_BA TLED

08 /28 u pd ate

R1 58

200_ 0402_5%@

1 2

PCH _JTA G_TDI

R1 67

100_ 0201_1%@

1 2

1

12

C1 80

2

1

12

C1 83

2

R1 29 33_0 402_5%

1 2

R1 30 33_0 402_5%

1 2

R1 31 33_0 402_5%

1 2

R1 32 33_0 402_5%

1 2

R1 33 33_0 402_5%

1 2

R1 34 33_0 402_5%

1 2

R1 36 33_0 402_5%

1 2

R1 37 33_0 402_5%

1 2

+3V ALW

07 /02 u pd ate

KBC _SPI _CLK_R30

KBC _SPI _CS0#_ R30

KBC _SPI _CS1#_ R30

KBC _SPI _SI_R30

1 2

R1 23 10M _0402_5%

18P _0402_5 0V8J

1

1

C1 81

Y2

2

HDA _BIT _CLK_ MDC

1 2

HDA _BIT _CLK_ CODE C

1 2

HD A_SD OUT_ MDC

1 2

HD A_S DOUT _CODE C

1 2

1 2

1 2

R1 76 51_0 402_5%

OSC4OSC

NC3NC

iT PM

iT PMiT PM

A A

2

@

C1 85 47P _0402_5 0V8J

@

C1 86 47P _0402_5 0V8J

@

C1 87 47P _0402_5 0V8J

@

C1 88 47P _0402_5 0V8J

B B

+3VM

iTPM ENABLE/DISABLE

R1 39 1K_ 0201_5%@

Enable=Stuff Disable=No Stuff

02 0 2 Dis abl e

02 0 2 Dis abl e iT PM

02 0 2 Dis abl e 0 202 D isa ble

C C

+R TCVC C +3VS

CL RP1

SHO RT P ADS@

CL RP2

SHO RT P ADS@

R1 38

1 2

1K_ 0201_5%

R8

1 2

10K _0402_5%

08 /31 u pd ate

T121P AD

KBC _SPI _SO30

12

R1 57

200_ 0402_5%@

PCH _JTA G_TDO

12

R1 66

100_ 0402_1%@

Pre -Pr od uctio n Uni ts Pro duc tion

ES1 AllES2

Ref .PCH Pin

R15 7

PCH _JT AG_TD O

D D

PCH _JT AG_TD I

PCH _JT AG_TM S

PCH _JT AG_TC K

1

R16 6

R15 8

R16 7

R15 6

R16 5

R17 6

Uns tuff

Uns tuff

200 ohm

100 ohm

200 ohm

51 ohm 5%

200 ohm

100 ohm

200 ohm

100 ohm

200 ohm

100 ohm

Uns tuff

Uns tuff

Uns tuff

Uns tuff

Uns tuff

Uns tuff100 ohm

51 ohm 5%51 ohm 5%

2

1 2

R1 21 1M_ 0402_5%

1 2

R1 24 330 K_0402_ 5%

PCH _RTCX 1
PCH _RTCX 2

PCH _RTCR ST#

PCH _SRT CRST#

S M_INT RUDE R#

PCH _INTV RME N

HDA _BIT _CLK

HD A_S YNC

HD A_SP KR

HDA _RST #

HD A_S DIN0

HD A_S DIN1

HD A_SD OUT

PCH _GPI O33

PCH _GPI O13

PCH _JTA G_TCK

PCH _JTAG_T MS

PCH _JTA G_TDI

PCH _JTA G_TDO

1 2

R1 44 0_04 02_5%

1 2

R1 48 0_04 02_5%

+3V ALW+3V ALW+3V ALW

12

R1 56

PCH _JTAG_T MS

12

R1 65

2

B13
D13

C14

D17

A16

A14

A30

D29

P1

C30

G30

F30

E32

F32

B29

H32

J30

M3

K3

K1

J2

J4

BA2

AV3

AY3

AY1

AV1

200_ 0402_5%@

100_ 0402_1%@

RTCX1
RTCX2

RTCRST#

SRTCRST#

INTRUDER#

INTVRMEN

HDA_BCLK

HDA_SYNC

SPKR

HDA_RST#

HDA_SDIN0

HDA_SDIN1

HDA_SDIN2

HDA_SDIN3

HDA_SDO

HDA_DOCK_EN# / GPIO33

HDA_DOCK_RST# / GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

JTAG_RST#

SPI_CLK

SPI_CS0#

SPI_CS1#

SPI_MOSI

SPI_MISO

IBE XPEAK- M_FCBGA1 071

S M_INT RUDE R# SI RQ

PCH _INTV RME N

U7 A

R1 22 10K_ 0201_5%

1 2

R1 25 10K_ 0201_5%@

RT CIH DA

SA TA

SPI JTAG

12

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

LP C

SERIRQ

SATA0RXN
SATA0RXP

SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP

SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP

SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP

SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP

SATA4TXN
SATA4TXP

SATA5RXN
SATA5RXP

SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATALED#

SATA0GP / GPIO21

SATA1GP / GPIO19

VGATE14,4 0

PLT_R ST#4,15 ,21, 22,23, 31

XDP _DBRESE T#4,14

D33
B33
C32
A32

C34

A34
F34

AB9

AK7
AK6
AK11
AK9

AH6
AH5
AH9
AH8

AF11
AF9
AF7
AF6

AH3
AH1
AF3
AF1

AD9
AD8
AD6
AD5

AD3
AD1
AB3
AB1

AF16

AF15

T3

Y9

V1

R2 14 1K_ 0402_5%

3

HD A_SP KR

NAN D_DET ECT#

SI RQ

SATA_ PRX_DTX_ N0
SATA_ PRX_DTX_P0
SATA_ PTX_DRX_ N0
SATA_ PTX_DRX_P0

SATA_ PRX_DTX_ N1
SATA_ PRX_DTX_P1
SATA_ PTX_DRX_ N1
SATA_ PTX_DRX_P1

SATA_ PRX_DTX_ N5
SATA_ PRX_DTX_P5
SATA_ PTX_DRX_ N5
SATA_ PTX_DRX_P5

SAT AICOMP IPCH _TRST #

R1 42 37.4 _0402_1 %

1 2

R1 45 10K_ 0201_5%

GPI O21

HD D_HA LTLE D

+3VS

R1 79

1 2

1K_ 0402_5%

1 2

PCH _JTA G_TDO

PCH _JTA G_TDI
PCH _JTAG_T MS

PCH _JTA G_TCK

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1 2

Issued Date

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

LPC _LAD0 2 2,30, 31
LPC _LAD1 2 2,30, 31
LPC _LAD2 2 2,30, 31
LPC _LAD3 2 2,30, 31

LPC _LFRA ME# 22, 30,31

NAN D_DET ECT# 23

SI RQ 22, 25,30 ,31

SATA_ PRX_DTX_ N0 22
SATA_ PRX_DTX_P0 2 2
SATA_ PTX_DRX_ N0 22
SATA_ PTX_DRX_P0 2 2

SATA_ PRX_DTX_ N1 22
SATA_ PRX_DTX_P1 2 2
SATA_ PTX_DRX_ N1 22
SATA_ PTX_DRX_P1 2 2

SATA_ PTX_DRX_ N5 29
SATA_ PTX_DRX_P5 2 9

+3VS

SAT A_LED# 2 8,29

HD D_HA LTLED 28

JP 5

1

OBSFN_A0

2

OBSFN_A1

3

GND

4

OBSDATA_A0

5

OBSDATA_A1

6

GND

7

OBSDATA_A2

8

OBSDATA_A3

9

GND
HOOK0
HOOK2
HOOK4
HOOK5
VCCOBS_AB
HOOK6
HOOK7
GND
TDO
TRST#
TDI
TMS
TCK1
GND
TCK0

MOLEX _52435-2472_ 24P-T

CO NN@

4

1

2

SATA_ PRX_DTX_ N5 29
SATA_ PRX_DTX_P5 2 9

+1.0 5VS

HD D_HA LTLE D

GPI O21

2008/09/15 2010/12/31

+3VS

R1 46

10K _0201_5%

Compal Secret Data

1 2

1 2

Deciphered Date

R1 47
10K _0201_5%

4

1

BAV 70W 3P C /C SOT -323

C1 84

1U_0 603_1 0V4Z

D1

5

BATT1 .1+V REG3_5 1125+R TCVC C

2

3

R1 27

R_B ATT1.1

1 2

1K_ 0201_5%

iAMT setting

AQU AWHI TE_BA TLED#28,3 0

1

+

SUY IN_06 0003F A002 G202NL

+3VS

R1 41

330K _0402_5 % @

1 2

2

1 2

AQU AWHI TE_BA TLED

61

GPIO33 iAMT En able / Disable

Hi

Enable (Defau lt)

DisableLo

Title

Size D ocum ent N umber R ev

Cu sto m

Da te: She et o f

Compal Electronics, Inc.

IBEX-M(1/6)-HDA/JTAG/SATA

LA -52 51P

5

JBATT1

2

-

CO NN@

R1 40

10K _0201_5%@

Q31A
2N70 02DW H 2N SOT3 63-6

12 47T uesda y, J anuar y 05 , 201 0

0. 9

1

A A

PCI E_PRX_D TX_N22 3
PCIE _PRX_DTX _P22 3
PCI E_PT X_C_DRX_N 22 3
PCI E_PTX _C_DRX_P223

PCI E_PRX_D TX_N42 2
PCIE _PRX_DTX _P42 2
PCI E_PT X_C_DRX_N 42 2
PCI E_PTX _C_DRX_P422

PCI E_PRX_D TX_N62 1
PCIE _PRX_DTX _P62 1
PCI E_PT X_C_DRX_N 62 1
PCI E_PTX _C_DRX_P621

B B

07 /01 u pd ate

CLK _PCIE _LAN _REQ1#21

CLK _PCIE_E XP#23
CLK _PCIE_E XP2 3

CLK REQ_EXP #23

+3VS

C C

CLK _PCIE _MCA RD#22
CLK _PCIE _MCA RD22

CL KREQ _WLA N#2 2

11 /13 u pd ate

C1 93 0.1U_04 02_25V4 K
C1 94 0.1U_04 02_25V4 K

C1 95 0.1U_04 02_25V4 K
C1 96 0.1U_04 02_25V4 K

C1 97 0.1U_04 02_25V4 K
C1 98 0.1U_04 02_25V4 K

+3V ALW

+3VS

R2 03 0_04 02_5%

1 2

R2 04 0_04 02_5%

1 2

10K _0201_5%

R2 05

1 2

+3V ALW

R2 08 0_04 02_5%

1 2

R2 09 0_04 02_5%

1 2

+3V ALW

+3V ALW

+3V ALW

1 2
1 2

1 2
1 2

1 2
1 2

R2 00 10K _0201_5%

1 2

R2 02 10K _0201_5%

1 2

R2 07 10K _0201_5%

1 2

R2 12 10K _0201_5%

1 2

R2 13 10K _0201_5%

1 2

R7 01 10K _0201_5%

1 2

PCI E_PRX_ DTX_N2
PCI E_PRX_DT X_P2
PCI E_PTX _DRX_N2
PCI E_PTX_DR X_P2

PCI E_PRX_ DTX_N4
PCI E_PRX_DT X_P4
PCI E_PTX _DRX_N4
PCI E_PTX_DR X_P4

PCI E_PRX_ DTX_N6
PCI E_PRX_DT X_P6
PCI E_PTX _DRX_N6
PCI E_PTX_DR X_P6

CLK _PCI E_EXP#_R
CLK _PCI E_EXP_R

CLK _PCIE _MCA RD#_ R
CL K_PC IE_M CARD _R

2

U7 B

BG30

PERN1

BJ30

PERP1

BF29

PETN1

BH29

PETP1

AW30

PERN2

BA30

PERP2

BC30

PETN2

BD30

PETP2

AU30

PERN3

AT30

PERP3

AU32

PETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

P9

PCIECLKRQ0# / GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

U4

PCIECLKRQ1# / GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

N4

PCIECLKRQ2# / GPIO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

AM51

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

M9

PCIECLKRQ4# / GPIO26

AJ50

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

H6

PCIECLKRQ5# / GPIO44

AK53

CLKOUT_PEG_B_N

AK51

CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ# / GPIO56

IBE XPEAK- M_FCBGA1 071

SMBus

PCI-E*

Link

Con trol ler

PEG_A_CLKRQ# / GPIO47

PEG

CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P

From C LK BUF FER

CLKIN_SATA_N / CKSSCD_N

CLKIN_SATA_P / CKSSCD_P

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

Clock Flex

SMBALERT# / GPIO11

SMBCLK

SMBDATA

SML0ALERT# / GPIO60

SML0CLK

SML0DATA

SML1ALERT# / GPIO74

SML1CLK / GPIO58

SML1DATA / GPIO75

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_BCLK_N
CLKIN_BCLK_P

CLKIN_DOT_96N
CLKIN_DOT_96P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

B9

H14

C8

J14

C6

G8

M14

E10

G12

T13

T11

T9

H1

AD43
AD45

AN4
AN2

AT1
AT3

AW24
BA24

AP3
AP1

F18
E18

AH13
AH12

P41

J42

AH51
AH53

AF38

T45

P43

T42

N50

LID_ SW#_ ISO#

SM BCLK

SMBDA TA

SML 0ALERT#

SML 0CLK

SML 0DATA

SML 1ALERT#

SML 1CLK

SML 1DATA

R_C LK_EXP#
R_C LK_EXP

R_ CLK_ DP#
R_ CLK_ DP

XTA L25_IN
XTAL25 _OUT

XCL K_RCOM P

3

LID_ SW#_ ISO# 2 0

SML 0CLK 21

SML0D ATA 21

CL _CLK1 2 2

CL_D ATA1 2 2

CL_R ST1# 2 2

R1 95 0_04 02_5%

1 2

R1 96 0_04 02_5%

1 2

R1 97 0_02 01_5%

1 2

R1 98 0_02 01_5%

1 2

CLK _DMI# 11
CLK _DMI 1 1

CLK _BUF_ BCLK # 11
CLK _BUF_ BCLK 11

CLK _BUF_ DOT96 # 11
CLK _BUF_ DOT96 11

CL K_BU F_CK SSCD # 11
CL K_BU F_CK SSCD 1 1

CLK _14M_ PCH 11

CL K_PCI _FB 1 5

R2 11 90.9 _0402_1 %

1 2

T55 P AD

T56 P AD

07 /03 u pd ate

CLK_EX P# 4
CLK_EX P 4

CLK _DP# 4
CL K_DP 4

+1.0 5VS

4

1 2

SMB _DATA_S3

R1 83 10K_ 0201_5%

1 2

R1 85 10K_ 0201_5%

4/2 3 C hange R1 87, R188 f rom 4 .7K_02 01
to 2.2K_0402 .

07 /03 u pd ate

Q8A

2N70 02DW -T/R7 _SOT363- 6

SM BCLK

6 1

+3VS

SMBDA TA SMB _DATA_S3

3

2N70 02DW -T/R7 _SOT363- 6

2N70 02DW -T/R7 _SOT363- 6

SML 1CLK

+3V ALW

SML 1DATA

4

XTA L25_IN

XTAL25 _OUT

SMB _CLK_S 3

2

5

4

Q8B

Q2A

1 2

61

0_02 01_5%

R2 63

2

5

R2 64

1 2

3

2N70 02DW -T/R7 _SOT363-6

0_02 01_5%

Q2B

1 2

R2 10 1M_0 402_5%

1 2

25MHZ_20PF_7A25000012

C1 99

1

18P _0402_50 V8J

2

Y3

SM BCLKSMB _CLK_S 3

+3VS

SMBDA TA

SML 0CLK

SML 0DATA

SML 1CLK

SML 1DATA

SML 0ALERT#

SML 1ALERT#

SMB _CLK_S3 4 ,9,10 ,11,24

SMB_ DATA_S3 4 ,9,10 ,11, 24

CAP _CLK 2 8,30

CAP _DAT 2 8,30

C2 00

1

18P _0402_5 0V8J

2

1 2

R1 84 2.2K _0402_ 5%

1 2

R1 86 2.2K _0402_ 5%

1 2

R1 87 2.2K _0402_ 5%

1 2

R1 88 2.2K _0402_ 5%

1 2

R1 89 4.7K _0201_ 5%

1 2

R1 91 4.7K _0201_ 5%

1 2

R1 92 10K_ 0201_5%

1 2

R1 94 10K_ 0201_5%

5

+3V ALW

6/1 6 R eserve ba ck th e 2 5MH z des ig n c ircui t. (Reser ve Y3 ,
R21 0,C 199 ); Move R10 93 to cl ose to Y3 and C199.
7/1 De l T12 2, Del R 1093 (0_040 2) and r epl ace b y a dd C2 00
(18 P); Inst all R210, Y3,C1 99 by Intel finalize d DP
wo rk ar ou nd an d n ee d the m.

D D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2010/12/31

Compal Secret Data

Deciphered Date

4

Title

Size D ocum ent N umber R ev

Cu sto m

Da te: She et o f

Compal Electronics, Inc.

IBEX-M(2/6)-PCI-E/SMBUS/CLK

LA -52 51P

5

13 47T uesda y, J anuar y 05 , 201 0

0. 9

5

4

3

2

1

DMI _CTX_PRX _N05
DMI _CTX_PRX _N15
DMI _CTX_PRX _N25
DMI _CTX_PRX _N35

DMI_CT X_PRX_P05
DMI_CT X_PRX_P15
DMI_CT X_PRX_P25

D D

PG D_I N30,4 0

07 /01 u pd ate 08 /25 u pd ate

C C

PM_ PWRB TN#_R4
ON /OFF BTN#28,3 0

01/ 04 up dat e for ESD

0.1U _0402 _16V4Z

Add C145 close to R231 pin 1.

L

B B

04 /2 8 R emove R238
(Co nf irm wh y pul l up to

Sus -Po wer d iff erent to

IN T EL DG Co re- Pow er)

DMI_CT X_PRX_P35

DMI _CRX_PTX _N05
DMI _CRX_PTX _N15
DMI _CRX_PTX _N25
DMI _CRX_PTX _N35

DMI_CRX _PTX_P05
DMI_CRX _PTX_P15
DMI_CRX _PTX_P25
DMI_CRX _PTX_P35

+1.0 5VS

1 2

R2 20 49.9 _0402_1 %

XDP _DBRESE T#4,12

VGATE12, 40

R4 08 1K_0 402_5%

1 2

M_P WROK3 2

PM_ DRAM _PWR GD4

RP GOOD36
PM_RS MRST#30

+3V ALW

SUS _PWR _ACK30

ON /OFF BTN#

AC_ PRES ENT3 0

ON /OFF BTN#

1

C1 45

2

DMI _CTX_PR X_N0
DMI _CTX_PR X_N1
DMI _CTX_PR X_N2
DMI _CTX_PR X_N3

DMI_CT X_PRX_P0
DMI_CT X_PRX_P1
DMI_CT X_PRX_P2
DMI_CT X_PRX_P3

DMI _CRX_PT X_N0
DMI _CRX_PT X_N1
DMI _CRX_PT X_N2
DMI _CRX_PT X_N3

DMI_CRX _PTX_P0
DMI_CRX _PTX_P1
DMI_CRX _PTX_P2
DMI_CRX _PTX_P3

DMI _IRCO MP

SYS _RS T#

1 2

R2 23 0_02 01_5%

VGATE

1 2

R2 24 0_02 01_5%

AUX PWROK

1 2

R2 25 0_02 01_5%

PM_ DRAM _PW RGD

R2 28 0_02 01_5%

1 2
1 2

1 2

1 2

LOW _BAT_ R

IBE X_R#

R2 29 10K_ 0201_5%
R2 30 10K_ 0201_5%

R2 31 0_02 01_5%

P M_CLK RUN#

SYS _RS T#

LOW _BAT_ R

PM_ SLP_LAN #

IBE X_R#

PCI E_WA KE#

AC_ PRES ENT

07 /01 u pd ate

U7C

BC24

DMI0RXN

BJ22

DMI1RXN

AW20

DMI2RXN

BJ20

DMI3RXN

BD24

DMI0RXP

BG22

DMI1RXP

BA20

DMI2RXP

BG20

DMI3RXP

BE22

DMI0TXN

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

T6

SYS_RESET#

M6

SYS_PWROK

B17

PWROK

K5

MEPWROK

A10

LAN_RST#

D9

DRAMPWROK

C16

RSMRST#

M1

SUS_PWR_ACK / GPIO30

P5

PWRBTN#

P7

ACPRESENT / GPIO31

A6

BATLOW# / GPIO72

F14

RI#

IBE XPEAK- M_FCBGA1 071

1 2

R2 37 10K _0201_5%

1 2

R2 38 10K _0201_5%@

1 2

R2 39 10K _0201_5%

1 2

R2 41 10K _0201_5%

1 2

R2 43 10K _0201_5%

1 2

R2 45 1K_ 0201_5%

1 2

R2 46 10K_ 0201_5%@

+3VS

+3V ALW

VGATE

SLP _S3#

SLP _S4#

SLP _S5#

DMI

FDI

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Manag ement

1 2

R2 36 10K _0201_5%

1 2

R2 40 10K _0201_5%@

1 2

R2 42 10K _0201_5%@

1 2

R2 44 10K _0201_5%@

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

WAKE#

SLP_S4#

SLP_S3#

SLP_M#

PMSYNCH

SLP_LAN#

TP23

BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12

BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12

BJ14

BF13

BH13

BJ12

BG14

J12

Y1

P8

F3

E4

H7

P12

K8

N2

BJ10

F6

FDI _CTX_ PRX_N0
FDI _CTX_ PRX_N1
FDI _CTX_ PRX_N2
FDI _CTX_ PRX_N3
FDI _CTX_ PRX_N4
FDI _CTX_ PRX_N5
FDI _CTX_ PRX_N6
FDI _CTX_ PRX_N7

FDI _CTX_PR X_P0
FDI _CTX_PR X_P1
FDI _CTX_PR X_P2
FDI _CTX_PR X_P3
FDI _CTX_PR X_P4
FDI _CTX_PR X_P5
FDI _CTX_PR X_P6
FDI _CTX_PR X_P7

FD I_I NT

FD I_F SYN C0

FD I_F SYN C1

FD I_L SY NC0

FD I_L SY NC1

PCI E_WA KE#

P M_CLK RUN#

SUS_S TAT#

SUS _CLK

FDI _CTX_ PRX_N0 5
FDI _CTX_ PRX_N1 5
FDI _CTX_ PRX_N2 5
FDI _CTX_ PRX_N3 5
FDI _CTX_ PRX_N4 5
FDI _CTX_ PRX_N5 5
FDI _CTX_ PRX_N6 5
FDI _CTX_ PRX_N7 5

FDI _CTX_PRX _P0 5
FDI _CTX_PRX _P1 5
FDI _CTX_PRX _P2 5
FDI _CTX_PRX _P3 5
FDI _CTX_PRX _P4 5
FDI _CTX_PRX _P5 5
FDI _CTX_PRX _P6 5
FDI _CTX_PRX _P7 5

FD I_IN T 5

FD I_F SYN C0 5

FD I_F SYN C1 5

FD I_L SYN C0 5

FD I_L SYN C1 5

PCI E_WA KE# 22 ,23

PM _CLK RUN# 25 ,30,31

T87 P AD

T58 P AD

SLP _S5#

SLP _S4# 24, 29,33 ,39

SLP _S3# 23, 29,30 ,32,3 3,35,3 7,38

PM_SL P_M# 30, 32,33

H_ PM_S YNC 4

PM_ SLP_LAN# 30,33,3 9

ENA BLT2 0
EN AVD D20

INV _PWM2 0

04/ 25 Del ete U7 .AT42 an d U7. AT4 3 DGND
con necti on (conf irmed wi th IN TEL)

CR T_D DC_C LK1 8
CR T_DDC _DAT A18

CR T_H SYN C18
CR T_V SYN C18

T57PA D

R2 32

1K_0402_0.5%

DA C_B LU
DA C_G RN
DA C_R ED

DA C_I REF

R2 47

150_ 0402_1%@

12

150_ 0402_1%@

AB48

AB46

AP39
AP41

AT43
AT42

AV53
AV51

BB47
BA52
AY48
AV47

BB48
BA50
AY49
AV48

AP48
AP47

AY53
AT49
AU52
AT53

AY51
AT48
AU50
AT51

AA52
AB53
AD53

AD48
AB51

R2 48

150_ 0402_1%@

12

12

U7D

T48

L_BKLTEN

T47

L_VDD_EN

Y48

L_BKLTCTL

L_DDC_CLK

Y45

L_DDC_DATA

L_CTRL_CLK

V48

L_CTRL_DATA

LVD_IBG
LVD_VBG

LVD_VREFH
LVD_VREFL

LVDSA_CLK#
LVDSA_CLK

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

LVDSB_CLK#
LVDSB_CLK

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED

V51

CRT_DDC_CLK

V53

CRT_DDC_DATA

Y53

CRT_HSYNC

Y51

CRT_VSYNC

DAC_IREF
CRT_IRTN

IBE XPEAK- M_FCBGA 1071

DA C_G RN

DA C_B LU

R2 49

11 /27 u pd ate

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN

SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

Digital Disp lay In terface

DDPD_CTRLCLK

DDPD_CTRLDATA

CRT

HLC0 603CS CC33 NJT_ 0603

HLC0 603CS CC33 NJT_ 0603

HLC0 603CS CC33 NJT_ 0603

18P _0402_5 0V8J

18P _0402_5 0V8J

1

2

18P _0402_5 0V8J

C2 33

C2 32

1

1

2

2

BJ46
BG46

BJ48
BG48

2.2K_0402_5%

BF45

SDVO_INTN

BH45

SDVO_INTP

T51
T53

BG44

DDPB_AUXN

BJ44

DDPB_AUXP

AU38

DDPB_HPD

BD42

DDPB_0N

BC42

DDPB_0P

BJ42

DDPB_1N

BG42

DDPB_1P

BB40

DDPB_2N

BA40

DDPB_2P

AW38

DDPB_3N

BA38

DDPB_3P

Y49
AB49

BE44

DDPC_AUXN

BD44

DDPC_AUXP

AV40

DDPC_HPD

BE40

DDPC_0N

BD40

DDPC_0P

BF41

DDPC_1N

BH41

DDPC_1P

BD38

DDPC_2N

BC38

DDPC_2P

BB36

DDPC_3N

BA36

DDPC_3P

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

DDPD_0N

DDPD_0P

DDPD_1N

DDPD_1P

DDPD_2N

DDPD_2P

DDPD_3N

DDPD_3P

1/4 u pda te L1 ~L6 PC B Foo tprint

L1

1 2

L3

1 2

L5

1 2

C2 34

U50
U52

BC46
BD46
AT38

BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36

R2 26
R2 27

C_DP D_AU X#
C_DP D_A UX

C_DP D_TX N0
C_DP D_TXP 0
C_DP D_TX N1
C_DP D_TXP 1
C_DP D_TX N2
C_DP D_TXP 2
C_DP D_TX N3
C_DP D_TXP 3

RE D_LDA C_R ED

GR EEN_ L

BLU E_L

1

2

18P _0402_5 0V8J@

DP B_H PD

DP D_H PD

1

C2 35

2

+3VS

R2 16

R2 15

2.2K_0402_5%

DPB _AUX# 2 9
DPB _AUX 29
DP B_HP D 29

DPB_T XN0 29
DPB_TX P0 29
DPB_T XN1 29
DPB_TX P1 29
DPB_T XN2 29
DPB_TX P2 29
DPB_T XN3 29
DPB_TX P3 29

2.2K_0402_5%

2.2K_0402_5%

C2 22 0.1 U_040 2_16V 4Z

1 2

C2 23 0.1 U_040 2_16V 4Z

1 2

C2 24 0.1 U_040 2_16V 4Z

1 2

C2 25 0.1 U_040 2_16V 4Z

1 2

C2 26 0.1 U_040 2_16V 4Z

1 2

C2 27 0.1 U_040 2_16V 4Z

1 2

C2 28 0.1 U_040 2_16V 4Z

1 2

C2 29 0.1 U_040 2_16V 4Z

1 2

C2 30 0.1 U_040 2_16V 4Z

1 2

C2 31 0.1 U_040 2_16V 4Z

1 2

1 2

R2 33 100 K_0201_5 %

1 2

R2 35 100 K_0201_5 %

L2
0_06 03_5%

1 2

L4
0_06 03_5%

1 2

L6
0_06 03_5%

1 2

1

C2 36

C2 37

2

18P _0402_5 0V8J@

18P _0402_5 0V8J@

Pla ce C669 c lo se to R2 15.

L

1

C6 69

0.1U _0402 _16V4Z

2

11/ 11 up dat e for EM I.

DPB _CTR LCLK 2 9
DPB _CTR LDATA 2 9

DPD _CTRL DATA 19

RE D_R 1 8

GR EEN_ R 18

BL UE_R 1 8

DP D_CT RLCLK 19

DPD _AUX# 19
DPD _AUX 19
DP D_H PD 19

DPD _TXN0 19
DPD_T XP0 19
DPD _TXN1 19
DPD_T XP1 19
DPD _TXN2 19
DPD_T XP2 19
DPD _TXN3 19
DPD_T XP3 19

+3VS

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2010/12/31

Compal Secret Data

Deciphered Date

2

Title

Size D ocum ent N umber R ev

Cu sto m

Da te: She et o f

Compal Electronics, Inc.

IBEX-M(3/6)-DMI/GPIO/LVDS

LA -52 51P

1

14 47T uesda y, J anuar y 05 , 201 0

0. 9

5

PC I_AD [0.. 31]2 5

D D

PCI _CBE 0#2 5
PCI _CBE 1#2 5
PCI _CBE 2#2 5
PCI _CBE 3#2 5

PCI _REQ 2#25

C C

T114PA D

PCI _GNT2 #25

PCI _PIRQ E#25
ODD _DET#2 2
PC I_PI RQG#2 5
ACC EL_IN T#24

PCI _RST#22 ,25

PC I_SE RR#2 2,25, 30,31
PC I_PE RR#25

PC I_I RDY #25
PC I_PA R25
PCI _DEV SEL#2 5
PCI _FRA ME#25

PCI _STOP#25
PC I_T RDY#25

PC I_P IRQD #
PCI _PIRQ E#
PCI _STOP#

PCI _REQ 2#
PCI _REQ 1#
PCI _FRA ME#
PC I_ TRDY#

PC I_I RD Y#
PC I_P ERR#
PCI _DEV SEL#
PC I_S ERR#

PCI _REQ 0#
PCI _PIRQ B#
OD D_DE T#
PCI _REQ 3#

PCI _GNT 3#

PLT_R ST#4,12 ,21, 22,23, 31

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 2

R3 00 1K_0 201_5% @

B B

10 /21 u pd ate

A A

PC I_A D0
PC I_A D1
PC I_A D2
PC I_A D3
PC I_A D4
PC I_A D5
PC I_A D6
PC I_A D7
PC I_A D8
PC I_A D9
P CI_AD 10
P CI_AD 11
P CI_AD 12
P CI_AD 13
P CI_AD 14
P CI_AD 15
P CI_AD 16
P CI_AD 17
P CI_AD 18
P CI_AD 19
P CI_AD 20
P CI_AD 21
P CI_AD 22
P CI_AD 23
P CI_AD 24
P CI_AD 25
P CI_AD 26
P CI_AD 27
P CI_AD 28
P CI_AD 29
P CI_AD 30
P CI_AD 31

PCI _PIRQ A#
PCI _PIRQ B#
PC I_P IRQC #
PC I_P IRQD #

PCI _REQ 0#
PCI _REQ 1#
PCI _REQ 2#
PCI _REQ 3#

PCI _GNT 0#

MOD EM_DIS ABLE

PCI _GNT 2#
PCI _GNT 3#

PCI _PIRQ E#
OD D_DE T#
P CI_PI RQG#
ACC EL_IN T#

PC I_S ERR#
PC I_P ERR#

PC I_I RD Y#

PCI _DEV SEL#
PCI _FRA ME#

PCI _LOCK #

PCI _STOP#
PC I_ TRDY#

CL K_PC I_KB C_R
CL K_P CI_FB _R
CLK _PCI_ TPM_R
CLK _PCI_ 1394 _R
CLK _PCI_ DB_P

RP 1

8.2K _080 4_8P4R_ 5%
RP 2

8.2K _080 4_8P4R_ 5%
RP 3

8.2K _080 4_8P4R_ 5%
RP 4

8.2K _080 4_8P4R_ 5%

5

U7 E

H40

AD0

N34

AD1

C44

AD2

A38

AD3

C36

AD4

J34

AD5

A40

AD6

D45

AD7

E36

AD8

H48

AD9

E40

AD10

C40

AD11

M48

AD12

M45

AD13

F53

AD14

M40

AD15

M43

AD16

J36

AD17

K48

AD18

F40

AD19

C42

AD20

K46

AD21

M51

AD22

J52

AD23

K51

AD24

L34

AD25

F42

AD26

J40

AD27

G46

AD28

F44

AD29

M47

AD30

H36

AD31

J50

C/BE0#

G42

C/BE1#

H47

C/BE2#

G34

C/BE3#

G38

PIRQA#

H51

PIRQB#

B37

PIRQC#

A44

PIRQD#

F51

REQ0#

A46

REQ1# / GPIO50

B45

REQ2# / GPIO52

M53

REQ3# / GPIO54

F48

GNT0#

K45

GNT1# / GPIO51

F36

GNT2# / GPIO53

H53

GNT3# / GPIO55

B41

PIRQE# / GPIO2

K53

PIRQF# / GPIO3

A36

PIRQG# / GPIO4

A48

PIRQH# / GPIO5

K6

PCIRST#

E44

SERR#

E50

PERR#

A42

IRDY#

H44

PAR

F46

DEVSEL#

C46

FRAME#

D49

PLOCK#

D41

STOP#

C48

TRDY#

M7

PME#

D5

PLTRST#

N52

CLKOUT_PCI0

P53

CLKOUT_PCI1

P46

CLKOUT_PCI2

P51

CLKOUT_PCI3

P48

CLKOUT_PCI4

+3VS

IBE XPEAK- M_FCBGA1 071

C6 61 0.1U _0402 _16V4Z

1 2

+3VS +1.05VM

CL K_PCI _KBC30

CL K_PC I_DB22, 31
CL K_PCI _FB1 3
CLK _PCI_TP M31

CLK _PCI_ 13942 5

PCI _PIRQ A#
THE RM_S CI#
PC I_P IRQC #
P CI_PI RQG#

ACC EL_IN T#
PCI _LOCK #

10 /19 u pd ate

RP 5

1 8
2 7
3 6
4 5

8.2K _080 4_8P4R_ 5%

RP 6

1 8
2 7
3 6
4 5

8.2K _080 4_8P4R_ 5%

NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3

NV_DQS0
NV_DQS1

NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8

NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11

NV RAM

NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15

NV_ALE
NV_CLE

NV_RCOMP

PC I

R2 66 22_0 402_5%

R2 74 22_0 402_5%
R2 76 22_0 402_5%
R2 78 22_0 402_5%

R2 82 22_0 402_5%

NV_RB#

NV_WR#0_RE#
NV_WR#1_RE#

NV_WE#_CK0
NV_WE#_CK1

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USB

USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

+1.05 VS +3VS

1 2

1 2
1 2
1 2

1 2

+3VS

C6 62 0.1U _0402 _16V4Z

C6 63 0.1U _0402 _16V4Z

AY9
BD1
AP15
BD8

AV9
BG8

AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6

NV_ ALE

BD3

NV _CLE

AY6

NV_ RCOM P

AU2

AV7

AY8
AY5

AV11
BF5

H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24

B25

D25

N16
J16
F16
L16
E14
G16
F12
T15

1 2

1 2

CL K_PC I_KB C_R

CLK _PCI_ DB_P
CL K_P CI_FB _R
CLK _PCI_ TPM_R

CLK _PCI_ 1394 _R

BUF _PLT_R ST#4

4

USB 20_N0
USB 20_P0
USB 20_N1
USB 20_P1
USB 20_N2
USB 20_P2
USB 20_N3
USB 20_P3
USB 20_N4
USB 20_P4

10 /13 u pd ate

USB 20_N8
USB 20_P8
USB 20_N9
USB 20_P9
USB 20_N 10
USB 20_P10
USB 20_N 11
USB 20_P11
USB 20_N 12
USB 20_P12

USB RBIA S

USB _OC# 0

USB _OC# 2

USB _OC# 4

USB _OC# 6
WO W#

+1.05V M+1.05 VS

4

NV _CE0# 23
NV _CE1# 23
NV _CE2# 23
NV _CE3# 23

NV _DQS 0 23
NV _DQS 1 23

NV _DQ0 2 3
NV _DQ1 2 3
NV _DQ2 2 3
NV _DQ3 2 3
NV _DQ4 2 3
NV _DQ5 2 3
NV _DQ6 2 3
NV _DQ7 2 3
NV _DQ8 2 3
NV _DQ9 2 3
NV _DQ1 0 2 3
NV _DQ1 1 2 3
NV _DQ1 2 2 3
NV _DQ1 3 2 3
NV _DQ1 4 2 3
NV _DQ1 5 2 3

NV_ ALE 23
NV _CLE 23

09 /03 u pd ate

1 2

R2 57 32.4 _0402_ 1%@

NV _RB# 2 3

NV _RE #_WR# 0 2 3
NV _RE #_WR# 1 2 3

NV _WE# _CK0 2 3
NV _WE# _CK1 2 3

USB 20_N0 24
USB 20_P0 2 4
USB 20_N1 24
USB 20_P1 2 4
USB 20_N2 24
USB 20_P2 2 4
USB 20_N3 24
USB 20_P3 2 4
USB 20_N4 23
USB 20_P4 2 3

USB 20_N8 24
USB 20_P8 2 4
USB 20_N9 23
USB 20_P9 2 3
USB 20_N1 0 31
USB 20_P10 31
USB 20_N1 1 29
USB 20_P11 29
USB 20_N1 2 20
USB 20_P12 20

1 2

R2 59 22. 6_0402 _1%

R2 65

08 /25 u pd ate

12

0_04 02_5%

PCI _GNT 0#

MOD EM_DIS ABLE

BT_ OFF 2 4

FP R_O FF 31

PRE P# 18, 21,29

LA NLIN K_R# 2 1,30

+3VS

07/ 08 up dat e for INT EL
S3 l eaka ge is sue .

CPP E# 23

R2 67 1K_ 0201_5%@

1 2

R2 71 1K_ 0201_5%@

1 2

07 /09 u pda te fo r I NTEL S3 le aka ge issue.

GPI O15

R3 02 10K _0201_5%LV@

1 2

09 /12 u pd ate

CP U Type Det ect : Hi gh--> SV , Low -->LV

L

1 2

R2 88 0_02 01_5%

+3VS

5

U1 0

1

P

IN1

4

O

2

IN2

G

SN7 4AHC1 G08D CKR_S C70- 5@

3

R2 50 10K_ 0201_5%

WWA N_TR ANSM IT_O FF#23,2 8

06 /16 u pd ate

CLK _PCIE _LAN _REQ#21

PCH _XDP _GPIO49

WLA N_TRA NSM IT_OFF#22

PLT_ RST#

3

1 2

PCH _XDP _GPIO0

OC P#4 1

RU NSC I_E C#30

THE RM_S CI#4

PC H_D DR_R ST4

LA N_DI S#21

ALS _EN#20

WW AN_D ET#23

NPC I_RST #30

WEB CAM _ON20

DO CK_ ID029

DO CK_ ID129

+3V ALW

PC H_N CTF617
PC H_N CTF717

PC H_NC TF191 7

PC H_NC TF261 7

Danbur y Technology Enable
NV_ALE High=Endabled

NV_ ALE

DMI Te rmination Voltage
NV_CLE Set to Vss when LOW

NV _CLE

3

PCH _XDP _GPIO0

RU NSC I_E C#

THE RM_S CI#

PC H_D DR_R ST

GPI O15

PCH _XDP _GPIO16

ALS _EN#

WW AN_D ET#

GPI O24

WWA N_TR ANSM IT_O FF#

PCH _XDP _GPIO28

STP _PCI#

SAT A_CLK REQ#

WEB CAM _ON

DO CK _ID0

DO CK _ID1

CLK _PCIE _LAN _REQ#

10K _0201_5%

R4 30

1 2

GPI O48

PCH _XDP _GPIO49

WLA N_TRA NSM IT_OFF#

Low=Di sable (@)

+V_ NVRA M_VCCQ

1 2

R2 84 1K_ 0201_5%@

Set to Vcc when HIGH

1 2

R2 97 1K_ 0201_5%@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

U7 F

Y3

BMBUSY# / GPIO0

C38

TACH1 / GPIO1

D37

TACH2 / GPIO6

J32

TACH3 / GPIO7

F10

GPIO8

K9

LAN_PHY_PWR_CTRL / GPIO12

T7

GPIO15

AA2

SATA4GP / GPIO16

F38

TACH0 / GPIO17

Y7

SCLOCK / GPIO22

H10

MEM_LED / GPIO24

AB12

GPIO27

V13

GPIO28

M11

STP_PCI# / GPIO34

V6

SATACLKREQ# / GPIO35

AB7

SATA2GP / GPIO36

AB13

SATA3GP / GPIO37

V3

SLOAD / GPIO38

P3

SDATAOUT0 / GPIO39

H3

PCIECLKRQ6# / GPIO45

F1

PCIECLKRQ7# / GPIO46

AB6

SDATAOUT1 / GPIO48

AA4

SATA5GP / GPIO49

F8

GPIO57

A4

VSS_NCTF_1

A49

VSS_NCTF_2

A5

VSS_NCTF_3

A50

VSS_NCTF_4

A52

VSS_NCTF_5

A53

VSS_NCTF_6

B2

VSS_NCTF_7

B4

VSS_NCTF_8

B52

VSS_NCTF_9

B53

VSS_NCTF_10

BE1

VSS_NCTF_11

BE53

VSS_NCTF_12

BF1

VSS_NCTF_13

BF53

VSS_NCTF_14

BH1

VSS_NCTF_15

BH2

VSS_NCTF_16

BH52

VSS_NCTF_17

BH53

VSS_NCTF_18

BJ1

VSS_NCTF_19

BJ2

VSS_NCTF_20

BJ4

VSS_NCTF_21

BJ49

VSS_NCTF_22

BJ5

VSS_NCTF_23

BJ50

VSS_NCTF_24

BJ52

VSS_NCTF_25

BJ53

VSS_NCTF_26

D1

VSS_NCTF_27

D2

VSS_NCTF_28

D53

VSS_NCTF_29

E1

VSS_NCTF_30

E53

VSS_NCTF_31

IBE XPEAK- M_FCBGA 1071

+3VS

2008/09/15 2010/12/31

GPIO

NCTF

RSVD

WLA N_TRA NSM IT_OFF#

WWA N_TR ANSM IT_O FF#

GPI O24

GPI O15

PRE P#

CLK _PCIE _LAN _REQ#

USB _OC# 0

PC H_D DR_R ST

USB _OC# 4

WO W#

PCH _XDP _GPIO28

USB _OC# 6

USB _OC# 2 LA N_DI S#

Compal Secret Data

2

CLKOUT_PCIE6N
CLKOUT_PCIE6P

CLKOUT_PCIE7N

MISC

CLKOUT_BCLK0_N / CLKOUT_PCIE8N

CLKOUT_BCLK0_P / CLKOUT_PCIE8P

CPU

Deciphered Date

CLKOUT_PCIE7P

PROCPWRGD

THRMTRIP#

R2 69 10K_ 0201_5%

1 2

R2 73 10K_ 0201_5%

1 2

R2 77 10K_ 0201_5%

1 2

R2 80 1K_ 0201_5%SV@

1 2

R2 83 10K_ 0201_5%

1 2

R2 86 10K_ 0201_5%

1 2

R2 89 10K_ 0201_5%

1 2

R2 91 10K_ 0201_5%@

1 2

R2 93 10K_ 0201_5%

1 2

R2 95 10K_ 0201_5%

1 2

R3 68 10K_ 0201_5%

1 2

R2 58 10K_ 0201_5%

R3 01 10K_ 0201_5%

12

12

2

AH45
AH46

AF48
AF47

U2

A20GATE

AM3

AM1

BG10

PECI

T1

RCIN#

BE10

BD10

BA22

TP1

AW22

TP2

BB22

TP3

AY45

TP4

AY46

TP5

AV43

TP6

AV45

TP7

AF13

TP8

M18

TP9

N18

TP10

AJ24

TP11

AK41

TP12

AK42

TP13

M32

TP14

N32

TP15

M30

TP16

N30

TP17

H12

TP18

AA23

TP19

AB45

NC_1

AB38

NC_2

AB42

NC_3

AB41

NC_4

T39

NC_5

P6

INIT3_3V#

C10

TP24

+3V ALW +3VS

CLK _PCIE _LAN #_R

CLK _PCIE _LAN _R

PC H_P ECI_ R

KB _RST#

H_T HERM TRIP#_L

T59 P AD

T60 P AD

T61 P AD

T62 P AD

T63 P AD

T64 P AD

T65 P AD

T66 P AD

T67 P AD

T68 P AD

T69 P AD

T70 P AD

T71 P AD

T72 P AD

T73 P AD

T74 P AD

T75 P AD

T76 P AD

T77 P AD

T78 P AD

T79 P AD

T80 P AD

T81 P AD

T82 P AD

T83 P AD

T84 P AD

NPC I_RST #

SAT A_CLK REQ#

PCH _XDP _GPIO49

WW AN_D ET#

ALS _EN#

RU NSC I_E C#

WEB CAM _ON

PCH _XDP _GPIO16

DO CK _ID0

DO CK _ID1

GPI O48

STP _PCI#

07 /02 u pd ate

1

0_04 02_5%
0_04 02_5%

12

12

R2 51
R2 52

1 2

1 2

0_02 01_5%

1 2

1 2

R2 55 54.9 _0402_1 %

56_0 402_5%

Title

Size D ocum ent N umber R ev

Cu sto m

LA -52 51P

Da te: She et o f

+3VS

R2 5310K_ 0201_5%

GATE A20 30

CLK _CPU_ BCLK # 4

CL K_CPU _BCL K 4

R2 54

H_ PEC I 4

+3VS

R2 6010K_ 0201_5%

KB_ RST# 30

H_ CPU PW RGD 4

H_T HERM TRIP# 4

12

R2 56

+V CCP

CLK _PCI_ KBC

1

C6 35
12P _0402 _50V8C@

2

CL K_PC I_FB

1

C6 58
12P _0402 _50V8C@

2

R2 68 10K_ 0201_5%

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

R2 72 10K_ 0201_5%

R2 75 10K_ 0201_5%

R2 79 100K _0201_5%

R2 81 10K_ 0201_5%

R2 85 10K_ 0201_5%

R2 87 10K _0402_5%@

R2 90 10K_ 0201_5%

R2 92 10K_ 0201_5%

R2 94 10K_ 0201_5%

R2 96 10K_ 0201_5%

R2 99 10K_ 0201_5%

R2 98 10K_ 0201_5%

Compal Electronics, Inc.

IBEX-M(4/6)-PCI/USB/RSVD

1

CLK _PCI_ 1394

1

2

CLK _PCI_T PM

1

2

+3VM _LAN

CLK _PCIE _LAN # 21

CLK _PCIE _LAN 21

C6 60
12P _0402_5 0V8C@

C6 59
12P _0402_5 0V8C@

07 /02 u pd ate

15 47T uesda y, J anuar y 05 , 201 0

0. 9

1

T123PA D

+1.05 VM

1U_0 402_6 .3V4Z

1

C2 45

A A

22U_ 0805_ 6.3V6M

B B

C C

+R TCVC C

D D

T111PA D

1 2

C2 72

1 2

C2 74

1 2

C2 78

1 2

C2 80

2

1 2

C2 47 0.1U _0402 _16V4Z

+1.05V M

1

C2 56

C2 55

2

22U_ 0805_6. 3V6M

C2 58

1 2

0.1U _0402 _16V4Z

+1.8V S

+V1 .05S_ VCC A_A_DPL

+V1 .05S_ VCC A_B_DPL

+1.0 5VS

1U_0 402_6 .3V4Z

C2 67

1

2

0.1U _0402 _16V4Z

+V1 .1A_I NT_V CCSUS

0.1U _0402 _16V4Z

+3V ALW

0.1U _0402 _16V4Z

+3VS

0.1U _0402 _16V4Z

+V CCP

C2 84

1

2

C2 90

1

2

C2 52

1

2

1U_0 402_6 .3V4Z

1

1

C2 57

2

2

+VC CRTCEXT

1U_0 402_6 .3V4Z

C2 68

C2 69

1

1

2

2

+VC CSST

0.

0. 2A @ 3. 3 V

2A @ 3. 3 V

0.0.

2A @ 3. 3 V2A @ 3. 3 V

0.

0. 4A @ 3. 3 V

4A @ 3. 3 V

0.0.

4A @ 3. 3 V4A @ 3. 3 V

0.

0. 1A @ 1. 1 V

1A @ 1. 1 V

0.0.

1A @ 1. 1 V1A @ 1. 1 V

4.7U _0603 _6.3V6K

0.1U _0402 _16V4Z

C2 85

1

2

2m A

2m A @3 . 3V

@3 . 3V

2m A2m A

@3 . 3V@3 . 3V

0.1U _0402 _16V4Z
C2 91

1

2

1U_0 402_6 .3V4Z

C2 86

0.1U _0402 _16V4Z

AP51

AP53

AD38

AD39

AD41

1U_0 402_6 .3V4Z

AU24

BB51
BB53

BD51
BD53

AH23

AH35

AH34

0.1U _0402 _16V4Z

1

AU18

2

U7 J

VCCACLK[1]

VCCACLK[2]

AF23

VCCLAN[1]

AF24

VCCLAN[2]

Y20

DCPSUSBYP

VCCME[1]

VCCME[2]

VCCME[3]

AF43

VCCME[4]

AF41

VCCME[5]

AF42

VCCME[6]

V39

VCCME[7]

V41

VCCME[8]

V42

VCCME[9]

Y39

VCCME[10]

Y41

VCCME[11]

Y42

VCCME[12]

V9

DCPRTC

0.035A

VCCVRM[3]

0.072A

VCCADPLLA[1]
VCCADPLLA[2]

0.073A

VCCADPLLB[1]
VCCADPLLB[2]

VCCIO[21]

AJ35

VCCIO[22]
VCCIO[23]

AF34

VCCIO[2]

VCCIO[3]

AF32

VCCIO[4]

V12

DCPSST

Y22

DCPSUS

P18

VCCSUS3_3[29]

U19

VCCSUS3_3[30]

U20

VCCSUS3_3[31]

U22

VCCSUS3_3[32]

V15

VCC3_3[5]

V16

VCC3_3[6]

Y16

VCC3_3[7]

AT18

V_CPU_IO[1]

>1mA

V_CPU_IO[2]

A12

VCCRTC

IBE XPEAK- M_FCBGA1 071

0.052A

0.344A

1.998A

3.208A

2mA

POWER

USB

Clock and Mi scella neous

PCI/GPIO/LPC

0.032A

SA TA

CPU

RTC PCI /GPIO/ LPC

0.163A

>1mA

>1mA

0.357A

6mA

HDA

VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]

VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]

VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCSUS3_3[21]
VCCSUS3_3[22]
VCCSUS3_3[23]
VCCSUS3_3[24]
VCCSUS3_3[25]
VCCSUS3_3[26]
VCCSUS3_3[27]

VCCSUS3_3[28]

VCCIO[56]

V5REF_SUS

V5REF

VCC3_3[8]

VCC3_3[9]

VCC3_3[10]

VCC3_3[11]

VCC3_3[12]

VCC3_3[13]

VCC3_3[14]

VCCSATAPLL[1]
VCCSATAPLL[2]

VCCIO[9]

VCCVRM[4]

VCCIO[10]

VCCIO[11]

VCCIO[12]

VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]

VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]

VCCME[13]
VCCME[14]
VCCME[15]
VCCME[16]

VCCSUSHDA

2

V24
V26
Y24
Y26

V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26

U23

V23

F24

K49

J38

L38

M36

N36

P36

U35

AD13

AK3
AK1

AH22

AT20

AH19

AD20

AF22

AD19
AF20
AF19
AH20

AB19
AB20
AB22
AD22

AA34
Y34
Y35
AA35

L30

+1.05 VS

IC H_V5 REF_ SUS

IC H_V 5RE F_RU N

+PC H_VCC 1_1_ 20
+PC H_VCC 1_1_ 21
+PC H_VCC 1_1_ 22
+PC H_VCC 1_1_ 23

1

C2 46
1U_0 402_6 .3V4Z

2

+3V ALW

0.1U _0402 _16V4Z

0.1U _0402 _16V4Z

C2 50

C2 51

1

1

2

2

+1.0 5VS

+3VS

1

C2 62

0.1U _0402 _16V4Z

2

+3VS

1 2

C2 70 0.1U _0402 _16V4Z

T126 PAD
T127 PAD

6/2 2

+1.8V S

1U_0 402_6 .3V4Z

C2 79

1

2

<BO M Stru cture>

R3 05 0_04 02_5%

1 2

R3 06 0_04 02_5%

1 2

R3 07 0_04 02_5%

1 2

R3 08 0_04 02_5%

1 2

1 2

R3 11 0_04 02_5%

1

C2 89

1U_0 402_6 .3V4Z

2

+1.0 5VS

+1.05V M

+3V ALW

3

Don't need extra-power

+1.8V S

+1.05 VS

+1.0 5VS

C2 40

1

2

+1.0 5VS

+1.0 5VS_AP LL

T124PA D

+1.0 5VS

C2 59

1

2

1U_0 402_6 .3V4Z

C2 63

C2 64

1

1

2

2

C2 710.1U_ 0402_ 16V4Z

1 2

R3 03 0_04 02_5%

1 2

+1.0 5VS_ VCCF DIPLL

T125PA D

+1.05 VS

Don't need extra-power

L10

1 2

10UH _LB2 012T1 00MR_20%_0 805

1U_0 402_6 .3V4Z

L11

1 2

10UH _LB2 012T1 00MR_20%_0 805

1U_0 402_6 .3V4Z

1U_0 603_1 0V4Z

C2 41

1U_0 402_6 .3V4Z

C2 60

1U_0 402_6 .3V4Z

C2 65

+3VS

C2 82

C2 88

AB24

10U_ 0805_ 6.3V6M

AB26
AB28

1

AD26
AD28

AF26

2

AF28
AF30

AF31
AH26
AH28
AH30
AH31

AJ30

AJ31

AK24

BJ24

AN20
AN22
AN23
AN24
AN26
AN28

BJ26

BJ28

AT26

AT28
AU26
AU28

1U_0 402_6 .3V4Z

AV26
AV28

1

AW26
AW28

BA26

2

BA28
BB26
BB28
BC26
BC28

10U_ 0603_6. 3V6M

BD26
BD28
BE26

1

BE28
BG26
BG28

2

BH27

AN30
AN31

AN35

AT22

BJ18

AM23

+V1 .05S_ VCC A_A_DPL

1

2

+V1 .05S_ VCC A_B_DPL

1

2

U7 G

VCCCORE[1]
VCCCORE[2]
VCCCORE[3]

1.524A

VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]

VCCIO[24]

0.042A

VCCAPLLEXP

VCCIO[25]
VCCIO[26]
VCCIO[27]
VCCIO[28]
VCCIO[29]
VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]
VCCIO[50]
VCCIO[51]
VCCIO[52]
VCCIO[53]

VCCIO[54]
VCCIO[55]

VCC3_3[1]

0.035A

VCCVRM[1]

6mA

VCCFDIPLL

VCCIO[1]

IBE XPEAK- M_FCBGA1 071

1

+

C2 81
220U _B2_ 2.5VM_R15M

2

1

+

C2 87
220U _B2_ 2.5VM_R15M

2

POWER

VCC CORE

DMI

PCI E*

NAND / SPI

FDI

4

0.069A

VSSA_DAC[1]

CRTLVDS

VSSA_DAC[2]

0.030A

VCCTX_LVDS[1]

0.059A

VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]

HVCMOS

0.061A

VCCPNAND[1]
VCCPNAND[2]
VCCPNAND[3]
VCCPNAND[4]

0.156A

VCCPNAND[5]
VCCPNAND[6]
VCCPNAND[7]
VCCPNAND[8]
VCCPNAND[9]

VCCME3_3[1]
VCCME3_3[2]

0.085A

VCCME3_3[3]
VCCME3_3[4]

020 2 C han ge va lue

VCCADAC[1]

VCCADAC[2]

VCCALVDS

VSSA_LVDS

VCC3_3[2]

VCC3_3[3]

VCC3_3[4]

VCCVRM[2]

VCCDMI[1]

VCCDMI[2]

AE50

AE52

AF53

AF51

AH38

AH39

AP43
AP45
AT46
AT45

AB34

AB35

AD35

AT24

AT16

AU16

AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15

AM8
AM9
AP11
AP9

100_ 0402_5%

0.01 U_060 3_16V7K

C2 42

C2 43

1

1

2

2

+3VS

1 2

C2 54 0.1U _0402 _16V4Z

+1.8V S

+VC CP

1 2

C2 61 1U_0 603_1 0V4Z

+V_ NVRA M_VCCQ

C2 66

1

2

+3VM

C2 75

1

2

12

R3 09

C2 92

1U_0 402_6 .3V4Z

1 2

10U_ 0805_6. 3V6M

10UH _LB2 012T1 00MR_20%_0 805

0.1U _0402 _16V4Z

C2 44

1

2

0.1U _0402 _16V4Z

0.1U _0402 _16V4Z

020 2 C han ge va lue

21

D2

CH75 1H-4 0PT_S OD323-2

IC H_V5 REF_ SUS

1

2

5

+3VS

L7

+5VS +3VS+3V ALW+5V ALW

21

12

R3 10

100_ 0402_5%

D3

CH75 1H-4 0PT_S OD323-2

IC H_V 5RE F_RU N

20 mi ls20 mi ls

1

C2 93
1U_0 603_6. 3V6M

2

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2010/12/31

Compal Secret Data

Deciphered Date

4

Title

Size D ocum ent N umber R ev

Cu sto m

Da te: She et o f

Compal Electronics, Inc.

IBEX-M(5/6)-PWR

LA -52 51P

5

16 47T uesda y, J anuar y 05 , 201 0

0. 9

1

2

3

4

5

U7 I

AY7

VSS[159]

B11

VSS[160]

B15

VSS[161]

B19

VSS[162]

B23

VSS[163]

B31

VSS[164]

B35

VSS[165]

B39

VSS[166]

B43

VSS[167]

B47

A A

B B

C C

D D

VSS[168]

B7

VSS[169]

BG12

VSS[170]

BB12

VSS[171]

BB16

VSS[172]

BB20

VSS[173]

BB24

VSS[174]

BB30

VSS[175]

BB34

VSS[176]

BB38

VSS[177]

BB42

VSS[178]

BB49

VSS[179]

BB5

VSS[180]

BC10

VSS[181]

BC14

VSS[182]

BC18

VSS[183]

BC2

VSS[184]

BC22

VSS[185]

BC32

VSS[186]

BC36

VSS[187]

BC40

VSS[188]

BC44

VSS[189]

BC52

VSS[190]

BH9

VSS[191]

BD48

VSS[192]

BD49

VSS[193]

BD5

VSS[194]

BE12

VSS[195]

BE16

VSS[196]

BE20

VSS[197]

BE24

VSS[198]

BE30

VSS[199]

BE34

VSS[200]

BE38

VSS[201]

BE42

VSS[202]

BE46

VSS[203]

BE48

VSS[204]

BE50

VSS[205]

BE6

VSS[206]

BE8

VSS[207]

BF3

VSS[208]

BF49

VSS[209]

BF51

VSS[210]

BG18

VSS[211]

BG24

VSS[212]

BG4

VSS[213]

BG50

VSS[214]

BH11

VSS[215]

BH15

VSS[216]

BH19

VSS[217]

BH23

VSS[218]

BH31

VSS[219]

BH35

VSS[220]

BH39

VSS[221]

BH43

VSS[222]

BH47

VSS[223]

BH7

VSS[224]

C12

VSS[225]

C50

VSS[226]

D51

VSS[227]

E12

VSS[228]

E16

VSS[229]

E20

VSS[230]

E24

VSS[231]

E30

VSS[232]

E34

VSS[233]

E38

VSS[234]

E42

VSS[235]

E46

VSS[236]

E48

VSS[237]

E6

VSS[238]

E8

VSS[239]

F49

VSS[240]

F5

VSS[241]

G10

VSS[242]

G14

VSS[243]

G18

VSS[244]

G2

VSS[245]

G22

VSS[246]

G32

VSS[247]

G36

VSS[248]

G40

VSS[249]

G44

VSS[250]

G52

VSS[251]

AF39

VSS[252]

H16

VSS[253]

H20

VSS[254]

H30

VSS[255]

H34

VSS[256]

H38

VSS[257]

H42

VSS[258]

IBE XPEAK- M_FCBGA1 071

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[326]
VSS[327]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[332]
VSS[333]
VSS[334]
VSS[335]
VSS[336]
VSS[337]
VSS[338]
VSS[339]
VSS[340]
VSS[341]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
VSS[353]
VSS[354]
VSS[355]
VSS[356]
VSS[366]

H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14

U7H

AB16

VSS[0]

AA19

VSS[1]

AA20

VSS[2]

AA22

VSS[3]

AM19

VSS[4]

AA24

VSS[5]

AA26

VSS[6]

AA28

VSS[7]

AA30

VSS[8]

AA31

VSS[9]

AA32

VSS[10]

AB11

VSS[11]

AB15

VSS[12]

AB23

VSS[13]

AB30

VSS[14]

AB31

VSS[15]

AB32

VSS[16]

AB39

VSS[17]

AB43

VSS[18]

AB47

VSS[19]

AB5

VSS[20]

AB8

VSS[21]

AC2

VSS[22]

AC52

VSS[23]

AD11

VSS[24]

AD12

VSS[25]

AD16

VSS[26]

AD23

VSS[27]

AD30

VSS[28]

AD31

VSS[29]

AD32

VSS[30]

AD34

VSS[31]

AU22

VSS[32]

AD42

VSS[33]

AD46

VSS[34]

AD49

VSS[35]

AD7

VSS[36]

AE2

VSS[37]

AE4

VSS[38]

AF12

VSS[39]

Y13

VSS[40]

AH49

VSS[41]

AU4

VSS[42]

AF35

VSS[43]

AP13

VSS[44]

AN34

VSS[45]

AF45

VSS[46]

AF46

VSS[47]

AF49

VSS[48]

AF5

VSS[49]

AF8

VSS[50]

AG2

VSS[51]

AG52

VSS[52]

AH11

VSS[53]

AH15

VSS[54]

AH16

VSS[55]

AH24

VSS[56]

AH32

VSS[57]

AV18

VSS[58]

AH43

VSS[59]

AH47

VSS[60]

AH7

VSS[61]

AJ19

VSS[62]

AJ2

VSS[63]

AJ20

VSS[64]

AJ22

VSS[65]

AJ23

VSS[66]

AJ26

VSS[67]

AJ28

VSS[68]

AJ32

VSS[69]

AJ34

VSS[70]

AT5

VSS[71]

AJ4

VSS[72]

AK12

VSS[73]

AM41

VSS[74]

AN19

VSS[75]

AK26

VSS[76]

AK22

VSS[77]

AK23

VSS[78]

AK28

VSS[79]

IBE XPEAK- M_FCBGA1 071

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47

+3VS

12

R3 12

100K _0201_5 %

PC H_NC TF615

PC H_NC TF715

PC H_NC TF191 5

PC H_NC TF261 5

R3 13

100K _0201_5 %

R3 14

100K _0201_5 %

R3 15

100K _0201_5 %

+3VS

+3VS

+3VS

2

12

5

12

2

12

5

61

Q10A
2N70 02DW -T/R7 _SOT363-6

CRA CK_B GA

3

Q10B
2N70 02DW -T/R7 _SOT363-6

4

CRA CK_B GA

61

Q11 A
2N70 02DW -T/R7 _SOT363- 6

CRA CK_B GA

3

Q11 B
2N70 02DW -T/R7 _SOT363- 6

4

CRA CK_B GA 8,3 0

BGA Ball Cracking Prevention and Detection

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2010/12/31

Compal Secret Data

Deciphered Date

4

Title

Size D ocum ent N umber R ev

Cu sto m

Da te: She et o f

Compal Electronics, Inc.

IBEX-M(6/6)-GND

LA -52 51P

5

17 47T uesda y, J anuar y 05 , 201 0

0. 9

1

2

3

4

5

CRT Connector

A A

F1

1.1A _6VD C_FU SE

1

2

12

R5 7

2.2K _0402 _5%

1

2

+3VS

C2 99

0.1U _0402 _16V4Z

CR T_D DC_CL K 14
CR T_DDC _DAT A 14

D_ DDC CLK 2 9
D_ DDCD ATA 2 9

+3VS

PRE P# 15, 21,29

Pla ce close to JCRT 1 f or EMI b ackup solu tion .

VGA _RED

V GA_G RN

VGA _BLUE

R3 22 150_ 0402_1%@

R3 23 150_ 0402_1%@

12

12

L

R3 16 0_04 02_5%

1 2

R3 17 0_04 02_5%

1 2

R3 18 0_04 02_5%

R3 24 150_ 0402_1%@

12

10P _0402_5 0V8J@

10P _0402_5 0V8J@

C2 96

C2 95

1

1

2

2

1 2

10P _0402_5 0V8J@

C2 97

1

2

11 /27 u pd ate

Pla ce R325,R 326,C3 00, C301 c lo ce to JP 30 (Docking Conn .)

L

HS Y NC D_ HS YN C

R3 25 0_06 03_5%

1 2

V SY NC

R3 26 0_06 03_5%

1 2

C3 00

5P_ 0402_50 V8C

1

2

D_ VSY NC

1

C3 01
5P_ 0402_50 V8C

2

75_0 402_1%

75_0 402_1%

C3 20

C3 21

1

1

2

2

11 /27 u pd ate

V GA_RE D_R

V GA_G RN_R

VGA _BLU E_R

75_0 402_1%

C3 15

1

2

D_ HS YNC 2 9

D_ VSY NC 29

PRE P#: DOCK --> L
PRE P#: UNDOC K --> H

RE D_R14

GR EEN _R14

BL UE_R1 4

DO CK_ RED2 9
DO CK_ GRN29

DO CK_B LU2 9

B B

C C

CR T_H SYN C1 4
CR T_V SYN C14

RE D_R
GR EE N_R
B LUE_R

DO CK _RED
DO CK _GRN
DO CK_ BLU

VGA _RED
V GA_G RN
VGA _BLUE

CR T_H SY NC
CR T_V SYN C

HS Y NC
V SY NC

U1 3

3
4
5

18
16
14

17
15
13

6
7

11
12

MAX48 85EETG+T_ TQFN24_4X4

ES D d esign insi de U13 alre ady

VCC

R0

MAX4885E

G0
B0

R1
G1
B1

R2
G2
B2

H0
V0

H1
V1

VL

SCL0

SDA0

SCL1

SDA1

SCL2

SDA2

EN

SEL

GND

EP

11 /06 u pd ate

CR T_D DC_C LK

CR T_DD C_DA TA

+5VS

C2 98

0.1U _0402 _16V4Z

8

9

CR T_D DC_C LK

2

CR T_DD C_DA TA

1

D_ DDC CLK

20

D_ DDC DATA

22

VG A_D DC_CL K

19

VGA _DDC _DATA

21

R3 19 10K_ 0402_5%

1 2

23

PRE P#

24

10
25

+3VS

12

R5 3

2.2K _0402 _5%

21

D4
CH 491D _SC59

2 1

C2 94

0.1U _0402 _16V4Z

VGA _DDC _DATA

VG A_D DC_CL K

1

2

+C RTVD D+R CRT_ VCC+5VS

W=40mi ls

JC RT1

6

11

1
7

12

2
8

13

3
9

14

16

G

4

17

G

10
15

5

SU YIN_ 07054 6FR01 5S23 3ZR

CO NN@

D D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2010/12/31

Compal Secret Data

Deciphered Date

4

Title

Size D ocum ent N umber R ev

Da te: She et o f

Compal Electronics, Inc.

CRT Connector

LA -5 251 P

5

18 47T uesda y, J anuar y 05 , 201 0

0. 9

5

08 /28 u pd ate

D D

DC A D

R3 46 0_02 01_5%

1 2

12

R3 48
1M_ 0402_5%

06 /18 u pd ate

0_06 03_5%

1 2

C C

+3VS

R3 49

4

+5V ALW +5VAL W

R3 42

10K _0201_5%

1 2

61

2N70 02DW H 2N SOT3 63-6

2

Q16 A

+3V S_DP_ F

NAN OSMD C050F 0.5 A 13. 2V P OLY- FUSE

2 1

F2

1 2

3

5

4

+3V S_DP

C3 08

0.1U _0402 _16V4Z

C3 09

1

2

R3 43

10K _0201_5%

D DC_ ENDP_E N

Q16 B
2N70 02DW H 2N SOT3 63-6

10U_ 0805_ 10V4Z

1

2

3

DPD _CTRL DATA14

DP D_CT RLCLK14

6/ 16 u pd ate

100K _0201_5 %@

DPD _AUX#14

DPD _AUX14

DPD _AUX#

DPD _AUX

100K _0201_5 %@

2N70 02DW H 2N SOT3 63-6

D DC_ EN

2N70 02DW H 2N SOT3 63-6

DP D_CT RLCL K DPD _C_A UX

D DC_ EN

+3VS

R3 38

1 2

R3 44

1 2

2

Q13A

61

2

Q14A

61

2

2

2N70 02DW H 2N SOT3 63-6

2N70 02DW H 2N SOT3 63-6

61

Q15A

5

3

4

Q15B

Q13B

2N70 02DW H 2N SOT3 63-6

3

4

5

Q14B

2N70 02DW H 2N SOT3 63-6

3

4

5

DP _EN

6 1

2N70 02DW -7-F_S OT363-6

DP _EN

3

2N70 02DW -7-F_S OT363-6

Q30A

Q30B

1

+3VS

6/ 16 u pd ate

R3 32
100K _0201_5%

1 2

DPD _C_AU X#DPD _CTRL DATA

R3 37
100K _0201_5 %

1 2

2

5

4

DPD_T XP01 4

DPD _TXN014
DPD_T XP11 4

DPD _TXN114
DPD_T XP21 4

DPD _TXN214
DPD_T XP31 4

DPD _TXN314

B B

R3 51

5.1M _0402_5%

A A

5

DPD_ TXP0

DPD _TXN0
DPD_ TXP1

DPD _TXN1
DPD_ TXP2

DPD _TXN2
DPD_ TXP3

DPD _TXN3
DC A D

DPD _C_A UX

12

DPD _C_AU X#

DP D_H PD_ R

+3V S_DP

4

JD P1

1

LAN0+

2

LAN0_shield

3

LAN0-

4

LAN1+

5

LAN1_shield

6

LAN1-

7

LAN2+

8

LAN2_shield

9

LAN2-

10

LAN3+

11

LAN3_shield

12

LAN3-

13

CA_DET

14

GND

15

AUX_CH+

16

GND

17

AUX_CH-

18

HP_DET

19

RTN

20

DP_PWR

MOLEX _105088-0001

CO NN@

GND
GND
GND
GND

24
23
22
21

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

R1 076

100K _0402_5 %

2008/09/15 2010/12/31

1 2

Compal Secret Data

+5VS

5

3

4

2N70 02DW H 2N SOT3 63-6

Q46B

12

R1 055

@

0_04 02_5%

Deciphered Date

2

DP D_H PDDP D_H PD_ R

DP D_H PD 14

Title

Size D ocum ent N umber R ev

Da te: She et o f

Compal Electronics, Inc.

Display Port Connector

LA -5 251 P

1

19 47T uesda y, J anuar y 05 , 201 0

0. 9

DDI PANEL CONN.

1

2

3

4

5

Web camera POWER CIRCUIT

A A

1

C3 11

2

ALS _EN#15

INV _PWM14

WEB CAM _ON15

12

WCM -2012-9 00T_4P

4

1

L18

@

12

D1 2

2

CH1

1

VN

CM1 213-02S R_SOT143- 4@

+L CDV DD

3

3

2

2

CH2

VP

1

2

C3 12

680P _0402_50V 7K

INV _PWM
WEB CAM _ON WEBCA M_ON _R

+5V _WEBCAM

12

1

2

3

4

+5VS

0_08 05_5%

R3 74 0_04 02_5%

R3 75

+5V_K L

INV _PWM

R3 72

22_0 402_5%

11 /11 u pd ate

C6 65

220P _0402_25V

R3 76

0_04 02_5%

09 /28 u pd ate

B+ IN VPWR _B+

220K _0402_5%@

100K _0402_1%@

1 2

R1 105

R1 106

+3VS IN VPWR _B++L CDV DD

12

12

DI SP_O FF#

USB 20_P 12_R
USB 20_N1 2_R

MB_ DP_AUX N
MB_ DP_AUXP

12

12

C9 75

0.22 U_060 3_25V7K@

07 /03 u pd ate

JE DP1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

+3VS

R5 69

100K _0402_5 %

1 2

R6 13

100K _0402_5 %

1 2

06 /16 u pd ate

Q78
SI2 301CD S-T1-GE 3 1P SOT 23-3@

12

47P _0402_50 V8J@

1

MB_ DP_AUXP

3

MB_ DP_AUX N

5
7

9
11
13
15
17
19
21
23
25
27

MB_ HPD

29

3132

ACE S_88 242-3001_30PC ONN @

2

WEB CAM _ON_R

D

S

13

G

2

C9 76

1U_0 603_25V 7K@

+3VS

12

C3 10

680P _0402_50V 7K

B B

C C

D D

USB 20_P1215

USB 20_N1 21 5

47P _0402_5 0V8J@

R3 58 0 _0402_5 %

4

1

R3 59 0 _0402_5 %

USB 20_N1 2_R USB 20_P 12_R

IN VPWR _B+

1

C3 13

2

1 2

R3 65 0_04 02_5%

61

Q18A
2N70 02DW -T/R7 _SOT363-6

R6 16

100K _0402_5 %

1 2

12

HCB 2012K F-121T 50_0805

1 2

1

C3 14

680P _0402_50V 7K

2

MB_DP _AUXP 5
MB_ DP_AUXN 5

MB_ DP_DATA 0_P 5
MB_ DP_DA TA0_N 5

L17

MB_ DP_H PD 5

B+

Keyboar d Light circuit

+3VS

12

R3 56

10K _0402_5%@

DI SP_O FF#

1

C3 26

680P _0402_5 0V7K

2

Q23

SI2 301CD S-T1-GE 3 1P SOT 23-3

D

1 3

2

R3 62

1 2

2K_ 0402_5%

ENA BLT

LCD POWER CIRCUIT

EN AVD D14

12

100K _0402_1 %

10K _0402_5%

3

Q56B

Q18B

R3 77

LI D_SW #

5

G

S

12

R3 57

100K _0402_1 %

2N70 02DW -T/R7 _SOT363- 6

+5VS+5V_K L +5VS

R1 49

2N70 02DW H 2N SOT3 63-6

ENAB LT 14

+5VS

+L CDV DD

12

R3 69
100_ 0201_1%

3

5

4

2

IN

12

+3V ALW

2

6 1

2N70 02DW H 2N SOT3 63-6

Q56A

4

Clo se to JED P1.24

L

R3 04 0_06 03_5%

1 2

06 /16 u pd ate

47K _0402_5%

R3 71

1 2

1

0.1U _0402 _16V4Z

OUT

Q20

DTC 124EK AT146_SC 59-3

GND

3

R3 66

1 2

DI SP_O FF# LI D_SW #

1

C3 23

2

Pla ce R366 c lo se to Q5 6.

L

12

R3 61

0_04 02_5%@

100K _0402_5 %

D5 7

2 1

CH75 1H-4 0PT_S OD323-2

47P _0402_5 0V8J

C3 16

C3 17

1

@

2

D

1 3

G

2

R3 70 1M_0 402_5%

1

C3 24

4.7U _0805 _10V4Z

2

LID_ SW#_ ISO# 1 3

08 /25 u pd ate

+5V _WEBCAM

0.1U _0402 _16V4Z

C3 18

1

2

1 2

4.7U _0805 _10V4Z

C3 19

1

2

4.7U _0805 _10V4Z
C3 25

@

0.01 U_040 2_16V7K

1

2

Q19

S

SI2 301CD S-T1-GE 3 1P SOT 23-3

1 2

C3 22 0.1U _0402 _16V4Z

LI D_SW # 28,3 0

+3VS+L CDV DD

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2010/12/31

Compal Secret Data

Deciphered Date

4

Title

Size D ocum ent N umber Re v

Da te: She et o f

Compal Electronics, Inc.

LCD CONN & Q-Switch & GPIO Ext.

LA -52 51P

5

20 47T uesd ay, J anua ry 05 , 20 10

0. 9

1

2

3

4

5

+3VM

R3 82
0_06 03_5%

1 2

0.1U _0402 _16V4Z

A A

C3 27

1

C3 28

2

10U_ 0805_ 10V4Z

+3VM _LAN

1

2

0.1U _0402 _16V4Z

07 /01 u pd ate

CLK _PCIE _LAN _REQ1 #13

CLK _PCIE _LAN _REQ#15

PLT_R ST#4,12 ,15, 22,23, 31

CLK _PCIE _LAN15
CLK _PCIE _LAN #15

PCIE _PRX_DTX _P613
PCI E_PRX_D TX_N613

PCI E_PTX _C_DRX_P613
PCI E_PT X_C_DRX_N 613

SML 0CLK13
SML0D ATA13

Y4

1 2

LA N_DIS #15

LA NLIN K_R#1 5,30

10P _0402_5 0V8J

2

1

B B

XTAL1_C

25MHZ_20PF_7A25000012

2

C3 41

33P _0402_50 V8J

1

C C

04/ 25 Del ete T RM_ CT, R407, R40 8. lea ve U14 -6 NC.
Add 1uF C339 d ecoup li ng cap t o TRM _CTR.

D D

@

@

C4 11

XTAL1

12

XTAL2

C3 42

33P _0402_50 V8J

10 /01 u pd ate

R4 07 0_04 02_5%

1 2

R3 88 0_02 01_5%
R3 89

C3 36
C3 37

R3 90
R3 91

R3 94
0_02 01_5%

R2 61

10K _0201_5%

R3 98
R4 00

10K _0201_5%

1 2
1 2

0_02 01_5%

0.1U _0402 _16V7K

1 2
1 2

0.1U _0402 _16V7K

1 2
1 2

1 2

1 2

0_02 01_5%

@

1 2
1 2

1 2

R4 03 1K_ 0201_5%

1 2

R4 04 3.01 K_040 2_1%

1 2

C3 46 0.1 U_040 2_16V7K

1 2

C3 49 0.1 U_040 2_16V7K

1 2

C3 52 0.1 U_040 2_16V7K

1 2

C3 54 0.1 U_040 2_16V7K

1

C3 39

1U_0 603_1 0V4Z

2

@

PLT _RST#_L AN

PCI E_PRX _C_DTX_P6
PCI E_PR X_C_DTX_ N6

0_02 01_5%

0_02 01_5%

LAN LINK _STATUS #

XTAL1
XTAL2

LAN _SM_C LK
LAN _SM_DAT

LA N_P HYP C_R

LAN _ACT#

T85PA D
T86PA D

LAN_ JTAG_TMS
LAN _JTAG _TCK

LA N_MD I0N

LAN _MDI0 P

TRM _CTR

LA N_MD I1N

LAN _MDI1 P

TRM _CTR

LA N_MD I2N

LAN _MDI2 P

TRM _CTR

LA N_MD I3N

LAN _MDI3 P

TRM _CTR

+1.0 VM_LAN

1

C3 34

2

04 /2 0 Canc el +1 .0 VM_ LAN from +3 VM reserv e
cir cui t for L AN Lay out P laceme nt is sue i mpr ov e.
05/ 06 In sta ll C4 1(3 30U _2V _B2 _15 mR) b y HP requ est.

U1 4

48

CLK_REQ_N

36

PE_RST_N

44

PE_CLKP

45

PE_CLKN

38

PETp

39

PETn

41

PERp

42

PERn

28

SMB_CLK

31

SMB_DATA

3

LAN_DISABLE_N

26

LED0

27

LED1

25

LED2

32

JTAG_TDI

34

JTAG_TDO

33

JTAG_TMS

35

JTAG_TCK

9

XTAL_OUT

10

XTAL_IN

30

TEST_EN

12

RBIAS

WG8 2577L M QL MG A3 QFN 48P

TAI MAG I H-037-2

12

TD4-

11

TD4+

10

TCT4

9

TD3-

8

TD3+

7

TCT3

6

TD2-

5

TD2+

4

TCT2

3

TD1-

2

TD1+

1

TCT1

1

C3 35

2

10U_ 0805_6. 3V6M

1

C4 1

+

330U _B2_2V M_R15M

2

MDI

PCIE

RSVD_VCC3P3_1
RSVD_VCC3P3_2

SMBUS

JTAG LED

1:1

1:1

1:1

1:1

1

R3 85
0_06 03_5%

1 2

MDI_PLUS0

MDI_MINUS0

MDI_PLUS1

MDI_MINUS1

MDI_PLUS2

MDI_MINUS2

MDI_PLUS3

MDI_MINUS3

VDD3P3_IN

VDD3P3_OUT

VDD3P3_15
VDD3P3_19
VDD3P3_29

VDD1P0_47
VDD1P0_46
VDD1P0_37

VDD1P0_43

VDD1P0_11

VDD1P0_40
VDD1P0_22
VDD1P0_16

VDD1P0_8

CTRL_1P0

VSS_EPAD

T47

2

+1.0 5VM_LA N

LAN _MDI0 P

13

LA N_MD I0N

14

LAN _MDI1 P

17

LA N_MD I1N

18

LAN _MDI2 P

20

LA N_MD I2N

21

LAN _MDI3 P

23

LA N_MD I3N

24

6

VCT

R3 92 3.01 K_040 2_1%

1

1 2

R3 93 3.01 K_040 2_1%

2

1 2

5

+3.3 VM_LA N_OUT

4

+3.3 VM_L AN_OUT_ R

15
19
29

47
46
37

+1.0 VM_LAN 3

43

+1.0 VM_LAN 2

11

40
22
16
8

LAN _CTRL _10

7

49

13

MX4-

14

MX4+

15

MCT4

16

MX3-

17

MX3+

18

MCT3

19

MX2-

20

MX2+

21

MCT2

22

MX1-

23

MX1+

24

MCT1

MDO 0-

MDO 0+

MCT0

MDO 1-

MDO 1+

MCT1

0.01 U_040 2_50V7K

MDO 2-

MDO 2+

MCT2

0.01 U_040 2_50V7K

MDO 3-

MDO 3+

MCT3

0.01 U_040 2_50V7K

1 2

R3 95 0_06 03_5%

1 2

R3 96 0_06 03_5%

1 2

R3 99 0_06 03_5%

1 2

R4 01 0_06 03_5%

1 2

R4 02 0_06 03_5%

0.01 U_040 2_50V7K

+3VM _LAN

1

C3 38

1U_0 603_1 0V4Z

2

+1.0 VM_LAN+3VM _LAN

T115 P AD

04/ 20 Te st Po int reserve .

MDO 0- 29

1 2

1 2

1 2

1 2

R4 09
75_0 402_1%

1 2

R4 12
75_0 402_1%

1 2

R4 13
75_0 402_1%

1 2

R4 14

75_0 402_1%

1 2

1000 P_1808_3K V7K

MDO 0+ 29

C3 47

MDO 1- 29

MDO 1+ 29

C3 50

MDO 2- 29

MDO 2+ 29

C3 53

MDO 3- 29

MDO 3+ 29

C3 55

C3 48

LA N_DI S#

2

R2 62

1 2

0_02 01_5%

+3VM _LAN +3V M_LAN_L ED

12

R3 97
100K _0402_5 %

PRE P#15, 18,29

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

6 1

2N70 02DW T/R7 _SOT-363 -6

S

Q2 2

G

SI2 301CD S-T1-G E3 1P SO T23-3

2

3

2N70 02DW T/R7 _SOT-36 3-6

5

4

LAN LINK _STATUS #LA NLIN K_R#

Q9A

D

13

Q9B

+3VM _LAN

R4 05

LAN _ACT#

R4 10
10K _0402_5%

LAN LINK _STATUS #

Deciphered Date

12

+3V M_LAN_L ED

R4 06 300_ 0603_5%

2

1

+3VM _LAN

1 2

C3 45

@

680P _0402_5 0V7K

12

+3V M_LAN_L ED

R4 11 300_ 0603_5%

1 2

2

C3 51

@

680P _0402_50V 7K

1

4

10K _0402_5%

LAN _ACT#29

LAN LINK_ STATUS #29

2008/09/15 2010/12/31

Compal Secret Data

11 /03 u pd ate
M/ E Des ign c hange
DC2 340 03O0 0(TYCO_200 6067-1 _13P) to
DC0 209 102 01( FOX _JM361 11-R222 5-7H_1 3P-T)

JR J45

11

Yellow LED+

12

Yellow LED-

MDO 3-

MDO 3+

MDO 1-

MDO 2-

MDO 2+

MDO 1+

MDO 0-

MDO 0+

8

7

6

5

4

3

2

1

9

10

DETECT PIN1

PR4-

PR4+

PR2-

PR3-

PR3+

PR2+

PR1-

PR1+

Green LED+

Green LED-

FOX _JM3 6111-R222 5-7H

CO NN@

Size D ocum ent Numbe r Re v

Da te: She et o f

3

Title

SHLD1
SHLD1

2

D1 3
PJS OT05C_SO T23-3

@

1

Compal Electronics, Inc.

LA -52 51P

13

14
15

Intel 82566 Nineveh

5

21 47T uesda y, J anuar y 05 , 201 0

0. 9

1

+1.5V S+3V_ WLAN

0.1U _0402 _16V4Z

0.01 U_040 2_16V7K

C3 56

A A

1

2

07 /01 u pd ate

10K _0201_5%@

MC2 _DISA BLE30

B B

XMI T_D_OFF #

4.7U _0805 _10V4Z

C3 57

C3 58

1

1

2

2

+3V ALW

12

R4 22

2 1

D1 4 C H751H -40P T_SOD32 3-2

C3 59

1

2

R4 25

1 2

220K _0402_1%

0.01 U_040 2_16V7K

C3 62

0.1U _0402 _16V4Z

C3 60

1

2

0.1U _0402 _10V6K@

1

2

2

4.7U _0805 _10V4Z

C3 61

1

2

Q24

31

SI2 305DS-T1 -E3_SOT23 -3

1 2

R1 19 0_06 03_5%

WLA N_TRA NSM IT_OFF# 15

+3V _WLAN

39P _0402_5 0V8J

1

C6 29

C4 43

@

2

39P _0402_5 0V8J

+3V _WLAN

1

@

2

2

PCI E_WA KE#14,23

CL KREQ _WLA N#1 3

CLK _PCIE _MCA RD#13
CLK _PCIE _MCA RD13

10 /19 u pd ateLClo se to C 443

CL K_PCI _DB15, 31

PCI E_PRX_D TX_N41 3
PCIE _PRX_DTX _P41 3

PCI E_PT X_C_DRX_N 41 3
PCI E_PTX _C_DRX_P413

CL _CLK113
CL_D ATA113
CL_R ST1#1 3

CL _CLK 1
CL_D ATA1
CL_R ST#1

PCI E_WA KE#

CLK _PCIE _MCA RD#
CLK _PCIE _MCA RD

R4 77

1 2

0_04 02_5%

R4 23 0_02 01_5%

1 2

R4 24 0_02 01_5%

1 2

R4 26 0_02 01_5%
R4 27 0_02 01_5%
R4 28 0_02 01_5%

12P _0402_50 V8J

@

C5 39

12
12
12

CL K_PC I_DE BUG

1

2

3

R4 53 0_0 402_5%

PC I_S ERR# _R
WW _LE D# SIR Q

8051TX_ R
DEB UG_K BCRS T_R

DEG _FRA ME#
DE BUG_ AD3
DE BUG_ AD2
DE BUG_ AD1
DE BUG_ AD0

PCI _RST #_R

8051 _REC OVER #_R
DEB UG_K BCRS T_R

PCI _RST #_R

CL K_PC I_DE BUG

PCI E_PR X_DTX_N4 _R
PCI E_PRX _DTX_P4_R

+3V _WLAN

CL _CLK 1-R
CL_D ATA 1-R
CL_R ST1 #-R

B+_ DEBU G_R

1 2

R4 33 0_0 201_5%@

1 2

R4 37 0_0 201_5%@

1 2

R4 32 0_0 201_5%@

1 2

R4 21 0_0 201_5%@

1 2

R4 31 0_0 201_5%@

1 2

R4 41 0_0 201_5%@

1 2

R4 15 0_0 201_5%

1 2

R4 16 0_0 201_5%

1 2

R4 17 0_0 201_5%

1 2

R4 18 0_0 201_5%

1 2

R4 19 0_0 201_5%

1 2

R4 20 0_0 201_5%

1 2

R4 75 0_0 201_5%

1 2

JP6

1

1

3

3

5

5

7

7
9910
111112
131314
151516

171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152

G153G254G355G3

2

2

4

4

6

6

8

8

10
12
14
16

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

56

FOX _AS0B 226-S99N- 7F

CO NN@

PC I_S ERR#

8051RX8051 RX_R
8051TX
DEB UG_K BCRST
8051 _REC OVER#8051 _REC OVER #_R

LPC _LAD3
LPC _LAD2
LPC _LAD1
LPC _LAD0

WL _LED #WW _LE D#

DEG _FRA ME#
DE BUG_ AD3
DE BUG_ AD2
DE BUG_ AD1
DE BUG_ AD0

XMI T_D_OFF #

8051TX_ R
8051 RX_R

10 /13 u pd ate

WW _LE D#
WL _LED #
PC I_S ERR# _R

4

B+_ DEBUGB+_ DEBU G_R
PC I_SE RR# 15, 25,3 0,31
SI RQ 12, 25,30 ,31
8051RX 30,31
8051TX 30 ,31
DEB UG_K BCRST 31,36
8051 _REC OVER# 30,31

LPC _LFRA ME# 12, 30,31
LPC _LAD3 1 2,30, 31
LPC _LAD2 1 2,30, 31
LPC _LAD1 1 2,30, 31
LPC _LAD0 1 2,30, 31

PCI _RST# 15,25

PLT_R ST# 4,12 ,15, 21,23, 31

WL _LED# 28

5

07 /01 u pd ate

+3V _WLAN

+1.5V S

06/ 25 Del JHDD1 and JHDD2 Cab le de sig n. Ad d JHD D3 B to B dir ect ly connect d esign .

C C

D D

JH DD 3

17

GND

18

GND

19

GND

1

GND

A+

A-

GND

B-

B+

GND

V33

V33
GND
GND

V5
V5

R
Rsv1
Rsv2

FOX _LM25163- BA01-9HCON N@

1

SATA_ PTX_C_DRX _P0 SATA_ PTX_DRX_P0

2

SA TA_PTX_C _DRX_N0

3
4

SA TA_PRX_C _DTX_N0 S ATA_PRX_ DTX_N0

5

SATA_ PRX_C_DTX _P0 SATA_ PRX_DTX_P0

6
7

8
9
10
11
12
13
14
15
16

+3VS

+3VS

1

C3 72

2

10U_ 0805_ 10V4Z

1 2
1 2

1 2
1 2

0.1U _0402 _16V4Z

1

C3 73

2

C3 74

0.1U _0402 _16V4Z

C3 650.0 1U_04 02_16V7K

SATA_ PTX_DRX_ N0

C3 670.0 1U_04 02_16V7K

C3 690.0 1U_04 02_16V7K
C3 700.0 1U_04 02_16V7K

0.1U _0402 _16V4Z

1

C3 75

2

SATA_ PTX_DRX_P0 1 2
SATA_ PTX_DRX_ N0 12

SATA_ PRX_DTX_ N0 12
SATA_ PRX_DTX_P0 1 2

1

2

2

7/1 Up date JOD D1 PCB Foot print f rom AL LTO_C 185 22- 113 03-L_1 3P_NR to T YCO_20 23233-3 _13P_N R

JO DD1

TYC O_202 3233- 3_NRC ONN @

1

GND

A+

A-

GND

B-

B+

GND

DP
V5
V5

MD
GND
GND

3

SATA_ PTX_C_DRX _P1

2

SA TA_PTX_C _DRX_N1

3
4

SA TA_PRX_C _DTX_N1

5

SATA_ PRX_C_DTX _P1

6
7

Issued Date

R4 29 0_02 01_5%@

1 2

+5VS

2008/09/15 2010/12/31

8
9
10
11
12
13

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2
1 2

1 2
1 2

Compal Secret Data

C3 630.0 1U_04 02_16V7K
C3 640.0 1U_04 02_16V7K

C3 660.0 1U_04 02_16V7K
C3 680.0 1U_04 02_16V7K

1

C3 71

@

0.1U _0402 _16V4Z

2

Deciphered Date

SATA_ PTX_DRX_P1
SATA_ PTX_DRX_ N1

SATA_ PRX_DTX_ N1
SATA_ PRX_DTX_P1

ODD _DET# 15

4

SATA_ PTX_DRX_P1 1 2
SATA_ PTX_DRX_ N1 12

SATA_ PRX_DTX_ N1 12
SATA_ PRX_DTX_P1 1 2

+5VS

0.1U _0402 _16V4Z
1U_0 603_1 0V4Z

C3 76

1

1

2

2

Title

Size D ocum ent N umber Re v

Da te: She et o f

Compal Electronics, Inc.

WLAN/ODD/HDD

10U_ 0805_ 10V4Z

C3 77

1

2

LA -52 51P

10U_ 0805_ 10V4Z

C3 79

C3 78

1

2

5

22 47T uesd ay, J anua ry 05 , 20 10

0. 9

1

JP 8

1

1

3

3

5

5

7

7
9910
111112
131314

NV _CLE1 5

NV_ ALE15

151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152

GND153GND2

MOLEX _67910-5700

CO NN@

+3VS

100U _B2_ 6.3VM_R45M@

NV _DQ015
NV _DQ115
NV _DQ215
NV _DQ315
NV _DQ415
NV _DQ515
NV _DQ615
NV _DQ715
NV _DQ815

NV _DQ915
NV _DQ1015
NV _DQ1115
NV _DQ1215
NV _DQ1315
NV _DQ1415
NV _DQ1515

NAN D_DET ECT#

1

T88PA D

+3 V_WW AN

39P _0402_5 0V8J@

C3 91

1

2

T89PA D

T90PA D

+3V _WWA N

1

C3 92

2

NV _RE# _WR#115
NV _RE# _WR#015

NAN D_DET ECT#12

39P _0402_5 0V8J@

A A

B B

C C

D D

2

2

4

4

6

6

8

8

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

0.01 U_040 2_16V7K

1

C3 88

C3 89

2

0.1U _0402 _16V4Z

R5 67 0_06 03_5%@

1 2

1

C5 71

2

NV _CLE

NV_ ALE

+

45
46
12
13
51
52
28
29
67
68
34
35
73
74

18
57
19
58

60
21

11
14
17
20
23
26
27
30
33
36

+3 V_WW AN

1

2

JP1 1

6

DQ0

7

DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

CLE_0
CLE_1
ALE_0
ALE_1

W/R_1#/RE_1#
W/R_0#/RE_0#

5

VSS_1

8

VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12

UI M_P WR
UIM _DATA
UIM _CLK
UIM _RST
UIM _VPP

M_W XMIT_OF F#

WW AN_D ET#

WW _LE D#

1

C3 90

4.7U _0805 _10V4Z

2

VCC_11VCC_22VCC_33VCC_440VCC_541VCC_6

+3 V_WW AN

+V_ NVRA M_VCCQ+3V _NVRAM

42

CK_0/WE_0#

CK_1/WE_1#

NVR AM C onnec tor@

WW AN_D ET# 15

USB 20_N9 15
USB 20_P9 1 5

WW _LE D# 28

78

VCCQ_138VCCQ_239VCCQ_3

DOS_0#

DOS_0

DOS_1#

DOS_1

RFU_1
RFU_2
RFU_3
RFU_4

CE_0#
CE_2#
CE_1#
CE_3#
CE_4#
CE_6#
CE_5#
CE_7#

CK_0#

CK_1#

R/B#
WP#

VREF

VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24

9
10
31
32

15
16
63
64

24
25
22
61
4
43
37
76

48
49
70
71

54
55

77

44
47
50
53
56
59
62
65
66
69
72
75

R5 61 0_06 03_5%@

R5 62 0_06 03_5%

Ne ed Keep

1

C5 66

22U_ 0805_6. 3VAM@

2

2

WWA N_TR ANSM IT_O FF#15,2 8

+3V ALW

09 /11 u pd ate

MC1 _DISA BLE30

UIM _DATA UIM _CLK

12

R4 34

47K _0402_5%@

UI M_P WR

1 2

1 2

R1 077

10K _0402_5%@

S D IO(B R) N UP4301 MR6T1 TS OP-6

JP1 0

4

GND

5

VPP

6

I/O

7

DET

SAN TA_13530 6-3 CON N@

+3VS

+1.8V S

1

2

Pla ce C933 b etween R1077 .1 an d R10 79. 2 f or li mit i nru sh cu rrent.07 /02 u pd ate

L

12

R1 079 220 K_0402_ 1%

U1 5

CH1

Vn

CH23CH3

C9 33

1000 P_0402_ 50V7K

1 2

SI2 305DS-T1 -E3_SOT23 -3

@

6

CH4

5

Vp

4

VCC
RST
CLK

GND
GND

08 /28 u pd ate

TP_ NV_DO S_0#

TP_ NV_DO S_1#

TP_ NV_RF U_1
TP_ NV_RF U_2
TP_ NV_RF U_3
TP_ NV_RF U_4

NV _CE0 #

NV _CE1 #

NV _CE2 #

NV _CE3 #

TP_ NV_CK _0#

TP_ NV_CK _1#

TP_ NV_WP 0#

TP_ NV_V REF

T91 P AD

NV_ DQS0 1 5

T92 P AD

NV_ DQS1 1 5

T93 P AD
T94 P AD
T95 P AD
T96 P AD

NV_ CE0# 1 5

NV_ CE1# 1 5

NV_ CE2# 1 5

NV_ CE3# 1 5

T97 P AD

NV_ WE#_ CK0 15

T98 P AD

NV_ WE#_ CK1 15

NV _RB# 15

T99 P AD

T100 PA D

2

CH75 1H-4 0PT_S OD323-2

1

2

2

Q77

1
2
3

C3 85

18P _0402_50 V8J

1

@

2

8
9

UI M_P WR
UIM _RSTUIM _VPP

C3 86

1

2

D1 6

31

4.7U _0805 _10V4Z

3

M_W XMIT_OF F#

21

J3
PAD -OPE N 4x 4m

1 2

0_08 05_5%

+3 V_WW AN

DAN 217T1 46_SC59- 3

1

D1 5

@

0.1U _0402 _16V4Z

C3 87

1

2

3

4

R4 35 0_02 01_5%

USB 20_N415
USB 20_P415

+3 V_WW AN

R1 080

12

+3 V_WW AN

3

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/09/15 2010/12/31

PCI E_WA KE#14,22

CLK REQ_EXP #13

CLK _PCIE_E XP#13
CLK _PCIE_E XP13

PCI E_PRX_D TX_N213
PCIE _PRX_DTX _P213

PCI E_PT X_C_DRX_N 213
PCI E_PTX _C_DRX_P213

C3 94 0.1U _0402 _16V4Z

C3 99 0.1U _0402 _16V4Z

C4 00 0.1U _0402 _16V4Z

+3V ALW

+3V ALW

Compal Secret Data

NC _CP #

PCI E_WA KE#

PE RST#

CLK REQ_EXP #

CPP E#
CLK _PCIE _EXP#
CLK _PCIE_E XP

PCI E_PRX_ DTX_N2
PCI E_PRX_DT X_P2

PCI E_PT X_C_DRX_ N2
PCI E_PTX _C_DRX_P2

12

12

12

PLT_R ST#4 ,12,1 5,21, 22,31

R4 40 100K _0201_5%

CPP E#15

+1.5V S

+3VS

12

SLP _S3#14,29 ,30,3 2,33 ,35,37 ,38

Deciphered Date

4

1 2

R4 36 0_02 01_5%

1 2

R4 39
0_02 01_5%

1 2

+3V _PEC

+3V S_PEC

C4 03 0.1U _0402 _16V7K

1 2

C4 04 0.1U _0402 _16V7K

1 2

U1 7

12

1.5Vin

14

NC

2

3.3Vin

4

NC

PLT_ RST#

CPP E#

NC _CP #

AUX_IN17AUX_OUT

6

SYSRST#

20

SHDN#

1

STBY#

10

CPPE#

9

CPUSB#

18

RCLKEN

TPS 2231M RGP R-2 QFN 20P

+1.5 VS_PE C
+1.5 VS_PE C

5

JEXP1

1

US B20_ N4_R
USB 20_P 4_R

PCI E_WA KE# _R

PCI E_PR X_DTX_N2 _R
PCI E_PRX _DTX_P2_R

11

1.5Vout

3.3Vout

PERST#

NC

NC

OC#

NC

GND

GND

+1.5 VS_PE C

13

3

+3V S_PEC

5

15

+3V _PEC

19

PE RST#

8

16

7

21

Title

Size D ocum ent N umber R ev

Da te: She et o f

Compal Electronics, Inc.

WWAN/NAND

LA -52 51P

GND

2

USB_D-

3

USB_D+

4

CPUSB#

5

RSV

6

RSV

7

SMB_CLK

8

SMB_DATA

9

+1.5V

10

+1.5V

11

WAKE#

12

+3.3VAUX

13

PERST#

14

+3.3V

15

+3.3V

16

CLKREQ#

17

CPPE#

18

REFCLK-

19

REFCLK+

20

GND

21

PERn0

22

PERp0

23

GND

24

PETn0

25

PETp0

26

GND

27

GND

28

GND

SAN TA_13 0853-1_RT

CO NN@

+3V S_PEC

0.1U _0402 _16V7K

C3 95

1

2

+1.5 VS_PE C

0.1U _0402 _16V7K

C4 01

1

2

5

GND
GND

+3V _PEC

4.7U _0805 _10V4Z

C3 96

1

2

4.7U _0805 _10V4Z

C4 02

1

2

29
30

4.7U _0805 _10V4Z

0.1U _0402 _16V7K
C3 98

C3 97

1

1

2

2

23 47T uesda y, J anuar y 05 , 201 0

0. 9

1

2

3

4

5

Rear side USB conn.

+5V ALW

(2A,10 0mils ,Via N O.=4)

1

C4 05

A A

4.7U _0805 _10V4Z

USB 20_L_ N0

2

SLP _S4#1 4,29, 33,39

D1 9

2

1

CM1 213-02S R_SOT143- 4@

3

CH1

CH2

4

VN

VP

07 /17 u pd ate

U1 8

1

GND

2

IN

3

IN

4

EN#

G54 7F1P8 1U MSO P 8P

+5V ALW

USB 20_L_P 0

8

OUT

7

OUT

6

OUT

5

OC#

R4 42

1 2

10K _0201_5%

220U _6.3V_M

1

+

C4 06

C4 07

2

0.1U _0402 _16V4Z

10 /13 u pd ate

D1 8

2

CH1

1

VN

CM1 213-02S R_SOT143- 4@

1000 P_0402_ 50V7K

1

C4 08

2

3

CH2

4

VP

+US B_VC CA

1

2

USB 20_L_P 2USB 20_L_ N2

+5V ALW+5V ALW

USB 20_L_ N0
USB 20_L_P 0

JP1 3

13

G614G5

12

G311G4

9

G210G1

4

8

VSS

VSS

3

D0+

2

D0-

1

VCC

CO NN@

SU YIN_ 02012 2GR00 8S51C ZL

09 /01 u pd ate

Ne ed C orre ct th e Sym bo l a nd

L

re ve rse th e con nec tion.

USB 20_L_ N2

7

D1+

USB 20_L_P 2

6

D1-

5

VCC

USB 20_P015

USB 20_N015

USB 20_P215

USB 20_N215

USB 20_N115

USB 20_P11 5

R3 52 0_04 02_5%

USB 20_P0

USB 20_P2

USB 20_N1 USB 20_P 8_R

1 2

1

1

4

4

L8 W CM- 2012-900T_ 4P@

R3 50 0_04 02_5%

1 2

R3 54 0_04 02_5%

1 2

1

1

4

4

L9 W CM- 2012-900T_ 4P@

R3 53 0_04 02_5%

1 2

R3 60 0_04 02_5%

1 2

1

1

4

4

L19 WC M-2012 -900T_4P@

R3 55 0_04 02_5%

1 2

USB 20_L_P 0

2

2

USB 20_L_ N0USB 20_N0

3

3

USB 20_L_P 2

2

2

USB 20_L_ N2USB 20_N2

3

3

R4 43 0_04 02_5%

USB 20_L_ N1

2

2

USB 20_L_P 1USB 20_P1

3

3

USB 20_P815

USB 20_N815

USB 20_P8

1 2

1

1

4

4

L26 WC M-2012 -900T_4P@

R4 44 0_04 02_5%

1 2

2

2

3

3

06 /18 u pd ate

US B20_ N8_RUS B20_ N8

USB+power conn.(Left Side)-debug port

+5V ALW +5VALW

1

B B

SLP _S4#1 4,29, 33,39

11 /03 u pd ate

L

C5 04

4.7U _0805 _10V4Z

1 2

470K _0402_5 %

0.01 U_040 2_16V7K

2

R1 1

SLP _S4_R

1

C7

2.5A norma l with 3.0A Max Peak(1ms)

2

Clo se to U3 3 p in3 a nd pin 4

U3 3

1

GND

2

IN

3

EN1#

4

EN2#

G54 6A1P1 UF_SO8

100K _0402_5 %

8

OC1#

7

OUT1

6

OUT2

5

OC2#

R5 01

R4 45

100K _0402_5 %

1 2

1 2

0.1U _0402 _16V4Z

1

1

+

C4 16

C4 17

2

150U _B2_ 6.3VM_R35M

USB 20_L_ N1 US B20_ L_P1

2

1000 P_0402_50 V7K

D2 0

2

CH1

1

VN

CM1 213-02S R_SOT143- 4@

+U SB_V CCC

1

C4 18

2

3

CH2

4

VP

+5V ALW

USB 20_L_ N1
USB 20_L_P 1

SUY IN_02 0173M R004 S582ZL

JP1 4

CO NN@

1

1

2

2

3

3

4

4

5

GND

6

GND

7

GND

8

GND

BT Connector

JP1 2

1
2

USB 20_P 8_R

3

US B20_ N8_R

4
5

ACE S_87 212-05G0_5PCON N@

USB 20_N8 USB 20_P8

2

3

D1 7

PJD LC05_ SOT23-3 @

1

+3VAUX _BT

BT_L ED 28

BT_ OFF15

R4 46

10K _0201_5%

12

1 2

220K _0402_1 %

SI2 301CD S-T1-G E3 1P SO T23-3

1

C5 06

0.1U _0402 _16V4Z@

R4 47

2

S

G

2

09 /21 u pd ate

Q26

D

13

R1 35

470_0402_5%

Q55B

5

2N70 02DW H 2N SOT3 63-6

3

4

+3VAUX _BT+3V ALW

1

C4 09

2

0.1U _0402 _16V4Z

1

C4 10

10U_ 0805_ 10V4Z

2

ACCELEROMETER

C C

Left side USB conn.(Extra-USB)

(2A,10 0mils ,Via N O.=4)

+5V ALW

1

C4 15

4.7U _0805 _10V4Z

D D

2

SLP _S4#

1

07 /17 u pd ate

U2 0

1

GND

2

IN

3

IN

4

EN#

G54 7F1P8 1U MSO P 8P

+5V ALW

8

OUT

7

OUT

6

OUT

5

OC#

R4 48

1 2

10K _0201_5%

1

C6 20

2

0.1U _0402 _16V4Z

+US B_VC CB

1

1000 P_0402_ 50V7K

2

2

C6 21

USB 20_N315

USB 20_P31 5

+US B_VC CB

JP1 5

CO NN@

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

DP

9

V5

10

V5

11

MD

12

GND

13

GND

P-T WO_1 21057-1 3251_13P_NR -T

+3V S_ACL _IO

+3V S_ACL

ACC EL_IN T#15

SMB_D ATA_S34, 9,10, 11,13
SMB _CLK_S34,9,1 0,11, 13

+3V S_ACL

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+3VS +3V S_ACL +3V S_ACL_ IO

U2 1

1

VDD_IO

6

VDD

8

INT 1
INT 29GND

12

SDO

13

SDA / SDI / SDO

14

R4 50 10K_ 0201_5%

2008/09/15 2010/12/31

12

Compal Secret Data

SCL / SPC

7

CS

HP3 02DLT R8_LGA14_3 X5

<BO M Stru cture>

Deciphered Date

LIS302DL

RSVD
RSVD

4

R4 49
0_06 03_5%

1 2

2

GND

4

GND

5

GND

10

3
11

+3V S_ACL

0.1U _0402 _16V4Z

10U_ 0805_6. 3V6M

C4 19

C4 20

1

1

2

2

+3V S_ACL

Title

Size D ocum ent N umber R ev

Da te: She et o f

Compal Electronics, Inc.

USB & BT Connector & Acclerometer

LA -52 51P

5

24 47T uesda y, J anuar y 05 , 201 0

0. 9

1

PC I_AD [0.. 31]1 5

+3VS

A A

R4 51

100K _0402_1%

12

CBS _GRST #

1

C4 41
1U_0 603_6. 3V6M

2

SDC LK_M MCCLK

R4 54

10_0 201_5%

12

@

4.7P _040 2_50V8C

C4 46

1

@

2

B B

P CI_AD 22 CBS _IDS EL

CLK _PCI_ 13941 5

PM_ CLKR UN#14 ,30,3 1

C C

R4 56

1 2

470_ 0402_5%

+3VS

+S C_PW R

R4 52

12

@

C4 42

@

CLK _PCI_ 1394

10_0 201_5%

4.7P _040 2_50V8C

1

2

PCI _CBE 3#1 5
PCI _CBE 2#1 5
PCI _CBE 1#1 5
PCI _CBE 0#1 5

PC I_PA R1 5
PCI _FRA ME#15
PC I_T RDY#15
PC I_I RDY #1 5
PCI _STOP#15
PCI _DEV SEL#1 5

PC I_PE RR#15
PC I_SE RR#1 5,22, 30,31

PC I_RE Q2#15
PCI _GNT2 #1 5

PCI _RST#15 ,22

R4 57 10K_ 0201_5%@

1 2

R4 58 0_02 01_5%

1 2

R4 59 10K_ 0201_5%

1 2

R4 60 0_02 01_5%

1 2

1 2

R4 62 10K _0402_5%

PC I_PI RQE#15
PC I_PI RQG#1 5

R4 65 10K_ 0201_5%

1 2

+3VS

1 2

R4 66 100K _0201_5%

SMART Card Connector

JP1 6

1

1

2

2

SC_ RST

3

3

4

4

S C_CLK

5

GND
GND

CO NN@

5

SC_ DATA

6

6

7

7

8

8

SC _CD #

9

9

10

10

11
12

D D

ACE S_85 201-1005N

+S C_PW R

1

+S C_PW R

1

C4 53

2

0.1U _0402 _16V4Z

P CI_AD 31
P CI_AD 30
P CI_AD 29
P CI_AD 28
P CI_AD 27
P CI_AD 26
P CI_AD 25
P CI_AD 24
P CI_AD 23
P CI_AD 22
P CI_AD 21
P CI_AD 20
P CI_AD 19
P CI_AD 18
P CI_AD 17
P CI_AD 16
P CI_AD 15
P CI_AD 14
P CI_AD 13
P CI_AD 12
P CI_AD 11
P CI_AD 10
PC I_A D9
PC I_A D8
PC I_A D7
PC I_A D6
PC I_A D5
PC I_A D4
PC I_A D3
PC I_A D2
PC I_A D1
PC I_A D0

PCI _CBE 3#
PCI _CBE 2#
PCI _CBE 1#
PCI _CBE 0#

P CI_PA R
PCI _FRA ME#
PC I_ TRDY#
PC I_I RD Y#
PCI _STOP#
PCI _DEV SEL#

PC I_P ERR#
PC I_S ERR#

PCI _REQ 2#
PCI _GNT 2#

CLK _PCI_ 1394

CBS _GRST #

PME#

SC_ RST
SC _CLK _RSC _CLK
SC_ DATA
SC _CD #
SCS ENSE

SC_ RST

S C_CLK

SC_ DATA

SC_ RST

S C_CLK

SC_ DATA

SC_ DATA

SC_ RST

S C_CLK

U2 2

121

AD31

122

AD30

123

AD29

124

AD28

125
126
127

1
4
5
7

9
10
12
13
14
27
28
29
30
31
32
34
36
39
40
41
42
43
44
45
46

2
15
26
37

25
16
18
17
21
19

3
22
24

120
119

117
116

82

114

78

89
88
87
86
85

112
113

77
81

98

101
105
109

07 /01 u pd ate

D5 4 1N41 48WS -7-F _SOD323- 2@

D5 5 1N41 48WS -7-F _SOD323- 2@

D5 6 1N41 48WS -7-F _SOD323- 2@

R4 63 15K _0402_5%@

1 2

R4 64 15K _0402_5%@

1 2

R4 68 15K_ 0402_5%

C4 49 12P _0402_5 0V8J

C4 50 12P _0402_5 0V8J

C4 51 12P _0402_5 0V8J

R5C835

AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

C/BE3#
C/BE2#
C/BE1#
C/BE0#

PAR
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL
PERR#
SERR#

REQ#
GNT#

PCICLK
PCIRST#
GBRST#
CLKRUN#
PME#

SCRST
SCCLK
SCIO
SCCD#
SCSENSE

INTA#
INTB#

HWSPND#
TEST

AGND
AGND
AGND
AGND

R5C8 35-T QFP128P _TQFP128_1 4X14

12

12

12

12

1 2

1 2

1 2

+S C_PW R

2

VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V

VCC_RIN

VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT

VCC_MD3V

AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V

SCVCC5EN#
SCVCC3EN#

UDIO0/SRIRQ#

2

VCC_3V

VCC_SC

TPBIAS0

TPAP0
TPAN0

TPBP0
TPBN0

MDIO00
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19

XI

XO

REXT
VREF

UDIO1
UDIO2
UDIO3
UDIO4
UDIO5

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

IEE E1394_ TPBN0
IEE E1394_TP BP0
IEE E1394_ TPAN0
IEE E1394_TP AP0

6
23
38
118

92

11
33
59
91
111

79

54

+3 V_PH Y

97
104
108

90

IEE E1394_T PBIAS0

110

IEE E1394_TP AP0

107

IEE E1394_ TPAN0

106

IEE E1394_TP BP0

103

IEE E1394_ TPBN0

102

S D_CAR D_DE T#

70
69

XD_ CE#

63

SD _WP

68

SDP WR0_ MSPW R_XD PWR

67

XDW P#

66

3I N1_LE D#

65

TP_MSEX TCK

64

SD_ MMC_ CMD

62

SDC LK_M MCCL K_R

60

SDD ATA0_M SDATA0

58

SDD ATA1_M SDATA1

57

SDD ATA2_M SDATA2

56

SDD ATA3_M SDATA3

55

MMC _D4

53

MMC _D5

52

MMC _D6

51

MMC _D7

50

XDC LE

49

XDALE

48

SC VCC 5EN#

83

SC VCC 3EN#

84

R5C8 32XI

95

R5C8 32XO

96

100
99

SI RQ

76

TP_ UDIO1

75

TP_ UDIO2

74

UD IO3

73

UD IO4

72

UD IO5

71

8
20
35
47
61
80
93
94
115
128

IEE E1394_T PBIAS0

0.01 U_040 2_16V7K

0.01 U_040 2_16V7K
C4 23

C4 22

C4 21

1

1

2

2

R4 55 0_02 01_5%

1 2

270P _0402_50V 7K

C4 52

R4 67

5.1K _0402_1 %

12

1

2

R4 69

56.2 _0402_1 %

R4 70

56.2 _0402_1 %

12

12

R4 80

56.2 _0402_1 %

12

12

0.01 U_040 2_16V7K

C4 54

1

1

2

2

R4 71 0_02 01_5%
R4 72 0_02 01_5%
R4 74 0_02 01_5%
R4 76 0_02 01_5%

R4 81

56.2 _0402_1 %

0.33 U_060 3_16V 4Z
C4 55

@

+3VS

0.01 U_040 2_16V7K

1

2

+3VS

0.01 U_040 2_16V7K

1

2

C4 39

SD _CAR D_DET # 31

T101 PA D
T102 PA D

SD _WP 3 1

SDP WR0_ MSPW R_XD PWR 31

T103 PA D
T104 PA D

SD_ MMC_C MD 31

SDD ATA0_MS DATA0 3 1
SDD ATA1_MS DATA1 3 1
SDD ATA2_MS DATA2 3 1
SDD ATA3_MS DATA3 3 1
MMC _D4 31
MMC _D5 31
MMC _D6 31

MMC _D7 31

T105 PA D
T106 PA D

SI RQ 12, 22,30 ,31

T107 PA D
T108 PA D

1 2
1 2
1 2
1 2

10U_ 0805_ 10V4Z

0.01 U_040 2_16V7K
C4 25

C4 24

1

1

2

2

0.01 U_040 2_16V7K

1

1

10U_ 0805_ 10V4Z

2

2

C4 36

C4 35

1

2

C4 40

3

C4 26

1 2

15P _0402_5 0V8J

+3VS

10U_ 0805_ 10V4Z

0.1U _0402 _16V4Z

0.01 U_040 2_16V7K

0.01 U_040 2_16V7K

1

2

C4 37

0.01 U_040 2_16V7K

0.47 U_060 3_16V 4Z

0.47 U_060 3_16V 4Z

1

1

2

C4 30

2

C4 38

1

1

1

2

2

2

C4 33

C4 31

C4 32

C4 34

1 2

15P _0402_5 0V8J

4

R5C8 32XI

12

Y7

24.5 76MH Z_16P F_1Y 72457 6CE1C~D

R5C8 32XO

SD,MMC,MS,XD muti-function pin define

MDIO
PIN Na me

MDIO00

SD Card
PIN Na me

SDCD#

MDIO01

+S C_PW R

0.01 U_040 2_16V7K

1

2

C4 44

10U_ 0805_ 10V4Z

1

2

C4 45

MDIO02

MDIO03

MDIO04

MDIO05

MDIO06

MDIO07

MDIO08

SDWP#

SDPWR0

SDPWR1

SDLED#

SDCCMD

SDCCLKMDIO 09

SDC LK_M MCCLK 3 1

MDIO10

MDIO11

MDIO12

MDIO13

MDIO14

SDCDAT0

SDCDAT1

SDCDAT2

SDCDAT3

MDIO15

MDIO16

MDIO17

MDIO18

MDIO19

0.01 U_040 2_16V7K
C4 47

R4 61

10K _0603_1%

12

1

2

IEE E139 4_TPBN0 _R
IEE E1394_ TPBP0_R
IEE E139 4_TPAN0 _R
IEE E1394_ TPAP0_R

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

JP3 7

1
2
3
4

SUY IN_02 0115F B004 S512ZL

CO NN@

TPB-

TPB+

TPA-

TPA+

GND
GND
GND
GND

5
6
7
8

2008/03/13 2010/12/31

Compal Secret Data

Deciphered Date

3

Q51B

5

2N70 02DW H 2N SOT3 63-6

4

+3VS

Function set pin define

UDIO3 UDIO5UDIO4 Function

Pull-down Disable MS,xD Card,serial ROMPull-down Pull-up

4

5

L20

1 2

+3VS

MMC Ca rd
PIN Na me

MMCCD#

MS Card
PIN Na me

MSCD#

MBK 2012 601YZF _2P

XD Card
PIN Na me

XDCD0#

XDCD1#

10U_ 0805_6. 3V6M

1

1

2

2

C4 28

C4 27

XDCE#

XDR/B#

MMCPWR

MSPWR

XDPWR

XDWP#

MMCLED#

MSLED#

XDLED#

MSEXTCK

MMCCMD

MMCCLK

MMCDAT0

MMCDAT1

MMCDAT2

MMCDAT3

MMCDAT4

MMCDAT5

MMCDAT6

MMCDAT7

MSBS

MSCCLK

MSCDAT0

MSCDAT1

MSCDAT2

MSCDAT3

XDWE#

XDRE#

XDCDAT0

XDCDAT1

XDCDAT2

XDCDAT3

XDCDAT4

XDCDAT5

XDCDAT6

XDCDAT7

XDCLE

XDALE

04 /23 Ad d Q28 to prev ent +5 VS fr om leaki ng throu gh Q2 7.

SC VCC 3EN#

1 2

+3VS

R1 088 10 0K_0 402_5%

1U_0 402_6 .3V4Z

2N70 02DW H 2N SOT3 63-6

SC VCC 3EN#

R1 091

1 2

SC VCC 5EN#

100K _0402_5 %

C4 48

R1 090

100K _0402_5 %

Q51A

2

+3VS

1

2

+5VS

12

61

2

31

Q28

AP2 309A GN-HF_SO T23-3

11 /13 u pd ate

+5VS

1

C9 67

1U_0 402_6 .3V4Z

R1 089

1 2

47K _0402_5%

2

2

3 1

Q27
AP2 301GN -HF_SOT 23-3

3 1

Q5 7

AP2 301GN -HF_SO T23-3

2

2

C9 69
1U_0 402_6 .3V4Z

1

+5VS

Pull-downPull-upPull-up Enable serial EEPROM

Pull-upPull-upPull-up Ensable MS,xD Card,disable serial ROM

UD IO5
UD IO3
UD IO4

R4 73 100K _0201_5%

1 2

R4 79 10K_ 0201_5%

1 2

R4 82 10K_ 0201_5%

Title

Size D ocum ent N umber Re v

Cu stom

Da te: She et o f

1 2

Compal Electronics, Inc.

1394+2 in 1 Card

LA -5 251 P

5

+3 V_PH Y

0.01 U_040 2_16V7K

+3VS

1000 P_0402_50 V7K

1

2

C4 29

+S C_PW R

C9 68

1

1U_0 402_6 .3V4Z

2

25 47T uesd ay, J anua ry 05 , 20 10

0. 9

5

+V DDA_ CODE C

R4 83

10K _0201_5%

12

HP_ DET

R5 10

100K _0201_1 %

HD A_SP KR

R6 14
20K _0201_1%

3

Q36B

5

2N70 02DW H 2N SOT3 63-6

4

R5 07
20K _0201_1%

61

Q36A

2

2N70 02DW H 2N SOT3 63-6

2

5

5

61

3

4

D D

C C

B B

L

LINE _OUT _SENSE29

A A

HD A_SP KR1 2

MIC _SENS E27

+V DDA _CODE C

R5 00

10K _0201_1%

HP_ DET27

1 2

C4 70 0.1U _0805_ 25V7M

1 2

C4 73 0.1U _0805_ 25V7M

1 2

C4 75 0.1U _0805_ 25V7M

1 2

C4 78 0.1U _0805_ 25V7M

PJP 603

1 2

PAD -OPE N 4x 4m

Pl ace PJP6 03 b etw een DG ND and A GND by
3vi as an d 8 0 m ils s hap e bri dg e f or ESD.

1 2

R5 15

1 2

100K _0201_1 %

LINE _IN_ SENS E29

C4 56

0.1U _0402 _16V7K

1 2
61

Q29A
2N70 02DW H 2N SOT3 63-6

2

3

Q29B
2N70 02DW H 2N SOT3 63-6

5

4

SEN SE_A

12

SEN SE_B

12

HD A_S DIN01 2

LINE _OUT _SENS E#

Q32A
2N70 02DW H 2N SOT3 63-6

LINE _IN_ SENS E#

Q32B
2N70 02DW H 2N SOT3 63-6

1 2

+V DDA_ CODE C

R4 84

1 2

300K _0201_5 %

07 /24 u pd ate

+3VS

C4 89 10P _0402_25V 8K@

HDA _BIT _CLK_ CODE C12

HD A_S DOUT_ CODE C1 2

R4 99
33_0 201_1%

HD A_S YNC _CO DEC1 2

HD A_RS T#_CO DEC12

R5 11 39.2 K_040 2_1%

R5 14 39.2 K_040 2_1%

R4 87

10K _0201_5%

1 2

12

R7 03

4.7K _0201_5 %

HD A_RS T#_C ODEC

1

C6 37

0.01 U_040 2_16V7K

2

12

12

C4 94 1U_0 603_16V 7_X7R

C4 97 10U_ 0805_16 V6K_X5R

12

C5 00 100 0P_0402_ 50V7K_X7R

1 2

R5 12

R5 13

12

C5 01 100 0P_0402_ 50V7K_X7R

1 2

4

MO NO_ IN_H D

1 2

C4 57 0.1U _0402 _16V7K_X7R

C4 59 0.01 U_040 2_16V7K

1

2

+V DDA _CODE C

C4 83

0.1U _0402 _16V7K

1

2

R4 97 10_0 201_5%@

12

HDA _BIT _CLK_ CODE C

HD A_S DOUT _CODE C

HD A_S DIN 0_CO DEC

HD A_S YNC _C ODEC

HD A_RS T#_C ODEC

12

MO NO_ IN_H D

12

+MI C_BIAS_ B

+MI C_BI AS_C

SEN SE_A

2.49K_0402_1%

12

2.49K_0402_1%

12

SEN SE_B

4

C4 84

1

2

3

1

1

D2 2 P JMB Z6V8_SOT2 3

D2 1

PJM BZ6V8_S OT23

R_S PK+
R_S PK­L_SP K+
L_SP K-

2

2

C4 62

C4 61

100P _0402_ 50V8J

1

2

3

3

100P _0402_ 50V8J

C4 64

100P _0402_ 50V8J

C4 63

100P _0402_ 50V8J

1

1

1

2

2

2

JP1 7

1

1

2

2

3

3

4

4

5

G1

6

G2

ACE S_85 204-04001

CO NN@

C4 71 0.02 2U_06 03_25V4Z _X7R

LINE _OU TL

C4 74 0.02 2U_06 03_25V4Z _X7R

C4 58 10U _0805_ 16V6K_X5R

C4 60 1U_ 0603_1 6V7_X7R

C4 65 1U_ 0603_1 6V7_X7R

C4 66 10U _0805_ 16V6K_X5R

LI NE_C _OUT RL INE_ OUTR

1 2

LINE _C_O UTL

1 2

12

12

12

12

1 2

C4 69 0.02 2U_06 03_25V4Z _X7R

1 2

C4 72 0.02 2U_06 03_25V4Z _X7R

C4 76 1U_0 603_16V 7_X7R

L

Pla ce R509,C 498,C4 99 close to U24.2 3.

L

R4 89

+V _CO DEC_R

0_08 05_5%

1

9

3

DO CK_O UT_R

41

DOC K_OUT _L

39

M IC1_C

22

M IC2_C

21

IN T_M ICR_C

24

INT _MICL _C

23

LI NE_O UTR

36

LINE _OU TL

35

DL INE _IN _RC_ R

15

DL INE _IN _RC_L

14

HP _I N_R

17

HP _IN_ L

16

47

2

4

MUT E_LE D_CNTL

30

31

43

44

45

48

7

49

12

C4 80

C4 81

4.7U _0805 _10V4Z

0.1U _0402 _16V7K

12

C4 87

C4 88

C4 90 1U_ 0603_1 6V7_X7R

C4 91 1U_ 0603_1 6V7_X7R

C4 92 1U_ 0603_1 6V7_X7R

C4 93 1U_ 0603_1 6V7_X7R

C4 95

C4 96

R5 08

12

0_02 01_5%

L

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+3VS

C4 85

10U_ 0805_16 V6K_X5R

0.1U _0402 _16V7K

1

2

U2 5

25

AVDD1

38

AVDD2

6

BITCLK

5

SDO

8

SDI_CODEC

10

SYNC

11

RESET#

46

DMIC_CLK

33

CAP2

12

PCBEEP

27

VREFFILT

28

VREFOUT-B

29

VREFOUT-C

32

NC

40

NC

37

NC

18

NC

19

NC

20

NC

13

SENSE_A

34

SENSE_B

26

AVSS1

42

AVSS2

92HD 75B3X 5NLGXYBX 8_QFN48_7X 7

C4 86
10U_ 0805_16 V6K_X5R

1 2

DVDD_LV

DVDD_CORE

DVDD_IO

PORTA_R

PORTA_L

PORTB_R

PORTB_L

PORTC_R

PORTC_L

PORTD_R

PORTD_L

PORTE_R

PORTE_L

PORTF_R

PORTF_L

EAPD/ SPDIF OUT 0 or 1 / GPIO 0

VOL_UP/DMIC_0/GPIO 1

VOL_DN/DMIC_1/GPIO 2

GPIO 3

VREFOUT-E / GPIO 4

GPIO 5

GPIO 6

SPDIF OUT1 / GPIO 7

SPDIF OUT0

DVSS

GPAD

L

U7 6

EAP D#

2

C4 82

A_S D#3 0

0.1U _0402 _16V7K

1

1

+V DDA _CODE C

2

2

47uF _6.3 V_1.3 _H1.9

+

DO CK_ OUTR

1 2

+

DOC K_OUT L DLIN E_OU T_L

1 2

47uF _6.3 V_1.3 _H1.9

12

12

12

12

2.2U _0603 _10V6K_X5 R

1 2

DL INE _IN_L

1 2

2.2U _0603 _10V6K_X5 R

EAP D#

MUT E_LE D_CNTL 3 0

A_S D#

BAT 54AW_S OT323-3~D

R5 09 15K _0402_1%

1 2

C4 98 0.1U _0402 _16V7K_X7 R

1 2

C4 99 1U_0 603_16V 7_X7R

1 2

R4 93 20K_ 0201_5%

R4 94 20K_ 0201_5%

60.4_0402_1%

R4 95

R4 96

60.4_0402_1%

INT _MIC1

INT _MIC2

2008/09/15 2010/12/31

1

3

12

12

DL INE_ OUTR DL INE_ OUT_ R

12

DLIN E_OU TL

12

MI C1 27

R5 02
R5 03
R5 04
R5 05

07 /24 u pd ate

Compal Secret Data

2

AMP. FOR INTERNAL SPEAKER

+5VS

9

17

8

18

30

SPK R_EN

23

2

1

3

4

12

L21 MBC 16081 21YZ F_0603

L22 MBC 16081 21YZ F_0603

INT _MIC1 27

INT _MIC2 27

6.04K_0402_1%

12

2K_0402_5%

12

6.04K_0402_1%

12

2K_0402_5%

12

14

13

28

11

21

5

33

SPK R_EN

12

12

Por t A = Doc k L ine Out
Por t B = Ext ern al M ic
Por t C = Int ern al M ic
Por t D = Int ern al Spe akers
Por t E = Lin e In
Por t F = Int ern al Hea dpho ne

Deciphered Date

2

U2 4

CPVDD

HPVDD

SPVDD

SPVDD

VDD

SPKR_EN

SPKR_RIN+

SPKR_RIN-

SPKR_LIN+

SPKR_LIN-

HPVSS

CPVSS

SGND

CPGND

SPGND

SPGND

TML

TPA 6047A 4RHB R_QFN32_5X 5

DO CK _LINE _IN_ RDL INE _IN_ R

DO CK_ LINE_ IN_L

REG_EN

REG_OUT

HP_EN

HP_INL

HP_INR

HP_OUTL

HP_OUTR

ROUT+

ROUT-

LOUT+

BYPASS

GAIN0

GAIN1

08 /28 u pd ate

R4 90

1 2

25

100K _0402_5 %

29

HP_ DET

22

HP _L_I N HP _IN_ L

C4 67 2.2U _0805 _10V6K

HP _R_ IN

C4 68 2.2U _0805 _10V6K

R_S PK+

R_S PK-

L_SP K+

L_SP K-

C4 77 1U_0 603_16V 7_X7R

C4 79 0.47 U_060 3_16V7K_X 7R

1 2

GA IN0

GA IN1

GA IN0

GA IN1

LOUT-

27

26

16

15

20

19

6

7

10

C1P

12

C1N

24

31

32

9/ 3 updat e

GAI N:10 dB

GAI N:12 dB

GAI N:1 5.6dB

GAI N:2 1.6dB

DO CK_ LINE _IN_R 2 9

DO CK_L INE_ IN_L 2 9

Title

Size D ocum ent N umber R ev

LA -52 51P

Da te: She et

1

+5V ALW

+V DDA _CODE C

R4 88 100K _0402_5 %@

1 2

1 2

1 2

HP_ OUTL 2 7

HP _OUT R 27

12

R4 91 100 K_0201_ 5%@

R4 92 100 K_0201_ 5%@

R4 85 0_0 201_5%

R4 86 0_0 201_5%

12

12

1 2

1 2

GAI N0 GAIN 1

L L

L H

H L

H H

DL INE_O UT_R 2 9

DLIN E_OU T_L 29

Compal Electronics, Inc.

HDA CODEC 92HD75

1

HP _I N_R

+5VS

+5VS

0. 9

o f

26 47T uesda y, J anuar y 05 , 201 0

5

4

3

2

1

R5 27

100K _0402_5%

1 2

+MI C_BIAS_ B

D D

1U_0 603_1 6V6K

HP_ OUTL26

HP _OUT R26

C C

EXT_MIC EXT _MIC_1

1 2

B B

+V DDA_ CODE C

1 2

R5 37 3K_ 0402_5% @

A A

1

C5 14

2

BAV 70W 3P C /C SOT -323

R5 16 60.4 _0402_1 %

R5 17 60.4 _0402_1 %

11 0NH_H LC060 3CSC CR11J T_5%

C6 390.47 U_040 2_6.3V6 K

R5 31

3K_ 0402_5%

INT _MIC _1_2

INT _MIC _2_2

R5 38
3K_ 0402_5%

1 2

@

1

C5 26
1U_0 603_1 0V4Z@

2

5

12

2.2K _0402 _5%
R5 28

D5 0

C6 38220 P_0402 _25V8J

12

1 2

1 2

20K _0402_5%

L27

1 2

+MI C_BI AS_C

12

12

R5 32
3K_ 0402_5%

1 2

C5 23 0.06 8U_06 03_16V7K

560K _0402_5 %

2

3

1

EXT_MIC

HP_ OUT_L HP_ L_OUT

12

R5 18

1

C6 41
68P _0402_5 0V8J

2

R6 17

1 2

1 2

EXT_M IC_2

110 NH_H LC060 3CSCC R11J T_5%

+V DDA _CODE C

R5 29

1 2

5

U7 5

1

P

IN+

4

O

3

IN-

G

2

LMV 331ID CKRG 4_SC70 -5~D
R5 26
120K _0402_5 %

1 2

L25 BLM 18BD 601SN 1D_0603

1 2

L23 BLM 18BD 601SN 1D_0603

1 2

L24 BLM 18BD 601SN 1D_0603

1 2

R5 19

20K _0402_5%

10K _0402_5%

INT _MIC _1_4INT _MIC _1_1 INT_ MIC_ 1_3

1

2

0.01 U_040 2_16V7K

EXT_M IC_3

+C ODE C_RE F

100P _0402_ 50V8J

C6 40

1

2

C5 27
68P _0402_50 V8J

C5 02

+V DDA_ CODE C

3

2

R5 39
10K _0402_5%

1 2

12

L30

R6 15

10K _0402_5%

1 2

MIC _SENS E 26

D2 4

PJD LC05_ SOT23@

2

1

3

MIC_EX TOUT

HP _R_O UTHP _OUT _R

1

1

C5 03

2

2

0.01 U_040 2_16V7K

04/ 27 Ch ang e C642 f rom 33 P to 15P vi a
ID T rec omm end to f ix th e SVT P f ail i ssue.

C6 42 15P _0402_5 0V8J

12

1 2

R7 04 100 K_0402 _5%

8

P

+

-

O

G

U4 4A

TLV 2462_SO8

4

C5 20

4

M IC1

1

INT _MIC _1_5

+C ODE C_REF

100P _0402_ 50V8J

1

2

C5 17 100P _0402_ 50V8J

1 2

1 2

R5 33 100 K_0402_ 5%

+V DDA_ CODE C

0.1U _0402 _16V4Z

C5 21

1

8

2

3

P

+

1

O

2

-

G

U2 6A

TLV2 462_SO8

4

INT _MIC126

JP3 5

7
5

4

3
1
2

6

SIN GA_2 SJ300 5-002211

CO NN@

HP_ DET 26

MI C1 26

04/ 24 Co rrec t the Sy mbol from SIN GA_2SJ -B960- 003
to SINGA_ 2SJ300 5-0 022 11, also corre ct th e
co nn ect io n f or fi x A udio work abn ormal is sue.

8

5

P

+

7

O

6

-

G

U4 4B

TLV2 462_SO8

4

+V DDA_ CODE C

1 2

R5 34 3K_ 0402_5% @

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

INT _MIC _2_2

R5 35

1

C5 24
1U_0 603_1 0V4Z@

2

3K_ 0402_5%

1 2

@

110 NH_H LC060 3CSCC R11J T_5%

1 2

C5 22

0.06 8U_06 03_16V7K

2008/09/15 2010/12/31

L29

1 2

Compal Secret Data

Deciphered Date

INT _MIC _2_4INT _MIC _2_1 INT_ MIC_ 2_3

1

C5 25
68P _0402_50 V8J

2

2

R5 36
10K _0402_5%

1 2

CO NN@

JP1 9

INT _MIC _1_2

1

1

2

2

INT _MIC _2_2

3

3

4

4

5

G1

6

G2

ACE S_8520 4-04001

INT _MIC _1_2 INT _MIC _2_2

2

3

PJS OT05C_S OT23

D3 8

1

+V DDA_ CODE C

1

C5 07

4.7U _0805 _10V4Z

INT _MIC _2_5

100P _0402_ 50V8J

C5 19

1

2

2

@

12

R5 24
47K _0402_5%

12

R5 25
47K _0402_5%

C5 16 100 P_040 2_50V8J

R5 30 100 K_0402_ 5%

+V DDA _CODE C

5

+

6

-

Title

Size D ocum ent N umber Re v

Da te: She et o f

+C ODE C_RE F

1 2

+C ODE C_RE F

1 2

0.1U _0402 _16V4Z

C5 18

1

2

8

P

7

O

G

U2 6B

TLV2 462_SO8

4

INT _MIC226

Compal Electronics, Inc.

AMP & Audio Jack

LA -5 251 P

1

27 47T uesd ay, J anua ry 05 , 20 10

0. 9

1

2

3

4

5

04/ 27 Del Q54, chang e the LED
cir cui t for commo n.

HDD_ STP#

R560

Q31B

3

5

12

4

A A

2N70 02DW H 2N S OT363-6

HDD_ HALTL ED12

@

100K_0201_ 5%

WW AN_TR ANSMIT_ OFF#1 5,23

WW _LED#23

WL_ LED#22

09/ 01 Upd ate

BT_LED

R541 100K_020 1_5%

1 2

JP23

R438

12

1
3
5
7
9

11

ACES_ 88025 -120N-CPCONN @

MOD _RING

3

1

+3VS

2

@

1

CAP_ INT

1

2

HDA_ SDOUT_ MDC1 2

B B

C C

D D

HD A_SYN C_MD C12

WL/ BT_LED#

CAP_ CLK13,3 0
CAP_D AT13,30
CAP_ INT30

LID_ SW#20,3 0

680P _0402_50V7K@

3

HD A_SDIN 112

HDA_ RST#_ MDC12

ACES_ 85204-02001

C742

LID_ SW#

2

D53
PJDL C05 3P _SOT23

1

R543 33_0402_ 5%

JP25

1

1

2

2

3

G1

4

G2

CON N@

+3VS +VREG 3_51125

R612 0_0201_5%

1 2

2

2

C744

330P _0402_50V7K

1

1

+3VL

5.1K_ 0402_5%

R695

1 2

R694

1 2

5.1K_ 0402_5%

1

HDA_ SDOUT_ MDC

HD A_SDIN 1_MDC

1 2

MOD _RING MOD_ TIP
MOD_ TIP

8/2 5 U pd ate

11/ 14 Upd ate

CON N@

JP28

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

CAP_ CLK

CAP_D AT

9

10

10

11

11

12

12

13

GND1

14

GND2

ACES_ 87213-120 0G

10K_0201_5 %

STB_LED#

1

2

3

4

5

6

7

8

9

10

11

12

GND13GND
GND15GND
GND17GND

1
2

3
4

FOX_JM 74613-V5-7F

WL_ LED#

2

D47

PJSOT 05C_SOT23

C752
330P _0402_50V7K

C627
220P _0402_25V

2
4
6
8
10
12

14
16
18

JP26

TIP
RING

GND
GND

CON N@

2N70 02DW T/R7_SOT -363-6

WW _LED#

WL_ LED#

+3VS

BITCL K_MDC

C531

@

1 2

CAP_ INT

STB_LED#

2

3

PJSOT 05C_SOT23

1

CAP_ CLK

CAP_D AT

2

3

D48

PJSOT 05C_SOT23

1

+3VL

2

C753

@

330P_ 0402_50V7K

1

2

1 2

R1099 0_04 02_5%

1 2

R1098 0_04 02_5%

1 2

R1097 0_04 02_5%

2N70 02DW T/R7_SOT -363-6

R544

0_0201_5%

10P_ 0402_25V8K

D49

Q34B

5

BT_LED24

12

3

+3VS

12

4

R540

47K_0402_5 %

WL/ BT_LED#

61

Q34A

2

HDA_ BIT_CLK _MDC 12

ON/ OFF#29

2

3

D45

1

PESD 24VS2UT_SOT 23-3~D

L

0.1U _0402 _16V4Z

AMBER _BATLED#30

AQUAW HITE_B ATLED#1 2,30

SATA_LE D#12,29

STB_LED#29

+3VS

1

1

1

C528

2

1 2

R547 47_ 0201_5%

+5VALW

ON/ OFF#
STB_LED#

Pla ce C670 c lo se to JP20.2's v ia.

ON/ OFF#

1

C670

2

11/ 11 up date for ESD.

C529

2

0.1U _0402_16 V4Z

1000P_ 0402_50V7K

JP20

1

1

2

2

3

3

4

4

5

G5

6

G6

ACES_ 85205-04001

CON N@

C530

2

4.7U _0805_10 V4Z

@

+3VL

12

1

2

+5VS

+3VL

+3VS

JP22

1

1

2

2

3

3

4

4

5

5

6

HDD_ STP#

WL/ BT_LED#

Pla ce C536 c lo se to JP22. 8

L

STB_LED#

07/ 02 up date

ON /OFFBTN _KBC#

0.1U _0402 _16V4Z

Add C146 cl ose t o D34 pin 1.

L

R546
100K_0201_ 5%

ON /OFFBTN _KBC#

C538

1U_0 603_10V4Z

CH75 1H-40 PT_SOD323-2@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

6

7

7

8

8

9

9

10

10

11

GND

12

GND

ACES_ 85201-10 05N

CON N@

1

C536

1000 P_0402_50V7K

2

1

C146

01/ 04 up date for ESD

2

ON/ OFFBTN _KBC# 30

07/ 22 up date

D34

1 2

100K_0402_ 5%

21

SP_C LK3 0

SP_D ATA30

0.1U _0402 _16V4Z

6/1 7 C orr ect JP 27 conn ection fro m currentl y
Pin 1:+5VS ,Pin2 :RI GHT,Pin7: GND,Pi n8:GND to
Pin 1:RIGH T,Pin 2:NC,Pin 7:NC, Pin8: +5VS.

Pla ce C668 c lo se to JP22.2.

L

+3VL

1

C668

0.1U _0402 _16V4Z

2

11/ 11 up dat e for EMI.

R550

+3VALW

ON/ OFFBTN # 14,30

CON N@

C535

1
2
3
4
5
6
7
8

1

E&T_ 6701-E08N-00 R

2

JP27

1
2
3
4
5
6
7
8

Compal Secret Data

Deciphered Date

4

RIG HT

LEFT

+5VS

2008/09/15 2010/12/31

KSO [0..11]30

KSI [0..7 ]30

KSO11
KSO0
KSO2
KSO5
KSI_D _14
KSI_ D_8
KSI_D _12
KSI_D _10
KSI_ D_0
KSI_ D_4
KSI_ D_2
KSI_ D_1
KSI_ D_3
KSO3
KSO8
KSO4
KSO7
KSO6

KSO10

KSO1
KSI_ D_5
KSI_ D_6

KSI7

KSI_D _13
KSI_D _11
KSI_ D_9

KSO9

LEFT
RIG HT

HRS_ FH28- 60(30) SB-1SH(86)

KSI0

1

KSI1 KS I5

1

KSI2

1

KS O[0..11 ]

KSI [0..7 ]

JP21

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

GND1

32

GND2

CON N@

D26

KSI_ D_0

2

KSI_ D_8

3

DAP20 2UGT1 06_SC-70
D28

KSI_ D_1

2

KSI_ D_9

3

DAP20 2UGT1 06_SC-70
D31

KSI_ D_2

2

KSI_D _10

3

DAP20 2UGT1 06_SC-70

TP_CLK30
TP_DATA30

+5VS

1

C532

0.1U _0402 _16V4Z

2

Title

Size Docu ment Number Re v

Dat e: Sheet o f

KSO11

C906 100P _0402_50V8J

1 2

C907 100P _0402_50V8J

1 2

C908 100P _0402_50V8J

1 2

C909 100P _0402_50V8J

1 2

C910 100P _0402_50V8J

1 2

C911 100P _0402_50V8J

1 2

C912 100P _0402_50V8J

1 2

C913 100P _0402_50V8J

1 2

C914 100P _0402_50V8J

1 2

C915 100P _0402_50V8J

1 2

C916 100P _0402_50V8J

1 2

C917 100P _0402_50V8J

1 2

C918 100P _0402_50V8J

1 2

C919 100P _0402_50V8J

1 2

C920 100P _0402_50V8J

1 2

C921 100P _0402_50V8J

1 2

C922 100P _0402_50V8J

1 2

C923 100P _0402_50V8J

1 2

C924 100P _0402_50V8J

1 2

C925 100P _0402_50V8J

1 2

C926 100P _0402_50V8J

1 2

C927 100P _0402_50V8J

1 2

C928 100P _0402_50V8J

1 2

C929 100P _0402_50V8J

1 2

C930 100P _0402_50V8J

1 2

C931 100P _0402_50V8J

1 2

C932 100P _0402_50V8J

1 2

D25

KSI3

1

DAP20 2UGT106 _SC-70
D27

KSI4

1

DAP20 2UGT106 _SC-70
D30

1

DAP20 2UGT106 _SC-70
D32

KSI6

1

DAP20 2UGT106 _SC-70

+5VS

JP29

1

1

2

2

3

3

4

4

5

G1

6

G2

ACES_ 50504-00 40N-001

CON N@

PJDL C05_SOT2 3-3
D29

3

1

KSO0
KSO2
KSO5

KSI_D _14

KSI_ D_8

KSI_D _12
KSI_D _10

KSI_ D_0
KSI_ D_4
KSI_ D_2
KSI_ D_1

KSI_ D_3
KSO3
KSO8
KSO4

KSO7
KSO6

KSO10

KSO1

KSI_ D_5
KSI_ D_6
KSI7

KSI_D _13

KSI_D _11
KSI_ D_9
KSO9

2

Compal Electronics, Inc.

MDC/KBD/ON_OFF/LID

LA -52 51P

5

2

3

2

3

2

3

2

3

KSI_ D_3

KSI_D _11

KSI_ D_4

KSI_D _12

KSI_ D_5

KSI_D _13

KSI_ D_6

KSI_D _14

0.9

28 47Tu esda y, Janu ary 05, 2010

1

2

3

4

5

6

7

8

VA

C5 41 0.1 U_060 3_50V4 Z

A A

MDO1+2 1 MDO 3+ 21
MDO 1-2 1
MDO0+2 1
MDO 0-2 1

LAN LINK_ STATUS#21 LAN _ACT# 2 1

LINE _IN_ SENS E26

LINE _OUT _SENSE26

DO CK_L INE_ IN_L2 6

DO CK_ LINE _IN_R26

DLIN E_OU T_L2 6

DL INE_O UT_R26

10K _0402_5%

SLP _S3#

STB _LED#2 8

USB 20_N1 11 5
USB 20_P1115

ON /OF F#28

DO CK_ ID015
DO CK_ ID115

+3V ALW

12

R4 9

13

2

G

ADP _SIG NAL

B B

DO CK_ RED18

DO CK_ GRN18

DO CK_B LU1 8

C C

DO CK _RED
DO CK _GRN
DO CK_ BLU

11 /05 u pd ate

SAT A_LED#1 2,28

SA TA_LED#

C5 42 0.1 U_060 3_50V4 Z

1

1

2

2

MDO 1+
MDO 1­MDO 0+
MDO 0-

ADP _SIG NAL PRE P#
SLP _S3#

ON /O FF#
VA_ ON#

DL INE _IN_L
DL INE _IN_ R

DLIN E_OU T_L
DL INE_ OUT_ R

DOC K_DE TECT#

R_ DOC K_RE D

R5 550 _0402_ 5%

12

R_ DOC K_G RN

R5 560_04 02_5%

12

R_ DOC K_BL U

R5 570_04 02_5%

12

SAT A_LED#_ Q

D

Q79
2N70 02H_S OT23-3

S

2

3

PJD LC05_ SOT23-3@

1

JP3 0

1

RJ45_B+

2

RJ45_B-

3

RJ45_A+

4

RJ45_A-

5

RJ45_LINKLED#

6

PWRLED

7

DOCK_ADP_SIGNAL

8

5VS(0.5A)

9

GND

10

USB1-

11

USB1+

12

GND

13

NBSWON#

14

VA_ON#

15

DOCK_ID0

16

DOCK_ID1

17

AUDIO AGND

18

LINE_IN_SENSE

19

LINE_OUT_SENSE

20

AUDIO AGND

21

LINE_IN_L

22

LINE_IN_R

23

AUDIO AGND

24

LINE_OUT_L

25

LINE_OUT_R

26

AUDIO AGND

27

DETECT2#

28

GND

29

CRT_R

30

CRT_G

31

CRT_B

32

GND

33

RESERVED(USB3_RX+)

34

RESERVED(USB3_RX-)

35

GND

36

RESERVED(USB3_TX+)

37

RESERVED(USB3_TX-)

38

GND

39

RESERVED(SATA_LED#)

40

GND

DO CK _RED
DO CK _GRN
DO CK_ BLU

DO CK _RED
DO CK _GRN
DO CK_ BLU

VIN VA

1 2

D3 5

VA

81

VA

RJ45_ACTLED#

DETECT1#

CRT_DDC_DATA

CRT_DDC_CLK

CRT_VSYNC
CRT_HSYNC

RESERVED(SATA_RXP)
RESERVED(SATA_RXN)

RESERVED(SATA_TXP)

RESERVED(SATA_TXN)

GND82GND83GND84GND85GND

FOX _QL10 44L-D261A 1-7H

86

CO NN@

C5 47 0.1 U_040 2_16V 4Z@

1 2

C5 48 0.1 U_040 2_16V 4Z@

1 2

C5 49 0.1 U_040 2_16V 4Z@

1 2

R5 64 150_ 0402_1%@

1 2

R5 68 150_ 0402_1%@

1 2

R5 70 150_ 0402_1%@

1 2

R6 98

0_08 05_5%

RJ45_D+

RJ45_D-

RJ45_C+

RJ45_C-

PREP#

5VS(0.5A)

GND

DP_ML0+

DP_ML0-

GND

DP_ML1+

DP_ML1-

GND

DP_ML2+

DP_ML2-

GND

DP_ML3+

DP_ML3-

GND

DP_AUX+

DP_AUX-

GND
DCAD
HCED

HPD

GND

GND

GND

GND

GND

08 /28 u pd ate

MDO 3+

41

MDO 3-

42

MDO 2+

43

MDO 2-

44

04/ 22 Ch ang e JP30 Pin 46 and 27 c on nec ti on from GND to DOCK_DET ECT#

45

DOC K_DE TECT#

46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

D_ DDC DATA

69

D_ DDC CLK

70
71
72
73
74
75
76
77
78
79
80

MDO 3- 21
MDO 2+ 21
MDO 2- 21

PRE P# 15, 18,21
SLP _S4# 14, 24,33 ,39SLP _S3#14,2 3,30, 32,33 ,35,37 ,38

04/ 20 JP3 0.8 b eco me NC, J P30 .48 co nnect t o S LP_S4 # f rom HP

DPB_TX P0 14
DPB_T XN0 14

DPB_TX P1 14
DPB_T XN1 14

DPB_TX P2 14
DPB_T XN2 14

DPB_TX P3 14
DPB_T XN3 14

DPB _AUX 14
DPB _AUX# 14

DPB _CTR LCLK 14
DPB _CTR LDATA 14
DP B_HP D 14

D_ DDC DATA 1 8
D_ DDC CLK 1 8

D_ VSY NC 18
D_ HS YNC 1 8

SATA_ PRX_DTX_P5 1 2
SATA_ PRX_DTX_ N5 12

SATA_ PTX_DRX_P5 1 2
SATA_ PTX_DRX_ N5 12

4/ 5 upda te for H P Doc kin g pin defi ne ch ang e

VA_ ON#

R5 52

1K_ 0201_5%

12

1

C5 40

0.1U _0402 _16V4Z

2

D D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

3

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

2008/09/15 2010/12/31

Compal Secret Data

Deciphered Date

6

Title

Size D ocum ent N umber Re v

Cu stom

Da te: She et o f

7

Compal Electronics, Inc.

DOCK CONN

LA -5 251 P

29 47T uesd ay, J anua ry 05 , 20 10

8

0. 9

1

100K _0402_5%@

ROM _CS# 0

SPI _SI31

SPI _CS0#31

SPI _SO31

PMC35

12

1U_0 603_1 0V4Z

C5 63

R5 21

PM _CLK RUN#14 ,25, 31

CL K_PCI _KBC15

RU NSC I_E C#15

LPC _LFRA ME#1 2,22, 31

NP CI_RS T#15

+3VL

12

1 2

R5 76 0_04 02_5%

1 2

R5 77 0_04 02_5%

1 2

R5 78 0_04 02_5%

KSO [0.. 11]28

TP_ CLK28

TP_DA TA2 8

SP_ CLK28

SP_ DATA28

SI RQ12, 22,25 ,31

LPC _LAD312,2 2,31
LPC _LAD212,2 2,31
LPC _LAD112,2 2,31
LPC _LAD012,2 2,31

+V CC0

OC P_A_ IN

+R TCVC C

1

2

0.1U _0402 _16V4Z

KS I[0. .7]28

TP _CLK
TP_DAT A
SP_ CLK
SP _DATA

CLK _PCI_ KBC
RU NSC I_E C#

1 2

R6 03 0_0 402_5%

1 2

R6 04 0_0 402_5%
R1 101 300 _0402_5%

1 2

1 2

R1 102 300 _0402_5%

12

R6 10
0_04 02_5%

1

C5 64

0.1U _0402 _16V4Z

2

C5 53

ROM _DATOU T

ROM _CS# 0

ROM _DAT IN

KS O0
KS O1
KS O2
KS O3
KS O4
KS O5
KS O6
KS O7
KS O8
KS O9
KS O10
KS O11

KSI 0
KSI 1
KSI 2
KSI 3
KSI 4
KSI 5
KSI 6
KSI 7

CR Y1
CR Y2

ROM _CLK

AD C1
AD C

+V CC0

0.1U _0402 _16V4Z

1

C5 54

2

128
127

97
96
95
94

21
20
19
18
17
16
13
12
10

9
8
7
6
5

29
28
27
26
25
24
23
22

35
36
61
62
66
67

55
57
54
76

51
50
48
46

52
53

70
71

68

1
2

3
30
31
32
33
34
43
44

+3VL

RP 7

KSI 3

1 8

KSI 2

2 7

KSI 1

3 6

KSI 0

+5VS

R5 87

@

C5 60

@

22P _0402_50 V8J

Y5

C5 61

1

2

4 5

10K _0804 _8P4R_5%

RP 8

1 8
2 7
3 6
4 5

10K _0804 _8P4R_5%

ROM _CLK

C6 54

1

4.7P _040 2_50V8C@

2

RP 9

1 8
2 7
3 6
4 5

10K _0804 _8P4R_5%

RP 10

1 8
2 7
3 6
4 5

10K _0804 _8P4R_5%

CLK _PCI_ KBC

10_0 402_5%

12

4.7P _040 2_50V8C

1

2

4IN1

OUT

NC3NC

2

KSI 7
KSI 6
KSI 5
KSI 4

TP _CLK
TP_DAT A

SP_ CLK
SP _DATA

22P _0402_50 V8J

C5 62

1

2

32.7 68KH Z QT FM28-32 768K125P20L

KBC _SPI _SI_R12

KBC _SPI _CS0 #_R12

KBC _SPI _SO1 2

BAT_A LARM

KBC _SPI _CLK_R12

SPI _CLK31

MC2 _DISA BLE22

KBC _SPI _CS1 #_R12

SPI _CS1#31
MC1 _DISA BLE23
PM_ SLP_LAN#14 ,33, 39

OC P_A_ IN41

R6 11

0_04 02_5%@

1

A A

B B

C C

D D

2

07 /01 u pd ate

0.1U _0402 _16V4Z

1

1

1

C5 55

2

0.1U _0402 _16V4Z

U3 2

FLDATAOUT
HSTDATAOUT/GPIO45
FLCS0#
HSTCS0#/GPIO44
FLDATAIN
HSTDATAIN/GPIO43

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12/GPIO00/KBRST
KSO13/GPIO18

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

IMCLK
IMDAT
KCLK
KDAT
EMCLK
EMDAT

CLKRUN#
SER_IRQ
PCI_CLK
EC_SCI#

LAD[3]
LAD[2]
LAD[1]
LAD[0]

LFRAME#
LRESET#

XTAL1
XTAL2

VCC0

Alarm [CKT#2]/GPIO36
HSTCLK/GPIO41
FLCLK
GPIO39
HSTCS1#/GPIO42
FLCS1#
GPIO38
GPIO37
ADC1/GPIO46
ADC_TO_PWM_IN

KBC 1098- NU_VTQ FP128_14X 14

C5 57

C5 56

2

2

4.7U _0805 _10V4Z

Pow er Mgm t/S IRQ

LPC
Bus

2

Key boa rd/ Mou se Int erface

1

2

+3VL

12

R5 90

0_06 03_5%

1

C5 65

0.1U _0402 _16V4Z

2

14

106

119

VCC1

VCC139VCC158VCC184VCC1

SMSC_1098-NU_TQFP-128P

Access Bus I nterface

AGND

VSS11VSS37VSS47VSS56VSS

72

VSS82VSS

104

117

R6 09

0_04 02_5%

1 2

R5 73 0_04 02_5%

1

C5 58

0.1U _0402 _16V4Z

2

49

VCC1

VCC2

GPIO11/AB2A_DATA

GPIO13/AB2B_DATA

GPIO15/FAN_TACH1
GPIO16/FAN_TACH2

ADP_PRES[CKT#2]/GPIO27/WK_SE05

Gen era l P urp ose I/ O I nte rface

32KHZ_OUT/GPIO22/WK_SE01

RESET_OUT#/GPIO06

ADC_TO_PWM_OUT/GPIO19

Mis cel lan eous

AVSS

45

12

GPIO28
GPIO29
GPIO30
GPIO31
GPIO32

OUT0/(SCI)

OUT1/IRQ8#

CFETA/OUT7/nSMI

OUT8/KBRST

OUT9/PWM2

OUT10/PWM0

PWM_CHRGCTL

GPIO01
GPIO02

GPIO03
GPIO04/KSO14
GPIO05/KSO15

GPIO07/PWM3

GPIO08/RXD
GPIO09/TXD

GPIO12/AB2A_CLK

GPIO14/AB2B_CLK

GPIO17/A20M

GPIO20/PS2CLK
GPIO21/PS2DAT

GPIO24/KSO16

AB1A_DATA

AB1A_CLK

AB1B_DATA

AB1B_CLK

GPIO25

GPIO26/KSO17

NC_CLOCKI

PWRGD

VCC1_RST#

TEST PIN

CFETB/GPIO10

BAT_LED#

PWR_LED#/8051TX

FDD_LED#/8051RX

AC[CKT#2]/GPIO23

ADC2/GPIO40

Q/GPIO33

GPIO34

GPIO35

AVCC

3

4

L

+3VS

07 /01 u pd ate

C5 59 4.7 U_080 5_10V6K

15

CAP

93
98
99
100
126

124
125

123
122
121
120
118

107
79
80
81
83

85
86
87

88
89
90
91
92
101
102

103
105
4
74

111
112

109
110

73

108
59
75
60
78
77
38

69

116
113
115
114

41
42
65
64
63
40

3

1 2

R5 79 0_04 02_5%

1 2

KB RST#

D3 6

CH75 1H-4 0PT_S OD323-2

CPU _SV_ ID_D ET
SLP _S3#

PM_ RSMRST#
CRA CK_B GA
BD _ID

AB 2A_DATA

R5 82 0_02 01_5%

AB2 A_CLK

R5 83 0_02 01_5%
R5 84 0_02 01_5%
R5 85 0_04 02_5%

R7 06 0_04 02_5%

PWR BTN_ OUT#

R6 08 0_04 02_5%@

AB 1A_DATA
AB1 A_CLK

AB 1B_DATA
AB1 B_CLK

R5 88 0_02 01_5%

32K _CLK

R5 92 0_02 01_5%

PG D_I N
PW R_ GD

R5 95 0_02 01_5%

TEST

R5 96 1K_0 201_5%

R6 01 100K _0201_5%

AD C2

R1 100 300_ 0402_5%

LI D_SW #

LI D_SW #

R3 63

1 2

100K _0402_5 %

07 /02 u pd ate

AD C

C9 70220 0P_0402 _25V7K

12

AD C1

C9 71220 0P_0402 _25V7K

12

AD C2

C9 72220 0P_0402 _25V7K

12

1 2
1 2
1 2
1 2

1 2

1 2

1 2

1 2

07 /03 u pd ate

1 2

1 2

1 2

1 2

11 /06 u pd ate

PM_SL P_M# 14, 32,33
SUS _PWR _ACK 1 4
AC_ PRES ENT 14
MUT E_LE D_CNTL 26
PC I_SE RR# 15, 22,25 ,31

KB C_PW R_ON 36
AQU AWHI TE_BA TLED# 12 ,28

21

KB_ RST# 15
FAN _PWM 4
BAT_ PWM_OUT 35
CH GCTR L 35

ON/ OFFB TN_K BC# 28

SLP _S3# 14, 23,29 ,32,3 3,35,3 7,38
8051 _REC OVER# 22,31

PM_RS MRST# 14
CRA CK_B GA 8,1 7

LA NLIN K_R#

+3VL

11 /14 u pd ate

CAP _DAT 1 3,28
CAP _CLK 1 3,28
CEL LS 35
A_S D# 26
ADP _DET# 4 1
THM _MAIN# 3 4
GATEA 20 15

ON /OFF BTN# 1 4,28

LA NLINK _R# 15 ,21
ADP _PRES 33,35

AB1 A_DATA 3 4
AB1 A_CLK 3 4

AB1 B_DATA
AB1 B_CLK

CAP _INT 2 8

ADP _EN 4 1

PW R_G D 32
VC C1_ PWRG D 36,4 1
OC P 41

AMB ER_BAT LED# 28
8051TX 22 ,31
8051RX 22,31

+3VL

AC_ ADP_ PRES 35
ADP _A_I D 41

LI D_SW # 20,2 8

PG D_I N14, 40

L

07 /01 u pd ate

PG D_I N

PM_ RSMRST#

07 /02 u pd ate

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/09/15 2010/12/31

Compal Secret Data

Deciphered Date

4

01 /0 4 upda te (Ca ncel Boa rd ID De tec t rese rve
cir cui t (De l U 8,Q37, R571,R572,R 574,R5 75)).

07 /22 u pd ate

L

CAP _CLK S PI_C LK

4.7P _040 2_50V8C

C6 22

1

@

2

R6 06 10K_ 0201_5%@

R6 07 100K _0201_5%

C6 34

@

1 2

1 2

5

CPU _SV_ ID_D ET

R5 51 100K _0402_5%

1 2

R5 53 100K _0402_5%@

1 2

CPU T ype De tec t : H igh -->SV , Lo w-->L V ( No use)

07 /02 u pd ate

KB RST#

R5 89 10K_ 0201_5%@

4.7P _040 2_50V8C

1

2

VC C1_ PWR GD

CRA CK_B GA

BD _ID

KB C_P WR_O N

Title

Size D ocum ent N umber Re v

LA -52 51P

Da te: She et o f

1 2

R5 91 10K_ 0201_5%

1 2

1 2

1 2

1 2

AB1 A_CLK
AB 1A_DATA
AB1 B_CLK
AB 1B_DATA

RP 11

4.7K _080 4_8P4R_ 5%

1 8
2 7
3 6
4 5

R5 93 10K_ 0201_5%

R5 86 10K_ 0201_5%

R5 97 10K_ 0201_5%

Compal Electronics, Inc.

KBC1098

5

+3VL

+3VL

+3VL

0. 9

30 47T uesd ay, J anua ry 05 , 20 10

1

2

3

4

5

TPM1.2 on board

LPC Debug Port

12P _0402_50 V8J

A A

B B

C C

D D

CL K_PC I_DB

1

res erv e it for W WAN n oise

C6 55

@

2

CL K_PCI _DB15, 22

LPC _LFRA ME#1 2,22, 30
SI RQ12, 22,25 ,30
PLT_R ST#4 ,12,1 5,21, 22,23
PC I_SE RR#1 5,22, 25,30
LPC _LAD012,2 2,30
LPC _LAD112,2 2,30
LPC _LAD212,2 2,30
LPC _LAD312,2 2,30

8051TX22 ,30
8051RX22,3 0
8051 _REC OVER#2 2,30
DEB UG_K BCRST22,3 6

SPI _CS1#30

BIOS ROM(8MB)

8MB SPI ROM

+3VL

SPI _CS0#30

SPI _CLK30

SPI _SI30

SPI _HOL D#_0 SPI _HOL D#_1

SPI _CLK _JP S PI_C LK

SPI _SI_ JP SPI _SI

8MB SPI ROM

&U 2

45@

W25Q64BVSSIG SOIC 8P

SPI ROM

8051 _REC OVER#

B+_ DEBUG

CL K_PC I_DB

SI RQ

8051 _REC OVER#

SPI _CLK _JP
SPI _CS0 #_JP
SPI _SI_ JP
SPI _SO_J P
SPI _HOL D#_0

20mils

1 2

R6 33 0_0 201_5%

1 2

R6 34 0_0 201_5%

1 2

R6 35 0_0 201_5%

1 2

R6 36 0_0 201_5%

1 2

R6 37 0_0 201_5%

@

SST25VF064B-66_SO8

R6 28 100K _0201_5%

1 2

JP3 1

1

Ground

2

LPC_PCI_CLK

3

Ground

4

LPC_FRAME#

5

+V3S

6

LPC_RESET#

7

+V3S

8

LPC_AD0

9

LPC_AD1

10

LPC_AD2

11

LPC_AD3

12

VCC_3VA

13

PWR_LED#

14

CAPS_LED#

15

NUM_LED#

16

VCC1_PWRGD

17

SPI_CLK

18

SPI_CS#

19

SPI_SI

20

SPI_SO

21

SPI_HOLD#

22

Reserved

23

Reserved

24

Reserved

ACE S_87 216-2404_24P

CO NN@

+3VL

1

C5 81

0.1U _0402 _16V4Z

R6 29 3.3K _0201_5 %

1 2

SPI _CS0 #SPI _CS0 #_JP

SPI _SO _R0SPI _SO_J P

&U 1

2

+3VL

Finger Printer

+3VL

20mils

25mA

SPI _WP#

SPI _HOL D#_1

SPI _CS0 #

SPI _CLK

20mils

SPI ROM SOCKET

U3 5

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

ACE S-919 60-0084LC ON N@

R6 31

1 2

3.3K _0201 _5%

+3V ALW

FP R_O FF15

4

VSS

SPI _SO _R0SP I_SI

2

Q

05/ 06 up dat e R630 f rom @ 33_ 0402 beco me insta ll.

SPI _WP#

Q38 SI 2301C DS-T 1-GE3 1P SOT23-3

S

R6 20
10K _0201_5%

1 2

R6 25
220K _0402_1 %

1 2

1 2

R6 30 33_0 402_5%

R6 32

1 2

0_02 01_5%@

D

G

2

01/ 04 up dat e (Can cel 1 6pi n BIO S r eserve (D el U3 6 a nd R6 96) ).

C5 79 10U_ 0805_ 10V4Z

USB 20_N1 015
USB 20_P1015

1

2

D3 9

2

CH1

1

VN

CM1 213-02S R_SOT143- 4

US B20_ N1_P WR

3

CH2

4

VP

13

C5 78 0.1U _0402 _16V4Z

1

2

USB 20_N 10 USB20 _P10

SPI _SO 30

SPI _CLK

12

R6 27

10_0 201_5% @

1

C5 82

4.7P _040 2_50V8C@

2

1 2

C5 72 22P_ 0402_50V 8J

Y6

CO NN@

JP3 2

1

1

2

2

3

3

4

4

5

G1

6

G2

ACE S_85 201-0405N

2

3

32.7 68KH Z QT FM28-3276 8K125P20L

1 2

C5 77 22P_ 0402_50V 8J

08 /25 u pd ate

+5V ALW

07 /02 u pd ate

SD/MMC socket

Layout note: U4 6 c los e t o J P33 wi thin 2"

SDD ATA0_MS DATA025
SDD ATA1_MS DATA125
SDD ATA2_MS DATA225
SDD ATA3_MS DATA325
MMC _D42 5
MMC _D52 5
MMC _D62 5
MMC _D72 5

@

1 2

C6 30
22P _0402_5 0V8J

SDP WR0_ MSPW R_XD PWR25

R5 65

1 2

SD_ MMC_C MD2 5

SDC LK_M MCCLK25

10_0 201_5%@

1

IN

NC

4

OUT

NC

+3VS

4.7K _0201 _5%@

LPC _LFRA ME#1 2,22, 30

R3 67 4.7K _0402_5 %

1 2

CLK _PCI_TPM15

1 2

C5 801 0P_0 402_50V8K @

PM_ CLKR UN#14 ,25,30

+3VS

12

R6 24

12

R6 26

0_02 01_5%@

07 /02 u pd ate

SDD ATA0_M SDATA0

SDD ATA1_M SDATA1

SDD ATA2_M SDATA2
SDD ATA3_M SDATA3

MMC _D4
MMC _D5
MMC _D6
MMC _D7

SDC LK_M MCCLK

SD_ MMC_ CMD

SDP WR0_ MSPW R_XD PWR

LPC _LAD012, 22,30
LPC _LAD112, 22,30
LPC _LAD212, 22,30
LPC _LAD312, 22,30

TPM_XTALI

12

R6 18
10M _0402_5%

TPM_XTALO

SI RQ12, 22,25 ,30

@

1 2

R6 21 10_0 201_5%

7
8
9

1
10
11
12
13

5

2

+3VS

0.1U _0402 _16V4Z
C6 31

1

2

C5 74

0.1U _0402 _16V4Z

C5 73

0.1U _0402 _16V4Z

1

1

2

2

LPC _LAD0
LPC _LAD1
LPC _LAD2
LPC _LAD3
LPC _LFR AME#
PLT_ RST#
LP C_PD #
SI RQ
CLK _PCI_T PM

TPM_XTALO

TPM_XTALI

JP3 3

D0
D1
D2
D3
D4
D5
D6
D7

CLK

CMD

TAI _PSD BT0- 16GNBS7 N14N0_15P

CO NN@

U4 6

3
4

2

RT9 701-GB SOT23 5P

VIN
VIN/CE

GND

VOUT
VOUT

VDD

VSS2
VSS1
VSS3
VSS4

26
23
20
17
22
16
28
27
21

15

7

14

13

WP

CD

1
5

C5 75

0.1U _0402 _16V4Z

1

2

24

U3 4

LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
LPCPD#
SERIRQ
LCLK

SL B 9 635

SL B 9 635 TT 1 .2

SL B 9 635S L B 9 63 5

CLKRUN#

PP

XTALO

XTALI/32K IN

25

4

14

S D_CAR D_DE T#

15

6
3
16
17

40mil

1U_0 402_6 .3V4Z

12

C6 32

1

2

+3VS

+3V ALW

5

10

19

VSB

VDD

VDD

VDD

GPIO

GPIO2

TT 1.2

TT 1.2 TT 1.2

TEST1

TESTB1/BADD

NC
NC
NC

GND

GND

GND

GND

SLB 9635 T T 1.2_TSS OP28

4

11

18

100P _0402_ 50V8J

1

C4 14

2

+SD _MMC _3VCC

10U_ 0805_ 10V4Z

R5 66

150K _0402_5 %

1

2

C6 33

C5 76

0.1U _0402 _16V4Z

1

2

TPM_G PIO

6

TPM_G PIO2

2

Base I/O Address
0 = 02Eh
1 = 04Eh*

8
9

3
12
1

SD _WP 2 5
SD _CAR D_DET # 25

R6 22

0_02 01_5%

1 2

T109 P AD
T110 P AD

12

4.7K _0201 _5%

1 2

R6 23

4.7K _0201_5 %

+SD _MMC _3VCC

R5 63

150K _0402_5 %

1

2

C4 13

+3VS

12

R6 19

@

4.7U _0603 _6.3V6K

0.1U _0402 _16V4Z

Near to JP33

1

2

C4 12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2010/12/31

Compal Secret Data

Deciphered Date

4

Title

Size D ocum ent N umber R ev

Da te: She et o f

Compal Electronics, Inc.

TCG/BIOS ROM/PS2/SW LPC DEBUG

LA -52 51P

5

31 47T uesda y, J anuar y 05 , 201 0

0. 9

1

1.5V _POK39

+5VS

+3VS

+1.0 5VS

+3VM

+1.05V M

M_P WROK14

SLP _S3#14,23 ,29,3 0,33 ,35,37 ,38

+0.75 VS

1 2

R6 50 3.3K _0201_ 5%

1 2

R6 53 49.9 K_0402 _1%

1 2

R6 54 16.2 K_0402 _1%

R6 70

1 2

3.3K _0201 _5%

A A

GFX VR_P WRGD42

B B

C C

1.05 VM_LAN _POK3 9

PM_SL P_M#14, 30,33

2

1 2

R6 40 3.3K _0201_ 5%

1 2

R6 41 76.8 K_040 2_1%

1 2

R6 44 11.5 K_0402 _1%

1 2

R6 46 3.3K _0201_ 5%

CH75 1H-4 0PT_S OD323-2

1 2

R6 47 3.3K _0201_ 5%

CH75 1H-4 0PT_S OD323-2

@

12

R6 58

56.2 K_040 2_1%

1.8V S_POK38

2VR EF_51 125

R6 65 3.3K _0201_5 %

1 2

R6 67 46.4 K_040 2_1%

1 2

R6 68 14.7 K_040 2_1%

1 2

D4 2

1 2

1N41 48WS -7-F _SOD323- 2

D4 0

D4 1

3300 P_0402_ 25V7K

1

C5 85

2

+1.5V S

2VR EF_51 125

R6 72

86.6 K_040 2_1%

2VR EF_51 125

21

21

1

C5 84

3300 P_0402_ 25V7K

2

3.3K _0201 _1%

1 2

R6 55

11.5 K_04 02_1%

1 2

R6 56

78.7 K_04 02_1%~D

R6 61

41.2 K_040 2_1%

1 2

71.5 K_04 02_1%

12

R6 42 10K _0201_5%

12

R6 59

12

R6 62

R6 66 10K_ 0201_5%

12

C5 88

3300 P_0402_ 50V7K

3

1 2

2VR EF_3 93

1 2

R6 43 34.8 K_04 02_1%

1 2

R6 45 49.9 K_04 02_1%

1 2

R6 51 10K _0201_5%

2VR EF_39 3

10K _0201_5%

R6 60

1 2

2VR EF_39 3

1

C5 86

2

3300 P_0402_ 25V7K

1

C5 87
1000 P_04 02_25V8J

2

12

D4 3

2 1

CH75 1H-4 0PT_S OD323-2

1 2

1M_ 0201_1%

+5V ALW

3

+

2

-

1

C5 83
1000 P_0402_ 50V7K

2

1 2

1M_ 0201_1%

+5V ALW

5

+

6

2VR EF_3 93

-

1 2

1M_ 0201_1%

+5V ALW

3

+

2

-

R6 63 1M_ 0201_1%

+5V ALW

5

+

6

-

R6 71 1M_0 201_1%

1 2

C5 89 0.04 7U_04 02_16V7K

R6 38

8

U3 7A

P

O

G

LM3 93DG_SO 8

4

R6 49

8

U3 7B

P

O

G

LM3 93DG_SO 8

4

R6 57

8

U3 9A

P

O

G

LM3 93DG_SO 8

4

12

8

U3 9B

P

O

G

LM3 93DG_SO 8

4

1 2

4

+3VS

12

R6 39

10K _0201_5%

J1

1 2

1

SHO RT P ADS

VCC P_POK37

7

1

+3V ALW

1 2

7

12

MC7 4VHC1 G08D FT2G_S C70-5

R6 64

3.3K _0201 _5%

M_P WROK

R6 69
1K_ 0201_5%

M_P WROK 14

5

VC CP_E N 37

+3V ALW

5

U3 8

1

IN1

VCC

OUT

2

IN2

GND

3

4/2 3 C ancel H16 f or
M/ E PC B ed ge
mo di fy.

1/4 Ca ncel H17 fo r
M/E modif y.

6

07 /09 u pda te fo r I NTEL S3 le aka ge issue.

SLP _S3#14,23 ,29,3 0,33 ,35,37 ,38

4

R6

0_04 02_5%@

12

R6 48

4.99 K_04 02_1%

12

R6 52

2.49 K_04 02_1%

12

PW R_G D 30

VTT PWRG OOD 4

12

R4

8.2K _0402 _5%

+3V ALW

5

1

IN1

VCC

OUT

2

IN2

GND

3

4/ 9 upda te fo r M /E , C hange
H3 H_3 P3- ->H_3P0, H10
H_2 P5- ->H _2P3

U7 7

4

MC7 4VHC1 G08D FT2G_S C70-5

H1 0
HOL EA

1

H2 4
HOL EA

1

H2 3
HOL EA

1

H1 4
HOL EA

1

H3
HOL EA

1

H2 5
HOL EA

1

H2 2
HOL EA

1

VC CP_1. 5VSP WRG D 4

7

10/ 19 Del ete H1 3 (H_3P 0);
ch ang e H2 fro m H_4P 7 to
H_4 P4; H2 8 fro m H_4 P9 to
H_4 P8.

11 /13 Ch ange H2 fro m
H_4 P4 to H_ 4P7 ; H2 8 fro m
H_4 P8 to H_4 P9.

7/1 5 u pdate fo r
M/ E, de l H31
8/1 8 u pdate fo r
M/ E, ad d bac k H 31

4/8 u pda te fo r
M/ E, d el H6

H4

H5

HOL EA

HOL EA

1

1

H8
HOL EA

1

H2
HOL EA

H3 1
HOL EA

1

8

H2 8
HOL EA

1

1

H1
HOL EA

1

H1 1
HOL EA

1

H2 6
HOL EA

1

08 /28 u pd ate

H3 0
HOL EA

1

H1 2
HOL EA

1

H2 0
HOL EA

1

H7
HOL EA

1

H9
HOL EA

1

H2 1
HOL EA

1

H2 9
HOL EA

1

FM3

FM2

FM1

1

D D

1

FM4

1

1

ZZ Z1

PCB-MB

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

3

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

2008/09/15 2010/12/31

Compal Secret Data

Deciphered Date

6

Title

Size D ocum ent N umber Re v

Da te: She et o f

7

Compal Electronics, Inc.

POK CKT

LA -52 51P

32 47T uesd ay, J anua ry 05 , 20 10

8

0. 9

1

2

3

4

5

SI7 326DN -T1-E3_P AK1212-8

U4 0

C5 94

0.1U _0402 _16V4Z

C5 93

SLP _S3

10U_ 0805_ 10V4Z

1

2

SLP _S3

1

2

R6 78
330K _0402_5 %

2

ADP _PRE S30,3 5

1

C6 11
10U_ 0805_ 10V4Z

2

+1.05 VS

12

R6 87
470_ 0201_5%

3

Q47B

5

2N70 02DW H 2N SOT3 63-6

4

+1.5 VS

12

R6 89
470_ 0201_5%

3

Q48B

5

2N70 02DW H 2N SOT3 63-6

4

R6 76

1 2

0_04 02_5%

RU N ON

B+

12

1

C5 97

2

10U_ 0805_ 10V4Z

12

J2
SHO RT P ADS

61

Q45A

2N70 02DW H 2N SOT3 63-6

SI7 326DN -T1-E3_P AK1212-8

U4 3

RU N ON

1

A A

B B

C C

D D

+1.0 5VS+1.0 5VM_LAN

1
2
35

4

C5 95

SI7 326DN -T1-E3_P AK1212-8

U4 1

12

R6 79
820K _0402_5%

3

Q45B

5

2N70 02DW H 2N SOT3 63-6

4

1
2
35

4

SLP _S3

SLP _S3SLP _S3

05/ 06 up dat e to in stal l C3 9
(33 0U_ 2V_ B2_ R15M) by HP
req ues t.

0.1U _0402 _16V4Z

C5 96

10U_ 0805_ 10V4Z

1

1

2

2

+3VS+ 3VALW

1
2
35

C5 98

4

RU N ON

12

R6 80
470_ 0402_5%

1

C6 08

0.01 U_040 2_16V7K

2

+5VS+ 5VALW

0.1U _0402 _16V4Z

C6 09

1

2

+3VS

12

R6 88
470_ 0201_5%

61

Q47 A
2N70 02DW H 2N SOT3 63-6

2

+5VS

12

R6 90
470_ 0201_5%

61

Q48 A
2N70 02DW H 2N SOT3 63-6

2

1

C3 9

+

330U _B2_2V M_R15M

2

0.1U _0402 _16V4Z

10U_ 0805_ 10V4Z

C5 99

1

1

2

2

1

C6 10
10U_ 0805_ 10V4Z

2

PM_ SLP_LAN #14,30, 39

ADP _PRE S30,3 5

PM_SL P_M#14, 30,32

SLP _S3

5

09 /10 u pd ate .

SLP _S3

2

G

+1.0 5VM_LA N +1.05V M

C6 00

10U_ 0805_ 10V4Z

1

2

R6 82 330K _0402_5%

B+

PM_SL P_M SLP _S3

PM_SL P_M#

+1.8V S

12

R6 91
470_ 0201_5%

3

Q49B

2N70 02DW H 2N SOT3 63-6

4

+0.7 5VS

12

R6 93

22_0 402_5%

13

D

Q53

S

2N70 02_SOT2 3-3

2

+3V ALW +3VM

C5 92

0.1U _0402 _16V4Z

12

1

2

C6 01

1

2

1 2

5

05 /0 6 Upda te R69 3 and Q5 3 b ecome no
in stal l t o avoid th e +0. 75V S lea kag e f rom
DDR sl ot on S3 M od e f or po wer sa vin g.

07 /09 Up date

R6 73
47K _0402_5%

61

Q50A
2N70 02DW H 2N SOT3 63-6

2

SI7 326DN -T1-E3_P AK1212-8

U4 2

0.1U _0402 _16V4Z

R6 83

1 2

820K _0402_5 %

3

Q44B

2N70 02DW H 2N SOT3 63-6

4

+3VL

12

R6 86
100K _0201_5 %

3

Q50B

5

2N70 02DW H 2N SOT3 63-6

4

SLP _S4

R6 77

1 2

4.7K _0402 _5%

1
2
35

4

Q44A
2N70 02DW H 2N SOT3 63-6

6 1

+1.5V

2

Q39

SI2 301CD S-T1-G E3 1P SO T23-3

2

12

R6 92
470_ 0201_5%

61

Q49A
2N70 02DW H 2N SOT3 63-6

LA N_EN

C6 02

1

2

PM_SL P_M

D

S

13

G

2

05/ 06 up dat e to in stal l C4 0
(33 0U_ 2V_ B2_ R15M) by HP
req ues t.

C6 03

10U_ 0805_ 10V4Z

0.1U _0402 _16V4Z

1

2

C5 90

0.1U _0402 _16V4Z

1

1

C5 91
10U_ 0805_ 10V4Z

2

2

1

C4 0

+

330U _B2_2V M_R15M

2

+3VL

12

R6 85
100K _0201_5%

3

Q43B

SLP _S3#14,2 3,29, 30,32 ,35,3 7,38 SLP_S4#1 4,24, 29,39

07 /01 u pd ate

SLP _S3 SLP _S4 SLP _S3

3

5

2N70 02DW H 2N SOT3 63-6

4

+V CCP +GF X_CORE +1.5 VS_C PU_V DDQ

12

R6 99
470_ 0201_5%

3

Q41B

5

2N70 02DW H 2N SOT3 63-6

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2N70 02DW H 2N SOT3 63-6

07 /08 u pda te fo r I NTEL S3 le aka ge issue.

+1.5 V +1.5 VS_C PU_V DDQ

SI7 326DN -T1-E3_P AK1212-8

C6 24

0.1U _0402 _16V4Z

1

2

RU N ON

2008/09/15 2010/12/31

+1.05 VM

Q40A

2

U4 5

4

12

1

R1 104

0_04 02_5%

2

SLP _S4

12

R7 02
470_ 0201_5%

61

Q41A

2

2N70 02DW H 2N SOT3 63-6

Compal Secret Data

12

R6 74
470_ 0201_5%

61

1
2
35

C6 25

1

2

C5 05

0.01 U_040 2_16V7K@

07 /17 u pd ate

SLP _S4

Deciphered Date

4

LA N_ENPM_SLP_M

0.1U _0402 _16V4Z

+3VM

12

R6 75
470_ 0201_5%

3

Q40B

5

2N70 02DW H 2N SOT3 63-6

4

Q42

AO4 430L 1N S OIC-8

8
7

10U_ 0805_ 10V4K

C6 05

1

2

5

5

0.1U _0402 _10V6K

R6 81

1 2

0_04 02_5%

12

R1 103

220_ 0402_5%

3

Q52B

2N70 02DW H 2N SOT3 63-6

4

2

+3VL

12

R6 84
100K _0201_5 %

61

C6 04

1

2

2N70 02DW H 2N SOT3 63-6
Q43A

07 /08 u pda te fo r I NTEL S3 le aka ge issue.

+1.5 VS+1 .5V

1
2
36

4

RU N ON

Add C626, C664 c lose to JDIMA 1;

L

C65 6,C 657 cl ose to JDIM B1.

+1.5 V +1.5 VS_C PU_V DDQ

C6 26 0.1U _0402 _16V4Z

1 2

C6 64 0.1U _0402 _16V4Z

1 2

C6 56 0.1U _0402 _16V4Z

1 2

C6 57 0.1U _0402 _16V4Z

1 2

07 /10 u pda te fo r I NTEL S3 le aka ge issue.

Add C666, C667,C 671 clo se to JP11 .

L

+5VS

C6 66 0.1U _0402 _16V4Z

1 2

C6 67 0.1U _0402 _16V4Z

1 2

C6 71 0.1U _0402 _16V4Z

1 2

C6 07

10U_ 0805_ 10V4K

C6 06

0.1U _0402 _10V6K

1

1

2

2

1/5 u pda te fo r E MI PC I I ssue.

07 /1 7 u pdate B OM.

Title

Size D ocum ent N umber R ev

Da te: She et o f

Compal Electronics, Inc.

DC/DC Circuits

LA -52 51P

5

33 47T uesda y, J anuar y 05 , 201 0

0. 9

1

2

3

4

PJP1

4

V-

5

V-

6

A A

PJP2

@SU YIN_2002 75MR0 05G15U ZL_5P

B B

GND_1

7

GND_2

8

GND_3

9

GND_4

@FO X_JPD1 131-DB371-7F

1

1

2

2

3

3

4

4

5

5

6

GND

7

GND

PJSOT24 CW_SOT323 -3

3

ID

1

V+

V+

PD6

THM _MAIN#30

A DPIN

2

3

2

PD1

1

@PJSOT2 4C_SOT23

2

3

2

3

1

PD7

1

PJSOT24 CW_SOT323 -3

PR4

100K_04 02_5%

+3VL

12

ADP _SIGNA L 29,4 1

ADPIN

12

12

PC 1

PC2
1000P_0 402_50V7K

100 P_0402_50V8J

12

12

PR 3

PC 7

1K_04 02_5%

100 P_0402_50V8J

PD5
BAV99W T1G_SC70-3

1

PL1

HCB 2012KF-121 T50_0805

1 2

1 2

PL3

HCB 2012KF-121 T50_0805

100P_04 02_50V8J

12

12

PC 8

PR 5

100_0 402_5%

100 P_0402_50V8J

PD3

1

BAV99W T1G_SC70-3

PC3

12

PR 6

100_0 402_5%

PD4

1

BAV99W T1G_SC70-3

VIN

12

PC 4

1000P _0402_50V7K

VMB BATT

12

PC9
100P_04 02_50V8J

12

12

PL2

HCB 2012KF-121 T50_0805

1 2

1 2

PL4

12

HCB 2012KF-121 T50_0805

PC5
1000P_0 402_50V7K

AB1A_DA TA 30

AB1 A_CLK 30

PR1
@15K_04 02_5%

12

PC6

0.01 U_0402_5 0V4Z

BATT

B+_DEBUG

Vin

PD1 2

1SS 355_SOD323-2

PD2

CH7 51H_SO D323-2

PD8
RLZ 27V

2 1

PR3 7

0_0402_ 5%

1 2

B++ 51125_PWR

12

PD2 2

1SS 355_SOD323-2

12

PR2 3

100_080 5_5%

12

B+_ DEBUG

1 2

0.1U _0603_50V7 K

PC1 5

12

ADP_SIGNAL

+3VL

2

3

2

3

2

3

+3VL

PH1 under CPU botten side :

CPU thermal protection at 93 +-3 degree C
(Need to be checked)

C C

Clos e to CPU

PC1 2

0.1U _0603_25V7 K

D D

0.9

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2VR EF_51125

12

PH1
100 K_0603_1%_T SM1A104F4361 RZ

PR12

53.6 K_0603_1%

1 2

12

12

PR16

19.1 K_0402_1%

2008/09/15 2010/12/31

1 2

2VR EF_51125

PR1 3

75K_040 2_1%

150K_04 02_1%

Compal Secret Data

Deciphered Date

3

PR17

12

1

2

3

12

PC1 3

1000P_0 402_50V7K

PR8

470K_04 02_1%

1 2

VL

PU1

IN+

GND

IN-

LMV 331IDCK RG4_SC70 -5

VCC+

OUT

5

4

VL

PR10
100K_04 02_5%

1 2

13

D

PQ1

2

G

SSM 3K7002FU _SC70-3

S

Title

Size Do cum ent Num ber R ev

Cu stom

Da te: Sheet of

Compal Electronics, Inc.

DC-IN/ BATTERY CONN

LA-4902P

4

EN0 36

34 47T uesd ay, J anuary 05, 201 0

A

VI N

8
7

5

3

+

2

-

12

PR1 40

23. 7K_0402_1%

PR1 18

255K_04 02_1%

8

P

+

O

-

G

PU1 03B
LM393DG _SO8

4

PQ102
AO4 407AL 1P S O8

4

12

13

D

S

VL

PR1 38

1 2

100K_04 02_5%

PR139

1 2

1M_0402 _5%

8

P

1

O

G

PU1 05A
LM393DG _SO8

4

BAT_PW M_OUT30

+3VL

12

7

PR105
15K_040 2_5%

PQ101
AO4407L _SO8

1
2
3 6

8
7

5

4

1 1

1 2

PC1 01

0.1U _0603_50V7 K

1 2

PR1 01

P2

P2BATT

PR1 36

24.3 K_0603_1%

12

PR1 11
150K_04 02_5%

PR1 35

100K_04 02_1%

1 2

1 2

PR1 37

1 2

200K_04 02_5%

ADP _EN#41

1 2

100K_04 02_1%

2 2

12

PR1 19
200K_04 02_1%

12

PR123

41.2 K_0402_1%

3 3

5

6

2VR EF_51125

P4

1
2
36

1 2

PR1 03

47K_040 2_5%

2

G

PQ104
SSM 3K7002FU _SC70-3

422K_04 02_1%

1U_ 0603_6.3V6M

AC Detector

PR1 20
22K_040 2_5%

High 11.85
Low 10.55

ADP_PRES 30,33

1 2

PR1 14

PC116

+3VL

1 2

56K_040 2_1%

12

PR1 04

SLP_S3#14,23,29,30,32,33,37,38

1 2

PC1 11
1U_ 0603_6.3V6M

12

PR1 13
453K_04 02_1%

12

PR1 15
1M_0402 _1%

22.6 K_0402_1%

IADAPT4 1

12

PC1 07

0.01 U_0402_16V 7K

PR1 09

0_0402_ 5%

1 2

BQ2 4740VREF

+3VL

PR1 16

100P_04 02_50V8J

B

B+

PR1 02

0.01 _2512_1%

1

2

ACD ET

AC P

1U_ 0603_6.3V6M

12

+3VL

7

LPREF

8

IADSLP

9

AGND

10

VREF

11

VDAC

12

VADJ

13

EXTPWR

14

ISYNSET

12

IADAPT

15

IADAP T

12

PC1 19

PC1 08

0.1 U_0603_50V 7K

4

5

6

LPMD

ACSET

ACDET

PU1 01
BQ2 4740RH DR_QFN28_ 5X5

BAT

SRSET

SRN

17

16

18

BATT

12

PR1 24
147K_04 02_1%

PC1 05

1 2

3

2

ACP

ACN

SRP

CELLS

19

20

PR1 22

210K_04 02_1%

12

PC1 22
1U_ 0603_6.3V6M

4

3

AC N

12

PL101

HCB 2012KF-121 T50_0805

1 2

PC106
@0.1 U_0603_25V 7K

CH GEN#

1

29

TP

CHGEN

28

PVCC

27

BTST

26

HIDRV

25

PH

24

REGN

23

LODRV

22

PGND

DPMDET

21

SRSET 41

12

CH GCTRL 30

PC109
1U_0805 _25V6K

BST _CHG

DH _CHG

LX_CHG

RE GNVA DJ

DL _CHG

C

12

PC1 02

4.7 U_0805_25V 6-K

1 2

1 2

PR1 21

0_0402_ 5%

1 2

PR1 45

0_0402_ 5%

PD1 01

RLS 4148_LL34-2

PC1 18

12

1U_ 0603_10V6K

12

12

PC1 03

4.7 U_0805_25V 6-K

PR1 10
10_0805 _1%

1 2

PC1 10

0.1U _0402_10V7 K

1 2

12

PR1 17
100K_04 02_5%

1 2

PC1 20

0.1U _0603_50V7 K

PC1 04

4.7 U_0805_25V 6-K

PQ106

AON 7406L

CEL LS 30

12

P4P2

CHG _B+

CHG _B+

PQ105
SIS41 2DN-T 1_POWER PAK8-5

3 5

241

10U H_MMD-10DZ -100M-X1_6A_20 %

1 2

PR1 41
@4.7 _1206_5%

1 2
12

PC1 26

@680P_0 603_50V8J

3 5

241

12

PC1 21
@0.1 U_0603_25V 7K

PQ103

AO4 407AL 1P S O8

1
2
3 6

4

PR106
0_0402_ 5%

1 2

PL102

12

12

PC1 12 4. 7U_0805 _25V6-K

8
7

5

P2

PC1 13 4. 7U_0805 _25V6-K

12

PC1 29 4. 7U_0805 _25V6-K

D

PR1 12

0.01 _1206_1%

1 2

1 2

PC1 17

0.1U _0402_10V7 K

PC1 14 4. 7U_0805 _25V6-K

BATT

12

12

12

PC1 15 4. 7U_0805 _25V6-K

PC1 28 4. 7U_0805 _25V6-K

1 2

PR1 25

3

2

VL

8

P

+

-

G

PU1 03A
LM393DG _SO8

4

604K_04 02_1%

12

PC1 24

0.1U _0402_10V7 K

1

O

VI N

P2

12

12

PR1 28

PR1 27

76. 8K_0402_1%
@76 .8K_0402_1%

12

PR1 31

10K _0603_0.1%

2VR EF_51125

4 4

Charge Detector
High 17.588

+3VL

Low 17.292

12

PR1 32
22K_040 2_5%

AC_ADP_PRES 30

CH GCTRL

PR1 30

1K_0402 _5%

1 2

1SS 355_SOD323-2

0.04 7U_0402_16 V7K

Note: X7R type

PD1 02

PC1 23

12

2

G

12

PR1 34

470K_04 02_5%

12

PR1 26
100K_04 02_5%

1 2

PR1 29
220K_04 02_5%

1 2

CH GEN#

13

D

PQ107

S

SSM 3K7002FU _SC70-3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2008/09/15 2010/12/31

+3VL+3VL

PQ108

E

3

B

2

1

MMBT3906H_S OT23-3

C

47K_040 2_5%

1 2

PR1 46

ACD ET

12

PR133
300K_04 02_5%

Compal Secret Data

Deciphered Date

C

IADAP T

PR1 42

11K_040 2_1%

1 2

PC1 27

1U_ 0603_6.3V6M

OUT

+5VALW

5

V+

4

PMC 3 0

PU1 04

1

12

+IN

2

V-

3

-IN

LMV321AS5X_SOT23-5

1 2

12

PR1 44

49.9 K_0402_1%

Title

Size Do cum ent Num ber R ev

Da te: Sheet of

PR1 43

39.2 K_0402_1%

Compal Electronics, Inc.

Charger

LA-4902P

D

35 47T uesd ay, J anuary 05, 201 0

0.9

A

B

C

D

E

2VREF_51125

12

PC3 02

1U_ 0603_10V6K

1 1

PR3 01

13.7 K_0402_1%

+3VALWP

B+

PL301

HCB 2012KF-121 T50_0805

1 2

2200P_0 402_50V7K

2 2

PC3 01

+3VALWP

150 U 6.3V M B2 LESR 45M

3 3

2N7 002KDW H-2N_SOT3 63-6

4 4

PC3 10

ENT RIP1

61

PQ305A

SSM 3K7002FU _SC70-3

B++

12

4.7U H 20% FDVE06 30-H-4 R7M=P3 5.5A

1

+

2

2

12

12

PC3 17

PC3 03

0.1 U_0402_25V 6

4.7 U_0805_25V 6-K

SIS41 2DN-T 1_POWER PAK8-5

PL302

12

PR3 11

2.2_ 1206_5%

PC3 12

1000P_0 603_50V7K

5

100K_04 02_5%

1 2

13

D

2

G

S

PQ307

PQ301

12

AON 7406L

12

ENT RIP2

34

PQ305B
2N7 002KDW H-2N_SOT 363-6

PR3 16

PR3 17

330K_04 02_5%

241

PQ304

241

12

12

PD3 05
1SS 355_SOD323-2

12

PD3 01
1SS 355_SOD323-2

3 5

3 5

VL

12

PR3 18
100K_04 02_5%

2.2U _0805_10V6 K

UG1 _3V

PR3 09

0_0402_ 5%

1 2

KBC_PWR_ON 30

DEBUG_KBCRST 22,31

VCC1_PWRGD 30, 41

12

PC3 07

1 2

PC3 08

0.1U _0402_10V 7K

VL

12

PC3 16
10U _0805_10V6K

+5VALW P

+3VALW P

+3VLP

PR3 07

1 2

0_0402_ 5%

PJP301

1 2

PA D-OPE N 4x4m
PJP303

1 2

PA D-OPE N 4x4m

EN0 34

A

B

1 2

PR3 03

20K_040 2_1%

1 2

PR3 05

110K_04 02_1%

1 2

BST_3V

UG_ 3V UG_ 5V

LX_3V

LG_3V

PR3 15

@620K_0 402_5%

2 1

2 1

2 1

ENT RIP2

3

4

5

6

25

P PAD

VFB2

VREF

TONSEL

ENTRIP2

7

VO2

8

VREG3

9

VBST2

10

DRVH2

11

LL2

12

DRVL2

GND

VIN

SKIPSEL

EN0

15

16

14

13

12

12

2VREF_51125

PC3 14

0.1U _0603_50V7 K

(4.5A, 180mil s ,Via NO.= 9)

+5VALW

(3A,12 0mils ,Via NO.= 6)

+3VALW

PJP302

PA D-OPE N 2x2m

PJP304

PA D-OPE N 2x2m

PJP305

PA D-OPE N 2x2m

+VREG3_51125+3VLP

VL+5VLP

+3VL+3VEXTLP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/09/15 2010/12/31

C

PR3 02

30.9 K_0402_1%

1 2

PR3 04

20K_040 2_1%

1 2

PR3 06

100K_04 02_1%

ENT RIP1

1 2

1

2

VFB1

ENTRIP1

24

VO1

23

PGOOD

22

VBST1

21

DRVH1

20

LL1

19

DRVL1

VREG5

VCLK

PU3 01

17

18

TPS 51125RGER_ QFN24_4X4

+5VLP

1 2

12

PC3 15
22U _0805_6.3V6M

PR3 19

@0_040 2_5%

1U_ 0603_10V6K

PR3 08

0_0402_ 5%

BST_5V

1 2

LX_5V

LG_5V

+3VL

12

PR3 14
@100K_0 402_5%

51125_P WR

B++

P2

PR3 20

255K_04 02_1%

12

PC3 21

PR3 21

Compal Secret Data

Deciphered Date

+5VALWP

12

PC3 18

0.1 U_0402_25V 6

PC3 09

0.1U _0402_10V7 K

1 2

RPG OOD 14

DEBUG_KBCRST22,31

12

12

11. 5K_0402_1%

12

12

PC3 05

PC3 04

2200P _0402_50V7K

PR3 10

0_0402_ 5%

1 2

PC3 19

10U _0805_10V6K

PU3 02

1

+IN

2

V-

3

-IN

LMV321AS5X_SOT23-5

D

B++

12

PC3 06

4.7 U_0805_25V 6-K

4.7 U_0805_25V 6-K

3 5

3 5

PQ303

IRFH3 707TR PBF_P QFN8-3

+5VLP

12

12

PR3 25

220K_ 0402_5%

12

+5VLP

470K_04 02_5%

5

V+

PR3 31

4

1 2

OUT

680K_04 02_5%

PQ302
SIS41 2DN-T 1_POWER PAK8-5

241

241

PL303

4.7U H 20% FDVE06 30-H-4 R7M=P3 5.5A

1 2

12

PR3 12

2.2_ 1206_5%

12

PC3 13
1000P_0 603_50V7K

1

+

PC3 11

2

150 U 6.3V M B2 LESR 45M

+5VALWP

+3VEXTLP

PU3 03

1

VIN

GND

EN

VOUT

FB

2

3

APL5317

PR3 26

PR3 24

16.5 K_0402_1%

PD3 04

12

1SS 355_SOD323-2

Title

Size Do cum ent Num ber R ev

Cu stom

Da te: Sheet of

Compal Electronics, Inc.

12

PR3 22

12

64.9 K_0402_1%

12

PR3 23

20K_040 2_1%

5

4

12

3.3VALWP/5VALWP

LA-4902P

E

PC3 20

2.2U _0805_10V6 K

36 47T uesd ay, J anuary 05, 201 0

0.9

A

B

C

D

1 1

2 2

B+

PL401

HCB 2012KF-121 T50_0805

1 2

12

PC4 16

SLP_S3#14,23,29,30,32,33,35,38

VCCP_EN32

VCC P_B+

12

PC4 01

0.1 U_0402_25V 6

+62 69_VCC

2.2U _0805_10V6 K

12

PC4 02

4.7 U_0805_25V 6-K

2200P _0402_50V7K

12

12

PR4 27

10K_040 2_5%

PC4 04

PC4 03

4.7 U_0805_25V 6-K

4.7 U_0805_25V 6-K

VCC P_POK32

1

PC4 07

1 2

@0_040 2_5%

1 2

0_0402_ 5%

12

PR4 06

PR4 28

PR4 05

0_0402_ 5%

1 2

22P_040 2_50V8J

2

3

4

12

PC4 11
@10K_04 02_5%

12

PC4 14

+3VS

12

PR4 01

@10K_04 02_5%

17

PU4 01

VIN

VCC

FCCM

EN

12

PR4 09

22. 6K_0402_1%

12

+VC CP

12

LX_ VCCP

16

15UG14

GND

PHASE

PGOOD

COMP5FB6FSET

FB _VCC P

PR4 10

49. 9K_0402_1%

DH _VC CP

BST _VCCP

7

12

1 2

PR4 02

0_0603_ 5%

+5VALW

12

PR4 03

0_0402_ 5%

13

BOOT

12

PVCC

DL _VCCP

11

LG

10

PGND

SE_ VCCP

9

ISEN

VO

8

ISL62 69ACR Z-T_QF N16

+VC CP

12

PC4 13

0.0 1U_0402_1 6V7K

0.22 U_0603_10V 7K

PR4 04

2.2_ 0603_5%

1 2

1 2

1 2

8.06 K_0402_1%

1 2

PR4 17

0_0603_ 5%

1 2

PC4 05

+62 69_VCC

PC4 06

2.2U _0805_10V 6K

PR4 07

578

PQ401

DH _VCC P1

AO4474L _SO8

3 6

241

PQ402

3 5

241

AO N6718 L 1N D FN

PL402

0.47 U 20% FDVE06 30-H-R 47M=P3 17.7 A

1 2

12

PR4 08

2.2_ 1206_5%

PC4 12

1 2

1000P_0 603_50V7K

(18A,7 20mils ,Via NO.= 36)

+VCCP

1

1

+

PC4 08

2

330 U_V_2VM_R6M

1

+

+

PC4 09

2

PC4 10

2

330 U_V_2VM_R6M

330 U_V_2VM_R6M

3 3

PC4 15

6800P_ 0603_50V7K

1 2

12

PR4 12

1.96 K_0402_1%

PR4 11

1.5K_ 0402_1%

12

1 2

1 2

PC4 17

@0. 1U_0402_2 5V6

1 2

PR4 15
0_0402_ 5%

PR4 13
10_0402 _5%

PR4 14
0_0402_ 5%

+VC CP

VTT_SENSE 7

VSS_SENSE_VTT 7

Need t o clos e CPU chipset

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2008/09/15 2010/12/31

Compal Secret Data

Deciphered Date

C

Title

Size Do cum ent Num ber R ev

Da te: Sheet of

Compal Electronics, Inc.

1.05V_VCCP

LA-4902P

D

37 47T uesd ay, J anuary 05, 201 0

0.9

A

12

PJP604

PA D-OPE N 3x3m

PJP605

PA D-OPE N 3x3m

+5VALW

5

+1.5V

1 1

+1.5 VS_CP U_VDDQ

To re sol ve +0 .7 5V S t o +1 .5V_ CPU_ VDDQ timi ng i ssue

PR6 04

20K_040 2_5%

SLP_S3#14,23,29,30,32,33,35,37

2 2

1 2

PD6 01

1SS 355_SOD323-2

1 2

.1U_ 0402_16V7K

PC6 06

B

12

12

12

PR602

10K_040 2_5%

2N7 002KDW H-2N_SOT3 63-6

34

+0.75VSP

PQ601A

2

PQ601B
2N7 002KDW H-2N_SOT 363-6

1 2

12

12

PC6 01

10U _0805_6.3V6 M

61

PJP601

PA D-OPE N 3x3m

PC6 02

@10 U_0805_1 0V4Z

12

PR6 01
1K_0402 _1%

12

PR6 03
1K_0402 _1%

+0.75VS

PU6 01

VIN1VCNTL

2

GND

3

VREF

4

VOUT

G29 92F1U_SO8

6

5

NC

7

NC

8

NC

9

TP

+0.75VSP

12

12

PC6 05
10U _0805_6.3V6M

0.1 U_0402_10V 7K

PC6 04

(2A,80 mils , Via NO.= 4)

C

12

PC6 03
1U_ 0603_10V6K

D

+5VALW

Change +1.8VS VR

316K_04 02_1%

1 2

12

PC6 08

0.1U _0402_16V7 K

PC6 09

1 2

10U_0 805_10V_X5R

PR6 07

1 2

1 2

PR6 09

0_0402_ 5%

+1.8VSP

PU6 02

1

FB

2

GND

3

SW

4

IN

5

BS

MP2 121DQ-LF -Z_QFN10_3X3

PJP602

1 2

PA D-OPE N 3x3m

EN/SYNC

GND

POK

10

9

8

SW

7

IN

6

11

TP

(1.5A, 60mils ,Via NO.= 3)

+1.8VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

PR6 08

12

402K_04 02_1%

12

PC6 11

0.1 U_0402 _10v_X7R

PC6 10

10U_0 805_10V_X5R

+1.8VSP

3 3

+5VALW

4 4

A

PL601

HCB 1608KF-121 T30_0603

1 2

PR6 05

0_0402_ 5%

1 2

12

PC607
@0.1 U_0402_16V 7K

SLP_S3# 14 ,23,29 ,30,32, 33,35,37

PL602

1.2U H +-30 % 1231 AS-H-1R 2N=P3 2.9A

1 2

12

1.8VS_POK 32

2008/09/15 2010/12/31

12

PD6 02

@B340A_ SMA2

PR6 06

4.7_ 1206_5%

12

PC6 12
680P_06 03_50V7K

Compal Secret Data

Deciphered Date

PC6 13

22U _0805_6.3V6 M

C

+1.8VSP

1

1

PC6 14

2

2

22U _0805_6.3V6 M

Title

Size Do cum ent Num ber R ev

Da te: Sheet

Compal Electronics, Inc.

0.75VSP/1.8VSP

LA-4902P

D

38 47T uesd ay, J anuary 05, 201 0

0.9

o f

A

B

C

D

PR5 16

PM_SLP_LAN#1 4,30, 33

1 1

+5VALW

+5VALW

2 2

1 2

PR5 18

316_040 2_1%

PC5 20

1U_ 0603_10V6K

12

SLP_S4#14,24,2 9,33

3 3

+5VALW

+5VALW

1 2

PR5 22

316_040 2_1%

PC5 22

1U_ 0603_10V6K

0_0402_ 5%

+1.0 5VMP_LAN

+1.0 5VMP_LAN

PR5 21

0_0402_ 5%

+1.5VP

+1.5VP

12

12

PC5 19

12

@1000P_ 0402_50V7K

1 2

PR5 19 0_0402_5%

PR5 03

1 2

4.12 K_0402_1%

1 2

PC5 26

@10P_04 02_50V8J

10K_040 2_1%

12

PC5 24

12

@1000P_ 0402_50V7K

1 2

PR5 20 0_0402_5%

PR5 01

1 2

10.2 K_0603_0.1 %

1 2

PC5 25

@10P_04 02_50V8J

10K _0603_0.1%

PR5 24
255K_04 02_1%

1 2

PR504

PR5 23
255K_04 02_1%

1 2

PR502

PR5 11

0_0402_ 5%

BST_1.05 V

1 2

1

PU5 01

2

TON

3

VOUT

4

V5FILT

5

VFB

6

PGOOD

12

1

PU5 02

2

TON

3

VOUT

4

V5FILT

5

VFB

6

PGOOD

12

14TP15

VBST

EN_PSV

DRVH

LL

TRIP

V5DRV

DRVL

GND7PGND

TPS 51117R GYR_QFN 14_3.5 x3.5

8

1.05 VM_LAN_POK 32

BST_1.5V

14TP15

VBST

EN_PSV

DRVH

LL

TRIP

V5DRV

DRVL

GND7PGND

TPS 51117R GYR_QFN 14_3.5 x3.5

8

13

12

11

10

9

PR5 10

0_0402_ 5%

1 2

13

12

11

10

9

UG_ 1.05V

LX_1.05V

PR5 17

1 2

+5VALW

LG_ 1.05V

UG_ 1.5V

LX_1.5V

PR5 15

1 2

+5VALW

LG_ 1.5V

PC5 11

0.1U _0402_10V7 K

1 2

14.3 K_0402_1%

PC5 10

0.1U _0402_10V7 K

1 2

14.3 K_0402_1%

12

PC5 21

4.7U _0805_10V6 K

12

PC5 23

4.7U _0805_10V6 K

PR5 09

0_0402_ 5%

1 2

PR5 08

0_0402_ 5%

1 2

UG1 _1.05V

AON 7702L_ DFN8-5

UG1 _1.5V

AON 7702L_ DFN8-5

PQ504

PQ503

SIS41 2DN-T 1-GE3_POW ERPAK8-5

3 5

241

3 5

241

PQ501
SIS41 2DN-T 1-GE3_POW ERPAK8-5

3 5

241

3 5

241

12

PQ502

+1.0 5VMP_LAN

12

+1.05VM_ LAN_B+

12

12

PC5 05

PC5 04

0.1 U_0402_25V 6

1000P _0402_50V7K

2.2U H_PCM C063T-2R2 MN_8A_20%

12

PR5 13

2.2_ 1206_5%

12

PC5 17
1000P_0 603_50V7K

PJP501

1 2

PA D-OPE N 4x4m

1.5V_B+

12

12

PC5 02

PC5 01

0.1 U_0402_25V 6

1000P _0402_50V7K

2.2U H_PCM C063T-2R2 MN_8A_20%

12

PR5 12

2.2_ 1206_5%

12

PC5 16
1000P_0 603_50V7K

PC5 06

4.7 U_0805_25V 6-K

PL503

1 2

4.7U _0805_ 6.3V6K

PC5 08

4.7 U_0805_25V 6-K

PL502

1 2

4.7U _0805_ 6.3V6K

PL501

HCB 1608KF-121 T30_0603

1 2

12

PC5 07

4.7 U_0805_25V 6-K

12

PC5 14

+1.0 5VM_LAN

PL504

HCB 1608KF-121 T30_0603

1 2

12

PC5 09

4.7 U_0805_25V 6-K

12

PC513

B+

+1.05VMP_LAN

1

+

PC5 15

2

220 U_B2_2.5VM_ R25M

(8A,32 0mils ,Via NO.= 16)

B+

+1.5VP

1

+

PC5 12

2

330 U_2.5V_B2_ R15M

1.5V _POK 32

PJP502

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2008/09/15 2010/12/31

Compal Secret Data

Deciphered Date

C

+1.5VP

1 2

PA D-OPE N 4x4m

Title

Size Do cum ent Num ber R ev

Da te: Sheet of

(8A,32 0mils ,Via NO.= 16)

+1.5V

Compal Electronics, Inc.

1.5VP/1.05VMP

LA-4902P

D

39 47T uesd ay, J anuary 05, 201 0

0.9

8

H H

H _VID 0

H_ VID 07

H _VID 1

H_ VID 17

H _VID 2

H_ VID 27

H _VID 3

H_ VID 37

H _VID 4

H_ VID 47

H _VID 5

H_ VID 57

H _VID 6

G G

PR OC_D PRS LPVR7

F F

H_P ROCH OT#4

E E

PR2 35

8.0 6K_040 2_1%

D D

PC2 27

150 P_040 2_50V8J

PR2 38

C C

PR2 60

H_ VID 67

PG D_IN14 ,30

CLK _EN#11

VGATE1 2,14

+VC CP

PSI #7

1 2

PR2 23 147K _0402_1%

+V CCP

PC2 20 @ 56P_ 0402_50V 8

1 2

PR2 27 @4. 02K_04 02_1%

1 2

1 2

@47 0K_0 402_5%_ TSM0B47 4J4702RE

12

12

PC2 22

1 2

PC2 25

10P _0402_ 50V8J

1 2

1 2

PR2 41

412 K_0402_ 1%

S V
LL= -1.9

2.8 7K 3 .92 K

1.3 K 1.1K

PR2 09 220 _0402_5 %

1 2

PR OC_ DPRS LPVR

PR2 19

0_0 402_5%

1 2

PR2 21 @1K_ 0402_5%

12

PSI #

100 0P_040 2_50V7K

1 2

1 2

PR2 25

0_0 402_5%

PH2 02

1 2

PR2 36

562 _0402_1 %

ISE N2

ISE N1

L V
LL= -3

PR2 22 0_0 402_5%

PR2 83 1K_0 402_5%

12

1 2

PR2 24

68_ 0402_5%

22P _0402_ 50V8J

390 P_0402 _50V7K

1 2

PR2 38

2.8 7K_040 2_1%

+3V ALW

1 2

47K _0402_1 %

1 2

PC2 21

PC2 24

VSU M-

10K 1 0. 7KPR2 46

8

1 2

PR2 51 0 _0402 _5%

PR2 63 0 _0402 _5%

1 2

330 P_0402 _50V7K

100 0P_040 2_50V7K

VC CSEN SE7

B B

VSS SENSE7

A A

PR2 15

1 2

PR2 29

1 2

+5V ALW

12

0.2 2U_0 603_10V7K

PC2 36

PC2 44

PC2 47

7

PM_ PWR OK

CLK _EN#

37

38

39

40

PU2 01

1

PGOOD

2

PSI#

3

RBIAS

4

VR_TT#

5

NTC

6

VW

7

COMP

8

FB

9

ISEN3

10

ISEN2

41

AGND

@0_ 0402_5%

12

0.2 2U_0 603_10V7K

PC2 37

12

12

12

7

35

VID4

VR_ON

CLK_EN#

DPRSLPVR

ISEN111VSEN12RTN13ISUM-14ISUM+15VDD

16

12

PC2 48

330 P_0402 _50V7K

PC2 49

1 2

@12 00P_04 02_50V7K

VID031VID132VID233VID334VID536VID6

BOOT2

UGATE2

PHASE2

VSSP2

LGATE2

VCCP

PWM3

LGATE1

VSSP1

PHASE1

VIN

IMON18BOOT119UGATE1

ISL 6288 3HRZ- T_QFN40 _5X5

17

20

12

12

PC2 28

1U_ 0603_ 10V6K

82.5_0402_1%

PR250

PC2 45

0.0 1U_0 402_16V7K

PR2 60

1.3 K_0402 _1%

1 2

@10 0_0402_ 1%

1 2

PR2 65

H _VID 0

H _VID 1

H _VID 2

H _VID 3

H _VID 4

H _VID 5

H _VID 6

PR OC_ DPRS LPVR

PC2 11
1U_ 0603_ 10V6K

30
29
28
27
26
25
24
23
22
21

12

PR2 42 0 _040 2_5%

1 2

PR2 44 1 _040 2_5%

1 2

PC2 29

0.2 2U_0 603_25V 7K

6

1 2

PR2 28
0_0 402_5%

1 2

PC2 23
1U_ 0603_ 10V6K

CPU_B+

+5V ALW

10K _0402_1 %

12

0.2 2U_0 603_10V 7K

PC2 42

6

+5V ALW

PR2 46

12

PC2 43

12

PR2 66 1K_0 201_5%

12

PR2 67 1K_0 201_5%

12

PR2 68 1K_0 201_5%

12

PR2 69 @1K_ 0201_5%

12

PR2 70 @1K_ 0201_5%

12

PR2 71 1K_0 201_5%

12

PR2 72 @1K_ 0201_5%

12

PR2 73 1K_0 201_5%

12

PR2 39 0 _0402 _5%

1 2

12

12

PC2 30

VSS SENS E

VSUM +

12

PR2 52

2.6 1K_040 2_1%

0.0 22U_ 0402_16V7 K

12

12

PH2 01

PR2 62

11K _0402_1 %

VSU M-

PC2 50

0.1 U_04 02_10V7 K

+VC CP

IMV P_IMON 7

0.0 47U_ 0603_16 V7K

12

PH2 03

@10 KB_0 603_5 %_ERTJ1 VR103J

10K B_06 03_5% _ERTJ1V R103J

5

H _VID 0

H _VID 1

H _VID 2

H _VID 3

H _VID 4

H _VID 5

H _VID 6

PR OC_ DPRS LPVR

BOO ST_C PU2

UGA TE_C PU2

PHA SE_C PU2

LGA TE_C PU2

5

BOO ST_C PU1

PR2 08

0_0 603_5%

UGA TE_C PU1

PHA SE_C PU1

LGA TE_C PU1

4

PR2 80 @1K_ 0201_5%

12

PR2 81 @1K_ 0201_5%

12

PR2 82 @1K_ 0201_5%

12

PR2 75 1K_0 201_5%

12

PR2 76 1K_0 201_5%

12

PR2 77 @1K_ 0201_5%

12

PR2 78 1K_0 201_5%

12

PR2 79 @1K_ 0201_5%

12

12

PR2 48
0_0 603_5%

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

VID[5:3] =100 fo r SV CP U 48A
VID[5:3] =011 fo r LV CP U 35A

PC2 09

0.2 2U_0 603_10V7K

1 2

12

PR2 49

0_0 603_5%

PR2 74
0_0 603_5%

PC2 40

0.2 2U_0 603_10V7K

1 2

Issued Date

4

UGA TE1_ CPU2

4

12

UGA TE1_ CPU1

12

4

2008/09/15 2010/12/31

3

CPU_B+

PC2 01

PQ2 01
IRF H79 14TR PBF

123

PQ2 02

TPC A8028 _PSO8

241

PQ20 5

123

IRF H79 14TR PBF

PQ2 06
TPC A8028 _PSO8

241

Deciphered Date

0.1 U_04 02_25V6

PC2 31

3

5

3 5

5

3 5

Compal Secret Data

12

PC2 02

12

0.1 U_04 02_25V6

2

PL2 01

HCB 2012 KF-121 T50_0805

12

12

PL2 03

12

220 0P_040 2_50V7K

12

PC2 32

220 0P_040 2_50V7K

PC2 46

12

12

PC2 03

PC2 07

4.7 U_08 05_25V6- K

PR2 11

PC2 10

100 0P_060 3_50V7K

12

PR2 53

12

100 0P_060 3_50V7K

PC2 08

4.7 U_08 05_25V6 -K

4.7 U_08 05_25V6- K

12

PR2 13

2.2 _1206_ 5%

12

2.2 _1206_ 5%

3.6 5K +- 1% 0603

12

PC2 33

4.7 U_08 05_25V6- K

PR2 55

HCB 2012 KF-121 T50_0805

12

12

PC2 04

4.7 U_08 05_25V6 -K

PL2 02

0.3 6UH 20% PCM C104 T-R36MN 1R105 3 0A

1

LF 2 V2 N

12

12

PR2 14

PR2 20

10K _0402_1 %

@0_ 0402_5%

1 2

ISE N2
VSUM +

12

12

PC2 38

PC2 34

4.7 U_08 05_25V6- K

4.7 U_08 05_25V6- K

LF 1 V1 N

12

12

PR2 56

10K _0402_1 %

3.6 5K +- 1% 0603

ISE N1

VSUM +

Title

Size Doc ume nt N umber R ev

Dat e: Sheet o f

2

4

3

2

V1 N VS UM-

CPU_B+

12

PC2 39

4.7 U_08 05_25V6- K

PL20 4

0.3 6UH 20% PCM C104 T-R36MN 1R105 3 0A

1

4

3

2

PR2 59
@0_ 0402_5%

1 2

V2 N

Compal Electronics, Inc.

CPU_CORE

L A-39 42P

1

B+

1

+

PC2 06

100 U_25V_M

2

+C PU_C ORE

12

PR2 16
1_0 402_5%

+C PU_C ORE

12

PR2 57
1_0 402_5%

VSU M-

40 47Tue sday , J anua ry 05, 2010

1

0. 9

5

BQ2 4740VREF

12

PR1 000
165K_04 02_1%

IADAP T35

D D

1 2

PR1 013

10K_040 2_1%

1

2

3

12

PR1 018

76.8 K_0402_1%

ADP _SIGNA L

1 2

PR1 022

100_040 2_5%

C C

VI N

PQ1003

NDS 0610_NL_ SOT23-3

12

PR1 030
68K_040 2_5%

12

PR1 040
33K_040 2_5%

12

PR1 045

B B

4.7 K_0402_5%

1SS 355_SOD323-2

2VR EF_51125

12

PR1 063
130K_04 02_1%

A A

12

PR1 065
10K_040 2_1%

PD1 004

PR1 046

8.6 6K_0402_1%

12

12

12

12

5

6

1 2

10K_040 2_5%

PR1 042

8.06 K_0402_1%

E

3

C

PQ1006

1

MMBT3906H_S OT23-3

AD P_A_ID

PR1 059

45.3 K_0402_1%

1 2

PR1 062

1M_0402 _5%

VL

8

P

+

O

-

G

PU1 05B
LM393DG _SO8

4

AD P_A_ID

PR1 066

5

+3VL

B

2

8

3

P

+

O

2

-

G

PU1 004A

4

LM393DG _SO8

+3VL

12

PR1 064
22K_040 2_5%

7

AD P_A_ID 30

ADP _DET# 30

4

PC1 000

0.22 U_0603_10V 7K

1 2

PU1 000

+IN

V-

-IN

LMV321AS5X_SOT23-5

1SS 355_SOD323-2

D

S

13

G

2

1

4

5

V+

4

OUT

PD1 000

12

2N7 002KDW H-2N_SOT3 63-6

2N7 002KDW H-2N_SOT3 63-6

+5VS

12

PC1 001

0.0 1U_0402_16 V7K

12

PR1 017
2K_0402 _5%

PD1 001
1SS 355_SOD323-2

1 2

12

1

PR1 025

2

3.9 K_0402_5%

PQ1007B

PQ1007A

3

SRSET 35

C

PQ1005

PR1 028

OC P_A_IN

2

B

E

3 1

12

PD1 003
GLZ 4.7B_LL34-2

ADP _EN# 35

MMBT3904W H_SOT323-3

OC P_A_IN 30

OCP30

12

PR1 031

100K_04 02_1%

12

27. 4K_0402_1%

PR1 029

1 2

PC1 004

0.0 1U_0402_16 V7K

1 2

100K_04 02_5%

1 2

PR1 032

100_040 2_5%

PC1 003

3900P _0402_50V7K

34

5

VCC 1_PW RGD 30,36

61

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

ADP _EN 30

2008/09/15 2010/12/31

3

Compal Secret Data

Deciphered Date

2

PR1 033 @0_0402 _1%

1 2

PR1 034 200K_04 02_1%

1 2

5

6

12

PR1 027 100K_04 02_1%

PR1 026

100K_ 0402_1%

2

+5VS

8

P

+

-

G

PU1 004B

4

LM393DG _SO8

1 2

1

+3VS

PR1 019
10K_040 2_5%

1 2

1 2

PR1 020
0_0402_ 5%

13

D

2

G

S

PQ1004
SSM 3K7002FU _SC70-3

PR1 035

1 2

7

O

10K_040 2_5%

+3VL

Title

Size Do cum ent Num ber R ev

Cu stom

LA-4902P

Da te: Sh eet o f

+3VS

Compal Electronics, Inc.

ADP_OCP

41 47T uesd ay, J anuary 05, 201 0

1

OCP # 15

5

4

3

2

1

B+

D D

PR7 04

10_0402 _5%

1 2

VSS_AXG _SENSE7

VCC _AXG_SENSE7

+GF X_CORE

C C

PR7 06

10_0402 _5%

1 2

150P_04 02_50V8J

PL701

HCB 2012KF-121 T50_0805

1 2

PL703

HCB 2012KF-121 T50_0805

1 2

1 2

PC7 09
1000P_0 402_50V7K

1 2

PC7 12
330P_04 02_50V7K

PR7 10

10.5 K_0402_1%

12

12

PC7 20

PR7 35

17.8 K_0402_1%

825K_04 02_1%

1 2

12

GFX_B+

12

PC7 01

2200P _0402_50V7K

12

PR7 11

1 2

PC7 16

100P_04 02_50V8J

PC7 21

22P_040 2_50V8J

1 2

12

12

PC7 02

4.7 U_0805_25V 6-K

PC711
330P_04 02_50V7K

PC7 17

1000P_0 402_50V7K

8.06 K_0402_1%

PC7 03

4.7 U_0805_25V 6-K

PR7 34

12

12

12

PC7 04

4.7 U_0805_25V 6-K

PC7 27

PC7 05

0.1 U_0402_25V 6

4.7 U_0805_25V 6-K

+5VALW

PR7 01

1_0402_ 5%

12

12

PC7 06
1U_ 0603_10V6K

29

AGND

7

VSEN

6

FB

5

COMP

4

PR7 12

47K_040 2_1%

12

+GF X_CORE

VW

3

12

RBIAS

2

PGOOD

1

CLK_EN#

12

12

12

PR7 19

PR7 20

@10K _0402_1%

@1. 91K_0402_1%

PR7 02

0_0402_ 5%

ISUM+

ISU M-

10

9

8

11

12

RTN

PU7 01
ISL62 881HR Z-T_QFN28_4X 4

28

VIN

VDD

ISUM

ISUM+

VID5

VID626VR_ON27DPRSLPVR

25

24

1 2
12

13

IMON

VID323VID4

PC7 07

0.2 2U_0603_25 V7K

BST_GFX

14

BOOT

UGATE

PHASE

VSSP

LGATE

VCCP

VID0

VID1

VID2

22

12

PR7 03

22. 6K_0402_1%

1 2

PR7 05
0_0603_ 5%

15

LX_GFX

16

17

DL_GFX

18

19

20

21

1 2

0_0402_ 5%

12

PC7 08

0.2 2U_0402 _6.3V6K

1 2

PC7 10

0.22 U_0603_10V 7K

PR7 33

0_0603_ 5%

1 2

PR7 13

1 2

0_0603_ 5%

12

PC7 18

2.2U _0603_10V7 K

GFX VR_IMON7

PR7 15

VSS_AXG _SENSE 7

DH_ GFX1DH_ GFX

+5VALW

AO N6718 L 1N D FN

PQ702

578

3 6

3 5

PQ701
AO4474L _SO8

241

241

12

PR7 07

2.2_ 1206_5%

1 2

PC7 19

0.56 UH +-2 0% PCM C104T-R5 6MN 25A

1000P _0603_50V7K

PL702

1 2

12

PR7 08

3.65 K_0603_1%

1 2

PR714

2.61 K_0402_1%

PR717

1 2

11K_040 2_1%

PC7 22

1 2

0.1U _0402_16V7 K

12

PR7 09

PH7 01

1 2

10K B_0603 _5%_ERTJ1VR1 03J

0_0402_ 5%

(15A,6 00mils ,Via NO.= 30)

+GFX_CORE

GFX VR_PW RGD32

GFX VR_CLKEN#

B B

PR7 310_0201_ 5%

12

PR7 320_0201_ 5%

12

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/09/15 2010/12/31

3

Compal Secret Data

Deciphered Date

GFX VR_VID_0 7
GFX VR_VID_1 7
GFX VR_VID_2 7
GFX VR_VID_3 7
GFX VR_VID_4 7
GFX VR_VID_5 7
GFX VR_VID_6 7
GFX VR_EN 7
GFX VR_DPR SLPVR 7

2

ISUM+

ISU M-

1 2

PC7 24

0.1U _0402_16V7 K

PR7 29

82.5 _0402_1%

1 2

Title

Size Do cum ent Num ber R ev

Cu stom

Da te: Sh eet o f

PR7 23

3.01 K_0402_1%

1 2

PC7 25

0.01 U_0402_16V 7K

1 2

PR7 25
@100_0 402_1%

1 2

PC7 26
@12 00P 50 V K X7R 0402

1 2

Compal Electronics, Inc.

VCCGFX

LA-3942P

42 47T uesd ay, J anuary 05, 201 0

1

5

4

3

2

Versio n chan ge lis t (P.I.R. List) Power section Page 1 of 1

1

Item Reason for change PG# Modif y List

For all S MSC10 98 pl atfor ms, p lease chan ge

1

the signa l "AC _AND_ CHG" to "A C_ADP _PRES ".

This is t o kee p up with AC ad apter tabl e cha nges made

2

D D

in K BC co de.

Chan ge PR 604 t o 15K to r esolv e +0. 75VS to

3

+1.5 V_CPU _VDDQ timi ng is sue s een o n Car tier/ Dior/ Vers ace.

To w orkar ound TPS51 125 t urn o n abn ormal issu e,

4

need to m ake s ure t otal caps on +5 VL ra il is at l east
30uF . Cu rrent ly on ly ha ve 20 .2uF.

The +1.8V S pow er ra il is very inef ficie nt an d

5

want to c hange to a bett er so lutio n.

For ULV C PU de sign reser ve.

6

To b est s olve the i ssue of +1 5V co mbo a dapte r
(air line adapt er) d etect , res erve PR127 , Add

35

PR12 8 76. 8K +- 1% 04 02.

PR10 42 ch ange the v alue from 21K + -1% 0 402 t o 8.0 6K + -1% 0 402.
PR10 59 ch ange the v alue from 24.9K +-1% 0402 to 4 5.3K +-1% 0402 .

41

PR10 46 ch ange the v alue from 4.12K +-1% 0402 to 8 .66K +-1% 0402 .

PR60 4 cha nge t he va lue f rom 1 0K to 20K.
PD60 1 add the compo nent 1SS35 5.

38

PC60 6 add the compo nent 0.1uF _0402 _16V7 K.

Add PC316 10U_ 0805_ 10V6K
PC30 7 cha nge t he va lue f rom 1 0U 6. 3V M X5R 0 805
to 2 .2U 1 0V K X5R 0 805.

36

PC31 5 cha nge t he vl aue f rom 1 0U 10 V K X 5R 08 05
H1.2 5 to 22UF 6.3V M X5R 0805 H1.2 5.

36

Chan ge +1 .8VS VR sc hemat ic.

Rese rve P R229 / 0_0 402_5 % and

40

PH20 3 10K B_060 3_5%_ ERTJ1 VR103 J

Date Ph ase

2009/5/4

2009/6/29

2009/8/28

2009/8/29

2009/9/16

2010/01/04

DB-2

SI-1

SI-2

SI-2

SI-2 B

MV

7

C C

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

2008/09/15 2010/12/31

Deciphered Date

2

Compal Electronics, Inc.

Title

Changed-List History

Size D oc umen t Numbe r Re v

Date : Sheet of

LA- 4902 P

43 47Tuesda y, Janua ry 0 5, 201 0

1

0.9

5

pin1 &

Redu ce u n-insta ll parts f or XDP-CPU Del R4, R6, R8, R11, R40, R41, R43, R48, R49

<2009.01.12>

D D

C C

<2009.01.14>

1

Add test points at XDP-CPU 4 Add T112, T113

2

Redu ce e DP la ne to meet panel res olution. 5 Red uce lan e1, 2

3

Add 1uf Cap s to meet Intel design gu de at +VCA P0, +VCAP1 7 add Caps account t o 12pcs

4

5

Add L31 at +VTT_DDR

6

Add L32 at +VDDQ_CK

7

Chan ge R 171 net name at XD P-PCH 1 2 Cha nge USB_OC #6 to PCH_ XDP_GPIO10

8

Add R190 at XDP-PCH 12 ad d R1 90 & USB_O C#4

9

Chan ge p ull up for Intel Design Gui de 13 ch ange pu ll up to contact t o R206 pin 1

1 0

Remo ve L VDS for HP request 1 4 Rem ove LVDS-A ch annel

1 1

chan ge v alue for H P request 15 ch ange R270 , R274 val ue to 39oh m

1 2

Add Resi sters for XDP-PCH

1 3

Chan ge R 295 net name at XD P-PCH 1 5 Cha nge USB_OC#7 t o WOW#

1 4

Chang e value 25 Ch ange R4 51 to lerance to 1% and C4 41 toleran ce

1 5

Chang e value 25 Ch ange C428 value to 1 000P

1 6

Remo ve E -SATA for HP request

1

4

PA G E Mod i fy L is tFi xe d Is s ue a n d ch an g e it emI t em

3

2

1

M. B . V er .

0.14

0.1

0.1

0.1

8 a dd C aps a ccount to 24pcsAdd 1uf Cap s to mee t Intel de sign gude at +Vccp

7 a dd L31

7 a dd L32

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

15 Ad d R35 1, R265

0.1

0.1

0.1

0.1

12 Re move SATA-2 channel

24 Re move E-SAT A support circuit

0.1

Chan ge U SB group for HP re quest 1 5 Cha nge USB -1 from Right side to Rear-1 side

2

Modi fy Aud io circuit

3

Add 4.7K ohm pul lup to +3 V and a 0. 01uF capac itor at HD A_RST# 26 Ad d R703 , C637

4

Chan ge Audi o Gain dB 26 R48 6 & R49 1 instal l ; R485 & R492 un-i nstall.

5

Dele te c hannel-C signals o f DP

<2009.01.15>

B B

<2009.01.16>

A A

1

Chan ge p ower USB control m ethod chan ge P owe r USB s olution to one chip control so lution

2

chan ge A udi o Dock Line in / out sense circuit

3

Add Ext-Mic A mp.

4

Chan ge XDP- CPU net

1

Chan ge e DP_AUXN contact t o CPU pin

2

Remo ve CFG 7 (No supp ort)

3

Add pull up for HP request

4

GFX_ CORE ne eds high f requency d ecoupling.

5

VTT pins contac t wrong po wer source

6

CPU_ CORE mi ssing high frequency decouplin g.

7

Chan ge L AN po wer source control m ethod

8

9

26

Add FET and s upport cir cuit for S ENSE.

27

Chan ge Audi o jack

14

Dele te c hannel-C signals o f DP

24

26 ch ange R5 10, R515 value t o 100k and R510, R51 5 pin1 con tact to A- GND

27

Add Ext-Mic A mp.

4 J P4 [ 28, 30] conn ect to CFG [10:11 ]. JP4 [34 ,36] conne ct to CFG [6:7].

5

MB_C _DP_ AUXN should con nect to U1 A.D19.

5

delet e R71.

7 A dd 1 0K (R70 5) NI pull -up to +VC CP on GFXV R_EN.

Add 16x040 2 1uF caps .

7

Chan ge VTT pin to +V CCP

7

Add 25x040 2 1uF caps .

7

C330 - C 333 , C3 29, R383, R386, Q21 uninstall and change "LAN_CTRL _18" to "L AN_CTRL_10 "

21

Add USB cha nnel 6Add USBP 6 for su pport WiMa x. 22

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

15

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2010/12/31

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

HW PIR(1)

LA-5251P

1

44 47T uesday, J anuary 05, 2 010

0.9

5

4

3

2

1

KAT10 from DB-2 to SI-1 LA-5251P REV:0.2 -> 0.3 Modify <2009.06.08.~2009.07.02. >

Item ImpactDate PageRev. Modify DescriptionChange Cause

0.3 1 6/12 CKT,Layout 29 -To avoid Docking side DP monitor signals back drive PCH during S3/S4/S5 <HP>.

0.3 -Add U13,R319 (10K_0402);Remove and Del C550,C551,C552,Q12,U11,U12,U29,U30,U31,R320,R321,R327,R328,R329,R330;Del D5,D6,D7.3 6/14 CKT,BOM,Layout 18,29 -Change CRT Switch design from TI/TS5A3157 to MAXIM/MAX4885E

0.3 4 6/16 BOM 19 -Make R338 & R344 no install. Make R332 & R337 installed.-Correct the DP design. <HP>

for Layout Quality improve also Components reducing. <Compal>

0.3 5 6/16 CKT,Layout 23 -Change net connection and move C933 to in between R1079.2 and R1077.1.-Current placement of C933 is ineffective to limit inrush current.<HP>

0.3 6 6/16 CKT,Layout 13 -Add back the 25MHz XTAL_IN circuit for Intel workaround on sighting #400750 -

D D

0.3 7 6/16 CKT,BOM,Layout 26 -A udio Am p Int. regulator design concern.<HP> -Add R490 (100K_0402) close to U24.25 to connect U24.25 and PLT_RST#.

0.3 8

6/16 CKT,BOM,Layout 15,20 -To leverage the LDO regulator of the camera modules.<HP> -1.Change R365 from 0_0201 to 0_0402. Change R569,R613 from 100K_0201 to 100K_0402.Change R377 from 100K_0201_1% to

3306048 - 96MHz jitter.<HP>

0.3 9 6/17 CKT,Layout 28 -Correct the TouchPoint pin connection.<Compal> -Correct JP2 7 conn ection from currently Pin1:+5VS,Pin2:RIGHT,Pin7:GND,Pin8:GND to Pin1:RIGHT,Pin2:NC,Pin7:NC,Pin8:+5VS.

0.3 10 6/18 CKT,Layout 16 -Simplify the reserve circuit.<HP> -Del C277(@10U_0603). Move C276 and related routing to bottom layer 0 mm limit high area without vias.

0.3 11 6/18 CKT,Layout 30 -Design Change for KBC I/F power rail synchronize.<HP> -Change U8.5 power from +3VALW to +3VL.

0.3 12 6/18 CKT,BOM,Layout 24 -Add com mon mo de chokes on all USB walk-up ports to address PCH EMI

0.3 13 6/18 CKT,BOM,Layout 30 -Design Change for KBC I/F power rail synchronize.<HP> -Change U8.5 power from +3VALW to +3VL.

issue on full/low s peed USB devices.<HP/INTEL>

0.3 14 6/18 CKT,BOM,Layout 19 -Add fus e (0.5A) for DP Safty solution.<Compal> -Add F2(FUSE) between R349.2 and JDP1.20 for Safty s olution.

0.3 15 6/22 CKT,Layout 16 -Layout Placement Limitation.<Compal> -Del C277(@10U_0603) and C276, add the test points T126,T127 for the ball pins.

C C

0.3 16 6/25 CKT,Layout 22 -Change 1. 8"HDD design from cable to Board to Board connection.<HP> -Del JHDD1 a nd JHDD2 Cable design. Add JHDD3 B to B directly connect design.

0.3 17 7/1 CKT,Layout 25 -Need to add ES D protection to SC_DATA, SC_RST, & SC_CLK.<HP> -Reserve D54,D55,D56 ESD protection design as what Ricoh recommend.

180.3 7/1 CKT,BOM,Layout 11 -Reserve Low Power CLK Gen design.<Compal> -Modify U6 Pin1,17,24 connection from +3VS_CK505 to +3VS_CK505_G (+3VS and +1.5VS option for tuture); Add R143(0ohm_0603)

190.3 7/1 CKT,BOM,Layout 12,20 -Mak e the LID_S W# design change for leakage issue fix.<HP> -Change Q56.5 from DISP_OFF# to LID_SW#; Del D10(DAP202U); Add R361(10K_0402) close to U7; Add D57(CH751H); Remove

0.3 20 7/1 CKT,BOM,Layout 13 -Fix I NTEL Chipset Issue impact DP function. <HP/INTEL> -Del T122, Del R1093(0_0402) and replace by add C200 (18P); Install R210,Y3,C199 by Intel finalized DP workaround and need them.

0.3 21 7/1 CKT,BOM,Layout 13,21 -Follow INTEL Design Change. <HP/INTEL> -Remove R388 (0_0201); Connect U14.48 through add R407 (0_0402) to U7.U4 (R202.2) by INTEL request.

0.3 22 7/1 CKT,BOM,Layout 30 -Follow SMsC KBC Chip Design Change and VCC1 decoupling improve. <HP/SMsC> -Add C565 (0.1U_0402) on and close to U32.14 for VCC1 decoupling improve by SMsC request; Change C559 from 4.7UF_Y5V to 4.7UF_X5R.

0.3 23 7/1 CKT,BOM,Layout 30,14,22 -D esign s implify on b oth EE and PWR from HP. <HP> -Del D37(@CH751H) and related. Remove R246,R422,and delete PR217.

0.3 24 7/1 CKT,BOM,Layout 33 -Add +VCCP and +GFX_CORE discharge circuit. <HP> -Add R699,R702,Q41 for +VCCP and +GFX_CORE discharge

0.3 25 7/1 CKT,BOM,Layout 22 -Half size m ini card I/F transfer design reserve for future. <Compal> -Del T87, Add R475 (0_0201) and R453 (0_0402); Reserve R433,R437,R432,R421,R431,R441 close to JP6 bottom layer under the module

0.3 26 7/1 CKT,Layout 22 -Update t he Symbol and PCBFootprint for meet. <Compal> -Update JODD1 PCB Footprint from ALLTO_C18522-11303-L_13P_NR to TYCO_2023233-3_13P_NR

0.3 27 7/2 CKT,BOM 15 -Simp lify the design for save power consumption. <HP> -Change R279 from 10K_0201 to 100K_0201.

0.3 28 7/2 CKT,BOM,Layout 23 -Design change for WW AN Power Rail. <HP> -Chang e R1077.1,C933.1,Q77.3,J3.2 connection from +3VS to +3VALW for WWAN power rail. Install C933(1000P_0402) in order to slow

0.3 29 7/2 CKT,Layout 15 -Design change for LAN_DIS#. <HP> -LAN_DI S# R298 should be pulled-up to +3VM_LAN instead of +3VALW.

B B

0.3 30 7/2 CKT,BOM,Layout 12 -Design change for LID_SW#. <HP> -Delete R135 since it is a duplicate. Change R361 to 100K_5%. Add 100K_5% pull-up to +3VL on LID_SW# and close to U32.64.

0.3 31 7/2 CKT,BOM 30 -Update the Board ID setting for SI-1. <HP> -For SI-1 Bo ard ID detec t, make R574 installed & make R575 no install.

0.3 32 7/2 CKT,BOM 30 -Simp lify the design for save power consumption. <HP> -Remove R589 on KBRST# pull-high to +3VL. Change R607 on PM_RSMRST# from 10K to 100K to reduce current.

0.3 33 7/2 CKT,Layout 31 -Design change t he USB I/F FPR ESD solution. <HP> -C hange the ESD diode (D39.4) power supply from +3VALW to +5VALW.

0.3 34 7/2 CKT,BOM 31 -Simp lify the design for save power consumption. <HP> -Remove R626 (0_0201) since there is an internal pull-down in U34.

0.3 35 7/2 CKT,Layout 28 -Reserve Caps solution on STB_LED# for EMI verify. <Compal EMI> -Reserve C536(1000P_0402) Cap on STB_LED# close to JP22.8 for EMI noise issue verify.

0.3 36 7/3 CKT,Layout 23 -New Card Power Switch design change for portload test improve. <TI> - Connect U17 pin 12 and 14;pin2 and pin4;pin11 and 13;pin3 and 5 for express card portload test.

0.3 37 7/3 CKT,BOM,Layout 12,13 - GPIO13 has internal pull-down which is source of leakage. <HP> -Change U7. J30 c onnection from LID_SW#_ISO# to T122. Change U7.B9 connection from SMBALERT# to LID_SW#_ISO#. Del R193

0.3 38 7/3 CKT,Layout 20 -Current draw on INVPWR_B+ could be very high.<HP> -Change JEDP1 pin6 connection from +3VS to INVPWR_B+.

0.3 39 7/3 CKT,BOM,Layout 30 -Save one resistor but also reduce the two long traces.<HP> -Del R594 (220_0402) (PM_PWROK)

-Change JP30 Pin 8 connection from NC to SLP_S3#

-Change JP30 Pin 39 connection from NC to SATA_LED#0.3 2 6/12 CKT,Layout 29 -New add SATA_LED# to monitor stand port <HP>.

-Reserv e back the 25MHz design circuit. (Reserve Y3, R210,C199); Move R1093 to close to Y3 and C199.

100K_0402_1%.

2.Renam e WEBCAM_OFF to WEBCAM_ON and connect PCH GPIO37(U7.AB13) through WEBCAM_ON_R by R375(0_0402) to JEDP1.18.

3.Connect +5 VS_WEBCAM to +5VS through R304 (0_0603) close to JEDP1.24 and move C316~C319 close to JEDP1.24. Del
Q17,C315,C321,R360-R362,R367,R373.

4.Change U7.AB13 and R287.1 connection from PCH_XDP_GPIO37 to WEBCAM_ON. Change R287 from 10K_0201 to
@10K_0402(uninstall).

5.Change U7.F16 connection from WEBCAM_OFF to USB_OC#2 and add pull-high R301(10K_0201) to +3VALW.

-Change JP13,JP14,D18,D19,D20 USB pairs net connection and add or reserve R352,R350,R354,R353,R360,R355,L8,L9,L19,L26. Change
R443,R444 from 0201 to 0402 and also the net connection.

to +3VS and reserve R120(@0ohm_0603) to +1.5VS but place close to U6.

R356(10K_0402);Change U7.J30 and R135.2 connection from LID_SW# to LID_SW#_ISO#.

Add 1K VGATE to PGD_IN resistor at PCH pin M6. Connect PGD_IN through add R408 (1Kohm_0402) to PCH U7.M6.

area for reworkable.

+3V_WWAN bring-up

(10K_0201) +3VALW PH.

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2010/12/31

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

H/W2 EE Dept. PIR SHEET(2)

LA-5251P

45 47T uesday, J anuary 05, 2 010

1

0.9

5

4

3

2

1

KAT10 from SI1 to SI1-R LA-5251P REV:0.3 -> 0.4 Modify <2009.07.07.~2009.07.14. >

Item ImpactDate PageRev. Modify DescriptionChange Cause

0.4 1 7/8 CKT,BOM,Layout 32 -To fix INT EL CPL S3 Power Leakage Issue <INTEL>.

0.4 2 7/8 CKT,BOM,Layout 4,15 -To fix INTEL CPL S3 Power Leakage Issue <INTEL>.

0.4 3 7/8 CKT,BOM,Layout 33 -To fix INT EL CPL S3 Power Leakage Issue <INTEL>.

D D

0.4 4 7/8 CKT,BOM,Layout 7,10 -To fix INTEL CPL S3 Power Leakage Issue <INTEL>.

CKT,BOM,Layout 32 -To fix I NTEL CPL S3 Power Leakage Issue <INTEL>.

0.4 6 7/9 --Install R693 (470_0201) and Q53 (2N7002).CKT,BOM 33 -To fix INTEL CPL S3 Power Leakage Issue <INTEL>.

0.4 7 7/9 CKT,BOM,Layout 4,5 -T o fix INTEL CPL S3 Power Leakage Issue <INTEL>. --Change R1092 PD connection from PCH_DDR_RST to SM_DRAMRST# and close to U1.BJ12. Add C6 (470P_0402) close to Q52.2.

0.4 8 7/10 CKT,Layout 7 -To f ix INTEL CPL S3 Power Leakage Issue <INTEL>. --Change L32.2 connection from +1.5V to +1.5VS_CPU_VDDQ.

0.4 9 7/10 CKT,BOM,Layout 33 -To fix I NTEL CPL S3 Power Leakage Issue <INTEL>. --Add C626,C664 close to JDIMA1;C656,C657 close to JDIMB1.

0.4 10 7/17 CKT,BOM 4 -To meet Intel electrical requirements <INTEL>. --Change back R12 from 4.99K_0402_1% to 1.5K_0402_1%; R13 from 2.49K_0402_1% to 750_0402_1%.

CKT,BOM,Layout7/17110. 4 --Change R1103 from 470_0402 to 220_0402; R693 from 470_0201 to 22_0402.-To meet Intel ramp down timing for 1.5V and 0.75VS <INTEL>.33

0.4 12 7/17 CKT,BOM 33 -To fix INTEL CPL S3 Pow er Leakage Issue <INTEL>. --Remove R1092 (100K_0402).

0.4 13 7/17 CKT,BOM,Layout 33 -To to avoid a glitch while turning on +1.5V_CPU_VDDQ <HP> --Add C505 (@0.01UF_0402) close to U45.4.

0.4 14 7/17 CKT,BOM 24 -Correct BOM <Compal> --Change U18 and U20 from SA000027C00 (G548A2P8U MSOP) to SA00002WY00 (G548A1P8U MSOP) for BOM correct.

0.4 15 7/22 CKT,BOM,Layout 28,30 -Design change ON/OFF# control from PCH directly become through EC. <HP>

0.4 16 7/22 CKT,BOM,Layout 30 -Design reserve for themal fan table switch for SV/LV CPU type detect. <Compal> --Reserve CPU_SV_ID_DET with R551(@100K_0402)PH and R553(@100K_0402)PD.

C C

0.4 17 7/22 CKT,Layout 15 -Design res erve for themal fan table switch for SV/LV CPU type detect. <Compal> --Add R302(@10K_0201) PD close to R280 on PCH GPIO15.

<KBC will b lock the PWRBTN# and hold PWRBTN_OUT# HIGH when it receives a
comman d from the BIOS indicating BOOT BLOCK reprogramming is in progress.>

0.4 18 7/24 CKT,BOM 26 -Increas es at tenuat ion of PC beep to an acceptable loudness level. <HP> --Change R484 from 100K_0201 to 300K_0201.

0.4 19 7/24 CKT,BOM 26 -Increas es line in attenuation from -6dB to -10dB. <HP> --Change R502, R504 from 4.7K_0402_5% to 6.04K_0402_1% & R503, R505 from 4.7K_0402_5% to 2K_0402_5%.

0.4 20 7/24 CKT,BOM 36 -Per TI 's recommendation for 3VLP. <TI> --Change PC307 from 10U_0805_6.3V6M to 2.2U_0805_10V6K.

--Update U38 Symbol. Add one new signal "VCCP_1.5VSPWRGD" be generated from VCCP_EN through an new add AND gate U77 to R12.2 .

--Change R12.2 connection from +1.5V to VCCP_1.5VSPWRGD. Change R12 from 1.1K_0402_1% to 4.99K_0402_1%; Change R13 from
3K_0402_1% to 2.49K_0402_1%. Change U1.BJ12 connection from DRAMRST# to SM_DRAMRST# by add Q52 which control by
PCH_DDR_RST new connect from U7.F10 (PCH GPIO8)(GPIO8-->PCH_DDR_RST) and with add R1093 (1K_0402) PH to +1.5V, add R1092
from @10K_0402 to 100K_0402.

--Add new Power from +1.5V to +1.5VS_CPU_VDDQ by add U45,C624,C625,R1104 close to C152; Add +1.5VS_CPU_VDDQ discharge circuit
by add R1103(470_0402) and Q52B (already exist) close to U45.

--Change U1 VDDQ Power source from +1.5V to +1.5VS_CPU_VDDQ but keep C20~C27 at the same place; Del C145,C146,C119,C120
10UF_0603 reserve for U45 and related placement.

--Change U77.1 connection from VCCP_EN to SLP_S3# reserve through R6(@0_0402) or to +3VALW through R4 (8.2K_0402).0.4 5 7/9

--Disconnect LANLINK_R# from KBC (GPIO24/KSO16) by through R608(@0_0402) reserve; Rename GPIO24 of KBC to PWRBTN_OUT#;
Install R550 (Change R550 from 100K_0201 to 100K_0402); Disconnect the PWRBTN# output from the button switch to the PCH by remove
D34; Co nnect ON/OFFBTN# from KBC GPIO24 to the PCH let KBC can now control the PWRBTN#.

KAT10 from SI1-R to SI2 LA-5251P REV:0.4 -> 0.5 Modify <2009.08.11.~2009.08.28. >

Item ImpactDate PageRev. Modify DescriptionChange Cause

0.5 1 8/18 CKT,Layout 32 -To avoid the thermal module Assy. risk. <Compal DFx>.

0.5 3 --Change JP28-1 from +3VL to +VREG3_51125 power rail.8/25 CKT,Layout 28 -To fix f alse CBB button triggering on AC insertion due to noise seen on +3VL

0.5 4 --Change U7.P8 connection from LPC_PD# to SUS_STAT# as NC with only T87 test pad only. Add R367 4.7K_0402 with PH +3VS on U34.28.8/25 CKT,BOM,Layout 14,31 -Disconnect LPC_PD# from TPM U34. <HP/Intel/Infineon>.

power rail. <HP>.

0.5 5 8/25 CKT,BOM,Layout 15,23 --Change U7.T15 GPIO14 connection through R265(0_0402) from WOW# as NC to CPPE# which connect to ExpressCard JEXP1-17 & U17-10.-Rename WOW# (U7F-T15) to CPPE# and connect to JEXP1-17 & U17-10. <HP>.

0.5 6 8/25 CKT,BOM 26 -Correct the Audio Amp. Gain setting. <Compal>. --Remove R485 (0_0201).

0.5 7 8/28 CKT,BOM 4 -Prevent glitch on DRAMRST#. <HP>. --Change C6 from 470P to .1U_0402.

0.5 8 8/28 CKT,BOM,Layout 26 -Ch ange audio REG_EN pin to +5VALW to prevent pop sound on warm boot. <HP>. - -Change R490.2 connection from PLT_RST# to +5VALW.

0.5 9 8/28 CKT,BOM 12 -Remove PCH Debug Port related to save power consumption. <Compal>. --Remove R158,R156,R167,R165.

0.5 10 8/28 CKT,BOM,Layout 29 -Cancelled Dock ing +5VS Caps design reserve before for design simplify. <Compal>. --Del C543 (10U_0805), C544~C546 (0.1U_0402).

B B

0.5 11 8/28 CKT,Layout 32 -Cancel S kew Hole because of M/E PCB outline change. <Compal>. --Del H27 (H_3P0).

0.5 12 8/28 CKT,BOM,Layout 19 -Cancel Swatch system side Display Port Common Mode Choke reserve for design

0.5 13 8/28 CKT,Layout 18 -Reserve 10PF caps on VGA_RED_R, VGA_GRN_R, VGA_BLUE_R for EMI backup

0.5 14 8/28 CKT,BOM 23 -Cancel Braidwood support but keep design reserve. <HP>. --Remove R567,R562,C571,C566,JP11.

simplif y and layout space free. <Compal>.

solution. <Compal>.

0.5 15 8/31 CKT,BOM,Layout 12 -Add back PCH GPIO1 3 Ext. Pull-High to +3VALW. <HP>. --Change U7.J30 connection from T122 to become PCH_GPIO13 and pull-high to +3VLAW through R8(10K_0402).

0.5 16 9/01 CKT,BOM,Layout 28 -W W_LED# Design change for fix WWAN Module LED issue. <HP/Compal>. --Del Q33,Q35,R542 Change R1097,R1098,R1099 value and connection.

0.5 17 9/01 CKT,BOM,Layout 24 -Stakup USB Connector update fro Compal DFb review. <Compal>. --Chaneg JP13 PCB Footprint from SUYIN_020122MR008S51CZL_8P to SUYIN_020122GR008S51CZL_8P-T.

0.5 18 9/03 CKT,BOM 15 -Cancel Braidwood support but keep design reserve. <HP>. --Remove R257 (@32.4_0402_1%).

0.5 19 9/03 CKT,BOM 23 -To resolve slow turn off of +3V_WWAN. <HP>. --Install R1077 (10K_0402_5%).

20 9/03 CKT,BOM 26 -To fix E Q set ting m ake the changes. <HP>. --Remove R491 (@100K_0201) ; Add R485,R486 (0_0201_5%).

0.5

0.5 21 9/10 CKT,BOM -- -To correc t the sym bol inside information to make value match with SMT BOM for

A A

long-term. <Compal>.

22 9/11 CKT,BOM 23 -To reduce power consumption. <HP>. --Remove R1077 (@10K_0402)0.5

--Add b ack H 31 and make the DDR routing modify for this.

--Reserve R366 (@0_0402 ohm NI) resistor between Q56-1 and R361-2.0.5 2 8/25 CKT,Layout 20 -To disconnect LID_S W#_ISO# from LID_SW# function. <HP>.

--Del L12~L16(@WCM-2012-900T_4P),R331,R333,R334,R335,R336,R339,R340,R341,R345,R347(0_0402) and related Net.

--Reserve C315,C320,C321(@10P_0402) close to R316,R317,R318.

--Change U8 from SA000023O00 to SA00003FF00; Q13 Q14 Q15 Q16 Q29 Q30 Q31 Q32 Q36 Q40 Q41 Q43 Q44 Q45 Q46 Q47 Q48
Q49 Q50 Q51 Q52 Q56 from SB570025280 to SB00000AR10; U17 from SA00001SL00 to SA00001SL20; U18,U20 from SA00002WY00
to SA000037P00; Q19, Q22, Q23, Q26, Q38, Q39 from SB923010030 to SB00000H500; U14 from SA00002MO10 to SA00002MO40; U6
from SA00002WX00 to SA00003NM00; U2 from SA000021J00 to SA00002ZT00; Change U46 from SA097010020 to SA097010040;
Correct L31 Value from TDK-MPZ140BS300A 0603 to 0_0603_5% for match; Correct L32 Value from 1UH_SQV322520T-1R0M-N_20% to
0_0603_5% for match; Install R551 (100K_0402) as default setting; Remove R143(@0_0603) and add R120(0_0603) for LP CLK Gen.
power as default setting; Remove &U1 for SMT BOM Match

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2010/12/31

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

H/W2 EE Dept. PIR SHEET(2)

LA-5251P

46 47T uesday, J anuary 05, 2 010

1

0.9

5

4

3

2

1

KAT10 from SI2 to SI2-R LA-5251P REV:0.5 -> 0.6 Modify <2009.09.11.~2009.09.29. >

Item ImpactDate PageRev. Modify DescriptionChange Cause

0.6 1 9/21 CKT,BOM,Layout 11,24 -To fix BT turn off time (>250mS spec) <HP>.

0.6 --Reserve Q28(SI2301),C975,C976,R1105,R1106 close to JEDP1.3 9/28 CKT,Layout 20 -To prev ent inrush current problem seen on some panels. <HP>.

0.6 4 9/28 CKT,Layout 20 --Reserve Reserve R372,C665 close to JEDP1.-To reserve the EMI solution for verify. <Compal-EMC>.

0.6 5 10/01 CKT,BOM 21 -To fix c rysta l frequ ency stability risk. <INTEL>. --Change C341 and C342 from 27P_0402 to 33P_0402.

D D

--Change CLK Gen CK_PWRGD from Q7(2N7002_SOT23-3) to Q55(2N7002DWH 2N SOT363-6); Add Q55B 2N7002 discharge FET on
+3VAUX _BT; Add R135 (470_0402) series resistor between drain of FET and +3VAUX_BT. Reserve C506 (@0.1UF_0402) for tune.

--Change PC713,PC714 location name to C973,C974.0.6 2 9/22 CKT,BOM 7 -Move +GFX_CORE Bulk Caps from Power related to EE related. <Compal>.

KAT10 from SI2-R to PV LA-5251P REV:0.6 -> 0.7 Modify <2009.10.13.~2009.11.4. >

Item ImpactDate PageRev. Modify DescriptionChange Cause

0.7 1 10/13 CKT,BOM,Layout 24 -Change one of the USB Bulk Cap from 150UF to 220UF. <Compal>.

0.7 3

0.7 4

0.7 5

10/19 CKT,BOM,Layout --Design change and del R270 to simplify that become CLK_PCI_DEBUG; Add R477 0 ohm to separate for JP6.19 option

10/21 CKT,Layout 15 --Modify RP1 Pin1,2,3 connection for layout routing smoothly. -Modify RP1 Pin1,2,3 connection for layout routing smoothly. <Compal>.

15,22,31 -S implify the CLK_PCI_DB and CLK_PCI_DEBUG design and routing for improve

EE signals quality and EMI Issue. <Compal>.

11/03 CKT,BOM,Layout 21 -M/E D esign change the RJ-45 connector. <Compal>. --M/E Design change JRJ45 DC234003O00(TYCO_2006067-1_13P) to DC020910201(FOX_JM36111-R2225-7H_13P-T). 0.7 6

11/030.7 CKT,BOM,Layout 24 -Add t he RC delay circuit between SLP_S4# and SLP_S4_R to fix dual USB

0.7 11/058 CKT,BOM,Layout 29 -Ad d the isolat e circ uit fo r Skagen side Monitor Stand HDD LED light on issue fix.

0.7 9 11/05 CKT,BOM 29 -Sc hematic BOM change for actual and common. <Compal>. --BOM change on Q30, Q19, U6.

can not power on issue. <Compal>.

<Compal>.

0.7 10 11/06 CKT,BOM 30 -Sc hematic BOM change for CBB Reset function. <HP>. --BOM change to install R605 (0_0201).

0.7 11 11/06 CKT,BOM,Layout 18 -Add + 3VS PH on CRT_DDC_CLK &C RT_DDC_DATA for design change.. <MAXIM>. --Add R53,R57(2.2K) +3VS pull-high on CRT_DDC_CLK &C RT_DDC_DATA for MAXIM CRT switch design change.

12 11/06 CKT,BOM,Layout 4 -Cancel REMOTE thermal sensor reserve. <HP/Compal>. --Delete REMOTE2+/- traces & Q1. Move C5 close to pins 16/15 of U2.0.7

C C

13 11/110.7 CKT,BOM,Layout 14,28 -A dd 0.1UF ca p for EMI issue fix. <Compal>. --Add C669 (0.1UF) close to R215; C668 (0.1UF) close to JP22.2.

14 11/110.7 CKT,BOM 20 -I nstall EMI INV_PWM reserve solution for issue fix. <Compal>. --Install R372 (22_0402) and C665 (220P_0402).

0.7 15 11/11 CKT,BOM,Layout 28 -Add 0.1UF CA P on ON/OFF# for ESD issue fix. <Compal>. --Add C670 (0.1UF_0402) close to JP20.2's via.

0.7 16 11/12 CKT,BOM,Layout 28 -Add 0 ohm resisto r for CBB reset function pin ground to avoid floating. <SMsC/Compal>. --Add R60 (0_0402) close JP28 pin 3 for CBB reset function reserve.

11/12170.7 --Add power jumper options for +1.5VS_CPU_VDDQ(PJP605) & +1.5V(PJP604) to PU601.1. Make PJP605 option installed.-To res olve glitch seen on +0.75VS power rail during S0->G3 transition. <HP/Compal>.38CKT,BOM,Layout

0.7 18 11/12 --Update the symbol and PCB Footprint FOX_QL1044L-D261A1-7H_82P-T for fix.-To resolve Docking Connector (JP30) SMT soldering issue. <HP/Compal>.CKT,Layout 29

0.7 19 11/12 CKT,BOM -- -S chemat ic BO M change for actual and common. <Compal>. --BOM change on C68,C69,C70,C71,C72,C92,C93,C94,C113,C114,C115,C140, C63,C64,C65,C66,C67,C85,C86,C87,C88,C89,C90,C91; C29,

0.7 20 11/13 CKT,BOM,Layout 32 -M/E S crew hole size modify. <Compal/HP>. --Change H2 from H_4P4 to H_4P7; H28 from H_4P8 to H_4P9.

0.7 21 11/13 CKT,BOM 25 -To fix CB B aut o active caused by +3VS leakage issue. <Compal>. --Change Q28 from AP2301(SB000007H10) to AP2309(SB00000MI00).

0.7 22 11/13 CKT,BOM 13 -To follow INTEL Design Guide requirement. <INTEL>. --Change C193,C194,C195,C196,C197,C198 from 0.1U_0402_16V4Z(SE070104Z80) to 0.1U_0402_25V4K(SE00000G880).

0.7 23 11/14 CKT,BOM,Layout 28,30 -Ca ncel CAP_RST related design reserve to avoid the ESD issuet. <HP/SMsC>. --Del CAP_RST Net and also R60,R605, leave the KBC pin63 (GPIO35) alone as NC.

0.7 24 11/27 CKT,BOM 14,18 -BOM change for C RT EMI and EE SVTP fail issue. <HP/Compal>. --Remove R247,R248,R249 (150_0402); Install C232,C233,C234 (18P_0402); Remove C235,C236,C237 (18P_0402); Change L2,L4,L6

0.7 25 11/27 CKT,BOM 7 -T o fix I NTEL Leakage circuit sequence issue. <HP/Compal>. --Change C26,C27 from 10UF(SE093106M80) to 22UF(SE000000I10); also change the soldering pad from PJP604 to PJP605.

B B

--Change C406 from 150U_B2_6.3VM_R35M (P/N:SGA00002N80) to 220U_6.3V_M (P/N:SF000002Y00).

--Delete USB20_N6/P6 between WLAN slot JP6.36/38 and PCH U7.M22/N22.0.7 2 10/13 CKT,Layout 15,22 -Delete USB 20_N6/P 6 from WLAN slot. WiMAX is dead. <HP>.

--Delete H13 (H_3P0); change H2 from H_4P7 to H_4P4; H28 from H_4P9 to H_4P8.10/19 CKT,Layout 32 -Delete and modify Skew Hole PCB Footprint for M/E Drawing update. <Compal>.

CLK_PCI_DEBUG connection.

--Del R697(0_0201); Add R11(470K_0402) and C7(0.01UF) close to U33 pin3 and pin4. 7

--Design in the isola te circuit on SATA_LED# by add Q79 (2N7002) and R49 (10K) PH close to Docking Connector JP30.39.

C60,C48,C62; C30;

from 0805CS-111XJLC_0805 to 0_0603_5%; Change L1,L3,L5 from 0805CS-111XJLC_0805 to HLC0603CSCC33NJT_0603;
Remove R322,R323,R324 (150_0402_1%); Install C321,C320,C315 (75_0402_1%)

KAT10 from PV-R to Pre-MV LA-5251P REV:0.8 -> 0.9 Modify <2009.12.29.~2010.01.05. >

Item ImpactDate PageRev. Modify DescriptionChange Cause

0.9 1 01/04 CKT,BOM,Layout 30,31 -Need rotate the BIOS Socket for new type one implement without repair and SMT
interfere issue. <Compal>.

0.9 3 --Cancel H17 Screw Hole for M/E design change.01/04 CKT,Layout 32 -Cancel H17 Screw Hole for M/E design change. <Compal>.

40.9 --Add C119 between JP4 pin 37 and 41; Add C120 close to R20.1; Add C145 close to R231 pin 1; Add C146 close to D34 pin 1.-Add Ca ps fo r ESD CBB issue fixed. <Compal>.4,14,28CKT,BOM,Layout01/04

0.9 5 --1. Change L2,L4,L6 PCB Footprint from TAIYO_LB2012T100MR_L2012_2P to R_0603 for final.

01/04 CKT,BOM,Layout 14 -Reduce L1~L6 pack age size for fix repair and SMT issue. <Compal>.

0.9 6 01/05 CKT,BOM,Layout 33 -Add Cut Mode Caps for EMI PCI issue fix. <Compal>. --Add 4 pcs 0.1UF Cut Mode Caps (C666,C667,C671) which located around the canceled Braidwood module. for EMI PCI issue fix.

--1. Cancel 16pin BIOS reserve (Del U36 and R696); 2. Cancel Board ID Detect reserve circuit (Del U8,Q37,R571,R572,R574,R575);

3. Rot ate 8 pin BIOS Socket 90 degree.

--Update PCB Footprint (FOX_QL1044L-D261A1-7H_82P-T) from Compal Server --> No change and same as PV phase.0.9 2 01/04 Layout 29 -To final Foxconn Docking Connector layout footprint. <Compal>.

2. Change L1,L3,L5 from TAIYO_LB2012T100MR_L2012_2P to KC_HLC0603CSCCR11JT_2P for final.

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2010/12/31

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

H/W2 EE Dept. PIR SHEET(2)

LA-5251P

47 47T uesday, J anuary 05, 2 010

1

0.9