Page 1
A
1 1
B
C
D
E
Compal confidential
Schematics Document
Mobile Penryn uFCPGA with Intel
2 2
Cantiga_GM+ICH9-M SFF core logic
Fossil
2009-02-03
3 3
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
C
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Docu ment Number Re v
Custom
D
Date: Sheet
Compal Electronics, Inc.
Cover Sheet
LA-5221P
E
145Tuesday, February 03, 2009
0.1
of
Page 2
A
Compal confidential
File Name : LA-5221P
B
C
D
E
Fossil
Thermal Sensor
1 1
EMC1402
Mobile Penym
LV/ULV Dual Core
uFCPGA-956 CPU - SFF
page 4
page 4,5,6,7
CK505
Clock Generator
ICS9LPRS397
page 15
Accelerometer
LIS302DLTR
page 25
Fan Conn
page 4
Display Port
page 16
LCD conn
page 17
2 2
WWAN Card
USB x1
page 25
USB2.0
H_A#( 3..35)
H_D#(0..63)
Intel Cantiga GS
FCBGA 1363 - SFF
page 8,9,10,11,12,13
FSB
667/800/1066MHz 1.05V
DMI X4
DDR3 800MHz 1.5V
Singal Channel
DDR3-SO-DIMM X 1
BANK 0, 1, 2, 3
BT(SoftBreeze) Conn USB x 1
page 14
page 30
USB conn x 1(For I/O)
PCI-E BUS
Intel ICH9-M
WBMMAP-569 - SFF
page 19,20,21,22
10/100/1000 LAN
Marvelle 88E8072
page 23
WLAN Card
PCIE x1
page 26
USB2.0
CardReader Controller
RealTek RTS5159
SPI
24HST1041A-3
3 3
RJ45 CONN
LED
page 18
page 24
SD/MMC Slot
LPC BUS
SPI ROM
MXIC/MX25L1605AM2C-12G SO8 (2MB)
or
WINBOND/W25X16-VSSIG(2MB)
USB2.0
Azalia
SATA0
page 31
page 30
USB conn x 2(For I/O)
page 28
USB x1(Camara)
page 17
Audio CKT
92HD75B2
2.5" SATA HDD Connector
NAND Flash module(SSD)
page 27
OR
page 20
daughter board
TPA6047
AMP & Audio Jack
page 28
RTC CKT.
page 20
daughter board
SMSC KBC 1091
page 32
Power OK CKT.
page 33
4 4
Power On/Off CKT.
page 34
DC/DC Interface CKT.
page 34
A
B
Touch Pad CONN.
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
Int.KBD
page 29page 29
C
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
D
Title
Size Docu ment Number Re v
Custom
Date: Sheet
Compal Electronics, Inc.
Block Diagram
LA-5221P
E
245Tuesday, February 03, 2009
of
0.1
Page 3
A
Voltage Rails
State
S0
S1
S3
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery
don't exist
1 1
( O MEANS ON X MEANS OFF )
+B
+3VL
power
plane
O
O
O
O
O
X
+5VALW
+3VALW
O
O
O
O
X
+1.8V
+5VS
+3VS
+1.5VS
+0.9V
+VCCP
+CPU_CORE
OO
OO
O
X
XX
X
X
XX X
Symbol Note :
: means Digital Ground
: means Analog Ground
@ : means just reserve , no build
CONN@ : means ME part.
45@ : means install after SMT.
ULV723@ mean CPU ULV723 (U1) for L01
SU9300@ mean CPU SU9300 (U1) for L02
ZZZ1
PCB- MB
U1
CPU
SU9300@
I2C / SMBUS ADDRESSING
DEVICE
DDR SO-DIMM 0
CLOCK GENERA TOR (EXT.)
HEX ADDRESS
A0
D2
1 0 1 0 0 0 0 0
1 1 0 1 0 0 1 0
SMBUS Control Table
SOURCE
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SMB_CK_CLK1
SMB_CK_DAT1 ICH9
LCD_CLK
LCD_DAT
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
A
2005/03/10 2006/03/10
KB926
KB926
Cantiga
Compal Secret Data
Deciphered Date
INVERTER BATT EEPROM
X
VV
X
XX
X
X
XX
SERIAL
THERMAL
SENSOR
(CPU)
XX
V
X
X
XX
Title
Size Docu ment Number Re v
Custom
Date: Sheet
X
X
MINI CARD
XX
X
SODIMM CLK CHIP
X
VVV
XX
Compal Electronics, Inc.
Notes List
LA-5221P
X
LCD
X
X
V
345Tuesday, February 03, 2009
0.1
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Page 4
5
4
3
2
1
XDP Connector
XDP_TDI
TP16PAD
0_0603_5%
R892
C3
1 2
XDP_TMS
XDP_TDO
XDP_BPM#5
XDP_HOOK1
XDP_TRST#
XDP_TCK
XDP_DBRESET#
0.1U_0402_10V6K@
1
2
3
R8
1K_0402_5%
XDP_BPM#4
XDP_BPM#3
XDP_BPM#2
XDP_BPM#1
XDP_BPM#0
TP15PAD
H_PWRGOOD_R
12
FAN_PWM_R
12
R890 3K_0402_5%
+3VS
R896
10K_0402_5%
1 2
1
2
+3VS
+3VS
5
U50
P
INB
O
INA
G
TC7SH00FU_SSOP5
3
TP21PAD
XDP_PRE#
12/22 Follow consumer design
+5VS
4
12
R891 2.2K_0402_5%
for RF, HP 12/10
12
TP10PAD
TP11PAD
TP12PAD
TP13PAD
D D
H_A#[3..16]<8>
H_ADSTB#0<8>
H_A#[17..35]<8>
C C
H_ADSTB#1<8>
H_FERR#<20>
B B
12/22 HP review
Remov e test point
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0<8>
H_REQ#1<8>
H_REQ#2<8>
H_REQ#4<8>
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_A20M#<20>
H_IGNNE#<20>
H_STPCLK#<20>
H_INTR<20>
H_NMI<20>
H_SMI#<20>
U1A
P2
A[3]#
V4
A[4]#
W1
A[5]#
T4
A[6]#
AA1
A[7]#
AB4
A[8]#
T2
A[9]#
AC5
A[10]#
AD2
A[11]#
AD4
A[12]#
AA5
A[13]#
AE5
A[14]#
AB2
A[15]#
AC1
A[16]#
Y4
ADSTB[0]#
R1
REQ[0]#
R5
REQ[1]#
U1
REQ[2]#
P4
REQ[3]#
W5
REQ[4]#
AN1
A[17]#
AK4
A[18]#
AG1
A[19]#
AT4
A[20]#
AK2
A[21]#
AT2
A[22]#
AH2
A[23]#
AF4
A[24]#
AJ5
A[25]#
AH4
A[26]#
AM4
A[27]#
AP4
A[28]#
AR5
A[29]#
AJ1
A[30]#
AL1
A[31]#
AM2
A[32]#
AU5
A[33]#
AP2
A[34]#
AR1
A[35]#
AN5
ADSTB[1]#
C7
A20M#
ICH
D4
FERR#
F10
IGNNE#
F8
STPCLK#
C9
LINT0
C5
LINT1
E5
SMI#
V2
RSVD01
Y2
RSVD02
AG5
RSVD03
AL5
RSVD04
J9
RSVD05
F4
RSVD06
H8
RSVD07
PENRYN SFF_UFCBGA956
ULV723@
ADDR GROUP 0
DEFER#
CONTROL
RESET#
ADDR GROUP 1
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
XDP/ITP SIGNALS
THERMAL
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
H CLK
BCLK[0]
BCLK[1]
ADS#
BNR#
BPRI#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HIT#
HITM#
PRDY#
PREQ#
TCK
TDO
TMS
TRST#
DBR#
TDI
RESERVED
TP22
M4
J5
L5
N5
F38
J1
M2
B40
D8
N1
G5
K2
H4
K4
L1
H2
F2
AY8
BA7
BA5
AY2
AV10
AV2
AV4
AW7
AU1
AW5
AV8
J7
PAD
H_RESET#
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5_R
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#
Place close to U1.
H_ADS# <8>
H_BNR# <8>
H_BPRI# <8>
H_DEFER# <8>
H_DRDY# <8>
H_DBSY# <8>
H_BR0# <8>
H_INIT# <20>
H_LOCK# <8>
H_RS#0 <8>
H_RS#1 <8>
H_RS#2 <8>
H_TRDY# <8>H_REQ#3<8>
H_HIT# <8>
H_HITM# <8>
R13
0_0402_5%
1 2
+VCCP
1 2
XDP_DBRESET# <21>
Place Close to U1.
D38
BB34
BD34
B10
A35
C35
H_PROCHOT#
H_THERMTRIP#
R14 68_0402_5%
1 2
H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil
CLK_CPU_B CLK <15>
CLK_CPU_B CLK# <15>
01/11 HP review
Del R15 and R16(short short net)
H_THERMTRIP# <8,20>
R9
56_0402_5%
02/03
install-->@
R10
51_0402_1%
@
1 2
+VCCP
H_RESET# <8>
XDP_BPM#5
H_THERMDA
H_THERMDC
H_PROCHOT#<42>
H_PW RGOOD<5,20>
H_PROCHOT#
TP14PAD
PWM Fan Control circuit
FAN_PWM<32>
+VCCP
Q21
CBE
123
PMBT3904_SOT2 3
External Thermal Sensor EMC1402
R1 54.9_0402_1%
R2 54.9_0402_1%
R3 54.9_0402_1%
R4 54.9_0402_1%
R5 54.9_0402_1%@
R6 54.9_0402_1%
R7 54.9_0402_1%
TP17 PAD
TP18 PAD
R12
0_0402_5%
1 2
JP2
1
4
2
G1
5
3
G2
ACES_85204-03001
conn@
1 2
1 2
1 2
1 2
1 2
1 2
1 2
This shall place near CPU
TP19 PAD
R11 1K_0402_5%
1 2
TP20 PAD
+VCCP
CLK_CPU_XDP <15>
CLK_CPU_XDP# <15>
H_RESET#H_RESET#_R
2
C4
0.1U_0402_16V4Z
C5 2200P_0402_50V7K
1 2
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
3
MAINPWON
H_THERMTRIP#
2006/02/13 2006/03/10
1 2
R18 0_0402_5%@
Compal Secret Data
1
H_THERMDA
H_THERMDC
Deciphered Date
U2
1
VDD
2
DP
3
DN
4
THERM#
EMC1402-1-ACZL-TR_MSOP8
Put the sensor colse to CPU
2
SMCLK
SMDATA
ALERT#
GND
8
7
6
5
1 2
R17 10K_0402_5%
Title
Size Docu ment Number Re v
Custom
LA-5221P
Date: Sheet
ICH_SM_CLK <1 4,15,21,25>
ICH_SM_DA <1 4,15,21,25>
THERM_SCI# <21>
+3VS
Compal Electronics, Inc.
Penryn(1/3)-AGTL+/ITP-XDP
1
445Tues day, February 03, 2009
0.1
of
Page 5
5
4
3
2
1
H_D#[0..1 5]<8>
D D
H_DSTBN#0<8>
H_DSTBP#0<8>
H_DINV#0<8>
H_D#[16..31]<8>
C C
layout note: Route TEST3 & TEST5 traces on
ground referenced layer to the TPs
H_DSTBN#1<8>
H_DSTBP#1<8>
H_DINV#1<8>
12/17 HP
review
Remov e test point
CPU_BSEL0<15>
CPU_BSEL1<15>
CPU_BSEL2<15>
H_D#0
H_D#1
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1
V_CPU_GTLREF
CPU_BSEL CPU_BSEL2 CPU_BSEL1
B B
166
200
01
0
1
U1B
F40
D[0]#
G43
D[1]#
E43
D[2]#
J43
D[3]#
H40
D[4]#
H44
D[5]#
G39
D[6]#
E41
D[7]#
L41
D[8]#
K44
D[9]#
N41
D[10]#
T40
D[11]#
M40
D[12]#
G41
D[13]#
M44
D[14]#
L43
D[15]#
K40
DSTBN[0]#
J41
DSTBP[0]#
P40
DINV[0]#
P44
D[16]#
V40
D[17]#
V44
D[18]#
AB44
D[19]#
R41
D[20]#
W41
D[21]#
N43
D[22]#
U41
D[23]#
AA41
D[24]#
AB40
D[25]#
AD40
D[26]#
AC41
D[27]#
AA43
D[28]#
Y40
D[29]#
Y44
D[30]#
T44
D[31]#
U43
DSTBN[1]#
W43
DSTBP[1]#
R43
DINV[1]#
AW43
GTLREF
E37
TEST1
D40
TEST2
C43
TEST3
AE41
TEST4
AY10
TEST5
AC43
TEST6
A37
BSEL[0]
C37
BSEL[1]
B38
BSEL[2]
PENRYN SFF_UFCBGA956
ULV723@
CPU_BSEL0
1
0
D[32]#
D[33]#
D[34]#
DATA GROUP 0
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
DATA GROUP 2DATA GROUP 3
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
D[48]#
D[49]#
D[50]#
D[51]#
DATA GROUP 1
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
MISC
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
Cause CPU core power change to
1 phase, and not need support
the pin, leave it as TP. 10/02
H_D#33
AR43
H_D#34H_D#2
AH40
H_D#35
AF40
H_D#36
AJ43
H_D#37
AG41
H_D#38
AF44
H_D#39
AH44
H_D#40
AM44
H_D#41
AN43
H_D#42
AM40
H_D#43
AK40
H_D#44
AG43
H_D#45
AP40
H_D#46
AN41
H_D#47
AL41
H_DSTBN#2
AK44
H_DSTBP#2
AL43
H_DINV#2
AJ41
H_D#48
AV38
H_D#49
AT44
H_D#50
AV40
H_D#51
AU41
H_D#52
AW41
H_D#53
AR41
H_D#54
BA37
H_D#55
BB38
H_D#56
AY36
H_D#57
AT40
H_D#58
BC35
H_D#59
BC39
H_D#60
BA41
H_D#61
BB40
H_D#62
BA35
H_D#63
AU43
H_DSTBN#3
AY40
H_DSTBP#3
AY38
H_DINV#3
BC37
COMP0
AE43
COMP1
AD44
COMP2
AE1
COMP3
AF2
G7
B8
C41
E7
D10
BD10
12/22 HP review
Remov e test point
H_D#32
AP44
H_DPRSTP# <8,20,42>
H_DPSLP# <20>
H_DPWR# <8>
H_PW RGOOD <4,20>
H_CPUSLP# <8>
H_D#[32..47] <8>
H_DSTBN#2 <8>
H_DSTBP#2 <8>
H_DINV#2 <8>
H_D#[48..63] <8>
H_DSTBN#3 <8>
H_DSTBP#3 <8>
H_DINV#3 <8>
R21
R22
R19
R20
12
12
12
12
54.9_0402_1%
27.4_0402_1%
54.9_0402_1%
27.4_0402_1%
Resistor placed within
0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4 mils.
266 0 0 0
+VCC_CORE +VCC_CORE
U1C
F32
VCC[001]
G33
VCC[002]
H32
VCC[003]
J33
VCC[004]
K32
VCC[005]
L33
VCC[006]
M32
VCC[007]
N33
VCC[008]
P32
VCC[009]
R33
VCC[010]
T32
VCC[011]
U33
VCC[012]
V32
VCC[013]
W33
VCC[014]
Y32
VCC[015]
AA33
VCC[016]
AB32
VCC[017]
AC33
VCC[018]
AD32
VCC[019]
AE33
VCC[020]
AF32
VCC[021]
AG33
VCC[022]
AH32
VCC[023]
AJ33
VCC[024]
AK32
VCC[025]
AL33
VCC[026]
AM32
VCC[027]
AN33
VCC[028]
AP32
VCC[029]
AR33
VCC[030]
AT34
VCC[031]
AT32
VCC[032]
AU33
VCC[033]
AV32
VCC[034]
AY32
VCC[035]
BB32
VCC[036]
BD32
VCC[037]
B28
VCC[038]
B30
VCC[039]
B26
VCC[040]
D28
VCC[041]
D30
VCC[042]
F30
VCC[043]
F28
VCC[044]
H30
VCC[045]
H28
VCC[046]
D26
VCC[047]
F26
VCC[048]
H26
VCC[049]
K30
VCC[050]
K28
VCC[051]
M30
VCC[052]
M28
VCC[053]
K26
VCC[054]
M26
VCC[055]
P30
VCC[056]
P28
VCC[057]
T30
VCC[058]
T28
VCC[059]
V30
VCC[060]
V28
VCC[061]
P26
VCC[062]
T26
VCC[063]
V26
VCC[064]
Y30
VCC[065]
Y28
VCC[066]
AB30
VCC[067]
PENRYN SFF_UFCBGA956
ULV723@
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCCP_001
VCCP_002
VCCP_003
VCCP_004
VCCP_005
VCCP_006
VCCP_007
VCCP_008
VCCP_009
VCCP_010
VCCP_011
VCCP_012
VCCP_013
VCCP_014
VCCP_015
VCCP_016
VCCA[01]
VCCA[02]
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
AB28
AD30
AD28
Y26
AB26
AD26
AF30
AF28
AH30
AH28
AF26
AH26
AK30
AK28
AM30
AM28
AP30
AP28
AK26
AM26
AP26
AT30
AT28
AV30
AV28
AY30
AY28
AT26
AV26
AY26
BB30
BB28
BD30
J11
E11
G11
J37
K38
L37
N37
P38
R37
U37
V38
W37
AA37
AB38
AC37
AE37
B34
D34
BD8
BC7
BB10
BB8
BC5
BB4
AY4
VCCSENSE
BD12
VSSSENSE
BC13
Length match within 25 mils.
The trace width/space/other is
20/7/25.
12/22 HP review
Remove 0 ohm
+VCCP
1
+
C6
330U_D2E_2.5VM_R9
2
CPU_VID0 <42>
CPU_VID1 <42>
CPU_VID2 <42>
CPU_VID3 <42>
CPU_VID4 <42>
CPU_VID5 <42>
CPU_VID6 <42>
VCCSENSE <42>
VSSSENSE <42>
1
C7
2
10U_0805_6.3V6M
0.01U_0402_16V7K
Near pin B34
Change to 330u_R9,
casue high
limitation. 12/14
+1.5VS
1
C8
Near pin D34
2
+VCC_CORE
R23
1 2
+VCCP
12
R25
1K_0402_1%
V_CPU_GTLREF
A A
12
R26
2K_0402_1%
100_0402_1%
R24
1 2
100_0402_1%
Close to CPU pin
within 500mils.
VCCSENSE
VSSSENSE
Close to CPU pin AW43
within 500mils.
5
4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
2
Title
Size Docu ment Number Re v
Custom
Date: Sheet
Compal Electronics, Inc.
Penryn(2/3)-AGTL+/ITP-XDP
LA-5221P
1
545Tues day, February 03, 2009
of
0.1
Page 6
5
D D
AL37
AN37
AP38
B32
C33
D32
E35
E33
F34
G35
F36
H36
J35
L35
N35
K36
R35
U35
P36
V36
W35
AA35
AC35
AB36
AE35
AG35
VCCP_040
VCC_120
AJ35
VCCP_041
VCCP_042
VCCP_043
VCCP_044
VCCP_045
VCCP_046
VCC_121
VCC_122
VCC_123
VCC_124
VCC_125
VCC_126
V22
Y24
Y22
AB24
AB22
AD24
AD22
C C
VCCP_021
VCCP_022
VCCP_023
VCCP_024
VCCP_025
VCCP_026
VCCP_027
VCCP_028
VCCP_029
VCCP_030
VCCP_031
VCCP_032
VCCP_033
VCCP_034
VCCP_035
VCCP_036
VCCP_037
VCCP_038
ULV723@
VCC_101
VCC_102
VCC_103
VCC_104
VCC_105
VCC_106
VCC_107
VCC_108
VCC_109
VCC_110
VCC_111
VCC_112
F24
F22
B22
B24
BB26
BD28
BD26
K24
D22
D24
H24
H22
VCCP_039
VCC_113
VCC_114
VCC_115
VCC_116
VCC_117
VCC_118
VCC_119
T24
T22
K22
P24
P22
V24
M24
M22
VCCP_047
VCC_127
AF36
AF24
VCCP_048
VCC_128
AL35
VCCP_049
VCC_129
AF22
4
AN35
AK36
AP36
B12
B14
C13
D12
D14
E13
F14
F12
G13
H14
H12
J13
K14
K12
L13
L11
M14
N13
N11
K10
P14
P12
R13
R11
T14
U13
U11
V14
V12
VCCP_050
VCCP_051
VCCP_052
VCCP_053
VCCP_054
VCCP_055
VCCP_056
VCCP_057
VCCP_058
VCCP_059
VCCP_060
VCCP_061
VCCP_062
VCCP_063
VCCP_064
VCCP_065
VCCP_066
VCCP_067
VCCP_068
VCCP_069
VCCP_070
VCCP_071
VCCP_072
VCCP_073
VCCP_074
VCCP_075
VCCP_076
VCCP_077
VCCP_078
VCCP_079
VCCP_080
VCCP_081
VCC_130
VCC_131
VCC_132
VCC_133
VCC_134
VCC_135
VCC_136
VCC_137
VCC_138
VCC_139
VCC_140
VCC_141
VCC_142
VCC_143
VCC_144
VCC_145
VCC_146
VCC_147
VCC_148
VCC_149
VCC_150
VCC_151
VCC_152
VCC_153
VCC_154
VCC_155
VCC_156
VCC_157
VCC_158
VCC_159
VCC_160
VCC_161
F18
F16
B16
B18
B20
AT24
AK24
AH24
AH22
AT22
AK22
AP24
AP22
AV24
AV22
AY24
AY22
AM24
AM22
BB24
D16
BB22
BD24
BD22
F20
K18
D18
K16
H18
H16
D20
H20
W13
M18
VCCP_082
VCC_162
W11
M16
VCCP_083
VCC_163
3
P10
V10
Y14
AA13
AA11
AB14
AB12
AC13
AC11
AD14
AB10
AE13
AE11
AF14
AF12
AG13
AG11
AH14
AJ13
AJ11
AF10
AK14
AK12
AL13
AL11
AN13
AN11
AP12
AR13
AR11
AK10
AP10
AU13
VCCP_084
VCCP_085
VCCP_086
VCCP_087
VCCP_088
VCCP_089
VCCP_090
VCCP_091
VCCP_092
VCCP_093
VCCP_094
VCCP_095
VCCP_096
VCCP_097
VCCP_098
VCCP_099
VCCP_100
VCCP_101
VCCP_102
VCCP_103
VCCP_104
VCCP_105
VCCP_106
VCCP_107
VCCP_108
VCCP_109
VCCP_110
VCCP_111
VCCP_112
VCCP_113
VCCP_114
VCCP_115
VCC_164
VCC_165
VCC_166
VCC_167
VCC_168
VCC_169
VCC_170
VCC_171
VCC_172
VCC_173
VCC_174
VCC_175
VCC_176
VCC_177
VCC_178
VCC_179
VCC_180
VCC_181
VCC_182
VCC_183
VCC_184
VCC_185
VCC_186
VCC_187
VCC_188
VCC_189
VCC_190
VCC_191
VCC_192
VCC_193
VCC_194
VCC_195
T18
T16
K20
P18
M20
T20
P16
V18
V16
P20
V20
Y18
Y16
Y20
AF18
AF16
AB18
AB16
AD18
AD16
AF20
AB20
AD20
AK18
AK16
AP18
AP16
AH18
AH16
AH20
AK20
AM18
AM16
2
AU11
VCCP_116
VCCP_117
VCCP_118L9VCCP_119L7VCCP_120N9VCCP_121N7VCCP_122R9VCCP_123R7VCCP_124U9VCCP_125U7VCCP_126W9VCCP_127W7VCCP_128
VCC_196
VCC_197
VCC_198
VCC_199
VCC_200
VCC_201
VCC_202
VCC_203
VCC_204
AT18
AT16
AP20
AV18
AV16
AY18
AM20
AY16
AT20
VCC_205
1
+VCCP
AA9
AA7
AC9
AC7
AE9
AE7
AG9
AG7
AJ9
AJ7
AL9
AL7
AN9
AN7
AR9
AR7
A33
A13
U1F
PENRYN SFF_UFCBGA956
VCCP_129
VCCP_130
VCCP_131
VCCP_132
VCCP_133
VCCP_134
VCCP_135
VCCP_136
VCCP_137
VCCP_138
VCCP_139
VCCP_140
VCCP_141
VCCP_142
VCCP_143
VCCP_144
VCCP_145
VCC_206
VCC_207
VCC_208
VCC_209
VCC_210
VCC_211
VCC_212
VCC_213
VCC_214
VCC_215
VCC_216
VCC_217
VCC_218
VCC_219
VCC_220
VCCP_020
VCCP_018
VCCP_019
VCCP_017
AV20
AY20
BB18
BB16
AT14
BB20
AP14
BD18
AV14
BD16
BD20
AM14
AJ37
AF38
AY14
BB14
AK38
BD14
AG37
+VCC_CORE +VCCP
B B
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Docu ment Number Re v
Custom
2
Date: Sheet
Compal Electronics, Inc.
Penryn(3/3)-Power
LA-5221P
1
645Tues day, February 03, 2009
0.1
of
Page 7
5
U1D
B42
VSS[001]
F44
VSS[002]
D44
VSS[003]
D42
VSS[004]
F42
VSS[005]
H42
VSS[006]
K42
VSS[007]
M42
VSS[008]
P42
VSS[009]
T42
VSS[010]
V42
VSS[011]
Y42
D D
C C
B B
A A
VSS[012]
AB42
VSS[013]
AD42
VSS[014]
AF42
VSS[015]
AH42
VSS[016]
AK42
VSS[017]
AM42
VSS[018]
AP42
VSS[019]
AY44
VSS[020]
AV44
VSS[021]
AT42
VSS[022]
AV42
VSS[023]
AY42
VSS[024]
BA43
VSS[025]
BB42
VSS[026]
C39
VSS[027]
E39
VSS[028]
G37
VSS[029]
H38
VSS[030]
J39
VSS[031]
L39
VSS[032]
M38
VSS[033]
N39
VSS[034]
R39
VSS[035]
T38
VSS[036]
U39
VSS[037]
W39
VSS[038]
Y38
VSS[039]
AA39
VSS[040]
AC39
VSS[041]
AD38
VSS[042]
AE39
VSS[043]
AG39
VSS[044]
AH38
VSS[045]
AJ39
VSS[046]
AL39
VSS[047]
AM38
VSS[048]
AN39
VSS[049]
AR39
VSS[050]
AR37
VSS[051]
AT38
VSS[052]
AU39
VSS[053]
AU37
VSS[054]
AW39
VSS[055]
AW37
VSS[056]
BA39
VSS[057]
BC41
VSS[058]
BD40
VSS[059]
BD38
VSS[060]
B36
VSS[061]
H34
VSS[062]
D36
VSS[063]
K34
VSS[064]
M34
VSS[065]
M36
VSS[066]
P34
VSS[067]
T34
VSS[068]
V34
VSS[069]
T36
VSS[070]
Y34
VSS[071]
AB34
VSS[072]
AD34
VSS[073]
Y36
VSS[074]
AD36
VSS[075]
AF34
VSS[076]
AH34
VSS[077]
AH36
VSS[078]
AK34
VSS[079]
AM34
VSS[080]
AP34
VSS[081]
PENRYN SFF_UFCBGA956
ULV723@
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
5
AM36
AR35
AU35
AV34
AW35
AW33
AY34
AT36
AV36
BA33
BC33
BB36
BD36
C27
C29
C31
E29
E27
G29
G27
E31
G31
J29
J27
L29
L27
N29
N27
J31
L31
N31
R29
R27
U29
U27
R31
U31
W29
W27
W31
AA29
AA27
AC29
AC27
AA31
AC31
AE29
AE27
AG29
AG27
AJ29
AJ27
AE31
AG31
AJ31
AL29
AL27
AN29
AN27
AL31
AN31
AR29
AR27
AR31
AU29
AU27
AW29
AW27
AU31
AW31
BA29
BA27
BC29
BC27
BA31
BC31
C21
C23
C25
E25
E23
E21
U1E
G25
VSS_164
G23
VSS_165
G21
VSS_166
J25
VSS_167
J23
VSS_168
J21
VSS_169
L25
VSS_170
L23
VSS_171
L21
VSS_172
N25
VSS_173
N23
VSS_174
N21
VSS_175
R25
VSS_176
R23
VSS_177
R21
VSS_178
U25
VSS_179
U23
VSS_180
U21
VSS_181
W25
VSS_182
W23
VSS_183
W21
VSS_184
AA25
VSS_185
AA23
VSS_186
AA21
VSS_187
AC25
VSS_188
AC23
VSS_189
AC21
VSS_190
AE25
VSS_191
AE23
VSS_192
AE21
VSS_193
AG25
VSS_194
AG23
VSS_195
AG21
VSS_196
AJ25
VSS_197
AJ23
VSS_198
AJ21
VSS_199
AL25
VSS_200
AL23
VSS_201
AL21
VSS_202
AN25
VSS_203
AN23
VSS_204
AN21
VSS_205
AR25
VSS_206
AR23
VSS_207
AR21
VSS_208
AU25
VSS_209
AU23
VSS_210
AU21
VSS_211
AW25
VSS_212
AW23
VSS_213
AW21
VSS_214
BA25
VSS_215
BA23
VSS_216
BA21
VSS_217
BC25
VSS_218
BC23
VSS_219
BC21
VSS_220
C17
VSS_221
C19
VSS_222
E19
VSS_223
E17
VSS_224
G19
VSS_225
G17
VSS_226
J19
VSS_227
J17
VSS_228
L19
VSS_229
L17
VSS_230
N19
VSS_231
N17
VSS_232
R19
VSS_233
R17
VSS_234
U19
VSS_235
U17
VSS_236
W19
VSS_237
W17
VSS_238
AA19
VSS_239
AA17
VSS_240
AC19
VSS_241
AC17
VSS_242
AE19
VSS_243
AE17
VSS_244
AG19
VSS_245
AG17
VSS_246
AJ19
VSS_247
AJ17
VSS_248
AL19
VSS_249
AL17
VSS_250
AN19
VSS_251
AN17
VSS_252
AR19
VSS_253
AR17
VSS_254
AU19
VSS_255
AU17
VSS_256
AW19
VSS_257
AW17
VSS_258
BA19
VSS_259
BA17
VSS_260
BC19
VSS_261
BC17
VSS_262
C11
VSS_263
C15
VSS_264
E15
VSS_265
G15
VSS_266
H10
VSS_267
M12
VSS_268
J15
VSS_269
L15
VSS_270
N15
VSS_271
M10
VSS_272
T12
VSS_273
R15
VSS_274
U15
VSS_275
W15
VSS_276
T10
VSS_277
Y12
VSS_278
AD12
VSS_279
PENRYN SFF_UFCBGA956
ULV723@
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
VSS_361
VSS_362
VSS_363
VSS_364
VSS_365
VSS_366
VSS_367
VSS_368
VSS_369
VSS_370
VSS_371
VSS_372
VSS_373
VSS_374
VSS_375
VSS_376
VSS_377
VSS_378
VSS_379
VSS_380
VSS_381
VSS_382
VSS_383
VSS_384
VSS_385
VSS_386
VSS_387
VSS_388
VSS_389
VSS_390
VSS_391
VSS_392
VSS_393
VSS_394
VSS_395
AA15
AC15
Y10
AD10
AH12
AE15
AG15
AJ15
AH10
AM12
AL15
AN15
AR15
AM10
AT12
AV12
AW13
AW11
AY12
AU15
AW15
AT10
BA13
BA11
BB12
BC11
BA15
BC15
B6
D6
E9
F6
G9
H6
K8
K6
M8
M6
P8
P6
T8
T6
V8
V6
U5
Y8
Y6
AB8
AB6
AD8
AD6
AF8
AF6
AH8
AH6
AK8
AK6
AM8
AM6
AP8
AP6
AT8
AT6
AU9
AV6
AU7
AW9
AY6
BA9
BB6
BC9
BD6
B4
C3
E3
G3
J3
L3
N3
R3
U3
W3
AA3
AC3
AE3
AG3
AJ3
AL3
AN3
AR3
AU3
AW3
BA3
BC3
D2
E1
G1
AW1
BA1
BB2
A41
A39
A29
A27
A31
A25
A23
A21
A19
A17
A11
A15
A7
A5
A9
BD4
4
+VCC_CORE
10U_0805_6.3V6M
1
C9
2
+VCC_CORE
1U_0402_6.3V6K
1
C33
2
Mid Frequence Decoupling
10U_0805_6.3V6M
10U_0805_6.3V6M
1
1
C11
C10
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
C35
C34
2
2
3
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C13
C12
2
High Frequence Decoupling
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C37
C36
2
10U_0805_6.3V6M
10U_0805_6.3V6M
1
1
C15
C14
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
C38
C39
2
2
10U_0805_6.3V6M
10U_0805_6.3V6M
1
2
1
2
1
1
C17
C16
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
C41
C40
2
2
2
10U_0805_6.3V6M
C18
1U_0402_6.3V6K
C42
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C19
2
1U_0402_6.3V6K
1
C43
2
10U_0805_6.3V6M
1
1
C20
C21
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
C44
C45
2
2
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
1
1
C23
C22
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
C46
2
C47
2
10U_0603_6.3V6M
1
1
C24
C25
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
C48
C49
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C26
2
1U_0402_6.3V6K
1
C50
2
10U_0603_6.3V6M
1
1
2
1
2
1
C27
C28
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
C51
C52
2
2
1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C30
C29
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C54
C53
2
10U_0603_6.3V6M
1
1
2
1
2
1
C31
C32
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
C56
C55
2
2
6/14 :Replace 12pcs 10uF_0805 to 24 pcs 1uF_0402 for CPU transient fail issue.
ESR <= 1.5m ohm
Near CPU CORE regulator
+VCC_CORE
220U_D2_2VK_R9
1
1
+
+
C58
C57
2
2
Del C37 to improve power plan. 6/14
+VCCP
1U_0603_10V4Z
1U_0603_10V4Z
1
C60
C61
2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
3
2006/02/13 2006/03/10
1U_0603_10V4Z
1
1
C62
2
2
Compal Secret Data
1U_0603_10V4Z
1U_0603_10V4Z
1
1
C63
C64
2
2
Deciphered Date
1U_0603_10V4Z
C65
220U_D2_2VK_R9
220U_D2_2VK_R9
1
+
C59
2
1U_0603_10V4Z
1
C66
2
1U_0603_10V4Z
1
C67
2
2
1U_0603_10V4Z
1U_0603_10V4Z
1
1
C68
C69
2
2
1U_0603_10V4Z
1U_0603_10V4Z
1
2
1
1
C71
C70
2
2
Title
Size Docu ment Number Re v
Custom
Date: Sheet
Compal Electronics, Inc.
Penryn(3/3)-GND/Bypass
LA-5221P
1
745Tues day, February 03, 2009
0.1
of
Page 8
5
H_D#[0..6 3]<5>
D D
C C
H_RESET#<4>
H_CPUSLP#<5>
B B
H_VREF
1
C79
2
0.1U_0402_16V4Z
@
Trace < = 500mils
layout note:
Route H_SCOMP and H_SCOMP# with trace width,
spacing and impedance (55 ohm) same as FSB data
traces
Layout Note:
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20
+VCCP
12
R44
1K_0402_1%
12
A A
R482K_0402_1%
within 100 mils from NB
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_SWNG
H_RCOMP
H_VREF
H_RCOMP
12
R49
24.9_0402_1%
5
U4A
J7
H_D#_0
H6
H_D#_1
L11
H_D#_2
J3
H_D#_3
H4
H_D#_4
G3
H_D#_5
K10
H_D#_6
K12
H_D#_7
L1
H_D#_8
M10
H_D#_9
M6
H_D#_10
N11
H_D#_11
L7
H_D#_12
K6
H_D#_13
M4
H_D#_14
K4
H_D#_15
P6
H_D#_16
W9
H_D#_17
V6
H_D#_18
V2
H_D#_19
P10
H_D#_20
W7
H_D#_21
N9
H_D#_22
P4
H_D#_23
U9
H_D#_24
V4
H_D#_25
U1
H_D#_26
W3
H_D#_27
V10
H_D#_28
U7
H_D#_29
W11
H_D#_30
U11
H_D#_31
AC11
H_D#_32
AC9
H_D#_33
Y4
H_D#_34
Y10
H_D#_35
AB6
H_D#_36
AA9
H_D#_37
AB10
H_D#_38
AA1
H_D#_39
AC3
H_D#_40
AC7
H_D#_41
AD12
H_D#_42
AB4
H_D#_43
Y6
H_D#_44
AD10
H_D#_45
AA11
H_D#_46
AB2
H_D#_47
AD4
H_D#_48
AE7
H_D#_49
AD2
H_D#_50
AD6
H_D#_51
AE3
H_D#_52
AG9
H_D#_53
AG7
H_D#_54
AE11
H_D#_55
AK6
H_D#_56
AF6
H_D#_57
AJ9
H_D#_58
AH6
H_D#_59
AF12
H_D#_60
AH4
H_D#_61
AJ7
H_D#_62
AE9
H_D#_63
B6
H_SWING
D4
H_RCOMP
J11
H_CPURST#
G9
H_CPUSLP#
L17
H_AVREF
K18
H_DVREF
CANTIGA GMCH SFF_FCBGA1363
+VCCP
12
R45
221_0603_1%
12
100_0402_1%
R50
H_SWNG
1
C80
2
0.1U_0402_16V4Z
Near B6 pin
H_ADSTB#_0
H_ADSTB#_1
H_BREQ#
H_DEFER#
HOST
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
layout note:
Place them close to U4 pin BC51.
Layout Note: V_DDR_MCH_REF trace
width and spacing is 20/20.
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_ADS#
H_BNR#
H_BPRI#
H_DBSY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_RS#_0
H_RS#_1
H_RS#_2
4
H_A#3
L15
H_A#4
B14
H_A#5
C15
H_A#6
D12
H_A#7
F14
H_A#8
G17
H_A#9
B12
H_A#10
J15
H_A#11
D16
H_A#12
C17
H_A#13
D14
H_A#14
K16
H_A#15
F16
H_A#16
B16
H_A#17
C21
H_A#18
D18
H_A#19
J19
H_A#20
J21
H_A#21
B18
H_A#22
D22
H_A#23
G19
H_A#24
J17
H_A#25
L21
H_A#26
L19
H_A#27
G21
H_A#28
D20
H_A#29
K22
H_A#30
F18
H_A#31
K20
H_A#32
F20
H_A#33
F22
H_A#34
B20
H_A#35
A19
F10
A15
C19
C9
B8
C11
E5
D6
AH10
AJ11
G11
H2
C7
F8
A11
D8
L9
N7
AA7
AG3
K2
N3
AA3
AF4
L3
M2
Y2
AF2
J13
L13
C13
G13
G15
F4
F2
G7
01/05 HP review
Del PM_EXTTS#0 and contact J39 L39
V_DDR_MCH_REF<14>
PM_EXTTS#0
R52 10K_0402_5%
4
V_DDR_MCH_REF
1 2
H_A#[3..35] <4>
H_ADS# <4>
H_ADSTB#0 <4>
H_ADSTB#1 <4>
H_BNR# <4>
H_BPRI# <4>
H_BR0# <4>
H_DEFER# <4>
H_DBSY# <4>
CLK_MCH_BCLK <15>
CLK_MCH_BCLK# <15>
H_DPWR# <5>
H_DRDY# <4>
H_HIT# <4>
H_HITM# <4>
H_LOCK# <4>
H_TRDY# <4>
H_DINV#0 <5>
H_DINV#1 <5>
H_DINV#2 <5>
H_DINV#3 <5>
H_DSTBN#0 <5>
H_DSTBN#1 <5>
H_DSTBN#2 <5>
H_DSTBN#3 <5>
H_DSTBP#0 <5>
H_DSTBP#1 <5>
H_DSTBP#2 <5>
H_DSTBP#3 <5>
H_REQ#0 <4>
H_REQ#1 <4>
H_REQ#2 <4>
H_REQ#3 <4>
H_REQ#4 <4>
H_RS#0 <4>
H_RS#1 <4>
H_RS#2 <4>
H_THERMTRIP#<4,20>
PM_DPRSLPVR<21,42>
02/02 DDR3 power
C78
1
2
0.1U_0402_16V4Z
+3VS
3
TCK
TDI
TDO
TMS
+3VS
R28
1 2
R27
1 2
R29 4.7K_0402_5%@
1 2
R30 1K_0402_5% @
1 2
1K_0402_5% @
4.7K_0402_5%@
Close to U4
02/02 DDR3 power
+1.5V
1
1
C73
0.01U_0402_25V7K
2
1
C75
2
0.01U_0402_25V7K
MCH_CLKSEL0<15>
MCH_CLKSEL1<15>
MCH_CLKSEL2<15>
3
12
R31
1K_0402_1%
12
R34
3.01K_0402_1%
12
R37
1K_0402_1%
CFG20<10>
PM_EXTTS#0
R38 0_0402_5%
1 2
R39 100_0402_1%
1 2
C760.1U_0402_16V4Z @
1
2
2006/02/13 2006/03/10
C72
2.2U_0603_6.3V4Z
2
SMRCOMP_VOH
SMRCOMP_VOL
1
C74
2
2.2U_0 603_6.3V4Z
12/29 HP review
Remove some CFG net
PM_BMBUSY#<21>
H_DPRSTP#<5,20,42>
PM_EXTTS#0<14>
PM_PWROK<21,32,42>
PLT_RST#<19,23,25,31>
1 2
R40 0_0402_5%
Add R428 in 9/26
+1.5V
12
R43
10K_0402_1%
12
R46
10K_0402_1%
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
U4B
J43
RSVD1
L43
RSVD2
J41
RSVD3
L41
RSVD4
AN11
RSVD5
AM10
RSVD6
AK10
RSVD7
AL11
RSVD8
F12
RSVD9
AN45
RSVD10
AP44
RSVD11
AT44
RSVD12
AN47
RSVD13
C27
RSVD14
D30
RSVD15
J9
RSVD17
AW42
RSVD20
BB20
RSVD22
BE19
RSVD23
BF20
RSVD24
BF18
RSVD25
K26
CFG_0
G23
CFG_1
G25
CFG_2
J25
CFG_3
L25
CFG_4
L27
CFG_5
F24
CFG_6
D24
CFG_7
D26
CFG_8
J23
CFG_9
B26
CFG_10
A23
CFG_11
C23
CFG_12
B24
CFG_13
B22
CFG_14
K24
CFG_15
C25
CFG_16
L23
CFG_17
L33
CFG_18
K32
CFG_19
K34
CFG_20
J35
PM_SYNC#
F6
PM_DPRSTP#
J39
PM_EXT_TS#_0
L39
PM_EXT_TS#_1
AY39
PWROK
BB18
RSTIN#
K28
THERMTRIP#
K36
DPRSLPVR
A7
NC_1
A49
NC_2
A52
NC_3
A54
NC_4
B54
NC_5
D55
NC_6
G55
NC_7
BE55
NC_8
BH55
NC_9
BK55
NC_10
BK54
NC_11
BL54
NC_12
BL52
NC_13
BL49
NC_14
BL7
NC_15
BL4
NC_16
BL2
NC_17
BK2
NC_18
BK1
NC_19
BH1
NC_20
BE1
NC_21
G1
NC_22
Compal Secret Data
CANTIGA GMCH SFF_FCBGA1363
Deciphered Date
CFGRSVD
PM
NC
2
BB32
SA_CK_0
BA25
SA_CK_1
BA33
SB_CK_0
BA23
SB_CK_1
BA31
SA_CK#_0
BC25
SA_CK#_1
BC33
SB_CK#_0
BB24
SB_CK#_1
BC35
SA_CKE_0
BE33
SA_CKE_1
BE37
SB_CKE_0
BC37
SB_CKE_1
BK18
SA_CS#_0
BK16
SA_CS#_1
BE23
SB_CS#_0
BC19
SB_CS#_1
BJ17
SA_ODT_0
BJ19
SA_ODT_1
BC17
SB_ODT_0
BE17
SB_ODT_1
SM_RCOMP
SM_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#
DPLL_REF_CLK
DPLL_REF_CLK#
DDR CLK/ CONTROL/COMPENSATION
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
PEG_CLK
PEG_CLK#
CLK
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI
DMI_TXP_2
DMI_TXP_3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
GFX_VR_EN
BL25
BK26
BK32
BL31
BC51
AY37
BH20
BA37
B42
D42
B50
D50
R49
P50
AG55
AL49
AH54
AL47
AG53
AK50
AH52
AL45
AG49
AJ49
AJ47
AG47
AF50
AH50
AJ45
AG45
G33
G37
F38
F36
G35
G39
SMRCOMP
SMRCOMP#
SMRCOMP_VOH
SMRCOMP_VOL
V_DDR_MCH_REF
SM_PWROK
SM_REXT
SM_DRAMRS T#
CLK_MCH_DREFCLK <15>
CLK_MCH_DREFCLK# <15>
MCH_SSCDREFCLK <15>
MCH_SSCDREFCLK# <15>
CLK_MCH_3GPLL <15>
CLK_MCH_3GPLL# <15>
DMI_TXN0 <21>
DMI_TXN1 <21>
DMI_TXN2 <21>
DMI_TXN3 <21>
DMI_TXP0 <21>
DMI_TXP1 <21>
DMI_TXP2 <21>
DMI_TXP3 <21>
DMI_RXN0 <21>
DMI_RXN1 <21>
DMI_RXN2 <21>
DMI_RXN3 <21>
DMI_RXP0 <21>
DMI_RXP1 <21>
DMI_RXP2 <21>
DMI_RXP3 <21>
DFG T_VID_0 <44>
DFG T_VID_1 <44>
DFG T_VID_2 <44>
DFG T_VID_3 <44>
DFG T_VID_4 <44>
GFXVR_EN <44>
GRAPHICS VID
AK52
CL_CLK
AK54
CL_DATA
AW40
CL_PWROK
AL53
2
ME
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
MISC
HDA
CL_RST#
CL_VREF
CLKREQ#
ICH_SYNC#
TSATN#
HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC
CL_VREF
AL55
F34
F32
B38
A37
C31
K42
TSATN#
D10
C29
B30
D28
A27
B28
R47 54.9_0402_1%
1 2
Title
Size Docu ment Number Re v
Custom
Date: Sheet
Compal Electronics, Inc.
Cantiga(1/6)-AGTL/DMI/DDR
LA-5221P
1
M_CLK_DDR0 <14>
M_CLK_DDR1 <14>
M_CLK_DDR#0 <14>
M_CLK_DDR#1 <14>
DDR_CKE0_DIMMA <14>
DDR_CKE1_DIMMA <14>
DDR_CS0_DIMMA# <14>
DDR_CS1_DIMMA# <14>
M_ODT0 <14>
M_ODT1 <14>
R32 80.6_0402_1%
1 2
R33 80.6_0402_1%
1 2
R35 10K_0402_1%
1 2
R36 499_0402_1%
1 2
SM_DRAMRST# <14>
CL_CLK0 <21>
CL_DATA0 <21>
PM_PWROK <21,32,42>
CL_RST# <21>
0.1U_0402_16V4Z
CLKREQ#_B <15>
MCH_ICH_SYNC# <21>
12/12 HP review
+1.05VM-->+VCCP
1
C77
2
1
02/02 DDR3 power
+VCCP
+VCCP
845Tuesday, February 03, 2009
+1.5V
12
R41
1K_0402_1%
12
R42
511_0402_1%
of
0.1
Page 9
5
D D
DDR_A_D[0..63]<14>
C C
B B
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
U4D
AP46
SA_DQ_0
AU47
SA_DQ_1
AT46
SA_DQ_2
AU49
SA_DQ_3
AR45
SA_DQ_4
AN49
SA_DQ_5
AV50
SA_DQ_6
AP50
SA_DQ_7
AW47
SA_DQ_8
BD50
SA_DQ_9
AW49
SA_DQ_10
BA49
SA_DQ_11
BC49
SA_DQ_12
AV46
SA_DQ_13
BA47
SA_DQ_14
AY50
SA_DQ_15
BF46
SA_DQ_16
BC47
SA_DQ_17
BF50
SA_DQ_18
BF48
SA_DQ_19
BC43
SA_DQ_20
BE49
SA_DQ_21
BA43
SA_DQ_22
BE47
SA_DQ_23
BF42
SA_DQ_24
BC39
SA_DQ_25
BF44
SA_DQ_26
BF40
SA_DQ_27
BB40
SA_DQ_28
BE43
SA_DQ_29
BF38
SA_DQ_30
BE41
SA_DQ_31
BA15
SA_DQ_32
BE11
SA_DQ_33
BE15
SA_DQ_34
BF14
SA_DQ_35
BB14
SA_DQ_36
BC15
SA_DQ_37
BE13
SA_DQ_38
BF16
SA_DQ_39
BF10
SA_DQ_40
BC11
SA_DQ_41
BF8
SA_DQ_42
BG7
SA_DQ_43
BC7
SA_DQ_44
BC9
SA_DQ_45
BD6
SA_DQ_46
BF12
SA_DQ_47
AV6
SA_DQ_48
BB6
SA_DQ_49
AW7
SA_DQ_50
AY6
SA_DQ_51
AT10
SA_DQ_52
AW11
SA_DQ_53
AU11
SA_DQ_54
AW9
SA_DQ_55
AR11
SA_DQ_56
AT6
SA_DQ_57
AP6
SA_DQ_58
AL7
SA_DQ_59
AR7
SA_DQ_60
AT12
SA_DQ_61
AM6
SA_DQ_62
AU7
SA_DQ_63
CANTIGA GMCH SFF_FCBGA1363
DDR SYSTEM MEMORY A
SA_BS_0
SA_BS_1
SA_BS_2
SA_RAS#
SA_CAS#
SA_WE#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
4
BC21
BJ21
BJ41
BH22
BK20
BL15
AT50
BB50
BB46
BE39
BB12
BE7
AV10
AR9
AR47
BA45
BE45
BC41
BC13
BB10
BA7
AN7
AR49
AW45
BC45
BA41
BA13
BA11
BA9
AN9
BC23
BF22
BE31
BC31
BH26
BJ35
BB34
BH32
BB26
BF32
BA21
BG25
BH34
BH18
BE25
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_BS0 <14>
DDR_A_BS1 <14>
DDR_A_BS2 <14>
DDR_A_RAS# <14>
DDR_A_CAS# <14>
DDR_A_WE# <14>
DDR_A_DM[0..7] <14>
DDR_A_DQS[0..7] <14>
DDR_A_DQS#[0..7] <14>
DDR_A_MA[0..14] <14>
3
U4E
AP54
AM52
AR55
AV54
AM54
AN53
AT52
AU53
AW53
AY52
BB52
BC53
AV52
AW55
BD52
BC55
BF54
BE51
BH48
BK48
BE53
BH52
BK46
BJ47
BL45
BJ45
BL41
BH44
BH46
BK44
BK40
BJ39
BK10
BH10
BK6
BH6
BJ9
BL11
BG5
BJ5
BG3
BF4
BD4
BA3
BE5
BF2
BB4
AY4
BA1
AP2
AU1
AT2
AT4
AV4
AU3
AR3
AN1
AP4
AL3
AJ1
AK4
AM4
AH2
AK2
CANTIGA GMCH SFF_FCBGA1363
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
2
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
DDR SYSTEM MEMORY B
SB_BS_0
SB_BS_1
SB_BS_2
SB_RAS#
SB_CAS#
SB_WE#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
BJ13
BK12
BK38
BE21
BH14
BK14
AP52
AY54
BJ49
BJ43
BH12
BD2
AY2
AJ3
AR53
BA53
BH50
BK42
BH8
BB2
AV2
AM2
AT54
BB54
BJ51
BH42
BK8
BC3
AW3
AN3
BJ15
BJ33
BH24
BA17
BF36
BH36
BF34
BK34
BJ37
BH40
BH16
BK36
BH38
BJ11
BL37
1
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Docu ment Number Re v
Custom
2
Date: Sheet
Compal Electronics, Inc.
Cantiga(2/6)-DDR2 A/B CH
LA-5221P
1
945Tuesday, February 03, 2009
0.1
of
Page 10
5
4
3
2
1
Strap Pin Table
Place R53 <500mils to U4 pin U45&T44.
U4C
BLON_PWM<17>
ENABLT<17>
+3VS
D D
1/2 Follow intel check list
4.22K-->2.4K
C C
B B
DDC2_CLK<17>
DDC2_DATA<17>
ENAVDD<17>
TXCLK_L-<17>
TXCLK_L+<17>
TXOUT_L0-<17>
TXOUT_L1-<17>
TXOUT_L2-<17>
TXOUT_L0+<17>
TXOUT_L1+<17>
TXOUT_L2+<17>
For make layout clearance, del
TP for channel B. 10/18
12/219 HP review
No TV out and contact to GND
12/19 HP review
CMOS buffers and can be left as NC
12/19 HP review
No CRT out and contact to GND
12/19 HP review
CMOS buffers and can be left as NC
Close to pin D32 and keep
30mil space to other
part/trace.
R54 10K_0402_5%
1 2
1 2
1 2
T4
R55 10K_0402_5%
R56 2.4K_0402_1%
10/18
10/19
10/19
1.02K_0402_1%
D38
L_BKLT_CTRL
C37
L_BKLT_EN
K38
L_CTRL_CLK
L37
L_CTRL_DATA
J37
L_DDC_CLK
L35
L_DDC_DATA
B36
L_VDD_EN
F50
LVDS_IBG
H46
LVDS_VBG
P44
LVDS_VREFH
K46
LVDS_VREFL
D46
LVDSA_CLK#
B46
LVDSA_CLK
D44
LVDSB_CLK#
B44
LVDSB_CLK
G45
LVDSA_DATA#_0
F46
LVDSA_DATA#_1
G41
LVDSA_DATA#_2
C45
LVDSA_DATA#_3
F44
LVDSA_DATA_0
G47
LVDSA_DATA_1
F40
LVDSA_DATA_2
A45
LVDSA_DATA_3
B40
LVDSB_DATA#_0
A41
LVDSB_DATA#_1
F42
LVDSB_DATA#_2
D48
LVDSB_DATA#_3
D40
LVDSB_DATA_0
C41
10/18
LVDSB_DATA_1
G43
LVDSB_DATA_2
B48
LVDSB_DATA_3
J27
TVA_DAC
E27
TVB_DAC
G27
TVC_DAC
F26
TVA_RTN
B34
TV_DCONSEL_0
D34
TV_DCONSEL_1
J29
CRT_BLUE
G29
CRT_GREEN
F30
CRT_RED
E29
CRT_IRTN
D36
CRT_DDC_CLK
C35
CRT_DDC_DATA
J33
CRT_HSYNC
D32
CRT_TVO_IREF
G31
CRT_VSYNC
R62
CANTIGA GMCH SFF_FCBGA1363
1 2
LVDS
TV
PEG_COMPI
PEG_COMPO
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PCI-EXPRESS GRAPHICS
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
VGA
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
layout note:
PEGCOMP trace width
and spacing is 20/25 mils.
PEGCOMP
U45
T44
D52
G49
DPB_AUX#
K54
H50
M52
N49
P54
V46
Y50
V52
W49
AB54
AD46
AC55
AE49
AF54
E51
F48
DPB_AUX
J55
DPB_HPD
J49
M54
M50
P52
U47
AA49
V54
V50
AB52
AC47
AC53
AD50
AF52
DPB_LANE0#
L47
DPB_LANE1#
F52
DPB_LANE2#
P46
DPB_LANE3#
H54
L55
T46
R53
U49
T54
Y46
AB46
W53
Y54
AC49
AF46
AD54
DPB_LANE0
J47
DPB_LANE1
F54
DPB_LANE2
N47
DPB_LANE3
H52
L53
R47
R55
T50
T52
W47
AA47
W55
Y52
AB50
AE47
AD52
R53 49.9_0402_1%
R885 100K_0402_5%
R886 100K_0402_5%
12/22 +VCC_PEG-->+VCCP
1 2
1 2
TR 2N7002DW-7-F 2N SOT-363
1 2
TR 2N7002DW-7-F 2N SOT-363
4
C83 0.1U_0402_16V7K
1 2
C84 0.1U_0402_16V7K
1 2
C85 0.1U_0402_16V7K
1 2
C86 0.1U_0402_16V7K
1 2
C87 0.1U_0402_16V7K
1 2
C88 0.1U_0402_16V7K
1 2
C89 0.1U_0402_16V7K
1 2
C90 0.1U_0402_16V7K
1 2
1 2
4
1 2
Q72B
5
+VCCP
Q71B
5
3
+3VS
C81 0.1U_0402_16V7K
TR 2N7002DW-7-F 2N SOT-363
3
+3VS
C82 0.1U_0402_16V7K
6 1
TR 2N7002DW-7-F 2N SOT-363
6 1
DP_DATA0_N
DP_DATA1_N
DP_DATA2_N
DP_DATA3_N
DP_DATA0_P
DP_DATA1_P
DP_DATA2_P
DP_DATA3_P
DPD_C_AUXR#
Q71A
2
DPD_C_AUXR
Q72A
2
DDC1_EN
DDC1_EN
DP_DATA0_N <16>
DP_DATA1_N <16>
DP_DATA2_N <16>
DP_DATA3_N <16>
DP_DATA0_P <16>
DP_DATA1_P <16>
DP_DATA2_P <16>
DP_DATA3_P <16>
DPD_C_AUXR# <16>
DPD_C_AUXR <16>
DPB_HPD <16>
DDC1_EN <16>
CFG[2:0] FSB Freq select
CFG[4:3] Reserved
CFG5 (DMI sel ect)
CFG6
CFG6
CFG7 (Intel Management
Engine Crypto str ap)
CFG8
CFG9
(PCIE Graphics Lane Reversal)
CFG10 (PCIE Lookback enable)
CFG11
CFG[13:12] (XOR/ALLZ)
CFG16 (FSB Dynamic ODT)
CFG19 (DMI Lane R eversal)
CFG20 (PCIE/SDVO concurren t)
000 = FSB 1066MHz
010 = FSB 800MHz
011 = FSB 667MHz
Others = Reserved
0 = DMI x 2
1 = DMI x 4
0 = The iTPM Host Interface is enable
1 = The iTPM Host Interface is disable
0 =(TLS)chiper suite with no confidentiality
*
*
1 =(TLS)chiper suite with confident iality
Reserved
0 = Reverse Lane,15->0, 14->1
1 = Normal Operation,Lane Number in or der
0 = Enable
1 = Disable
Reserved
00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
ReservedCFG[15:14]
*
(Default)11 = Normal Operation
*
0 = Disabled
1 = Enabled
*
ReservedCFG[18:17]
0 = Normal Operation
(Lane number in Order)
*
1 = Reverse Lane
0 = Only PCIE or SDVO is operat ional.
1 = PCIE/SDVO are operat ing simu.
*
*
*
12/29 HP review
Remove some reserved R for CFG net
+3VS
R67 4.02K_0402_1% @
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
2
CFG20<8>
Title
Size Docu ment Number Re v
Custom
Date: Sheet
Compal Electronics, Inc.
Cantiga(3/6)-VGA/LVDS/TV
LA-5221P
1 2
1
10 45Tuesday, February 03, 2009
0.1
of
Page 11
5
12/22 HP review
Pin J31 L31 cont act to GND
12/24 HP review
Pin J31 L31 cont act to GND
D D
12/17 HP review
+1.05VM-->+VCCP
C C
B B
+1.05VM_HPLL
1
C125
2
0.1U_0402_16V4Z
12/22 HP review
DPLLA contact with DPLLB PWR
12/22 HP review
Remove 0 ohm
+1.5VS
0.1U_0402_16V4Z
+VCCP
1
+
2
C108
+1.05VM_PEGPLL
9/27
1
C101
2
100U_D2_6.3VM
12/17 HP review
Remove 0 ohm
1
C126
2
0.1U_0402_16V4Z
+1.05VM_DPLLA
+1.8V
1 2
BLM18PG181SN1D_0603
1
C98
1000P_0402_50V7K
2
9/27
+1.05VM_PEGPLL
4.7U_0805_10V4Z
10U_0805_6.3V6M
1
2
C109
10U_0805_6.3V6M
+1.8V
12/17 HP review
Remov e 0 ohm
+1.05VM_HPLL
+1. 05VM_MP LL
L1
720mA
1U_0603_10V4Z
1
2
C110
0.1U_0402_16V4Z
1
C119
2
+1.8V_TXLVDS
1
2
C111
1
C120
2
1U_0603_10V4Z
1
C127
2
4
U4H
VTT_1
VCCA_TV_DAC
TVD TV/CRT
HDA
VCCD_QDAC
VCCD_TVDAC
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
AXF
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
SM CK
VCC_TX_LVDS
HV
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
PEG
DMI
VTTLF
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT
VCC_HDA
VCC_HV_1
VCC_HV_2
VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VTTLF1
VTTLF2
VTTLF3
J31
VCCA_CRT_DAC
L31
VCCA_DAC_BG
M33
VSSA_DAC_BG
J45
VCCA_DPLLA
L49
VCCA_DPLLB
AF10
VCCA_HPLL
AE1
VCCA_MPLL
U43
VCCA_LVDS1
U41
VCCA_LVDS2
V44
VSSA_LVDS
AJ43
VCCA_PEG_BG
AG43
VCCA_PEG_PLL
AW24
VCCA_SM_1
AU24
VCCA_SM_2
AW22
VCCA_SM_3
AU22
VCCA_SM_4
AU21
VCCA_SM_5
AW20
VCCA_SM_6
AU19
VCCA_SM_7
AW18
VCCA_SM_8
AU18
VCCA_SM_9
AW16
VCCA_SM_10
AU16
VCCA_SM_11
AT16
VCCA_SM_12
AR16
VCCA_SM_13
AU15
VCCA_SM_14
AT15
VCCA_SM_15
AR15
VCCA_SM_16
AW14
VCCA_SM_17
AT24
VCCA_SM_NCTF_1
AR24
VCCA_SM_NCTF_2
AT22
VCCA_SM_NCTF_3
AR22
VCCA_SM_NCTF_4
AT21
VCCA_SM_NCTF_5
AR21
VCCA_SM_NCTF_6
AT19
VCCA_SM_NCTF_7
AR19
VCCA_SM_NCTF_8
AT18
VCCA_SM_NCTF_9
AR18
VCCA_SM_NCTF_10
AU27
VCCA_SM_CK_4
AU28
VCCA_SM_CK_3
AU29
VCCA_SM_CK_2
AU31
VCCA_SM_CK_1
AT31
VCCA_SM_CK_NCTF_1
AR31
VCCA_SM_CK_NCTF_2
AT29
VCCA_SM_CK_NCTF_3
AR29
VCCA_SM_CK_NCTF_4
AT28
VCCA_SM_CK_NCTF_5
AR28
VCCA_SM_CK_NCTF_6
AT27
VCCA_SM_CK_NCTF_7
AR27
VCCA_SM_CK_NCTF_8
AH12
VCCD_HPLL
AE43
VCCD_PEG_PLL
M46
VCCD_LVDS_1
L45
VCCD_LVDS_2
CANTI GA GMCH SFF_FCBGA1363
CRTPLLA PEGA SM
A LVDS
POWER
LVDS
R13
T12
R11
T10
R9
T8
R7
T6
R5
T4
R3
T2
R1
K30
A31
N34
N32
M25
N24
M23
BK24
BL23
BJ23
BK22
T41
C33
A33
AB44
Y44
AC43
AA43
AM44
AN43
AL43
K14
Y12
P2
0.47U_0603_10V7K
C128
3
+1.5VS_QDAC
+VCCP
+VCCP
0.47U_0603_10V7K
1
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2.2U_0805_16V4Z
0.47U_0603_10V7K
1
2
C94
10U_0805_10V4Z
1
C102
2
1
1
1
C96
2
2
2
C97
C95
1U_0603_10V4Z
12/22 HP review
+3VS-->GND
01/10 HP review
Del R69 0ohm andcontact GND directly
12/22 HP review
+1.5VS-->GND
1
C103
2
Near AXF PIN
02/02
Del 10u andR73 0ohm-->1ohm
01/10 HP review
3VS_HV-->+3VS
+3VS
0.1U_0402_16V4Z
1
2
C121
12/22 HP review
+1.05VM-->+VCCP
0.47U_0603_10V7K
1
1
C129
C130
2
2
2
+1.05VM_DPLLA
9/27
+VCCP
852mA
1
+
C93
220U_B2_2.5VM_R25M
@
2
01/10 C93 (330u D2 ESR9-->220u B2 ESR25M@)
+VCCP
+1.5V
0.1U_0402_16V4Z
10U_0805_6.3V6M
1
1
R73
1_0603_5%
C114
C115
1 2
2
2
10U_0805_6.3V6M
+1.5V_SM_CKG
1
C118
2
2 1
+VCCP
D3 C H751H-40_SC76
+3VS
1
C92
2
0.1U_0402_16V4Z
+1.05VM_HPLL
1
2
C99
0.1U_0402_16V4Z
+1. 05VM_MP LL
1
C104
2
0.1U_0402_16V4Z
1
2
C112
1000P_0402_50V7K
+1.05VM_PEGPLL
0.1U_0402_16V4Z
10U_0805_10V4Z
1
C122
2
+VCCP_D
+1.5VS_QDAC
0.1U_0402_16V4Z
0.01U_0402_16V7K
1
C131
2
4.7U_0805_10V4Z
10U_0805_6.3V6M
12/22 HP review
Remove 0 ohm
Near T41 Pin
R74 10_0402_5%
12/12
R68
1 2
BLM18PG181SN1D_0603
@
1
+
C91
220U_B2_2.5VM_R25M
2
01/10 C91(D2 ESR15M@-->B2 ESR25M@)
12/22 HP review
+1.05VM-->+VCCP
Remove 0ohm
R70
1 2
BLM18PG181SN1D_0603
1
2
C100
BLM18PG181SN1D_0603
1
C105
2
BLM18PG121SN1D_0603
1
C123
2
1 2
1
C132
2
R71
1 2
L2
1 2
4.7U_0603_6.3V
1
C133
2
12/22 HP review
+1.05VM-->+VCCP
12/22 HP review
+1.05VM-->+VCCP
1 2
BLM18PG181SN1D_0603
+VCCP
12/22 HP review
+1.05VM-->+VCCP
12/22 HP review
+VCCP
+1.05VM-->+VCCP
+VCCP
+1.8V
4.7U_0805_10V4Z
+VCCP
01/10 HP review
Del R75 0ohm and +3VS_HV-->+3VS
+1.5VS
R76
1
12/22 HP review
+1.05VM-->+VCCP
Remove 0ohm
12/22 HP review
Remove 0 ohm
12/22 HP review
+1.5VS-->GND
12/22 HP review
+1.05VM-->+VCCP
Remove 0ohm
10U_0805_6.3V6M
1
1
1
+
C113
220U_B2_2.5VM_R25M
C117
C116
2
2
2
01/10 C113(D2 ESR15M@-->B2 ESR25M)
12/22 HP review
+1.05VM-->+VCCP
Remove 0ohm
+VCCP
0.1U_0402_16V4Z
1
C124
2
01/02 Near U4 Pin AM44
+VCCP
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELEC TRONIC S, INC . NEITH ER THIS S HEET NO R THE IN FORMATI ON IT CO NTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIO R WRI TTEN C ONSEN T OF C OMPAL ELECT RONIC S, IN C.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Document Number Re v
Custom
2
Dat e: Sheet
Compal Electronics, Inc.
Cantiga(4/6)-PWR
LA-52 21P
1
0.1
of
11 45Tuesd ay, February 03, 2009
Page 12
5
Extnal Graphic: 1210.34mA
integrated Graphic: 1930.4mA
12/12 HP review
+1.05VM-->+VCCP
D D
0.22U_0402_10V4Z
0.22U_0402_10V4Z
1
+
C141
220U_B2_2.5VM_R25M
2
10U_0805_6.3V6M
C142
C143
1
2
1853mA
(VCC and VCC_NCTF)
1
1
2
2
+VCCP
0.1U_0402_16V4Z
C145
C144
1
2
01/10 C141(D2 ESR15M-->B2 ESR25M)
C C
B B
A A
5
U4F
AT41
VCC_1
AR41
VCC_2
AN41
VCC_3
AJ41
VCC_4
AH41
VCC_5
AD41
VCC_6
AC41
VCC_7
Y41
VCC_8
W41
VCC_9
AT40
VCC_10
AM40
VCC_11
AL40
VCC_12
AJ40
VCC_13
AH40
VCC_14
AG40
VCC_15
AE40
VCC_16
AD40
VCC_17
AC40
VCC_18
AA40
VCC_19
Y40
VCC_20
AN35
VCC_21
AM35
VCC_22
AJ35
VCC_23
AH35
VCC_24
AD35
VCC_25
AC35
VCC_26
W35
VCC_27
AM34
VCC_28
AL34
VCC_29
AJ34
VCC_30
AH34
VCC_31
AG34
VCC_32
AE34
VCC_33
AD34
VCC_34
AC34
VCC_35
AA34
VCC_36
Y34
VCC_37
W34
VCC_38
AM32
VCC_39
AL32
VCC_40
AJ32
VCC_41
AH32
VCC_42
AE32
VCC_43
AD32
VCC_44
AA32
VCC_45
AM31
VCC_46
AL31
VCC_47
AJ31
VCC_48
AH31
VCC_49
AM29
VCC_50
AL29
VCC_51
AM28
VCC_52
AL28
VCC_53
AJ28
VCC_54
AM27
VCC_55
AL27
VCC_56
AM25
VCC_57
AL25
VCC_58
AJ25
VCC_59
AM24
VCC_60
N36
VCC_61
CANTIGA GMCH SFF_FCBGA1363
VCC CORE
4
POWER
VCC NCTF
4
VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
3
01/10 C137(330u D2 ESR9M-->220u B2 ESR25M)
+1.5V
02/02 Change to DDR3 power
C137
220U_B2_2.5VM_R25M
+VCC_CM_BB36
+VCC_CM_BE35
0.1U_0402_10V7K~D
12/12 HP review
+1.05VM-->+VCCP
+VCCP
AT38
AR38
AN38
AM38
AL38
AG38
AE38
AA38
Y38
W38
U38
T38
R38
AT37
AR37
AN37
AM37
AL37
AJ37
AH37
AG37
AE37
AD37
AC37
AA37
Y37
W37
U37
T37
R37
AT35
AR35
U35
AT34
AR34
U34
T34
R34
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
330U_D2E_2.5VM_R9
C1103
1
2
C1105
1
2
C1104
1
2
+VCC_CM_BF24
+VCC_CM_BL19
0.1U_0402_10V7K~D
C1106
1
2
CRB use
+VCCGFX
5739mA
(VCC_AXG and VCC_AXG_NCTF)
1
1
+
C146
2
C148
C147
2
10U_0805_6.3V
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
3
U4G
+VCC_CM_BB36
10U_0805_6.3V6M
C138
1
1
2
2
+VCC_CM_BC29
+VCC_CM_BB16
+VCC_CM_BC29
C1110
1
2
1
C150
2
1U_0603_10V4Z
0.1U_0402_16V4Z
+VCC_CM_BE35
0.01U_0402_16V7K
C139
+VCC_CM_BF24
+VCC_CM_BL19
+VCC_CM_BB16
01/10 HP review
Del T5 and T6
Compal Secret Data
3000mA
10U_0805_6.3V6M
1
+
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
C1102
1
2
1
1
C149
2
2
10U_0805_6.3V
2006/02/13 2006/03/10
C140
2
1
BB36
VCC_SM_1
BE35
VCC_SM_2
AW34
VCC_SM_3
AW32
VCC_SM_4
BK30
VCC_SM_5
BH30
VCC_SM_6
BF30
VCC_SM_7
BD30
VCC_SM_8
BB30
VCC_SM_9
AW30
VCC_SM_10
BL29
VCC_SM_11
BJ29
VCC_SM_12
BG29
VCC_SM_13
BE29
VCC_SM_14
BC29
VCC_SM_15
BA29
VCC_SM_16
AY29
VCC_SM_17
BK28
VCC_SM_18
BH28
VCC_SM_19
BF28
VCC_SM_20
BD28
VCC_SM_21
BB28
VCC_SM_22
BL27
VCC_SM_23
BJ27
VCC_SM_24
BG27
VCC_SM_25
BE27
VCC_SM_26
BC27
VCC_SM_27
BA27
VCC_SM_28
AY27
VCC_SM_29
AW26
VCC_SM_30
BF24
VCC_SM_31
BL19
VCC_SM_32
BB16
VCC_SM_33
W32
VCC_AXG_1
AG31
VCC_AXG_2
AE31
VCC_AXG_3
AD31
VCC_AXG_4
AC31
VCC_AXG_5
AA31
VCC_AXG_6
Y31
VCC_AXG_7
W31
VCC_AXG_8
AH29
VCC_AXG_9
AG29
VCC_AXG_10
AE29
VCC_AXG_11
AD29
VCC_AXG_12
AC29
VCC_AXG_13
AA29
VCC_AXG_14
Y29
VCC_AXG_15
W29
VCC_AXG_16
AH28
VCC_AXG_17
AG28
VCC_AXG_18
AE28
VCC_AXG_19
AA28
VCC_AXG_20
AH27
VCC_AXG_21
AG27
VCC_AXG_22
AE27
VCC_AXG_23
AD27
VCC_AXG_24
AC27
VCC_AXG_25
AA27
VCC_AXG_26
Y27
VCC_AXG_27
W27
VCC_AXG_28
AH25
VCC_AXG_29
AD25
VCC_AXG_30
AC25
VCC_AXG_31
W25
VCC_AXG_32
AJ24
VCC_AXG_33
AH24
VCC_AXG_34
AG24
VCC_AXG_35
AE24
VCC_AXG_36
AD24
VCC_AXG_37
AC24
VCC_AXG_38
AA24
VCC_AXG_39
Y24
VCC_AXG_40
W24
VCC_AXG_41
AM22
VCC_AXG_42
AL22
VCC_AXG_43
AJ22
VCC_AXG_44
AH22
VCC_AXG_45
AG22
VCC_AXG_46
AE22
VCC_AXG_47
AD22
VCC_AXG_48
AC22
VCC_AXG_49
AA22
VCC_AXG_50
AM21
VCC_AXG_51
AL21
VCC_AXG_52
AJ21
VCC_AXG_53
AH21
VCC_AXG_54
AD21
VCC_AXG_55
AC21
VCC_AXG_56
AA21
VCC_AXG_57
Y21
VCC_AXG_58
W21
VCC_AXG_59
AM16
VCC_AXG_60
AL16
VCC_AXG_61
AG13
VCC_AXG_SENSE
AE13
VSS_AXG_SENSE
CANTIGA GMCH SFF_FCBGA1363
Deciphered Date
2
+VCCGFX
T32
U31
T31
R31
U29
T29
R29
U28
U27
T27
R27
U25
T25
R25
U24
U22
T22
R22
U21
T21
R21
AM19
AL19
AH19
AG19
AE19
AD19
AC19
W19
U19
AM18
AL18
AJ18
AH18
AG18
AE18
AD18
AC18
AA18
Y18
W18
U18
T18
R18
AJ16
AH16
AD16
AC16
AA16
U16
T16
R16
AM15
AL15
AJ15
AH15
AG15
AE15
AA15
Y15
W15
U15
T15
AU45
BF52
BB38
BA19
BE9
AU9
AL9
VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
VCC SMVCC GFX
POWER
VCC GFX NCTF
VCC GFX
VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_62
VCC_AXG_63
VCC_AXG_64
VCC_AXG_65
VCC_AXG_66
VCC_AXG_67
VCC_AXG_68
VCC_AXG_69
VCC_AXG_70
VCC_AXG_71
VCC_AXG_72
VCC_AXG_73
VCC_AXG_74
VCC_AXG_75
VCC_AXG_76
VCC_AXG_77
VCC_AXG_78
VCC_AXG_79
VCC_AXG_80
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
VCC SM LF
Title
Size Docu ment Number Re v
Custom
2
Date: Sheet
Compal Electronics, Inc.
Cantiga(5/6)-PWR/GND
LA-5221P
1
1
1
1
2
2
2
C136
C135
C134
0.1U_0402_16V4Z
C156 0.1U_0402_16V4Z
1
2
4.7U_0805_10V4Z
0.22U_0402_10V4Z
C151 0.22U_0603_10V7K
C152 0.22U_0603_10V7K
1
1
1
C157 0.1U_0402_16V4Z
1
2
2
2
2
12 45Tuesday, February 03, 2009
1
C153 0.47U_0402_6.3V6K
C155 1U_0603_10V4Z
C154 1U_0603_10V4Z
1
1
2
2
0.1
of
Page 13
5
U4I
BA55
VSS_1
AU55
VSS_2
AN55
VSS_3
AJ55
VSS_4
AE55
VSS_5
AA55
VSS_6
U55
VSS_7
N55
VSS_8
BD54
VSS_9
BG53
VSS_10
AJ53
VSS_11
AE53
D D
C C
B B
A A
VSS_12
AA53
VSS_13
U53
VSS_14
N53
VSS_15
J53
VSS_16
G53
VSS_17
E53
VSS_18
K52
VSS_19
BG51
VSS_20
BA51
VSS_21
AW51
VSS_22
AU51
VSS_23
AR51
VSS_24
AN51
VSS_25
AL51
VSS_26
AJ51
VSS_27
AG51
VSS_28
AE51
VSS_29
AC51
VSS_30
AA51
VSS_31
W51
VSS_32
U51
VSS_33
R51
VSS_34
N51
VSS_35
L51
VSS_36
J51
VSS_37
G51
VSS_38
C51
VSS_39
BK50
VSS_40
AM50
VSS_41
K50
VSS_42
BG49
VSS_43
E49
VSS_44
C49
VSS_45
BD48
VSS_46
BB48
VSS_47
AY48
VSS_48
AV48
VSS_49
AT48
VSS_50
AP48
VSS_51
AM48
VSS_52
AK48
VSS_53
AH48
VSS_54
AF48
VSS_55
AD48
VSS_56
AB48
VSS_57
Y48
VSS_58
V48
VSS_59
T48
VSS_60
P48
VSS_61
M48
VSS_62
K48
VSS_63
H48
VSS_64
BL47
VSS_65
BG47
VSS_66
E47
VSS_67
C47
VSS_68
A47
VSS_69
BD46
VSS_70
AY46
VSS_71
AM46
VSS_72
AK46
VSS_73
AH46
VSS_74
BG45
VSS_75
AE45
VSS_76
AC45
VSS_77
AA45
VSS_78
W45
VSS_79
R45
VSS_80
N45
VSS_81
E45
VSS_82
BD44
VSS_83
BB44
VSS_84
AV44
VSS_85
AK44
VSS_86
AH44
VSS_87
AF44
VSS_88
AD44
VSS_89
K44
VSS_90
H44
VSS_91
BL43
VSS_92
BG43
VSS_93
AY43
VSS_94
AR43
VSS_95
W43
VSS_96
R43
VSS_97
M43
VSS_98
E43
VSS_99
CANTIGA GMCH SFF_FCBGA1363
VSS
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
C43
A43
BD42
H42
BG41
AY41
AU41
AM41
AL41
AG41
AE41
AA41
R41
M41
E41
BD40
AU40
AR40
AN40
W40
U40
T40
R40
K40
H40
BL39
BG39
BA39
E39
C39
A39
BD38
AU38
H38
BG37
AU37
M37
E37
BD36
AW36
H36
BL35
BG35
AY35
AU35
AL35
AG35
AE35
AA35
Y35
M35
E35
A35
BD34
AU34
AN34
H34
BL33
BG33
AY33
E33
BD32
AU32
AN32
AG32
AC32
Y32
H32
B32
BJ31
BG31
AY31
AN31
M31
E31
N30
H30
AN29
AJ29
M29
A29
AW28
AN28
AD28
AC28
Y28
W28
H28
F28
AN27
AJ27
M27
BF26
BD26
N26
H26
BJ25
AY25
AU25
4
3
U4J
AN25
VSS_199
AG25
VSS_200
AE25
VSS_201
AA25
VSS_202
Y25
VSS_203
E25
VSS_204
A25
VSS_205
BD24
VSS_206
AN24
VSS_207
AL24
VSS_208
H24
VSS_209
BG23
VSS_210
AY23
VSS_211
E23
VSS_212
BD22
VSS_213
BB22
VSS_214
AN22
VSS_215
Y22
VSS_216
W22
VSS_217
H22
VSS_218
BL21
VSS_219
BG21
VSS_220
AY21
VSS_221
AN21
VSS_222
AG21
VSS_223
AE21
VSS_224
M21
VSS_225
E21
VSS_226
A21
VSS_227
BD20
VSS_228
H20
VSS_229
BG19
AY19
M19
BD18
BL17
BG17
AY17
M17
BD16
AN16
AG16
AE16
W16
BG15
AY15
AN15
AD15
AC15
M15
BD14
BL13
BG13
AY13
AU13
AR13
AJ13
AC13
AA13
W13
M13
BD12
AV12
AP12
AM12
AK12
AB12
BG11
AG11
BD10
AY10
AP10
BG9
BD8
E19
N18
H18
E17
A17
Y16
N16
H16
R15
E15
H14
U13
E13
A13
V12
P12
H12
E11
H10
BL9
E9
A9
BB8
AY8
AV8
AT8
AP8
VSS
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
CANTIGA GMCH SFF_FCBGA1363
VSS NCTF
VSS SCB
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
VSS_361
VSS_362
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5
VSS_SCB_6
VSS_SCB_7
2
AM8
AK8
AH8
AF8
AD8
AB8
Y8
V8
P8
M8
K8
H8
BJ7
E7
BF6
BC5
BA5
AW5
AU5
AR5
AN5
AL5
AJ5
AG5
AE5
AC5
AA5
W5
U5
N5
L5
J5
G5
C5
BH4
BE3
U3
E3
BC1
AW1
AR1
AL1
AG1
AC1
W1
N1
J1
AU43
BB42
AW38
BA35
L29
N28
N22
N20
N14
AL13
B10
AN13
N42
N40
N38
M39
AJ38
AH38
AD38
AC38
T35
R35
AT32
AR32
U32
R32
T28
R28
AT25
AR25
T24
R24
AN19
AJ19
AA19
Y19
T19
R19
AN18
BL55
BL1
A55
D1
B55
B2
A4
12/12 FOR NO CRACK DETECT FUNCTION
1
Security Classification
12/12 FOR NO CRACK DETECT FUNCTION
5
4
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Docu ment Number Re v
Custom
2
Date: Sheet
Compal Electronics, Inc.
Cantiga(6/6)-PWR/GND
LA-5221P
1
13 45Tuesday, February 03, 2009
0.1
of
Page 14
5
DDR_A_DQS#[0..7]<9>
DDR_A_D[0..63]<9>
DDR_A_DM[0..7]<9>
DDR_A_DQS[0..7]<9>
DDR_A_MA[0..14]<9>
D D
Layout Note:
Place near JP3
+1.5V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C166
1
2
C C
B B
Layout Note:
Place near JP3 203,204
+0.75VS
A A
+1.5V
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
C1113
1
2
1U_0603_10V4Z~D
1U_0603_10V4Z~D
1
1
C1120
C1121
2
2
0.1U_0402_16V4Z
C167
1
2
10U_0603_6.3V6M~D
C1114
1
2
1U_0603_10V4Z~D
1
C1122
2
0.1U_0402_16V4Z
C168
C169
1
1
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
C1115
C1116
1U_0603_10V4Z~D
C1117
1
1
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
C1153
C1123
2
1
2
1
2
4
V_DDR_MCH_REF<8>
DDR_CKE0_DIMMA<8>
330U_D2_2.5VY_R15M
1
C1119
C1118
1
+
2
2
10U_0603_6.3V6M~D
1
1
C1154
C1155
2
2
+3VS
2.2U_0603_6.3V6K~D
1
2
3
+1.5V +1.5V
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
DDR_A_D0
1
C158
2
DDR_A_BS2<9>
M_CLK_DDR0<8>
M_CLK_DDR#0<8>
DDR_A_BS0<9>
DDR_A_WE#<9>
DDR_A_CAS#<9>
DDR_CS1_DIMMA#<8>
0.1U_0402_16V4Z~D
C183
+0.75VS
C184
1
2
DDR_A_D1
1
DDR_A_DM0
C159
DDR_A_D2
2
DDR_A_D3
DDR_A_D8
DDR_A_D13
DDR_A_DQS#1
DDR_A_DQS1 SM_DRAMRS T#
DDR_A_D10
DDR_A_D11
DDR_A_D20
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D25
DDR_A_D30
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA DDR_CKE1_DIMMA
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA3
DDR_A_MA1
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_CS1_DIMMA#
DDR_A_D32
DDR_A_D39
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D54
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
1 2
R128 10K_0402_5%~D
1 2
R129 10K_0402_5%~D
3
5
7
9
11
13
15
17
19
21
23
25
27
33
35
39
41
45
47
49
51
53
55
57
59
63
67
69
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
2
JP3
VREF_DQ1VSS1
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS129RESET#
VSS1131VSS12
DQ10
DQ11
VSS1337VSS14
DQ16
DQ17
VSS1543VSS16
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS2261DQS#3
DM3
VSS2365VSS24
DQ26
DQ27
VSS2571VSS26
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
G1
DQS#0
VSS10
VSS17
VSS19
VSS21
VDD10
VDD12
VDD14
VDD16
VDD18
VREF_CA
VSS28
VSS30
VSS31
VSS33
VSS35
DQS#5
VSS38
VSS40
VSS42
VSS43
VSS45
VSS47
DQS#7
VSS50
VSS52
EVENT#
FOX_AS0A626-U4RN-7F
VSS3
DQS0
VSS6
VSS8
DQ12
DQ13
DM1
DQ14
DQ15
DQ20
DQ21
DM2
DQ22
DQ23
DQ28
DQ29
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
CK1#
RAS#
ODT0
ODT1
NC2
DQ36
DQ37
DM4
DQ38
DQ39
DQ44
DQ45
DQS5
DQ46
DQ47
DQ52
DQ53
DM6
DQ54
DQ55
DQ60
DQ61
DQS7
DQ62
DQ63
SDA
VTT2
DQ4
DQ5
DQ6
DQ7
A15
A14
A11
CK1
BA1
S0#
SCL
1
2
DDR_A_D4
4
DDR_A_D5
6
8
DDR_A_DQS#0
10
DDR_A_DQS0
12
14
DDR_A_D6
16
DDR_A_D7
18
20
DDR_A_D14
22
DDR_A_D15
24
26
DDR_A_DM1
28
30
32
DDR_A_D9
34
DDR_A_D12
36
38
DDR_A_D22
40
DDR_A_D21
42
44
DDR_A_DM2
46
48
DDR_A_D16
50
DDR_A_D23
52
54
DDR_A_D28
56
DDR_A_D29
58
60
DDR_A_DQS#3
62
DDR_A_DQS3
64
66
DDR_A_D24
68
DDR_A_D31
70
72
74
76
78
DDR_A_MA14
80
82
DDR_A_MA11
84
DDR_A_MA7
86
A7
88
DDR_A_MA6
90
A6
A4
A2
A0
G2
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
DDR_A_MA4DDR_A_MA5
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
M_ODT1
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D33
DDR_A_D38
DDR_A_D47
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D44
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D48
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
PM_EXTTS#0
MEM_SDATA
MEM_SCLK
+0.75VS
SM_DRAMR ST# <8>
T161PAD~ D
M_CLK_DDR1 <8>
M_CLK_DDR#1 <8>
DDR_A_BS1 <9>
DDR_A_RAS# <9>
DDR_CS0_DIMMA# <8>
M_ODT0 <8 >
M_ODT1 <8 >
PM_EXTTS#0 < 8>
ICH_SMBDATA <4,15,21,25>
ICH_SMBCLK <4 ,15,21,25>
DDR_CKE1_DIMMA <8>
V_DDR_MCH_REF <8>
0.1U_0402_16V4Z~D
2.2U_0603_6.3V6K~D
C1089
C1088
1
1
2
2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Docu ment Number Re v
2
Date: Sheet
Compal Electronics, Inc.
DDRII-SODIMM SLOT
LA-5221P
14 45Tuesday, February 03, 2009
1
0.1
of
Page 15
5
FSB
MHz
1066
800
667
1 2
SRC
MHz
1000
100
1 2
R85
1 2
1K_0201_5%
R92
1 2
1K_0201_5%
R95
0_0201_5%
MHz
33.30
33.3
R82
1K_0201_5%
CLKSEL1
FSLA
CLKSEL0
MHz
FSLC1FSLB
CLKSEL2
CPU
0 1000 2660 33.3
1
0
1
D D
12/20 HP review
Remove reserved pull +VCCP R
FSA
R81 2.2K_0402_5%
CPU_BSEL0<5>
12/20 HP review
Remove reserved pull low R
C C
B B
12/20 HP review
Remove reserved pull +VCCP R
CPU_BSEL1<5>
12/20 HP review
Remove reserved pull low R
FSC
CPU_BSEL2<5>
200
166
12
1 2
R84 0_0201_5%
FSB
1 2
R86 0_0201_5%
R91 10K_0201_5%
12
1 2
R93 0_0201_5%
PCI
12/17 HP review
+3VM-->+3VS
MCH_CLKSEL1 <8>
MCH_CLKSEL2 <8>
12/31 Us e 0201 size
CLK_XTAL_OUT
CLK_XTAL_IN
Y3
A A
12
14.318MHZ_16PF_7A14300083
2
2
C205
C20433P_0402_50V8J
33P_0402_50V8J
1
1
+3VS
1 2
1 2
R98
10K_0201_5%
R101
10K_0201_5%
@
12/31 Y3 sue 5032 size and confirm C204 C205 c value
5
4
+3VS
12/26 R78(1206-->0805)
MCH_CLKSEL0 <8>
C963
01/05 Reserved for WWAN
CLK_PCI_EC<32>
CLK_PCI_DEBUG<25>
CLK_PCI_DB<31>
CLK_PCI_ICH<19>
48MHZ_Clock<28>
CLK_48M_ICH<21>
CLK_14M_ICH<21>
CLK_14M_KBC<32>
+3VS
R99
10K_0201_5%
@
1 2
27_SELITP_EN
R102
10K_0201_5%
1 2
12/31 Us e 0201 size
4
1 2
R78 0_0805_5%
400mA
12/20 HP review
Use +VCCP power
CLK_PCI_DEBUG
12
47P_0402_50V8C@
+3VS_CK505
12/20 +3VM_CK505-->+3VS_CK505
1
2
C189
10U_0805_10V4Z
12/17 HP review
Remove damping R
CLKREQ#_B
12/20
+3VM_CK505-->+3VS_CK505
12/20 HP review
Use +VCCP power
1
1
2
2
C191
C190
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+VCCP
0.1U_0402_16V4Z
1
2
C192
01/08 33 ohm-->22ohm
CLK_PCI_EC PCI_CLK3
CLK_PCI_DB
CLK_PCI_ICH
1 2
1 2
1 2
1 2
R8733_0201_1%
R8822_0402_1%
R85022_0402_1%
R9033_0201_1%
12/26 R eserved for card reader clk
48MHZ_Clock
CLK_48M_ICH
CLK_14M_ICH
CLK_14M_KBC
1 2
@
1 2
1 2
1 2
01/08 33 ohm-->22ohm
+3VS
R100
10K_0201_5%
1 2
PCI2_TME
R103
10K_0201_5%
@
1 2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
3
1
2
C193
0.1U_0402_16V4Z
+3VS_CK505
+VCCP
PCI2_TME
27_SEL
ITP_EN
CLK_XTAL_IN
CLK_XTAL_OUT
R85622_0402_1%
R9433_0402_1%
R9622_0402_1%
R9722_0402_1%
3
+VCCP
12/17 HP review
+1.05VM-->+VCCP
1
1
2
2
C194
C195
0.1U_0402_16V4Z
6
12
19
23
27
55
72
31
38
52
62
66
13
14
15
16
17
5
4
20
2
7
59
18
22
26
30
69
34
42
3
R79 10K_0201_5%
1 2
U5
VDDREF
VDDPCI
VDD48
VDD96_IO
VDDPLL3
VDDSRC
VDDCPU
VDDPLL3_IO
VDDSRC_IO
VDDSRC_IO
VDDSRC_IO
VDDCPU_IO
PCI
PCI2/TME
PCI3
PCI4/27_Select
PCI_F5/ITP_EN
X1
X2
USB_48MHz/FSLA
FSLB/TEST_MODE
FSLC/TEST_SEL/REF0
GNDSRC
GNDPCI
GND48
GND
GND
GNDCPU
GNDSRC
GNDSRC
GNDREF
SLG8SP 553VTR QFN 72P
0.1U_0402_16V4Z
FSA
FSB
FSC
2006/02/13 2006/03/10
100mil
12/20 HP review
Remove damping R
CLKREQ#_B <8>
PCI_STOP#
CPU_STOP#
CPUT0_LPR_F
CPUC0_LPR_F
CPUT1_LPR_F
CPUC1_LPR_F
CPUT2_ITP_LPR/SRCT8_LPR
CPUC2_ITP_LPR/SRCC8_LPR
SRCC0_LPR/DOTC_96_LPR
27MHz_NonSS/SRCT1_LPR/SE1
27MHz_SS/SRCC1_LPR/SE2
SRCT7_LPR
SRCC7_LPR
SRCT6_LPR
SRCC6_LPR
SRCT10_LPR
SRCC10_LPR
SRCT11_LPR
SRCC11_LPR
SRCT9_LPR
SRCC9_LPR
SRCT4_LPR
SRCC4_LPR
SRCT3_LPR
SRCC3_LPR
SRCT2_LPR/SATAT_LPR
SRCC2_LPR/SATAC_LPR
SRCT0_LPR/DOTT_96_LPR
CK_PWRGD/PD#
Compal Secret Data
Deciphered Date
+3VS
SCLK
SDATA
CR10#
CR#11
CR#A
CR7#
CR#6
CR#9
CR#4
CR#3
REF1
10U_0805_10V4Z
NC
2
1
1
2
2
C778
C777
0.1U_0402_16V4Z
11
10
9
54
53
71
70
68
67
CLKREQ#_B
65
64
63
61
60
CR#6
58
57
56
CLKREQ_W LAN#
49
50
51
CR#11
46
48
47
CLK_PCIE_LAN_REQ#
43
44
45
41
39
40
37
35
36
32
33
24
25
28
29
1
CLKSATAREQ#
21
8
2
12/20 HP review
Use +VCCP power
1
1
2
2
C779
C199
10U_0805_10V4Z
0.1U_0402_16V4Z
CLKREQ_W LAN#
CLKSATAREQ#
R_CPU_XDP
R_CPU_XDP#
R895 10K_0201_5%
0.1U_0402_16V4Z
12/17 HP review
Remove damping R
ICH_SMBCLK <4 ,14,21,25>
ICH_SMBDATA <4,14,21,25>
H_STP_PCI# <21>
H_STP_CPU# <21>
CLK_CPU_BCLK <4>
CLK_CPU_BCLK# <4>
CLK_MCH_BCLK <8>
CLK_MCH_BCLK# <8>
R859 0_0201_5%
R860 0_0201_5%
CLK_MCH_3GPLL <8>
CLK_MCH_3GPLL# <8>
R894 10K_0201_5%
1 2
CLK_PCIE_MCARD <25>
CLK_PCIE_MCARD# <25>
1 2
CLK_P CIE_LAN <23>
CLK_PCIE_LAN# <23>
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_PCIE_SATA <20>
CLK_PCIE_SATA# <20>
CLK_MCH_DREFCLK <8>
CLK_MC H_DREFCLK# <8>
MCH_SS CDREFCLK <8>
MCH_SS CDREFCLK# <8>
CK_ PWRGD <21>
1
C185
C186
C187
1
1
2
2
C200
C201
0.1U_0402_16V4Z
C188
C202
C203
Place close to U5
1 2
1 2
12/19
G LAN clock
CLK_PCIE_LAN_REQ# <23>
02/02
No support Express card
12/17 HP review
Remove damping R
Title
Size Docu ment Number Re v
Date: Sheet
Compal Electronics, Inc.
CLOCK GENERATOR
LA-5221P
01/11
+3VS
Add R8 94 pull +3VS
+3VS
CLK_CPU_XDP <4>
CLK_CPU_XDP# <4>
CLK_PCIE_ICH <21>
CLK_PCIE_ICH# <21>
CLK_48M_ICH
12
5P_0402_50V8C@
CLK_14M_ICH
1 2
12P_0402_50V8J
CLK_PCI_ICH
12
4.7P_0402_50V8C@
CLK_14M_KBC
1 2
12P_0402_50V8J
CLK_PCI_EC
12
4.7P_0402_50V8C@
CLK_PCI_DB
12
5P_0402_50V8C@
12/20
No use CLK_PCI_TCG net
R80 10K_0201_5%
1 2
CLKREQ_W LAN# <25>
CLKSATAREQ# <21>
R83 10K_0201_5%
1 2
01/11
Add R8 95 pull +3VS
of
15 45Tuesday, February 03, 2009
1
+3VS
+3VS
0.1
Page 16
5
D D
1 2
R1040_0402_5%
DP_DA TA0_P<10>
DP_DATA0_N<10>
DP_DA TA1_P<10>
DP_DATA1_N<10>
C C
DP_DA TA2_P<10>
DP_DATA2_N<10>
DP_DA TA0_P
DP_DA TA0_N
DP_DA TA1_P
DP_DA TA1_N
DP_DA TA2_P
DP_DA TA2_N
01/06 P-->N
DP_DA TA3_P<10>
DP_DATA3_N<10>
B B
DPD_C_AUXR<10>
DPD_C_AUXR#<10>
DP_DA TA3_P
DP_DA TA3_N
DPD_C_AUXR#
L3
1
1
4
4
WCM- 2012-900T_4P
1 2
1 2
L4
1
1
4
4
WCM- 2012-900T_4P
1 2
1 2
L5
1
1
4
4
WCM- 2012-900T_4P
1 2
1 2
L6
1
1
4
4
WCM- 2012-900T_4P
1 2
1 2
L7
1
1
4
4
WCM- 2012-900T_4P
1 2
@
@
@
@
@
2
3
R1050_0402_5%
R1060_0402_5%
2
3
R1070_0402_5%
R1090_0402_5%
2
3
R1120_0402_5%
R1140_0402_5%
2
3
R1180_0402_5%
R1190_0402_5%
2
3
R1210_0402_5%
2
3
2
3
2
3
2
3
2
3
DP_DATA0R_P
DP_DATA0R_N
DP_DATA1R_P
DP_DATA1R_N
DP_DATA2R_P
DP_DATA2R_N
DP_DATA3R_P
DP_DATA3R_N
DPD_C_A UXR_RDPD_C_AUXR
DPD_C_AUXR#_R
R897
100K_0402_5%
+3VS
12
4
12
R898
100K_0402_5%
3
01/12
Del reserved ESD part, because M/B no m ore space
+3VS
21
F2
NANOSMDC050F 0.5A 13.2V PO LY-FUSE
+DPA _3V
12
R108
0_0805_5%
C765
12
R115
5.1M_ 0402_5%
01/06
Del R1 15, support DP only
R116-->@
1
2
0.1U_0402_16V4Z
C766
12
R116
1M_0402_5%
+3VS_DP
10U_0805_10V4Z
1
2
DP_HPD
DPD_C_AUXR#_R
DPD_C_A UXR_R
DP_DCAD
DP_DATA3R_N DP_HPD
DP_DATA3R_P
DP_DATA2R_N
DP_DATA2R_P
DP_DATA1R_N
DP_DATA1R_P
DP_DATA0R_N
DP_DATA0R_P
JDP1
CONN@
20
DP_PWR
19
RTN
18
HP_DET
17
AUX_CH-
16
GND
15
AUX_CH+
14
GND
13
12
11
10
9
8
7
6
5
4
3
2
1
FOX_ 3V10211-RBJH3-8H_20P -T
CA_DET
LANE3LANE3_shield
LANE3+
LANE2LANE2_shield
LANE2+
LANE1LANE1_shield
LANE1+
LANE0LANE0_shield
LANE0+
GND
GND
GND
GND
24
23
22
21
2
DP_DCAD
2
G
R123
100K_0402_1%
1 2
01/12 HP review
Follow intel DG REV2.1(20k-->100K)
+3VS_DP
1 2
13
D
S
2
R120
20K_0 402_1%
DPB_HPD
Q3
2N7002_SOT23-3
R110
10K_0 402_5%
1 2
DP_EN DDC1_ EN
61
2N7002DW-7-F_SOT363-6
Q2A
DP B_HPD <10>
R122
7.5K_ 0402_5%
1 2
+5VS+5VS
1 2
4
5
3
1
R111
10K_0 402_5%
DDC1_EN <10>
2N7002DW-7-F_SOT363-6
Q2B
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRO NICS, INC. NEIT HER THIS SHEE T NOR THE INFO RMATION IT CO NTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF C OMPAL ELECT RONICS, INC.
3
2008/09/15 2009/12/31
Compal Secret Data
Deciphered Date
2
Title
Size Docum ent Number Re v
Date: Sheet of
Compal Electronics, Inc.
Display Port Connector
LA-5221P
1
16 45Tuesday, February 03, 2009
0.1
Page 17
5
4
3
2
1
LED/PANEL BD. CONN.
D D
C208 0.1U_0603_50V
12
C209 68P_0402_50V8J
12
+3VS
R126
10K_0402_5%
ENABLT<10>
LID_SW#<21,29,32>
+3VALW
C C
12/29 HP review
+3VS-->+3VALW
R849
100K_0402_1%
R634
10K_0402_5%
12
12
D53
CH751H-40_SC76
D54
CH751H-40_SC76
1 2
21
21
DISPLAY_OFF
USB20_P10<21>
USB20_N10<21>
B+
+3VS
LCDVDD
+5V_WEBCAM
L8
1 2
LQM21FN4R7N00L_0805
BLON_PWM<10>
+5V_WEBCAM
USB20_P10
USB20_N10
12/20 HP review
Del ALS_EN net
01/08 Follow Dior design
USB20_N10
B+_LCD
JP5
ACES_88242-3001_30P
CONN@
D32
4
3
CM1293A-02SR_SOT143-4
2
IO1
VIN
1
GND
IO2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
3132
USB20_P10
+3VS
R1242.2K_0402_5%
1 2
R1252.2K_0402_5%
1 2
DDC2_CLK <10>
DDC2_DATA <10>
TXOUT_L0- <10>
TXOUT_L0+ <10>
TXOUT_L1- <10>
TXOUT_L1+ <10>
TXOUT_L2- <10>
TXOUT_L2+ <10>
TXCLK_L- <10>
TXCLK_L+ <10>
1
1
C9555P_0402_50V8C
C9545P_0402_50V8C
2
2
@
@
1
1
C9565P_0402_50V8C
2
@
1
1
C9575P_0402_50V8C
2
@
1
C9585P_0402_50V8C
2
@
1
C9595P_0402_50V8C
C9605P_0402_50V8C
C9615P_0402_50V8C
2
2
@
@
@
12/20 HP review
2
Reserved for LVDS EMI
12/29 ESD request
Near JP5
LCD POWER CIRCUIT
R169
Q41
LCDVDD
12
13
D
S
1 2
R166
100_0402_1%
R168 47K_0402_5%
1 2
2
G
1
OUT
2
IN
Q8
DTC124EKAT146_SC59-3
GND
3
0.1U_0402_16V4Z
B B
RHU002N06_SOT323
ENAVDD<10>
100K_0402_1%
A A
5
LCDVDD
C767
+3VS
Connect LCD power source to
Q6
D
S
SI2301 1P_SOT23
1 3
G
2
R167 1M_0402_5%
1 2
C769 0.1U_0402_16V4Z
1
1
C768
4.7U_0805_10V4Z
2
2
4
1 2
+3VS directly. 5/16
1
C770
4.7U_0805_10V4Z@
2
WEBCAM_ON/OFF#<21>
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
3
2005/03/10 2006/03/10
Compal Secret Data
Deciphered Date
2
+3VALW
1 2
+5VALW +5V_WEBCAM
1U_0603_10V4Z
1
C218
2
1 2
R164
R601
10K_0402_5%
Title
Size Docu ment Number Re v
Date: Sheet
100K_0402_5%
1 2
R602 47K_0402_5%
13
D
Q7
2
G
RHU002N06_SOT323
S
Compal Electronics, Inc.
LCD CONN & Q-Switch & GPIO Ext.
LA-5221P
Q5
SI2301BDS_SOT23
S
D
G
2
1
C562
0.1U_0402_16V4Z
2
+5VALW
1
13
1
1
1
C220
C221
C219
2
2
2
0.1U_0402_16V4Z
4.7U_0805_10V4Z
0.01U_0402_16V7K
0.1
of
17 45Tuesday, February 03, 2009
Page 18
5
D D
+3VS
47K
10K
2
13
HDD_HALTLED<21>
C C
HDD_HALTLED
R334
@
100K_0402_5%
12/26
Modify HD LED cont rol(follow skyy)
D
Q80
2
G
2N7002_SOT23
S
12
1 3
To LED small board
01/06
B B
JP6
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
GND
12
GND
ACES_85201-1005N CONN@
A A
+3VL-->+3VS
+3VS
APP_BUTTON_1_LED#
APP_BUTTON_2_LED#
01/06
Confirm LED GPIO ok
12/26
Power LED on small board
WL_BLUE_BTN
WL/BT_LED
APP_BUTTON_1
APP_BUTTON_2
WL_BLUE_BTN <32>
APP_BUTTON_1 <32>
APP_BUTTON_2 <32>
4
Q32
DTA114YKAT146_SOT23-3
IDE_LED#<20>
HT-297UY5/BP5_YELLOW-WHITE
12/26
Use Ripley white/Amber LED
HDD active LED
+3VS
47K
R852
D5
10K
2
12
43
YELLOW
APP_BUTTON_1
APP_BUTTON_2
IDE_LED#
HDD_STP
255_0402_1%
Q18
DTA114YKA_SC59
1 3
12
R853
255_0402_1%
21
WHITE
whiteAMBER
0.22U_0402_10V4Z
0.22U_0402_10V4Z
C967
C968
3
WL/BT_LED
BT_LED
BT_LED<30>
BT_LED
WL_LED
01/06
Small boa rd no more space,so add circuit on main board
+3VS
12
R881
470_0402_5%
D45
61
Q93A
TR 2N7002DW-7-F 2N SOT-363
2
2
1
+3VS
12
R880
470_0402_5%
61
Q94A
TR 2N7002DW-7-F 2N SOT-363
2
2
1
2 1
CH751H-40_SC76
2 1
CH751H-40_SC76
D46
2
WL_LED
R170 100K_0402_5%
1 2
R171 100K_0402_5%
1 2
R879
1M_0402_5%
1 2
1
C965
1U_0402_6.3V6K
2
R878
1M_0402_5%
1 2
1
C964
1U_0402_6.3V6K
2
2
12
R570
47K_0402_5%
61
Q10A
TR 2N7002DW-7-F 2N SOT-363
3
Q10B
TR 2N7002DW-7-F 2N SOT-363
5
4
APP_BUTTON_1_LED#
3
Q93B
TR 2N7002DW-7-F 2N SOT-363
5
4
APP_BUTTON_2_LED#
3
Q94B
TR 2N7002DW-7-F 2N SOT-363
5
4
+3VS+3VS
47K
Q9
DTA114YKAT146_SOT23-3
10K
2
1 3
WL_LED
WW_LED#<25>
12/26
LID sw itch on small board
1
WL_LED# <25>
13
10K
47K
+3VS
Q79
DTA114YKAT146_SOT23-3
2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Docu ment Number Re v
Custom
2
Date: Sheet
Compal Electronics, Inc.
LEDS & LID
LA-5221P
1
18 45Tuesday, February 03, 2009
0.1
of
Page 19
5
+3VS
1 2
R172 8.2K_0402_5%
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
12
R173 8.2K_0402_5%
R174 8.2K_0402_5%
D D
C C
R175 8.2K_0402_5%
R176 8.2K_0402_5%
R177 8.2K_0402_5%
R178 8.2K_0402_5%
R179 8.2K_0402_5%
+3VS
R180 8.2K_0402_5%
R181 8.2K_0402_5%
R182 8.2K_0402_5%
R183 8.2K_0402_5%
R184 8.2K_0402_5%
R185 8.2K_0402_5%
R186 8.2K_0402_5%
R187 8.2K_0402_5%
R188 8.2K_0402_5%
R189 8.2K_0402_5%
R191 8.2K_0402_5%
R192 8.2K_0402_5%
PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
01/13 HP review
Add R182 and R186
12/20 HP review
Update net(No ODD_DET#)
4
U8B
A11
AD0
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
B12
A10
C12
A8
A12
E10
C11
B9
D8
A4
E8
A3
D9
C8
C2
D7
B3
D11
B6
D5
D3
F4
E3
E4
B2
C4
C1
D1
E2
J4
H2
F1
F5
F2
PCI
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
Interrupt I/F
PIRQA#
PIRQB#
PIRQC#
PIRQD#C7PIRQH#/GPIO5
ICH9-M SFF ES_FCBGA569
REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55
C/BE0#
C/BE1#
C/BE2#
C/BE3#
IRDY#
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
PLTRST#
PCICLK
PME#
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PAR
3
G4
E1
A9
E12
B11
C10
D6
C6
D10
A5
E6
C9
C3
B1
T3
A7
D4
C5
H5
A6
A2
B8
A21
B5
T1
G3
G1
F3
H4
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
PCI_GNT3#
PCI_IRDY#
PCI_RST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PLT_RST#
CLK_PCI_ICH
12/20 HP review
Del PCI_PME#
R190 0_0402_5%
PCI_RST# <25,32>
PCI_SERR# <32>
PLT_RST# <8, 23,25,31>
CLK_PCI_ICH <15>
12
2
12/20 HP review
Update net(No ODD_DET#)
ACCEL_INT# <25>
1
B B
PCI_GNT3#
A A
A16 swap override Strap
Low= A16 swap override Enble
High= Default
PCI_GNT3#
*
12
R194
1K_0402_5% @
Boot BIOS Strap
PCI_GNT0# SPI_CS#1
12
R195
1K_0402_5%
1
0
1
0
1
1
PCI_GNT0#
DEL J3. 9/29
Boot BIOS Location
SPI
*
PCI
LPC
KBC_SPI_CS1#<21>
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
3
Place closely pin B10
CLK_PCI_ICH
12
R196
1K_0402_5%@
2006/02/13 2006/03/10
12
@
R193
10_0402_5%
1
@
C196
8.2P_0402_50V
2
Compal Secret Data
Deciphered Date
Title
Size Docu ment Number Re v
2
Date: Sheet
Compal Electronics, Inc.
ICH9(1/4)-PCI/INT
LA-5221P
19 45Tuesday, February 03, 2009
1
0.1
of
Page 20
+RTCVCC
1 2
R198 1M_0402_5%
1 2
R199 330K_0402_1%
1 2
R200 20K_0402_5%
D D
5
12/22 HP review
SM_INTRUDER#
ICH_INTVRMEN
ICH_SRTCRST#
C197
1U_0603_10V4Z
1
2
Del L AN10 0_SLP and del pull R
12/22 HP review
Del r eserved pull low R
4
3
2
1
ICH_RTCX1
TP24
PAD
ICH_RTCX2
ICH_RTCRST#
ICH_SRTCRST#
SM_INTRUDER#
ICH_INTVRMEN
T50PAD
HDA_SDIN0
AC97_SDOUT
GLAN_COMP
HDA_SYNC
HDARST#
R205
20K_0402_5%
+RTCVCC
+3VS
@
1 2
R206 1K_0201_5%
C C
B B
A A
AC97_SDOUT
GND
GND
GND
V33
V33
V33
GND
GND
GND
26
GND
25
GND
GND
Reserved
GND
V12
24
V12
NC
23
V12
NC
FOX_LD2122H-S43_NR
CONN@
12/24 HP review
Del ICH_RSVD net
12/22
Modify net name for IDT code
HDA_BITCLK_CODEC<27>
C600
56P_0402_50VNPO
HDA_SDOUT_CODEC<27>
C602
56P_0402_50VNPO
2.5' SATA HDD Connector
JP10
1
2
A+
A-
B-
B+
V5
V5
V5
5
SATA_TXN0_C
3
4
SATA_RXN0
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
12
12
C763 0.01U_0402_16V7K
1 2
C764 0.01U_0402_16V7K
1 2
C773 0.01U_0402_16V7K
1 2
C774 0.01U_0402_16V7K
1 2
C211
1
1
2
2
10U_0805_10V4Z
Place component's
closely SATA
CONN.(JP10)
1 2
1
12
C198
1U_0603_10V4Z
IDE_LED#<18>
C213
HDA_SDIN0<27>
0.1U_0402_16V4Z
+1.5VS
R221 33_0402_5%
+3VS
SATA_RXN0 _C
SATA_RXP0_C
SATA_TXN0_C R
SATA_TXP0_CR
C214
1
2
0.1U_0402_16V4Z
HDA_BITCLK_CODEC HDA_BITCLK
HDA_SYNC_CODEC<27>
HDA_RST#_CODEC<27>
HDA_SDOUT_CODEC
C212
1
2
0.1U_0402_16V4Z
CLRP1
2
SHORT PADS
12/22 HP review
Pin E25 contact with Pin D25
R220 24.9_0402_1%
1 2
R212 33_0402_5%
1 2
R213 33_0402_5%
1 2
R215 33_0402_5%
1 2
1 2
R229 10K_0201_5%
SATA_TXP0_CRSATA_TXP0_C
SATA_TXN0_C R
SATA_RXN0_C
SATA_RXP0_CSATA_RXP0
12/22
Fossil can support 2.5HD and SSD
+5VS
4
12/20 HP review
Del G_BATLED# and TP
12
12/22
Remove damping R
TP23
PAD
U8A
F25
RTCX1
G25
RTCX2
G24
RTCRST#
C24
SRTCRST#
C23
INTRUDER#
E25
INTVRMEN
D25
LAN100_SLP
G22
GLAN_CLK
D14
LAN_RSTSYNC
A14
LAN_RXD0
D12
LAN_RXD1
B14
LAN_RXD2
D13
LAN_TXD0
C13
LAN_TXD1
A13
LAN_TXD2
D15
GPIO56
H22
GLAN_COMPI
H21
GLAN_COMPO
AE7
HDA_BIT_CLK
AB7
HDA_SYNC
AA7
HDA_RST#
AB6
HDA_SDIN0
AE6
HDA_SDIN1
AC6
HDA_SDIN2
AA5
HDA_SDIN3
AC7
HDA_SDOUT
AD8
HDA_DOCK _EN#/GPIO33
AB8
HDA_DOCK_RST#/GPIO34
AC9
SATALED#
AE14
SATA0RXN
AD14
SATA0RXP
AC15
SATA0TXN
AD15
SATA0TXP
AD13
SATA1RXN
AC13
SATA1RXP
AA14
SATA1TXN
AB14
SATA1TXP
ICH9-M SFF ES_FCBGA569
01/13
Add test point
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
3
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
FWH4/LFRAME#
RTCLAN / GLAN
LPCCPU
LDRQ0#
LDRQ1#/GPIO23
A20GATE
A20M#
DPRSTP#
DPSLP#
FERR#
CPUPWRGD
IGNNE#
INIT#
INTR
RCIN#
NMI
SMI#
STPCLK#
THRMTRIP#
TP11
SATA4RXN
SATA4RXP
IHDA
SATA4TXN
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATA_CLKN
SATA_CLKP
SATA
SATARBIAS#
SATARBIAS
12/20
R230 use 24.9ohm(as intel design,skyy use 18ohm)
R231
1 2
10M_0402_5%
C20612P_0402_50V8J
1
1
2
Y2
OSC4OSC
NC3NC
2
2006/02/13 2006/03/10
LPC_AD0
H3
LPC_AD1
J3
LPC_AD2
K5
LPC_AD3
L3
J2
H1
J1
GATEA20
N3
AB23
H_DPRSTP_R#
AE23
AE24
H_FERR#_R
AD25
AE22
AD23
AE21
AD24
KB_RST#
L1
AD21
H_SMI#
AC21
H_STPCLK#
AC25
THRMTRIP_ICH#
AC23
AC22
AD12
AE12
AB12
AA12
AC11
AD11
AB10
AA10
CLK_PCIE_SATA#
AC16
CLK_PCIE_SATA
AB16
AD10
AE10
ICH_RTCX1
ICH_RTCX2
C20712P_0402_50V8J
1
2
32.768KHZ_12.5PF_Q13MC1461005000
Compal Secret Data
T49 PAD
R230 24.9_0402_1%
Within 500 mils
+RTCVCC +3VL
Deciphered Date
LPC_A D[0..3] <25,31,32>
LPC_FRAME# <25,31,32>
T111 PAD
T48 PAD
GATEA20 <32>
H_A20M# <4>
R209 0_0402_5%
1 2
H_DPSLP# <5>
R210 56_0402_5%
1 2
H_PWRGOOD <4,5>
H_IGNNE# <4>
H_INIT# <4>
H_INTR <4>
KB_RST# <32>
H_NMI <4>
H_SMI# <4>
H_STPCLK# <4>
R226 54.9_0402_1%
1 2
placed within 2" from
ICH9M
CLK_PCIE_SATA# <15>
CLK_PCIE_SATA <15>
1 2
R232 0_0402_5%
1 2
1
C210
1U_0603_10V4Z
2
2
H_DPRSTP# <5,8,42>
H_FERR#
Place Close to U8.
+VCCP
12
R223
56_0402_5%
D8
3
1
DAN202UT106_SC70-3
2
Custom
Date: Sheet
12/12
+1.05VM-->+VCCP
+VCCP
R207
56_0402_5%
1 2
H_FERR# <4>
+3VS
GATEA20
R216 10K_0201_5%
KB_RST#
R233
1K_0402_5%
RTC1
1 2
W=20mils
L
Title
Size Docu ment Number Re v
Compal Electronics, Inc.
ICH9(2/4)_LAN,HD,IDE,LPC
LA-5221P
1 2
R218 10K_0201_5%
1 2
H_THERMTRIP# <4,8>
12/23
Update JBATT1 footprint
RTC2
1
-+
JBATT1
1
1
2
2
3
G1
4
G2
ACES_85204-02001
CONN@
20 45Tuesday, February 03, 2009
of
0.1
Page 21
+3VS
1 2
R326 10K_0201_5%
1 2
R234 10K_0201_5%
1 2
R237 8.2K_0402_5%
1 2
R245 47K_0402_5%
1 2
R246 8.2K_0402_5%
D D
1 2
R848 8.2K_0402_5%
1 2
R508 8.2K_0402_5%
1 2
R621 10K_0201_5%
12/24 HP review
Del GPIO5 7
+3VALW
C C
+3VALW
B B
A A
R252
1 2
1 2
R255 10K_0201_5%
1 2
R258 10K_0201_5%
1 2
R321 10K_0201_5%
1 2
R266 10K_0201_5%
12/20 No AC_PRESENT
R331
1 2
10K_0201_5%
1 2
R72610K_0402_5%
1 2
R724 10K_0201_5%
R238 10K_0201_5%
1 2
1 2
R603 10K_0201_5%
Add in 9/14.
1 2
R335 10K_0201_5%
ICH_SMBDATA<4,14,15,25>
ICH_SMBCLK<4,14,15,25>
ICH_SM_DA<4,1 4,15,25>
ICH_SM_CLK<4,14,15,25>
12/20 HP review
Del some part(ALS_EN#)
5
LAN_STATUS#_D PM_PWROK
SIRQ
PM_CLKRUN#
HDD_HALTLED
GPIO22
GPIO21
GPIO37
GPIO17
10K_0201_5%
LINKALERT#
PCIE_WAKE#
ICH_RI#
ICH_LOW_BAT#
SUS_PWR_ACK
CB_IN_R
USB_OC#7
USB_OC#5
USB_OC#0
USB_OC#4
USB_OC#1
USB_OC#2
USB_OC#6
WXMIT_OFF#
GPIO11
XMIT_OFF#
EXP_RST
12/20 HP review
No S4_STATE#
R282
2.2K_0402_5%
ICH_SMBDATA
12/24 HP review
Reserved on Page4
12/20 HP review
No ALS_EN#
12/24 HP review
GPIO18-->GPIO17
H_STP_PCI#<15>
H_STP_CPU#<15>
12/29 HP review
XDP_DBRESET#( +3VALW-->+3 VS)
+3VS
1 2
R259 1K_0201_5%
12/24 HP review
LAN_STATUS#-->LANLINK_STATUS#
LANLINK_STATUS#<23,24>
CB_IN<24>
12/20 HP review
Updat e net mane
R276
low -->default
High -->No boot
12/20 HP review
Use the same as pull high R
12/20 HP review
Updat e net mane
12/20 HP review
+3VM-->+3VS
+3VS
R283
12
12
2.2K_0402_5%
Q12
RHU002N06_SOT323
D
S
13
D
S
G
2
G
2
+3VS
12/20 HP review
+3VM-->+3VS
XDP_DBRESET#
13
Q13
RHU002N06_SOT323
12/20 HP review
Remove reserved R
12/30 HP review
Contac t E18 and A24
+3VS
12/24 HP review
Install R
12
12
R249
10K_0201_5%
+3VS
+3VS
+3VS +3VALW
+3VALW
12
02/02
No support Express card
ICH_SMB_DATA
ICH_SMB_CLKICH_SMBCLK
R250
10K_0201_5%
12/20 HP review
Remove reserved R
D40 CH751H-40_SC76
R268 10K_0201_5%
1 2
12/20 HP review
No ALS_EN#
R275 8.2K_0402_5%
1 2
R857 10K_0201_5%
1 2
12/24 HP review Del GPIO57(A16)
R276 1K_0402_5% @
1 2
R280
10K_0201_5%
1 2
R332 0_0201_5%
KBC_S PI_CLK_R<32>
KBC_SPI_CS0#_R<32>
KBC_SPI_CS1#_R<32>
KBC_SPI_CS1#<19>
KBC_SPI_SI_R<32>
KBC_SPI_SO<32>
WXMIT_OFF#<25>
WEBCAM_ON/OFF#<17>
01/02 Add pull high R
+3VALW
5
1 2
R877 10K_0201_5%
4
2.2K_0402_5%
+3VALW
12/20 HP review
Remove TP
XDP_DBRESET#<4>
PM_BMBUSY#<8>
R253 0_0201_5%
1 2
PM_CLKRUN#<32>
PCIE_WAKE#<23>
THERM_SCI#<4>
RUNSCI_EC#<32>
21
LID_SW#<17,29,32>
12/24 HP review
GPIO18-->GPIO17
CLKSATAREQ#<15>
SB_SPKR<27>
MCH_ICH_SYNC#<8>
12/24 HP review
Del ICH_RSVD net
ISO_PREP#
PCIE_RXN2<25>
PCIE_RXP2<25>
PCIE_TXN2<25>
PCIE_TXP2<25>
ICH_SMB_DATA
ICH_SMB_CLK
GLAN_RXN<23>
GLAN_RXP<23>
GLAN_T XN<23>
GLAN_TX P<23>
BT_OFF<30>
XMIT_OFF#<25>
USB_OC#11
4
+3VALW
12
12
R236
R235
2.2K_0402_5%
ICH_SMB_CLK
ICH_SMB_DATA
LINKALERT#
1 2
R272 10K_0201_5%
OCP#<43>
ICH_RI#
XDP_DBRESET#
PM_BMBUSY#
GPIO11
H_STP_PCI#
R_STP_CPU#
PM_CLKRUN#
PCIE_WAKE#
SIRQ
SIRQ<31,32>
THERM_SCI#
VRMPWRGD
LAN_STATUS#_DLANLINK_STATUS#
ISO_PREP#
CB_IN_R
GPIO17
GPIO22
GPIO38
GPIO39
EXP_RST
SB_SPKR
MCH_ICH_SYNC# AC_PRESENT
12/20
Remove TP
C227 0.1U_0402_16V4Z
1 2
C228 0.1U_0402_16V4Z
1 2
12/20
G LAN interface
C920 0 .1U_0402_16V4Z
1 2
C453 0 .1U_0402_16V4Z
1 2
R285 15_0402_5%
1 2
R286 15_0402_5%
1 2
R290 15_0402_5%
1 2
R289 15_0402_5%
1 2
R291 0_0402_5%
1 2
12
R293
22.6_0402_1%
U8C
C18
SMBCLK
C15
SMBDATA
B21
LINKALERT#/GPIO60/CLGPIO4
E18
SMLINK0
A24
SMLINK1
C20
RI#
T5
SUS_STAT#/LPCPD#
C25
SYS_RESET#
L2
PMSYNC#/GPIO0
A23
SMBALERT#/GPIO11
B15
STP_PCI#/GPIO15
A20
STP_CPU#/GPIO25
M5
CLKRUN#/GPIO32
C21
WAKE#
L4
SERIRQ
AD20
THRM#
B24
VRMPWRGD
A19
TP12
AE16
GPIO1
AE18
GPIO6
AD18
GPIO7
B25
GPIO8
C14
GPIO12
D20
GPIO13
AE17
GPIO17
K3
GPIO18
AC8
GPIO20
AC19
SCLOCK/GPIO22
D17
GPIO27
E20
GPIO28
M4
SATACLKREQ#/GPIO35
AB18
SLOAD/GPIO38
AC18
SDATAOUT0/GPIO39
AB19
SDATAOUT1/GPIO48
AC20
GPIO49
A16
GPIO57/CLGPIO5
K4
SPKR
AB20
MCH_SYNC#
C19
TP3
AB17
TP8
AC17
TP9
AD17
TP10
ICH9-M SFF ES_FCBGA569
PCIE_RXN2
PCIE_RXP2
PCIE_C_TXN2
PCIE_C_TXP2
GLAN_RXN
GLAN_RXP
GLAN_TXN_C
GLAN_TXP_C
KBC_SPI_CLK
KBC_SPI_CS0#
KBC_SPI_CS1#
KBC_SPI_SI
USB_OC#0
USB_OC#1
USB_OC#2
WXMIT_OFF#
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
XMIT_OFF#
USB_OC#11
USBRBIAS
Within 500 mils
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
3
U8D
T25
PERN1
T24
PERP1
R24
PETN1
R23
PETP1
P25
PERN2
P24
PERP2
P21
WLAN
PETN2
P22
PETP2
N23
PERN3
N24
PERP3
M21
M22
M25
M24
G23
AE5
AD5
EXP
PETN3
PETP3
PERN4
PERP4
L24
WWAN
PETN4
L23
PETP4
K24
PERN5
K25
PERP5
K21
PETN5
K22
PETP5
H24
PERN6/GLAN_RXN
H25
PERP6/GLAN_RXP
J24
PETN6/GLAN_TXN
J23
PETP6/GLAN_TXP
E24
SPI_CLK
E23
SPI_CS0#
F23
SPI_CS1#/GP IO58/CLGPIO6
F22
SPI_MOSI
SPI_MISO
P4
OC0#/GPIO59
N4
OC1#/GPIO40
N1
OC2#/GPIO41
P5
OC3#/GPIO42
P1
OC4#/GPIO43
P2
OC5#/GPIO29
M3
OC6#/GPIO30
M2
OC7#/GPIO31
P3
OC8#/GPIO44
R1
OC9#/GPIO45
R4
OC10#/GPIO46
R2
OC11#/GPIO47
USBRBIAS
USBRBIAS#
ICH9-M SFF ES_FCBGA569
Issued Date
3
12/20 HP review
Remove damping R
SMB
SYS GPIO
GPIO
MISC
PM_PWROK <8,32,42>
GPIO21
CLK14
CLK48
SUSCLK
SLP_S3#
SLP_S4#
SLP_S5#
PWROK
BATLOW#
PWRBTN#
LAN_RST#
RSMRST#
CK_PWRGD
CLPWROK
SLP_M#
CL_CLK0
CL_CLK1
CL_DATA0
CL_DATA1
CL_VREF0
CL_VREF1
CL_RST0#
CL_RST1#
V25
V24
U24
U23
W23
W24
V21
V22
Y24
Y25
Y21
Y22
AB24
AB25
AA23
AA24
T21
T22
AB21
AB22
AE2
AD1
AD3
AD4
AC2
AC3
AC5
AB4
AB2
AB1
AA3
AA2
Y1
Y2
W2
W3
V1
V2
Y5
Y4
U3
U2
V4
V5
AE19
HDD_HALTLED
AA18
AE20
GPIO37
AA20
CLK_14M_ICH
K1
CLK_48M_ICH
AB5
ICH_SUSCLK
R3
SLP_S3#
D18
SLP_S4#
B20
SLP_S5#
D16
E14
PM_PWROK
D23
DPRSLPVR
M1
ICH_LOW_BAT#
C16
U4
R725 10K_0201_5%
D22
1 2
RSMRST#
D19
U1
T4
B23
C22
A18
E22
B18
F21
A17
C17
B17
A22
E16
A15
D21
12/20 HP review
Del net
DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1
DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2
DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3
CLK_PCIE_ICH#
CLK_PCIE_ICH
R263 10K_0201_5%
CK_PW RGD_R
PM_PWROK
CL_CLK0
CL_DATA0
CL_VREF0_ICH
CL_VREF1_ICH
CL_RST#
SUS_PWR_ACK
DMI_IRCOMP
Compal Secret Data
Deciphered Date
R265 0_0201_5%
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37
SATA
GPIO
Clocks
S4_STATE#/GPIO26
DPRSLPVR/GPIO16
Power MGTController Link
MEM_LED /GPIO24
GPIO10/SUS_PWR_ACK
GPIO14/AC_PRESENT
WOL_EN/GP IO9
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
DMI_CLKN
PCI-Express
DMI_CLKP
Direct Media Interface
DMI_ZCOMP
DMI_IRCOMP
USBP0N
USBP0P
USBP1N
GLAN
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
SPI
USBP5P
USBP6N
USB
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
2006/02/13 2006/03/10
2
HDD_HALTLED <18>
12/20 HP review
Del NCPI_RST#
CLK_14M_ICH <15>
CLK_48M_ICH <15>
T53 PAD
SLP_S3# <23,27,32,33,34,37,38,40,41,43>
SLP_S4# <34,39>
SLP_S5#
R254 10K_0201_5%
1 2
1 2
R256 0_0201_5%
ON/O FFBT N# <29>
1 2
1 2
CL_CLK0 <8>
CL_DATA0 <8>
CL_RST# <8>
LP_EN <23>
R284 24.9_0402_1%
USB20_N0 <30>
USB20_P0 <30>
USB20_N1 <28>
USB20_P1 <28>
USB20_N4 <28>
USB20_P4 <28>
USB20_N5 <28>
USB20_P5 <28>
USB20_N6 <30>
USB20_P6 <30>
USB20_N7 <25>
USB20_P7 <25>
USB20_N10 <17>
USB20_P10 <17>
12/20 HP review
Del S4_STATE# and R254 install
DMI_RXN0 <8>
DMI_RXP0 <8>
DMI_TXN0 <8>
DMI_TXP0 <8>
DMI_RXN1 <8>
DMI_RXP1 <8>
DMI_TXN1 <8>
DMI_TXP1 <8>
DMI_RXN2 <8>
DMI_RXP2 <8>
DMI_TXN2 <8>
DMI_TXP2 <8>
DMI_RXN3 <8>
DMI_RXP3 <8>
DMI_TXN3 <8>
DMI_TXP3 <8>
CLK_PCIE_ICH# <15>
CLK_PCIE_ICH <15>
1 2
12/20 HP review
Add pull low R
R366 0_0201_5%
12/29 HP review
PWROK-->PM_PWROK
MB
Small board
card reader
Small board
Bluetooth
WWAN
USB Camera
2
VRMPWRGD
13
D
2
G
S
Q63
RHU002N06_SOT323
12/29 HP review
PM_PWROK_R-->PM_PWROK
PM_DPRSLPVR <8,42>
1 2
PM_RSMRST# <32>
CK_ PWRGD <15>
R271
3.24K_0402_1%
1 2
12
1
R274
2
453_0402_1%
C225
0.1U_0402_16V4Z
R277
3.24K_0402_1%
1 2
12
1
R278
2
C226
453_0402_1%
0.1U_0402_16V4Z
Within 500 mils
+1.5VS
12/20
Fine tune USB support device
02/02
No support Express card
Title
Size Docu ment Number Re v
Custom
Date: Sheet
1
R595 10K_0201_5%
1 2
R858
1 2
10K_0201_5%
12/29 HP review
1
Remove damping R and add pull +3VALW R
C547
0.1U_0402_16V4Z @
2
+3VALW
R257
100K_0402_5%
1 2
RPGOOD <38>
+3VS
AC_PRESENT
1 2
R851 10K_0201_5%
12/24 HP review
LAN_STATUS#-->LANLINK_STATUS#
???
+3VS
+3VALW
12/20 HP review
+3VL-->+3VALW
12/20 HP review
Del diode
CLK_ENABLE# <42>
ADP_PRES <23,32,37>
Place closely pin H1Place closely pin AF3
CLK_14M_ICHCLK _48M_ICH
12
@
R239
10_0402_5%
@
1
C223
4.7P_0402_50V8C
2
12
@
R240
10_0402_5%
@
1
C224
4.7P_0402_50V8C
2
Compal Electronics, Inc.
ICH9(3/4)_DMI,USB,GPIO,PCIE
LA-5221P
21 45Tuesday, February 03, 2009
1
0.1
of
Page 22
5
+RTCVCC
C235
0.1U_0402_16V4Z
R295
D D
+1.5VS
1 2
BLM18PG181SN1D_0603
646mA
220U_B2_2.5VM_R35
C242
12/29 C242(D2 ESR15M-->B2 ESR35M)
+5VS +3VS +3VALW+5VALW
12
R298
100_0402_5%
C C
+1.5VS
B B
+1.5VS
MBK1608301YZF 0603
12/20
+3VM_WOL-->+3VS
+3VS
01/11
Del R302
A A
21
1
2
R301
1 2
0.1U_0402_16V4Z
78mA
D11
CH751H-40_SC76
2mA
ICH_V5REF_RUN
20 mils
C251
1U_0603_10V6K
12/20 HP review
C251 use X5R cap
47mA
R300
1 2
MBK1608301YZF 0603
+1.5VS_USBPLL
11mA
1
2
C265
0.1U_0402_16V4Z
+1.5VS
1
2
C268
0.1U_0402_16V4Z
5
1U_0603_10V4Z
1
2
C266
R303
MBK1608301YZF 0603
1 2
23mA
1
1
C236
2
2
1
+
2
R299
10_0402_5%
1
1
2
2
C257
C256
10U_0805_10V4Z
C267
0.1U_0402_16V4Z
12
10U_0805_10V4Z
20 mils
+1.5VS_PCIE_ICH
0.1U_0402_16V4Z
40 mils
1
1
2
2
C239
C240
10U_0805_10V4Z
12
+1.5VS
1342mA
+1.5VS_PCIE_ICH
1
2
C269
ICH_V5REF_RUN
ICH_V5REF_SUS
1
2
C241
10U_0805_10V4Z
2.2U_0 603_6.3V4Z
21
D12
CH751H-40_SC76
ICH_V5REF_SUS
20 mils
1
C252
0.1U_0402_16V4Z
2
+1.5VS_VCCSATAPLL
1
2
C258
1U_0603_10V4Z
1
2
C259
1U_0603_10V4Z
1
2
C263
0.1U_0402_16V4Z
VCC_LAN1_05_INT_ICH
+1.5VS_GLAN
1
2
C270
10U_0805_10V4Z
+3VS
2mA
M18
M19
W17
W13
W12
W10
W18
G17
G7
J19
K18
K19
L18
L19
N18
N19
P18
R18
T18
T19
U18
U19
U13
V13
U12
V12
U15
V15
G9
V11
U11
G11
H11
G12
H13
J17
H19
J18
K16
4
U8F
VCCRTC
V5REF
U7
V5REF_SUS
VCC1_5_B[01]
VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCCSATAPLL
VCC1_5_A[01]
VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]
VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
VCC1_5_A[09]
VCC1_5_A[10]
VCC1_5_A[11]
H9
VCC1_5_A[12]
VCC1_5_A[13]
VCC1_5_A[14]
U8
VCCUSBPLL
T9
VCC1_5_A[15]
U9
VCC1_5_A[16]
VCCLAN1_05[1]
VCCLAN1_05[2]
VCCLAN3_3[1]
VCCLAN3_3[2]
VCCGLANPLL
VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN3_3
ICH9-M SFF ES_FCBGA569
4
VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
CORE
V_CPU_IO[1]
V_CPU_IO[2]
VCCA3GP ATXARX USB CORE
VCCP_CORE
PCI
VCCSUSHDA
VCCSUS1_05[1]
VCCSUS1_05[2]
VCCSUS1_5[1]
VCCSUS1_5[2]
VCCSUS3_3[01]
VCCSUS3_3[02]
VCCSUS3_3[03]
VCCPSUSVCCPUSB
VCCSUS3_3[04]
VCCSUS3_3[05]
VCCSUS3_3[06]
VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCCL3_3[1]
VCCCL3_3[2]
GLAN POWER
VCCDMIPLL
VCC_DMI[1]
VCC_DMI[2]
VCC3_3[01]
VCC3_3[02]
VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]
VCC3_3[07]
VCC3_3[08]
VCCHDA
VCCCL1_05
VCCCL1_5
L11
L12
L13
L14
L15
M11
M15
N11
N15
P11
P15
R11
R12
R13
R14
R15
P19
T17
U17
V16
U16
V18
AE9
AA9
V14
W14
G8
H7
H8
AD7
V10
T7
H15
H16
V7
G14
G15
H14
W8
J7
J8
K7
K8
L7
L8
M7
M8
N7
N8
P7
P8
G18
H17
J14
K14
+VCCP
+1.5VS_DMIPLL
VCCCL1_05_ICH
1 2
C264 1U_0603_10V4Z
12/20
+3VM_WOL-->+3VS
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
3
1634mA
1
1
2
2
C238
C237
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C244
C243
10U_0805_10V4Z
0.01U_0402_16V7K
9/29
VCC_DMI
(DMI)
0.1U_0402_16V4Z
+3VS
1
2
C253
0.1U_0402_16V4Z
12/20 HP review
Del TP
+3VALW
1
212mA
2
C262
4.7U_0805_10V4Z
C217
0.1U_0402_16V4Z
1 2
+3VS
3
23mA
R296
1 2
MBK1608301YZF 0603
48mA
R297
1 2
MBK1608301YZF 0603
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
2
C248
1
2
C260
0.1U_0402_16V4Z
308mA
2
2
C250
C249
+3VALW
1
2
C255
0.1U_0402_16V4Z
+3VALW
1
2
C261
0.1U_0402_16V4Z
2006/02/13 2006/03/10
9/29
+1.5VS
+VCCP
+3VS
1
2
C254
0.1U_0402_16V4Z
Compal Secret Data
VCC_DMI
1
2
C245
1U_0603_10V4Z
+VCCP
0.1U_0402_16V4Z
4.7U_0805_10V4Z
1
2
C246
+3VS
Deciphered Date
1
2
C247
2
U8E
B4
VSS[001]
B7
VSS[002]
B10
VSS[003]
B13
VSS[004]
B16
VSS[005]
B19
VSS[006]
B22
VSS[007]
D2
VSS[008]
D24
VSS[009]
E5
VSS[010]
E7
VSS[011]
E9
VSS[012]
E11
VSS[013]
E13
VSS[014]
E15
VSS[015]
E17
VSS[016]
E19
VSS[017]
E21
VSS[018]
F24
VSS[019]
G2
VSS[020]
G5
VSS[021]
G10
VSS[022]
G13
VSS[023]
G16
VSS[024]
G19
VSS[025]
G21
VSS[026]
H10
VSS[027]
H12
VSS[028]
H18
VSS[029]
H23
VSS[030]
J5
VSS[031]
J9
VSS[032]
J10
VSS[033]
J11
VSS[034]
J12
VSS[035]
J13
VSS[036]
J15
VSS[037]
J21
VSS[038]
J22
VSS[039]
J25
VSS[040]
K2
VSS[041]
K9
VSS[042]
K10
VSS[043]
K11
VSS[044]
K12
VSS[045]
K13
VSS[046]
K15
VSS[047]
K17
VSS[048]
K23
VSS[049]
L5
VSS[050]
L9
VSS[051]
L10
VSS[052]
L16
VSS[053]
L17
VSS[054]
L21
VSS[055]
L22
VSS[056]
L25
VSS[057]
M9
VSS[058]
M10
VSS[059]
M12
VSS[060]
M13
VSS[061]
M14
VSS[062]
M16
VSS[063]
M17
VSS[064]
M23
VSS[065]
N2
VSS[066]
N5
VSS[067]
N9
VSS[068]
N10
VSS[069]
N12
VSS[070]
N13
VSS[071]
N14
VSS[072]
N16
VSS[073]
N17
VSS[074]
N21
VSS[075]
N22
VSS[076]
N25
VSS[077]
P9
VSS[078]
P10
VSS[079]
P12
VSS[080]
P13
VSS[081]
P14
VSS[082]
P16
VSS[083]
P17
VSS[084]
P23
VSS[085]
R5
VSS[086]
R7
VSS[087]
R8
VSS[088]
R9
VSS[089]
R10
VSS[090]
R16
VSS[091]
R17
VSS[092]
R19
VSS[093]
R21
VSS[094]
R22
VSS[095]
R25
VSS[096]
T2
VSS[097]
T8
VSS[098]
T10
VSS[099]
T11
VSS[100]
T12
VSS[101]
T13
VSS[102]
T14
VSS[103]
T15
VSS[104]
T16
VSS[105]
T23
VSS[106]
ICH9-M SFF ES_FCBGA569
2
1
U5
VSS[107]
U10
VSS[108]
W11
VSS[109]
U14
VSS[110]
W16
VSS[111]
U21
VSS[112]
U22
VSS[113]
U25
VSS[114]
V3
VSS[115]
V8
VSS[116]
V19
VSS[117]
V23
VSS[118]
W1
VSS[119]
W4
VSS[120]
W5
VSS[121]
W7
VSS[122]
W9
VSS[123]
W15
VSS[124]
W19
VSS[125]
W21
VSS[126]
W22
VSS[127]
W25
VSS[128]
Y3
VSS[129]
Y23
VSS[130]
AA1
VSS[131]
AA4
VSS[132]
AA6
VSS[133]
AA8
VSS[134]
AA11
VSS[135]
AA13
VSS[136]
AA15
VSS[137]
AA16
VSS[138]
AA17
VSS[139]
AA19
VSS[140]
AA21
VSS[141]
AA22
VSS[142]
AA25
VSS[143]
AB3
VSS[144]
AB9
VSS[145]
AB11
VSS[146]
AB13
VSS[147]
AB15
VSS[148]
AC24
VSS[149]
AC1
VSS[150]
AC4
VSS[151]
AC10
VSS[152]
AC12
VSS[153]
AC14
VSS[154]
AD2
VSS[155]
AD6
VSS[156]
AD9
VSS[157]
AD16
VSS[158]
AD19
VSS[159]
AD22
VSS[160]
AE3
VSS[161]
AE4
VSS[162]
AE11
VSS[163]
AE13
VSS[164]
AE15
VSS[165]
V17
VSS[166]
AE8
VSS[167]
V9
VSS[168]
J16
VSS[169]
12/12 FOR NO CRACK DETECT FUNCTION
VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
A1
A25
AE1
AE25
Title
Size Docu ment Number Re v
Custom
Date: Sheet
Compal Electronics, Inc.
ICH9(4/4)_POWER&GND
LA-5221P
1
22 45Tuesday, February 03, 2009
0.1
of
Page 23
5
12/24 HP review
Use +3VS power rail
R540
10K_0402_5%
CLK_PCIE_LAN_REQ#<15>
D D
+3VS
12
1 3
+3VS
12
R709
10K_0402_5%
2
G
D
S
2N7002_SOT23-3
Q91
+3V_LAN
12
R541
10K_0402_5%
CLK_LAN_REQ#
4
2N7002DW-7-F_SOT363-6
ADP_PRES<21,32,37>
SLP_S3#<21,27,32,33,34,37,38,40,41,43>
Q92A
2
6 1
3
5
Q92B
2N7002DW-7-F_SOT363-6
4
+3VALW
SI2301BDS_SOT23
12
R539
47K_0402_5%
47K_0402_5%
R710
3
S
Q65
G
12
+3V_LAN
D
13
370mA
2
+3V_LAN
0.1U_0402_16V4Z
1
C489
2
0.1U_0402_16V4Z
1
C490
2
2
0.1U_0402_16V4Z
1
C491
2
0.1U_0402_16V4Z
1
1
1
C492
C493
0.1U_0402_16V4Z
2
2
V1.8_LAN
0.1U_0402_16V4Z
1
C494
2
0.1U_0402_16V4Z
1
C495
2
LED_ACTn
TESTMODE
AVDDH
AVDD
AVDD
VDDO_TTL
VDDO_TTL
VDDO_TTL
VDDO_TTL
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
EAPD
SMALERTn
SMCLK
Reserved
Reserved
Reserved
SMDATA
0115 Marvell
Open P in62 Pin63
59
60
62
63
46
8
19
22
NC
23
NC
28
1
40
45
61
2
7
13
33
39
44
48
58
65
51
NC
52
NC
32
57
64
24
25
29
43
LAN_ACT#
R711 10K_0402_5%
1 2
LANLINK_STATUS#
+3V_LAN
V1.8_LAN
+3V_LAN
V1.2_LAN
12/20
Del reserved part(Support 8072 only)
12/20
Del reserved SPI part
LAN_A CT# <24>
+3V_LAN
LANLINK_STATUS# <21,24>
12/26
8072@-->install
151mA
379mA
V1.2_LAN
2SB1188T100R_SC62-3
V1.8_LAN
V1.2_LAN
0.1U_0402_16V4Z
1
C913
2
0.1U_0402_16V4Z
V1.2_LAN
0.1U_0402_16V4Z
1
C917
2
0.1U_0402_16V4Z
+3V_LAN
C9254.7U_0805_10V4Z
12
C50910U_0805_10V4Z
12
+3V_LAN
C9274.7U_0805_10V4Z
12
C51310U_0805_10V4Z
12
1
1
C914
2
0.1U_0402_16V4Z
1
C918
2
0.1U_0402_16V4Z
R714 4.7K_0402_5%
Q68
2SB1188T100R_SC62-3
2 3
Q69
2 3
12/26
Del reserved part(Support 8072 only)
1
C915
2
2
1
1
C953
2
2
12
CTRL12
1
R718 4.7K_0402_5%
12
1
C916
0.1U_0402_16V4Z
C924
0.1U_0402_16V4Z
CTRL18
12/20
Update net
LAN_DIS#
+3V_LAN
CLK_LAN_REQ#
PCIE_WAKE#
CLK_PCIE_LAN
CLK_PCIE_LAN#
12
R719
4.7K_0402_5%
R544 0_0402_5%
R546 0_0402_5%
1 2
LAN_DIS#
+3V_LAN
1 2
GLAN_RXP<21>
GLAN_RXN<21>
GLAN_TX P<21>
GLAN_T XN<21>
PCIE_WAKE#<21>
CLK_PCIE_LAN<15>
CLK_PCIE_LAN#<15>
PLT_RST#<8 ,19,25,31>
LAN_MDI0P<24>
LAN_MDI0N<24>
LAN_MDI1P<24>
12/26
8072@-->install
1 2
4.7K_0402_5%
LAN_EE_CLK
LAN_EE_DATA
LAN_MDI1N<24>
LAN_MDI2P<24>
LAN_MDI2N<24>
LAN_MDI3P<24>
LAN_MDI3N<24>
12/20
Del reserved SPI net
01/23
No support 8075
LAN_X1
LAN_X2
12
R557
C C
C92627P_0402_50V8J
12
25MHZ_20P_1BG25000CK1A
B B
0.1U_0402_16V4Z
U33
1
CS#
2
SO
3
WP#
4
GND
CAT24C08WI-GT3 SO 8P
Y6
C50827P_0402_50V8J
12
C511
12
8
VCC
7
HOLD#
6
SCK
5
SI
PCIE_RXP6_LAN
C9190.1U_0402_16V4Z
12
PCIE_RXN6_LAN
C4970.1U_0402_16V4Z
12
1 2
LAN_EE_CLK
LAN_EE_DATA
LAN_X1
LAN_X2
R550 0_0402_5%8075@
1 2
+3VS
CTRL18
CTRL12
4.99K_0402_1%
R715
+3V_LAN
88E8072 88E8075
R653
C533
R440
A A
Q28
U31
42
CLKREQn
49
TX_P
50
TX_N
54
53
6
55
56
5
17
18
20
21
26
27
30
31
38
41
34
35
37
36
15
14
10
9
11
12
47
4
3
16
R717 10K_0402_5%
1 2
2N7002_SOT23-3
PCI-E
RX_P
RX_N
WAKEn
REFCLKP
REFCLKN
PERSTn
MDIP0
MDIN0
MDIP1
MDIN1
Media
MDIP2
MDIN2
MDIP3
MDIN3
VPD_CLK
EEPROM
VPD_DATA
SPI_DO
SPI_DI
FLASH
SPI_CLK
MEMORY
SPI_CS
XTALI
CLOCK
XTALO
LOM_DISABLEn(USB_DM-)
SWITCH_VAUX(USB_DP+)
SWITCH_VCC(LOM_DISABLEn)
VAUX_AVLBL
VMAIN_AVLBL
CTRL18
CTRL12
Analog
RSET
S
Q14
D
1 3
R654
R655
U36
C694
R659
LED
LED_LINK10/100n
LED_LINK1000n
LED_DUPLEXn
TEST
POWER
&
GROUND
(PD18LDO)NC
No Connect
88E8072 & 88E8075_QFN64
LAN_DIS#
G
2
LP_EN <21>
12/22 HP review
Add LP_EN
R658
Insert
5
4
R656
R652
R660
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
3
2008/10/03 2009/10/03
Compal Secret Data
Deciphered Date
2
Title
Size Docu ment Number Re v
Date: Sheet
Compal Electronics, Inc.
23 45Tuesday, February 03, 2009
1
of
0.1
Page 24
5
D D
4
3
2
1
12/15 No support Docking
Delete all termination cause they are already inside BOAZMAN. 9/28
12/23
+1.8VM-->V1.8_LAN
C C
B B
LAN_ACT#
LANLINK_STATUS#
2
3
D44
PACDN042_SOT23~D@
Reserve to
1
prevent ESD issue
as other project.
1/18
A A
C297 0.1U_0402_16V7K
C299 0.1U_0402_16V7K
C304 0.1U_0402_16V7K
C305 0.1U_0402_16V7K
V1.8_LAN
12
V1.8_LAN
12
V1.8_LAN
12
V1.8_LAN
12
LAN_MDI0P<23>
LAN_MDI0N<23>
TRM_CT
LAN_MDI1P<23>
LAN_MDI1N<23>
TRM_CT
LAN_MDI2P<23>
LAN_MDI2N<23>
TRM_CT
LAN_MDI3P<23>
LAN_MDI3N<23>
LAN_ACT#<23>
LANLINK_STATUS#<21,23>
T69
12
TD4-
11
TD4+
10
TCT4
9
TD3-
8
TD3+
7
TCT3
6
TD2-
5
TD21+
4
TCT2
3
TD1-
2
TD1+
1
TCT1
X'FORM_ NS692405 LAN_24P
LAN_ACT#
1 2
C311680P_0402_50V7K@
LANLINK_STATUS#
1 2
C312680P_0402_50V7K@
1:1
1:1
1:1
1:1
+3V_LAN
R339 300_0603_5%
1 2
R341 300_0603_5%
1 2
MX4-
MX4+
MCT4
MX3-
MX3+
MCT3
MX2-
MX2+
MCT2
MX1-
MX1+
MCT1
+3V_LAN
13
14
15
16
17
18
19
20
21
22
23
24
MDO3-
MDO3+
MDO1-
MDO2-
MDO2+
MDO1+
MDO0-
MDO0+
MDO0+
MDO0-
MCT0
MDO1+
MDO1-
MCT1
MDO2+
MDO2-
MCT2
MDO3+
MDO3-
MCT3TRM_CT
11
12
10
JP7
Yellow LED+
Yellow LED-
8
PR4-
7
6
5
4
3
2
1
9
DETECT PIN1
PR4+
PR2-
PR3-
PR3+
PR2+
PR1-
PR1+
Green LED +
Green LED -
SANTA_130452-3_13P-T
CONN@
C307 0.01U_0402_50V7K
C308 0.01U_0402_50V7K
C309 0.01U_0402_50V7K
C310 0.01U_0402_50V7K
15
SHLD1
13
14
SHLD1
1 2
1 2
1 2
1 2
01/13
Update JP7 footprint
R89 0_0402_5%
1 2
R319
75_0402_1%
R323
75_0402_1%
R329
75_0402_1%
R330
75_0402_1%
CB_IN
12
12
12
C306 1000P_1808_3KV7K
12
1 2
CB_ IN <21>
12/29 HP review
Del Q23 Q24
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
3
2006/02/13 2006/07/26
Compal Secret Data
Deciphered Date
Title
Size Docu ment Number Re v
2
Date: Sheet
Compal Electronics, Inc.
Magnetic & RJ45
LA-5221P
1
0.1
of
24 45Tuesday, February 03, 2009
Page 25
A
B
C
D
E
1
1
2
2
C318
C319
0.1U_0402_16V4Z
12/17 HP review
Del net and TP
+1.5VS
Delete R407, R409, R522, R528, R529, & R530 of LPC for
1
2
C320
4.7U_0805_10V4Z
layout improve. 2/21
WWLAN/WiMax Mini-Express Card
Del R345 & improve
+3V_WLAN. 12/11
2/21
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
XMIT_D_OFF#
PLT_RST#
WL_LED#
XMIT_D_OFF#
Add to prevent leakage issue.
PLT_RST# <8, 19,23,31>
12/29 HP review
Del Pin30 ICH_SMB_CLK
Del Pin32 ICH_SMB_DATA
WL_LED# <18>
2 1
D13 CH751H-40_SC76
PCI_RST#
PCIE_C_RXN2
PCIE_C_RXP2
+3VS
half size
JP13
1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
GND1
GND2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
FOX_AS0B226-S40N-7F
CONN@
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
LPC_FRAME# <20,31,32>
LPC_AD3 <20,31,32>
LPC_AD2 <20,31,32>
LPC_AD1 <20,31,32>
LPC_AD0 <20,31,32>
+3VS
12/17 HP review
+3V_WLAN-->+3VS
XMIT_OFF# <21>
+1.5VS
+3VS
1
2
C316
0.1U_0402_16V4Z
4.7U_0805_10V4Z
12/17 HP review
Del PCI_W AKE#
2/21
1
2
C317
0.01U_0402_16V7K
CLKREQ_W LAN#<15>
CLK_PCIE_MCARD#<15>
CLK_PCIE_MCARD<15>
PCI_RST#<19,32>
CLK_PCI_DEBUG<15>
R346 0_0402_5%
1 2
R347 0_0402_5%
1 2
12/17 HP review
+3V_WLAN-->+3VS
1
2
C315
1 1
2 2
0.01U_0402_16V7K
PCIE_RXN2<21>
PCIE_RXP2<21>
PCIE_TXN2<21>
PCIE_TXP2<21>
12/17 HP review
Remove reserved part(No mini card contol pin)
+3VS
Close to JP14
12/20 HP review
Del PLT_RST#
USB20_N7 <21>
USB20_P7 <21>
WW_LED# <18>
UIM_DATA
Note2
1
1
1
2
2
2
C591
39P_0402_50V8J
C590
39P_0402_50V8J
@
B
C592
39P_0402_50V8J
@
@
S DIO(BR ) NUP4301MR6T1 TSOP-6@
JP15
4
GND
5
VPP
6
I/O
7
DET
R367
47K_0402_5%
@
1 2
Note1
Change Power rail same
as pin2, 52. 8/16
Note2
Reserve for 800 & 900MHz
EMI issue. 8/16
TAITW_PMPAT6-06GLBS7N14N0CONN@
UIM_PWR
U13
1
2
CH1
CH4
Vn
CH23CH3
Vp
0.01U_0402_16V7K
6
5
4
VCC
RST
CLK
GND
GND
Add in 9/27
0LQL([SUHVV&DUG::$1
DEL in 9/26
A
JP14
1
1
3
3
5
5
7
7
9
9
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152
GND153GND2
MOLEX_67910-5700CONN@
2
2
4
4
6
6
8
8
10
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
WXMIT_OFF#<21>
Full size
3 3
T78 PAD
T79 PAD
12/20 HP review
Use +3VS power
+3VS
R359 0_0603_5%
1 2
1 2
R360 0_0603_5%
delete R362~R364,
not support Clink
on 2008 products to
WWAN slot 5/22
4 4
12/20 HP review
Remove reserved part(No mini card contol pin)
T80 PAD
Del R354 &
+3VS
improve
+3V_WWAN.
12/11
UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP
M_WXMIT_OFF#
12/29 HP review
Del Pin3 0 ICH_SMB_ CLK
Del Pin32 ICH_SMB_DATA
WW_LED#
WL_LED#
Add back 9/27
D16
CH751H-40_SC76
21
+3VS
M_WXMIT_OFF#
Change value
to 47K. 9/27
+3VS
ACCELEROMETER
1
2
C333
1
1
2
2
C335
C334
4.7U_0805_10V4Z
0.1U_0402_16V4Z
+3VS
D15
DAN217T146_SC59-3@
UIM_PWR
1
UIM_RSTUIM_VPP
2
UIM_CLK
3
1
C336
2
8
9
1
18P_0402_50V8J
2
@
C342
4.7U_0805_10V4Z
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
C
+3VS
3
1
2
1
2
C343
0.1U_0402_16V4Z
2005/05/26 2006/07/26
Compal Secret Data
12/20 HP review
Use +3VS pwoer rail
+3VS
+3VS
Deciphered Date
ACCEL_INT#<19>
ICH_SM_DA<4,14,15,21>
ICH_SM_CLK<4,14,15,21>
R365 10K_0402_5%
12
L
Change U12 part description from
LIS302DLTR LGA to HP302DLTR8 as HP
change list. 12/03
D
12/20 HP review
Use +3VS pwoer rail
U12
LIS302DL
1
VDD_IO
6
VDD
8
INT 1
INT 29GND
12
SDO
13
SDA / SDI / SDO
14
SCL / SPC
7
CS
Must be placed in the center of the system.
HP302DLTR8_LGA14_3X5
2
GND
4
GND
5
GND
10
3
RSVD
11
RSVD
Title
WLAN&WWAN Mini-Card/Accelerometer
Size Docu ment Number Re v
Date: Sheet
Compal Electronics, Inc.
LA-5221P
+3VS
+3VS
1
1
C341
C340
2
2
0.1U_0402_16V4Z
10U_0805_6.3V6M
0.1
of
25 45Tuesday, February 03, 2009
E
Page 26
5
4
3
2
1
12/17 Remove to small board
D D
C C
B B
A A
Title
Size Doc ument Nu mber Re v
5
4
3
2
Dat e: Sheet
Card reader board
LA-5221P
1
0.1
of
26 45Tuesday, February 03, 2009
Page 27
A
TPA6044 no longer needed. So delete BOM options & co-layout
components for TPA6044. SGND and SGND1 nets can also be
deleted. Only TPA6041 will be supported. 9/5
B
C
D
AMP. FOR INTERNAL SPEAKER
+5VS
E
11/25
C737 10U_0805_16V6K_X5R
12
C746 1U_0603_16V7_X7R
+VDDA _CODEC
1 1
+3VS_DVDD
R839
4.7K_ 0402_5%
1 2
HDA_RST#_CODEC
1
C711
0.01U_0402_16V7K
2
01/08 HP review
R835
R828
20K_0 402_1%
Q84B
Install R839 and C711
+VDDA_CODE C
12
+VDDA_CODE C
12
12
R826
2.49K_0402_1%
SENSEB
2
C724
1000P_0402_50V7K_X7R
1
12
R827
2.49K_0402_1%
SENSEA
2
C725
1000P_0402_50V7K_X7R
1
01/08 Confirm Audio jack norm al open or normal close
2 2
HP_DET<28>
3 3
4 4
+VDDA _CODEC
R823
100K_0402_5%
1 2
HP_DET
+VDDA_CODE C
R824
100K_0402_5%
2
1 2
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
61
5
39.2K _0402_1%
Q84A
3
4
SB_SPKR< 21>
+3VS
BLM18BD601SN1D_0603
33P_0 402_50V8K
HDA_BITCLK_CODEC<20>
HDA_ SDIN0<20>
HDA_S DOUT_CODEC<20>
HDA_SYNC_CODEC<20>
HDA_RST#_CODEC<20>
A_SD
A_SD<32>
EAPD<32>
R816
10K_0 402_5%
2
G
40mils
R845
C754
@
12
+VDDA _CODEC
A_SD#
2
G
12
@
47_0402_5%
12
CH751H-40PT_SOD323-2
13
D
S
12
C710
0.1U_0402_16V4Z
13
D
Q33
2N7002_SOT23
S
+3VS_DVDD +VDDA _CODEC
R840
R834
R825 15K_0 402_1%
R817
10K_0 402_5%
Q11
2N7002_SOT23-3
1 2
C715
0.1U_0402_16V7K
1
2
12
33_0402_5%
1 2
R810
100K_0402_5%
1 2
R818
10K_0 402_5%
C741
C736
C716
10U_0805_16V6K_X5R
0.1U_0402_16V7K
1
1
1
2
2
2
HDA_SDIN0_CODEC
HDA _SDOUT_CODEC
HDA_SYNC_CODEC
HDA_RST#_CODEC
12
21
D4
1 2
C709 0.1U_0402_16V4Z
12
2
C742
0.01U_0402_16V7K
1
10U_0805_16V6K_X5R
U49
1
DVDD_LV
6
DVDD_CORE
3
HDA_BITCLK
5
HDA_SDI
2
HDA_SDO
7
HDA_SYNC
8
HDA_RST#
30
DMIC_CLK
29
DMIC0/GPIO1
32
SPDIF_OUT_0
28
SPDIF_OUT_1/GPIO7
31
EAPD/GPIO0/SPDIF_OUT 0 or 1
4
DVSS
92HD75B2X5NLGXYBX8_QFN32_5X5
MON O_IN_HD
AVDD
SENSE_A
SENSE_B
PORT_A_L
PORT_A_R
PORT_B_L
PORT_B_R
VREFOUT_B
PORT_C_L
PORT_C_R
VREFOUT_C
PORT_D_L
PORT_D_R
PORT_E_L
PORT_E_R
PC_BEEP/MONO
CAP2
VREFFILT
AVSS
TPAD
LINE_OUTR
LINE_OUTL
C714
C743
0.1U_0402_16V7K
1U_0603_10V6K
2
1
1
2
17
SENSEA
10
SENSEB
23
26
27
MIC1_C
13
MIC2_C
14
+MIC_BIAS_B
20
MIC_INT_L_R
15
MIC_INT_R_R
16
+MIC_BIAS_C
21
LINE_OUTL
24
LINE_OUTR
25
11
12
MON O_IN_HD
9
22
19
C735
18
33
1
2
audio ground must be connect to
digital ground with an 80mil copper
bridge located directly under codec
to prevent ESD latch up.
HP_IN_LHDA_BITCLK_CODEC
HP_IN_R
C751 1U_0603_16V7_X7R
12
C756 1U_0603_16V7_X7R
12
C745 1U_0603_16V7_X7R
12
C747 1U_0603_16V7_X7R
12
C744
10U_0805_16V6K_X5R
1U_0603_10V6K
2
1
+MIC_BIAS_B <28>
+MIC_BIAS_C <28>
12
C748 1U_0603_16V7_X7R
12
C738 10U_0805_16V6K_X5R
12
A_SD#
LINE_C_OUTL
1 2
C705 0.022U_0603_25V4Z_X7R
1 2
C703 0.022U_0603_25V4Z_X7R
C706 0.022U_0603_25V4Z_X7R
C704 0.022U_0603_25V4Z_X7R
C750 1U_0603_16V7_X7R
1 2
1 2
LINE_C_OUT R
12
Place close to U49
02/02 HP review
Follow swatch
MIC1 <28>
MIC_I NT_L <28>MIC_SENSE<28>
MIC_I NT_R < 28>
C718 0.1U_ 0805_25V7M
C717 0.1U_ 0805_25V7M
C720 0.1U_ 0805_25V7M
C719 0.1U_ 0805_25V7M
R805 0_1206_5%
U14
9
CPVDD
17
HPVDD
8
SPVDD
18
SPVDD
30
VDD
23
SPKR_EN
2
SPKR_RIN+
1
SPKR_RIN-
3
SPKR_LIN+
4
SPKR_LIN-
14
HPVSS
13
CPVSS
28
SGND
11
CPGND
21
SPGND
5
SPGND
33
TML
TPA6047A4RHBR_QFN32_5X5
Jack MIC
Internal MIC
12
12
12
12
12
GNDAGND
REG_EN
REG_OUT
HP_EN
HP_INL
HP_INR
HP_OUTL
HP_OUTR
ROUT+
ROUT-
LOUT+
LOUT-
C1P
C1N
BYPASS
GAIN0
GAIN1
12/29 ESD request
SLP_S3#
25
29
HP_DET
22
C753 2.2U_0603_10V6K_X5R
27
1 2
C752 2.2U_0603_10V6K_X5R
26
1 2
16
15
SPKR_R+
20
SPKR_R-
19
SPKR_L+
6
SPKR_L-
7
C749 1U_0603_16V7_X7R
10
12
C723 0.47U_0603_16V7K_X7R
1 2
24
GAIN0
31
GAIN1
32
SLP_S3# <21,23,32,33,34,37,38,40,41,43>
+VDDA_CODE C
40mils
Internal SPKR.
12
HP_OUTL <28>
HP_ OUTR <28>
GAIN0 GAIN1 Av(inv)
0
0 1 10dB
1
1
D18
PJSO T05C_SOT23
SPKR_L+
SPKR_LSPKR_R+
SPKR_R-EAPD
C780
220P_0402_50V7K
220P_0402_50V7K
0 6dB
0
1
1
2
3
1
1
C781
220P_0402_50V7K
2
2
C782
2
1
2
HP_IN_L
HP_IN_R
R802
100K_0402_5%
R808
0_0201_5%
@
1
D17
PJSO T05C_SOT23
3
1
C783
220P_0402_50V7K
2
HP Jack
1 2
12
15.6dB
21.6dB
1
2
3
4
5
6
+5VS
R803
100K_0402_5%
@
1 2
12
R806
0_0201_5%
JP18
1
2
3
4
GND1
GND2
E&T_3806-F04N-02R
CONN@
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRO NICS, INC. NEIT HER THIS SHEE T NOR THE INFO RMATION IT CO NTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF C OMPAL ELECT RONICS, INC.
C
2007/05/29 2008/05/29
Compal Secret Data
Deciphered Date
D
Title
Size Docum ent Number Rev
Date: Sheet
Compal Electronics, Inc.
IDT CODEC 92HD75B2
LA-5221P
E
of
27 4 5Tuesday, February 03, 2009
0.1
Page 28
A
01/10 Fine tune pin def ine Use the same conn JP9
B
C
D
E
3
1
R903
100K_0402_5%
1 2
560K_0402_5%
EXT_MIC
R904
+VDDA_CODEC
1 2
1
3
R905
120K_0402_5%
1 2
5
U51
P
IN+
4
O
IN-
G
2
LMV331IDCKRG4_SC70-5~D
MIC_SENSE <27>
+5VALW +5VALW
1 1
USB20_N1<21>
USB20_P1<21>
USB20_N4<21>
USB20_P4<21>
SLP<30,34>
USB20_N1
USB20_P1
USB20_N4
USB20_P4
SLP
EXT_MIC
INT_MIC_1_2
INT_MIC_2_2
02/02 Update EXT Mic detect circuit
USB I/O connx2 , Aduio JACK
Card reader transfer conn
2 2
L14
EXT_MIC EXT_MIC_1
3 3
12
C722 0.47U_0402_6.3V6K_X5R
HLC0603CSCCR10JT_0603
1 2
1
C759
68P_0402_50V8J
2
JP9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
26
28
30
CONN@
HP_DET
HP_OUTR
HP_OUTL
25
27
29
31 32
ACES_88242-3001_30P
1 2
R820 10K_0402_5%
USB20_N5
USB20_P5
48MHZ_Clock
EXT_MICL_3
R814 100K_0402_5%
+CODEC_REF
+VDDA_CODEC
1
C731
2
3
2
100P_0402_50V8J
USB20_N5 <21>
USB20_P5 <21>
48MHZ_Clock <15>
HP_DET <27>
HP_OUTR <27>
HP_OUTL <27>
@
1 2
C726 33P_0402_50V8K
1 2
4
P
+
1
OUT
-
G
U18A
TLV2464_TSSOP14
11
MIC_EXT_L
+5VALW+5VALW
+3VS
MIC1 <27>
+MIC_BIAS_ B<27>
12/26 R eserved for card reader
2.2K_0402_5%
1
C973
Place close to U18
+VDDA_CODEC
R841
10K_0402_5%
R842
10K_0402_5%
1U_0603_16V6K
+CODEC_REF
1 2
2
1
C7554.7U _0805_10V4Z
C7840.1U _0402_16V4Z
1
2
1 2
2
220P_0402_25V8J
C974
DAN202U_SC70
AMP. FOR EXTERNAL MICROPHONE
5
6
R902
+
-
D56
1
2
12
2
4
P
7
OUT
G
U18B
TLV2464_TSSOP14
11
@
1 2
+MIC_BIAS_C<27>
INT_MIC_1_4
R837
R838
3K_0402_5%
INT_MIC_2_2
INT_MIC_1_2
+VDDA_CODEC
4 4
R906
3K_0402_5%
@
12
1
2
A
R907
3K_0402_5%
@
C975
1U_0603_16V7_X7R
3K_0402_5%
1 2
1 2
L16
HLC0603CSCCR10JT_0603
INT_MIC_1_3
12
1 2
C708 0.068U_0603_16V7K
1 2
1 2
10K_0402_5%
1
C761
68P_0402_50V8J
2
R819
+CODEC_REF
1
C727
2
B
100P_0402_50V8J
@
1 2
C734 100P_0402_50V8J
1 2
R813 100K_0402_5%
+VDDA_CODEC
1
C713
4
2
+
OUT
-
11
0.1U_0402_16V4Z
P
8
G
U18C
TLV2464_TSSOP14
MIC_INT_L<27>
10
9
AMP. FOR INTERNAL MICROPHONE
+VDDA_CODEC
3K_0402_5%
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
C
INT_MIC_2_2
R908
@
2007/05/29 2008/05/29
12
1
2
R909
12
3K_0402_5%
@
C976
1U_0603_16V7_X7R
Compal Secret Data
Deciphered Date
1 2
C707 0.068U_0603_16V7K
INT_MIC_2_3
L15
HLC0603CSCCR10JT_0603
1 2
D
R821
10K_0402_5%
1 2
1
C760
68P_0402_50V8J
2
INT_MIC_2_4
Title
Size Docu ment Number Re v
Date: Sheet
C732 100P_0402_50V8J
1 2
R812 100K_0402_5%
+CODEC_REF
+VDDA_CODEC
1
C730
2
100P_0402_50V8J
12
13
+
-
1
C712
4
2
P
14
OUT
TLV2464_TSSOP14
G
U18D
11
0.1U_0402_16V4Z
MIC_INT_R<27>
Compal Electronics, Inc.
AMP & Audio Jack
LA-5221P
E
0.1
of
28 45Tuesday, February 03, 2009
Page 29
INT_KBD CONN.
01/09 Co layout for DB phase
KSO11
KSO0
KSO2
KSO5
KSI_D_14
KSI_D_8
KSI_D_12
KSI_D_10
KSI_D_0
KSI_D_4
KSI_D_2
KSI_D_1
KSI_D_3
KSO3
KSO8
KSO4
KSO7
KSO6
KSO10
KSO1
KSI_D_5
KSI_D_6
KSI7
KSI_D_13
KSI_D_11
KSI_D_9
KSO9
JP35
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
GND1
GND3
62
GND2
GND4
HIROSE FH12HP- 30S-1SV 55 30PCONN@
KSO11
2
2
KSO0
4
4
KSO2
6
6
KSO5
8
8
KSI_D_14
10
10
KSI_D_8
12
12
KSI_D_12
14
14
KSI_D_10
16
16
KSI_D_0
18
18
KSI_D_4
20
20
KSI_D_2
22
22
KSI_D_1
24
24
KSI_D_3
26
26
KSO3
28
28
KSO8
30
30
KSO4
32
32
KSO7
34
34
KSO6
36
36
KSO10
38
38
KSO1
KSI_D_5
KSI_D_6
KSI7
KSI_D_13
KSI_D_11
KSI_D_9
KSO9
0.1U_0402_16V4Z
20mil
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
60
63
64
+3VS
1
2
+3VS
12/31 KB LED power
Dior KB up contact
Pin 1 Pin 1
Pin1 reserve , so net name is reserve
for Fossil down contact
DB use
C962
R893
0_0603_5%
12
KSO11
KSO0
KSO2
KSO5
KSI_D_14
KSI_D_8
KSI_D_12
KSI_D_10
KSI_D_0
KSI_D_4
KSI_D_2
KSI_D_1
KSI_D_3
KSO3
KSO8
KSO4
KSO7
KSO6
KSO10
KSO1
KSI_D_5
KSI_D_6
KSI7
KSI_D_13
KSI_D_11
KSI_D_9
KSO9
JP22
34
GND2
33
GND1
32
32
31
31
30
30
29
29
28
28
27
27
26
26
25
25
24
24
23
23
22
22
21
21
20
20
19
19
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
HRS_F H28-60(30)SB-1SH(86)
CONN@
KSO[0..11]<32>
KSI[0..7 ]<32>
KSO9
KSI_D_9
KSI_D_11
KSO1
KSO10
KSO6
KSO7
KSI_D_1 KSI_D_10
KSI_D_2
KSI_D_4 KSI_D_8
KSI_D_0
KSI0
1
KSI1
1
KSI2
1
KSO[0..11]
KSI[0 ..7]
CP1
2
3
4 5
100P_1206_8P4C_50V8K
CP3
2
3
4 5
100P_1206_8P4C_50V8K
CP5
2
3
4 5
100P_1206_8P4C_50V8K
D21
KSI_D_0
2
KSI_D_8
3
DAP202U_SOT323-3
D23
KSI_D_1
2
KSI_D_9
3
DAP202U_SOT323-3
D25
KSI_D_2
2
KSI_D_10
3
DAP202U_SOT323-3
81
7
6
81
7
6
81
7
6
KSI3
1
KSI4
1
KSI5
1
KSI6
1
KSI_D_13
KSI7
2
KSI_D_6
3
KSI_D_5
4 5
100P_1206_8P4C_50V8K
KSO4
KSO8
2
KSO3
3
KSI_D_3
4 5
100P_1206_8P4C_50V8K
KSI_D_12
2
3
KSI_D_14
4 5
100P_1206_8P4C_50V8K
KSO5
KSO2
2
KSO0
3
KSO11
4 5
100P_1206_8P4C_50V8K
D20
KSI_D_3
2
KSI_D_11
3
DAP202U_SOT323-3
D22
KSI_D_4
2
KSI_D_12
3
DAP202U_SOT323-3
D24
KSI_D_5
2
KSI_D_13
3
DAP202U_SOT323-3
D26
KSI_D_6
2
KSI_D_14
3
DAP202U_SOT323-3
CP2
CP4
CP6
CP7
81
7
6
81
7
6
81
7
6
81
7
6
Power BTN/LED and Lid switch BD
JP8
GND
GND
ACES_85201-06051
1
2
3
4
5
6
CONN@
1
2
3
LID_SW#
4
STB_LED
5
6
7
8
AMBER_BATLED# <32>
GREEN_BATLED# <32>
LID_SW # <17,21,32>
STB_LED <31,32>
12/29 HP review
Lid swit ch power(+3VS-->+3VALW)
PS:GND use DC in jack GND
+3VALW
+3VL
12
R472
100K_0402_5%
1
C463
1U_0603_10V4Z
2
ON/OFFBTN_KBC#
ON/OFFBTN_KBC# <32>
1 2
R474 100K_0402_5%
D28
21
CH751H-40_SC76
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
ON/OFFBTN# <21>
2005/03/10 2006/03/10
12/20 HP review
Modify ON/OFFBTN# circuit
+3VALW
Compal Secret Data
Deciphered Date
T/P BOARD.
+5VS
TP_CLK<32>
TP_DATA<32>
3
Title
Size Docu ment Number Re v
LA-5221P
Date: Sheet
JP28
1
2
3
4
5
6
CONN@
2
D39
PACDN042Y3R_SOT23-3
12/29 ESD request
1
ACES_87151-04051_4P
Compal Electronics, Inc.
MDC/KBD/ON_OFF/LID
+5VS
1
C461
0.1U_0402_16V4Z
2
0.1
of
29 45Tuesday, February 03, 2009
Page 30
5
4
3
2
1
D55
+3VAUX_BT
USB20_N6_R
D D
C C
4
VIN
3
IO2
CM1293A-02SR_SOT143-4
@
GND
USB20_P6_R
2
IO1
1
BT_OFF<21>
BT(SoftBreeze) Connector
JP29
1
2
USB20_P6_R
3
USB20_N6_R
4
5
6
7
8
ACES_87213-0800G_8PCONN@
12
R480
10K_0402_5%
R475 0_0402_5%
R477 0_0402_5%
R705
1 2
220K_0402_1%
12
12
Q39
SI2301BDS_SOT23
S
D
13
G
2
+3VAUX_BT
+3VAUX_BT+3VALW
C4710.1U_0402_16V4Z
1
2
USB20_P6 <21>
USB20_N6 <21>
BT_LED <18>
C47210U_0805_10V4Z
1
2
12/16 change to small board
2A normal with 3.5A Max(1ms)
+5VALW
01/15 Del R356 R887
B B
A A
5
12/16 HP review
S4_STATE#-->SLP
SLP<28,34>
R628 10K_0402_5%
1 2
4
4A
U23
1
GND
2
SLP_R
IN
3
EN1#
4
EN2#
G546A1P1UF_SO8
01/08 Update USB power and footprint
USB_VCCC
8
OC1#
7
OUT1
6
OUT2
5
OC2#
USB20_N0<21>
USB20_P0<21>
12/16
USB port 0 for debug on M/B
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
3
2006/02/13 2006/07/26
12/29 Use B2 size
USB20_N0
USB20_P0
Compal Secret Data
1
+
C480
2
Deciphered Date
USB CONNECTOR 3
160mils
1
1
C481
C482
2
2
0.1U_0402_16V4Z
150U_B2_6.3VM_R45M
1000P_0402_50V7K
2
01/15 Pin7 and Pin8 contact to GND
JP32
1
1
2
2
3
3
4
4
5
GND
6
GND
7
GND
8
GND
SUYIN_020173MR004S558ZL
USB_VCCC
D31
4
IO1
12/29 ESD request
LA-5221P
VIN
3
GND
IO2
CM1293A-02SR_SOT143-4
@
1
USB20_N0
Title
Size Docu ment Number Re v
Date: Sheet
Compal Electronics, Inc.
USB & BT Connector
USB20_P0
2
1
of
30 45Tuesday, February 03, 2009
0.1
Page 31
5
D D
C C
4
3
2
1
01/23
U25 is conn
&U1 is SPI ROM
B B
A A
BIOS ROM
C496
0.1U_0402_16V4Z
R501 3.3K_0402_5%
1 2
1 2
1 2
1 2
5
1 2
SPI_CS0#<32>
SPI_CLK<32>
12
SPI_SI<32>
+3VL
20mils
SPI_CLK_JP34 SPI_CLK_JP34
SPI_SI_JP34
R503 0_0402_5%
R504 0_0402_5%
R507 0_0402_5%
R846 0_0402_5%
R632 0_0402_5%
+3VL
20mils
1
2
SPI_WP#
SPI_HOLD#_0
SPI_CS0#
SPI_CLK
SPI_SI SPI_SO_R
SPI_CS0#SP I_CS0#_JP34
SPI_CLK
SPI_SO_RSPI_SO_JP34
SPI_HOLD#_0SPI_H OLD#_0_JP34
8
3
7
1
6
5
+3VL
12
R899
4.7_0402_5%
@
1
C969
680P_0402_50V7K
2
@
01/13
Reserved for ESD
U25
VCC
W
HOLD
S
C
D
WIESO_G6179-100000_8P
CONN@
4
VSS
2
Q
20mils
R505 3.3K_0402_5%
4
1 2
12/26
SPI use MXIT 2MB size
&U1
45@
MX25L1605AM2C-12G_SO8-200mil
R502 15_0402_5%
1 2
SPI_WP#
R506 0_0402_5%@
SPI_SO <32>
1 2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
3
2005/03/10 2006/03/10
Add SIRQ and connect to
pin5. 10/08
8051_RECOVER#
Compal Secret Data
Deciphered Date
+3VL
12
R500
100K_0402_5%
CLK_PCI_DB<15>
LPC_FRAME#<20,25,32>
SIRQ<21,32>
PLT_RST#<8 ,19,23,25>
LPC_AD0<20,25,32>
LPC_AD1<20,25,32>
LPC_AD2<20,25,32>
LPC_AD3<20,25,32>
8051TX<29,32>
8051RX<32>
8051_RECOVER#<32>
VCC1_PWRGD<32,33>
Modify in 2/23.
KBC_SPI_CS1#_R_JP34<32>
8051_RECOVER#
SPI_CS0#_JP34
SPI_SI_JP34SPI_SI
SPI_SO_JP34
SPI_HO LD#_0_JP34
Pin3, 23 tie to GND. 10/10
2
LPC Debug Port
B+
JP34
1
Ground
2
LPC_PCI_CLK
3
Ground
4
SIRQ
Title
Size Docu ment Number Re v
Date: Sheet
LPC_FRAME#
5
+V3S
6
LPC_RESET#
7
+V3S
8
LPC_AD0
9
LPC_AD1
10
LPC_AD2
11
LPC_AD3
12
VCC_3VA
13
PWR_LED#
14
CAPS_LED#
15
NUM_LED#
16
VCC1_PWRGD
17
SPI_CLK
18
SPI_CS#
19
SPI_SI
20
SPI_SO
21
SPI_HOLD#
22
Reserved
23
Reserved
24
Reserved
ACES_87216-2404_24P
CONN@
Compal Electronics, Inc.
TCG/BIOS ROM/PS2/SW LPC DEBUG
LA-5221P
1
0.1
of
31 45Tuesday, February 03, 2009
Page 32
C972
0.1U_0402_16V4Z
+3VL
R861 10K_0201_5%
1 2
R862 10K_0201_5%
1 2
R863 10K_0201_5%
1 2
R864 10K_0201_5%
1 2
R865 10K_0201_5%
1 2
R866 10K_0201_5%
1 2
R867 10K_0201_5%
1 2
R868 10K_0201_5%
1 2
+5VS
R869 10K_0201_5%
1 2
R870 10K_0201_5%
1 2
R871 10K_0201_5%
1 2
R872 10K_0201_5%
1 2
+3VL
R521
1 2
+3VL
10K_0201_5%
R524
1 2
10K_0201_5%
+3VS
12/20 HP review
Add ADP_PS1 and ADP_ID
R533
1 2
+5VS
10K_0201_5%
01/15 BIOS review
R900 10K_0201_5%
1 2
R901 10K_0201_5%
1 2
32.768KHZ_12.5PF_9H03200413
Y5
1
OSC4OSC
1
NC3NC
2
2
C506 33P_0402_50V8J
01/19 SMSC review
22P-->33 P
01/15 HP review
Every +3VL share 0.1u cap for U26
1
0.1U_0402_16V4Z
2
ADP_PS1
ADP_ID
RUNSCI_EC#
01/19 SMSC review
Pin 68 +3VL--->+RTCVCC
12/20 HP review
+VCC0- ->+3VL and Del GPIO40
12/20 HP review
Del GPIO39(WWLAN power control)
Del GPIO38(WLAN power control)
1
Del GPIO37( LAN_WOL_EN to ICH)
2
C507 33P_0402_50V8J
12/20 HP review
+VCC0-->+3VL
1
C971
2
KSI0
KSI3
KSI2
KSI1
KSI7
KSI6
KSI5
KSI4
TP_CLK
TP_DATA
PS2_CLK
PS2_DATA
01/05 HP review
+3VS-->+3VL
SP_CLK
SP_DATA
0.1U_0402_16V4Z
KBC_SPI_CLK_R<21>
01/15 HP review
C339-->@
1
C499
2
KBC_SPI_SI_R<21>
SPI_CS0#<31>
KBC_SPI_CS0#_R<21>
KBC_SPI_SO<21>
KSO[0..11]<29>
KSI[0..7 ]<29>
TP_CLK<29>
TP_DATA<29>
01/15 BIOS review
PM_CLKRUN#<21>
SIRQ<21,31>
CLK_PCI_EC<15>
RUNSCI_EC#<21>
LPC_AD3<20,25,31>
LPC_AD2<20,25,31>
LPC_AD1<20,25,31>
LPC_AD0<20,25,31>
LPC_FRAME#<20,25,31>
PCI_RST#<19,25>
12/20 HP review
Add ADP_PS1
+3VL
SPI_CLK<31>
1
C500
0.1U_0402_16V4Z
SPI_SI<31>
SPI_SO<31>
@
2
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
TP_CLK
TP_DATA
SP_CLK
SP_DATA
PS2_CLK
PS2_DATA
CLK_PCI_EC
RUNSCI_EC#
ADP_PS1
CRY1
C970 0.1U_0402_16V4Z
12
KBC_S PI_CS1#_R
2
C339
4.7U_0805_10V6K
1
1
C501
0.1U_0402_16V4Z
U26
128
FLDATAOUT
127
HSTDATAOUT
97
FLCS0#
96
HSTCS0#
95
FLDATAIN
94
HSTDATAIN
21
KSO0
20
KSO1
19
KSO2
18
KSO3
17
KSO4
16
KSO5
13
KSO6
12
KSO7
10
KSO8
9
KSO9
8
KSO10
7
KSO11
6
KSO12/GPIO00/KBRST
5
KSO13/GPIO18
29
KSI0
28
KSI1
27
KSI2
26
KSI3
25
KSI4
24
KSI5
23
KSI6
22
KSI7
35
IMCLK
36
IMDAT
38
KCLK
40
KDAT
41
EMCLK
42
EMDAT
55
CLKRUN#
57
SER_IRQ
54
PCI_CLK
76
EC_SCI#
51
LAD[3]
50
LAD[2]
48
LAD[1]
46
LAD[0]
52
LFRAME#
53
LRESET#
45
LPCPD#/GPIO23
70
XTAL1
71
XTAL2
68
VCC0
1
GPIO40
2
HSTCLK
3
FLCLK
30
GPIO39
31
HSTCS1#
32
FLCS1#
33
GPIO38
34
GPIO37
43
NC
44
NC
2
Modify in 2/23.
C503
12
4.7U_0805_10V4Z
1
C502
0.1U_0402_16V4Z
2
Keyboard/Mouse Interface
Power Mgmt/SIRQ
LPC
Bus
12/20 HP review
Contact DGND
R633 0_0201_5%
+3VL
01/14 HP review
Del R722
1
C498
2
14
106
119
49
VCC1
VCC139VCC158VCC184VCC1
VCC1
VCC2
SMSC_1091-NU_TQFP-128P
Access Bus Interface
24MHZ_OUT/GPIO19/WINDMON
Miscellaneous
AGND
VSS11VSS37VSS47VSS56VSS
1 2
VSS82VSS
104
117
KBC_S PI_CS1#_R
72
01/14 HP review
Del R511
0.1U_0402_16V4Z
CAP
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
OUT0
OUT1/IRQ8#
OUT7/SMI#
OUT8/KBRST
OUT9/PWM 2
OUT10/PWM0
OUT11/PWM1
GPIO01
GPIO02
GPIO03
GPIO04/KSO14
GPIO05/KSO15
GPIO07/PWM 3
GPIO08/RXD
GPIO09/TXD
GPIO11/AB2A_DATA
GPIO12/AB2A_CLK
GPIO13/AB2B_DATA
GPIO14/AB2B_CLK
GPIO15/FAN_TACH1
GPIO16/FAN_TACH2
GPIO17/A20M
GPIO20/PS2CLK
GPIO21/PS2DA T
GPIO24/KSO16
GPIO27
General Purpose I/O Interface
KBC1091-NU_TQFP128_14X14
AB1A_DATA
AB1A_CLK
AB1B_DATA
AB1B_CLK
PGM Strap/GPIO25
EA Strap#/GPIO26/KSO17
CLOCKI
32KHZ_OUT/GP IO22
RESET_OUT#/GPIO06
PWRGD
VCC1_PWRGD
TEST PIN
DMS_LED# /GPIO10
BAT_LED#
PWR_LED#/8051TX
FDD_LED#/8051RX
GPIO33
GPIO34
GPIO35
GPIO36
KBC_SPI_CS1#_R <21>KBC_SPI_CS1#_R_JP34<31>
NC
NC
+3VS
01/15 HP review
C504 Y5V-- >X5R
C504 4.7U_0805_10V6K
15
93
98
99
100
126
124
125
123
122
121
120
118
107
79
80
81
83
85
86
87
88
89
90
91
92
101
102
103
105
4
74
111
112
109
110
73
108
59
75
60
78
77
61
69
116
113
115
114
67
66
65
64
63
62
1 2
R517 0_0201_5%
KBC_PWR_ON
GREEN_BATLED#
KBRST#
THM_TRAVEL#
12/20 HP review
Del LOW_BAT# and TP
PM_RSMRST#
APP_BUTTON_1
APP_BUTTON_2
BATCON
8051_RECOVER#
WL_BLUE_BTN
ADP_PRES
SMB_EC_DA1
SMB_EC_CK1
AB1B_DATA
AB1B_CLK
EA#
CLK_14M_KBC
32K_CLK
PGD_IN
PWR_GD
VCC1_PWRGD
ADP_PS0
TEST
ADP_ID
AMBER_BATL ED#CRY2
1 2
R538 100K_0402_5%
R847 0_0201_5%
1 2
1 2
R730 10K_0201_5%
R279 0_0201_5%
R516 0_0201_5%
R729 10K_0201_5%
R728 10K_0201_5%
R531
R536 1K_0201_5%
KBC_PWR_ON <38>
GREEN_BATLED# <29>
FAN_PWM <4>
BAT_PWM_OUT <37>
CHGCTRL <37>
ON/OFFBTN_KBC# <29>
R604 10K_0201_5%
1 2
1 2
1 2
1 2
BAT_ID# <36>
GATEA20 <20>
8051_RECOVER# <31>
SLP_S3# <21,23,27,33,34,37,38,40,41,43>
WL_BLUE_BTN <18>
ADP_PRES <21,23,37>
SMB_EC_DA1 <36>
SMB_EC_CK1 <36>
1 2
1K_0201_5%
1 2
R545 0_0201_5%
1 2
R543 1.2K_0402_5%
1 2
PWR_GD <33,42>
AMBER_BATLED# <29>
8051RX <31>
12
+3VL
12/20 HP review
Del GPIO28(PM_SLP_M#)
Del GPIO29((SUS_PWR_ACK)
Del GPIO30(AC_PRESENT)
EAPD <27>
PCI_SERR# <19>
12/20 HP review
Del reserved pull high R
12/20 HP review
LAN_DISABLE_N-->FAN_PWM
1 2
+3VL
PM_RSMRST# <2 1>
APP_BUTTON _1 <18>
APP_BUTTON _2 <18>
12/20 HP review
Contact to +3VL
CELLS <37>
A_SD <27>
12/20 HP review
Contact to GND
01/06 HP review
12/20 HP review
Contact to GND
R535 10_0402_5% @
+3VL
12/20 HP review
LANLINK_STATUS by ICH9
LID_SW# <17,21,29>
1 2
PM_PWROK
21
D33
CH751H-40_SC76
01/06 HP review
ADP_PS0
PGD_IN
CLK_14M_KBC <15>
ADP_EN <43>
PM_PWROK <8,21,42>
VCC1_PWRGD <31,33>
STB_LED <29,31>
8051TX <29,31>
WL_BLUE_BTN
APP_BUTTON_1
APP_BUTTON_2
01/06 HP review
Add pull up R
KB_RST# <20>
SMB_EC_CK1
SMB_EC_DA1
AB1B_CLK
12/20 HP review
Contact to +3VL
AB1B_DATA
R723
1 2
10K_0201_5%
R532
1 2
10K_0201_5%
C505 10P_0402_25V8K @
1 2
12/29 HP review
Contact Pin 115
R882 100K_0402_5%
1 2
R883 100K_0402_5%
1 2
R884 100K_0402_5%
1 2
12/20 HP review
Del G_BATLED#
12/29 HP review
R523 @-->2.2k
ADP_PRES
R523 2.2K_0402_5%
THM_TRAVEL#
R320 100K_0402_5%
12/20 HP review
Del reserved pull high R
KBC_PWR_ON
R622
R873 4.7K_0402_5%
R874 4.7K_0402_5%
R875 4.7K_0402_5%
R876 4.7K_0402_5%
+3VL
12/29 HP review
R543 2.2k-->1.2k
12/29 HP review
Del D36
1 2
1 2
1 2
12
12
12
12
+3VL
+3VL
+3VL
10K_0201_5%
12/20 HP review
No AGND filter
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
2006/02/13 2006/07/26
Compal Secret Data
Deciphered Date
Title
Size Docu ment Number Re v
Date: Sheet
Compal Electronics, Inc.
KBC1091
LA-5221P
of
32 45Tuesday, February 03, 2009
0.1
Page 33
1.5VS_PG<40>
+0.9VS
VCCP_PG<40>
DDR2_PG<39>
12/20 HP review
Updat e net mane
R554 3.3K_0402_5%
+5VS
R555 64.9K_0402_1%
D43 CH751H-40_SC76
R478 11.8K_0402_1%
+3VS
2 1
1 2
12
12
1 2
R560 3.3K_0402_5%
1 2
1 2
1 2
30.1K_0402_1%
12/20 HP review
Update R value
12
R561
28K_0402_1%
R564 3.3K_0402_5%
R566 15K_0402_1%
R386 3.3K_0402_5%
12/30 HP review
2VREF_8734-->2VREF_51125
R556 10K_0402_5%
2VREF_51125
12
C526
3300P_0402_50V7K
R567
R558 30.1K_0402_5%
R479 64.9K_0402_1%
SLP_S3# <21,23,27,32,34,37,38,40,41,43>
R565 10K_0402_5%
12
12
C527
0.033U_0402_16V7K
12
12
12
12
2VREF_393
2VREF_393
R551
1M_0402_5%
12
+5VALW
8
U30A
3
P
+
1
O
2
-
G
LM393M_SO8
4
1
C523
1000P_0402_50V7K
2
R562 1M_0402_5%
5
6
+5VALW
8
P
+
-
G
LM393M_SO8
4
U30B
12
7
O
+3VS
12
R553
10K_0402_5%
1 2
J6 SHORT PADS
01/06 HP review
R553 Pin2 contact J6 pin1
12/20 HP review
Contact to J6
PWR_GD <32,42>
WWAN Card STANDOFF CPU support
H6
H1
HOLEA
1
WWLAN Card STANDOFF
H3
HOLEA
H9
HOLEA
H19
HOLEA
H10
HOLEA
H2
HOLEA
1
H4
HOLEA
1
1
1
1
H12
HOLEA
1
1
H11
HOLEA
1
H13
HOLEA
1
H14
HOLEA
1
H15
HOLEA
1
H5
HOLEA
1
H16
HOLEA
1
HOLEA
1
H7
HOLEA
1
H8
HOLEA
1
R591
23.7K_0402_1%
+3VL
1 2
1
C215
0.1U_0402_16V4Z
2
+3VL
5
U37
SN74LVC1G14DCKR_SC70-5
V
2
A
Y
NC
G
1
3
4
12/26
Use SCHMITT-TRIGGER
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
Issued Date
VCC1_ PWRGD <31,32>
2005/05/26 2006/07/26
Compal Secret Data
Deciphered Date
FM1
1
FM3
FM2
1
FM4
1
1
Title
Size Docu ment Number Re v
Date: Sheet
Compal Electronics, Inc.
POK CKT
LA-5221P
0.1
of
33 45Tuesday, February 03, 2009
Page 34
A
B
C
D
E
+1.05VM to +VCCP Transfer
12/12
+1.05VN-->+VCCP
1 1
+3VALW to +3VM_WOL Transfer
12/20
+3VM_WO L-->+3VALW
12/12 REMOVE
+3VALW to +3VM Transfer
+3VALW to +3VS Transfer
2 2
R578
330K_0402_5%
SLP_S3
2
G
B+
12
1
2
12
J7
SHORT PADS
13
D
Q52
RHU002N06_SOT323
S
8
7
6
5
C538
10U_0805_10V4Z
RUNON
U35
SI4800DY_SO8
D
D
D
D
12
R579
470_0402_5%
1
C541
0.01U_0402_25V7K
2
+5VALW to +5VS Transfer
S
S
S
G
RUNON
+5VS+5VALW
1
2
3
4
3 3
1
2
8
7
6
5
C544
10U_0805_10V4M
U36
SI4800DY_SO8
D
D
D
D
+3VS+3VALW
1
S
2
S
3
S
4
G
1
2
C545
0.1U_0402_16V4Z
1
1
2
2
C539
0.1U_0402_16V4Z
1
C546
10U_0805_10V4Z
2
C540
10U_0805_10V4Z
12/20 HP review
01/16 del part
SLP control
SLP<28,30>
SLP
SLP_S4#<21,39>
Q57
RHU002N06_SOT323
2
G
+3VL
12
R583
100K_0402_5%
13
D
S
12/20
+3VM-->+3VALW
SLP_S3
SLP_S3#<21,23,27,32,33,37,38,40,41,43>
Q56
RHU002N06_SOT323
SLP_S3
2
G
+3VL
12
R582
100K_0402_5%
13
D
S
Discharge circuit-1
SLP_S3
+3VS
12
13
2
G
R587
470_0402_5%
D
Q59
S
RHU002N06_SOT323
+0.9VS
12
R586
470_0402_5%
13
2
G
D
Q58
S
RHU002N06_SOT323
A
SLP
4 4
01/16 del part
B
SLP_S3
+5VS
12
R589
470_0402_5%
13
D
2
G
Q61
S
RHU002N06_SOT323
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
C
2006/02/13 2006/07/26
01/16 del part
Compal Secret Data
Deciphered Date
Title
Size Docu ment Number Re v
D
Date: Sheet
Compal Electronics, Inc.
DC/DC Circuits
LA-5221P
E
0.1
of
34 45Tuesday, February 03, 2009
Page 35
5
4
3
2
1
AC
D D
Adapter
in
Page37
VIN
SWITCHADP_EN#
EN0
EN0
LM393
Thermal
Protector
Page39
2VREF_51125
+5VALW
B+
VDD VR_ON
PWR_GD
+3VALWP 3A
B+
TPS51125
DC/DC
(3V/5V)
C C
51125_PWR
Page39
+5VALWP 4.5A
ISL6261ACRZ-T
DC/DC
(CPU_CORE)
Page47
CPU_CORE
(ICCDES=18A)
+1.05VCCP 8A
Page41
BQ24740
Charger
Page41
B+
SLP_S4#
TPS51117
DC/DC
(1.8V)
EN_PSV
Page40
+1.8VP 8A
G2992
Page42
+0.9VP 2A
SLP_S3#
B+
EN1
TPS51117
DC/DC
(1.05V)
B B
TPS51117
Switch
B+
ISL6263
DC/DC
VGA_COREP 5A
B+
SLP_S3#
EN2
EN2
DC/DC
(1.5V)
Page42
+1.5ALWP 4A
(VGA_CORE)
GFXVN_EN
Page45
Battery
A A
Title
POWER BLOCK DIAGRAM
Size Document N umber Rev
Date: Sheet
5
4
3
2
of
35 45Tuesday, February 03, 2009
1
Page 36
A
B
C
D
PCN1
6
1 1
2 2
GND
5
GND
4
4
3
3
2
2
1
1
ACES_87302-0441
1/13 PCN1 ping 5 and 6 should be
connected to GND, and ping 4 is
ideally connect to ADPIN to have
more power delivery.
ADPIN
2
3
@PJSOT24C_SOT23-3
1
PD1
PL1
ADP_SIGNAL <43>
12
12
PC1
100P_0402_50V8J
PC2
SMB302 5500YA_2P
1000P_0402_50V7K
1 2
12
PC3
100P_0402_50V8J
PC4
1000P_0402_50V7K
VIN
12
12
PR1
@15K_0402_5%
PH1 under CPU botten side :
CPU thermal protection at 90 +-3 degree C
Recovery at 47 +-3 degree C
VMB
PCN2
1
1
EC_SMD
2
2
EC_SMC
3
3
4
4
5
5
6
GND
7
GND
SUYIN_200275MR005G187ZR
3 3
12
PC5
@100P_0402_50V8J
12
PR4
1K_0402_1%
1 2
PR6
210K_0402_1%
BAT_ID# <32>
+3VL
12
PC8
12
2007-12-11
PR8
100_0402_5%
12
PC9
@100P_0402_50V8J
@100P_0402_50V8J
12
PR9
100_0402_5%
PL3
HCB201 2KF-121T50_0805
1 2
12
PC6
1000P_0402_50V7K
BATT
12
PC7
0.01U_0402_50V7K
SMB_EC_DA1
SMB_EC_CK1
1
BAV99WT1G_SC70-3
4 4
PD2
2
3
1
PD3
BAV99WT1G_SC70-3
2
3
1
PD4
BAV99WT1G_SC70-3
2
3
+3VL
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS , INC.
B
SMB_EC_DA1 <32>
SMB_EC_CK1 <32>
2005/03/10 2006/03/10
Compal Secret Data
Deciphered Date
C
12/26 HP review
Remove reserved PH1 circuit
Title
Size Doc ument Number R ev
Custom
Dat e: Sheet
Compal Electronics, Inc.
DCIN/BATT/CPU OTP
LA-3261P UMA
D
of
36 45Tuesday, F ebruary 03, 2009
Page 37
A
VIN
PQ100
AO4433_SO8
1
2
3 6
PC100
1 2
PR100
4
13
2
G
12
3
+
2
-
D
PQ104
RHU002N06_SOT323-3
S
PR107
150K_0402_5%
RLS4148_LL34-2
BAT_PWM_OUT<32>
1 2
PR119
255K_0402_1%
VL
12
8
P
1
O
G
PU102A
LM393DG_SO8
4
BATCAL#
P2
12
PR123
75K_0402_1%
12
PR129
10K_0603_0.1%
0.22U_0603_10V7K
200K_0402_5%
1 2
PR105
220K_0402_5%
1 2
1 1
2 2
3 3
2VREF_51125
12/30 HP review
2VREF_8734-->2VREF_51125
PQ101
AO4433_SO8
8
8
7
7
5
5
12
PD100
PC124
0.1U_0402_10V7K
1
2
36
4
1 2
PR102
200K_0402_5%
12
PR103
150K_0402_5%
13
D
2
G
PQ103
S
RHU002N06_SOT323-3
ADP_EN# <43>
1 2
PR111
422K_0402_1%
PC116
1U_0603_6.3V6M
Charge Detector
High 17.588
Low 17.292
AC_AND_CHG
BQ24740VREF
12
PR133
10K_0402_5%
CHGEN#
13
D
2
G
S
ADP_PRES
12
1 2
PR126
11.3K_0402_1%
PQ108
RHU002N06_SOT323-3
+3VL
1 2
PR101
56K_0402_1%
PC107
0.01U_0402_16V7K
SLP_S3#<21,23,27,32,33,34,3 8,40, 41,43>
12
PR110
453K_0402_1%
12
PR112
1M_0402_1%
ACDETACDET
12
PR130
100K_0402_1%
12
PC111
1U_0603_6.3V6M
1 2
22.6K_0402_1%
IADAPT
PR108
0_0402_5%
1 2
BQ24740VREF
+3VL
PR113
100P_0402_50V8J
P2
12
PR124
57.6K_0402_1%
1 2
12
PR127
4.32K_0402_1%
PR131
10K_0603_0.1%
B
ACDET
6
7
LPREF
IADSLP
AGND
VREF
VDAC
VADJ
EXTPWR
ISYNSET
ACSET
PU100
BQ24740RHDR_QFN28_5X5
IADAPT
SRSET
15
16
12
12
PR118
147K_0402_1%
8
9
10
11
12
13
14
12
IADAPT
PC119
5
ACDET
BAT
17
BATT
1U_0603_6.3V6M
12
PC108
0.1U_0603_50V7K
4
LPMD
SRN
18
B+
1 2
PC101
12
3
2
ACP
ACN
SRP
CELLS
19
20
PR117 210K_0402_1%
12
PC122
1U_0603_6.3V6M
PL100
HCB2012KF-121T50_0805
1 2
ACNACP
PC106
@0.1U_0603_25V7K
CHGEN#
1
29
TP
CHGEN
28
PVCC
27
BTST
26
HIDRV
25
PH
24
REGN
23
LODRV
22
PGND
DPMDET
21
SRSET <43>
12
CHGCTRL <32>
BST_CHG
DH_CHG
LX_CHG
REGNVADJ
DL_CHG
AC Detector
High 13.774
+3VL
1 2
PR121
681K_0402_1%
8
5
P
+
6
-
G
4
2VREF_51125
7
O
PU102B
LM393DG_SO8
Low 13.357
12
PR125
22K_0402_5%
ADP_PRES <21,23,32>
12/30 HP review
2VREF_8734-->2VREF_51125
C
12
PC102
4.7U_0805_25V6-K
PC109
1U_0805_25V6K
1 2
1 2
PR137
0_0402_5%
1 2
PR138
0_0402_5%
12
PD101
RLS4148_LL34-2
PC118
12
1U_0603_10V6K
CHGCTRL
1 2
PC125
1000P_0402_50V7K
12
12
PC103
4.7U_0805_25V6-K
PR106
10_0805_1%
1 2
PC110
0.1U_0402_10V7K
1 2
PR114
100K_0402_5%
1 2
PC120
0.1U_0603_50V7K
1 2
PR128
1K_0402_5%
CHG_B+
1
+
PC105
47U_25V_M
2
PC104
4.7U_0805_25V6-K
CHG_B+
578
578
PQ106
AO4468_SO8
CELLS <32>
12
PC123
0.047U_0402_16V7K
Note: X7R type
12
PR132
B+P2
1
2
3 6
PQ105
AO4466_SO8
3 6
241
PR139
@4.7_1206_5%
3 6
241
1/12 Update
for EMI&ESD.
ACPACN
12
PC121
@0.1U_0603_25V7K
470K_0402_5%
2007/9/27
+3VL
12
PR120
1 2
13
D
2
G
S
12
PD102
1SS355_SOD323-2
PQ102
AO4433_SO8
10U_LF919AS-100M-P3_4.5A_20%
12
12
PR115
0_0402_5%
1 2
1 2
PR116 0_0402_5%
+3VL
470K_0402_5%
PQ107
RHU002N06_SOT323-3
8
7
5
4
PR104
0_0402_5%
1 2
P2
PL101
1 2
12
PC126
@680P_0603_50V8J
1
5
P
NC
4
A2Y
G
PU101
3
74LVC1G14GW_SOT353-5
PC112
CHG
D
12
PC113
4.7U_0805_25V6-K
4.7U_0805_25V6-K
PR122
10K_0402_5%
1 2
PR109
0.01_1206_1%
1 2
1 2
PC117
0.1U_0402_10V7K
BATT
12
12
PC114
4.7U_0805_25V6-K
AC_AND_CHG
PC115
4.7U_0805_25V6-K
4 4
12/30 HP review
Del this circ uit
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS , INC.
B
2007/05/29 2008/05/29
Compal Secret Data
Deciphered Date
C
Title
Size Doc ument Number R ev
Dat e: Sheet
Compal Electronics, Inc.
Charger
LA-3941P
D
37 45Tuesday, F ebruary 03, 2009
of
0.1
Page 38
A
B
C
D
E
2VREF_51125
12
PC300
0.22U_0603_10V7K
1 1
PR300
13.7K_0402_1%
20K_0402_1%
95.3K_0402_1%
BST_3V
UG_3V
LX_3V
LG_3V
12
PR315
620K_0402_5%
1 2
PR302
1 2
PR304
1 2
PU300
25
P PAD
7
VO2
8
VREG3
9
VBST2
10
DRVH2
11
LL2
12
DRVL2
12
2VREF_51125
ENTRIP2
6
3
4
5
VFB2
VREF
TONSEL
ENTRIP2
TPS51125RGER_QFN24_4X4
GND
VIN
SKIPSEL
EN0
15
16
14
13
12
PC316
0.1U_0603_25V7K
+3VALWP
B+
PL300
HCB2012KF-121T50_0805
1 2
1
+
PC301
@100U_25V_M
2
2 2
+3VALWP
PC312
150U_B2_6.3VM_R45M
3 3
2N7002KDW-2N_SOT363-6
4 4
ENTRIP1
61
PQ304A
SSM3K7002FU_SC70-3
B++
12
12
PC302
4.7UH_MSCDRI-74D-4R7M-E_4A_20%
1
+
2
2
PQ305
12
PC303
@0.1U _0402_25V6
@2200P_0402_50V7K
PL301
12
PR310
@4.7_1206_5%
@680P_0603_50V8J
PC314
5
13
D
2
G
S
PC304
4.7U_0805_25V6-K
12
12
ENTRIP2
34
PQ304B
2N7002KDW-2N_SOT363-6
PR317
100K_0402_5%
1 2
330K_0402_5%
PR318
3 5
241
3 6
241
12
PQ300
AON7408L_DFN8-5
UG1_3V
578
PQ302
AO4468_SO8
VL
12
PC309
10U_0805_6.3V6M
PR308
0_0402_5%
1 2
1 2
PC310 0.1U_0402_10V7K
SLP_S3#<21,23,27,32,33,34,37,40,41,43>
KBC_PWR_ON <32>
+3VLP
PR306 0_0402_5%
1 2
B++
EN0
PR312
@1M_0402_1%
1 2
PR313
@0_0402_5%
1 2
PD300
1SS355_SOD323-2
PR301
30.9K_0402_1%
1 2
PR303
20K_0402_1%
1 2
105K_0402_1%
ENTRIP1
1 2
1
2
VFB1
ENTRIP1
VO1
PGOOD
VBST1
DRVH1
LL1
DRVL1
VREG5
VCLK
17
18
+5VLP
1 2
12
0_0402_5%
PC317
10U_0805_10V6K
PR305
24
23
22
21
20
19
PR316
BST_5V
UG_5V
LX_5V
LG_5V
+5VALWP
+3VALWP
0_0402_5%
1 2
B++
PR307
+3VL
12
PR314
@100K_0402_5%
1 2
1 2
2 1
2 1
+5VALWP
12
12
PC305
@0.1U _0402_25V6
PC311
0.1U_0402_10V7K
1 2
RPGOOD <21>
PJP300
PAD-OPEN 4x4m
PJP301
PAD-OPEN 4x4m
PJP302
PAD-OPEN 2x2m
PJP303
PAD-OPEN 2x2m
12
PC307
PC306
4.7U_0805_25V6-K
@2200P_0402_50V7K
PR309
0_0402_5%
1 2
IRF8707TRPBF_SO8
+5VALW
+3VALW
+3VL+3VLP
VL+5VLP
B++
12
PC308
4.7U_0805_25V6-K
5
4
PQ303
3 5
241
786
PQ301
AON7408L_DFN8-5
10U_LF919AS-100M-P3_4.5A_20%
12
12
123
PC315
@680P_0603_50V8J
(4.5A,180mils ,Via NO.= 9)
(3A,120mils ,Via NO.= 6)
PL302
1 2
PR311
@4.7_1206_5%
+5VALWP
1
+
PC313
2
150U_B2_6.3VM_R45M
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS , INC.
2008/09/15 2009/09/15
C
Compal Secret Data
Deciphered Date
Title
Size Doc ument Number R ev
Custom
D
Dat e: Sheet
Compal Electronics, Inc.
3.3VALWP/5VALWP
LA-4902P
38 45Tuesday, F ebruary 03, 2009
E
0.1
of
Page 39
A
1 1
PR400
0_0402_5%
SLP_S4#<21,34>
2 2
+5VALW
+5VALW
1 2
@0.1U_0402_16V7K
PR405
316_0402_1%
1 2
PC406
1U_0603_10V6K
12
PC400
+1.8VP
+1.8VP
12
255K_0402_1%
1 2
PR404 0_0402_5%
4.12K_0402_1%
PR407
1 2
1 2
PC408
@10P_0402_50V8J
PR409
10K_0402_1%
PR402
1 2
12
2
3
4
5
6
PU400
TON
VOUT
V5FILT
VFB
PGOOD
B
BST_1.8V
15
14
1
TP
VBST
EN_PSV
DRVH
TRIP
V5DRV
DRVL
GND7PGND
TPS51117RGYR_QFN14_3.5x3.5
8
LL
PR401
0_0402_5%
1 2
UG_1.8V
13
LX_1.8V
12
11
1 2
+5VALW
10
LG_1.8V
9
PC405
0.1U_0402_10V7K
1 2
PR406
10.7K_0402_1%
12
PR403
0_0402_5%
1 2
PC407
4.7U_0805_10V6K
UG1_1.8V
C
+1.8V_B+
12
578
PC401
@1000P_0402_50V7K
PQ400
AO4466_SO8
3 6
241
786
5
4
PQ401
IRF8707TRPBF_SO8
123
12
12
PC403
PC402
@0.1U _0402_25V6
4.7U_0805_25V6-K
4.7UH_MSCDRI-74D-4R7M-E_4A_20%
PL401
1 2
12
PR408
@4.7_1206_5%
12
PC411
@680P_0603_50V8J
4.7U_0805_6.3V6K
PL400
HCB1608KF-121T30_0603
1 2
12
PC404
4.7U_0805_25V6M
12
PC409
D
B+
+1.8VP
1
+
PC410
2
220U_B2_2.5VM_R25M
DDR2 _PG <33>
PJP400
+1.8VP
3 3
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS , INC.
B
2008/10/31 2009/10/31
Compal Secret Data
Deciphered Date
C
1 2
PAD-OPEN 4x4m
Title
Size Doc ument Number R ev
Dat e: Sheet
(3A,120mils ,Via NO.= 6)
+1.8V
Compal Electronics, Inc.
1.8VP
LA-3942P
D
0.1
of
39 45Tuesday, F ebruary 03, 2009
Page 40
5
4
3
2
1
PR516
SLP_S3#<21,23,27,32,33,34,37,38,41,43>
D D
+5VALW
+5VALW
C C
1 2
PR518
316_0402_1%
PC520
1U_0603_10V6K
SLP_S3#<21,23,27,32,33,34,37,38,41,43>
B B
+5VALW
+5VALW
1 2
PR522
316_0402_1%
PC522
1U_0603_10V6K
0_0402_5%
+1.05VCCP
+1.05VCCP
12
PR521
0_0402_5%
+1.5VSP
+1.5VSP
12
12
PC519
12
@1000P_0402_50V7K
1 2
PR519 0_0402_5%
PR503
1 2
4.12K _0402_1%
1 2
PC526
@10P_ 0402_50V8J
10K_0 402_1%
12
PC524
12
@1000P_0402_50V7K
1 2
PR520 0_0402_5%
PR501
1 2
10.2K_0603_0.1%
1 2
PC525
@10P_ 0402_50V8J
10K_0603_0.1%
PR524
255K_0402_1%
1 2
PR504
PR523
255K_0402_1%
1 2
PR502
PR511
UG_V CCP
LX_VCCP
+5VALW
LG_VCCP
PR510
UG_1.5V
LX_1.5V
+5VALW
LG_1.5V
0.1U_0402_10V7K
PR517
1 2
0.1U_0402_10V7K
PR515
1 2
PC511
1 2
14.7K _0402_1%
PC510
1 2
14K_0 402_1%
12
PC521
4.7U_0805_10V6K
12
PC523
4.7U_0805_10V6K
PR509
0_0402_5%
1 2
PR508
0_0402_5%
1 2
UG1_VCCP
UG1_1.5V
0_0402_5%
BST_VCCP
1 2
1
15
PU501
2
TON
3
VOUT
4
V5FILT
5
VFB
6
PGOOD
12
PU502
2
TON
3
VOUT
4
V5FILT
5
VFB
6
PGOOD
12
14
TP
VBST
DRVH
EN_PSV
V5DRV
DRVL
GND7PGND
TPS51117RGYR_QFN14_3.5x3.5
8
VCCP_PG <33>
BST_1.5V
1
15
14
TP
VBST
DRVH
EN_PSV
V5DRV
DRVL
GND7PGND
TPS51117RGYR_QFN14_3.5x3.5
8
TRIP
TRIP
LL
LL
13
12
11
10
9
0_0402_5%
1 2
13
12
11
10
9
4
578
3 6
241
578
3 6
241
3 5
241
5
AON7406L_DFN8-5
123
PQ502
AO4466_S O8
PQ501
AON7408L_DFN8-5
PQ503
PQ504
AO4468_S O8
VCCP_B+
12
12
PC504
PC505
@1000P_0402_50V7K
2.2UH_PCMC063T-2R2MN_8A_20%
12
PR513
@4.7_1206_5%
12
PC517
@680P_0603_50V8J
+1.5VS_B+
12
12
PC502
PC501
@1000P_0402_50V7K
2.2UH_PCMC063T-2R2MN_8A_20%
12
PR512
@4.7_1206_5%
12
PC516
@680P_0603_50V8J
@0.1U_0402_25V6
@0.1U_0402_25V6
12
PC506
1 2
12
PC508
1 2
HCB1608KF-121T30_0603
1 2
12
PC507
4.7U_0805_25V6-K
4.7U_0805_25V6-K
PL503
PC514
4.7U_0805_6.3V6K
HCB1608KF-121T30_0603
1 2
1/17 delete PC509
4.7U_0805_25V6-K
PL502
PC513
@4.7U_0805_6.3V6K
PL501
PL504
+1.05VCCP
12
+1.5VSP
12
B+
1
+
PC515
2
220U_B2_2.5VM_R25M
B+
1
+
PC512
220U_B2_4VM_R35M
2
1.5VS_PG <33>
PJP500
A A
+1.05VCCP
+1.5VSP
5
1 2
PAD-OPEN 4x4m
PJP501
1 2
PAD-OPEN 4x4m
(8A,120mils ,Via NO.= 6)
+VCCP
(4A,120mils ,Via NO.= 6)
+1.5VS
4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRO NICS, INC. NEIT HER THIS SHEE T NOR THE INFO RMATION IT CO NTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF C OMPAL ELECT RONICS, INC.
3
2006/11/23 2007/11/23
Compal Secret Data
Deciphered Date
2
Title
Size Docum ent Number Rev
Date: Sheet
Compal Electronics, Inc.
1.5VSP/1.05VCCP
LA-3732P
1
of
40 4 5Tuesday, February 03, 2009
0.2
Page 41
A
1 1
B
C
D
+1.8VP
PU600
VIN1VCNTL
2
12
0.1U_0402_10V7K
GND
3
VREF
4
VOUT
G2992F1U_SO8
PC604
10U_0805_6.3V6M
PC601
10U_08 05_10V4Z
12
PR600
1K_0402_1%
12
2 2
+5VALW
PC600
10U_0805_6.3V6M
12
12
PR601
10K_0402_5%
2
13
D
SLP_S3#<21,23,27,32,33,34,37,38,40,43>
1 2
PR603
0_0402_5%
@0.1U_0402_16V7K
PC605
2
G
12
RHU002N06_SOT323-3
S
PQ601
RHU002N06_SOT323-3
G
PQ600
12
13
D
PR602
1K_0402_1%
12
S
PC603
NC
NC
NC
TP
+0.9VSP
6
5
7
8
9
+5VALW
12
PC602
1U_0603_10V6K
3 3
PJP600
+0.9VSP
1 2
(2A,80mils ,Via NO.= 4)
+0.9VS
PAD-OPEN 3x3m
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS , INC.
B
2008/09/15 2009/09/15
Compal Secret Data
Deciphered Date
C
Title
Size Doc ument Number R ev
Dat e: Sheet
Compal Electronics, Inc.
0.9VSP
LA-4902P
D
41 45Tuesday, F ebruary 03, 2009
of
0.1
Page 42
+VCCP
5
4
3
2
1
D D
C C
B B
A A
PR200
68_0402_5%
VGATE
PM_PWROK<8,21,32>
H_PROCHOT#<4>
1 2
H_PROCHOT#
0_0402_5%
VCCSENSE<5>
VSSSENSE<5>
5
PM_DPRSLPVR<8,21>
CLK_ENABLE#<21>
12
PR209
PR215
1 2
@4.22K_0402_1%
PR217
6.81K_0402_1%
150P_0402_50V8J
PC215
H_DPRSTP#< 5,8,20>
+3VALW
PR211 147K_0402_1%
1 2
PH201
@100K_0603_1%_TH11-4H104FT
1 2
1 2
PR216
14.7K_0402_1%
1 2
1000P_0402_50V7K
1 2
1 2
PR218 464K_0402_1%
1 2
12
1 2
PC216 47P_0402_50V8J
1 2
PR223
0_0402_5%
1 2
PR225
0_0402_5%
330P_0402_50V7K
12
PC200
@0.1U_0402_16V7K
PC212
PC214
5.49K_0402_1%
1 2
PC222
PR221
PR206 0_0402_5%
PR205
0_0402_5%
1 2
12
PR207
@1.91K_0402_1%
PR210@40.2K_0402_1%
1 2
H_PROCHOT#
0.015U_0603_25V7K
PC218
390P_0402_50V7K
1 2
PR222
2.21K_0402_1%
1 2
PC220 1000P_0603_50V7K
1 2
12
PC221
1000P_0603_50V7K
12
0.22U_0603_10V7K
PC223 330P_0402_50V7K
1 2
PR227
1K_0402_1%
PC226
PR203
0_0402_5%
1 2
1 2
PU200
1
FDE
2
PMON
3
RBIAS
4
VR_TT#
5
NTC
6
SOFT
7
OCSET
8
VW
9
COMP
10
FB
1 2
1 2
12
PC208
41
40
GND PAD
11
1 2
PR228
11K_0402_1%
4
PR202
0_0402_5%
1 2
1U_0603_6.3V6M
39
38
3V3
PGOOD
VSEN12VDIFF
13
CLK_EN
RTN
37
DPRSTP#
DROOP
14
PWR_GD
12
35
36
VR_ON
DPRSLPVR
DFB
VO
15
16
CPU_VID5
CPU_VID6
CPU_VID4
0_0402_5%
PR208
34
VSS
VSUM
VIN
19
17
18
12
PC219
0.22U_0603_25V7K
1 2
PC224 0.1U_0402_10V7K
2008-07-17
<5>
<5>
CPU_VID3
<32,33>
VID331VID432VID533VID6
30
VID2
29
VID1
28
VID0
27
VCCP
26
LGATE
25
VSSP
24
PHASE
23
UGATE
22
BOOT
21
NC
VDD
ISL6261ACRZ-T_QFN40_6X6
20
1 2
PR219
12
10_0603_5%
PC217
1U_0603_10V6K
PR220
10_0603_5%
1 2
12
0.1U_0402_10V7K
PC225
<5>
<5>
CPU_VID2
LGATE_CPU1
PHASE_CPU1
UGATE_CPU1
BOOT_CPU1
VSUM
12
4.53K_0402_1%
PR226
<5>
<5>
CPU_VID0
CPU_VID1
1 2
PR212
0_0603_5%
+5VALW
+CPU_B+
12
PR224
3.57K_0402_1%
PH200
10KB_0603_5%_ERTJ1VR103J
1 2
+VCC_CORE
<5>
12
PC209
0.01U_0402_16V7K
PC211
0.22U_0603_10V7K
1 2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMA TION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELEC TRONICS, INC.
3
+5VALW
PR204
1_0603_5%
1 2
12
PC210
1U_0603_10V6K
2005/06/23 2006/10/22
578
PQ200
NTMS4816N_SO8
3 6
241
PQ201
NTMFS4946NT1G_SO8FL-5
3 5
241
Compal Secret Data
Deciphered Date
+CPU_B+
12
12
12
PC202
PC201
@0.1U_0603_50V7K
@1000P_0402_50V7K
2
12
PC203
PC204
4.7U_0805_25V6-K
4700P_0402_25V7K
12
12
Title
Size Docu ment Number Re v
Custom
Date: Sheet
12
12
PC205
4.7U_0805_25V6-K
PR213
4.7_1206_5%
PC213
@680P_0603_50V8J
12
PC206
4.7U_0805_25V6-K
0.45UH_ETQP4LR45XFC_25A_-25+20%
12
PR214
7.68K_0805_1%
VSUM
Compal Electronics, Inc.
CPU_CORE
IAX00
Tuesday, February 03, 2009
PL200
HCB2012KF-121T50_0805
1 2
PC207
1000P_0402_50V7K
PL201
1 2
1
B+
+VCC_CORE
42 45
of
0.1
Page 43
5
4
3
2
1
D D
PR1001
100K_0402_5%
1 2
PR1000
100_0402_1%
ADP_SIGNAL<36>
C C
1 2
VIN
12
PR1004
22.6K_ 0402_1%
12
PR1005
10K_0402_1%
S
G
2
PQ1000
D
NDS0610_NL_SOT23-3
13
PR1007
1M_0402_5%
1 2
12
3.9K_0 402_5%
VIN
12
PR1002
12
PR1006
1_0805_1%
PC1000
3900P_0402_50V7K
PD1000
RLS4148_LL34-2
C
PQ1001
2
B
E
3 1
1 2
VIN
12
PR1009
22.6K_ 0402_1%
B B
12
PR1012
10K_0402_1%
3
2
8
P
+
-
G
4
12
PC1001
1U_0805_25V6K
1
O
PU1000A
LM393DG_SO8
12
PR1010
47K_0402_5%
1 2
PD1001
1SS355_SOD323-2
12
PR1011
220K_0402_5%
12
PR1013
220K_0402_5%
SRSET <37>
MMBT3904W_SOT323-3
2
G
+3VL
12
PR1008
47K_0402_5%
SLP_S3#<21,23,27,32,33,34,37,38,40,41>
13
D
PQ1003
RHU002N06_SOT323-3
S
PR1003
10K_0402_5%
+3VS
12
OCP# <21>
BATCAL# <37>
13
D
G
PQ1002
RHU002N06_SOT323-3
S
ADP_ EN <32>
2
12
PR1014
191K_0402_1%
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELEC TRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ADP_EN# <37>
2008/09/15 2009/09/15
3
Compal Secret Data
Deciphered Date
2
Title
Size Docum ent Number Re v
Custom
Date: Sheet
Compal Electronics, Inc.
ADP_OCP
LA-4902P
of
43 45Tuesday, February 03, 2009
1
Page 44
5
+3VS
12
PR700
@30K_0402_1%
D D
C C
+3VS
PR713
10K_0402_5%
+5VALW
B B
A A
1 2
PR717
1 2
1_0402_5%
PC707
2.2U_0603_10V6K
12
5
VGAVR_ON
DFGT_VID_4<8>
DFGT_VID_3<8>
DFGT_VID_2<8>
DFGT_VID_1<8>
DFGT_VID_0<8>
PR712 @0_0402_5%
1 2
GFXVR_EN<8>
PC708 0.0 1U_0402_16V7K
PC714
@68P_0402_50V8J
1 2
1 2
1 2
1 2
1 2
+3VS
1 2
PR716 100K_0402_1%
12
374_0402_1%
12
12
VCC_PRM
PC710 1000P_0402_50V7K
1 2
1 2
PR725 6.98K_0402_1%
12
PC715
180P_0402_50V8J
12
PR730
+5VALW
PR709
PR705
PR710
PR706
PR711
PR707 10K_0402_5%
1 2
PR715
PR720 150K_0402_1%
12
12.4K_0603_1%
PR723
1 2
PR731
4.99K_0402_1%
12
PR701
10_0402_5%
12
PC700
1U_0603_10V6K
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
VGAVR_ON
0_0402_5%
PR728
2.21K_0402_1%
12
4
PU700
16
VCC
31
PGOOD
27
D4
26
D3
25
D2
24
D1
23
D0
30
SPIR
32
FDE
29
VR_ON
22
PVCC
1
RBIAS
2
SOFT
3
OCSET
4
VW
5
COMP
6
FB
12
PC718
560P_0402_50V7K
12
4
3
GFX_B+
12
PR702
10_0402_5%
12
PC704
0.01U_0402_50V7K
15
VSS
VDIFF
7
14
VIN
17
BOOT
18
UGATE
19
PHASE
21
LGATE
20
PGND
13
VSUM
12
VO
28
I2UA
11
DFB
10
DROOP
8
VSEN
9
RTN
EP
ISL6263CRZ-T_QFN32_5X5
33
PC719
1000P_0402_50V7K
BST_GFX
1 2
PR721
20K_0402_1%
12
12
PR708
0_0402_5%
1 2
2008-07-02
1 2
PR726 1.74K_0402_1%~N
1 2
PC716
330P_0402_50V7K
12
PC717
1000P_0402_50V7K
PC720
1000P_0402_50V7K
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY O F COMPAL ELECTRONICS, INC. AND CONTAI NS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETE NT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NO R THE IN FORMATI ON IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECT RONICS, INC.
2005/03/10 2006/03/10
3
AO4466_SO8
DH_GFX
12
PC705
0.1U_0402_10V7K
DL_GFX
FDS6690AS_NL_SO8
VSUM1
PR727 1K_0402_1%
1 2
1 2
PR732 0_0402_5%
Compal Secret Data
PQ700
LX_GFX
PQ701
VCC_PRM
1 2
PR729
0_0402_5%
Deciphered Date
578
3 6
241
578
3 6
241
12
Parellel from VCCGFX and GND underneath GMCH at Interface Power pin
12
12
PC701
2200P_0402_50V7K
12
PR714
@4.7_1206_5%
12
PC709
@680P_0603_50V8J
PC713
0.1U_0402_10V7K
+VCCGFX
PC702
4.7U_0805_25V6-K
PR718
+VCCGFXP
2
12
12
PC703
1UH_MPL73-1R0_11A_20%
12
PR722
3.57K_0402_1%
1 2
7.68K_0805_1%
PR724
PC711
PC712 0 .022U_0402_16V7K
2
PC721
4.7U_0805_25V6-K
@0.1U_0603_50V7K
PL701
1 2
1 2
1 2
4.53K_0402_1%
1 2
0.033U_0402_16V7K
1 2
PJP700
1 2
PAD-OPEN 4x4m
PH700
10KB_0603_5%_ERTJ1VR103J
B
1
GFX_B+
PL700
HCB1608KF-121T30_0603
12
PR719
0_0402_5%
Title
Size Document Number Re v
Date : Sheet of
Compal Electronics, Inc.
LA-3261P UMA
12
B+
+VCCGFXP
1
+
PC706
330U_D2E_2.5VM_R9M
2
(5A,200mils ,Via NO.= 10)
+VCCGFX
GM VGA_CORE
1
44 45Tuesday, February 03, 2009
Page 45
Version change list (P.I.R. List) Power section Page 1 of 1
5
4
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1
Item Reason for change PG# Modify List
1
D D
2
3
4
5
6
7
40
42
44
37
41
42
38
39
Date
Phase
41
43
8
9
C C
10
11
12
13
14
15
42
41
42
38
38
42
43
38
39
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17
B B
18
19
20
A A
5
4
38
42
42
43
42
Security Classification
Security Classification
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHOR IZED BY COMPAL E LECTRON ICS, IN C. NEI THER THI S SHEE T NOR THE I NFORMA TION IT CO NTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHOR IZED BY COMPAL E LECTRON ICS, IN C. NEI THER THI S SHEE T NOR THE I NFORMA TION IT CO NTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Compal Secret Data
2006/02/28 2007/02/28
Compal Secret Data
2005/03/10 2006/03/10
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Title
Compal Electronics, Inc.
Title
Changed-List History-1
Size Do cume nt Number R ev
Size Do cume nt Number R ev
Custom
Date: Sheet of
Date: Sheet
LA-3732P
LA-3261P UMA
GM VGA_CORE
45 45Tuesda y, February 03, 2009
45 45Tuesda y, February 03, 2009
1
of
0.2
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