Compal LA-5162P KAM00 UMA, Inspiron Mini 10, LA-5162P KAM01 DIS Schematic

A

B

C

D

E

Compal Model Name:

KAM01(DIS)
KAM00(UMA)

PCB NO:

BOM P/N:

1 1

DA80000E800 LA-5162P R02(X01)(DIS & UMA)

46170431L11 (DIS)
46170431L01 (UMA)

Liver-Pool 13.3"

Compal Confidential

2 2

Schematic Document

Penryn + Cantiga(GM45) + ICH9-M

2009 / 04 / 20

Rev:0.2(X01)

@ : Nopop Component

3 3

1@ : UMA Only
2@ : Discrete Only

ME@ : Mechanical Component

Main-Board TYPE

DIS M/B
UMA M/B

4 4

A

B

BOM P/N

46170431L11
46170431L01

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BOM CONFIGURATION

2@+ME@
1@+ME@

2009/01/05 2009/01/05

C

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

LA-5162P

E

1 60Monday, A pril 20, 2009

0.2

A

B

C

D

E

Block Diagram
Compal confidential
Model : KAM00 LA-5162P (UMA)

KAM01 LA-5162P (DIS)

1 1

Discrete Only

DDR2

+1.8VS

64MX16

512 MB

DDR2

+1.8VS

64MX16

CRT CONN

+5VS

2 2

LVDS CONN

+B+
+3VS
+LCDVDD

HDMI CONN

+3VS

CardReader

OZ888GS0L3N

3 3

+3.3VS

page 19

page 19

page 20

3 in 1 CONN

+3VS_CR

page 27

page 27

Giga LAN

RTL8111DL

+3VALW
+LAN_IO
+LAN_VDD

M92-S2-LP

+1.8VS

+VGA_CO RE

+3VS_DE LAY

+1.1V S_GFX_PCIE

PCI Express BUS

page 26

page 34 ~39

PCIE-E 16X

RG B

L VD S

HDMI level shift

PS8101T

+3.3V _RUN

Mini Card

WiFi

+3VS
+1.5VS
+3VALW
+3V_WLAN

USB[4]

PC IE3PC IE2PC IE5

page 28

page 20

+3VS
+3V_PEC
+3VS_PEC
+1.5VS
+1.5VS_PEC

HD MI

PC IE4

EX PRESS Card

page30

USB[7]

+1.5VS

+VCCP

+CPU_CORE

H_ A#( 3.. 35) H_ D#( 0..6 3)

+3VS

+1.8V/+1.8VS

+1.5VS

+VCCP

+3VS

+VCCP

+1.5VS

+3VALW

+RTCVCC

Pe ntium-M

Penryn -4MB (Socket P)

uFCPGA CPU

478pin

FSB

FSB 800/106 6 MHz

IN TEL

Cantiga

1329pin BGA

page 10,11 ,12,13,14, 15

DM I

+1.5V_R UN
100M Hz

IN TEL

IC H9-M

67 6pin BGA

page 21,22,23,24

page 7,8,9

Memory BUS
(DDR2)

IHDA I/F

S-ATA 0/4

HDD

+5VS

page 28

Clock Generator

CK505
SLG8LP554BVTR

+3VS

+1.8 V_MEM 667/800M Hz

USB 2.0

SA TA0

eSATA Repeater

+3VS

USB[2]

SA TA4

page 29

page6

USB[11]

USB[8]

FAN

FAN1_POWER

+5VS

DDRII-DIMM X2

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7

+1.8V
+V_DDR_MCH_REF

Combine with LVDS Cable

+5VS

Bl ue Tooth

+3VS

USB[0]

USB[1]

page 16,17

Ca mera

USB Port

+5V_USBR

USB Port

+5V_USBR

page 28

page 30

page 29

page 29

The rmal Sensor

+3VS

1402

page 18page 18

INT MIC

IEEE 139 4
C onn

page 29

Transformer

page 29

LPC BUS

E-SATA
CONN

+5V_ESATA

page 29

HeadPhone &
MIC Jack

page 29

On IO/B

RJ45 Conn

+LAN_IO

page 29

On IO/B

4 4

Power On/Off
SW & LED

page 31

Power Cont rol

page 32

DCIN/Pre charge

Ch arger

A

page 40

page 41

+3VALWP/+5VALWP

page 42

+VCCP

page 43

Touch Pad

+5VS

B

page 31

+1.8VP

+1.5VSP

PS2 I/F

page 44

page 45

+VGA_COREP

KBC

KB926D3

+RTC_CELL
+3.3V_ALW

Int.KBD

page 46

page 30

page 31

+CPU_COREP

C

SPI

MX 2 5 L 160 5AM 2C

+3VALW
+EC_AVCC

page 30

2Mb

+0.9V SP/+1.1V_GFX_PCIEP

page 47

Battery

page 48

page 49

D

HD Codec
92 HD81B

+3VS
+AVDD_H D

page 25

INT. Speaker

2 x 1W

On IO/B

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Doc ument Number Re v

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

LA-5162P

2 60Monday, A pril 20, 2009

E

1A

A

Voltage Rails

State

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

1 1

O MEANS ON X MEANS OFF

power
plane

+B

O

O

O

O

O

X

+5VALW

+3VALW

+1.8V

+1.1VS_GFX_PCIE

O

O

O

O

X

O

X X

X

X X X

+5VS

+3VS

+1.5VS

+VCCP

+CPU_CORE

+GPU_CORE

+1.8VS

+0.9VS

OO

OO

X

X

SATA

Lane 0

Lane 1

Lane 4

Lane 5

DESTINATION

HDD

NONE

ESATA

NONE

USB PORT#

0

1

2

3

DESTINATION

JUSBR1

JUSBR2

JUSBR3(E-SATA)

NONE

PCI EXPRESS

Lane 1 NONE

Lane 2

Lane 3

Lane 4

Lane 5

Lane 6

DESTINATION

GIGA LAN

WLAN

EXPRESS CARD

CARD READER

NONE

BOARD ID Table

BOARD ID

ID

0

0.1(X00)

1

0.2(X01)

2

0.3(X02)

3

1.0(A00)

NC
100K
100K
100K

Symbol Note :

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build
DEBUG@ : means just reserve for debug.

RbRa

0

9.09K
20K

37.4K

Vab

0V

0.25V

0.50V

0.82V

ICH9-M

4

5

6

*

7

8

9

10

11

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

WLAN

NONE

NONE

Express card

Bluetooth

NONE

NONE

CAMERA

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

Index and Configuration

LA-5162P

3 60Monday, A pril 20, 2009

0.2

5

4

3

2

1

INVERTER

ADAPTER

D D

EN_WOL#

SUSP

BATTERY

EC_ON

TPS51427

(PU5)

+3VALW

(U41)

SI3456BDV

(Q128)

SI4800DY

(U40)

RT9013

+1.5V_HDA

+LAN_IO

+3VS

3VS_DELAY_ON

SI2301BDS

(QG1)

+3VS_DELAY

B+

BATT+

C C

+5VALW

RUNON

CHARGER

24751
(PU4)

2@

VGA_ON

ISL6268CAZ-T

(PU9)

+VGA_CORE

SI4800DY

(U39)

+5VS

CAM_ON/OFF#

TPS71718DCKR

(U59)

SI2301BDS

(Q15)

+5V_AVDD_HD

+5V_CAM

SYSON

B B

VR_ON'

SUSP#

A A

5

SUSP#

TPS51117RGYR

(PU7)

ISL6266ACRZ-T

(PU10)

TPS51117RGYR

(PU6)

TPS51117RGYR

(PU8)

4

+1.8V

+CPU_CORE

+VCCP

+1.5VS

1.1VS_GFX_ON

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

SUSP

VGA_PWROD#

MAX8794

(PU11)

RT9026GFP

(PU12)

SI4800DY

(UG41)

+1.1V_GFX_PCIEP

+0.9VS

+1.8VS

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Doc ument Number Re v

2

Date: Sheet of

Compal Electronics, Inc.

Power Rails

LA-5162P

4 60Monday, A pril 20, 2009

1

1.0

5

4

3

2

1

2.2K

2.2K

G16

D D

ICH9-M

C C

ICH_SMBCLK

A13 ICH_SMBDATA

4.7K

4.7K

EC_SMB_CK1 7

77

EC_SMB_DA1

78

ENE

2.2K

+3VALW

2N7002

+5VALW

100 ohm

100 ohm

ICH_SM_CLK

ICH_SM_DA

Battery

6

Connector

2.2K

2.2K

16

Colck

17

Generator

195

JDIMMA

197

JDIMMB

8

7

Express Card

32

30

WLAN Card

+3VS

KB926

+3VS

CLK_THERMAL

DATA_THERMAL

8

7

EMC
1402

79

SMB_CLK_THERMAL

80

SMB_DATA_THERMAL

2.2K

B B

2.2K

2.2K

ATI

U7 ATI_SMBCLK

ATI_SMBDATAU8

M92-S2

A A

+3V_DELAY

ATI_SMBCLK

ATI_SMBDATA

8

7

ADM
1032

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Doc ument Number Re v

5

4

3

2

Date: Sheet of

Compal Electronics, Inc.

SMBus Topology

LA-5162P

5 60Monday, A pril 20, 2009

1

1.0

5

D D

4

+CK_VDD_M AIN+3VS

L1

1 2

BK2125HS601-T_0805~D

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C1

C9

2

0.1U_0402_16V4Z

1

1

C1011

2

2

1

C2

2

3

0.1U_0402_16V4Z

10U_0805_6.3V6-M~D

1

C4

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C5

C6

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C3

C7

2

2

2

FSB

FSC

CLKSEL2

0

0 1

*

0

1

1

FSA

CPU

SRC
MHz

100

100

PCI
MHz

33.3100

33.3

33.3

MHz

CLKSEL0CLKSEL1

266

00

200

0

166

1

R1222

1 2

0.047U_0402_16V 4Z~D

0.047U_0402_16V 4Z~D

1

1

C1012

Place close to U1 pin 18 and 40

C16

12

Place crystal w ithin
500 mils of CK505

C C

CLK_ICH_48M

10P_0402_50V8J~D

@

1

C1419

2

Place close to R21 pin2

+3VS

10K_0402_5%~D

B B

R45

1 2

TME

+3VS

10K_0402_5%~D

R1050

1 2

PCI _ICH

+3VS

10K_0402_5%~D

@

12

RG116

*

*

CLK_ICH_ 48M<23>
CPU_MCH_BSEL0<8,10>
CPU_MCH_BSEL1<8,10>

CPU_MCH_BSEL2<8,10>

CLK_DEBU G_PORT<28>

CLK_PC I_926<30>

CLK_ICH_ 14M<23>

MCH_ DREFCLK<10>
CLK_ATI_27M<35>
MCH_ DREFCLK#<10>
CLK_ATI_27M_SS<35>

CLK_P CI_ICH<21>

TME0PIN 32

Overclo cking enable

Overclo cking disable1

ITP_EN

PIN 37

Pin 5/6 as SRC_10

0

Pin 5/6 as CPU_ITP

1

33P_0402_50V8J~D

33P_0402_50V8J~D

CLK_ICH_48M
CPU_MCH_BSEL0
CPU_MCH_BSEL1

CPU_MCH_BSEL2

CLK_ICH_14M CLKRE F

MCH_ DREFCLK
CLK_ATI_27M
MCH_ DREFCLK#
CLK_ATI_27M_SS

CLK_P CI_ICH

12

CPN: SJ100005W0L

Y6

C17

14.318 18MHZ_20PF_1Y714318CE1B~D

12

R19 0_0402_5%

R21 33_0402_5%~D
R23 2.2K_0402_5%~D

R25 10K_0402_5%~D

R117 33_0402_5%~D

R1034 33_0402_5%~D

R9 33_0402_5%~D

R40 33_040 2_5%~D
RG44 61.9_0402_1%@
R41 33_040 2_5%~D
RG119 33_ 0402_5%~D@

R44 33_0402_5%~D

1 2

1 2

1 2

1 2

1 2

1 2
1 2
1 2
1 2

12

12

12

CLK_PW RGD<23>

ICH_SM _CLK< 16,17,23,27,28>

ICH_SM_DA<16,17 ,23,27,28>

C13

2

2

CLK_XTAL_IN

CLK_XTAL_OUT

FSA

FSC

FCT_SEL

CLK_DE BUGCLK_DEBU G_PORT

TME CLK_P CIE_LAN#

PCI_E CCLK_PC I_926

DOT96

DOT96#

PCI _ICH

CLK_PW RGD

ICH_SM_CLK

ICH_SM_DA

1
49
54
65

30
36

12

18

40

20

19

41

45

23

34

33

32

27

22

43

44

37

39

9

16

17

4

15

21

31

35

42

68

73

2.2_0603_5%~D

U1

VDD_SRC
VDD_SRC
VDD_SRC
VDD_SRC

VDD_PCI
VDD_PCI

VDD_CPU

VDD_REF

VDD_48

XTAL_IN

XTAL_OUT

USB_48MHz/FSLA

FSL_B/TEST_MODE

REF_0/FSL_C/TEST_SEL

PCICLK4/FCT_SEL

PCICLK3

PCICLK2/TME

PCICLK1

REF_1

DOT_96/27M

DOT_96#/27M_SS

PCICLK_F0/ITP_EN

CKPWRGD/PD#

NC

SMBCLK

SMBDAT

VSS_SRC

VSS_CPU

VSS_REF

VSS_PCI

VSS_PCI

VSS_48

VSS_SRC

THRM_PAD

SLG8LP554BVTR

FCT_SEL PIN44PIN43 PIN48PIN47

A A

FCT_SEL

10K_0402_5%~D

12

R58

1=DIS 27M SSout27M_out

5

DOT96T0=UMA

96/100M_C96/100M_TDOT96C

SRCC0SRCT0

4

SLG8LP554BVTR_QFN72_10X10~D

CIS Link:OK

CPN:SA000026T0L

PROPR IETARY NOTE : THI S SHEE T OF ENGIN EERIN G DRAW ING A ND SP ECIFIC ATION S CON TAINS CONFIDENTIAL
TRADE SECRE T AND OTHE R PROP RIETA RY IN FORMA TION O F DEL L INC . ("DE LL") THIS DOCUME NT MAY NOT
BE TR ANSFER RED O R COP IED WI THOUT THE EXPRE SS WRI TTEN AUTHO RIZATI ON OF DELL . IN ADDITION,
NEITH ER THI S SHE ET NO R THE INFOR MATIO N IT CONTAI NS WA Y BE USED B Y OR DISCL OSED T O ANY THIRD
PARTY WITHO UT DE LL'S EXPRES S WRI TTEN CONSENT.

3

+CK_VDD_A

VDD_A

VSS_A

PCI_STP#

CPU_STP#

CPU_1

CPU_1#

CPU_0

CPU_0#

CPU_ITP/SRC_10

CPU_ITP#/SRC_10#

SRC_9

SRC_9#

CLKREQ_9#

SRC_8

SRC_8#

CLKREQ_8#

SRC_7

SRC_7#

CLKREQ_7#

SRC_6

SRC_6#

CLKREQ_6#

SRC_5

SRC_5#

CLKREQ_5#

SRC_4

SRC_4#

CLKREQ_4#

SRC_3

SRC_3#

CLKREQ_3#

SRC_2

SRC_2#

CLKREQ_2#

SRC_1/SATA

SRC_1#/SATA#

CLKREQ_1#

LCD_CLK/SRC_0

LCD_CLK#/SRC_0#

7

8

25

24

11

10

14

13

6

5

3

2

72

70

69

71

66

67

38

63

64

62

60

61

29

58

59

57

55

56

28

52

53

26

50

51

46

47

48

4.7U_0603_6.3V6M~D

1

C14

C15

2

H_STP_PCI#

H_STP_CPU#

CLK_MCH_BCLK

CLK_MCH_BCLK#

CLK_CP U_BCLK

CLK_CP U_BCLK#

CLK_P CIE_WLAN

CLK_P CIE_WLAN#

WLAN _CLK_REQ#

CLK_P CIE_LAN

LAN_CLK_RE Q#

CLK_P CIE_ICH

CLK_P CIE_ICH#

CLK_P CIE_CR

CLK_P CIE_CR#

CR_CL K_REQ#

CLK_P CIE_VGA_R

CLK_P CIE_VGA#_R

VGA_CLK_R EQ#_R

CLK_PCIE_EXP

CLK_PCIE_EXP#

EXP_CLK_REQ#

CLK_MCH_3GPLL

CLK_MCH_3GPLL#

CLK_3GPLLR EQ#_R

CLK_PCIE_SATA

CLK_PCIE_SATA#

SATA_CLK_REQ#_R

DREF_ SSCLK_R

DREF_ SSCLK#_R

0.047U_0402_16V 4Z~D

H_STP_PCI# <23>

H_STP_CPU# <23>

CLK_MCH_BCLK <10>

CLK_MCH_BCLK# <10>

CLK_CP U_BCLK <7>

CLK_CP U_BCLK# <7>

CLK_P CIE_WLAN <28>

CLK_P CIE_WLAN# <28>

WLAN _CLK_REQ# <28>

CLK_P CIE_LAN <26>

CLK_P CIE_LAN# <26>

LAN_CLK_RE Q# <26>

CLK_P CIE_ICH <23>

CLK_P CIE_ICH# <23>

CLK_P CIE_CR <27>

CLK_P CIE_CR# <27>

CR_CL K_REQ# <27>

1 2

RG53 0_0402_5%2@

1 2

RG59 0_0402_5%2@

1 2

RG120 0_0402_5%2@

CLK_PCIE_EXP <27>

CLK_PCIE_EXP# <27>

EXP_CLK_REQ# <27>

CLK_MCH_3GPLL <10>

CLK_MCH_3GPLL# <10>

1 2

R51 475_0402_1%~D

CLK_PCIE_SATA <22>

CLK_PCIE_SATA# <22>

1 2

R1155 475_0402_1%~D

1 2

R54 0_0402_5%

1 2

R60 0_0402_5%

2

CLK_PCIE_ATI <34>

CLK_PCIE_ATI# <34>

ATI_CLK_REQ# <35>

CLK_3GPLLREQ# <10>

SATA_CLK_REQ# <23>

DREF_ SSCLK <10>

DREF_ SSCLK# <10>

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Doc ument Number Re v

Date: Sheet of

WLAN _CLK_REQ#

LAN_CLK_RE Q#

CR_CL K_REQ#

EXP_CLK_REQ#

CLK_3GPLLREQ#

SATA_CLK_REQ#

R6 10K_0402_5%~D

1 2

1 2

1 2

1 2

1 2

1 2

R10 10K_ 0402_5%~D

R7 10K_0402_5%~D

R121 10K_0402_5%~D

R122 10K_0402_5%~D

R127 10K_0402_5%~D

Compal Electronics, Inc.

Clock GEN. with internal terminations

LA-5162P

1

+3VS

1.0

6 60Monday, A pril 20, 2009

5

D D

4

3

2

1

H_A#[ 3..35]<10>

H_ADSTB#0<10>

H_REQ#0<10>
H_REQ#1<10>
H_REQ#2<10>
H_REQ#3<10>
H_REQ#4<10>

C C

H_ADSTB#1<10>

H_A20M#<22>
H_FER R#<22>
H_IGNN E#<22>

H_STPCLK#<22>
H_INTR<22>
H_NMI<22>
H_SMI#<22>

B B

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_FER R#
H_IGNN E#

H_STPCLK#
H_INT R
H_NMI
H_SMI#

ME@

JCPU1A

ADDR GROUP 0 ADDR GROUP 1

J4

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4
AB2
AA3

V1

A6
A5
C4

D5
C6
B4
A3

M4

N5
T2
V3
B2
C3
D2

D22

D3
F6

TH ERMAL

A[33]#
A[34]#

PROCHOT#

A[35]#
ADSTB[1]#

ICH

A20M#
FERR#

THERMTRIP#

IGNNE#

STPCLK#
LINT0
LINT1
SMI#

RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]

RESERVED

RSVD[10]

FOX_PZ4782A-274R-41_M erom

ADS#
BNR#
BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK

TDO
TMS

TRST#

XDP/ITP SIGNALS

DBR#

THERMDA
THERMDC

H CLK

BCLK[0]
BCLK[1]

H_ADS#

H1

H_BNR #

E2

H_BPR I#

G5

H_DEF ER#

H5

H_D RDY#

F21

H_ DBSY#

E1

H_BR0#

F1

H_IER R#

D20
B3

H_LOCK#

H4

H_RESET#

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3

H_ TRDY#

G2

H_HIT#

G6

H_HITM#

E4

AD4
AD3
AD1
AC4
AC2
AC1

XDP_TCK

AC5

XDP_TDI

AA6

TDI

AB3

XDP_TMS

AB5

XDP_TRST#

AB6
C20

VR_TT#

D21

H_THERMDA

A24

H_THERMDC

B25

H_THERMTRIP#

C7

CLK_CP U_BCLK

A22

CLK_CP U_BCLK#

A21

H_ADS# <10>
H_BNR # <10>
H_BPR I# <10>

H_DEF ER# <10>
H_D RDY# <10>
H_D BSY# <10>

H_BR0# <10>

H_INIT# < 22>

H_LOCK# <10>

H_RESET# <10>
H_RS#0 <10>
H_RS#1 <10>
H_RS#2 <10>
H_T RDY# <10>

H_HIT# <10>
H_HITM# <10>

R68

@

1 2

0_0402_5%

R69

@

1 2

0_0402_5%

R71

@

1 2

0_0402_5%

R87

@

1 2

0_0402_5%

H_THERMDA <18>
H_THERM DC <18>

H_THERMTRIP# <10,22>

CLK_CP U_BCLK <6>
CLK_CP U_BCLK# <6>

H_IER R#

XDP_TDI

XDP_TMS

XDP_TRST#

XDP_TCK

R18 56_0402_5%

R5 54.9_0402_1%

R4 54.9_0402_1%

R11 54.9_0402_1%

R35 54.9_0402_1%

This shall place near CPU

+VCCP

VR_TT#

1 2

1 2

1 2

1 2

12

R92

68_0402_1%~D

VR_TT# <48>

+VCCP

12

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

CIS Link:OK

12/29

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

Penryn(1/3)-AGTL+/ITP-XDP

LA-5162P

1

7 60Monday, A pril 20, 2009

0.2

5

4

3

2

1

H_D #[0..63]<10>

ME@

H_D#0
H_D#1
H_D#2

D D

H_DSTBN#0<10>
H_DSTBP#0<10>
H_DIN V#0<10>

C C

R52 1K_0402_5%~D@
R22 1K_0402_5%~D@

CPU_MCH_BSEL0<6,10>
CPU_MCH_BSEL1<6,10>
CPU_MCH_BSEL2<6,10>

H_DSTBN#1<10>
H_DSTBP#1<10>
H_DIN V#1<10>

1 2
1 2

T12
T13
T14
T15

H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DIN V#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30

H_D#31
H_DSTBN#1
H_DSTBP#1
H_DIN V#1

+V_CPU_GTLREF

TEST1

TEST2

TEST3

TEST4

TEST5

TEST6

CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2

layout note: Rout H_DPRSTP# from ICH9 to IMVP6 then to GMCH & CPU

layout note: Route TEST3 & TE ST5 tr aces on ground referenced layer to the TPs

FSB
Frequency

B B

667MHz

800MHz

BSEL[2] BSEL[1]

0 1

0 1

JCPU1B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

AD26

AF26

M24

M23

R24

N25

M26
N24

C23
D25
C24

AF1

C21

L23

L22

P25
P23
P22
T24

L25
T25

L26

A26

B22
B23

DATA GRP 1

D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

GTLREF

MISC

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

BSEL[0]
BSEL[1]
BSEL[2]

FOX_PZ4782A-274R-41_M erom

BSEL[0]

1

0

DATA GRP 0

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#

DATA GRP 2DATA GRP 3

D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#

COMP[0]
COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

*

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DIN V#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DIN V#3

COMP0
COMP1
COMP2
COMP3

H_DPRSTP#
H_DPSLP#
H_DPW R#
H_PW RGOOD
H_CPUSLP #
H_PSI#

H_DSTBN#2 <10>
H_DSTBP#2 <10>
H_DIN V#2 <10>

H_DSTBN#3 <10>
H_DSTBP#3 <10>
H_DIN V#3 <10>

H_DPRSTP# <10,22,48>
H_DPSLP# <22>

H_DPW R# <10>

H_PW RGOOD <22>
H_CPUSLP # <10>

H_PSI# <48>

12

12

12

R1023

R24

54.9_0402_1%

27.4_0402_1%

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4 mils

R26

R1025

27.4_0402_1%

54.9_0402_1%

+CPU_ CORE +CPU_CORE

12

ME@

JCPU 1C

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15
AB17
AB18

VCCSENSE
VCC[065]
VCC[066]
VCC[067]

VSSSENSE

FOX_PZ4782A-274R-41_M erom

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

VCCSENS E

VSSSENSE

CPU_V ID0 <48>
CPU_V ID1 <48>
CPU_V ID2 <48>
CPU_V ID3 <48>
CPU_V ID4 <48>
CPU_V ID5 <48>
CPU_V ID6 <48>

VCCSENS E <48>

VSSSENSE <48>

220U_ D2_4VY_R15M

+VCCP

C1110

10U_0805_6.3V6M

1

2

1

2

+

C1112

+1.5VS

1

C11

2

0.01U_0402_16V7K

Near pin B26

1066MHz 0 0 0

VCCSENSE, VSSSENSE-->Width=18mils,
Space=7mils, Space to other signals 25mils at least.

+VCCP

12

R27

1K_0402_1%

+V_CPU_GTLREF

12

R29

2K_0402_1%

A A

Close to CPU pin AD26

Length match within 25 mils.

Close to CPU pin
within 500mils.

within 500mils.

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

2

VCCSENS E

VSSSENSE

Title

Size Doc ument Number Re v

Cus tom

LA-5162P

Date: Sheet of

+CPU_C ORE

R28100_0402_1%

12

R30100_0402_1%

12

Compal Electronics, Inc.

Penryn(2/3)-AGTL+/ITP-XDP

1

8 60Monday, A pril 20, 2009

0.2

5

High Frequence Decoupling

10uF 0805 X5R -> 85 degree.

D D

C C

B B

A A

ME@

JCPU 1D

A4

A8
A11
A14
A16
A19
A23
AF2

B6

B8
B11
B13
B16
B19
B21
B24

C5

C8
C11
C14
C16
C19

C2
C22
C25

D1

D4

D8
D11
D13
D16
D19
D23
D26

E3

E6

E8
E11
E14
E16
E19
E21
E24

F5

F8
F11
F13
F16
F19

F2
F22
F25

G4

G1
G23
G26

H3

H6
H21
H24

J2

J5
J22
J25

K1

K4
K23
K26

L3

L6
L21
L24

M2

M5
M22
M25

N1

N4
N23
N26

FOX_PZ4782A-274R-41_M erom

VSS[082]

VSS[001]
VSS[002]

VSS[083]

VSS[003]

VSS[084]

VSS[004]

VSS[085]

VSS[005]

VSS[086]

VSS[006]

VSS[087]

VSS[007]

VSS[088]

VSS[008]

VSS[089]

VSS[009]

VSS[090]

VSS[010]

VSS[091]

VSS[011]

VSS[092]

VSS[012]

VSS[093]

VSS[013]

VSS[094]

VSS[014]

VSS[095]

VSS[015]

VSS[096]

VSS[016]

VSS[097]

VSS[017]

VSS[098]

VSS[018]

VSS[099]

VSS[019]

VSS[100]

VSS[020]

VSS[101]

VSS[021]

VSS[102]

VSS[022]

VSS[103]

VSS[023]

VSS[104]

VSS[024]

VSS[105]

VSS[025]

VSS[106]

VSS[026]

VSS[107]

VSS[027]

VSS[108]

VSS[028]

VSS[109]

VSS[029]

VSS[110]

VSS[030]

VSS[111]

VSS[031]

VSS[112]

VSS[032]

VSS[113]

VSS[033]

VSS[114]

VSS[034]

VSS[115]

VSS[035]

VSS[116]

VSS[036]

VSS[117]

VSS[037]

VSS[118]

VSS[038]

VSS[119]

VSS[039]

VSS[120]

VSS[040]

VSS[121]

VSS[041]

VSS[122]

VSS[042]

VSS[123]

VSS[043]

VSS[124]

VSS[044]

VSS[125]

VSS[045]

VSS[126]

VSS[046]

VSS[127]

VSS[047]

VSS[128]

VSS[048]

VSS[129]

VSS[049]

VSS[130]

VSS[050]

VSS[131]

VSS[051]

VSS[132]

VSS[052]

VSS[133]

VSS[053]

VSS[134]

VSS[054]

VSS[135]

VSS[055]

VSS[136]

VSS[056]

VSS[137]

VSS[057]

VSS[138]

VSS[058]

VSS[139]

VSS[059]

VSS[140]

VSS[060]

VSS[141]

VSS[061]

VSS[142]

VSS[062]

VSS[143]

VSS[063]

VSS[144]

VSS[064]

VSS[145]

VSS[065]

VSS[146]

VSS[066]

VSS[147]
VSS[148]

VSS[067]
VSS[068]

VSS[149]

VSS[069]

VSS[150]

VSS[070]

VSS[151]

VSS[071]

VSS[152]

VSS[072]

VSS[153]

VSS[073]

VSS[154]

VSS[074]

VSS[155]

VSS[075]

VSS[156]

VSS[076]

VSS[157]

VSS[077]

VSS[158]

VSS[078]

VSS[159]

VSS[079]

VSS[160]

VSS[080]

VSS[161]

VSS[081]P3VSS[162]

VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

+VCCP

1

C213

0.1U_0402_16V7K~D

2

4

+CPU_ CORE

1

C204
10U_0805_4VAM~D

2

+CPU_ CORE

1

C180
10U_0805_4VAM~D

2

+CPU_ CORE

1

C501
10U_0805_4VAM~D

2

+CPU_ CORE

1

C502
10U_0805_4VAM~D

2

+CPU_C ORE

1

C196

+

2

1

C209

0.1U_0402_16V7K~D

2

3

2

1

Place these caps inside
the CPU socket.

1

C205
10U_0805_4VAM~D

2

1

C529
10U_0805_4VAM~D

2

1

C232
10U_0805_4VAM~D

2

1

C258
10U_0805_4VAM~D

2

1

C505
10U_0805_4VAM~D

2

1

C504
10U_0805_4VAM~D

2

1

C257
10U_0805_4VAM~D

2

1

C262
10U_0805_4VAM~D

2

1

( Left side on Top ).

C214
10U_0805_4VAM~D

2

Place these caps inside
the CPU socket.

1

C202
10U_0805_4VAM~D

2

1

C508
10U_0805_4VAM~D

2

1

C510
10U_0805_4VAM~D

2

330U_ D2_2.5VY_R9M

330U_ D2_2.5VY_R9M

1

C198

+

2

1

C259

+

2

1

C212

0.1U_0402_16V7K~D

2

330U_ D2_2.5VY_R9M

330U_ D2_2.5VY_R9M

1

C255

+

2

1

2

1

C254
10U_0805_4VAM~D

2

1

C514
10U_0805_4VAM~D

2

1

C515
10U_0805_4VAM~D

2

C188

0.1U_0402_16V7K~D

1

C190
10U_0805_4VAM~D

2

1

C519
10U_0805_4VAM~D

2

1

C520
10U_0805_4VAM~D

2

1

C183

0.1U_0402_16V7K~D

2

1

C203
10U_0805_4VAM~D

2

1

C523
10U_0805_4VAM~D

2

1

C528
10U_0805_4VAM~D

2

1

C200
10U_0805_4VAM~D

2

1

C533
10U_0805_4VAM~D

2

1

C532
10U_0805_4VAM~D

2

ESR <= 1.5m ohm

Capacitor > 880 uF

Plac e these inside
sock et cavity o n L8
(North side
Secon dary)

1

C185

0.1U_0402_16V7K~D

2

1

C184
10U_0805_4VAM~D

2

1

C199
10U_0805_4VAM~D

2

1

C208
10U_0805_4VAM~D

2

1

( Righ t side on Top ).

C1126
10U_0805_4VAM~D

2

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

Penryn(3/3)-AGTL+/ITP-XDP

LA-5162P

1

9 60Monday, A pril 20, 2009

0.2

5

U4A

H_D# [0..63]<8>

D D

C C

H_RESET#<7>
H_CPU SLP#<8>

B B

Layout Note:
+H_RCO MP / +H_VREF / +H_SWING

trace width and spacing is 10/20

+VCCP

12

R1045

1K_0402_1%

A A

12

R46

2K_0402_1%

1

2

0.1U_0402_16V7K~D

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

+H_SW ING
+H_RCOMP

H_RESET#

H_CPUSLP #

+H_VREF

+H_VREF

C391

@

5

F2

H_D#_0

G8

H_D#_1

F8

H_D#_2

E6

H_D#_3

G2

H_D#_4

H6

H_D#_5

H2

H_D#_6

F6

H_D#_7

D4

H_D#_8

H3

H_D#_9

M9

H_D#_10

M11

H_D#_11

J1

H_D#_12

J2

H_D#_13

N12

H_D#_14

J6

H_D#_15

P2

H_D#_16

L2

H_D#_17

R2

H_D#_18

N9

H_D#_19

L6

H_D#_20

M5

H_D#_21

J3

H_D#_22

N2

H_D#_23

R1

H_D#_24

N5

H_D#_25

N6

H_D#_26

P13

H_D#_27

N8

H_D#_28

L7

H_D#_29

N10

H_D#_30

M3

H_D#_31

Y3

H_D#_32

AD14

H_D#_33

Y6

H_D#_34

Y10

H_D#_35

Y12

H_D#_36

Y14

H_D#_37

Y7

H_D#_38

W2

H_D#_39

AA8

H_D#_40

Y9

H_D#_41

AA13

H_D#_42

AA9

H_D#_43

AA11

H_D#_44

AD11

H_D#_45

AD10

H_D#_46

AD13

H_D#_47

AE12

H_D#_48

AE9

H_D#_49

AA2

H_D#_50

AD8

H_D#_51

AA3

H_D#_52

AD3

H_D#_53

AD7

H_D#_54

AE14

H_D#_55

AF3

H_D#_56

AC1

H_D#_57

AE3

H_D#_58

AC3

H_D#_59

AE11

H_D#_60

AE8

H_D#_61

AG2

H_D#_62

AD6

H_D#_63

C5

H_SWING

E3

H_RCOMP

C12

H_CPURST#

E11

H_CPUSLP#

A11

H_AVREF

B11

H_DVREF

CANTI GA ES_FCBGA1329

+H_RCOMP

12

R324

24.9_0402_1%

+VCCP

221_0603_1%

100_0402_1%

12

R322

12

R323

H_ADSTB#_0
H_ADSTB#_1

H_DEFER#

HOST

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

Near B3 pinwithin 100 mils from NB

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_BREQ#

H_DBSY#

H_DRDY#

H_HIT#

H_HITM#

H_LOCK#
H_TRDY#

H_RS#_0
H_RS#_1
H_RS#_2

+H_SW ING

1

2

0.1U_0402_16V7K~D

C386

A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20

H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9

J8
L3
Y13
Y1

L10
M7
AA5
AE6

L9
M8
AA6
AE5

B15
K13
F13
B13
B14

B6
F12
C8

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR #
H_BPR I#
H_BR0#
H_DEF ER#
H_ DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPW R#
H_D RDY#
H_HIT#
H_HITM#
H_LOCK#
H_ TRDY#

H_DIN V#0
H_DIN V#1
H_DIN V#2
H_DIN V#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

4

H_A#[ 3..35] <7>

+SMRCOMP_VOH

+SMRCOMP_VOL

H_ADS# <7>
H_ADSTB#0 < 7>
H_ADSTB#1 < 7>
H_BNR # <7>
H_BPR I# <7>
H_BR0# <7>
H_DEF ER# <7>
H_D BSY# <7>
CLK_MCH_BCLK <6>
CLK_MCH_BCLK# <6>
H_DPW R# <8>
H_D RDY# <7>

H_HIT# <7>
H_HITM# <7>
H_LOCK# <7>

H_T RDY# <7>

H_DIN V#0 <8>
H_DIN V#1 <8>
H_DIN V#2 <8>
H_DIN V#3 <8>

H_DSTBN#0 <8>
H_DSTBN#1 <8>
H_DSTBN#2 <8>
H_DSTBN#3 <8>

H_DSTBP#0 <8>
H_DSTBP#1 <8>
H_DSTBP#2 <8>
H_DSTBP#3 <8>

H_REQ#0 <7>
H_REQ#1 <7>
H_REQ#2 <7>
H_REQ#3 <7>
H_REQ#4 <7>

H_RS#0 <7>
H_RS#1 <7>
H_RS#2 <7>

ICH_P WROK<23,30>

Layout Note:
+V_DDR _MCH_REF
trace width and
spacin g is 20/20.

4

3

T7
T11
T72

+1.8V

1

1

C398

2

2.2U_06 03_6.3V6K~D

1

C403

2

2.2U_06 03_6.3V6K~D

PLT_RST#<21,27,30,34>

DPRSLPVR<23,48>

1 2

R408 0_0402_5%

+V_DD R_MCH_REF +VCCP

0.1U_0402_16V7K~D

12

R331

C400

1K_0402_1%

0.01U_0402_16V7K

2

12

R332

3.01K_0402_1%

12

R333

1

1K_0402_1%

C404

2

0.01U_0402_16V7K

+3VS

10K_0402_5%~D

10K_0402_5%~D

R523 100_0402_5%~D

+V_DD R_MCH_REF

1

C121

2

R82

12

R83

12

C36

@

12

0.1U_0402_16V7K~D

CPU_MCH_BSEL0<6,8>
CPU_MCH_BSEL1<6,8>
CPU_MCH_BSEL2<6,8>

PM_BMBUSY#<23>

H_DPRSTP#<8,22,48>
PM_EXTTS#0<16>

PM_PWROK_R

PM_EXTTS#1<17>

H_THERMTRIP#<7,22>

+1.8V

1 2

PM_EXTTS#0

PM_EXTTS#1

H_DPRSTP#

CFG5<12>
CFG6<12>
CFG7<12>

CFG9<12>

CFG16<12>

CFG19<12>
CFG20<12>

12

R42
1K_0402_1%

12

R43
1K_0402_1%

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

T23
T74
T75
T136
T17
T18
T19
T20
T21
T22
T24

T25
T26
T27

T28

T41
T44
T73
T184

CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2

T8
T9

CFG5
CFG6
CFG7

T37

CFG9

T65
T40

CFG12

T67

CFG13

T47
T10
T66

CFG16

T68
T39

CFG19
CFG20

PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_PWROK_R
PLT_RST#_NB
H_THERMTRIP#
DPRSLPVR

2009/01/05 2009/01/05

3

U4B

M36

RSVD1

N36

RSVD2

R33

RSVD3

T33

RSVD4

AH9

RSVD5

AH10

RSVD6

AH12

RSVD7

AH13

RSVD8

K12

RSVD9

AL34

RSVD10

AK34

RSVD11

AN35

RSVD12

AM35

RSVD13

T24

RSVD14

B31

RSVD15

B2

RSVD16

M1

RSVD17

AY21

RSVD20

BG23

RSVD22

BF23

RSVD23

BH18

RSVD24

BF18

RSVD25

T25

CFG_0

R25

CFG_1

P25

CFG_2

P20

CFG_3

P24

CFG_4

C25

CFG_5

N24

CFG_6

M24

CFG_7

E21

CFG_8

C23

CFG_9

C24

CFG_10

N21

CFG_11

P21

CFG_12

T21

CFG_13

R20

CFG_14

M20

CFG_15

L21

CFG_16

H21

CFG_17

P29

CFG_18

R28

CFG_19

T28

CFG_20

R29

PM_SYNC#

B7

PM_DPRSTP#

N33

PM_EXT_TS#_0

P32

PM_EXT_TS#_1

AT40

PWROK

AT11

RSTIN#

T20

THERMTRIP#

R32

DPRSLPVR

BG48

NC_1

BF48

NC_2

BD48

NC_3

BC48

NC_4

BH47

NC_5

BG47

NC_6

BE47

NC_7

BH46

NC_8

BF46

NC_9

BG45

NC_10

BH44

NC_11

BH43

NC_12

BH6

NC_13

BH5

NC_14

BG4

NC_15

BH3

NC_16

BF3

NC_17

BH2

NC_18

BG2

NC_19

BE2

NC_20

BG1

NC_21

BF1

NC_22

BD1

NC_23

BC1

NC_24

F1

NC_25

A47

NC_26

CANTI GA ES_FCBGA1329

Compal Secret Data

Deciphered Date

2

M_CLK_DD R0

AP24

SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1

SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1

SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1

SA_CS#_0
SA_CS#_1
SB_CS#_0

RSVD CFG PM NC

DDR CLK/ CONTROL/ COMPENSATIONHDA

CLKDMIGRAPHICS VIDMEMISC

SB_CS#_1

SA_ODT_0
SA_ODT_1

SB_ODT_O

SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_PWROK

SM_DRAMRST#

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

GFX_VR_EN

CL_PWROK

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

ICH_SYNC#

HDA_BCLK
HDA_RST#

HDA_SDO

HDA_SYNC

2

SM_VREF

SM_REXT

PEG_CLK

CL_CLK

CL_DATA

CL_RST#
CL_VREF

CLKREQ#

TSATN#

HDA_SDI

M_CLK_DD R1

AT21

M_CLK_DD R2

AV24

M_CLK_DD R3

AU20

M_CLK_DDR#0

AR24

M_CLK_DDR#1

AR21

M_CLK_DDR#2

AU24

M_CLK_DDR#3

AV20

DDR_CKE 0_DIMMA

BC28

DDR_CKE 1_DIMMA

AY28

DDR_CKE 2_DIMMB

AY36

DDR_CKE 3_DIMMB

BB36

DDR_C S0_DIMMA#

BA17

DDR_C S1_DIMMA#

AY16

DDR_C S2_DIMMB#

AV16

DDR_C S3_DIMMB#

AR13

M_ODT0

BD17

M_ODT1

AY17

M_ODT2

BF15

M_ODT3

AY13

SMRCOMP

BG22

SMRCOMP#

BH21

+SMRCOMP_VOH

BF28

+SMRCOMP_VOL

BH28

+V_DD R_MCH_REF

AV42
AR36

SM_REXT

BF17

TP_SM_DRAMRST#

BC36

MCH_ DREFCLK

B38

MCH_ DREFCLK#

A38

DREF_ SSCLK

E41

DREF_ SSCLK#

F41

CLK_MCH_3GPLL

F43

CLK_MCH_3GPLL#

E43

DMI_ITX_MRX_N0

AE41

DMI_ITX_MRX_N1

AE37

DMI_ITX_MRX_N2

AE47

DMI_ITX_MRX_N3

AH39

DMI_ITX_MRX_P0

AE40

DMI_ITX_MRX_P1

AE38

DMI_ITX_MRX_P2

AE48

DMI_ITX_MRX_P3

AH40

DMI_MTX_IRX_N0

AE35

DMI_MTX_IRX_N1

AE43

DMI_MTX_IRX_N2

AE46

DMI_MTX_IRX_N3

AH42

DMI_MTX_IRX_P0

AD35

DMI_MTX_IRX_P1

AE44

DMI_MTX_IRX_P2

AF46

DMI_MTX_IRX_P3

AH43

B33
B32
G33
F33
E33

C34

AH37
AH36
AN36
AJ35
AH34

N28
M28
G36
E36
K36
H36

B12

B28
B30
B29
C29
A28

T30
T31
T32
T33
T34

T35

CL_CLK0
CL_DATA0
M_PWROK
CL_RST#
+CL_VREF

CLK_3GPLLREQ#
MCH _ICH_SYNC #

TSATN#

ADC_A CZ_SDIN0_GMC H

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

M_CLK_DDR0 <16>
M_CLK_DDR1 <16>
M_CLK_DDR2 <17>
M_CLK_DDR3 <17>

M_CLK_DDR#0 <16>
M_CLK_DDR#1 <16>
M_CLK_DDR#2 <17>
M_CLK_DDR#3 <17>

DDR_CKE 0_DIMMA <16>
DDR_CKE 1_DIMMA <16>
DDR_CKE 2_DIMMB <17>
DDR_CKE 3_DIMMB <17>

DDR_CS0_D IMMA# <16>
DDR_CS1_D IMMA# <16>
DDR_CS2_D IMMB# <17>
DDR_CS3_D IMMB# <17>

M_ODT0 <16>
M_ODT1 <16>
M_ODT2 <17>
M_ODT3 <17>

R328 80.6_0402_1%

1 2

R329 80.6_0402_1%

1 2

+V_DD R_MCH_REF

R1040 499_0402_1%

1 2

T29

MCH_ DREFCLK <6>
MCH_ DREFCLK# <6>
DREF_ SSCLK <6>
DREF_ SSCLK# <6>

CLK_MCH_3GPLL <6>
CLK_MCH_3GPLL# <6>

DMI_ITX_MRX_N0 <23>
DMI_ITX_MRX_N1 <23>
DMI_ITX_MRX_N2 <23>
DMI_ITX_MRX_N3 <23>

DMI_ITX_MRX_P0 <23>
DMI_ITX_MRX_P1 <23>
DMI_ITX_MRX_P2 <23>
DMI_ITX_MRX_P3 <23>

DMI_MTX_IRX_N0 <23>
DMI_MTX_IRX_N1 <23>
DMI_MTX_IRX_N2 <23>
DMI_MTX_IRX_N3 <23>

DMI_MTX_IRX_P0 <23>
DMI_MTX_IRX_P1 <23>
DMI_MTX_IRX_P2 <23>
DMI_MTX_IRX_P3 <23>

MCH_ DREFCLK

MCH_ DREFCLK#

DREF_ SSCLK

DREF_ SSCLK#

CL_CLK0 <23>
CL_DATA0 <23>
M_PWROK <23>
CL_RST# <23>

T36

0.1U_0402_16V7K~D

T48

GMCH_ HDMICLK <20>
GMCH_HDM IDAT <20>

CLK_3GPLLREQ# <6>

MCH _ICH_SYNC# <23>

R521 56_0402_5%

GMCH_H DA_BITCLK <22>

GMCH_HDA _RST# <22>

1 2

R98 33_0402_5%~D1@

GMCH_H DA_SDOUT <22>
GMCH_ HDA_SYNC <22>

Compal Electronics, Inc.

Cantiga(1/6)-AGTL/DMI/DDR

LA-5162P

1

RG156

@

RG158

@

RG160

@

RG161

@

1

C181

2

12

1

+1.8V

1 2

0_0402_5%

1 2

0_0402_5%

1 2

0_0402_5%

1 2

0_0402_5%

+VCCP

12

R100
1K_0402_1%

0.35V

12

R99
511_0402_1%

ADC_G MCH_SDIN2 <22>

10 60Monday , April 20, 2009

0.2

5

4

3

2

1

D D

U4D

DDR_A _D0
DDR_A _D1
DDR_A _D2
DDR_A _D3
DDR_A _D4
DDR_A _D5
DDR_A _D6
DDR_A _D7
DDR_A _D8
DDR_A _D9
DDR_A _D10
DDR_A _D11
DDR_A _D12
DDR_A _D13
DDR_A _D14
DDR_A _D15
DDR_A _D16
DDR_A _D17
DDR_A _D18
DDR_A _D19
DDR_A _D20
DDR_A _D21
DDR_A _D22
DDR_A _D23
DDR_A _D24
DDR_A _D25
DDR_A _D26
DDR_A _D27

C C

B B

DDR_A _D28
DDR_A _D29
DDR_A _D30
DDR_A _D31
DDR_A _D32
DDR_A _D33
DDR_A _D34
DDR_A _D35
DDR_A _D36
DDR_A _D37
DDR_A _D38
DDR_A _D39
DDR_A _D40
DDR_A _D41
DDR_A _D42
DDR_A _D43
DDR_A _D44
DDR_A _D45
DDR_A _D46
DDR_A _D47
DDR_A _D48
DDR_A _D49
DDR_A _D50
DDR_A _D51
DDR_A _D52
DDR_A _D53
DDR_A _D54
DDR_A _D55
DDR_A _D56
DDR_A _D57
DDR_A _D58
DDR_A _D59
DDR_A _D60
DDR_A _D61
DDR_A _D62
DDR_A _D63

AJ38

SA_DQ_0

AJ41

SA_DQ_1

AN38

SA_DQ_2

AM38

SA_DQ_3

AJ36

SA_DQ_4

AJ40

SA_DQ_5

AM44

SA_DQ_6

AM42

SA_DQ_7

AN43

SA_DQ_8

AN44

SA_DQ_9

AU40

SA_DQ_10

AT38

SA_DQ_11

AN41

SA_DQ_12

AN39

SA_DQ_13

AU44

SA_DQ_14

AU42

SA_DQ_15

AV39

SA_DQ_16

AY44

SA_DQ_17

BA40

SA_DQ_18

BD43

SA_DQ_19

AV41

SA_DQ_20

AY43

SA_DQ_21

BB41

SA_DQ_22

BC40

SA_DQ_23

AY37

SA_DQ_24

BD38

SA_DQ_25

AV37

SA_DQ_26

AT36

SA_DQ_27

AY38

SA_DQ_28

BB38

SA_DQ_29

AV36

SA_DQ_30

AW36

SA_DQ_31

BD13

SA_DQ_32

AU11

SA_DQ_33

BC11

SA_DQ_34

BA12

SA_DQ_35

AU13

SA_DQ_36

AV13

SA_DQ_37

BD12

SA_DQ_38

BC12

SA_DQ_39

BB9

SA_DQ_40

BA9

SA_DQ_41

AU10

SA_DQ_42

AV9

SA_DQ_43

BA11

SA_DQ_44

BD9

SA_DQ_45

AY8

SA_DQ_46

BA6

SA_DQ_47

AV5

SA_DQ_48

AV7

SA_DQ_49

AT9

SA_DQ_50

AN8

SA_DQ_51

AU5

SA_DQ_52

AU6

SA_DQ_53

AT5

SA_DQ_54

AN10

SA_DQ_55

AM11

SA_DQ_56

AM5

SA_DQ_57

AJ9

SA_DQ_58

AJ8

SA_DQ_59

AN12

SA_DQ_60

AM13

SA_DQ_61

AJ11

SA_DQ_62

AJ12

SA_DQ_63

CANTI GA ES_FCBGA1329

DDR_A_BS #0

BD21

SA_BS_0
SA_BS_1
SA_BS_2

SA_RAS#
SA_CAS#

SA_WE#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7

SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3

DDR SYSTEM MEMORY A

SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

BG18
AT25

BB20
BD20
AY20

AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5

AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7

AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8

BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25

DDR_A_BS #1
DDR_A_BS #2

DDR_A _RAS#
DDR_A _CAS#
DDR_A_W E#

DDR_A_DM 0
DDR_A_DM 1
DDR_A_DM 2
DDR_A_DM 3
DDR_A_DM 4
DDR_A_DM 5
DDR_A_DM 6
DDR_A_DM 7

DDR_A _DQS0
DDR_A _DQS1
DDR_A _DQS2
DDR_A _DQS3
DDR_A _DQS4
DDR_A _DQS5
DDR_A _DQS6
DDR_A _DQS7

DDR_A _DQS#0
DDR_A _DQS#1
DDR_A _DQS#2

DDR_A _DQS#3

DDR_A _DQS#4
DDR_A _DQS#5
DDR_A _DQS#6
DDR_A _DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

DDR_A_BS #0 <16>
DDR_A_BS #1 <16>
DDR_A_BS #2 <16>

DDR_A _RAS# <16>
DDR_A _CAS# <16>
DDR_A_W E# <16>

DDR_A _DM[0..7] <16>

DDR_A _DQS[0..7 ] <16>

DDR_A _DQS#[0.. 7] <16>

DDR_A _MA[0..14] <16>

DDR_ B_D[0..63 ]<17>DDR_ A_D[0..63 ]<16>

DDR_B _D0
DDR_B _D1
DDR_B _D2
DDR_B _D3
DDR_B _D4
DDR_B _D5
DDR_B _D6
DDR_B _D7
DDR_B _D8
DDR_B _D9
DDR_B _D10
DDR_B _D11
DDR_B _D12
DDR_B _D13
DDR_B _D14
DDR_B _D15
DDR_B _D16
DDR_B _D17
DDR_B _D18
DDR_B _D19
DDR_B _D20
DDR_B _D21
DDR_B _D22
DDR_B _D23
DDR_B _D24
DDR_B _D25
DDR_B _D26
DDR_B _D27
DDR_B _D28
DDR_B _D29
DDR_B _D30
DDR_B _D31
DDR_B _D32
DDR_B _D33
DDR_B _D34
DDR_B _D35
DDR_B _D36
DDR_B _D37
DDR_B _D38
DDR_B _D39
DDR_B _D40
DDR_B _D41
DDR_B _D42
DDR_B _D43
DDR_B _D44
DDR_B _D45
DDR_B _D46
DDR_B _D47
DDR_B _D48
DDR_B _D49
DDR_B _D50
DDR_B _D51
DDR_B _D52
DDR_B _D53
DDR_B _D54
DDR_B _D55
DDR_B _D56
DDR_B _D57
DDR_B _D58
DDR_B _D59
DDR_B _D60
DDR_B _D61
DDR_B _D62
DDR_B _D63

U4E

AK47

SB_DQ_0

AH46

SB_DQ_1

AP47

SB_DQ_2

AP46

SB_DQ_3

AJ46

SB_DQ_4

AJ48

SB_DQ_5

AM48

SB_DQ_6

AP48

SB_DQ_7

AU47

SB_DQ_8

AU46

SB_DQ_9

BA48

SB_DQ_10

AY48

SB_DQ_11

AT47

SB_DQ_12

AR47

SB_DQ_13

BA47

SB_DQ_14

BC47

SB_DQ_15

BC46

SB_DQ_16

BC44

SB_DQ_17

BG43

SB_DQ_18

BF43

SB_DQ_19

BE45

SB_DQ_20

BC41

SB_DQ_21

BF40

SB_DQ_22

BF41

SB_DQ_23

BG38

SB_DQ_24

BF38

SB_DQ_25

BH35

SB_DQ_26

BG35

SB_DQ_27

BH40

SB_DQ_28

BG39

SB_DQ_29

BG34

SB_DQ_30

BH34

SB_DQ_31

BH14

SB_DQ_32

BG12

SB_DQ_33

BH11

SB_DQ_34

BG8

SB_DQ_35

BH12

SB_DQ_36

BF11

SB_DQ_37

BF8

SB_DQ_38

BG7

SB_DQ_39

BC5

SB_DQ_40

BC6

SB_DQ_41

AY3

SB_DQ_42

AY1

SB_DQ_43

BF6

SB_DQ_44

BF5

SB_DQ_45

BA1

SB_DQ_46

BD3

SB_DQ_47

AV2

SB_DQ_48

AU3

SB_DQ_49

AR3

SB_DQ_50

AN2

SB_DQ_51

AY2

SB_DQ_52

AV1

SB_DQ_53

AP3

SB_DQ_54

AR1

SB_DQ_55

AL1

SB_DQ_56

AL2

SB_DQ_57

AJ1

SB_DQ_58

AH1

SB_DQ_59

AM2

SB_DQ_60

AM3

SB_DQ_61

AH3

SB_DQ_62

AJ3

SB_DQ_63

CANTI GA ES_FCBGA1329

DDR_B_BS#0

BC16

SB_BS_0
SB_BS_1
SB_BS_2

SB_RAS#
SB_CAS#

SB_WE#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7

SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2

DDR SYSTEM MEMORY B

SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

BB17
BB33

AU17
BG16
BF14

AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2

AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6

AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5

AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33

DDR_B_BS #1
DDR_B_BS #2

DDR_B _RAS#
DDR_B _CAS#
DDR_B_W E#

DDR_B_DM 0
DDR_B_DM 1
DDR_B_DM 2
DDR_B_DM 3
DDR_B_DM 4
DDR_B_DM 5
DDR_B_DM 6
DDR_B_DM 7

DDR_B _DQS0
DDR_B _DQS1
DDR_B _DQS2
DDR_B _DQS3
DDR_B _DQS4
DDR_B _DQS5
DDR_B _DQS6
DDR_B _DQS7

DDR_B _DQS#0
DDR_B _DQS#1
DDR_B _DQS#2
DDR_B _DQS#3
DDR_B _DQS#4
DDR_B _DQS#5
DDR_B _DQS#6
DDR_B _DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14

DDR_B_BS #0 <17>
DDR_B_BS #1 <17>
DDR_B_BS #2 <17>

DDR_B _RAS# <17>
DDR_B _CAS# <17>
DDR_B _WE# <17>

DDR_B _DM[0..7] <17>

DDR_ B_DQS[0.. 7] <17>

DDR_B _DQS#[0.. 7] <17>

DDR_B _MA[0..14] <17>

CPN:SA00002JT3L(GM45) for Discrete and UMA

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

Cantiga(2/6)-DDR2 A/B CH

LA-5162P

1

11 60Monday , April 20, 2009

0.2

5

+3VS

R57

1@

GMCH _EDID_CLK_ LCD

1 2

2.2K_0402_5%~D
R62

1@

GMCH _EDID_DAT_LC D

D D

C C

B B

1 2

2.2K_0402_5%~D

150_0402_1%

12

1@

R75

INVT_PWM< 19,30>

+3VS

GMCH_EN BKL

R81 10K_0402_5%~D1@

R80 10K_0402_5%~D1@

GMCH _EDID_CLK_ LCD
GMCH _EDID_DAT_LC D
GMCH _LVDDEN

GMCH_LV DSAC­GMCH_LV DSAC+

GMCH_LVDSA0­GMCH_LVDSA1­GMCH_LVDSA2-

GMCH_LVDSA0+
GMCH_LVDSA1+
GMCH_LVDSA2+

GMCH_ENBKL<19>

GMCH _EDID_CLK_L CD<19>

GMCH_ EDID_DAT_LCD<19>

GMCH_ LVDDEN<19>

GMCH_LVDS AC-<19>
GMCH_LVDSAC +<19>

GMCH_LVDSA0-<19>
GMCH_LVDSA1-<19>
GMCH_LVDSA2-<19>

GMCH_LVDSA0+<19>
GMCH_LVDSA1+<19>
GMCH_LVDSA2+<19>

CRT_B
CRT_G
CRT_R

150_0402_1%

150_0402_1%

12

12

1@

1@

R74

R76

@

0_0402_5%

1 2

R119

1@

1 2

100K_0402_5%~D

1 2
1 2

R94 2.4K_0402_1%~D1@

T38

T46

R37 75_0402_5%~D
R63 75_0402_5%~D
R50 75_0402_5%~D

CRT_B<19>

CRT_G<19>

CRT_R<19>

3VDD CCL<19>
3VDD CDA<19>

CRT _HSYNC<19>

R334 1K_0402_1%1@

CRT _VSYNC<19>

R314

1 2

1 2
1 2
1 2

INVT_PW M_GMCH

GMCH_LVDSA3-

GMCH_LVDSA3+

CRT_B

CRT_G

CRT_R

3VDD CCL
3VDD CDA
CRT _HSYNC

12

CTRL_CLK
CTRL_DATA

CRT _VSYNC

4

U4C

L32

L_BKLT_CT RL

G32

L_BKLT_EN

M32

L_CTRL_C LK

M33

L_CTRL_D ATA

K33

L_DDC_CL K

J33

L_DDC_DATA

M29

L_VDD_EN

C44

LVDS_IBG

B43

LVDS_VBG

E37

LVDS_VREFH

E38

LVDS_VREFL

C41

LVDSA_CLK#

C40

LVDSA_CLK

B37

LVDSB_CLK#

A37

LVDSB_CLK

H47

LVDSA_DATA#_0

E46

LVDSA_DATA#_1

G40

LVDSA_DATA#_2

A40

LVDSA_DATA#_3

H48

LVDSA_DATA_0

D45

LVDSA_DATA_1

F40

LVDSA_DATA_2

B40

LVDSA_DATA_3

A41

LVDSB_DATA#_0

H38

LVDSB_DATA#_1

G37

LVDSB_DATA#_2

J37

LVDSB_DATA#_3

B42

LVDSB_DATA_0

G38

LVDSB_DATA_1

F37

LVDSB_DATA_2

K37

LVDSB_DATA_3

F25

TVA_DAC

H25

TVB_DAC

K25

TVC_DAC

H24

TV_RTN

C31

TV_DCONSEL_0

E32

TV_DCONSEL_1

E28

CRT_BLUE

G28

CRT_GREEN

J28

CRT_RED

G29

CRT_IRTN

H32

CRT_DDC_ CLK

J32

CRT_DDC_ DATA

J29

CRT_HSYNC

E29

CRT_TVO_IREF

L29

CRT_VSYNC

CANTIGA ES_FCBGA1329

3

R95 wi thin 500 mils from
pin T 37,T36

T37

PEG_COMPI

T36

PEG_COMPO

H44

PEG_RX#_0

J46

PEG_RX#_1

L44

PEG_RX#_2

L40

PEG_RX#_3

N41

PEG_RX#_4

P48

PEG_RX#_5

N44

PEG_RX#_6

T43

PEG_RX#_7

U43

PEG_RX#_8

Y43

PEG_RX#_9

Y48

PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

Y36
AA43
AD37
AC47
AD39

H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40

J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46

J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46

LVDS TV VGA

PCI-EXPRESS GRAPHICS

1 2

R95 49.9_0402_1%

CG568 0.1U _0402_16V7K~D2@
CG537 0.1U _0402_16V7K~D2@
CG538 0.1U _0402_16V7K~D2@
CG539 0.1U _0402_16V7K~D2@
CG540 0.1U _0402_16V7K~D2@
CG541 0.1U _0402_16V7K~D2@
CG542 0.1U _0402_16V7K~D2@
CG543 0.1U _0402_16V7K~D2@
CG544 0.1U _0402_16V7K~D2@
CG545 0.1U _0402_16V7K~D2@
CG546 0.1U _0402_16V7K~D2@
CG547 0.1U _0402_16V7K~D2@
CG548 0.1U _0402_16V7K~D2@
CG549 0.1U _0402_16V7K~D2@
CG550 0.1U _0402_16V7K~D2@
CG551 0.1U _0402_16V7K~D2@

CG552 0.1U _0402_16V7K~D2@
CG553 0.1U _0402_16V7K~D2@
CG554 0.1U _0402_16V7K~D2@
CG555 0.1U _0402_16V7K~D2@
CG556 0.1U _0402_16V7K~D2@
CG557 0.1U _0402_16V7K~D2@
CG558 0.1U _0402_16V7K~D2@
CG559 0.1U _0402_16V7K~D2@
CG560 0.1U _0402_16V7K~D2@
CG561 0.1U _0402_16V7K~D2@
CG562 0.1U _0402_16V7K~D2@
CG563 0.1U _0402_16V7K~D2@
CG564 0.1U _0402_16V7K~D2@
CG565 0.1U _0402_16V7K~D2@
CG566 0.1U _0402_16V7K~D2@
CG567 0.1U _0402_16V7K~D2@

1 2

R93 0_0402_5%1@

PEG_NRX_G TX_N[0..15] <34>

PEG_NRX_G TX_P[0..15] <34>

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

PEG_NRX_GTX_N0
PEG_NRX_GTX_N1
PEG_NRX_GTX_N2
PEG_NRX_GTX_N3
PEG_NRX_GTX_N4
PEG_NRX_GTX_N5
PEG_NRX_GTX_N6
PEG_NRX_GTX_N7
PEG_NRX_GTX_N8
PEG_NRX_GTX_N9
PEG_NRX_GTX_N10
PEG_NRX_GTX_N11
PEG_NRX_GTX_N12
PEG_NRX_GTX_N13
PEG_NRX_GTX_N14
PEG_NRX_GTX_N15

PEG_NRX_GTX_P0
PEG_NRX_GTX_P1
PEG_NRX_GTX_P2
PEG_NRX_GTX_P3
PEG_NRX_GTX_P4
PEG_NRX_GTX_P5
PEG_NRX_GTX_P6
PEG_NRX_GTX_P7
PEG_NRX_GTX_P8
PEG_NRX_GTX_P9
PEG_NRX_GTX_P10
PEG_NRX_GTX_P11
PEG_NRX_GTX_P12
PEG_NRX_GTX_P13
PEG_NRX_GTX_P14
PEG_NRX_GTX_P15

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5 PEG_NTX_C_GRX_N5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10

PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

PEG_TXP3
PEG_TXN3
PEG_TXP2
PEG_TXN2
PEG_TXP1
PEG_TXN1
PEG_TXP0
PEG_TXN0
PEG_NRX_GTX_P3

PEG COM P tr ace wi dth

+VCCP

and sp aci ng i s 20/ 25 mils.

PEG_NTX_C_GRX_N0
PEG_NTX_C_GRX_N1
PEG_NTX_C_GRX_N2
PEG_NTX_C_GRX_N3
PEG_NTX_C_GRX_N4

PEG_NTX_C_GRX_N6
PEG_NTX_C_GRX_N7
PEG_NTX_C_GRX_N8

PEG_NTX_C_GRX_N9
PEG_NTX_C_GRX_N10
PEG_NTX_C_GRX_N11PEG_TXN11
PEG_NTX_C_GRX_N12
PEG_NTX_C_GRX_N13
PEG_NTX_C_GRX_N14
PEG_NTX_C_GRX_N15

PEG_NTX_C_GRX_P0

PEG_NTX_C_GRX_P1

PEG_NTX_C_GRX_P2

PEG_NTX_C_GRX_P3

PEG_NTX_C_GRX_P4

PEG_NTX_C_GRX_P5

PEG_NTX_C_GRX_P6

PEG_NTX_C_GRX_P7

PEG_NTX_C_GRX_P8

PEG_NTX_C_GRX_P9
PEG_NTX_C_GRX_P10
PEG_NTX_C_GRX_P11
PEG_NTX_C_GRX_P12
PEG_NTX_C_GRX_P13
PEG_NTX_C_GRX_P14
PEG_NTX_C_GRX_P15

PEG_TXP3 <20>
PEG_TXN3 <20>
PEG_TXP2 <20>
PEG_TXN2 <20>
PEG_TXP1 <20>
PEG_TXN1 <20>
PEG_TXP0 <20>
PEG_TXN0 <20>

HDMI_ HPD# <20>

2

PEG_NTX_ C_GRX_N[0..15] <34>

PEG_NTX_ C_GRX_P[0..15] <34>

Only For HDMI

Strap Pin Table

CFG[2: 0] FSB Freq select

CFG[4:3]

CFG5 ( DMI select)

CFG6

CFG 7 (Intel M anagement
Eng ine Crypto strap)

CFG8

CFG9

(PCIE Graphics La ne Reversal)

CFG10 (PCIE Lookb ack enable)

CFG11

CFG[13:12] (XOR/ALLZ)

CFG[15:14]

CFG16 (FSB Dynamic ODT)

CFG[18:17]

CFG19 (DMI L ane Reversal)

CFG20 (PCIE/SDVO con current)

R66 2.21K_0402_1%~D@

CFG5<10>

R1058 2.21K_0402_1%~D@

CFG6<10>

R59 2.21K_0402_1%~D@

CFG7<10>

R55 2.21K_0402_1%~D@

CFG9<10>

R70 2.21K_0402_1%~D@

CFG16<10>

CFG[5:16] have internal pull-up

R72 4.02K_0402_1%~D@

CFG19<10>

R73 4.02K_0402_1%~D@

CFG20<10>

1

000 = FSB 1066MHz
010 = FSB 800MHz
011 = FSB 667MHz
Others = Reserved

Reserved

0 = DMI x 2
1 = DMI x 4
0 = The iTPM Host Interface is enable

1 = The iTPM Host Interface is disable

0 =(TLS)chiper suite with no confidentiality

1 =(TLS)chiper suite with confidentiality

*

*

Reserved

0 = R everse Lane,15->0, 14->1

1 = Normal Operation,Lane Number in order

0 = Enable

1 = Disable

*

Reserved

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled

Reserved

0 = Disabled

1 = Enabled

Reserved

0 = Normal Operation
(Lane number in Order)

1 = Reverse Lane

0 = Only PCIE or SDVO is operational.

1 = PCIE/SDVO are operating simu.

1 2

1 2

1 2

1 2

1 2

1 2

1 2

(Default)11 = Normal Operation

*

*

+3VS

*

*

*

*

*

CFG[19:20] have internal pull-down

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Cantiga(3/6)-VGA/LVDS/TV

Size Doc ument Num ber R ev

Cust om

LA -5 162 P

2

Date: Sheet o f

1

12 60Monday, Apr il 20, 20 09

0.2

5

+VCCP +1.05VS_DPLLA

D D

10U_FLC-453232-1 00K_0.25A_10%

+VCCP +1.05VS_MPLL

1 2

0.15 UH_LQH32CNR15M33L_20%_1210 ~D

C C

+VCCP

B B

+1.5VS

BLM18PG181SN1_0 603~D

A A

L13

10U_FLC-453232-1 00K_0.25A_10%

L9

BLM21PG221SN1D_0 805~D

1 2

12

+1.05VS_DP LLB

L14

12

C174

R132

1 2

0_0402_5%

C29

1 2

22U_0805_6.3VAM

40 mils

1@

0_0603_5%

L12

12

R137

1 2

1_0402_5%~D

C179

1 2

10U_0805_10V4 Z~D

R64

1@

12

0_0805_5%

0.1U_0402_16V7K~D

L3

0.1U_0402_16V7K~D

1

2

+1.8V_TXLVDS+1.8VS

R350

12

1@

C413

+1.5VS_TV DAC

1@

1

C114

2

+1.5VS_QDA C

1

C98

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

+

C27

2

0.1U_0402_16V7K~D

1

2

1000P_0402_50V7K~D

0_0402_5%

1

2

+1.05VS_PEGPLL

C176

0.01U_0402_16V7K

1@

1

C30

2

0.01U_0402_16V7K

1

C97

2

1

2

C173

220U_ D2_4VY_R15M

0_0402_5%

C63

12

1

2

0_0402_5%

+3VS_DA C_CRT

1

+

C191

2

12

@

RG165

2@

RG22

0.1U_0402_16V7K~D

+3VS_DA C_CRT

2@

12

RG102

4

1@

0_0402_5%

220U_ D2_4VY_R15M

0_0402_5%

12

@

RG164

MBK2012121YZF _0805

12

1@

0_0603_5%~D

0.01U_0402_16V7K

1@

1@

1

C402

C401

2

+1.05VS_HPLL

R836

12

0.1U_0402_16V7K~D

L29

+1.5VS

R79

0.1U_0402_16V7K~D

1

2

0.1U_0402_16V7K~D

+3VS

1@

BLM18PG181SN1_0 603~D

+3VS_DAC_BG

0.01U_0402_16V7K

1@

1

1

C408

2

2

+1.05VS_HPLL+VCCP

12

4.7U_0603_10V6K

2

C28

1

1

C175

0.1U_0402_16V 7K~D

2

+VCCP

100U_D2E_6.3VM_R18M~D

1

2

2@

0_0402_5%

12

+1.5VS

RG134

0_0402_5%

1 2

0.1U_0402 _16V4Z

1

2

+1.05VS_PEGPLL

1

C33

2

0_0402_5%

1@

C405

0.1U_0402_16V7K~D

+

C31

1@

R67

1@

C1413

L11

12

12

2@

RG13

C388

1

2

+1.05VS_PEGPLL

22U_0805_6.3V6M~D

1

2

R86 0_0402_5%2@

+1.5VS_TV DAC

+1.5VS_Q DAC

0.1U_0402_16V7K~D

2

1

+1.8VS

+3VS_DAC_CRT

0.1U_0402_16V7K~D

1

2

+1.05VS_HPLL

+1.05VS_MPLL

+1.8V_TXLVDS

4.7U_0805 _10V4Z~D

1

C82

C83

2

22U_0805_6.3V6M~D

1

C123

C104

2

1 2

C233

+1.8V_LVDS

R110

1@

0_0603_5%

0.01U_0402_16V7K

1@

1@

1

C411

C407

2

2.6 8mA

64. 8mA

64. 8mA

139 .2m A

13. 2mA

414 uA

720 mA

1U_0603_10V6K~D

1

C72

2

0.1U_0402_16V7K~D

1

2

TVA 24 .15 mA
TVB 39 .48 mA
TVX 24 .15 mA

50 mA

58. 67m A

48. 363 mA

157 .2m A

50 mA

60. 31m A

12

1@

1U_0603_10V6K~D

0_0603_5%~D

1

C186

2

24 mA

50 mA

26 mA

0_0402_5%

73 mA

12

2@

RG162

12

AD48

AA48

AR20

AP20
AN20
AR17

AP17
AN17

AT16
AR16

AP16

AP28
AN28

AP25
AN25
AN24
AM28
AM26
AM25

AL25
AM24

AL24
AM23

AL23

AA47

3

2@

RG7

U4H

B27

VCCA_CRT_DAC_1

A26

VCCA_CRT_DAC_2

A25

VCCA_DAC_BG

B25

VSSA_DAC_BG

F47

VCCA_DPLLA

L48

VCCA_DPLLB

AD1

VCCA_HPLL

AE1

VCCA_MPLL

J48

VCCA_LVDS

J47

VSSA_LVDS

VCCA_PEG_BG

VCCA_PEG_PLL

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_6
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9

VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_SM_CK_3
VCCA_SM_CK_4
VCCA_SM_CK_5
VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2
VCCA_SM_CK_NCTF_3
VCCA_SM_CK_NCTF_4
VCCA_SM_CK_NCTF_5
VCCA_SM_CK_NCTF_6
VCCA_SM_CK_NCTF_7
VCCA_SM_CK_NCTF_8

B24

VCCA_TV_DAC_1

A24

VCCA_TV_DAC_2

A32

VCC_HDA

M25

VCCD_TVDAC

L28

VCCD_QDAC

AF1

VCCD_HPLL

VCCD_PEG_PLL

M38

VCCD_LVDS_1

L37

VCCD_LVDS_2

CANTIGA E S_FCBGA1329

POWER

HDA

A SM

LVDS D TV/CRT

CRTPLLA LVDSA PEG

TV

VTT

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

AXF

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

VCC_TX_LVDS

A CK

HV

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5

VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4

DMI PEG

VTTLF

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8

VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25

VCC_HV_1
VCC_HV_2
VCC_HV_3

VTTLF1
VTTLF2
VTTLF3

U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1

B22
B21
A21

BF21
BH20
BG20
BF20

K47

C35
B35
A35

V48
U48
V47
U47
U46

AH48
AF48
AH47
AG47

A8
L1
AB2

456 mA

852 mA

321 .35 mA

124 mA

118 .8m A

173 2mA

20mils

+VTTLF1
+VTTLF2
+VTTLF3

0.47U_0402_10V4Z~D

C382

4.7U_0805 _10V4Z~D

1

C384

2

+1.8V_TXLVDS

105 .3m A

0.47U_0402_10V4Z~D

C385

1

2

1

2

C383

+VCCP

10U_0805_10V4Z~D

C65

2

0.47U_040 2_10V4Z~D

1

2

@

C113

1

2

+1.8V_SM_CK

1_0402_5%~D

C96

0.1U_0402_16V7K~D

1

2

0.47U_0402_10V4Z~D

1

2

4.7U_0805 _10V4Z~D

1

1

C373

C56

2

2

1U_0603_10V6K~D

C69

1

2

1UH_L QM21FN1R0N00D_30%_0805~ D

R139

0.1U_0402_16V7K~D

1

C102

10U_0805_10V4Z~D

1

2

2

+VCCP

220U_ D2_4VY_R15M

22U_0805_6.3V6M~D

1

2

+

C116

C95

C117

2

1

+VCCP

2.2U_0805 _16V4Z

C370

1 2

4.7U_0805 _10V4Z~D

1

2

1

220U_ D2_4VY_R15M

1

+

2

+1.8V

L4

+3VS

0.1U_0402_16V7K~D

1

C410

2

C389

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

2

Title

Size D ocumen t Number Re v

Cust om

Date : Sheet o f

Compal Electronics, Inc.

Cantiga(4/6)-PWR

LA -5 16 2P

1

13 60Monday, A pril 20, 200 9

0.2

5

Extnal Graphic: 1210.34mA
integrated Graphic: 1930.4mA

U4G

AG34

VCC_1

AC34

VCC_2

AB34

VCC_3

AA34

VCC_4

Y34

VCC_5

V34

D D

+VCCP

220U_ D2_4VY_R15M

22U_0805_6.3V6M~D

1

+

C374

2

C C

B B

A A

0.22U_0402_10V4 Z

0.22U_0402_10V4 Z

C118

1

2

0.1U_0402_16V7K~D

C119

C143

1

2

C120

1

1

2

2

VCC_6

U34

VCC_7

AM33

VCC_8

AK33

VCC_9

AJ33

VCC_10

AG33

VCC_11

AF33

VCC_12

AE33

VCC_13

AC33

VCC_14

AA33

VCC_15

Y33

VCC_16

W33

VCC_17

V33

VCC_18

U33

VCC_19

AH28

VCC_20

AF28

VCC_21

AC28

VCC_22

AA28

VCC_23

AJ26

VCC_24

AG26

VCC_25

AE26

VCC_26

AC26

VCC_27

AH25

VCC_28

AG25

VCC_29

AF25

VCC_30

AG24

VCC_31

AJ23

VCC_32

AH23

VCC_33

AF23

VCC_34

T32

VCC_35

CANTI GA ES_FCBGA1329

VCC CORE

POWER

VCC NCTF

4

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8

VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44

AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23

+VCCP

3

+1.8V

330U_ D2_2.5VY_R9M

1

C148

+

2

Co-Layout Component

Location

0_0805_5%~D

12

C80
RG163

+1.05V_VCCP

0.47U_0402_10V4 Z~D

1U_0603_10V6K~D

@

1

C140

RG163

2

Layout Note: Inside GMCH
cavity for VCC_AXG.

0.1U_0402_16V7K~D

1

1

C78

2

2

2

U4F

3000mA

0.1U_0402_16V7K~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

C147

C165

1

1

2

2

6326. 84mA

22U_0805_6.3V6M~D

10U_0805_10V4Z~D

0.1U_0402_16V7K~D

C66

1

1

1

C79

C100

2

2

2

T42
T43

AP33

VCC_SM_1

AN33

VCC_SM_2

BH32

VCC_SM_3

BG32

VCC_SM_4

BF32

C164

2

1

C80

BD32
BC32
BB32
BA32
AY32

AW32

AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29

AW29

AV29
AU29
AT29
AR29
AP29

BA36
BB24
BD16

BB21
AW16
AW13

AT13

AE25

AB25

AA25

AE24

AC24

AA24

AE23

AC23

AB23

AA23

AJ21
AG21
AE21
AC21
AA21

AH20
AF20
AE20
AC20
AB20
AA20

AM15

AL15
AE15

AJ15
AH15
AG15
AF15
AB15
AA15

AN14
AM14

AJ14
AH14

Y26

Y24

Y21

T17
T16

Y15
V15

U15

U14

T14

VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35

VCC_SM_36/NC
VCC_SM_37/NC
VCC_SM_38/NC
VCC_SM_39/NC
VCC_SM_40/NC
VCC_SM_41/NC
VCC_SM_42/NC

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42

VCC_AXG_SENSE
VSS_AXG_SENSE

VCC_AXG_NTCF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC SM

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43

VCC GFX NCTF

VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52

POWER

VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60

VCC GFX

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16

AV44
BA37
AM40
AV21
AY5
AM10
BB13

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

VCC SM LF

CANTI GA ES_FCBGA1329

+1.05V_VCCP +VCCP

330U_ D2_2.5VY_R9M

1

1

C86

+

+

2

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.22U_0603_10V7K

1

1

C71

C70

2

2

1

PJP21

JUMP_43X118

2

Short

PJP24

JUMP_43X118

2

Short

112

112

330U_ D2_2.5VY_R9M

C57

Layout Note:

Place close to GMCH

0.22U_0603_10V7K

0.47U_0402_10V4 Z~D
C146

1

1

C67

2

1

C81

2

2

1U_0603_10V6K~D

1U_0603_10V6K~D

1

1

C145

C163

2

2

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

Title

Cantiga(5/6)-PWR/GND

Size Doc ument Number Re v

Cus tom

LA-5162P

2

Date: Sheet

1

0.2

of

14 60Monday , April 20, 2009

Compal Electronics, Inc.

5

U4I

AU48

VSS_1

AR48

VSS_2

AL48

VSS_3

BB47

VSS_4

AW47

VSS_5

AN47

VSS_6

AJ47

VSS_7

AF47

D D

C C

B B

A A

VSS_8

AD47

VSS_9

AB47

VSS_10

Y47

VSS_11

T47

VSS_12

N47

VSS_13

L47

VSS_14

G47

VSS_15

BD46

VSS_16

BA46

VSS_17

AY46

VSS_18

AV46

VSS_19

AR46

VSS_20

AM46

VSS_21

V46

VSS_22

R46

VSS_23

P46

VSS_24

H46

VSS_25

F46

VSS_26

BF44

VSS_27

AH44

VSS_28

AD44

VSS_29

AA44

VSS_30

Y44

VSS_31

U44

VSS_32

T44

VSS_33

M44

VSS_34

F44

VSS_35

BC43

VSS_36

AV43

VSS_37

AU43

VSS_38

AM43

VSS_39

J43

VSS_40

C43

VSS_41

BG42

VSS_42

AY42

VSS_43

AT42

VSS_44

AN42

VSS_45

AJ42

VSS_46

AE42

VSS_47

N42

VSS_48

L42

VSS_49

BD41

VSS_50

AU41

VSS_51

AM41

VSS_52

AH41

VSS_53

AD41

VSS_54

AA41

VSS_55

Y41

VSS_56

U41

VSS_57

T41

VSS_58

M41

VSS_59

G41

VSS_60

B41

VSS_61

BG40

VSS_62

BB40

VSS_63

AV40

VSS_64

AN40

VSS_65

H40

VSS_66

E40

VSS_67

AT39

VSS_68

AM39

VSS_69

AJ39

VSS_70

AE39

VSS_71

N39

VSS_72

L39

VSS_73

B39

VSS_74

BH38

VSS_75

BC38

VSS_76

BA38

VSS_77

AU38

VSS_78

AH38

VSS_79

AD38

VSS_80

AA38

VSS_81

Y38

VSS_82

U38

VSS_83

T38

VSS_84

J38

VSS_85

F38

VSS_86

C38

VSS_87

BF37

VSS_88

BB37

VSS_89

AW37

VSS_90

AT37

VSS_91

AN37

VSS_92

AJ37

VSS_93

H37

VSS_94

C37

VSS_95

BG36

VSS_96

BD36

VSS_97

AK15

VSS_98

AU36

VSS_99

CANTI GA ES_FCBGA1329

CIS Link:OK

VSS

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199

4

AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6

3

U4J

BG21

VSS_199

L12

VSS_200

AW21

VSS_201

AU21

VSS_202

AP21

VSS_203

AN21

VSS_204

AH21

VSS_205

AF21

VSS_206

AB21

VSS_207

R21

VSS_208

M21

VSS_209

J21

VSS_210

G21

VSS_211

BC20

VSS_212

BA20

VSS_213

AW20

VSS_214

AT20

VSS_215

AJ20

VSS_216

AG20

VSS_217

Y20

VSS_218

N20

VSS_219

K20

VSS_220

F20

VSS_221

C20

VSS_222

A20

VSS_223

BG19

VSS_224

A18

VSS_225

BG17

VSS_226

BC17

VSS_227

AW17

VSS_228

AT17

VSS_229

R17

VSS_230

M17

VSS_231

H17

VSS_232

C17

VSS_233

BA16

VSS_235

AU16

VSS_237

AN16

VSS_238

N16

VSS_239

K16

VSS_240

G16

VSS_241

E16

VSS_242

BG15

VSS_243

AC15

VSS_244

W15

VSS_245

A15

VSS_246

BG14

VSS_247

AA14

VSS_248

C14

VSS_249

BG13

VSS_250

BC13

VSS_251

BA13

VSS_252

AN13

VSS_255

AJ13

VSS_256

AE13

VSS_257

N13

VSS_258

L13

VSS_259

G13

VSS_260

E13

VSS_261

BF12

VSS_262

AV12

VSS_263

AT12

VSS_264

AM12

VSS_265

AA12

VSS_266

J12

VSS_267

A12

VSS_268

BD11

VSS_269

BB11

VSS_270

AY11

VSS_271

AN11

VSS_272

AH11

VSS_273

Y11

VSS_275

N11

VSS_276

G11

VSS_277

C11

VSS_278

BG10

VSS_279

AV10

VSS_280

AT10

VSS_281

AJ10

VSS_282

AE10

VSS_283

AA10

VSS_284

M10

VSS_285

BF9

VSS_286

BC9

VSS_287

AN9

VSS_288

AM9

VSS_289

AD9

VSS_290

G9

VSS_291

B9

VSS_292

BH8

VSS_293

BB8

VSS_294

AV8

VSS_295

AT8

VSS_296

CANTI GA ES_FCBGA1329

VSS

VSS N CTF

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16

VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5

VSS S CB

NC

2

VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325

VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350

VSS_351
VSS_352
VSS_353
VSS_354

NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42

AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4

BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1

U24
U28
U25
U29

AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17

BH48
BH1
A48
C1
A3

E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48

1

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

Cantiga(6/6)-PWR/GND

LA-5162P

1

15 60Monday , April 20, 2009

0.2

5

D D

Lay out No te:
Pl ac e ne ar J DIM MA

+1.8V

2.2U_0603_6.3V6K~ D

C105

1

2

C C

Lay out No te:
Pl ac e one c ap cl ose to e very 2 pul lup
res is tor s t er mina ted to +0. 9V

+0.9VS

0.1U_0402_16V7K~D

1

C106

2

B B

A A

2.2U_0603_6.3V6K~ D

1

2

0.1U_0402_16V7K~D

1

C125

2

2.2U_0603_6.3V6K~ D

C149

C124

1

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

1

C126

2

2

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

DDR_C S0_DIMMA#
DDR_A _RAS#

DDR_A_MA10
DDR_A_BS #0

DDR_A_W E#
DDR_A _CAS#

M_ODT1
DDR_C S1_DIMMA#

DDR_CKE 1_DIMMA

5

2.2U_0603_6.3V6K~ D

2.2U_0603_6.3V6K~ D

C166

1

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

C127

C150

2

La yout Note :
Pl ac e th es e r esi stor
cl osel y J DIM MA,a ll
tr ace len gth Max= 1.5"

RP14

1 4
2 3

56_0404_4P2R_5%

RP13

1 4
2 3

RP7

56_0404_4P2R_5%

1 4
2 3

RP6

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

RP5

1 4
2 3

56_0404_4P2R_5%

RP1

2 3
1 4

56_0404_4P2R_5%

1 2

R96 56_0402_ 5%

1

2

1

2

C169

C151

+0.9VS

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

C154

1

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

1

C167

2

2

RP22 56_0404_4P2R_5%

14
23

RP17 56_0404_4P2R_5%

14
23

RP15 56_0404_4P2R_5%

14
23

RP16 56_0404_4P2R_5%

14
23

RP8 56_0404_4P2R_5%

14
23

RP2 56_0404_4P2R_5%

14
23

RP23 56_0404_4P2R_5%

14
23

C131

1

2

0.1U_0402_16V7K~D

C107

DDR_CKE 0_DIMMA
DDR_A_BS #2

DDR_A_MA6
DDR_A_MA7

DDR_A_MA12
DDR_A_MA9

DDR_A_MA2
DDR_A_MA4

DDR_A_BS #1
DDR_A_MA0

DDR_A_MA13
M_ODT0

DDR_A_MA11
DDR_A_MA14

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

C128

2

C108

C130

1

1

2

2

0.1U_0402_16V7K~D

1

1

C129

C152

2

2

4

Close to VREF pins of SO-DIMM

+V_DD R_MCH_REF

0.1U_0402_16V7K~D

2.2U_0805_16V4Z

1

1

C201

2

2

330U_ D2_2.5VY_R9M

1

@

C84

+

2

DDR_C KE0_DIMMA<10>

DDR_A_BS #2<11>

DDR_A_BS #0<11>
DDR_A_W E#<11>

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

2

1

1

C153

C22

C168

2

2

4

DDR_A _CAS#<11>

DDR_C S1_DIMMA#<10>

M_ODT1<10>

ICH_SM_DA<6,17, 23,27,28>
ICH_SM_CLK<6,17, 23,27,28>

+3VS

C58

0.1U_0402_16V7K~D

3

+1.8V +1.8V

ME@

JDIMMA

C220

DDR_A _D0
DDR_A _D1

DDR_A _DQS#0
DDR_A _DQS0

DDR_A _D2
DDR_A _D3

DDR_A _D8
DDR_A _D9

DDR_A _DQS#1
DDR_A _DQS1

DDR_A _D10
DDR_A _D11

DDR_A _D16
DDR_A _D17

DDR_A _DQS#2
DDR_A _DQS2

DDR_A _D19

DDR_A _D24
DDR_A _D25

DDR_A_DM 3

DDR_A _D26
DDR_A _D27

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10

DDR_A _D32
DDR_A _D33

DDR_A _DQS#4
DDR_A _DQS4

DDR_A _D34
DDR_A _D35

DDR_A _D40
DDR_A _D41

DDR_A_DM 5

DDR_A _D42
DDR_A _D43

DDR_A _D48
DDR_A _D49

DDR_A _DQS#6
DDR_A _DQS6

DDR_A _D50
DDR_A _D51

DDR_A _D56
DDR_A _D57

DDR_A_DM 7

DDR_A _D58
DDR_A _D59

1

2

1

2

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

C59

2.2U_06 03_6.3V6K~D

TYCO_292526-4

SO-DIMM A

STANDARD TYPE

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

BA1
RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SA0

SA1

2

DDR_A _D4

4

DDR_A _D5

6
8

DDR_A_DM 0

10
12

DDR_A _D6

14

DDR_A _D7

16
18

DDR_A _D12

20

DDR_A _D13

22
24

DDR_A_DM 1

26
28
30
32
34

DDR_A _D14

36

DDR_A _D15

38
40

42

DDR_A _D20

44

DDR_A _D21

46
48
50

NC

A11

A7
A6

A4
A2
A0

S0#

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_DM 2

DDR_A _D22DDR_A _D18
DDR_A _D23

DDR_A _D28
DDR_A _D29

DDR_A _DQS#3
DDR_A _DQS3

DDR_A _D30
DDR_A _D31

DDR_A_MA14

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_MA13

DDR_A _D36
DDR_A _D37

DDR_A_DM 4

DDR_A _D38
DDR_A _D39

DDR_A _D44
DDR_A _D45

DDR_A _DQS#5
DDR_A _DQS5

DDR_A _D46
DDR_A _D47

DDR_A _D52
DDR_A _D53

DDR_A_DM 6

DDR_A _D54
DDR_A _D55

DDR_A _D60
DDR_A _D61

DDR_A _DQS#7
DDR_A _DQS7

DDR_A _D62
DDR_A _D63

CIS Link:OK 12/29

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

2

M_CLK_DD R0 <10>
M_CLK_DD R#0 <10>

PM_EXTTS#0 <10>

DDR_C KE1_DIMMA <10>

DDR_A_BS #1 <11>
DDR_A _RAS# <11>
DDR_C S0_DIMMA# <10>

M_ODT0 <10>

M_CLK_DD R1 <10>
M_CLK_DD R#1 <10>

12

12

R32

R31

10K_0402_5%~D

10K_0402_5%~D

2

1

DDR_A _DQS#[0.. 7] <11>

DDR_ A_D[0..63 ] <11>

DDR_A _DM[0..7] <11>

DDR_A _DQS[0..7 ] <11>

DDR_A _MA[0..14] <11>

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

DDR2 SO-DIMM A

LA-5162P

1

16 60Monday , April 20, 2009

0.2

5

4

3

2

1

Close to VREF pins of SO-DIMM

+1.8V

ME@

JDIMMB

2.2U_0805_16V4Z

0.1U_0402_16V7K~D

1

1

C225

C226

2

2

D D

Lay out No te:
Pl ac e ne ar J DIM MB

+1.8V

2.2U_06 03_6.3V6K~D

C160

1

2

0.1U_0402_16V7K~D

1

1

2

2

C135

C156

DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS #0

DDR_B_BS #1
DDR_B_MA0

DDR_C S2_DIMMB#
DDR_B _RAS#

DDR_B _CAS#
DDR_B_W E#

M_ODT3
DDR_C S3_DIMMB#

DDR_CKE 3_DIMMB

5

2.2U_06 03_6.3V6K~D

2.2U_06 03_6.3V6K~D

C138

1

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

2

C157

La yout Note :
Pl ac e th es e r esi stor
cl osel y J DIMMB, all
tr ace len gth Max= 1.5"

RP18

1 4
2 3

RP10

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

RP12

1 4
2 3

RP11

56_0404_4P2R_5%

1 4
2 3

RP9

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

RP3

2 3
1 4

56_0404_4P2R_5%

1 2

R335 56_04 02_5%

C177

1

2

0.1U_0402_16V7K~D

1

1

2

2

C170

C171

+0.9VS

C132

C109

1

1

2

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

2

C111

RP24 56_0404_4P2R_5%

14
23

RP26 56_0404_4P2R_5%

14
23

RP19 56_0404_4P2R_5%

14
23

RP21 56_0404_4P2R_5%

14
23

RP20 56_0404_4P2R_5%

14
23

RP4 56_0404_4P2R_5%

14
23

RP25

14
23

56_0404_4P2R_5%

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

2.2U_06 03_6.3V6K~D

2.2U_06 03_6.3V6K~D

C C

Lay out No te:
Pl ac e one c ap cl ose to e very 2 pul lup
res is tor s t er min ated to + 0.9VS

+0.9VS

0.1U_0402_16V7K~D

B B

A A

C139

C112

1

1

2

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

1

2

2

C134

C110

0.1U_0402_16V7K~D

C133

1

2

0.1U_0402_16V7K~D

1

1

2

2

C136

C158

DDR_B_MA12
DDR_B_MA9

DDR_B_MA11
DDR_B_MA14

DDR_B_MA8
DDR_B_MA5

DDR_B_MA6
DDR_B_MA7

DDR_B_MA2
DDR_B_MA4

DDR_B_MA13
M_ODT2

DDR_CKE 2_DIMMB
DDR_B_BS #2

0.1U_0402_16V7K~D

330U_ D2_2.5VY_R9M

1

@

C155

C189

1

+

2

2

DDR_CKE 2_DIMMB<10>

DDR_B_BS #2<11>

DDR_B_BS #0<11>

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

1

1

2

2

C137

2

C172

C159

4

DDR_B _WE#<11>

DDR_B _CAS#<11>
DDR_C S3_DIMMB#<10>

M_ODT3<10>

ICH_SM_DA<6,16, 23,27,28>
ICH_SM_CLK<6,16, 23,27,28>

0.1U_0402_16V7K~D

+3VS

DDR_B _D2

DDR_B _DQS#0
DDR_B _DQS0

DDR_B _D6
DDR_B _D7

DDR_B _D8
DDR_B _D9

DDR_B _DQS#1
DDR_B _DQS1

DDR_B _D10
DDR_B _D11

DDR_B _D16
DDR_B _D17

DDR_B _DQS#2
DDR_B _DQS2

DDR_B _D18
DDR_B _D19

DDR_B _D24
DDR_B _D25

DDR_B_DM 3

DDR_B _D27

DDR_B_MA12
DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10

DDR_B _D32
DDR_B _D33

DDR_B _DQS#4
DDR_B _DQS4

DDR_B _D34
DDR_B _D35

DDR_B _D40
DDR_B _D41

DDR_B_DM 5

DDR_B _D42
DDR_B _D43

DDR_B _D48
DDR_B _D49

DDR_B _DQS#6
DDR_B _DQS6

DDR_B _D50
DDR_B _D51

DDR_B _D56

DDR_B_DM 7

DDR_B _D58
DDR_B _D59

1

1

C61

2

C60

2.2U_06 03_6.3V6K~D

2

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

TYCO_292526-4

NC/CKE1

NC/A15
NC/A14

NC/A13

81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

SO-DIMM B

STANDARD TYPE

CIS Link:OK 12/29

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.8V+V_DD R_MCH_REF

2

VSS
DQ4
DQ5

VSS
DM0

VSS
DQ6
DQ7

VSS

DQ12
DQ13

VSS
DM1

VSS

CK0

CK0#

VSS

DQ14
DQ15

VSS

VSS

DQ20
DQ21

VSS

NC

DM2

VSS

DQ22
DQ23

VSS

DQ28
DQ29

VSS

DQS3#

DQS3

VSS

DQ30
DQ31

VSS

VDD

VDD

A11

A7
A6

VDD

A4
A2
A0

VDD

BA1

RAS#

S0#

VDD

ODT0

VDD

NC

VSS

DQ36
DQ37

VSS
DM4

VSS

DQ38
DQ39

VSS

DQ44
DQ45

VSS

DQS5#

DQS5

VSS

DQ46
DQ47

VSS

DQ52
DQ53

VSS

CK1

CK1#

VSS
DM6

VSS

DQ54
DQ55

VSS

DQ60
DQ61

VSS

DQS7#

DQS7

VSS

DQ62
DQ63

VSS

SA0

SA1

2009/01/05 2009/01/05

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_B _D1
DDR_B _D4DDR_B _D3

DDR_B_DM 0

DDR_B _D5
DDR_B _D0

DDR_B _D12
DDR_B _D13

DDR_B_DM 1

M_CLK_DD R2 <10>

DDR_B _D14
DDR_B _D15

DDR_B _D20
DDR_B _D21

DDR_B_DM 2

DDR_B _D22
DDR_B _D23

DDR_B _D28
DDR_B _D29

DDR_B _DQS#3
DDR_B _DQS3

DDR_B _D30DDR_B _D26
DDR_B _D31

DDR_B_MA14

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_MA13

DDR_B _D36
DDR_B _D37

DDR_B_DM 4

DDR_B _D38
DDR_B _D39

DDR_B _D44
DDR_B _D45

DDR_B _DQS#5
DDR_B _DQS5

DDR_B _D46
DDR_B _D47

DDR_B _D52
DDR_B _D53

DDR_B_DM 6

DDR_B _D54
DDR_B _D55

DDR_B _D60
DDR_B _D61DDR_B _D57

DDR_B _DQS#7
DDR_B _DQS7

DDR_B _D62
DDR_B _D63

M_CLK_DDR#2 <10>

PM_EXTTS#1 <10>

DDR_CKE 3_DIMMB <10>

DDR_B_BS #1 <11>
DDR_B _RAS# <11>
DDR_CS2_D IMMB# <10>

M_ODT2 <10>

M_CLK_DD R3 <10>
M_CLK_DDR#3 <10>

10K_0402_5%~D

Compal Secret Data

Deciphered Date

R33

1 2

12

10K_0402_5%~D

R34

+3VS

2

DDR_B _DQS#[0.. 7] <11>

DDR_ B_D[0..63 ] <11>

DDR_B _DM[0..7] <11>

DDR_ B_DQS[0.. 7] <11>

DDR_B _MA[0..14] <11>

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

DDR2 SO-DIMM B

LA-5162P

1

17 60Monday , April 20, 2009

0.2