COMPAL LA-5162P Schematic

A

B

C

D

E

Compal Model Name:

KAM01(DIS)
KAM00(UMA)

PCB NO:

BOM P/N:

1 1

DA80000E800 LA-5162P R02(X01)(DIS & UMA)

46170431L11 (DIS)
46170431L01 (UMA)

Liver-Pool 13.3"

Compal Confidential

2 2

Schematic Document

Penryn + Cantiga(GM45) + ICH9-M

2009 / 04 / 20

Rev:0.2(X01)

@ : Nopop Component

3 3

1@ : UMA Only
2@ : Discrete Only

ME@ : Mechanical Component

Main-Board TYPE

DIS M/B
UMA M/B

4 4

A

B

BOM P/N

46170431L11
46170431L01

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BOM CONFIGURATION

2@+ME@
1@+ME@

2009/01/05 2009/01/05

C

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

LA-5162P

E

1 60Monday, A pril 20, 2009

0.2

A

B

C

D

E

Block Diagram
Compal confidential
Model : KAM00 LA-5162P (UMA)

KAM01 LA-5162P (DIS)

1 1

Discrete Only

DDR2

+1.8VS

64MX16

512 MB

DDR2

+1.8VS

64MX16

CRT CONN

+5VS

2 2

LVDS CONN

+B+
+3VS
+LCDVDD

HDMI CONN

+3VS

CardReader

OZ888GS0L3N

3 3

+3.3VS

page 19

page 19

page 20

3 in 1 CONN

+3VS_CR

page 27

page 27

Giga LAN

RTL8111DL

+3VALW
+LAN_IO
+LAN_VDD

M92-S2-LP

+1.8VS

+VGA_CO RE

+3VS_DE LAY

+1.1V S_GFX_PCIE

PCI Express BUS

page 26

page 34 ~39

PCIE-E 16X

RG B

L VD S

HDMI level shift

PS8101T

+3.3V _RUN

Mini Card

WiFi

+3VS
+1.5VS
+3VALW
+3V_WLAN

USB[4]

PC IE3PC IE2PC IE5

page 28

page 20

+3VS
+3V_PEC
+3VS_PEC
+1.5VS
+1.5VS_PEC

HD MI

PC IE4

EX PRESS Card

page30

USB[7]

+1.5VS

+VCCP

+CPU_CORE

H_ A#( 3.. 35) H_ D#( 0..6 3)

+3VS

+1.8V/+1.8VS

+1.5VS

+VCCP

+3VS

+VCCP

+1.5VS

+3VALW

+RTCVCC

Pe ntium-M

Penryn -4MB (Socket P)

uFCPGA CPU

478pin

FSB

FSB 800/106 6 MHz

IN TEL

Cantiga

1329pin BGA

page 10,11 ,12,13,14, 15

DM I

+1.5V_R UN
100M Hz

IN TEL

IC H9-M

67 6pin BGA

page 21,22,23,24

page 7,8,9

Memory BUS
(DDR2)

IHDA I/F

S-ATA 0/4

HDD

+5VS

page 28

Clock Generator

CK505
SLG8LP554BVTR

+3VS

+1.8 V_MEM 667/800M Hz

USB 2.0

SA TA0

eSATA Repeater

+3VS

USB[2]

SA TA4

page 29

page6

USB[11]

USB[8]

FAN

FAN1_POWER

+5VS

DDRII-DIMM X2

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7

+1.8V
+V_DDR_MCH_REF

Combine with LVDS Cable

+5VS

Bl ue Tooth

+3VS

USB[0]

USB[1]

page 16,17

Ca mera

USB Port

+5V_USBR

USB Port

+5V_USBR

page 28

page 30

page 29

page 29

The rmal Sensor

+3VS

1402

page 18page 18

INT MIC

IEEE 139 4
C onn

page 29

Transformer

page 29

LPC BUS

E-SATA
CONN

+5V_ESATA

page 29

HeadPhone &
MIC Jack

page 29

On IO/B

RJ45 Conn

+LAN_IO

page 29

On IO/B

4 4

Power On/Off
SW & LED

page 31

Power Cont rol

page 32

DCIN/Pre charge

Ch arger

A

page 40

page 41

+3VALWP/+5VALWP

page 42

+VCCP

page 43

Touch Pad

+5VS

B

page 31

+1.8VP

+1.5VSP

PS2 I/F

page 44

page 45

+VGA_COREP

KBC

KB926D3

+RTC_CELL
+3.3V_ALW

Int.KBD

page 46

page 30

page 31

+CPU_COREP

C

SPI

MX 2 5 L 160 5AM 2C

+3VALW
+EC_AVCC

page 30

2Mb

+0.9V SP/+1.1V_GFX_PCIEP

page 47

Battery

page 48

page 49

D

HD Codec
92 HD81B

+3VS
+AVDD_H D

page 25

INT. Speaker

2 x 1W

On IO/B

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Doc ument Number Re v

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

LA-5162P

2 60Monday, A pril 20, 2009

E

1A

A

Voltage Rails

State

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

1 1

O MEANS ON X MEANS OFF

power
plane

+B

O

O

O

O

O

X

+5VALW

+3VALW

+1.8V

+1.1VS_GFX_PCIE

O

O

O

O

X

O

X X

X

X X X

+5VS

+3VS

+1.5VS

+VCCP

+CPU_CORE

+GPU_CORE

+1.8VS

+0.9VS

OO

OO

X

X

SATA

Lane 0

Lane 1

Lane 4

Lane 5

DESTINATION

HDD

NONE

ESATA

NONE

USB PORT#

0

1

2

3

DESTINATION

JUSBR1

JUSBR2

JUSBR3(E-SATA)

NONE

PCI EXPRESS

Lane 1 NONE

Lane 2

Lane 3

Lane 4

Lane 5

Lane 6

DESTINATION

GIGA LAN

WLAN

EXPRESS CARD

CARD READER

NONE

BOARD ID Table

BOARD ID

ID

0

0.1(X00)

1

0.2(X01)

2

0.3(X02)

3

1.0(A00)

NC
100K
100K
100K

Symbol Note :

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build
DEBUG@ : means just reserve for debug.

RbRa

0

9.09K
20K

37.4K

Vab

0V

0.25V

0.50V

0.82V

ICH9-M

4

5

6

*

7

8

9

10

11

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

WLAN

NONE

NONE

Express card

Bluetooth

NONE

NONE

CAMERA

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

Index and Configuration

LA-5162P

3 60Monday, A pril 20, 2009

0.2

5

4

3

2

1

INVERTER

ADAPTER

D D

EN_WOL#

SUSP

BATTERY

EC_ON

TPS51427

(PU5)

+3VALW

(U41)

SI3456BDV

(Q128)

SI4800DY

(U40)

RT9013

+1.5V_HDA

+LAN_IO

+3VS

3VS_DELAY_ON

SI2301BDS

(QG1)

+3VS_DELAY

B+

BATT+

C C

+5VALW

RUNON

CHARGER

24751
(PU4)

2@

VGA_ON

ISL6268CAZ-T

(PU9)

+VGA_CORE

SI4800DY

(U39)

+5VS

CAM_ON/OFF#

TPS71718DCKR

(U59)

SI2301BDS

(Q15)

+5V_AVDD_HD

+5V_CAM

SYSON

B B

VR_ON'

SUSP#

A A

5

SUSP#

TPS51117RGYR

(PU7)

ISL6266ACRZ-T

(PU10)

TPS51117RGYR

(PU6)

TPS51117RGYR

(PU8)

4

+1.8V

+CPU_CORE

+VCCP

+1.5VS

1.1VS_GFX_ON

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

SUSP

VGA_PWROD#

MAX8794

(PU11)

RT9026GFP

(PU12)

SI4800DY

(UG41)

+1.1V_GFX_PCIEP

+0.9VS

+1.8VS

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Doc ument Number Re v

2

Date: Sheet of

Compal Electronics, Inc.

Power Rails

LA-5162P

4 60Monday, A pril 20, 2009

1

1.0

5

4

3

2

1

2.2K

2.2K

G16

D D

ICH9-M

C C

ICH_SMBCLK

A13 ICH_SMBDATA

4.7K

4.7K

EC_SMB_CK1 7

77

EC_SMB_DA1

78

ENE

2.2K

+3VALW

2N7002

+5VALW

100 ohm

100 ohm

ICH_SM_CLK

ICH_SM_DA

Battery

6

Connector

2.2K

2.2K

16

Colck

17

Generator

195

JDIMMA

197

JDIMMB

8

7

Express Card

32

30

WLAN Card

+3VS

KB926

+3VS

CLK_THERMAL

DATA_THERMAL

8

7

EMC
1402

79

SMB_CLK_THERMAL

80

SMB_DATA_THERMAL

2.2K

B B

2.2K

2.2K

ATI

U7 ATI_SMBCLK

ATI_SMBDATAU8

M92-S2

A A

+3V_DELAY

ATI_SMBCLK

ATI_SMBDATA

8

7

ADM
1032

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Doc ument Number Re v

5

4

3

2

Date: Sheet of

Compal Electronics, Inc.

SMBus Topology

LA-5162P

5 60Monday, A pril 20, 2009

1

1.0

5

D D

4

+CK_VDD_M AIN+3VS

L1

1 2

BK2125HS601-T_0805~D

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C1

C9

2

0.1U_0402_16V4Z

1

1

C1011

2

2

1

C2

2

3

0.1U_0402_16V4Z

10U_0805_6.3V6-M~D

1

C4

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C5

C6

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C3

C7

2

2

2

FSB

FSC

CLKSEL2

0

0 1

*

0

1

1

FSA

CPU

SRC
MHz

100

100

PCI
MHz

33.3100

33.3

33.3

MHz

CLKSEL0CLKSEL1

266

00

200

0

166

1

R1222

1 2

0.047U_0402_16V 4Z~D

0.047U_0402_16V 4Z~D

1

1

C1012

Place close to U1 pin 18 and 40

C16

12

Place crystal w ithin
500 mils of CK505

C C

CLK_ICH_48M

10P_0402_50V8J~D

@

1

C1419

2

Place close to R21 pin2

+3VS

10K_0402_5%~D

B B

R45

1 2

TME

+3VS

10K_0402_5%~D

R1050

1 2

PCI _ICH

+3VS

10K_0402_5%~D

@

12

RG116

*

*

CLK_ICH_ 48M<23>
CPU_MCH_BSEL0<8,10>
CPU_MCH_BSEL1<8,10>

CPU_MCH_BSEL2<8,10>

CLK_DEBU G_PORT<28>

CLK_PC I_926<30>

CLK_ICH_ 14M<23>

MCH_ DREFCLK<10>
CLK_ATI_27M<35>
MCH_ DREFCLK#<10>
CLK_ATI_27M_SS<35>

CLK_P CI_ICH<21>

TME0PIN 32

Overclo cking enable

Overclo cking disable1

ITP_EN

PIN 37

Pin 5/6 as SRC_10

0

Pin 5/6 as CPU_ITP

1

33P_0402_50V8J~D

33P_0402_50V8J~D

CLK_ICH_48M
CPU_MCH_BSEL0
CPU_MCH_BSEL1

CPU_MCH_BSEL2

CLK_ICH_14M CLKRE F

MCH_ DREFCLK
CLK_ATI_27M
MCH_ DREFCLK#
CLK_ATI_27M_SS

CLK_P CI_ICH

12

CPN: SJ100005W0L

Y6

C17

14.318 18MHZ_20PF_1Y714318CE1B~D

12

R19 0_0402_5%

R21 33_0402_5%~D
R23 2.2K_0402_5%~D

R25 10K_0402_5%~D

R117 33_0402_5%~D

R1034 33_0402_5%~D

R9 33_0402_5%~D

R40 33_040 2_5%~D
RG44 61.9_0402_1%@
R41 33_040 2_5%~D
RG119 33_ 0402_5%~D@

R44 33_0402_5%~D

1 2

1 2

1 2

1 2

1 2

1 2
1 2
1 2
1 2

12

12

12

CLK_PW RGD<23>

ICH_SM _CLK< 16,17,23,27,28>

ICH_SM_DA<16,17 ,23,27,28>

C13

2

2

CLK_XTAL_IN

CLK_XTAL_OUT

FSA

FSC

FCT_SEL

CLK_DE BUGCLK_DEBU G_PORT

TME CLK_P CIE_LAN#

PCI_E CCLK_PC I_926

DOT96

DOT96#

PCI _ICH

CLK_PW RGD

ICH_SM_CLK

ICH_SM_DA

1
49
54
65

30
36

12

18

40

20

19

41

45

23

34

33

32

27

22

43

44

37

39

9

16

17

4

15

21

31

35

42

68

73

2.2_0603_5%~D

U1

VDD_SRC
VDD_SRC
VDD_SRC
VDD_SRC

VDD_PCI
VDD_PCI

VDD_CPU

VDD_REF

VDD_48

XTAL_IN

XTAL_OUT

USB_48MHz/FSLA

FSL_B/TEST_MODE

REF_0/FSL_C/TEST_SEL

PCICLK4/FCT_SEL

PCICLK3

PCICLK2/TME

PCICLK1

REF_1

DOT_96/27M

DOT_96#/27M_SS

PCICLK_F0/ITP_EN

CKPWRGD/PD#

NC

SMBCLK

SMBDAT

VSS_SRC

VSS_CPU

VSS_REF

VSS_PCI

VSS_PCI

VSS_48

VSS_SRC

THRM_PAD

SLG8LP554BVTR

FCT_SEL PIN44PIN43 PIN48PIN47

A A

FCT_SEL

10K_0402_5%~D

12

R58

1=DIS 27M SSout27M_out

5

DOT96T0=UMA

96/100M_C96/100M_TDOT96C

SRCC0SRCT0

4

SLG8LP554BVTR_QFN72_10X10~D

CIS Link:OK

CPN:SA000026T0L

PROPR IETARY NOTE : THI S SHEE T OF ENGIN EERIN G DRAW ING A ND SP ECIFIC ATION S CON TAINS CONFIDENTIAL
TRADE SECRE T AND OTHE R PROP RIETA RY IN FORMA TION O F DEL L INC . ("DE LL") THIS DOCUME NT MAY NOT
BE TR ANSFER RED O R COP IED WI THOUT THE EXPRE SS WRI TTEN AUTHO RIZATI ON OF DELL . IN ADDITION,
NEITH ER THI S SHE ET NO R THE INFOR MATIO N IT CONTAI NS WA Y BE USED B Y OR DISCL OSED T O ANY THIRD
PARTY WITHO UT DE LL'S EXPRES S WRI TTEN CONSENT.

3

+CK_VDD_A

VDD_A

VSS_A

PCI_STP#

CPU_STP#

CPU_1

CPU_1#

CPU_0

CPU_0#

CPU_ITP/SRC_10

CPU_ITP#/SRC_10#

SRC_9

SRC_9#

CLKREQ_9#

SRC_8

SRC_8#

CLKREQ_8#

SRC_7

SRC_7#

CLKREQ_7#

SRC_6

SRC_6#

CLKREQ_6#

SRC_5

SRC_5#

CLKREQ_5#

SRC_4

SRC_4#

CLKREQ_4#

SRC_3

SRC_3#

CLKREQ_3#

SRC_2

SRC_2#

CLKREQ_2#

SRC_1/SATA

SRC_1#/SATA#

CLKREQ_1#

LCD_CLK/SRC_0

LCD_CLK#/SRC_0#

7

8

25

24

11

10

14

13

6

5

3

2

72

70

69

71

66

67

38

63

64

62

60

61

29

58

59

57

55

56

28

52

53

26

50

51

46

47

48

4.7U_0603_6.3V6M~D

1

C14

C15

2

H_STP_PCI#

H_STP_CPU#

CLK_MCH_BCLK

CLK_MCH_BCLK#

CLK_CP U_BCLK

CLK_CP U_BCLK#

CLK_P CIE_WLAN

CLK_P CIE_WLAN#

WLAN _CLK_REQ#

CLK_P CIE_LAN

LAN_CLK_RE Q#

CLK_P CIE_ICH

CLK_P CIE_ICH#

CLK_P CIE_CR

CLK_P CIE_CR#

CR_CL K_REQ#

CLK_P CIE_VGA_R

CLK_P CIE_VGA#_R

VGA_CLK_R EQ#_R

CLK_PCIE_EXP

CLK_PCIE_EXP#

EXP_CLK_REQ#

CLK_MCH_3GPLL

CLK_MCH_3GPLL#

CLK_3GPLLR EQ#_R

CLK_PCIE_SATA

CLK_PCIE_SATA#

SATA_CLK_REQ#_R

DREF_ SSCLK_R

DREF_ SSCLK#_R

0.047U_0402_16V 4Z~D

H_STP_PCI# <23>

H_STP_CPU# <23>

CLK_MCH_BCLK <10>

CLK_MCH_BCLK# <10>

CLK_CP U_BCLK <7>

CLK_CP U_BCLK# <7>

CLK_P CIE_WLAN <28>

CLK_P CIE_WLAN# <28>

WLAN _CLK_REQ# <28>

CLK_P CIE_LAN <26>

CLK_P CIE_LAN# <26>

LAN_CLK_RE Q# <26>

CLK_P CIE_ICH <23>

CLK_P CIE_ICH# <23>

CLK_P CIE_CR <27>

CLK_P CIE_CR# <27>

CR_CL K_REQ# <27>

1 2

RG53 0_0402_5%2@

1 2

RG59 0_0402_5%2@

1 2

RG120 0_0402_5%2@

CLK_PCIE_EXP <27>

CLK_PCIE_EXP# <27>

EXP_CLK_REQ# <27>

CLK_MCH_3GPLL <10>

CLK_MCH_3GPLL# <10>

1 2

R51 475_0402_1%~D

CLK_PCIE_SATA <22>

CLK_PCIE_SATA# <22>

1 2

R1155 475_0402_1%~D

1 2

R54 0_0402_5%

1 2

R60 0_0402_5%

2

CLK_PCIE_ATI <34>

CLK_PCIE_ATI# <34>

ATI_CLK_REQ# <35>

CLK_3GPLLREQ# <10>

SATA_CLK_REQ# <23>

DREF_ SSCLK <10>

DREF_ SSCLK# <10>

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Doc ument Number Re v

Date: Sheet of

WLAN _CLK_REQ#

LAN_CLK_RE Q#

CR_CL K_REQ#

EXP_CLK_REQ#

CLK_3GPLLREQ#

SATA_CLK_REQ#

R6 10K_0402_5%~D

1 2

1 2

1 2

1 2

1 2

1 2

R10 10K_ 0402_5%~D

R7 10K_0402_5%~D

R121 10K_0402_5%~D

R122 10K_0402_5%~D

R127 10K_0402_5%~D

Compal Electronics, Inc.

Clock GEN. with internal terminations

LA-5162P

1

+3VS

1.0

6 60Monday, A pril 20, 2009

5

D D

4

3

2

1

H_A#[ 3..35]<10>

H_ADSTB#0<10>

H_REQ#0<10>
H_REQ#1<10>
H_REQ#2<10>
H_REQ#3<10>
H_REQ#4<10>

C C

H_ADSTB#1<10>

H_A20M#<22>
H_FER R#<22>
H_IGNN E#<22>

H_STPCLK#<22>
H_INTR<22>
H_NMI<22>
H_SMI#<22>

B B

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_FER R#
H_IGNN E#

H_STPCLK#
H_INT R
H_NMI
H_SMI#

ME@

JCPU1A

ADDR GROUP 0 ADDR GROUP 1

J4

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4
AB2
AA3

V1

A6
A5
C4

D5
C6
B4
A3

M4

N5
T2
V3
B2
C3
D2

D22

D3
F6

TH ERMAL

A[33]#
A[34]#

PROCHOT#

A[35]#
ADSTB[1]#

ICH

A20M#
FERR#

THERMTRIP#

IGNNE#

STPCLK#
LINT0
LINT1
SMI#

RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]

RESERVED

RSVD[10]

FOX_PZ4782A-274R-41_M erom

ADS#
BNR#
BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK

TDO
TMS

TRST#

XDP/ITP SIGNALS

DBR#

THERMDA
THERMDC

H CLK

BCLK[0]
BCLK[1]

H_ADS#

H1

H_BNR #

E2

H_BPR I#

G5

H_DEF ER#

H5

H_D RDY#

F21

H_ DBSY#

E1

H_BR0#

F1

H_IER R#

D20
B3

H_LOCK#

H4

H_RESET#

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3

H_ TRDY#

G2

H_HIT#

G6

H_HITM#

E4

AD4
AD3
AD1
AC4
AC2
AC1

XDP_TCK

AC5

XDP_TDI

AA6

TDI

AB3

XDP_TMS

AB5

XDP_TRST#

AB6
C20

VR_TT#

D21

H_THERMDA

A24

H_THERMDC

B25

H_THERMTRIP#

C7

CLK_CP U_BCLK

A22

CLK_CP U_BCLK#

A21

H_ADS# <10>
H_BNR # <10>
H_BPR I# <10>

H_DEF ER# <10>
H_D RDY# <10>
H_D BSY# <10>

H_BR0# <10>

H_INIT# < 22>

H_LOCK# <10>

H_RESET# <10>
H_RS#0 <10>
H_RS#1 <10>
H_RS#2 <10>
H_T RDY# <10>

H_HIT# <10>
H_HITM# <10>

R68

@

1 2

0_0402_5%

R69

@

1 2

0_0402_5%

R71

@

1 2

0_0402_5%

R87

@

1 2

0_0402_5%

H_THERMDA <18>
H_THERM DC <18>

H_THERMTRIP# <10,22>

CLK_CP U_BCLK <6>
CLK_CP U_BCLK# <6>

H_IER R#

XDP_TDI

XDP_TMS

XDP_TRST#

XDP_TCK

R18 56_0402_5%

R5 54.9_0402_1%

R4 54.9_0402_1%

R11 54.9_0402_1%

R35 54.9_0402_1%

This shall place near CPU

+VCCP

VR_TT#

1 2

1 2

1 2

1 2

12

R92

68_0402_1%~D

VR_TT# <48>

+VCCP

12

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

CIS Link:OK

12/29

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

Penryn(1/3)-AGTL+/ITP-XDP

LA-5162P

1

7 60Monday, A pril 20, 2009

0.2

5

4

3

2

1

H_D #[0..63]<10>

ME@

H_D#0
H_D#1
H_D#2

D D

H_DSTBN#0<10>
H_DSTBP#0<10>
H_DIN V#0<10>

C C

R52 1K_0402_5%~D@
R22 1K_0402_5%~D@

CPU_MCH_BSEL0<6,10>
CPU_MCH_BSEL1<6,10>
CPU_MCH_BSEL2<6,10>

H_DSTBN#1<10>
H_DSTBP#1<10>
H_DIN V#1<10>

1 2
1 2

T12
T13
T14
T15

H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DIN V#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30

H_D#31
H_DSTBN#1
H_DSTBP#1
H_DIN V#1

+V_CPU_GTLREF

TEST1

TEST2

TEST3

TEST4

TEST5

TEST6

CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2

layout note: Rout H_DPRSTP# from ICH9 to IMVP6 then to GMCH & CPU

layout note: Route TEST3 & TE ST5 tr aces on ground referenced layer to the TPs

FSB
Frequency

B B

667MHz

800MHz

BSEL[2] BSEL[1]

0 1

0 1

JCPU1B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

AD26

AF26

M24

M23

R24

N25

M26
N24

C23
D25
C24

AF1

C21

L23

L22

P25
P23
P22
T24

L25
T25

L26

A26

B22
B23

DATA GRP 1

D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

GTLREF

MISC

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

BSEL[0]
BSEL[1]
BSEL[2]

FOX_PZ4782A-274R-41_M erom

BSEL[0]

1

0

DATA GRP 0

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#

DATA GRP 2DATA GRP 3

D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#

COMP[0]
COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

*

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DIN V#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DIN V#3

COMP0
COMP1
COMP2
COMP3

H_DPRSTP#
H_DPSLP#
H_DPW R#
H_PW RGOOD
H_CPUSLP #
H_PSI#

H_DSTBN#2 <10>
H_DSTBP#2 <10>
H_DIN V#2 <10>

H_DSTBN#3 <10>
H_DSTBP#3 <10>
H_DIN V#3 <10>

H_DPRSTP# <10,22,48>
H_DPSLP# <22>

H_DPW R# <10>

H_PW RGOOD <22>
H_CPUSLP # <10>

H_PSI# <48>

12

12

12

R1023

R24

54.9_0402_1%

27.4_0402_1%

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4 mils

R26

R1025

27.4_0402_1%

54.9_0402_1%

+CPU_ CORE +CPU_CORE

12

ME@

JCPU 1C

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15
AB17
AB18

VCCSENSE
VCC[065]
VCC[066]
VCC[067]

VSSSENSE

FOX_PZ4782A-274R-41_M erom

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

VCCSENS E

VSSSENSE

CPU_V ID0 <48>
CPU_V ID1 <48>
CPU_V ID2 <48>
CPU_V ID3 <48>
CPU_V ID4 <48>
CPU_V ID5 <48>
CPU_V ID6 <48>

VCCSENS E <48>

VSSSENSE <48>

220U_ D2_4VY_R15M

+VCCP

C1110

10U_0805_6.3V6M

1

2

1

2

+

C1112

+1.5VS

1

C11

2

0.01U_0402_16V7K

Near pin B26

1066MHz 0 0 0

VCCSENSE, VSSSENSE-->Width=18mils,
Space=7mils, Space to other signals 25mils at least.

+VCCP

12

R27

1K_0402_1%

+V_CPU_GTLREF

12

R29

2K_0402_1%

A A

Close to CPU pin AD26

Length match within 25 mils.

Close to CPU pin
within 500mils.

within 500mils.

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

2

VCCSENS E

VSSSENSE

Title

Size Doc ument Number Re v

Cus tom

LA-5162P

Date: Sheet of

+CPU_C ORE

R28100_0402_1%

12

R30100_0402_1%

12

Compal Electronics, Inc.

Penryn(2/3)-AGTL+/ITP-XDP

1

8 60Monday, A pril 20, 2009

0.2

5

High Frequence Decoupling

10uF 0805 X5R -> 85 degree.

D D

C C

B B

A A

ME@

JCPU 1D

A4

A8
A11
A14
A16
A19
A23
AF2

B6

B8
B11
B13
B16
B19
B21
B24

C5

C8
C11
C14
C16
C19

C2
C22
C25

D1

D4

D8
D11
D13
D16
D19
D23
D26

E3

E6

E8
E11
E14
E16
E19
E21
E24

F5

F8
F11
F13
F16
F19

F2
F22
F25

G4

G1
G23
G26

H3

H6
H21
H24

J2

J5
J22
J25

K1

K4
K23
K26

L3

L6
L21
L24

M2

M5
M22
M25

N1

N4
N23
N26

FOX_PZ4782A-274R-41_M erom

VSS[082]

VSS[001]
VSS[002]

VSS[083]

VSS[003]

VSS[084]

VSS[004]

VSS[085]

VSS[005]

VSS[086]

VSS[006]

VSS[087]

VSS[007]

VSS[088]

VSS[008]

VSS[089]

VSS[009]

VSS[090]

VSS[010]

VSS[091]

VSS[011]

VSS[092]

VSS[012]

VSS[093]

VSS[013]

VSS[094]

VSS[014]

VSS[095]

VSS[015]

VSS[096]

VSS[016]

VSS[097]

VSS[017]

VSS[098]

VSS[018]

VSS[099]

VSS[019]

VSS[100]

VSS[020]

VSS[101]

VSS[021]

VSS[102]

VSS[022]

VSS[103]

VSS[023]

VSS[104]

VSS[024]

VSS[105]

VSS[025]

VSS[106]

VSS[026]

VSS[107]

VSS[027]

VSS[108]

VSS[028]

VSS[109]

VSS[029]

VSS[110]

VSS[030]

VSS[111]

VSS[031]

VSS[112]

VSS[032]

VSS[113]

VSS[033]

VSS[114]

VSS[034]

VSS[115]

VSS[035]

VSS[116]

VSS[036]

VSS[117]

VSS[037]

VSS[118]

VSS[038]

VSS[119]

VSS[039]

VSS[120]

VSS[040]

VSS[121]

VSS[041]

VSS[122]

VSS[042]

VSS[123]

VSS[043]

VSS[124]

VSS[044]

VSS[125]

VSS[045]

VSS[126]

VSS[046]

VSS[127]

VSS[047]

VSS[128]

VSS[048]

VSS[129]

VSS[049]

VSS[130]

VSS[050]

VSS[131]

VSS[051]

VSS[132]

VSS[052]

VSS[133]

VSS[053]

VSS[134]

VSS[054]

VSS[135]

VSS[055]

VSS[136]

VSS[056]

VSS[137]

VSS[057]

VSS[138]

VSS[058]

VSS[139]

VSS[059]

VSS[140]

VSS[060]

VSS[141]

VSS[061]

VSS[142]

VSS[062]

VSS[143]

VSS[063]

VSS[144]

VSS[064]

VSS[145]

VSS[065]

VSS[146]

VSS[066]

VSS[147]
VSS[148]

VSS[067]
VSS[068]

VSS[149]

VSS[069]

VSS[150]

VSS[070]

VSS[151]

VSS[071]

VSS[152]

VSS[072]

VSS[153]

VSS[073]

VSS[154]

VSS[074]

VSS[155]

VSS[075]

VSS[156]

VSS[076]

VSS[157]

VSS[077]

VSS[158]

VSS[078]

VSS[159]

VSS[079]

VSS[160]

VSS[080]

VSS[161]

VSS[081]P3VSS[162]

VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

+VCCP

1

C213

0.1U_0402_16V7K~D

2

4

+CPU_ CORE

1

C204
10U_0805_4VAM~D

2

+CPU_ CORE

1

C180
10U_0805_4VAM~D

2

+CPU_ CORE

1

C501
10U_0805_4VAM~D

2

+CPU_ CORE

1

C502
10U_0805_4VAM~D

2

+CPU_C ORE

1

C196

+

2

1

C209

0.1U_0402_16V7K~D

2

3

2

1

Place these caps inside
the CPU socket.

1

C205
10U_0805_4VAM~D

2

1

C529
10U_0805_4VAM~D

2

1

C232
10U_0805_4VAM~D

2

1

C258
10U_0805_4VAM~D

2

1

C505
10U_0805_4VAM~D

2

1

C504
10U_0805_4VAM~D

2

1

C257
10U_0805_4VAM~D

2

1

C262
10U_0805_4VAM~D

2

1

( Left side on Top ).

C214
10U_0805_4VAM~D

2

Place these caps inside
the CPU socket.

1

C202
10U_0805_4VAM~D

2

1

C508
10U_0805_4VAM~D

2

1

C510
10U_0805_4VAM~D

2

330U_ D2_2.5VY_R9M

330U_ D2_2.5VY_R9M

1

C198

+

2

1

C259

+

2

1

C212

0.1U_0402_16V7K~D

2

330U_ D2_2.5VY_R9M

330U_ D2_2.5VY_R9M

1

C255

+

2

1

2

1

C254
10U_0805_4VAM~D

2

1

C514
10U_0805_4VAM~D

2

1

C515
10U_0805_4VAM~D

2

C188

0.1U_0402_16V7K~D

1

C190
10U_0805_4VAM~D

2

1

C519
10U_0805_4VAM~D

2

1

C520
10U_0805_4VAM~D

2

1

C183

0.1U_0402_16V7K~D

2

1

C203
10U_0805_4VAM~D

2

1

C523
10U_0805_4VAM~D

2

1

C528
10U_0805_4VAM~D

2

1

C200
10U_0805_4VAM~D

2

1

C533
10U_0805_4VAM~D

2

1

C532
10U_0805_4VAM~D

2

ESR <= 1.5m ohm

Capacitor > 880 uF

Plac e these inside
sock et cavity o n L8
(North side
Secon dary)

1

C185

0.1U_0402_16V7K~D

2

1

C184
10U_0805_4VAM~D

2

1

C199
10U_0805_4VAM~D

2

1

C208
10U_0805_4VAM~D

2

1

( Righ t side on Top ).

C1126
10U_0805_4VAM~D

2

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

Penryn(3/3)-AGTL+/ITP-XDP

LA-5162P

1

9 60Monday, A pril 20, 2009

0.2

5

U4A

H_D# [0..63]<8>

D D

C C

H_RESET#<7>
H_CPU SLP#<8>

B B

Layout Note:
+H_RCO MP / +H_VREF / +H_SWING

trace width and spacing is 10/20

+VCCP

12

R1045

1K_0402_1%

A A

12

R46

2K_0402_1%

1

2

0.1U_0402_16V7K~D

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

+H_SW ING
+H_RCOMP

H_RESET#

H_CPUSLP #

+H_VREF

+H_VREF

C391

@

5

F2

H_D#_0

G8

H_D#_1

F8

H_D#_2

E6

H_D#_3

G2

H_D#_4

H6

H_D#_5

H2

H_D#_6

F6

H_D#_7

D4

H_D#_8

H3

H_D#_9

M9

H_D#_10

M11

H_D#_11

J1

H_D#_12

J2

H_D#_13

N12

H_D#_14

J6

H_D#_15

P2

H_D#_16

L2

H_D#_17

R2

H_D#_18

N9

H_D#_19

L6

H_D#_20

M5

H_D#_21

J3

H_D#_22

N2

H_D#_23

R1

H_D#_24

N5

H_D#_25

N6

H_D#_26

P13

H_D#_27

N8

H_D#_28

L7

H_D#_29

N10

H_D#_30

M3

H_D#_31

Y3

H_D#_32

AD14

H_D#_33

Y6

H_D#_34

Y10

H_D#_35

Y12

H_D#_36

Y14

H_D#_37

Y7

H_D#_38

W2

H_D#_39

AA8

H_D#_40

Y9

H_D#_41

AA13

H_D#_42

AA9

H_D#_43

AA11

H_D#_44

AD11

H_D#_45

AD10

H_D#_46

AD13

H_D#_47

AE12

H_D#_48

AE9

H_D#_49

AA2

H_D#_50

AD8

H_D#_51

AA3

H_D#_52

AD3

H_D#_53

AD7

H_D#_54

AE14

H_D#_55

AF3

H_D#_56

AC1

H_D#_57

AE3

H_D#_58

AC3

H_D#_59

AE11

H_D#_60

AE8

H_D#_61

AG2

H_D#_62

AD6

H_D#_63

C5

H_SWING

E3

H_RCOMP

C12

H_CPURST#

E11

H_CPUSLP#

A11

H_AVREF

B11

H_DVREF

CANTI GA ES_FCBGA1329

+H_RCOMP

12

R324

24.9_0402_1%

+VCCP

221_0603_1%

100_0402_1%

12

R322

12

R323

H_ADSTB#_0
H_ADSTB#_1

H_DEFER#

HOST

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

Near B3 pinwithin 100 mils from NB

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_BREQ#

H_DBSY#

H_DRDY#

H_HIT#

H_HITM#

H_LOCK#
H_TRDY#

H_RS#_0
H_RS#_1
H_RS#_2

+H_SW ING

1

2

0.1U_0402_16V7K~D

C386

A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20

H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9

J8
L3
Y13
Y1

L10
M7
AA5
AE6

L9
M8
AA6
AE5

B15
K13
F13
B13
B14

B6
F12
C8

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR #
H_BPR I#
H_BR0#
H_DEF ER#
H_ DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPW R#
H_D RDY#
H_HIT#
H_HITM#
H_LOCK#
H_ TRDY#

H_DIN V#0
H_DIN V#1
H_DIN V#2
H_DIN V#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

4

H_A#[ 3..35] <7>

+SMRCOMP_VOH

+SMRCOMP_VOL

H_ADS# <7>
H_ADSTB#0 < 7>
H_ADSTB#1 < 7>
H_BNR # <7>
H_BPR I# <7>
H_BR0# <7>
H_DEF ER# <7>
H_D BSY# <7>
CLK_MCH_BCLK <6>
CLK_MCH_BCLK# <6>
H_DPW R# <8>
H_D RDY# <7>

H_HIT# <7>
H_HITM# <7>
H_LOCK# <7>

H_T RDY# <7>

H_DIN V#0 <8>
H_DIN V#1 <8>
H_DIN V#2 <8>
H_DIN V#3 <8>

H_DSTBN#0 <8>
H_DSTBN#1 <8>
H_DSTBN#2 <8>
H_DSTBN#3 <8>

H_DSTBP#0 <8>
H_DSTBP#1 <8>
H_DSTBP#2 <8>
H_DSTBP#3 <8>

H_REQ#0 <7>
H_REQ#1 <7>
H_REQ#2 <7>
H_REQ#3 <7>
H_REQ#4 <7>

H_RS#0 <7>
H_RS#1 <7>
H_RS#2 <7>

ICH_P WROK<23,30>

Layout Note:
+V_DDR _MCH_REF
trace width and
spacin g is 20/20.

4

3

T7
T11
T72

+1.8V

1

1

C398

2

2.2U_06 03_6.3V6K~D

1

C403

2

2.2U_06 03_6.3V6K~D

PLT_RST#<21,27,30,34>

DPRSLPVR<23,48>

1 2

R408 0_0402_5%

+V_DD R_MCH_REF +VCCP

0.1U_0402_16V7K~D

12

R331

C400

1K_0402_1%

0.01U_0402_16V7K

2

12

R332

3.01K_0402_1%

12

R333

1

1K_0402_1%

C404

2

0.01U_0402_16V7K

+3VS

10K_0402_5%~D

10K_0402_5%~D

R523 100_0402_5%~D

+V_DD R_MCH_REF

1

C121

2

R82

12

R83

12

C36

@

12

0.1U_0402_16V7K~D

CPU_MCH_BSEL0<6,8>
CPU_MCH_BSEL1<6,8>
CPU_MCH_BSEL2<6,8>

PM_BMBUSY#<23>

H_DPRSTP#<8,22,48>
PM_EXTTS#0<16>

PM_PWROK_R

PM_EXTTS#1<17>

H_THERMTRIP#<7,22>

+1.8V

1 2

PM_EXTTS#0

PM_EXTTS#1

H_DPRSTP#

CFG5<12>
CFG6<12>
CFG7<12>

CFG9<12>

CFG16<12>

CFG19<12>
CFG20<12>

12

R42
1K_0402_1%

12

R43
1K_0402_1%

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

T23
T74
T75
T136
T17
T18
T19
T20
T21
T22
T24

T25
T26
T27

T28

T41
T44
T73
T184

CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2

T8
T9

CFG5
CFG6
CFG7

T37

CFG9

T65
T40

CFG12

T67

CFG13

T47
T10
T66

CFG16

T68
T39

CFG19
CFG20

PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_PWROK_R
PLT_RST#_NB
H_THERMTRIP#
DPRSLPVR

2009/01/05 2009/01/05

3

U4B

M36

RSVD1

N36

RSVD2

R33

RSVD3

T33

RSVD4

AH9

RSVD5

AH10

RSVD6

AH12

RSVD7

AH13

RSVD8

K12

RSVD9

AL34

RSVD10

AK34

RSVD11

AN35

RSVD12

AM35

RSVD13

T24

RSVD14

B31

RSVD15

B2

RSVD16

M1

RSVD17

AY21

RSVD20

BG23

RSVD22

BF23

RSVD23

BH18

RSVD24

BF18

RSVD25

T25

CFG_0

R25

CFG_1

P25

CFG_2

P20

CFG_3

P24

CFG_4

C25

CFG_5

N24

CFG_6

M24

CFG_7

E21

CFG_8

C23

CFG_9

C24

CFG_10

N21

CFG_11

P21

CFG_12

T21

CFG_13

R20

CFG_14

M20

CFG_15

L21

CFG_16

H21

CFG_17

P29

CFG_18

R28

CFG_19

T28

CFG_20

R29

PM_SYNC#

B7

PM_DPRSTP#

N33

PM_EXT_TS#_0

P32

PM_EXT_TS#_1

AT40

PWROK

AT11

RSTIN#

T20

THERMTRIP#

R32

DPRSLPVR

BG48

NC_1

BF48

NC_2

BD48

NC_3

BC48

NC_4

BH47

NC_5

BG47

NC_6

BE47

NC_7

BH46

NC_8

BF46

NC_9

BG45

NC_10

BH44

NC_11

BH43

NC_12

BH6

NC_13

BH5

NC_14

BG4

NC_15

BH3

NC_16

BF3

NC_17

BH2

NC_18

BG2

NC_19

BE2

NC_20

BG1

NC_21

BF1

NC_22

BD1

NC_23

BC1

NC_24

F1

NC_25

A47

NC_26

CANTI GA ES_FCBGA1329

Compal Secret Data

Deciphered Date

2

M_CLK_DD R0

AP24

SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1

SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1

SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1

SA_CS#_0
SA_CS#_1
SB_CS#_0

RSVD CFG PM NC

DDR CLK/ CONTROL/ COMPENSATIONHDA

CLKDMIGRAPHICS VIDMEMISC

SB_CS#_1

SA_ODT_0
SA_ODT_1

SB_ODT_O

SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_PWROK

SM_DRAMRST#

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

GFX_VR_EN

CL_PWROK

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

ICH_SYNC#

HDA_BCLK
HDA_RST#

HDA_SDO

HDA_SYNC

2

SM_VREF

SM_REXT

PEG_CLK

CL_CLK

CL_DATA

CL_RST#
CL_VREF

CLKREQ#

TSATN#

HDA_SDI

M_CLK_DD R1

AT21

M_CLK_DD R2

AV24

M_CLK_DD R3

AU20

M_CLK_DDR#0

AR24

M_CLK_DDR#1

AR21

M_CLK_DDR#2

AU24

M_CLK_DDR#3

AV20

DDR_CKE 0_DIMMA

BC28

DDR_CKE 1_DIMMA

AY28

DDR_CKE 2_DIMMB

AY36

DDR_CKE 3_DIMMB

BB36

DDR_C S0_DIMMA#

BA17

DDR_C S1_DIMMA#

AY16

DDR_C S2_DIMMB#

AV16

DDR_C S3_DIMMB#

AR13

M_ODT0

BD17

M_ODT1

AY17

M_ODT2

BF15

M_ODT3

AY13

SMRCOMP

BG22

SMRCOMP#

BH21

+SMRCOMP_VOH

BF28

+SMRCOMP_VOL

BH28

+V_DD R_MCH_REF

AV42
AR36

SM_REXT

BF17

TP_SM_DRAMRST#

BC36

MCH_ DREFCLK

B38

MCH_ DREFCLK#

A38

DREF_ SSCLK

E41

DREF_ SSCLK#

F41

CLK_MCH_3GPLL

F43

CLK_MCH_3GPLL#

E43

DMI_ITX_MRX_N0

AE41

DMI_ITX_MRX_N1

AE37

DMI_ITX_MRX_N2

AE47

DMI_ITX_MRX_N3

AH39

DMI_ITX_MRX_P0

AE40

DMI_ITX_MRX_P1

AE38

DMI_ITX_MRX_P2

AE48

DMI_ITX_MRX_P3

AH40

DMI_MTX_IRX_N0

AE35

DMI_MTX_IRX_N1

AE43

DMI_MTX_IRX_N2

AE46

DMI_MTX_IRX_N3

AH42

DMI_MTX_IRX_P0

AD35

DMI_MTX_IRX_P1

AE44

DMI_MTX_IRX_P2

AF46

DMI_MTX_IRX_P3

AH43

B33
B32
G33
F33
E33

C34

AH37
AH36
AN36
AJ35
AH34

N28
M28
G36
E36
K36
H36

B12

B28
B30
B29
C29
A28

T30
T31
T32
T33
T34

T35

CL_CLK0
CL_DATA0
M_PWROK
CL_RST#
+CL_VREF

CLK_3GPLLREQ#
MCH _ICH_SYNC #

TSATN#

ADC_A CZ_SDIN0_GMC H

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

M_CLK_DDR0 <16>
M_CLK_DDR1 <16>
M_CLK_DDR2 <17>
M_CLK_DDR3 <17>

M_CLK_DDR#0 <16>
M_CLK_DDR#1 <16>
M_CLK_DDR#2 <17>
M_CLK_DDR#3 <17>

DDR_CKE 0_DIMMA <16>
DDR_CKE 1_DIMMA <16>
DDR_CKE 2_DIMMB <17>
DDR_CKE 3_DIMMB <17>

DDR_CS0_D IMMA# <16>
DDR_CS1_D IMMA# <16>
DDR_CS2_D IMMB# <17>
DDR_CS3_D IMMB# <17>

M_ODT0 <16>
M_ODT1 <16>
M_ODT2 <17>
M_ODT3 <17>

R328 80.6_0402_1%

1 2

R329 80.6_0402_1%

1 2

+V_DD R_MCH_REF

R1040 499_0402_1%

1 2

T29

MCH_ DREFCLK <6>
MCH_ DREFCLK# <6>
DREF_ SSCLK <6>
DREF_ SSCLK# <6>

CLK_MCH_3GPLL <6>
CLK_MCH_3GPLL# <6>

DMI_ITX_MRX_N0 <23>
DMI_ITX_MRX_N1 <23>
DMI_ITX_MRX_N2 <23>
DMI_ITX_MRX_N3 <23>

DMI_ITX_MRX_P0 <23>
DMI_ITX_MRX_P1 <23>
DMI_ITX_MRX_P2 <23>
DMI_ITX_MRX_P3 <23>

DMI_MTX_IRX_N0 <23>
DMI_MTX_IRX_N1 <23>
DMI_MTX_IRX_N2 <23>
DMI_MTX_IRX_N3 <23>

DMI_MTX_IRX_P0 <23>
DMI_MTX_IRX_P1 <23>
DMI_MTX_IRX_P2 <23>
DMI_MTX_IRX_P3 <23>

MCH_ DREFCLK

MCH_ DREFCLK#

DREF_ SSCLK

DREF_ SSCLK#

CL_CLK0 <23>
CL_DATA0 <23>
M_PWROK <23>
CL_RST# <23>

T36

0.1U_0402_16V7K~D

T48

GMCH_ HDMICLK <20>
GMCH_HDM IDAT <20>

CLK_3GPLLREQ# <6>

MCH _ICH_SYNC# <23>

R521 56_0402_5%

GMCH_H DA_BITCLK <22>

GMCH_HDA _RST# <22>

1 2

R98 33_0402_5%~D1@

GMCH_H DA_SDOUT <22>
GMCH_ HDA_SYNC <22>

Compal Electronics, Inc.

Cantiga(1/6)-AGTL/DMI/DDR

LA-5162P

1

RG156

@

RG158

@

RG160

@

RG161

@

1

C181

2

12

1

+1.8V

1 2

0_0402_5%

1 2

0_0402_5%

1 2

0_0402_5%

1 2

0_0402_5%

+VCCP

12

R100
1K_0402_1%

0.35V

12

R99
511_0402_1%

ADC_G MCH_SDIN2 <22>

10 60Monday , April 20, 2009

0.2

5

4

3

2

1

D D

U4D

DDR_A _D0
DDR_A _D1
DDR_A _D2
DDR_A _D3
DDR_A _D4
DDR_A _D5
DDR_A _D6
DDR_A _D7
DDR_A _D8
DDR_A _D9
DDR_A _D10
DDR_A _D11
DDR_A _D12
DDR_A _D13
DDR_A _D14
DDR_A _D15
DDR_A _D16
DDR_A _D17
DDR_A _D18
DDR_A _D19
DDR_A _D20
DDR_A _D21
DDR_A _D22
DDR_A _D23
DDR_A _D24
DDR_A _D25
DDR_A _D26
DDR_A _D27

C C

B B

DDR_A _D28
DDR_A _D29
DDR_A _D30
DDR_A _D31
DDR_A _D32
DDR_A _D33
DDR_A _D34
DDR_A _D35
DDR_A _D36
DDR_A _D37
DDR_A _D38
DDR_A _D39
DDR_A _D40
DDR_A _D41
DDR_A _D42
DDR_A _D43
DDR_A _D44
DDR_A _D45
DDR_A _D46
DDR_A _D47
DDR_A _D48
DDR_A _D49
DDR_A _D50
DDR_A _D51
DDR_A _D52
DDR_A _D53
DDR_A _D54
DDR_A _D55
DDR_A _D56
DDR_A _D57
DDR_A _D58
DDR_A _D59
DDR_A _D60
DDR_A _D61
DDR_A _D62
DDR_A _D63

AJ38

SA_DQ_0

AJ41

SA_DQ_1

AN38

SA_DQ_2

AM38

SA_DQ_3

AJ36

SA_DQ_4

AJ40

SA_DQ_5

AM44

SA_DQ_6

AM42

SA_DQ_7

AN43

SA_DQ_8

AN44

SA_DQ_9

AU40

SA_DQ_10

AT38

SA_DQ_11

AN41

SA_DQ_12

AN39

SA_DQ_13

AU44

SA_DQ_14

AU42

SA_DQ_15

AV39

SA_DQ_16

AY44

SA_DQ_17

BA40

SA_DQ_18

BD43

SA_DQ_19

AV41

SA_DQ_20

AY43

SA_DQ_21

BB41

SA_DQ_22

BC40

SA_DQ_23

AY37

SA_DQ_24

BD38

SA_DQ_25

AV37

SA_DQ_26

AT36

SA_DQ_27

AY38

SA_DQ_28

BB38

SA_DQ_29

AV36

SA_DQ_30

AW36

SA_DQ_31

BD13

SA_DQ_32

AU11

SA_DQ_33

BC11

SA_DQ_34

BA12

SA_DQ_35

AU13

SA_DQ_36

AV13

SA_DQ_37

BD12

SA_DQ_38

BC12

SA_DQ_39

BB9

SA_DQ_40

BA9

SA_DQ_41

AU10

SA_DQ_42

AV9

SA_DQ_43

BA11

SA_DQ_44

BD9

SA_DQ_45

AY8

SA_DQ_46

BA6

SA_DQ_47

AV5

SA_DQ_48

AV7

SA_DQ_49

AT9

SA_DQ_50

AN8

SA_DQ_51

AU5

SA_DQ_52

AU6

SA_DQ_53

AT5

SA_DQ_54

AN10

SA_DQ_55

AM11

SA_DQ_56

AM5

SA_DQ_57

AJ9

SA_DQ_58

AJ8

SA_DQ_59

AN12

SA_DQ_60

AM13

SA_DQ_61

AJ11

SA_DQ_62

AJ12

SA_DQ_63

CANTI GA ES_FCBGA1329

DDR_A_BS #0

BD21

SA_BS_0
SA_BS_1
SA_BS_2

SA_RAS#
SA_CAS#

SA_WE#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7

SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3

DDR SYSTEM MEMORY A

SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

BG18
AT25

BB20
BD20
AY20

AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5

AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7

AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8

BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25

DDR_A_BS #1
DDR_A_BS #2

DDR_A _RAS#
DDR_A _CAS#
DDR_A_W E#

DDR_A_DM 0
DDR_A_DM 1
DDR_A_DM 2
DDR_A_DM 3
DDR_A_DM 4
DDR_A_DM 5
DDR_A_DM 6
DDR_A_DM 7

DDR_A _DQS0
DDR_A _DQS1
DDR_A _DQS2
DDR_A _DQS3
DDR_A _DQS4
DDR_A _DQS5
DDR_A _DQS6
DDR_A _DQS7

DDR_A _DQS#0
DDR_A _DQS#1
DDR_A _DQS#2

DDR_A _DQS#3

DDR_A _DQS#4
DDR_A _DQS#5
DDR_A _DQS#6
DDR_A _DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

DDR_A_BS #0 <16>
DDR_A_BS #1 <16>
DDR_A_BS #2 <16>

DDR_A _RAS# <16>
DDR_A _CAS# <16>
DDR_A_W E# <16>

DDR_A _DM[0..7] <16>

DDR_A _DQS[0..7 ] <16>

DDR_A _DQS#[0.. 7] <16>

DDR_A _MA[0..14] <16>

DDR_ B_D[0..63 ]<17>DDR_ A_D[0..63 ]<16>

DDR_B _D0
DDR_B _D1
DDR_B _D2
DDR_B _D3
DDR_B _D4
DDR_B _D5
DDR_B _D6
DDR_B _D7
DDR_B _D8
DDR_B _D9
DDR_B _D10
DDR_B _D11
DDR_B _D12
DDR_B _D13
DDR_B _D14
DDR_B _D15
DDR_B _D16
DDR_B _D17
DDR_B _D18
DDR_B _D19
DDR_B _D20
DDR_B _D21
DDR_B _D22
DDR_B _D23
DDR_B _D24
DDR_B _D25
DDR_B _D26
DDR_B _D27
DDR_B _D28
DDR_B _D29
DDR_B _D30
DDR_B _D31
DDR_B _D32
DDR_B _D33
DDR_B _D34
DDR_B _D35
DDR_B _D36
DDR_B _D37
DDR_B _D38
DDR_B _D39
DDR_B _D40
DDR_B _D41
DDR_B _D42
DDR_B _D43
DDR_B _D44
DDR_B _D45
DDR_B _D46
DDR_B _D47
DDR_B _D48
DDR_B _D49
DDR_B _D50
DDR_B _D51
DDR_B _D52
DDR_B _D53
DDR_B _D54
DDR_B _D55
DDR_B _D56
DDR_B _D57
DDR_B _D58
DDR_B _D59
DDR_B _D60
DDR_B _D61
DDR_B _D62
DDR_B _D63

U4E

AK47

SB_DQ_0

AH46

SB_DQ_1

AP47

SB_DQ_2

AP46

SB_DQ_3

AJ46

SB_DQ_4

AJ48

SB_DQ_5

AM48

SB_DQ_6

AP48

SB_DQ_7

AU47

SB_DQ_8

AU46

SB_DQ_9

BA48

SB_DQ_10

AY48

SB_DQ_11

AT47

SB_DQ_12

AR47

SB_DQ_13

BA47

SB_DQ_14

BC47

SB_DQ_15

BC46

SB_DQ_16

BC44

SB_DQ_17

BG43

SB_DQ_18

BF43

SB_DQ_19

BE45

SB_DQ_20

BC41

SB_DQ_21

BF40

SB_DQ_22

BF41

SB_DQ_23

BG38

SB_DQ_24

BF38

SB_DQ_25

BH35

SB_DQ_26

BG35

SB_DQ_27

BH40

SB_DQ_28

BG39

SB_DQ_29

BG34

SB_DQ_30

BH34

SB_DQ_31

BH14

SB_DQ_32

BG12

SB_DQ_33

BH11

SB_DQ_34

BG8

SB_DQ_35

BH12

SB_DQ_36

BF11

SB_DQ_37

BF8

SB_DQ_38

BG7

SB_DQ_39

BC5

SB_DQ_40

BC6

SB_DQ_41

AY3

SB_DQ_42

AY1

SB_DQ_43

BF6

SB_DQ_44

BF5

SB_DQ_45

BA1

SB_DQ_46

BD3

SB_DQ_47

AV2

SB_DQ_48

AU3

SB_DQ_49

AR3

SB_DQ_50

AN2

SB_DQ_51

AY2

SB_DQ_52

AV1

SB_DQ_53

AP3

SB_DQ_54

AR1

SB_DQ_55

AL1

SB_DQ_56

AL2

SB_DQ_57

AJ1

SB_DQ_58

AH1

SB_DQ_59

AM2

SB_DQ_60

AM3

SB_DQ_61

AH3

SB_DQ_62

AJ3

SB_DQ_63

CANTI GA ES_FCBGA1329

DDR_B_BS#0

BC16

SB_BS_0
SB_BS_1
SB_BS_2

SB_RAS#
SB_CAS#

SB_WE#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7

SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2

DDR SYSTEM MEMORY B

SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

BB17
BB33

AU17
BG16
BF14

AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2

AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6

AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5

AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33

DDR_B_BS #1
DDR_B_BS #2

DDR_B _RAS#
DDR_B _CAS#
DDR_B_W E#

DDR_B_DM 0
DDR_B_DM 1
DDR_B_DM 2
DDR_B_DM 3
DDR_B_DM 4
DDR_B_DM 5
DDR_B_DM 6
DDR_B_DM 7

DDR_B _DQS0
DDR_B _DQS1
DDR_B _DQS2
DDR_B _DQS3
DDR_B _DQS4
DDR_B _DQS5
DDR_B _DQS6
DDR_B _DQS7

DDR_B _DQS#0
DDR_B _DQS#1
DDR_B _DQS#2
DDR_B _DQS#3
DDR_B _DQS#4
DDR_B _DQS#5
DDR_B _DQS#6
DDR_B _DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14

DDR_B_BS #0 <17>
DDR_B_BS #1 <17>
DDR_B_BS #2 <17>

DDR_B _RAS# <17>
DDR_B _CAS# <17>
DDR_B _WE# <17>

DDR_B _DM[0..7] <17>

DDR_ B_DQS[0.. 7] <17>

DDR_B _DQS#[0.. 7] <17>

DDR_B _MA[0..14] <17>

CPN:SA00002JT3L(GM45) for Discrete and UMA

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

Cantiga(2/6)-DDR2 A/B CH

LA-5162P

1

11 60Monday , April 20, 2009

0.2

5

+3VS

R57

1@

GMCH _EDID_CLK_ LCD

1 2

2.2K_0402_5%~D
R62

1@

GMCH _EDID_DAT_LC D

D D

C C

B B

1 2

2.2K_0402_5%~D

150_0402_1%

12

1@

R75

INVT_PWM< 19,30>

+3VS

GMCH_EN BKL

R81 10K_0402_5%~D1@

R80 10K_0402_5%~D1@

GMCH _EDID_CLK_ LCD
GMCH _EDID_DAT_LC D
GMCH _LVDDEN

GMCH_LV DSAC­GMCH_LV DSAC+

GMCH_LVDSA0­GMCH_LVDSA1­GMCH_LVDSA2-

GMCH_LVDSA0+
GMCH_LVDSA1+
GMCH_LVDSA2+

GMCH_ENBKL<19>

GMCH _EDID_CLK_L CD<19>

GMCH_ EDID_DAT_LCD<19>

GMCH_ LVDDEN<19>

GMCH_LVDS AC-<19>
GMCH_LVDSAC +<19>

GMCH_LVDSA0-<19>
GMCH_LVDSA1-<19>
GMCH_LVDSA2-<19>

GMCH_LVDSA0+<19>
GMCH_LVDSA1+<19>
GMCH_LVDSA2+<19>

CRT_B
CRT_G
CRT_R

150_0402_1%

150_0402_1%

12

12

1@

1@

R74

R76

@

0_0402_5%

1 2

R119

1@

1 2

100K_0402_5%~D

1 2
1 2

R94 2.4K_0402_1%~D1@

T38

T46

R37 75_0402_5%~D
R63 75_0402_5%~D
R50 75_0402_5%~D

CRT_B<19>

CRT_G<19>

CRT_R<19>

3VDD CCL<19>
3VDD CDA<19>

CRT _HSYNC<19>

R334 1K_0402_1%1@

CRT _VSYNC<19>

R314

1 2

1 2
1 2
1 2

INVT_PW M_GMCH

GMCH_LVDSA3-

GMCH_LVDSA3+

CRT_B

CRT_G

CRT_R

3VDD CCL
3VDD CDA
CRT _HSYNC

12

CTRL_CLK
CTRL_DATA

CRT _VSYNC

4

U4C

L32

L_BKLT_CT RL

G32

L_BKLT_EN

M32

L_CTRL_C LK

M33

L_CTRL_D ATA

K33

L_DDC_CL K

J33

L_DDC_DATA

M29

L_VDD_EN

C44

LVDS_IBG

B43

LVDS_VBG

E37

LVDS_VREFH

E38

LVDS_VREFL

C41

LVDSA_CLK#

C40

LVDSA_CLK

B37

LVDSB_CLK#

A37

LVDSB_CLK

H47

LVDSA_DATA#_0

E46

LVDSA_DATA#_1

G40

LVDSA_DATA#_2

A40

LVDSA_DATA#_3

H48

LVDSA_DATA_0

D45

LVDSA_DATA_1

F40

LVDSA_DATA_2

B40

LVDSA_DATA_3

A41

LVDSB_DATA#_0

H38

LVDSB_DATA#_1

G37

LVDSB_DATA#_2

J37

LVDSB_DATA#_3

B42

LVDSB_DATA_0

G38

LVDSB_DATA_1

F37

LVDSB_DATA_2

K37

LVDSB_DATA_3

F25

TVA_DAC

H25

TVB_DAC

K25

TVC_DAC

H24

TV_RTN

C31

TV_DCONSEL_0

E32

TV_DCONSEL_1

E28

CRT_BLUE

G28

CRT_GREEN

J28

CRT_RED

G29

CRT_IRTN

H32

CRT_DDC_ CLK

J32

CRT_DDC_ DATA

J29

CRT_HSYNC

E29

CRT_TVO_IREF

L29

CRT_VSYNC

CANTIGA ES_FCBGA1329

3

R95 wi thin 500 mils from
pin T 37,T36

T37

PEG_COMPI

T36

PEG_COMPO

H44

PEG_RX#_0

J46

PEG_RX#_1

L44

PEG_RX#_2

L40

PEG_RX#_3

N41

PEG_RX#_4

P48

PEG_RX#_5

N44

PEG_RX#_6

T43

PEG_RX#_7

U43

PEG_RX#_8

Y43

PEG_RX#_9

Y48

PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

Y36
AA43
AD37
AC47
AD39

H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40

J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46

J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46

LVDS TV VGA

PCI-EXPRESS GRAPHICS

1 2

R95 49.9_0402_1%

CG568 0.1U _0402_16V7K~D2@
CG537 0.1U _0402_16V7K~D2@
CG538 0.1U _0402_16V7K~D2@
CG539 0.1U _0402_16V7K~D2@
CG540 0.1U _0402_16V7K~D2@
CG541 0.1U _0402_16V7K~D2@
CG542 0.1U _0402_16V7K~D2@
CG543 0.1U _0402_16V7K~D2@
CG544 0.1U _0402_16V7K~D2@
CG545 0.1U _0402_16V7K~D2@
CG546 0.1U _0402_16V7K~D2@
CG547 0.1U _0402_16V7K~D2@
CG548 0.1U _0402_16V7K~D2@
CG549 0.1U _0402_16V7K~D2@
CG550 0.1U _0402_16V7K~D2@
CG551 0.1U _0402_16V7K~D2@

CG552 0.1U _0402_16V7K~D2@
CG553 0.1U _0402_16V7K~D2@
CG554 0.1U _0402_16V7K~D2@
CG555 0.1U _0402_16V7K~D2@
CG556 0.1U _0402_16V7K~D2@
CG557 0.1U _0402_16V7K~D2@
CG558 0.1U _0402_16V7K~D2@
CG559 0.1U _0402_16V7K~D2@
CG560 0.1U _0402_16V7K~D2@
CG561 0.1U _0402_16V7K~D2@
CG562 0.1U _0402_16V7K~D2@
CG563 0.1U _0402_16V7K~D2@
CG564 0.1U _0402_16V7K~D2@
CG565 0.1U _0402_16V7K~D2@
CG566 0.1U _0402_16V7K~D2@
CG567 0.1U _0402_16V7K~D2@

1 2

R93 0_0402_5%1@

PEG_NRX_G TX_N[0..15] <34>

PEG_NRX_G TX_P[0..15] <34>

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

PEG_NRX_GTX_N0
PEG_NRX_GTX_N1
PEG_NRX_GTX_N2
PEG_NRX_GTX_N3
PEG_NRX_GTX_N4
PEG_NRX_GTX_N5
PEG_NRX_GTX_N6
PEG_NRX_GTX_N7
PEG_NRX_GTX_N8
PEG_NRX_GTX_N9
PEG_NRX_GTX_N10
PEG_NRX_GTX_N11
PEG_NRX_GTX_N12
PEG_NRX_GTX_N13
PEG_NRX_GTX_N14
PEG_NRX_GTX_N15

PEG_NRX_GTX_P0
PEG_NRX_GTX_P1
PEG_NRX_GTX_P2
PEG_NRX_GTX_P3
PEG_NRX_GTX_P4
PEG_NRX_GTX_P5
PEG_NRX_GTX_P6
PEG_NRX_GTX_P7
PEG_NRX_GTX_P8
PEG_NRX_GTX_P9
PEG_NRX_GTX_P10
PEG_NRX_GTX_P11
PEG_NRX_GTX_P12
PEG_NRX_GTX_P13
PEG_NRX_GTX_P14
PEG_NRX_GTX_P15

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5 PEG_NTX_C_GRX_N5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10

PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

PEG_TXP3
PEG_TXN3
PEG_TXP2
PEG_TXN2
PEG_TXP1
PEG_TXN1
PEG_TXP0
PEG_TXN0
PEG_NRX_GTX_P3

PEG COM P tr ace wi dth

+VCCP

and sp aci ng i s 20/ 25 mils.

PEG_NTX_C_GRX_N0
PEG_NTX_C_GRX_N1
PEG_NTX_C_GRX_N2
PEG_NTX_C_GRX_N3
PEG_NTX_C_GRX_N4

PEG_NTX_C_GRX_N6
PEG_NTX_C_GRX_N7
PEG_NTX_C_GRX_N8

PEG_NTX_C_GRX_N9
PEG_NTX_C_GRX_N10
PEG_NTX_C_GRX_N11PEG_TXN11
PEG_NTX_C_GRX_N12
PEG_NTX_C_GRX_N13
PEG_NTX_C_GRX_N14
PEG_NTX_C_GRX_N15

PEG_NTX_C_GRX_P0

PEG_NTX_C_GRX_P1

PEG_NTX_C_GRX_P2

PEG_NTX_C_GRX_P3

PEG_NTX_C_GRX_P4

PEG_NTX_C_GRX_P5

PEG_NTX_C_GRX_P6

PEG_NTX_C_GRX_P7

PEG_NTX_C_GRX_P8

PEG_NTX_C_GRX_P9
PEG_NTX_C_GRX_P10
PEG_NTX_C_GRX_P11
PEG_NTX_C_GRX_P12
PEG_NTX_C_GRX_P13
PEG_NTX_C_GRX_P14
PEG_NTX_C_GRX_P15

PEG_TXP3 <20>
PEG_TXN3 <20>
PEG_TXP2 <20>
PEG_TXN2 <20>
PEG_TXP1 <20>
PEG_TXN1 <20>
PEG_TXP0 <20>
PEG_TXN0 <20>

HDMI_ HPD# <20>

2

PEG_NTX_ C_GRX_N[0..15] <34>

PEG_NTX_ C_GRX_P[0..15] <34>

Only For HDMI

Strap Pin Table

CFG[2: 0] FSB Freq select

CFG[4:3]

CFG5 ( DMI select)

CFG6

CFG 7 (Intel M anagement
Eng ine Crypto strap)

CFG8

CFG9

(PCIE Graphics La ne Reversal)

CFG10 (PCIE Lookb ack enable)

CFG11

CFG[13:12] (XOR/ALLZ)

CFG[15:14]

CFG16 (FSB Dynamic ODT)

CFG[18:17]

CFG19 (DMI L ane Reversal)

CFG20 (PCIE/SDVO con current)

R66 2.21K_0402_1%~D@

CFG5<10>

R1058 2.21K_0402_1%~D@

CFG6<10>

R59 2.21K_0402_1%~D@

CFG7<10>

R55 2.21K_0402_1%~D@

CFG9<10>

R70 2.21K_0402_1%~D@

CFG16<10>

CFG[5:16] have internal pull-up

R72 4.02K_0402_1%~D@

CFG19<10>

R73 4.02K_0402_1%~D@

CFG20<10>

1

000 = FSB 1066MHz
010 = FSB 800MHz
011 = FSB 667MHz
Others = Reserved

Reserved

0 = DMI x 2
1 = DMI x 4
0 = The iTPM Host Interface is enable

1 = The iTPM Host Interface is disable

0 =(TLS)chiper suite with no confidentiality

1 =(TLS)chiper suite with confidentiality

*

*

Reserved

0 = R everse Lane,15->0, 14->1

1 = Normal Operation,Lane Number in order

0 = Enable

1 = Disable

*

Reserved

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled

Reserved

0 = Disabled

1 = Enabled

Reserved

0 = Normal Operation
(Lane number in Order)

1 = Reverse Lane

0 = Only PCIE or SDVO is operational.

1 = PCIE/SDVO are operating simu.

1 2

1 2

1 2

1 2

1 2

1 2

1 2

(Default)11 = Normal Operation

*

*

+3VS

*

*

*

*

*

CFG[19:20] have internal pull-down

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Cantiga(3/6)-VGA/LVDS/TV

Size Doc ument Num ber R ev

Cust om

LA -5 162 P

2

Date: Sheet o f

1

12 60Monday, Apr il 20, 20 09

0.2

5

+VCCP +1.05VS_DPLLA

D D

10U_FLC-453232-1 00K_0.25A_10%

+VCCP +1.05VS_MPLL

1 2

0.15 UH_LQH32CNR15M33L_20%_1210 ~D

C C

+VCCP

B B

+1.5VS

BLM18PG181SN1_0 603~D

A A

L13

10U_FLC-453232-1 00K_0.25A_10%

L9

BLM21PG221SN1D_0 805~D

1 2

12

+1.05VS_DP LLB

L14

12

C174

R132

1 2

0_0402_5%

C29

1 2

22U_0805_6.3VAM

40 mils

1@

0_0603_5%

L12

12

R137

1 2

1_0402_5%~D

C179

1 2

10U_0805_10V4 Z~D

R64

1@

12

0_0805_5%

0.1U_0402_16V7K~D

L3

0.1U_0402_16V7K~D

1

2

+1.8V_TXLVDS+1.8VS

R350

12

1@

C413

+1.5VS_TV DAC

1@

1

C114

2

+1.5VS_QDA C

1

C98

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

+

C27

2

0.1U_0402_16V7K~D

1

2

1000P_0402_50V7K~D

0_0402_5%

1

2

+1.05VS_PEGPLL

C176

0.01U_0402_16V7K

1@

1

C30

2

0.01U_0402_16V7K

1

C97

2

1

2

C173

220U_ D2_4VY_R15M

0_0402_5%

C63

12

1

2

0_0402_5%

+3VS_DA C_CRT

1

+

C191

2

12

@

RG165

2@

RG22

0.1U_0402_16V7K~D

+3VS_DA C_CRT

2@

12

RG102

4

1@

0_0402_5%

220U_ D2_4VY_R15M

0_0402_5%

12

@

RG164

MBK2012121YZF _0805

12

1@

0_0603_5%~D

0.01U_0402_16V7K

1@

1@

1

C402

C401

2

+1.05VS_HPLL

R836

12

0.1U_0402_16V7K~D

L29

+1.5VS

R79

0.1U_0402_16V7K~D

1

2

0.1U_0402_16V7K~D

+3VS

1@

BLM18PG181SN1_0 603~D

+3VS_DAC_BG

0.01U_0402_16V7K

1@

1

1

C408

2

2

+1.05VS_HPLL+VCCP

12

4.7U_0603_10V6K

2

C28

1

1

C175

0.1U_0402_16V 7K~D

2

+VCCP

100U_D2E_6.3VM_R18M~D

1

2

2@

0_0402_5%

12

+1.5VS

RG134

0_0402_5%

1 2

0.1U_0402 _16V4Z

1

2

+1.05VS_PEGPLL

1

C33

2

0_0402_5%

1@

C405

0.1U_0402_16V7K~D

+

C31

1@

R67

1@

C1413

L11

12

12

2@

RG13

C388

1

2

+1.05VS_PEGPLL

22U_0805_6.3V6M~D

1

2

R86 0_0402_5%2@

+1.5VS_TV DAC

+1.5VS_Q DAC

0.1U_0402_16V7K~D

2

1

+1.8VS

+3VS_DAC_CRT

0.1U_0402_16V7K~D

1

2

+1.05VS_HPLL

+1.05VS_MPLL

+1.8V_TXLVDS

4.7U_0805 _10V4Z~D

1

C82

C83

2

22U_0805_6.3V6M~D

1

C123

C104

2

1 2

C233

+1.8V_LVDS

R110

1@

0_0603_5%

0.01U_0402_16V7K

1@

1@

1

C411

C407

2

2.6 8mA

64. 8mA

64. 8mA

139 .2m A

13. 2mA

414 uA

720 mA

1U_0603_10V6K~D

1

C72

2

0.1U_0402_16V7K~D

1

2

TVA 24 .15 mA
TVB 39 .48 mA
TVX 24 .15 mA

50 mA

58. 67m A

48. 363 mA

157 .2m A

50 mA

60. 31m A

12

1@

1U_0603_10V6K~D

0_0603_5%~D

1

C186

2

24 mA

50 mA

26 mA

0_0402_5%

73 mA

12

2@

RG162

12

AD48

AA48

AR20

AP20
AN20
AR17

AP17
AN17

AT16
AR16

AP16

AP28
AN28

AP25
AN25
AN24
AM28
AM26
AM25

AL25
AM24

AL24
AM23

AL23

AA47

3

2@

RG7

U4H

B27

VCCA_CRT_DAC_1

A26

VCCA_CRT_DAC_2

A25

VCCA_DAC_BG

B25

VSSA_DAC_BG

F47

VCCA_DPLLA

L48

VCCA_DPLLB

AD1

VCCA_HPLL

AE1

VCCA_MPLL

J48

VCCA_LVDS

J47

VSSA_LVDS

VCCA_PEG_BG

VCCA_PEG_PLL

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_6
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9

VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_SM_CK_3
VCCA_SM_CK_4
VCCA_SM_CK_5
VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2
VCCA_SM_CK_NCTF_3
VCCA_SM_CK_NCTF_4
VCCA_SM_CK_NCTF_5
VCCA_SM_CK_NCTF_6
VCCA_SM_CK_NCTF_7
VCCA_SM_CK_NCTF_8

B24

VCCA_TV_DAC_1

A24

VCCA_TV_DAC_2

A32

VCC_HDA

M25

VCCD_TVDAC

L28

VCCD_QDAC

AF1

VCCD_HPLL

VCCD_PEG_PLL

M38

VCCD_LVDS_1

L37

VCCD_LVDS_2

CANTIGA E S_FCBGA1329

POWER

HDA

A SM

LVDS D TV/CRT

CRTPLLA LVDSA PEG

TV

VTT

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

AXF

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

VCC_TX_LVDS

A CK

HV

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5

VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4

DMI PEG

VTTLF

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8

VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25

VCC_HV_1
VCC_HV_2
VCC_HV_3

VTTLF1
VTTLF2
VTTLF3

U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1

B22
B21
A21

BF21
BH20
BG20
BF20

K47

C35
B35
A35

V48
U48
V47
U47
U46

AH48
AF48
AH47
AG47

A8
L1
AB2

456 mA

852 mA

321 .35 mA

124 mA

118 .8m A

173 2mA

20mils

+VTTLF1
+VTTLF2
+VTTLF3

0.47U_0402_10V4Z~D

C382

4.7U_0805 _10V4Z~D

1

C384

2

+1.8V_TXLVDS

105 .3m A

0.47U_0402_10V4Z~D

C385

1

2

1

2

C383

+VCCP

10U_0805_10V4Z~D

C65

2

0.47U_040 2_10V4Z~D

1

2

@

C113

1

2

+1.8V_SM_CK

1_0402_5%~D

C96

0.1U_0402_16V7K~D

1

2

0.47U_0402_10V4Z~D

1

2

4.7U_0805 _10V4Z~D

1

1

C373

C56

2

2

1U_0603_10V6K~D

C69

1

2

1UH_L QM21FN1R0N00D_30%_0805~ D

R139

0.1U_0402_16V7K~D

1

C102

10U_0805_10V4Z~D

1

2

2

+VCCP

220U_ D2_4VY_R15M

22U_0805_6.3V6M~D

1

2

+

C116

C95

C117

2

1

+VCCP

2.2U_0805 _16V4Z

C370

1 2

4.7U_0805 _10V4Z~D

1

2

1

220U_ D2_4VY_R15M

1

+

2

+1.8V

L4

+3VS

0.1U_0402_16V7K~D

1

C410

2

C389

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

2

Title

Size D ocumen t Number Re v

Cust om

Date : Sheet o f

Compal Electronics, Inc.

Cantiga(4/6)-PWR

LA -5 16 2P

1

13 60Monday, A pril 20, 200 9

0.2

5

Extnal Graphic: 1210.34mA
integrated Graphic: 1930.4mA

U4G

AG34

VCC_1

AC34

VCC_2

AB34

VCC_3

AA34

VCC_4

Y34

VCC_5

V34

D D

+VCCP

220U_ D2_4VY_R15M

22U_0805_6.3V6M~D

1

+

C374

2

C C

B B

A A

0.22U_0402_10V4 Z

0.22U_0402_10V4 Z

C118

1

2

0.1U_0402_16V7K~D

C119

C143

1

2

C120

1

1

2

2

VCC_6

U34

VCC_7

AM33

VCC_8

AK33

VCC_9

AJ33

VCC_10

AG33

VCC_11

AF33

VCC_12

AE33

VCC_13

AC33

VCC_14

AA33

VCC_15

Y33

VCC_16

W33

VCC_17

V33

VCC_18

U33

VCC_19

AH28

VCC_20

AF28

VCC_21

AC28

VCC_22

AA28

VCC_23

AJ26

VCC_24

AG26

VCC_25

AE26

VCC_26

AC26

VCC_27

AH25

VCC_28

AG25

VCC_29

AF25

VCC_30

AG24

VCC_31

AJ23

VCC_32

AH23

VCC_33

AF23

VCC_34

T32

VCC_35

CANTI GA ES_FCBGA1329

VCC CORE

POWER

VCC NCTF

4

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8

VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44

AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23

+VCCP

3

+1.8V

330U_ D2_2.5VY_R9M

1

C148

+

2

Co-Layout Component

Location

0_0805_5%~D

12

C80
RG163

+1.05V_VCCP

0.47U_0402_10V4 Z~D

1U_0603_10V6K~D

@

1

C140

RG163

2

Layout Note: Inside GMCH
cavity for VCC_AXG.

0.1U_0402_16V7K~D

1

1

C78

2

2

2

U4F

3000mA

0.1U_0402_16V7K~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

C147

C165

1

1

2

2

6326. 84mA

22U_0805_6.3V6M~D

10U_0805_10V4Z~D

0.1U_0402_16V7K~D

C66

1

1

1

C79

C100

2

2

2

T42
T43

AP33

VCC_SM_1

AN33

VCC_SM_2

BH32

VCC_SM_3

BG32

VCC_SM_4

BF32

C164

2

1

C80

BD32
BC32
BB32
BA32
AY32

AW32

AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29

AW29

AV29
AU29
AT29
AR29
AP29

BA36
BB24
BD16

BB21
AW16
AW13

AT13

AE25

AB25

AA25

AE24

AC24

AA24

AE23

AC23

AB23

AA23

AJ21
AG21
AE21
AC21
AA21

AH20
AF20
AE20
AC20
AB20
AA20

AM15

AL15
AE15

AJ15
AH15
AG15
AF15
AB15
AA15

AN14
AM14

AJ14
AH14

Y26

Y24

Y21

T17
T16

Y15
V15

U15

U14

T14

VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35

VCC_SM_36/NC
VCC_SM_37/NC
VCC_SM_38/NC
VCC_SM_39/NC
VCC_SM_40/NC
VCC_SM_41/NC
VCC_SM_42/NC

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42

VCC_AXG_SENSE
VSS_AXG_SENSE

VCC_AXG_NTCF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC SM

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43

VCC GFX NCTF

VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52

POWER

VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60

VCC GFX

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16

AV44
BA37
AM40
AV21
AY5
AM10
BB13

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

VCC SM LF

CANTI GA ES_FCBGA1329

+1.05V_VCCP +VCCP

330U_ D2_2.5VY_R9M

1

1

C86

+

+

2

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.22U_0603_10V7K

1

1

C71

C70

2

2

1

PJP21

JUMP_43X118

2

Short

PJP24

JUMP_43X118

2

Short

112

112

330U_ D2_2.5VY_R9M

C57

Layout Note:

Place close to GMCH

0.22U_0603_10V7K

0.47U_0402_10V4 Z~D
C146

1

1

C67

2

1

C81

2

2

1U_0603_10V6K~D

1U_0603_10V6K~D

1

1

C145

C163

2

2

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

Title

Cantiga(5/6)-PWR/GND

Size Doc ument Number Re v

Cus tom

LA-5162P

2

Date: Sheet

1

0.2

of

14 60Monday , April 20, 2009

Compal Electronics, Inc.

5

U4I

AU48

VSS_1

AR48

VSS_2

AL48

VSS_3

BB47

VSS_4

AW47

VSS_5

AN47

VSS_6

AJ47

VSS_7

AF47

D D

C C

B B

A A

VSS_8

AD47

VSS_9

AB47

VSS_10

Y47

VSS_11

T47

VSS_12

N47

VSS_13

L47

VSS_14

G47

VSS_15

BD46

VSS_16

BA46

VSS_17

AY46

VSS_18

AV46

VSS_19

AR46

VSS_20

AM46

VSS_21

V46

VSS_22

R46

VSS_23

P46

VSS_24

H46

VSS_25

F46

VSS_26

BF44

VSS_27

AH44

VSS_28

AD44

VSS_29

AA44

VSS_30

Y44

VSS_31

U44

VSS_32

T44

VSS_33

M44

VSS_34

F44

VSS_35

BC43

VSS_36

AV43

VSS_37

AU43

VSS_38

AM43

VSS_39

J43

VSS_40

C43

VSS_41

BG42

VSS_42

AY42

VSS_43

AT42

VSS_44

AN42

VSS_45

AJ42

VSS_46

AE42

VSS_47

N42

VSS_48

L42

VSS_49

BD41

VSS_50

AU41

VSS_51

AM41

VSS_52

AH41

VSS_53

AD41

VSS_54

AA41

VSS_55

Y41

VSS_56

U41

VSS_57

T41

VSS_58

M41

VSS_59

G41

VSS_60

B41

VSS_61

BG40

VSS_62

BB40

VSS_63

AV40

VSS_64

AN40

VSS_65

H40

VSS_66

E40

VSS_67

AT39

VSS_68

AM39

VSS_69

AJ39

VSS_70

AE39

VSS_71

N39

VSS_72

L39

VSS_73

B39

VSS_74

BH38

VSS_75

BC38

VSS_76

BA38

VSS_77

AU38

VSS_78

AH38

VSS_79

AD38

VSS_80

AA38

VSS_81

Y38

VSS_82

U38

VSS_83

T38

VSS_84

J38

VSS_85

F38

VSS_86

C38

VSS_87

BF37

VSS_88

BB37

VSS_89

AW37

VSS_90

AT37

VSS_91

AN37

VSS_92

AJ37

VSS_93

H37

VSS_94

C37

VSS_95

BG36

VSS_96

BD36

VSS_97

AK15

VSS_98

AU36

VSS_99

CANTI GA ES_FCBGA1329

CIS Link:OK

VSS

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199

4

AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6

3

U4J

BG21

VSS_199

L12

VSS_200

AW21

VSS_201

AU21

VSS_202

AP21

VSS_203

AN21

VSS_204

AH21

VSS_205

AF21

VSS_206

AB21

VSS_207

R21

VSS_208

M21

VSS_209

J21

VSS_210

G21

VSS_211

BC20

VSS_212

BA20

VSS_213

AW20

VSS_214

AT20

VSS_215

AJ20

VSS_216

AG20

VSS_217

Y20

VSS_218

N20

VSS_219

K20

VSS_220

F20

VSS_221

C20

VSS_222

A20

VSS_223

BG19

VSS_224

A18

VSS_225

BG17

VSS_226

BC17

VSS_227

AW17

VSS_228

AT17

VSS_229

R17

VSS_230

M17

VSS_231

H17

VSS_232

C17

VSS_233

BA16

VSS_235

AU16

VSS_237

AN16

VSS_238

N16

VSS_239

K16

VSS_240

G16

VSS_241

E16

VSS_242

BG15

VSS_243

AC15

VSS_244

W15

VSS_245

A15

VSS_246

BG14

VSS_247

AA14

VSS_248

C14

VSS_249

BG13

VSS_250

BC13

VSS_251

BA13

VSS_252

AN13

VSS_255

AJ13

VSS_256

AE13

VSS_257

N13

VSS_258

L13

VSS_259

G13

VSS_260

E13

VSS_261

BF12

VSS_262

AV12

VSS_263

AT12

VSS_264

AM12

VSS_265

AA12

VSS_266

J12

VSS_267

A12

VSS_268

BD11

VSS_269

BB11

VSS_270

AY11

VSS_271

AN11

VSS_272

AH11

VSS_273

Y11

VSS_275

N11

VSS_276

G11

VSS_277

C11

VSS_278

BG10

VSS_279

AV10

VSS_280

AT10

VSS_281

AJ10

VSS_282

AE10

VSS_283

AA10

VSS_284

M10

VSS_285

BF9

VSS_286

BC9

VSS_287

AN9

VSS_288

AM9

VSS_289

AD9

VSS_290

G9

VSS_291

B9

VSS_292

BH8

VSS_293

BB8

VSS_294

AV8

VSS_295

AT8

VSS_296

CANTI GA ES_FCBGA1329

VSS

VSS N CTF

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16

VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5

VSS S CB

NC

2

VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325

VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350

VSS_351
VSS_352
VSS_353
VSS_354

NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42

AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4

BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1

U24
U28
U25
U29

AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17

BH48
BH1
A48
C1
A3

E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48

1

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

Cantiga(6/6)-PWR/GND

LA-5162P

1

15 60Monday , April 20, 2009

0.2

5

D D

Lay out No te:
Pl ac e ne ar J DIM MA

+1.8V

2.2U_0603_6.3V6K~ D

C105

1

2

C C

Lay out No te:
Pl ac e one c ap cl ose to e very 2 pul lup
res is tor s t er mina ted to +0. 9V

+0.9VS

0.1U_0402_16V7K~D

1

C106

2

B B

A A

2.2U_0603_6.3V6K~ D

1

2

0.1U_0402_16V7K~D

1

C125

2

2.2U_0603_6.3V6K~ D

C149

C124

1

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

1

C126

2

2

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

DDR_C S0_DIMMA#
DDR_A _RAS#

DDR_A_MA10
DDR_A_BS #0

DDR_A_W E#
DDR_A _CAS#

M_ODT1
DDR_C S1_DIMMA#

DDR_CKE 1_DIMMA

5

2.2U_0603_6.3V6K~ D

2.2U_0603_6.3V6K~ D

C166

1

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

C127

C150

2

La yout Note :
Pl ac e th es e r esi stor
cl osel y J DIM MA,a ll
tr ace len gth Max= 1.5"

RP14

1 4
2 3

56_0404_4P2R_5%

RP13

1 4
2 3

RP7

56_0404_4P2R_5%

1 4
2 3

RP6

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

RP5

1 4
2 3

56_0404_4P2R_5%

RP1

2 3
1 4

56_0404_4P2R_5%

1 2

R96 56_0402_ 5%

1

2

1

2

C169

C151

+0.9VS

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

C154

1

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

1

C167

2

2

RP22 56_0404_4P2R_5%

14
23

RP17 56_0404_4P2R_5%

14
23

RP15 56_0404_4P2R_5%

14
23

RP16 56_0404_4P2R_5%

14
23

RP8 56_0404_4P2R_5%

14
23

RP2 56_0404_4P2R_5%

14
23

RP23 56_0404_4P2R_5%

14
23

C131

1

2

0.1U_0402_16V7K~D

C107

DDR_CKE 0_DIMMA
DDR_A_BS #2

DDR_A_MA6
DDR_A_MA7

DDR_A_MA12
DDR_A_MA9

DDR_A_MA2
DDR_A_MA4

DDR_A_BS #1
DDR_A_MA0

DDR_A_MA13
M_ODT0

DDR_A_MA11
DDR_A_MA14

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

C128

2

C108

C130

1

1

2

2

0.1U_0402_16V7K~D

1

1

C129

C152

2

2

4

Close to VREF pins of SO-DIMM

+V_DD R_MCH_REF

0.1U_0402_16V7K~D

2.2U_0805_16V4Z

1

1

C201

2

2

330U_ D2_2.5VY_R9M

1

@

C84

+

2

DDR_C KE0_DIMMA<10>

DDR_A_BS #2<11>

DDR_A_BS #0<11>
DDR_A_W E#<11>

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

2

1

1

C153

C22

C168

2

2

4

DDR_A _CAS#<11>

DDR_C S1_DIMMA#<10>

M_ODT1<10>

ICH_SM_DA<6,17, 23,27,28>
ICH_SM_CLK<6,17, 23,27,28>

+3VS

C58

0.1U_0402_16V7K~D

3

+1.8V +1.8V

ME@

JDIMMA

C220

DDR_A _D0
DDR_A _D1

DDR_A _DQS#0
DDR_A _DQS0

DDR_A _D2
DDR_A _D3

DDR_A _D8
DDR_A _D9

DDR_A _DQS#1
DDR_A _DQS1

DDR_A _D10
DDR_A _D11

DDR_A _D16
DDR_A _D17

DDR_A _DQS#2
DDR_A _DQS2

DDR_A _D19

DDR_A _D24
DDR_A _D25

DDR_A_DM 3

DDR_A _D26
DDR_A _D27

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10

DDR_A _D32
DDR_A _D33

DDR_A _DQS#4
DDR_A _DQS4

DDR_A _D34
DDR_A _D35

DDR_A _D40
DDR_A _D41

DDR_A_DM 5

DDR_A _D42
DDR_A _D43

DDR_A _D48
DDR_A _D49

DDR_A _DQS#6
DDR_A _DQS6

DDR_A _D50
DDR_A _D51

DDR_A _D56
DDR_A _D57

DDR_A_DM 7

DDR_A _D58
DDR_A _D59

1

2

1

2

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

C59

2.2U_06 03_6.3V6K~D

TYCO_292526-4

SO-DIMM A

STANDARD TYPE

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

BA1
RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SA0

SA1

2

DDR_A _D4

4

DDR_A _D5

6
8

DDR_A_DM 0

10
12

DDR_A _D6

14

DDR_A _D7

16
18

DDR_A _D12

20

DDR_A _D13

22
24

DDR_A_DM 1

26
28
30
32
34

DDR_A _D14

36

DDR_A _D15

38
40

42

DDR_A _D20

44

DDR_A _D21

46
48
50

NC

A11

A7
A6

A4
A2
A0

S0#

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_DM 2

DDR_A _D22DDR_A _D18
DDR_A _D23

DDR_A _D28
DDR_A _D29

DDR_A _DQS#3
DDR_A _DQS3

DDR_A _D30
DDR_A _D31

DDR_A_MA14

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_MA13

DDR_A _D36
DDR_A _D37

DDR_A_DM 4

DDR_A _D38
DDR_A _D39

DDR_A _D44
DDR_A _D45

DDR_A _DQS#5
DDR_A _DQS5

DDR_A _D46
DDR_A _D47

DDR_A _D52
DDR_A _D53

DDR_A_DM 6

DDR_A _D54
DDR_A _D55

DDR_A _D60
DDR_A _D61

DDR_A _DQS#7
DDR_A _DQS7

DDR_A _D62
DDR_A _D63

CIS Link:OK 12/29

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

2

M_CLK_DD R0 <10>
M_CLK_DD R#0 <10>

PM_EXTTS#0 <10>

DDR_C KE1_DIMMA <10>

DDR_A_BS #1 <11>
DDR_A _RAS# <11>
DDR_C S0_DIMMA# <10>

M_ODT0 <10>

M_CLK_DD R1 <10>
M_CLK_DD R#1 <10>

12

12

R32

R31

10K_0402_5%~D

10K_0402_5%~D

2

1

DDR_A _DQS#[0.. 7] <11>

DDR_ A_D[0..63 ] <11>

DDR_A _DM[0..7] <11>

DDR_A _DQS[0..7 ] <11>

DDR_A _MA[0..14] <11>

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

DDR2 SO-DIMM A

LA-5162P

1

16 60Monday , April 20, 2009

0.2

5

4

3

2

1

Close to VREF pins of SO-DIMM

+1.8V

ME@

JDIMMB

2.2U_0805_16V4Z

0.1U_0402_16V7K~D

1

1

C225

C226

2

2

D D

Lay out No te:
Pl ac e ne ar J DIM MB

+1.8V

2.2U_06 03_6.3V6K~D

C160

1

2

0.1U_0402_16V7K~D

1

1

2

2

C135

C156

DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS #0

DDR_B_BS #1
DDR_B_MA0

DDR_C S2_DIMMB#
DDR_B _RAS#

DDR_B _CAS#
DDR_B_W E#

M_ODT3
DDR_C S3_DIMMB#

DDR_CKE 3_DIMMB

5

2.2U_06 03_6.3V6K~D

2.2U_06 03_6.3V6K~D

C138

1

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

2

C157

La yout Note :
Pl ac e th es e r esi stor
cl osel y J DIMMB, all
tr ace len gth Max= 1.5"

RP18

1 4
2 3

RP10

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

RP12

1 4
2 3

RP11

56_0404_4P2R_5%

1 4
2 3

RP9

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

RP3

2 3
1 4

56_0404_4P2R_5%

1 2

R335 56_04 02_5%

C177

1

2

0.1U_0402_16V7K~D

1

1

2

2

C170

C171

+0.9VS

C132

C109

1

1

2

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

2

C111

RP24 56_0404_4P2R_5%

14
23

RP26 56_0404_4P2R_5%

14
23

RP19 56_0404_4P2R_5%

14
23

RP21 56_0404_4P2R_5%

14
23

RP20 56_0404_4P2R_5%

14
23

RP4 56_0404_4P2R_5%

14
23

RP25

14
23

56_0404_4P2R_5%

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

2.2U_06 03_6.3V6K~D

2.2U_06 03_6.3V6K~D

C C

Lay out No te:
Pl ac e one c ap cl ose to e very 2 pul lup
res is tor s t er min ated to + 0.9VS

+0.9VS

0.1U_0402_16V7K~D

B B

A A

C139

C112

1

1

2

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

1

2

2

C134

C110

0.1U_0402_16V7K~D

C133

1

2

0.1U_0402_16V7K~D

1

1

2

2

C136

C158

DDR_B_MA12
DDR_B_MA9

DDR_B_MA11
DDR_B_MA14

DDR_B_MA8
DDR_B_MA5

DDR_B_MA6
DDR_B_MA7

DDR_B_MA2
DDR_B_MA4

DDR_B_MA13
M_ODT2

DDR_CKE 2_DIMMB
DDR_B_BS #2

0.1U_0402_16V7K~D

330U_ D2_2.5VY_R9M

1

@

C155

C189

1

+

2

2

DDR_CKE 2_DIMMB<10>

DDR_B_BS #2<11>

DDR_B_BS #0<11>

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

1

1

2

2

C137

2

C172

C159

4

DDR_B _WE#<11>

DDR_B _CAS#<11>
DDR_C S3_DIMMB#<10>

M_ODT3<10>

ICH_SM_DA<6,16, 23,27,28>
ICH_SM_CLK<6,16, 23,27,28>

0.1U_0402_16V7K~D

+3VS

DDR_B _D2

DDR_B _DQS#0
DDR_B _DQS0

DDR_B _D6
DDR_B _D7

DDR_B _D8
DDR_B _D9

DDR_B _DQS#1
DDR_B _DQS1

DDR_B _D10
DDR_B _D11

DDR_B _D16
DDR_B _D17

DDR_B _DQS#2
DDR_B _DQS2

DDR_B _D18
DDR_B _D19

DDR_B _D24
DDR_B _D25

DDR_B_DM 3

DDR_B _D27

DDR_B_MA12
DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10

DDR_B _D32
DDR_B _D33

DDR_B _DQS#4
DDR_B _DQS4

DDR_B _D34
DDR_B _D35

DDR_B _D40
DDR_B _D41

DDR_B_DM 5

DDR_B _D42
DDR_B _D43

DDR_B _D48
DDR_B _D49

DDR_B _DQS#6
DDR_B _DQS6

DDR_B _D50
DDR_B _D51

DDR_B _D56

DDR_B_DM 7

DDR_B _D58
DDR_B _D59

1

1

C61

2

C60

2.2U_06 03_6.3V6K~D

2

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

TYCO_292526-4

NC/CKE1

NC/A15
NC/A14

NC/A13

81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

SO-DIMM B

STANDARD TYPE

CIS Link:OK 12/29

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.8V+V_DD R_MCH_REF

2

VSS
DQ4
DQ5

VSS
DM0

VSS
DQ6
DQ7

VSS

DQ12
DQ13

VSS
DM1

VSS

CK0

CK0#

VSS

DQ14
DQ15

VSS

VSS

DQ20
DQ21

VSS

NC

DM2

VSS

DQ22
DQ23

VSS

DQ28
DQ29

VSS

DQS3#

DQS3

VSS

DQ30
DQ31

VSS

VDD

VDD

A11

A7
A6

VDD

A4
A2
A0

VDD

BA1

RAS#

S0#

VDD

ODT0

VDD

NC

VSS

DQ36
DQ37

VSS
DM4

VSS

DQ38
DQ39

VSS

DQ44
DQ45

VSS

DQS5#

DQS5

VSS

DQ46
DQ47

VSS

DQ52
DQ53

VSS

CK1

CK1#

VSS
DM6

VSS

DQ54
DQ55

VSS

DQ60
DQ61

VSS

DQS7#

DQS7

VSS

DQ62
DQ63

VSS

SA0

SA1

2009/01/05 2009/01/05

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_B _D1
DDR_B _D4DDR_B _D3

DDR_B_DM 0

DDR_B _D5
DDR_B _D0

DDR_B _D12
DDR_B _D13

DDR_B_DM 1

M_CLK_DD R2 <10>

DDR_B _D14
DDR_B _D15

DDR_B _D20
DDR_B _D21

DDR_B_DM 2

DDR_B _D22
DDR_B _D23

DDR_B _D28
DDR_B _D29

DDR_B _DQS#3
DDR_B _DQS3

DDR_B _D30DDR_B _D26
DDR_B _D31

DDR_B_MA14

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_MA13

DDR_B _D36
DDR_B _D37

DDR_B_DM 4

DDR_B _D38
DDR_B _D39

DDR_B _D44
DDR_B _D45

DDR_B _DQS#5
DDR_B _DQS5

DDR_B _D46
DDR_B _D47

DDR_B _D52
DDR_B _D53

DDR_B_DM 6

DDR_B _D54
DDR_B _D55

DDR_B _D60
DDR_B _D61DDR_B _D57

DDR_B _DQS#7
DDR_B _DQS7

DDR_B _D62
DDR_B _D63

M_CLK_DDR#2 <10>

PM_EXTTS#1 <10>

DDR_CKE 3_DIMMB <10>

DDR_B_BS #1 <11>
DDR_B _RAS# <11>
DDR_CS2_D IMMB# <10>

M_ODT2 <10>

M_CLK_DD R3 <10>
M_CLK_DDR#3 <10>

10K_0402_5%~D

Compal Secret Data

Deciphered Date

R33

1 2

12

10K_0402_5%~D

R34

+3VS

2

DDR_B _DQS#[0.. 7] <11>

DDR_ B_D[0..63 ] <11>

DDR_B _DM[0..7] <11>

DDR_ B_DQS[0.. 7] <11>

DDR_B _MA[0..14] <11>

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

DDR2 SO-DIMM B

LA-5162P

1

17 60Monday , April 20, 2009

0.2

5

D D

4

3

2

1

Thermal Sensor

H_THERMDA<7> SMB_DATA_THERMAL <30,39>

H_THERMDC<7>

C C

C227 2200P_0402_50V7K~D

1 2

1 2

+3VS

R20 10K_0402_5%~D

FAN Control circuit

B B

FAN_SPEED1<30>

+3VS

1

CPN:SA00001Z700

C219

2

0.1U_0402_16V7K~D

H_THERMDA

H_THERMDC

L_THERM#

U14

1

VDD

2

DP

3

DN

4

THERM#

EMC1402-1-ACZL-TR_MSOP8

CIS Link:OK

FAN1_P OWER

1000P_0402_50V7K~D

10U_1206_16V4Z~N

1

1

C221

2

2

+3VS

12

R126

10K_0402_5%~D

2

C218

0.01U_0402_16V7K

1

EN_DF AN1<30>

8

SMCLK

7

SMDATA

6

ALERT#

5

GND

C222

+5VS

CPN:SA000022J00

C223 10U_1206_16V4Z~N

FAN1_P OWER

1 2

U3

1

VEN

2

VIN

3

VO

4

VSET

RT9027BPS SO 8P

40mil

1
2
3

4
5

ACES_87213-0300G

SMB_CLK_THERMAL <30,39>

GND
GND
GND
GND

ME@

JFA N

1
2
3

GND
GND

8
7
6
5

CIS Link:OK 12/29

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Doc ument Number Re v

Date: Sheet of

Compal Electronics, Inc.

FAN & Thermal Sensor

LA-5162P

18 60Monday, A pril 20, 2009

1

1A

A

C R T

RG1 197

2@

ATI _CRT_B< 35>

ATI _CRT_G<35>

ATI _CRT_ R< 35>

1 1

2 2

CR T_R< 12>

R1 200

1@

CR T_G<1 2>

R1 201

1@

CR T_B<12>

R1 202

1@

CR T_H SYN C<12>

AT I_H SYNC<35 ,39>

AT I_VS YNC<3 5,39>

CR T_V SYNC<12>

Close to GMCH Close to ATI

12

0_04 02_5%

RG1 198

2@

12

0_04 02_5%

RG1 199

2@

12

0_04 02_5%

0_04 02_5%

12

0_04 02_5%

12

0_04 02_5%

12

R1 208

C1 447 0 .1U_ 0402_ 16V7K~D

R1 216

1@

CR T_H SY NC

1 2

30_0 402_1%

RG1 218

2@

0_04 02_5%

RG1 220

2@

0_04 02_5%

R1 221

1@

CR T_V SYN C

1 2

30_0 402_1%

CR T_R _C

CR T_G_ C

CR T_B_ C

22P _0402_50 V8J

22P _0402_50 V8J

@

@

1

1

12

150_ 0402_1%

1 2

12

12

R1 209

150_ 0402_1%

CR T_H SYN C_B

12

12

CR T_V SYNC _B D_ CRT _VS YNC

C1 441

C1 442

2

R1 210

150_ 0402_1%

2

+C RT_VC C

1

5

U6 2
74A HCT1G 125GW_S OT353-5

P

4

OE#

A2Y

G

3

C1 454 0 .1U_0 402_1 6V7K~D

1 2

1 2

BLM 18BB 050SN1 D_0603~D

1 2

BLM 18BB 050SN1 D_0603~D

1 2

BLM 18BB 050SN1 D_0603~D

22P _0402_50 V8J

1

@

C1 443

2

+C RT_V CC

B

+3VS

L5

CR T_R_ L

L6

CRT _G_L

L7

CRT _B_L

R1 213

10K _0402_5 %~D

D_ CRT _HS YNC

1

5

U6 3

74A HCT1G 125GW_S OT353-5

P

4

OE#

A2Y

G

3

D4 7

@

DAN 217_S C59-3

1

2

1

C1 444

2

4.7P _040 2_50V8C

12

DAN 217_S C59-3

3

1

C1 445

2

@

4.7P _040 2_50V8C

R1 211

R1 214

D4 8

1

2

DAN 217_S C59-3

3

1

C1 446

2

1 2

1 2

@

2

4.7P _040 2_50V8C

D4 9

1

3

HS YNC _L

0_06 03_5%

VS YN C_L

0_06 03_5%

C1 448

1

2

C

W=40mils

+C RT_VC C

0.1U _0402 _16V7K ~D

1U_0 402_6 .3V6K~ D

1

1

C1 440

C1 439

2

2

MSE N#<30>

C1 449

C1 450

1

2

15P _0402 _50V8J~D

C1 451

1

1

2

2

100P _0402_ 50V8J

15P _0402 _50V8J~D

100P _0402_ 50V8J

D5 0

+5V S_CRT VCC

2

1

3

RB4 91D_S OT23-3

ME@

JC RT

6

11

1
7

12

2
8

CIS Link:OK

13

3
9

14

10
15

SU YIN_ 07054 6FR01 5S29 7ZR

VGA _DDC _DATA _C

VG A_D DC_CL K_C

16

G

4

17

G

5

1.1A _6VD C_FU SE

2

03/03

F7

@

2 1

P WR_ CR

2

Short

+C RT_VC C

2.2K _040 2_5%~D

12

R1 48

D

W=40mils

+5VS

1

1

2.2K _040 2_5%~D

12

R1 49

Q3

SSM 3K70 02FU_SC 70-3

Co-Layout Component

Location

+3VS +3VS_D ELAY

0_04 02_5%

0_04 02_5%

2@

1@

12

12

R2 76

R2 73

2.2K _040 2_5%~D

2

G

1 3

D

S

2

G

1 3

D

SSM 3K70 02FU_SC 70-3

S

Q1

F7

PWR_CRT

+3VS +3VS_D ELAY

0_04 02_5%

0_04 02_5%

1@

12

12

R2 83

2.2K _040 2_5%~D

R1 206

1 2

DD C_DA TA

DD C_C LK

E

2@

R2 84

R1 207

1 2

R1 212 0_0 402_5%1@

R1 215 0_0 402_5%1@

RG 1217 0_0 402_5%2@

RG 1219 0_0 402_5%2@

12

12

12

12

3V DDC DA < 12>

3V DDC CL <12>

AT I_DDC _CLK <35>

ATI _DDC_ DAT <35>

L C D LVDS signal from GMCH

+L CDV DD +5 VALW +3VS

R1 41

D

D9

CH75 1H-4 0PT_S OD323-2

CH75 1H-4 0PT_S OD323-2

R2 03 0_040 2_5%

R6 58

1@

12

0_04 02_5%

RG 657

2@

12

0_04 02_5%

A

1@

2 1

2@

2 1

GM CH_L VDDE N<1 2>

ATI _LVD DEN<35>

3 3

LCD_ VCC_ TEST _EN<30>

BKO FF#<30 >

EC_ ENBK L<3 0>

GMC H_EN BKL<12>

4 4

ATI _ENBKL< 35>

GM CH_ LVDDE N

ATI _LVD DEN

LCD_ VCC_ TES T_EN

BKO FF#

EC_ ENBK L

S

DG 8

12

C3 8 0.1 U_040 2_16V7 K~D@

2N70 02W- 7-F_SO T323-3~D

R1 40

1 2
13

SSM 3K70 02FU_SC 70-3

1 2

1 2

100_ 0603_ 1%~D

Q7

2

G

13

2

G

12

R8 8
100K _040 2_5%~D

D2 6

CH75 1H-4 0PT_S OD323-2

D2 5

@

CH75 1H-4 0PT_S OD323-2

Q34

S

G

2

R1 132

@

1 2

100K _0402_ 5%~D

47K _0402_5 %~D

R1 14 1K_ 0402_5 %~D

D

SSM 3K70 02FU_SC 70-3

S

21

21

EN _I NVPW R

Q9

+3VS

12

R1 021

4.7K _0402 _5%

DI SPO FF#

R1 131

D

13

1 2

100K _0402_ 5%~D

EN _IN VPWR <30>

12

1000 P_0402 _50V7K~D

1

C2 52

2

1

C1 97

0.04 7U_04 02_16V7K

2

100K _0402_ 5%~D

B+

SI3 457BDV- T1-E3_TS OP6~D

12

R1 122

PW R_S RC_ ON

B

W=60mils

Q6

S

AO3 413_SOT23- 3

G

2

D

1 3

10U_ 0805_ 6.3V6-M~ D

1

2

Q36

D

S

4 5

G

3

W=60mils

+L CDV DD

C2 06

INV T_PWM<12,30>

6

2
1

0.1U _0402 _16V7K ~D

1

2

C4 6

LCD_ CBL_ DET#<30>

@

C1 016

+I NV_P WR_S RC

1

C2 50

0.1U _0603 _50V 4Z~D

2

100P _0402_25V 8K

+I NV_P WR_S RC

+L CDV DD

R2 80

1 2

1K_ 0402_5% ~D

TEST_ BIST<30>

40mil40mil

+3VS

C3 4

ED ID_ CLK _LCD
ED ID_ DAT_ LCD

LVD SA0­LVD SA0+

LVD SA1­LVD SA1+

LVD SA2­LVD SA2+

LVD SAC­LVD SAC+

TEST_ BIST
INV T_PWM
DI SPO FF#

0.1U _0603 _50V 4Z~D

2

2

C3 2

1

1

ME@

JL VDS

0.1U _0603 _50V 4Z~D

30

30

29

29

28

28

27

27

26

26

25

25

24

24

23

23

22

22

21

21

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

I-P EX_201 43-030E-20 F~D

MGND1
MGND2

MGND3
MGND4

31
32

33
34

ED ID_ CLK _LCD
ED ID_ DAT_ LCD

LVDS signal from ATI-M92-S2

CIS Link:OK

12/29

ED ID_ CLK _LCD
ED ID_ DAT_ LCD ATI _EDI D_DAT _LCD

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

D

LVD SAC+
LVD SAC-

LVD SA0+
LVD SA0-

LVD SA1+
LVD SA1-

LVD SA2+
LVD SA2-

LVD SAC+
LVD SAC-

LVD SA0+
LVD SA0-

LVD SA1+ ATI _LVDSA1 +
LVD SA1-

LVD SA2+
LVD SA2-

R10_0 402_5% 1@

12

R20_0 402_5% 1@

12

R30_0 402_5% 1@

12

R3 60_0 402_5% 1@

12

R3 80_0 402_5% 1@

12

R4 90_0 402_5% 1@

12

R5 30_0 402_5% 1@

12

R1 160_ 0402_5% 1@

12

R1 450_ 0402_5% 1@

12

R1 470_ 0402_5% 1@

12

12
12

12
12

12
12

12
12

12
12

Title

Size D ocum ent N umber Re v

Cu stom

Da te: She et o f

GMC H_LV DSAC+
GMC H_LV DSAC-

GMC H_LV DSA0+
GMC H_LV DSA0-

GMC H_LV DSA1+
GMC H_LV DSA1-

GMC H_LV DSA2+
GMC H_LV DSA2-

GM CH_ EDID _CLK_ LCD
GM CH_E DID_ DAT_L CD

RG 6310_04 02_5% 2@
RG 6320_04 02_5% 2@

RG 6360_04 02_5% 2@
RG 6370_04 02_5% 2@

RG 6380_04 02_5% 2@
RG 6390_04 02_5% 2@

RG 6400_04 02_5% 2@
RG 6430_04 02_5% 2@

RG 6440_04 02_5% 2@
RG 6450_04 02_5% 2@

ATI _LVDS AC+
ATI _LVDS AC-

ATI _LVDSA0 +
ATI _LVDSA0 -

ATI _LVDSA1 -

ATI _LVDSA2 +
ATI _LVDSA2 -

A TI_ED ID_C LK_LC D

Compal Electronics, Inc.

CRT CONN/LCD CONN

LA -51 62P

GMC H_LV DSAC+ < 12>

GMC H_LV DSAC- <12>

GMC H_LV DSA0+ <1 2>

GMC H_LV DSA0- <1 2>

GMC H_LV DSA1+ <1 2>

GMC H_LV DSA1- <1 2>

GMC H_LV DSA2+ <1 2>

GMC H_LV DSA2- <1 2>

GM CH_ EDID _CLK_ LCD <12>
GM CH_E DID_ DAT_L CD <12>

ATI _LVDS AC+ <35>

ATI _LVDS AC- <35>

ATI _LVDSA0 + <35>

ATI _LVDSA0 - <35>

ATI _LVDSA1 + <35>

ATI _LVDSA1 - <35>

ATI _LVDSA2 + <35>

ATI _LVDSA2 - <35>

AT I_ED ID_CL K_LCD < 35>
ATI _EDI D_DAT _LCD <3 5>

E

19 60Mon day, Apri l 20, 2 009

0. 2

5

4

3

2

1

+3VS_DE LAY +5VS

2.2K_0402_5%~D

2.2K_0402_5%~D

2.2K_0402_5%~D

HDMIDAT_ATI<35>

D D

HDMIC LK_ATI<35>

Fo r Po we r Sa ving

+3VS

12

R561

1@

10K_0402_1%

R261

1@

0_0402_5%

HDMI_OE#

1 2

13

D

2

G

1@

S

SSM3K7002FU_SC70-3

C C

HDMI_ HPD_SINK

Q13

U10 Select Component

X76(Main)
X7617831L01
Parade(Main)
SA00002D700

V

R568

SD034470180

R569

R165

B B

R166

R161

R162

R163

R164

R560

C1280

A A

X

V
SD028000080

X

X

X

X

X

499 ohm
SD034499080

X

2@

2@

12

12

RG85

RG185

+3VS_DE LAY

X76(2nd)
X7617831L02
ST(2nd)
SA00002C610

V
SD034470180
V
SD034470180

X

V
SD028000080
V
SD028000080
V
SD028000080
V
SD028200280
V
SD034750180

4.7K ohm
SD028470180
0 ohm
SD028000080

5

4

5

2

+3VS

3

QG107B

2@

SSM6N7002FU_US6~D

QG107A

2@

SSM6N7002FU_US6~D

61

R571

@

1 2

4.7K_0402_1%

R572

1@

1 2

4.7K_0402_1%

R143

@

1 2

4.7K_0402_1%

HPD # o utp ut high vol tag e con fig ura tion:
CFG [1: 0]= 00 Vo h=0 .9 V, i nte rna l pull-up re sistor to 0.9 V
CFG [1: 0]= 01 Vo h=0 .8 V, i nte rna l pull-up re sistor to 0.8 V
CFG [1: 0]= 10 Vo h=1 .0 V, i nte rna l pull-up re sistor to 1.0 V
CFG [1: 0]= 11 ex te rna l pul l-u p r es ist or, V oh is determined
by e xte rn al su ppl y

ATI_H DMI_HPD<35>

2.2K_0402_5%~D

12

12

R281

R282

HDMI_ SDA_SINK

HDMI_ SCL_SINK

R161

DDCB UF_EN

DDC_E N

PRE /CFG

X76@

1 2

0_0402_5%

R162

X76@

1 2

0_0402_5%

C1275 0.1U _0402_16V7K~D1@

PEG_TXP0<12>
PEG_TXN0<12>

PEG_TXP1<12>
PEG_TXN1<12>

PEG_TXP2<12>
PEG_TXN2<12>

PEG_TXP3<12>
PEG_TXN3<12>

1 2

C1279 0.1U _0402_16V7K~D1@

1 2

C1274 0.1U _0402_16V7K~D1@

1 2

C1278 0.1U _0402_16V7K~D1@

1 2

C1273 0.1U _0402_16V7K~D1@

1 2

C1277 0.1U _0402_16V7K~D1@

1 2

C1272 0.1U _0402_16V7K~D1@

1 2

C1276 0.1U _0402_16V7K~D1@

1 2

HDMI_OE#

HDMI_ SCL_SINK

HDMI_ SDA_SINK

HDMI_ HPD_SINK

DDC_E N

DDCB UF_EN
PRE /CFG HDMI_P C0

HDMI signal from GMCH

+3VS

C

QG8

2@

MMBT3904_NL_SOT23-3

R689

2@

1 2

0_0402_5%

E

3 1

12

2@

10K_0402_1%~D

2@

2

1 2

B

200K_0402_5%~D

RG688

RG686

4

HDMI_ HPD_SINK

12

RG687

@

200K_0402_5%~D

Re co mme nde d Equ aliza tio n: [PC 1, PC0 ]=0 1, 4dB

R569

X76@

@

1 2

4.7K_0402_1%

HDMI_DATA2+
HDMI_DATA2-

HDMI_DATA1+
HDMI_DATA1-

HDMI_DATA0+
HDMI_DATA0-

HDMI_CLK+
HDMI_C LK-

HDMI_P C1

R157

HDMI_P C0

DDCBUF_EN=L:DDC Passive Switch(default)
R136,R138=47K(Pop)[For PS8101T]

DDCBUF_EN=H:DDC Actiive Buffer
R136,R138=1.5K(Nopop)[For 8171]

U10

1@

25

OE#

28

SCL_SINK

29

SDA_SINK

30

HPD_SINK

32

DDC_EN

34

CFG0

35

CFG1

48

IN_D4+

47

IN_D4-

45

IN_D3+

44

IN_D3-

42

IN_D2+

41

IN_D2-

39

IN_D1+

38

IN_D1-

PS8101TQFN48G_QFN48_7X7

12

4.7K_0402_1%
R568

1@

12

4.7K_0402_1%

GMCH_ HDMICLK

GMCH_HDM IDAT

CIS Link:OK

CPN:SA00002D700-->Main
CPN:SA00002C610-->2nd

R144

@

1 2

4.7K_0402_1%
R155

@

1 2

4.7K_0402_1%
R146

1@

0_0402_5%

R14

1@

1 2

0_0402_5%

EMI1/VCC

APD/V CC

EMI0/GND

12

ASQ1/GND

ATI_HDMI_CLK+<35>
ATI_HDM I_CLK-<35>

+3VS

R165

1@

1 2

0_0402_5%

R166

X76@

1 2

0_0402_5%

+3VS

R136

1@

1 2

47K_0402_5%~D

R138

1@

1 2

47K_0402_5%~D

1@

1 2

0_0402_5%

1@

1 2

0_0402_5%

4.7K_0402_1%

1 2

4.7K_0402_1%

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

ATI_HDMI_TX0+<35>
ATI_HDMI_TX0-<35>
ATI_HDMI_TX1+<35>
ATI_HDMI_TX1-<35>
ATI_HDMI_TX2+<35>
ATI_HDMI_TX2-<35>

2

VCC

11

VCC

15

VCC

21

VCC

26

VCC

33

VCC

40

VCC

46

VCC

4

PC1

3

PC0

6

REXT

7

HPD#

8

SDA

9

SCL

10

RT_EN#

13

OUT_D4+

14

OUT_D4-

16

OUT_D3+

17

OUT_D3-

19

OUT_D2+

20

OUT_D2-

22

OUT_D1+

23

OUT_D1-

1

GND

5

GND

12

GND

18

GND

24

GND

27

GND

31

GND

36

GND

37

GND

43

GND

49

PAD

+3VS

R150

R154

R151

@

12

R153

@

CG1280 0.1U_0402_16V7K~D2@

1 2

CG1281 0.1U_0402_16V7K~D2@

1 2

CG1284 0.1U_0402_16V7K~D2@

1 2

CG1282 0.1U_0402_16V7K~D2@

1 2

CG1283 0.1U_0402_16V7K~D2@

1 2

CG1285 0.1U_0402_16V7K~D2@

1 2

CG1287 0.1U_0402_16V7K~D2@

1 2

CG1286 0.1U_0402_16V7K~D2@

1 2

Place Close to JHDMI

+3VS

0.01U_0402_16V7K

0.1U_0402_10V6K

APD/V CC

EMI1/VCC

HDMI_P C1

R560 499_0402_1%1@

HDMI_ HPD#

R15 0_0402_5 %1@

R8 0_0402_5%1@

1 2

C1280 2.2U_0402_6.3V6M ~D@

HDMI_OUT _D2+_R
HDMI_ OUT_D2-_R

HDMI_OUT _D1+_R
HDMI_ OUT_D1-_R

HDMI_OUT _D0+_R
HDMI_ OUT_D0-_R

HDMI_OUT _CLK+_R
HDMI_ OUT_CLK-_R

ASQ0/GND

ASQ1/GND

EMI0/GND

0.1U_0402_25V6

1@

1

C744

2

1 2

GMCH_HDM IDAT

12

GMCH_ HDMICLK

12

C746

1 2

1@

1

C745

HDMI_ HPD#

2

HDMI_ HPD# <12>

R102 0_0402_5%1@
R112 0_0402_5%1@

R134 0_0402_5%1@
R142 0_0402_5%1@

R152 0_0402_5%1@
R156 0_0402_5%1@

R158 0_0402_5%1@
R160 0_0402_5%1@

R39

1@

1 2

0_0402_5%

+5V_HDMI_D

1.1A_6 VDC_FUSE

@

F1

2 1

Co-Layout Component

Location

PWR_HDMI

+3VS

GMCH_ HDMICLK <10>

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1

1

Short

2

2

F1

HDMI signal from ATI-M92-S2-L2

499_0402_1%~D

12

R163

X76@

20K_0402_5%

12

R164

X76@

7.5K_0402_1%

GMCH_HDMIDAT <10>

D

6

2
1

G

0.01U_0402_16V7K

PWR_ HD

+5V_HDMI

2

499_0402_1%~D

499_0402_1%~D

12

12

2@

2@

RG69

RG104

2@

2N7002W-7-F_SOT323-3~D

HDMI_OUT_D2+
HDMI_OUT _D2-

HDMI_OUT_D1+
HDMI_OUT _D1-

HDMI_OUT_D0+
HDMI_OUT _D0-

HDMI_OUT_CLK+
HDMI_OUT _CLK-

S

45

+5VALW

Q16
SI3456BDV-T1-E3_TSOP6~D

3

100_0402_1%~D

+5V_HDMI

RG20

C747

RUN ON <32>

499_0402_1%~D

12

12

2@

2@

RG83

RG105

D

QG9

S

HDMI_OUT_D2+

HDMI_OUT _D2-

HDMI_OUT _D1-

HDMI_OUT_D0+

HDMI_OUT _D0-

HDMI_OUT_CLK+

HDMI_OUT _CLK-

HDMI_ HPD_SINK

HDMI_ SDA_SINK
HDMI_ SCL_SINK

T2

HDMI_ OUT_CLK-_CONN

HDMI_ OUT_CLK+_CONN
HDMI_ OUT_D0-_CONN

HDMI_ OUT_D0+_CONN
HDMI_ OUT_D1-_CONN

HDMI_ OUT_D1+_CONN
HDMI_ OUT_D2-_CONN

HDMI_ OUT_D2+_CONN

499_0402_1%~D

13

499_0402_1%~D

499_0402_1%~D

12

2@

RG92

2

G

RG108 100K_0402_1%~D2@

12

2@

RG106

1

1

4

4

1

1

4

4

1

1

4

4

1

1

4

4

499_0402_1%~D

12

12

2@

RG113

12

L17

L28

L20

L21

ME@

JHDM I

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

FOX_QJ1119L-NVBT-7F

CIS Link:OK 12/29

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Doc ument Number Re v

Date: Sheet of

Compal Electronics, Inc.

HDMI Level Shifter

LA-5162P

HDMI_OUT_CLK+
HDMI_OUT _CLK­HDMI_OUT_D0+
HDMI_OUT _D0­HDMI_OUT_D1+
HDMI_OUT _D1­HDMI_OUT_D2+
HDMI_OUT _D2-

2@

RG107

+5VS

HDMI_ OUT_D2+_CONN

2

2

WCM-2012-900T_4P

HDMI_ OUT_D2-_CONN

3

3

HDMI_ OUT_D1+_CONNHDMI_OUT_D1+

2

2

WCM-2012-900T_4P

HDMI_ OUT_D1-_CONN

3

3

HDMI_ OUT_D0+_CONN

2

2

WCM-2012-900T_4P

HDMI_ OUT_D0-_CONN

3

3

HDMI_ OUT_CLK+_CONN

2

2

WCM-2012-900T_4P

HDMI_ OUT_CLK-_CONN

3

3

GND
GND
GND
GND

1

20
21
22
23

20 60Monday, A pril 20, 2009

1A

5

+3VS

R1035 8.2K_0402_5%

1 2

R1036 8.2K_0402_5%

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

12

D D

C C

R1037 8.2K_0402_5%

R1038 8.2K_0402_5%

R1039 8.2K_0402_5%

R240 8.2K_0402_5%

R1041 8.2K_0402_5%

R1042 8.2K_0402_5%

+3VS

R1043 8.2K_0402_5%

R1044 8.2K_0402_5%

R245 8.2K_0402_5%

R1046 8.2K_0402_5%

R1047 8.2K_0402_5%

R1048 8.2K_0402_5%

R1049 8.2K_0402_5%

R1150 8.2K_0402_5%

R1051 8.2K_0402_5%

R1052 8.2K_0402_5%

R1053 8.2K_0402_5%

R1054 8.2K_0402_5%

PCI_DEVSEL#

PCI_STOP#

PC I_TRDY#

PCI_FRAME#

PCI_PLOCK#

PCI _IRDY#

PCI_S ERR#

PCI_P ERR#

PCI_P IRQA#

PCI_P IRQB#

PCI_P IRQC#

PCI_P IRQD#

PCI_P IRQE#

PCI_P IRQF#

PCI_P IRQG#

PCI_P IRQH#

PCI_R EQ0#

PCI_R EQ1#

PCI_R EQ2#

PCI_R EQ3#

4

CPN:SA00002JH0L

U56B

D11

AD0

C8
D9

E12

E9

C9

E10

B7
C7
C5

G11

F8

F11

E7

A3
D2

F10

D5

D10

B3

F7
C3

F3

F4
C1
G7
H7
D1
G5
H6
G1
H3

PCI_P IRQA#
PCI_P IRQB#
PCI_P IRQC# PCI_P IRQG#
PCI_P IRQD#

J5

E1

J6

C4

PCI

AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

Interrupt I/F

PIRQA#
PIRQB#
PIRQC#
PIRQD#

ICH9M _FCBGA676~D

REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

PIRQE#/GPIO2
PIRQF#/GPIO3

PIRQG#/GPIO4

PIRQH#/GPIO5

REQ0#
GNT0#

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#

STOP#
TRDY#

FRAME#

PLTRST#

PCICLK

PME#

F1
G4
B6
A7
F13
F12
E6
F6

D8
B4
D6
A5

D3
E3
R1
C6
E4
C2
J4
A4
F5
D7

C14
D4
R2

H4
K6
F2
G2

3

PCI_R EQ0#
PCI_GNT0#
PCI_R EQ1#

PCI_R EQ2#

PCI_R EQ3#
PCI_GNT3#

PCI _IRDY#

PCI_P CIRST#
PCI_DEVSEL#
PCI_P ERR#
PCI_PLOCK#
PCI_S ERR#
PCI_STOP#
PC I_TRDY#
PCI_FRAME#

PCI_PLTRST#
CLK_P CI_ICH

PCI_P IRQE#
PCI_P IRQF#

PCI_P IRQH#

CLK_P CI_ICH <6>
EC_PME# <30>

2

+3VALW

C101 0.1U_0402_16V7K~D@

U61

@

5

PCI_P CIRST#

R1112 0_0402_5%

PCI_PLTRST#

R1061 0_0402_5%

Close to ICH9-M( U56 .D4)

CLK_P CI_ICH

MC74V HC1G08DFT2G SC70 5P

2

P

B

1

A

G

3

12

+3VALW

@

5

MC74V HC1G08DFT2G SC70 5P

2

P

B

1

A

G

3

12

R1010

@

12

33_0402_5%

22P_0402_50V8J

Y

C1251 0.1U_0402_16V7K~D@

U58

Y

4

4

C1002

@

1 2

1 2

PCI_RST#

1 2

PLT_RST#

1

PCI_RST# <26,27,28>

PLT_RST# <10 ,27,30,34>

12

R1059
100K_0402_5%~D

CIS Link:OK

A16 Swap Override Strap

PCI_GNT3#

B B

A A

5

Low= A16 swap override Enble
High= Default

R1055

4

@

1 2

1K_0402_5%~D

PCI_GNT3#

*

PCI_GNT0# SPI_CS#1

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Boot BIOS Strap

0

1

1

PCI_GNT0#

3

Boot BIOS Destination

SPI1

R1060

Compal Secret Data

PCI

LPC

Deciphered Date

*

2

0

1

@

1 2

1K_0402_5%~D

2009/01/05 2009/01/05

Title

Size Doc ument Number Re v

Date: Sheet of

Compal Electronics, Inc.

ICH9(1/4)-PCI/INT

LA-5162P

1

21 60Monday , April 20, 2009

0.2

5

4

3

2

1

+RTCVCC

1 2

R1062 1M_0402_5%

1 2

R1065 332K_0402_1%~D

D D

SM_INTR UDER#

ICH_IN TVRMEN

CPN: SJ100001U00

32.768 KHZ_12.5PF_1TJS125BJ4A421P

+RTCVCC

HDA Bus to GMCH

GMCH_H DA_BITCLK<10>

GMCH_ HDA_SYNC<10>

GMCH_HDA_RST#<10>

GMCH_H DA_SDOUT<10>

1 2

R103 33_0402_5%~D1@

1 2

R104 33_0402_5%~D1@

1 2

R105 33_0402_5%~D1@

1 2

R106 33_0402_5%~D1@

HDA_BITCLK

HDA _SYNC

HDA_RST#

HDA_SDOUT

HDA Bus to IDT CODEC

C C

B B

IDT_H DA_BITCLK<25>

IDT_H DA_SYNC<25>

IDT_HDA_RST #<25>

IDT_H DA_SDOUT<25>

1 2

R107 33_0402_5%~D

1 2

R108 33_0402_5%~D

1 2

R109 33_0402_5%~D

1 2

R111 33_0402_5%~D

+3VS

1 2

R17 10K_0402_5%~D

HDD

HDA_BITCLK

HDA _SYNC

HDA_RST#

HDA_SDOUT

SATA_LED#

PSATA_IRX_DTX_N0_C<28>
PSATA_IRX_DTX_P0_C<28>

PSATA_ITX_DRX_N0<28>
PSATA_ITX_DRX_P0<28>

C1211

1 2

12P_0402_50V8J

Y8

2

3

1

IN

NC

4

OUT

NC

C1212

1 2

12P_0402_50V8J

1 2

R1068 20K_0402_5%

1 2

R1109 20K_0402_5%

1 2

C1220 1U_0603_10V6K~D

CS_CLR

1

1

Open

1 2

C1210 1U_0603_10V6K~D

+1.5VS

ADC_A CZ_SDIN0<25>

ADC_G MCH_SDIN2<10>

C1213 0.01U_0402_16V7K

1 2
1 2

C1214 0.01U_0402_16V7K

12

R1069

10M_0402_5%

R89

1 2

0_0402_5%

2

1 2

R1073 24.9_0402_1%

SATA_LED#<31>

2

PSATA_ITX_DRX_N0_C
PSATA_ITX_DRX_P0_C

ICH_RTCX1
ICH_RTCX2

ICH_R TCRST#
SRTCRST#
SM_INTR UDER#

ICH_IN TVRMEN

GLAN_COMP

HDA_BITCLK
HDA _SYNC

HDA_RST#

ADC_A CZ_SDIN0

ADC_G MCH_SDIN2

HDA_SDOUT

SATA_LED#

T123
T124

U56A

C23

RTCX1

C24

RTCX2

A25

RTCRST#

F20

SRTCRST#

C22

INTRUDER#

B22

INTVRMEN

A22

LAN100_SLP

E25

GLAN_CLK

C13

LAN_RSTSYNC

F14

LAN_RXD0

G13

LAN_RXD1

D14

LAN_RXD2

D13

LAN_TXD0

D12

LAN_TXD1

E13

LAN_TXD2

B10

GPIO56

B28

GLAN_COMPI

B27

GLAN_COMPO

AF6

HDA_BIT_CLK

AH4

HDA_SYNC

AE7

HDA_RST#

AF4

HDA_SDIN0

AG4

HDA_SDIN1

AH3

HDA_SDIN2

AE5

HDA_SDIN3

AG5

HDA_SDOUT

AG7

HDA_DOCK_EN#/GPIO33

AE8

HDA_DOCK_RST#/GPIO34

AG8

SATALED#

AJ16

SATA0RXN

AH16

SATA0RXP

AF17

SATA0TXN

AG17

SATA0TXP

AH13

SATA1RXN

AJ13

SATA1RXP

AG14

SATA1TXN

AF14

SATA1TXP

ICH9M _FCBGA676~D

RTCLAN / GLANIHDAS ATA

LPCCPU

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME#

LDRQ0#

LDRQ1#/GPIO23

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

CPUPWRGD

IGNNE#

INIT#

INTR

RCIN#

SMI#

STPCLK#

THRMTRIP#

TP12

SATA4RXN

SATA4RXP
SATA4TXN
SATA4TXP

SATA5RXN

SATA5RXP
SATA5TXN
SATA5TXP

SATA_CLKN
SATA_CLKP

SATARBIAS#

SATARBIAS

LPC_AD0

K5

LPC_AD1

K4

LPC_AD2

L6

LPC_AD3

K2

LPC_FRAME#

K3

J3

T121

J1

T122

GATEA20

N7

H_A20M#

AJ27

H_DPRSTP#

AJ25

H_DPSLP#

AE23

R_H_F ERR#

AJ26

H_PW RGOOD

AD22

H_IGNN E#

AF25

H_INIT#

AE22

H_INT R

AG25

KB_RST#

L3

H_NMI

AF23

NMI

H_SMI#

AF24

H_STPCLK#

AH27

AG26

AG27

AH11
AJ11

ESATA_ITX_DRX_N4_C

AG12

ESATA_ITX_DRX_P4_C

AF12

AH9
AJ9
AE10
AF10

CLK_PCIE_SATA#

AH18

CLK_PCIE_SATA

AJ18

AJ7

SATARBIAS

AH7

1 2

24.9_0402_1%

Within 500 mils

LPC_A D[0..3] <28,30>

LPC_FRAME# <28,30>

GATEA20 <30>

H_A20M# <7>

H_DPRSTP# <8,10,48>
H_DPSLP# <8 >

H_FER R#

1 2

R1072 56_0402_5%

H_PW RGOOD <8>

H_IGNN E# <7>

H_INIT# <7>
H_INTR <7>

KB_RST# <30>

H_NMI <7>
H_SMI# <7>

H_STPCLK# <7>

H_THERMTRIP#THRM TRIP_ICH#

1 2

R1078 54.9_0402_1%

C275 0.01U_0402_16V7K

1 2

C276 0.01U_0402_16V7K

1 2

CLK_PCIE_SATA# <6>
CLK_PCIE_SATA <6>

R1081

GATEA20

KB_RST#

H_FER R#

H_THERMTRIP#

H_FER R# <7>

H_THERMTRIP# <7,10>

1 2

R1063 10K_0402_5%~D

1 2

R1066 10K_0402_5%~D

R1070 56_0402_5%

1 2

R1075 56_0402_5%

ESATA_IRX_DTX_N4_C <29>
ESATA_IRX_DTX_P4_C <29>

ESATA_ITX_DRX_N4 <29>
ESATA_ITX_DRX_P4 <29>

+3VS

+VCCP

12

E-SATA

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

ICH9(2/4)_LAN,HD,IDE,LPC

LA-5162P

1

22 60Monday , April 20, 2009

0.2

5

ICH_SM_CLK<6,16, 17,27,28>

ICH_SM_DA<6,16, 17,27,28>

D D

+3VALW

1 2

R1108 10K_0402_5%~D

1 2

R1111 10K_0402_5%~D

1 2

R1113 10K_0402_5%~D

1 2

R1114 10K_0402_5%~D

1 2

R1115 10K_0402_5%~D

1 2

R1116 10K_0402_5%~D

1 2

R1117 10K_0402_5%~D

1 2

R1119 8.2K_0402_5%

+3VS

8.2K_0402_5%

C C

B B

1 2

R1084 10K_0402_5%~D

1 2

R1086 8.2K_0402_5%

1 2

R1095 8.2K_0402_5%

10K_04 02_5%~D

R1088

1 2

THERM#

1 2

1 2

R1093

2

B

Q10
MMBT3904_NL_SOT23-3

E

31

C

R1124

2.2K_0402_5%~D

R1123

2.2K_0402_5%~D

CL_RST#1

ICH_P CIE_WAKE#

ICH _RI#

XDP_DBRESET#

ME_EC_CLK1

ME_EC_DATA1

EC_LID_OUT#

EC_SMI#

SERIR Q

PCI_C LKRUN#

EC_SC I#

EC_THERM# <30>

Express Card

Card Reader

+3VALW

R124 10K_0402_5%~D

R125 10K_0402_5%~D

R123 10K_0402_5%~D

R131 10K_0402_5%~D

R130 10K_0402_5%~D

R135 10K_0402_5%~D

A A

12

12

12

12

12

12

USB_OC#01

USB_OC#2

USB_OC#4

USB_OC#7

USB_OC#8

USB_OC#11

5

Q108A

SSM6N7002FU_US6~D

2

+3VS +3VALW+3VS

5

4

Q108B

SSM6N7002FU_US6~D

GLAN

WLAN

ICH_SMBCLK

61

R1085

1 2

2.2K_0402_5%~D

R1087

1 2

2.2K_0402_5%~D

ICH_SMBDATA

3

XOR CHAIN ENTRANCE STRAP:RSVD

PCIE_ITX_LANRX_N2<26>
PCIE_ITX_LANRX_P2<26>

PCIE_ITX_WLANRX_N3<28>
PCIE_ITX_WLANRX_P3<28>

PCIE_LANTX_IRX_N2<26>
PCIE_LANTX_IRX_P2<26>

PCIE_WLANTX_IRX_N3<28>
PCIE_WLANTX_IRX_P3<28>

PCIE_EXPTX_IRX_N4<27>

PCIE_EXPTX_IRX_P4<27>
PCIE_ITX_EXPRX_N4<27>
PCIE_ITX_EXPRX_P4<27>

PCIE_CRTX_IRX_N5<27>

PCIE_CRTX_IRX_P5<27>
PCIE_ITX_CRRX_N5<27>
PCIE_ITX_CRRX_P5<27>

R1083

@

1 2

1K_0402_5%~D

4

PM_BMBUSY#<10>

EC_LID_OUT#<30>

H_STP_PCI#<6>
H_STP_CPU#<6>

PCI_C LKRUN#<30>

ICH_P CIE_WAKE#<26,27,28>

SERI RQ<30>

VGATE<30,48>

1 2

R1099 0_0402_5%

R101 0_0402_5%

EC_SMI#<30>
EC_SC I#<30>

SB_SPKR<25>

12
12

12
12

12
12

12
12

4

1 2

ISOLATEB<26>

SATA_CLK_REQ#<6>

MCH _ICH_SYNC #<10>

ICH_R SVD

C1221 0.1U_0402_16V7K~D
C1222 0.1U_0402_16V7K~D

C1223 0.1U_0402_16V7K~D
C1224 0.1U_0402_16V7K~D

C1225 0.1U_0402_16V7K~D
C1226 0.1U_0402_16V7K~D

C1228 0.1U_0402_16V7K~D
C1227 0.1U_0402_16V7K~D

ICH_SMBCLK
ICH_SMBDATA
CL_RST#1
ME_EC_CLK1
ME_EC_DATA1

ICH _RI#

T125

XDP_DBRESET#

PM_BMBUSY#

EC_LID_OUT#

H_STP_PCI#
R_STP_CPU#

PCI_C LKRUN#

ICH_P CIE_WAKE#
SERIR Q
THERM#

VRMPWRGD

T128

EC_SMI#
EC_SC I#

T130

T49

T131
T132

SATA_CLK_REQ#

SB_SPKR
MCH _ICH_SYNC #
ICH_R SVD

T133
T134
T135

PCIE_LANTX_IRX_N2
PCIE_LANTX_IRX_P2
PCIE_ITX_LANRX_N2_C
PCIE_ITX_LANRX_P2_C

PCIE_WLANTX_IRX_N3
PCIE_WLANTX_IRX_P3
PCIE_ITX_WLANRX_N3_C
PCIE_ITX_WLANRX_P3_C

PCIE_EXPTX_IRX_N4
PCIE_EXPTX_IRX_P4
PCIE_ITX_EXPRX_N4_C
PCIE_ITX_EXPRX_P4_C

PCIE_CRTX_IRX_N5
PCIE_CRTX_IRX_P5
PCIE_ITX_CRRX_N5_C
PCIE_ITX_CRRX_P5_C

USB_OC#01<29>

USB_OC#2<29>

R1125

1 2

22.6_0402_1%

Within 50 0 mils

U56C

G16

SMBCLK

A13

SMBDATA

E17

LINKALERT#/GPIO60/CLGPIO4

C17

SMLINK0

B18

SMLINK1

F19

RI#

R4

SUS_STAT#/LPCPD#

G19

SYS_RESET#

M6

PMSYNC#/GPIO0

A17

SMBALERT#/GPIO11

A14

STP_PCI#

E19

STP_CPU#

L4

CLKRUN#

E20

WAKE#

M5

SERIRQ

AJ23

THRM#

D21

VRMPWRGD

A20

TP11

AG19

GPIO1

AH21

GPIO6

AG21

GPIO7

A21

GPIO8

C12

GPIO12

C21

GPIO13

AE18

GPIO17

K1

GPIO18

AF8

GPIO20

AJ22

SCLOCK/GPIO22

A9

GPIO27

D19

GPIO28

L1

SATACLKREQ#/GPIO35

AE19

SLOAD/GPIO38

AG22

SDATAOUT0/GPIO39

AF21

SDATAOUT1/GPIO48

AH24

GPIO49

A8

GPIO57/CLGPIO5

M7

SPKR

AJ24

MCH_SYNC#

B21

TP3

AH20

TP8

AJ20

TP9

AJ21

TP10

ICH9M _FCBGA676~D

USB_OC#01

USB_OC#2

USB_OC#4

USB_OC#7
USB_OC#8

USB_OC#11

USBR BIAS

3

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37

SATA

GPIO

SMBSYS GP IO

Clocks

S4_STATE#/GPIO26

DPRSLPVR/GPIO16

Power MGTController Link

GPIO

MEM_LED/GPIO24

GPIO10/SUS_PWR_ACK

GPIO14/AC_PRESENT

CLK14
CLK48

SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

PWROK

BATLOW#

PWRBTN#

LAN_RST#

RSMRST#

CK_PWRGD

CLPWROK

SLP_M#

CL_CLK0
CL_CLK1

CL_DATA0
CL_DATA1

CL_VREF0
CL_VREF1

CL_RST0#
CL_RST1#

WOL_EN/GPIO9

R1089

8.2K_0402_5%

GPIO21

AH23
AF19
AE21
AD20

H1
AF3

P1

C16
E16
G17

C10

G20

M2

B13

R3

D20

D22

R5

R6

B16

F24
B19

F22
C19

C25
A19

F21
D18

A16
C18
C11
C20

1 2

GPIO19
GPIO36
GPIO37

CLK_ICH_14M
CLK_ICH_48M

SLP_S3#
SLP_S4#
SLP_S5#

ICH_P WROK

DPRSLPVR

ICH_LOW_B AT#

R_EC_RSMRST#

M_PWROK

CL_CLK0

CL_DATA0

+CL_V REF0_ICH

CL_RST#

LAN_CABDT_R LAN_CABDT

T126

R1097 10K_0402_5%~D

T127

R695 100_0402_5%~D

R1104 10K_0402_5%~D

T129

T299

1 2

R1121 0_0402_5%

CLK_ICH_ 14M <6>
CLK_ICH_ 48M <6>

SLP_S3# <30>
SLP_S4# <30>
SLP_S5# <30>

1 2
1 2

DPRSLPVR <10,48>

PBTN_OUT# <30>

1 2

CLK_PW RGD <6>

M_PWROK <10>

+3VS

CL_CLK0 <10>

CL_DATA0 <10>

CL_RST# <10>

2

M_PWROK

ICH_P WROK <10,30>

LAN_CABDT <26>

MISC

U56D

N29

PERN1

N28

PERP1

P27

PETN1

P26

PETP1

L29

PERN2

L28

PERP2

M27

PETN2

M26

PETP2

J29

PERN3

J28

PERP3

K27

PETN3

K26

PETP3

G29

PERN4

G28

PERP4

H27

PETN4

H26

PETP4

E29

PERN5

E28

PERP5

F27

PETN5

F26

PETP5

C29

PERN6/GLAN_RXN

C28

PERP6/GLAN_RXP

D27

PETN6/GLAN_TXN

D26

PETP6/GLAN_TXP

D23

SPI_CLK

D24

SPI_CS0#

F23

SPI_CS1#/GPIO58/CLGPIO6

D25

SPI_MOSI

E23

SPI_MISO

N4

OC0#/GPIO59

N5

OC1#/GPIO40

N6

OC2#/GPIO41

P6

OC3#/GPIO42

M1

OC4#/GPIO43

N2

OC5#/GPIO29

M4

OC6#/GPIO30

M3

OC7#/GPIO31

N3

OC8#/GPIO44

N1

OC9#/GPIO45

P5

OC10#/GPIO46

P3

OC11#/GPIO47

AG2

USBRBIAS

AG1

USBRBIAS#

ICH9M _FCBGA676~D

USB

DMI0RXN
DMI0RXP

DMI0TXN
DMI0TXP

DMI1RXN
DMI1RXP

DMI1TXN
DMI1TXP

DMI2RXN
DMI2RXP

DMI2TXN
DMI2TXP

DMI3RXN
DMI3RXP

DMI3TXN
DMI3TXP

DMI_CLKN
DMI_CLKP

PCI-Express

Direct Media Int erf ace

DMI_ZCOMP

DMI_IRCOMP

SPI

USBP10N
USBP10P
USBP11N
USBP11P

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DMI_MTX_IRX_N0

V27

DMI_MTX_IRX_P0

V26

DMI_ITX_MRX_N0

U29

DMI_ITX_MRX_P0

U28

DMI_MTX_IRX_N1

Y27

DMI_MTX_IRX_P1

Y26

DMI_ITX_MRX_N1

W29

DMI_ITX_MRX_P1

W28

DMI_MTX_IRX_N2

AB27

DMI_MTX_IRX_P2

AB26

DMI_ITX_MRX_N2

AA29

DMI_ITX_MRX_P2

AA28

DMI_MTX_IRX_N3

AD27

DMI_MTX_IRX_P3

AD26

DMI_ITX_MRX_N3

AC29

DMI_ITX_MRX_P3

AC28

CLK_P CIE_ICH#

T26

CLK_P CIE_ICH

T25

AF29

DMI_IRCOM P

AF28

USB20_N0

AC5

USB20_P0

AC4

USB20_N1

AD3

USB20_P1

AD2

USB20_N2

AC1

USB20_P2

AC2
AA5
AA4

USB20_N4

AB2

USB20_P4

AB3
AA1
AA2
W5
W4

USB20_N7

Y3

USB20_P7

Y2

USB20_N8

W1

USB20_P8

W2
V2
V3
U5
U4

USB20_N11

U1

USB20_P11

U2

2009/01/05 2009/01/05

Compal Secret Data

DMI_MTX_IRX_N0 <10>

DMI_MTX_IRX_P0 <10>
DMI_ITX_MRX_N0 <10>
DMI_ITX_MRX_P0 <10>

DMI_MTX_IRX_N1 <10>

DMI_MTX_IRX_P1 <10>
DMI_ITX_MRX_N1 <10>
DMI_ITX_MRX_P1 <10>

DMI_MTX_IRX_N2 <10>

DMI_MTX_IRX_P2 <10>
DMI_ITX_MRX_N2 <10>
DMI_ITX_MRX_P2 <10>

DMI_MTX_IRX_N3 <10>

DMI_MTX_IRX_P3 <10>
DMI_ITX_MRX_N3 <10>
DMI_ITX_MRX_P3 <10>

CLK_P CIE_ICH# <6>
CLK_P CIE_ICH <6>

1 2

R1120 24.9_0402_1%

USB20_N0 <29>

USB20_P0 <29>

USB20_N1 <29>

USB20_P1 <29>

USB20_N2 <29>

USB20_P2 <29>

USB20_N4 <28>

USB20_P4 <28>

USB20_N7 <27>

USB20_P7 <27>

USB20_N8 <28>

USB20_P8 <28>

USB20_N11 <28>

USB20_P11 <28>

Deciphered Date

+1.5VS

JUSBR1

JUSBR2

JUSBR3(E-SATA)

WLAN

Express Card

Bluetooth

Cam era

2

R1092

CLK_ICH_14M

CLK_ICH_48M

@

1 2

10_0402_5%~D

R1091

@

1 2

10_0402_5%~D

1 2

4.7P_0402_50V8C

1 2

4.7P_0402_50V8C

Close to ICH9-M

LAN_CABDT

ICH_LOW_B AT#

R_EC_RSMRST#

EC_RSMRST#<30> POK <43>

R1106

1 2

0.1U_0402_16V7K~D
453_0402_1%

3.24K_0402_1%

12

C1219

R1107

1

2

Within 50 0 mils

Title

ICH9(3/4)_DMI,USB,GPIO,PCIE

Size Doc ument Number Re v

Cus tom

LA-5162P

Date: Sheet of

1

C1218

@

C1217

@

+3VS

1 2

R313 10K_0402_5%~D

R1110 8.2K_0402_5%

R1103

1 2

0_0402_5%

+3VS

12

+3VALW

R656

@

1 2

0_0402_5%

Compal Electronics, Inc.

1

23 60Monday , April 20, 2009

0.2

20 mils

20 mils

5

+1.5VS

BLM21PG600SN1D_0805~D

+1.5VS

+3VS

1 2

C1268 0.1U_0402_16V7K~D

5

+RTCVCC

L96

1 2

1 2

10UH_LB2012T100MR_20%_0805~D

R1129 0_0603_5%

1 2

+1.5VS

1UH_20%_0805~D

20 mils

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

1

C1229

2

2

40 mils

22U_0805_6.3V6M~D

220U_ D2_4VY_R15M

1

+

C1234

2

L99

C1267

0.1U_0402_16V7K~D

1 2

1 2

L100

10U_0805_10V4Z~D

1

2

C1230

+VCCGLANPLL

+ICH_ V5REF_RUN

+ICH_ V5REF_SUS

+VCC1_5_B

22U_0805_6.3V6M~D

1

1

C1235

2

2

+VCCSATAPLL

1U_0603_10V6K~D

1

C1255

2

+1.5VS

1342mA

1U_0603_10V6K~D

1

C1258

2

+1.5VS

1

2

+VCC_ LAN1_05_INT_ICH_1
+VCC_ LAN1_05_INT_ICH_2

+VCCLAN3_3

2.2U_06 03_6.3V6K~D

1

C1269

C1270

2

+5VS +3VS

10_0402_5%~D

12

21

D45

R1127

CH751H -40PT_SOD323-2

+ICH_ V5REF_RUN

1

C1241

0.1U_06 03_50V4Z~D

D D

C C

B B

A A

2

+3VALW+5VALW

10_0402_5%~D

12

21

D46

R1128

CH751H -40PT_SOD323-2

+ICH_ V5REF_SUS

1

C1306

0.1U_06 03_50V4Z~D

2

646 mA

2.2U_06 03_6.3V6K~D

1

C1236

2

47m A

10U_0805_10V4Z~D

1

C1254

2

+1.5VS

1U_0603_10V6K~D

1

2

+1.5VS

11m A

0.1U_0402_16V7K~D

1

C1262

2

11m A

0.1U_0402_16V7K~D

C1263

19/ 78 /78mA

+1.5VS

4.7U_0603_6.3V6M~D

1

2

G3: 6u A

C1237

C1256

+3VS

C1271

4

2mA

2mA

23m A

80m A

1mA

4

U56F

A23

VCCRTC

A6

V5REF

AE1

V5REF_SUS

AA24

VCC1_5_B[1]

AA25

VCC1_5_B[2]

AB24

VCC1_5_B[3]

AB25

VCC1_5_B[4]

AC24

VCC1_5_B[5]

AC25

VCC1_5_B[6]

AD24

VCC1_5_B[7]

AD25

VCC1_5_B[8]

AE25

VCC1_5_B[9]

AE26

VCC1_5_B[10]

AE27

VCC1_5_B[11]

AE28

VCC1_5_B[12]

AE29

VCC1_5_B[13]

F25

VCC1_5_B[14]

G25

VCC1_5_B[15]

H24

VCC1_5_B[16]

H25

VCC1_5_B[17]

J24

VCC1_5_B[18]

J25

VCC1_5_B[19]

K24

VCC1_5_B[20]

K25

VCC1_5_B[21]

L23

VCC1_5_B[22]

L24

VCC1_5_B[23]

L25

VCC1_5_B[24]

M24

VCC1_5_B[25]

M25

VCC1_5_B[26]

N23

VCC1_5_B[27]

N24

VCC1_5_B[28]

N25

VCC1_5_B[29]

P24

VCC1_5_B[30]

P25

VCC1_5_B[31]

R24

VCC1_5_B[32]

R25

VCC1_5_B[33]

R26

VCC1_5_B[34]

R27

VCC1_5_B[35]

T24

VCC1_5_B[36]

T27

VCC1_5_B[37]

T28

VCC1_5_B[38]

T29

VCC1_5_B[39]

U24

VCC1_5_B[40]

U25

VCC1_5_B[41]

V24

VCC1_5_B[42]

V25

VCC1_5_B[43]

U23

VCC1_5_B[44]

W24

VCC1_5_B[45]

W25

VCC1_5_B[46]

K23

VCC1_5_B[47]

Y24

VCC1_5_B[48]

Y25

VCC1_5_B[49]

AJ19

VCCSATAPLL

AC16

VCC1_5_A[1]

AD15

VCC1_5_A[2]

AD16

VCC1_5_A[3]

AE15

VCC1_5_A[4]

AF15

VCC1_5_A[5]

AG15

VCC1_5_A[6]

AH15

VCC1_5_A[7]

AJ15

VCC1_5_A[8]

AC11

VCC1_5_A[9]

AD11

VCC1_5_A[10]

AE11

VCC1_5_A[11]

AF11

VCC1_5_A[12]

AG10

VCC1_5_A[13]

AG11

VCC1_5_A[14]

AH10

VCC1_5_A[15]

AJ10

VCC1_5_A[16]

AC9

VCC1_5_A[17]

AC18

VCC1_5_A[18]

AC19

VCC1_5_A[19]

AC21

VCC1_5_A[20]

G10

VCC1_5_A[21]

G9

VCC1_5_A[22]

AC12

VCC1_5_A[23]

AC13

VCC1_5_A[24]

AC14

VCC1_5_A[25]

AJ5

VCCUSBPLL

AA7

VCC1_5_A[26]

AB6

VCC1_5_A[27]

AB7

VCC1_5_A[28]

AC6

VCC1_5_A[29]

AC7

VCC1_5_A[30]

A10

VCCLAN1_05[1]

A11

VCCLAN1_05[2]

A12

VCCLAN3_3[1]

B12

VCCLAN3_3[2]

A27

VCCGLANPLL

D28

VCCGLAN1_5[1]

D29

VCCGLAN1_5[2]

E26

VCCGLAN1_5[3]

E27

VCCGLAN1_5[4]

A26

VCCGLAN3_3

ICH9M _FCBGA676~D

CORE

VCCA3GP ATXARX USB CORE

VCCP_CORE

PCI

VCCSUS1_05[1]
VCCSUS1_05[2]

VCCSUS1_5[1]

VCCSUS1_5[2]

VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]

VCCPSUSVCCPUSB

VCCSUS3_3[5]

VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]

VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]

GLAN POWER

VCC1_05[1]
VCC1_05[2]
VCC1_05[3]
VCC1_05[4]
VCC1_05[5]
VCC1_05[6]
VCC1_05[7]
VCC1_05[8]

VCC1_05[9]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]

VCCDMIPLL

VCC_DMI[1]
VCC_DMI[2]

V_CPU_IO[1]
V_CPU_IO[2]

VCC3_3[1]

VCC3_3[2]

VCC3_3[7]

VCC3_3[3]
VCC3_3[4]
VCC3_3[5]
VCC3_3[6]

VCC3_3[8]

VCC3_3[9]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCC3_3[14]

VCCHDA

VCCSUSHDA

VCCCL1_05

VCCCL1_5

VCCCL3_3[1]
VCCCL3_3[2]

3

+VCCP

A15
B15
C15
D15
E15
F15
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

R29

W23
Y23

AB23
AC23

AG29

AJ6

AC10

AD19
AF20
AG24
AC20

B9
F9
G3
G6
J2
J7
K7

AJ4

AJ3

AC8
F17

AD8

F18

A18
D16
D17
E22

AF1

T1
T2
T3
T4
T5
T6
U6
U7
V6
V7
W6
W7
Y6
Y7
T7

G22

G23

19/ 73 /73mA

A24
B24

163 4mA

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

1

C1232

C1233

2

2

+VCCDMIPLL

0.01U_0402_16V7K

1

2

0.1U_0402_16V7K~D

1

2

12

T140
T141

R118

@

0_0402_5%

T142

C1257 0.1U_0402_16V7K~D

+3VALW

0.1U_0402_16V7K~D

0.022U_0402_16V7K~D

1

C1259

2

C1264 0.1U_0402_16V7K~D

1 2

1U_0603_10V6K~D

+3VS

1

2

10U_0805_10V4Z~D

BLM18PG181SN1_0603~D

1

C1238

C1239

2

+VCC_DM

308 mA

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

C1248

C1249

2

1 2

+3VALW

212 mA

0.022U_0402_16V7K~D

1

1

C1260

2

2

0.1U_0402_16V7K~D

1

@

@

C1265

C1266

2

1 2

+3VS

C1261

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.5VS

L97

23m A

1 2

4.7U_0603_6.3V6M~D
BLM18PG181SN1_0603~D

1

C1240

2

1

C1250

2

1

C1414

0.1U_0402_16V4Z

2

2009/01/05 2009/01/05

L98

4.7U_0603_6.3V6M~D

1

C1242

2

0.1U_0402_16V7K~D

1

C1247

2

R115

1 2

0_0402_5%

48m A

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

+VCCP

+VCCP

0.1U_0402_16V7K~D

1

1

C1244

C1243

2

2

+3VS

2mA

0.1U_0402_16V7K~D

2

2

C1245

C1246

1

1

+1.5VS

+1.5V_HDA +3VALW

1U_0402_6.3V6K~D

1

2

U41

5

VOUT

4

NC

2

GND

RT9013-15GB_SOT23-5~D

C19

CPN:SA00002YT1L

Compal Secret Data

Deciphered Date

2

VIN

EN

2

U56E

AA26

VSS[1]

AA27

VSS[2]

AA3

VSS[3]

AA6

VSS[4]

AB1

VSS[5]

AA23

VSS[6]

AB28

VSS[7]

AB29

VSS[8]

AB4

VSS[9]

AB5

VSS[10]

AC17

VSS[11]

AC26

VSS[12]

AC27

VSS[13]

AC3

VSS[14]

AD1

VSS[15]

AD10

VSS[16]

AD12

VSS[17]

AD13

VSS[18]

AD14

VSS[19]

AD17

VSS[20]

AD18

VSS[21]

AD21

VSS[22]

AD28

VSS[23]

AD29

VSS[24]

AD4

VSS[25]

AD5

VSS[26]

AD6

VSS[27]

AD7

VSS[28]

AD9

VSS[29]

AE12

VSS[30]

AE13

VSS[31]

AE14

VSS[32]

AE16

VSS[33]

AE17

VSS[34]

AE2

VSS[35]

AE20

VSS[36]

AE24

VSS[37]

AE3

VSS[38]

AE4

VSS[39]

AE6

VSS[40]

AE9

VSS[41]

AF13

VSS[42]

AF16

VSS[43]

AF18

VSS[44]

AF22

VSS[45]

AH26

VSS[46]

AF26

VSS[47]

AF27

VSS[48]

AF5

VSS[49]

AF7

VSS[50]

AF9

VSS[51]

AG13

VSS[52]

AG16

VSS[53]

AG18

VSS[54]

AG20

VSS[55]

AG23

VSS[56]

AG3

1

1U_0402_6.3V6K~D

3

1

C21

2

VSS[57]

AG6

VSS[58]

AG9

VSS[59]

AH12

VSS[60]

AH14

VSS[61]

AH17

VSS[62]

AH19

VSS[63]

AH2

VSS[64]

AH22

VSS[65]

AH25

VSS[66]

AH28

VSS[67]

AH5

VSS[68]

AH8

VSS[69]

AJ12

VSS[70]

AJ14

VSS[71]

AJ17

VSS[72]

AJ8

VSS[73]

B11

VSS[74]

B14

VSS[75]

B17

VSS[76]

B2

VSS[77]

B20

VSS[78]

B23

VSS[79]

B5

VSS[80]

B8

VSS[81]

C26

VSS[82]

C27

VSS[83]

E11

VSS[84]

E14

VSS[85]

E18

VSS[86]

E2

VSS[87]

E21

VSS[88]

E24

VSS[89]

E5

VSS[90]

E8

VSS[91]

F16

VSS[92]

F28

VSS[93]

F29

VSS[94]

G12

VSS[95]

G14

VSS[96]

G18

VSS[97]

G21

VSS[98]

G24

VSS[99]

G26

VSS[100]

G27

VSS[101]

G8

VSS[102]

H2

VSS[103]

H23

VSS[104]

H28

VSS[105]

H29

VSS[106]

ICH9M _FCBGA676~D

Title

Size Doc ument Number Re v

Cus tom

LA-5162P

Date: Sheet of

VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

Compal Electronics, Inc.

ICH9(4/4)_POWER&GND

VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]

VSS_NCTF[1]
VSS_NCTF[2]
VSS_NCTF[3]
VSS_NCTF[4]
VSS_NCTF[5]
VSS_NCTF[6]
VSS_NCTF[7]
VSS_NCTF[8]
VSS_NCTF[9]

1

1

H5
J23
J26
J27
AC22
K28
K29
L13
L15
L2
L26
L27
L5
L7
M12
M13
M14
M15
M16
M17
M23
M28
M29
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
P12
P13
P14
P15
P16
P17
P2
P23
P28
P29
P4
P7
R11
R12
R13
R14
R15
R16
R17
R18
R28
T12
T13
T14
T15
T16
T17
T23
B26
U12
U13
U14
U15
U16
U17
AD23
U26
U27
U3
V1
V13
V15
V23
V28
V29
V4
V5
W26
W27
W3
Y1
Y28
Y29
Y4
Y5
AG28
AH6
AF2
B25

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

24 60Monday , April 20, 2009

0.2

5

4

3

2

1

D D

IDT_H DA_BITCLK

10_0402_5%~D

@

R13

MIC_C LK_R

1 2

10P_0402_50V 8J

1

@

C C

B B

A A

C1007

2

220P_0402_50V7K

@

2

C1411

1

ADC _ACZ_SD IN0<22>

MIC_C LK<28>

MIC0<28>

EC_MUTE _R#<30>

+3VS

20mil

0.1U_0 402_16V7K~D

0.1U_0 603_50V4Z~D

+1.5VS

1

1

C1727

C1726

0.1U_0 402_16V7K~D

2

2

IDT_H DA_BITCLK<22>

R113 33_0402_5%~D

IDT_H DA_SDOUT<22>

IDT _HDA_ SYNC<22>

IDT_H DA_RST#<22>

1 2

R1394 0_0402_5%

1 2

R1395 0_0402_5%

R418 0_0402_5%

1

C1728

2

IDT_H DA_BITCLK

ADC _ACZ_SD IN0_IDT

1 2

IDT_H DA_SDOUT

IDT _HDA_ SYNC

IDT_H DA_RST#

12

C1190

12

4.7U_0 603_6.3V6M~D

CAP-

CAP+

10U_0 603_6.3V6M

1

C1729

2

U60

1

DVDD_CORE

9

DVDD

3

DVDD_IO

6

HDA_BITCLK

8

HDA_SDI

5

HDA_SDO

10

HDA_SYNC

11

HDA_RST#

MIC_C LK_R
MIC_S IG_R

EC_MUTE#

2

DMIC_CLK/GPIO1

4

DMIC0/GPIO2

46

DMIC1/GPIO0/SPDIF_OU T_1

48

SPDIF_OUT_0

47

EAPD

35

CAP-

36

CAP+

7

DVSS

33

AVSS

30

AVSS

26

AVSS

42

PVSS

49

DAP

92HD8 1B1A5NLG XYYX8_QFN48_7X7~D

CIS Link:OK

CPN:SA00002QZ50

Place close to codec

1 2

R191 0_0805_5%

1 2

R189 0_0603_5%@

1 2

R193 0_0603_5%@

1 2

R210 0_0603_5%@

1 2

R209 0_0603_5%@

DIGIT AL GND A NALOG GND

AVDD
AVDD

PVDD
PVDD

SENSE_A
SENSE_B

HP0_PORT_A_L

HP0_PORT_A_R

VREFOUT_A_or_F

HP1_PORT_B_L

HP1_PORT_B_R

PORT_C_L

PORT_C_R

VREFOUT_C

SPKR_PORT_D_L+

SPKR_PORT_D_L-

SPKR_PORT_D_R­SPKR_PORT_D_R+

PORT_E_L

PORT_E_R

PORT_F_L

PORT_F_R

PC_BEEP

MONO_OUT

CAP2

VREFFILT

VREG

0.1U_0 603_50V4Z~D

27
38

39
45

SENSE_A

13

SENSE_B

14

28
29
23

HP_LE FT_R

31

HP_ RIGHT_R

32

MIC_L EFT_C

19

MIC_R IGHT_C

20
24

SPKER O_L1

40

SPKER O_L2

41

43
44

15
16

BEEP_R

17
18

MONO_I N

12

25

22

21

34

V-

37

10U_0 603_6.3V6M

4.7U_0 603_6.3V6M~D

1

C490

2

10U_0 603_6.3V6M

1

1

C1734

C1730

2

2

1 2

R185 5 6_0402_5%

1 2

R186 5 6_0402_5%

1 2

C39 2.2U _0603_6.3V6K

1 2

C40 2.2U _0603_6.3V6K

R1407 0_0603_5%

1 2

R1408 0_0603_5%

1 2

R1409 0_0603_5%

1 2

R1410 0_0603_5%

1 2

R178

1 2

0_0402_5%

R176

1 2

0_0402_5%

10U_0 603_6.3V6M

0.1U_0 603_50V4Z~D

1

1

C915

C814

2

2

40mil

0.1U_0 402_16V7K~D

1

2

1

2

0.1U_0 603_50V4Z~D

C1731

C815

0.1U_0 402_16V7K~D

1

1

C1732

2

2

12

R139820K_0402_1%

12

R139910K_0402_1%

12

R1189

2.2K_0 402_5%~D

L2

1 2

BLM21 PG600SN1D_0805~D

C1733

HP _JD

HP_ JD < 29>

MIC _JD

MIC _JD <29>

HP_LEFT
HP_RI GHT

MIC_LEFT
MIC_R IGHT

SPKER_L1
SPKER_L2

SPKER _R2SPKER O_R2
SPKER _R1SPKER O_R1

R1183

1 2

20K_0402_1%

R1188

1 2

20K_0402_1%

HP_LEFT <29>
HP_RI GHT <29>

0.1U_0 402_16V7K~D

0.1U_0 402_16V7K~D

+5V_A VDD_HD+AVDD _HD

MIC_LEFT <29>
MIC_R IGHT <29>

C1412

12

C1416

12

ANTIPOP<30>

SSM3K 7002FU_SC70-3

Speaker Connector

SPKER_L1
SPKER_L2
SPKER _R2
SPKER _R1

R1411

1 2

0_0603_5%~D

U59

@

5

Vout

2

GND

TPS71 718DCKR_SC70-5~D

EC Beep

BEEP <30>

ICH Beep

SB_SPKR <23>

2

G

Q17

1

Vin

3

EN

4

NR/FB

SENSE_A

SENSE_B

MIC_LEFT

1 2

4.7K_0 402_5%~D

MIC_R IGHT

1 2

4.7K_0 402_5%~D

+5VALW

SI1972 DH-T1-E3_SOT363-6

10K_0402_1%

12

R169

SI1972 DH-T1-E3_SOT363-6

13

D

S

100P_0402_25V8K

@

C23

2.49K_ 0402_1%~D

+5VS

EC_MUTE#

1 2

C18

@

0.01U_ 0402_16V7K

+AVDD _HD

R129

12

R297

1 2

10K_0402_1%

R16

R61

HP_LEFT HP_ RIGHT

100P_0402_25V8K

100P_0402_25V8K

@

C24

C1739

1 2

0.1U_0 402_16V7K~D

+MIC1 _VREFO

10mil

1U_04 02_6.3V6K~D

1

C8

2

61

Q4A

2

5

Q4B

3 4

100P_0402_25V8K

@

C25

ACES_ 87213-0400G

@

C26

CIS Link:OK

61

Q2A
SI1972 DH-T1-E3_SOT363-6

2

5

Q2B
SI1972 DH-T1-E3_SOT363-6

3 4

ME@

JSPK

1

1

2

2

3

3

GND

4

4

GND

12/29

5
6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

P24-Co dec 92HD81B / Speaker

Size Do cument Number R ev

2

Da te: Sh eet of

LA-516 2P

Monday, April 20, 2009

1

25 60

0.2

A

B

C

D

E

LED Table

LED[S1-S0]

LED0

1 1

LED1

LED2

LED3

Note1:D uring power down mode, the LED signals are logic high.

Note2:L ED[S1-S0] initial value comes from the 93C46.

W=60mils

+3VALW

1U_0603_10V6K~D

1

+B+_BIAS

100K_0402_1%~D

12

2 2

EN_WOL#<30>

ISOLATEB<23>

3 3

25MHZ_12PF_X8A025000FC1H-H

15P_0402_50V8J

1

C1488

2

13

D

2

G

S

+3VS

1K_0402_5%~D

12

15K_0402_5%

1 2

CPN:SJ100004S00

Y9

1 2

C1455

2

R292

EN_WOL

Q58
SSM3K7002FU_SC70-3

R1245

ISOLATEB

R1246

R1282

15P_0402_50V8J

Q128

SI3456BDV-T1-E3 1N TSOP6

D

6

S

2
1

G

3

2200P_0402_50V7K~D

CKTAL1

CKTAL2

0_0402_5%

1 2

1

C1489

2

L123

45

1 2

FBMA-L11-322513-201LMA40T_1210

C311

1 2

PCIE_LANTX_IRX_P2<23>

PCIE_LANTX_IRX_N2<23>

PCIE_ITX_LANRX_P2<23>

PCIE_ITX_LANRX_N2<23>

CLK_P CIE_LAN<6>
CLK_P CIE_LAN#<6>

LAN_CLK_RE Q#<6>

ICH_P CIE_WAKE#<23,27,28>

W=60mils

+LAN_IO

1.5A

22U_0805_6.3VAM

22U_0805_6.3VAM

C1473 0.1U _0402_16V7K~D

C1476 0.1U _0402_16V7K~D

PCIE_ITX_LANRX_P2

PCIE_ITX_LANRX_N2

PCI_RST#<21,27,28>

R1244 2.49K_0402_1%

LAN_CABDT<23>

0.1U_0402_16V7K~D

@

1

1

C1457

C1456

2

1 2

C1458

2

PCIE_LANTX_IRX_P2_C

12

PCIE_LANTX_IRX_N2_C LAN_LED1_100#

12

ISOLATEB

CKTAL1
CKTAL2

U64

20

HSOP

21

HSON

15

HSIP

16

HSIN

17

REFCLK_P

18

REFCLK_N

25

CLKREQB

27

PERSTB

46

RSET

26

LANWAKEB

28

ISOLATEB

41

CKTAL1

42

CKTAL2

23

GPO

24

NC

7

GND

14

GND

31

GND

47

GND

22

EGND

RTL8111DL-GR_LQFP48_7X7

RTL8111DL

LED3/EEDO

LED2/EEDI/AUX

LED1/EESK

EECS

LED0

MDIP0
MDIN0
MDIP1
MDIN1
MDIP2
MDIN2
MDIP3
MDIN3

FB12

SROUT12

EVDD12
DVDD12
DVDD12
DVDD12
AVDD12

AVDD12

VDDSR
VDDSR

VDD33
VDD33

AVDD33
AVDD33

ENSR

CIS Link:OK

CPN:SA00002UV00

4 4

If there is no 93C46, the default value is [1:1].

33
34
35
32

38

2
3
5
6
8
9
11
12

4

48

19
30
36
13
10

39

44
45

29
37

1
40
43

LAN_LED3_1000#
LAN_LED2_10#

LAN_LED0_ACT#

LAN_MDIP0
LAN_M DIN0
LAN_MDIP1
LAN_M DIN1
LAN_MDIP2
LAN_M DIN2
LAN_MDIP3
LAN_M DIN3

+VDDSR

+LAN_IO

LAN_LED2_10#

LAN_LED0_ACT# <29>

LAN_MDIP0 <29>
LAN_M DIN0 <29>
LAN_MDIP1 <29>
LAN_M DIN1 <29>
LAN_MDIP2 <29>
LAN_M DIN2 <29>
LAN_MDIP3 <29>
LAN_M DIN3 <29>

22U_0805_6.3VAM

C1486 0.1U_04 02_16V7K~D

C1487 0.1U_04 02_16V7K~D

C1544 0.1U_04 02_16V7K~D

C1616 0.1U_04 02_16V7K~D

00 01 10 11

TX/RX

LINK 100

LINK 10

LINK 1000

1 2

R1241 3.6K_0402_5%

+LAN_D VDD12

0.1U_0402_16V7K~D

0_0805_5%~D

1

1

C1474

C1475

2

2

1 2

1 2

1 2

1 2

+LAN_D VDD12

0.01U_0402_25V7K~D

@

1

C37

2

0.1U_0402_16V7K~D

12

R294

W=40mils

TX/RX

LINK
10/100/1000
LINK
10/100

LINK 1000

+LAN_IO

0.1U_0402_16V7K~D

@

1

C312

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

2

C1466

C1467

2

1

+LAN_IO

LINK

TX

10/ACT
LINK

LINK

100/ACT

RX

FULL

4.7UH _1008HC-472EJFS-A_5%_1008

W=30mils

0.1U_0402_16V7K~D

2

C1465

1

L107

1 2

0.1U_0402_16V7K~D

2

C1464

1

FULL

LINK
1000/ACT

LAN_LED2_10#

LAN_LED3_1000#

LAN_LED3_1000#

+LAN_VDD

R1238

12

0_0603_5%

2

C1463

1

D54

CH751H-40PT_S OD323-2

CH751H-40PT_S OD323-2

CH751H-40PT_S OD323-2

CH751H-40PT_S OD323-2

+LAN_EVDD

21

D55

21

D56

21

D57

21

W=60milsW=60mils

+LAN_VDD+LAN_SROUT

0.1U_0402_16V7K~D

22U_0805_6.3VAM

1

C1478

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

C1470

2

C1479

1

2

LED_10/1000#

LED_100/1000#LAN_LED1_100#

R293

1 2

0_0603_5%~D

C1469

W=30mils

+LAN_VDD

LED_10/1000# <29>

LED_100/1000# <29>

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

Giga LAN_RTL8111DL

LA-5162P

E

26 60Monday , April 20, 2009

0.2

5

+1 .8VC CD_CB

Q57

@

AO3 413_SOT23- 3

D

S

G

R1 70

L15

1 2

54.9 K_040 2_1%

12

100K _0402_1%

12

13

2

C1 786

0.01 U_040 2_16V7K

@

1

C4 1

2

1

C1 797

2

+1.8 V

@

1 2

SUS P<32,49>

100K _040 2_5%~D

D D

+3VS

BLM 18BD 601SN 1D_0603~D

1.86V

VOUT

FB

+1 .8VC CD_CB

5

4

22UF _080 5_6.3V6M

1

2

R2 30

C4 3

+

R2 31

+3VS

R2 29

1 2

0.1U _0402 _25V6~D
10K _0402_5%

C C

1

C4 2

2

U2

1

VIN

2

GND

3

EN

RT9 043-GB_ SOT23-5~D

+1 .8VC CD_C B

4.7U _0805 _10V 4Z~D

1

C1 787

2

+3V S_PH Y

0.1U _0402 _16V7K~ D

C1 798

BLM 18BD 601SN 1D_0603~D

0.1U _0402 _16V7K ~D

0.1U _0402 _16V7K ~D

1

C1 788

2

4.7U _0805 _10V4 Z~D

1 2

50_0 603_1%

4.7U _0805 _10V 4Z~D

PCI E_ITX_ CRRX_P5<2 3>
PCI E_IT X_CRRX_N5<23>

PCI E_CRTX _IRX_P5<2 3>
PCI E_CRT X_IRX_N5<23>

L10

1 2

0.1U _0402 _16V7K ~D

1

C1 789

2

R1 520

@

C1 794

@

CL K_P CIE_C R<6>
CL K_PC IE_C R#<6>

CR _CLK _REQ#<6>

PLT_R ST#<10, 21,30, 34>

4

4.7U _0805 _10V 4Z~D

0.1U _0402 _16V7K ~D

0.1U _0402 _16V7K ~D

1

C1 783

C1 784

2

0.1U _0402 _16V7K ~D

1

1

C1 793

C1 792

2

2

C1 795

@

0.1U _0402 _16V7K ~D

PCI E_IT X_CRRX_P5
PCI E_IT X_CRRX_ N5

12
12

CL K_P CIE_ CR
CL K_P CIE_C R#

CR _CLK _REQ #

PLT_ RST#

1 2

R1 68 0_040 2_5%

C3 05 1U _0603_ 10V6K~D@

1

2

0.1U _0402 _16V7K ~D

1 2

C1 782

+3VS

4.7U _0805 _10V 4Z~D

C1 791

1

2

C1 799 0 .1U_0 402_1 6V7K~D
C1 800 0 .1U_0 402_1 6V7K~D

+1.8 VCCA _CB

L8

@

+1.8 VCCA _CB _OUT

1 2

BLM 18BD 601SN 1D_0603~D

R1 476

@

+1.8 VCCD _CB_ OUT

1 2

0_06 03_5%

C3 5

@

1 2

4.7U _0805 _10V4 Z~D

+3V S_PH Y_PLL

R1 478 1 .2K_ 0402_1%@

R1 479 5 .1K_ 0402_1%

12

12

PCI E_CRT X_IRX _P5_C
PCI E_CRT X_I RX_N5_C

3

CIS Link:OK 01/07
CPN:SA000036M10

U4 6

5

PE_VCCA

13

PE_VCCA

17

PE_VCCA

64

VCCA_OUT

2
18
24
42
63

20
28

46
27
19
45

36
41

1

9

7

8

11
12

15
16

3

4

32

31

65

POWER

CORE_VCCD
CORE_VCCD
CORE_VCCD
CORE_VCCD
CORE_VCCD

VCCD_OUT
VCCD_OUT

3.3VCCD

3.3VCCD

3.3VCCD
AUX_VCCD

3.3VCCA

3.3VCCA

PE_3.3VCCA

PLL_REF_RETURN

PE_RTERM2

PE_RTERM1

PE_RXP
PE_RXN

PE_TXP
PE_TXN

PE_REFCLKP
PE_REFCLKN

PE_CLKREQ#

PE_RST#

DGND

OZ8 88GS0 L3N- C1-0-TR_ QFN64_8X8

PCIe

GND

IEEE1394

1394_TPBN
1394_TPBP

1394_TPAN
1394_TPAP

1394_TPBIAS

MS_CLK/XD_CE#/SD_CLK

MMI_BS/XD_ALE/SD_CMD

MMI_XD_WE#

WAKEUP#

CardReader

MS_XD_D2

MS_XD_D1

1394_XI

1394_XO

1394_REF

MMI_VCC

XD_CD#
MS_CD#
SD_CD#

SD_WPI

XD_WPO

XD_RE#
XD_RB#
XD_CLE

MMI_LED

MMI_D7
MMI_D6
MMI_D5
MMI_D4
MMI_D3

SD_D2

SD_D1

MMI_D0

AGND
AGND
AGND

1394 _TPBN0

34

1394_T PBP0

35

1394 _TPAN0

37

1394_T PAP0

38

139 4_TPBIAS 0

39

OZ8 88XI

43

OZ88 8XO

44

R1 475 5.9K _0402_ 1%

1 2

40

26

25

MS_ CD#

29

SD/ MMC_ CD#

30

SD/ MS_C LK

47

SD _WP I

60
62
61
23
22

SD/ MS_C MD/BS

48
21
59
33

49
50
51
52

SD/ MMC_ D3

53

MS _D2

54

SD/ MMC_ D2

55

MS _D1

56

SD/ MMC_ D1

57

SD/ MMC_ D0

58

6
10
14

2

CPN:SJ1000 05U0L

24.5 76MH Z_16P F_1Y 72457 6CE1C~D

Close to
OZ888 Chipset

C1 802

LAN _WAK EUP# < 30>

OZ8 88XI

OZ88 8XO

1

2

1U_0 603_1 0V6K~D

1

R9 90

1 2

0_04 02_5%

+3V S_CR

1

C1 803

2

1U_0 603_1 0V6K~D

SD/ MS_C LKLAN _WAK EUP#

10P _0402_5 0V8J

X3

R9 95

@

0_04 02_5%

@

C1 781

1 2

18P _0402_50 V8J

1 2

C1 785

1 2

15P _0402 _50V8J~D

12

1

C1 842

2

139 4_TPBIAS 0

R1 481

R1 496

C1 805

56.2 _0402_1 %

56.2 _0402_1 %

12

12

R1 482

1394_T PAP0

1394 _TPAN0
1394_T PBP0

1394 _TPBN0

56.2 _0402_1 %

56.2 _0402_1 %

12

12

R1 497

270P _0402_5 0V7K

5.1K _0402 _1%

2

R1 503

1

1 2

C1 804

1U_0 603_1 0V6K~D

1

2

1394_TP AP0 <29 >

1394 _TPAN0 < 29>
1394_TP BP0 <29 >

1394 _TPBN0 < 29>

Express Card Power Switch & Connector

ME@

(1.5A)

B B

A A

+3V ALW

(0.5A) (1.5A)

0.1U _0402 _16V7K ~D

0.1U _0402 _16V7K ~D

1

1

C8 5

2

2

PCI _RST#<21 ,26,28>

SY SON< 30,32, 45>

SUS P#<30, 32,44 ,46>

+1.5V S +1.5VS _EXP

+3VS +3VS_EXP

(1A)

0.1U _0402 _16V7K ~D

1

C7 4

C9 1

2

U1 1

12

1.5Vin

14

1.5Vin

2

3.3Vin

4

3.3Vin

PCI _RST #

SY SO N

SUS P#

CP USB #

EXP R_CP USB#

AUX_IN17AUX_OUT

6

SYSRST#

20

SHDN#

1

STBY#

10

CPPE#

9

CPUSB#

18

RCLKEN

R553 8D001 -TR- F_QFN 20_4X4~D

1.5Vout

1.5Vout

3.3Vout

3.3Vout

PERST#

GND

(1A)

OC#

NC

4.7U _0805 _10V 4Z~D

0.1U _0402 _16V7K ~D

0.1U _0402 _16V7K ~D

1

1

C8 9

C9 0

2

2

11
13

3
5

15

19

PE RST#

8

16

7

4.7U _0805 _10V 4Z~D

1

C7 5

2

(0.5A)

1

C9 2

2

0.1U _0402 _16V7K ~D

+3V_EXP

C9 3

R4 8 0 _0402_5 %

USB 20_N7<23>
USB 20_P7<23>

1

C7 3

2

1

2

4.7U _0805 _10V 4Z~D

1 2

R4 7 0 _0402_5 %

1 2

ICH _SM_C LK<6,1 6,17, 23,28>

ICH _SM_D A<6,1 6,17 ,23,28>

+1.5VS _EXP

IC H_PCI E_WA KE#< 23,26 ,28>

+3V_EXP

+3VS_EXP

EXP _CLK_RE Q#<6>

CLK _PCIE_E XP#<6>
CLK _PCIE_E XP<6>

PCIE_E XPTX_IR X_N4<23>
PCIE_E XPTX_IR X_P4<23>

PCIE_I TX_EXPR X_N4<23>
PCIE_I TX_EXPR X_P4<23>

US B20_ N7_R
USB 20_P 7_R
EXP R_CP USB#

ICH _SM_C LK
ICH _SM_D A

PE RST#

EXP _CLK_R EQ#
CP USB #
CLK _PCI E_EXPR#
CLK _PCI E_EXPR

PCIE_E XPTX_IR X_N4
PCIE_E XPTX_IR X_P4

PCIE_I TX_EXPR X_N4
PCIE_I TX_EXPR X_P4

CIS Link:OK

CPN:SA00001SL1L

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

JEXP

1

GND

2

USB_D-

3

USB_D+

4

CPUSB#

5

RSV

6

RSV

7

SMB_CLK

8

SMB_DATA

9

+1.5V

10

+1.5V

11

WAKE#

12

+3.3VAUX

13

PERST#

14

+3.3V

15

+3.3V

16

CLKREQ#

17

CPPE#

18

REFCLK-

19

REFCLK+

20

GND

21

PERn0

22

PERp0

23

GND

24

PETn0

25

PETp0

26

GND

27

GND

28

GND

SAN TA_13080 1-5_LT

CIS Link:OK

121/29

2009/01/05 2009/01/05

SD/MMC/MS 3-IN-1 CONNECTOR

+3V S_CR

ME@

SD/ MMC_ D2

SD/ MMC_ D3

SD/ MS_C LK
SD/ MS_C MD/BS
SD/ MMC_ D3
MS_ CD#

MS _D2

SD/ MMC_ D0
SD/ MS_C LK
MS _D1
SD/ MS_C MD/BS

SD/ MMC_ D0
SD/ MMC_ D1
SD _WP I
SD/ MMC_ CD#

J3 IN1

1

DAT2/SD9

2

VSS/MS10

3

DAT3/SD1

4

VCC/MS9

5

SCLK/MS8

6

CMD/SD2

7

DATA3/MS7

8

INS/MS6

9

VSS1/SD3

10

DATA2/MS5

11

VCC/VDD/SD4

12

DATA0/MS4

13

CLK/SD5

14

DATA1/MS3

15

BS/MS2

16

GND/VSS2/SD6

17

VSS/MS1

18

DAT0/SD7

19

#19DAT1/SD8

20

#20

21

#21

T-S OL_1 43-130 0002900_NR~D

CIS Link:OK

04/15

Compal Secret Data

Deciphered Date

2

Title

Size D ocum ent N umber Re v

Cu stom

Da te: She et o f

22

GND

23

GND

Compal Electronics, Inc.

Card Reader_OZ888GS0L1N

LA-5162P

1

27 6 0Monda y, A pril 20, 2009

0. 2

A

B

C

D

E

Mini-Card(WLAN Module & Debug Card Connector)

1 1

ICH_P CIE_WAKE#<23,26,27>

WLAN _CLK_REQ#<6>

CLK_P CIE_WLAN#<6>

R999

@

CLK_DEBU G_PORT

1 2

10P_0402_50V8J

0_0402_5%

@

1

C1843

2

2 2

CLK_P CIE_WLAN<6>

PCI_RST#<21,26,27>

CLK_DEBU G_PORT<6>

PCIE_WLANTX_IRX_N3<23>
PCIE_WLANTX_IRX_P3<23>

PCIE_ITX_WLANRX_N3<23>
PCIE_ITX_WLANRX_P3<23>

EC_TX_DATA<30>

EC_RX_CLK<30>

ICH_P CIE_WAKE#

WLAN _CLK_REQ#

CLK_P CIE_WLAN#
CLK_P CIE_WLAN

R444 0_0402_5%

1 2

CLK_DEBU G_PORT

R403 0_0402_5%

1 2

R404 0_0402_5%

1 2

PCIE_ITX_WLANRX_N3
PCIE_ITX_WLANRX_P3

1 2

R90 0_0402_5%

1 2

R97 0_0402_5%

WLAN_ACTIVE
BT_ACTIVE

WLANTX_N3_C
WLANTX_P3_C

+3V_WLAN

EC_TX_DATA_R
EC_RX_CLK_R

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53

(+3V_WLAN=1A)

0.1U_0402_16V7K~D

0.01U_0402_16V7K

1

1

C500

2

2

ME@

JWLAN

1

1

3

3

5

5

7

7

9

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

GND1

GND2

TYCO_1775861-1~D

+3V_WLAN

4.7U_08 05_10V4Z~D

1

C489

C456

2

2

2

4

4

6

6

8

8

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

1 2

R415 0_0603_5%@

1 2

R412 0_0805_5%~D

C485 0.01U_0402_16V7K

1 2

C488 0.01U_0402_16V7K

+3V_WLAN

+1.5VS

+3V_WLAN

1 2

R171 0_0402_5%
R172 0_0402_5%
R174 0_0402_5%
R175 0_0402_5%
R173 0_0402_5%

1 2
1 2

LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R

WL_O FF#
PCI_RST#

USB20_N4_R
USB20_P4_R

1 2
1 2
1 2
1 2
1 2

R3730_0402_5%
R3430_0402_5%

+3VALW

+3VS

+1.5VS

(+1.5VS=0.5A)

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

WL_O FF# <30>

PCI_RST# <21,26,27>

+1.5VS

ICH_SM_CLK <6,1 6,17,23,27>

ICH_SM _DA <6,16,17,23,27>

12

R10900_0402_5%

12

R10940_0402_5%

USB20_N4 <23>
USB20_P4 <23>

LPC_FRAME# <22,30>

LPC_A D[0..3] <22,30>

EC_TX_DATA

R91

@

1 2

0_0402_5%

10P_0402_50V8J~D

1

@

C503

2

CIS Link:OK

12/29

12/29

Camera Module Connector

+5VS +5VS_CAM

0.1U_0402_10V6K

1

3 3

C20

2

Q15

SI2301BDS-T1-E3_SOT23-3

S

100K_04 02_5%~D

G

2

R120

R128

1 2

1K_0402_5%~D

CAM_ ON/OFF#<30>

D

13

CAM_ ON/OFF

2

G

13

D

Q14
2N7002_SOT23-3

S

USB20_P11<23>
USB20_N11<23>

1 2

R1096 0_0402_5%

1 2

R1098 0_0402_5%

MIC_CLK<25>

+5VS_CAM

CAM_DET#<30>

MIC0

MIC0<25>

MIC_CLK

+3VS

CIS Link:OK

USB20_P11_R
USB20_N11_R

100P_0402_25V8K

100P_0402_25V8K

1

1

C1737

C1736

2

2

ME@

JCAM

12

GND

11

GND

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

ACES_87036-1001-CP

Bluetooth Module Connector

112
334
556
778
9910
111112
131314

GND15GND

2
4
6
8
10
12
14

16

+3VS

BT_ACTIVE

USB20_P8_R
USB20_N8_R

DETECT GND

R11180_0402_5%

12
12

USB20_P8 <23 >

R11020_0402_5%

USB20_N8 <23>

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

ME@

BT_DET#<30>

WLAN_ACTIVE

4 4

BT_OFF#<30>

JBT

HRS_CL537-0918-4-86

CIS Link:OK

12/29

A

SATA Hard-Disk Connector

PSATA_ITX_DRX_P0<22>
PSATA_ITX_DRX_N0<22>

PSATA_IRX_DTX_N0_C<22>
PSATA_IRX_DTX_P0_C<22>

2009/01/05 2009/01/05

C

Compal Secret Data

C10 0.01U_0402_16V7K

1 2

C12 0.01U_0402_16V7K

1 2

+3VS

0.1U_0402_16V7K~D

10U_0805_10V4Z~D

@

1

C378

2

Deciphered Date

ME@

JH DD

1

PSATA_ITX_DRX_P0
PSATA_ITX_DRX_N0

PSATA_IRX_DTX_N0
PSATA_IRX_DTX_P0

PJP20

JUMP_43X118

2

112

Open

+5VS

0.1U_0402_16V7K~D

10U_0805_10V4Z~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1000P_0402_50V7K~D

@

@

1

1

2

1

1

1

C379

C380

C574

C296

2

2

2

1

C377

2

2

2

3

4

5

6

7

8

9

10
11
12
13
14
15
16
17
18
19
20

C376

21

GND
RX+
RX­GND
TX­TX+
GND

V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12

GND

V1222GND

OCTEK_SAT-22EH4G_RV

24
23

CIS Link:OK

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

Mini-Card / BT / Camera

LA-5162P

E

28 60Monday , April 20, 2009

0.2

Right-side USB Port(Up&Down)(2A)

W=80mils W=80mils

+5VALW +5V_USBR

0.1U_0402_16V7K~D

1

USB_EN1#<30>

C1502

2

USB_EN1#

U47

1

GND

2

IN

3

EN1#

4

EN2#

TPS2062ADR_SO8~D

CPN: SA00002AS0L
CIS LinkL:OK 01/07

OC1#
OUT1
OUT2

OC2#

8
7
6
5

USB_OC#01 <23>

Right-side E-SATA & USB Port(2A)

W=80milsW=80mils

U49

1

GND

0.1U_0402_16V7K~D

C1509

USB_EN2#

2

IN

3

EN1#

4

EN2#

TPS2062ADR_SO8~D

CPN: SA00002AS0L
CIS LinkL:OK 01/07

OC1#
OUT1
OUT2

OC2#

8
7
6
5

USB_OC#2 <23>USB_EN2#<30>

+5V_ESATA+5VALW

I/O Board Connector
Type : Board to Board(50 Pin)

ME@

LED_10/1000#<26>

LED_100/1000#<26>

LAN_LED0_ACT#<26>

LAN_MDIN3<26>
LAN_MDIP3<26>
LAN_MDIN2<26>
LAN_MDIP2<26>
LAN_MDIN1<26>
LAN_MDIP1<26>
LAN_MDIN0<26>
LAN_MDIP0<26>

ESATA_ITX_DRX_P4<22>
ESATA_ITX_DRX_N4<22>

ESATA_IRX_DTX_N4_C<22>
ESATA_IRX_DTX_P4_C<22>

1394_TPAP0<27>
1394_TPAN0<27>
1394_TPBP0<27>
1394_TPBN0<27>

HP_JD<25>
MIC_JD<25>

LED_10/1000#
LED_100/1000#
LAN_LED0_ACT#
LAN_M DIN3
LAN_MDIP3
LAN_M DIN2
LAN_MDIP2
LAN_M DIN1
LAN_MDIP1
LAN_M DIN0
LAN_MDIP0

1394_TPAP0
1394_TPAN0
1394_TPBP0
1394_TPBN0

HP_JD
MIC_J D MIC_R IGHT

JI O

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

G1

E-T_1000-F50E-02R

2
4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

G2

CIS Link:OK

04/13

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

+5V_USBR

+5V_ESATA

+3VS
+LAN_IO

USB20_N2
USB20_P2
IOB_DETECT#
USB20_N0
USB20_P0

USB20_N1
USB20_P1

HP_LEFT
HP_RI GHT

MIC_LEFT

USB20_N2 <23>
USB20_P2 <23 >

IOB_DETECT# <30>

USB20_N0 <23>
USB20_P0 <23 >

USB20_N1 <23>
USB20_P1 <23 >

HP_LEFT <25>

HP_RI GHT <25>

MIC_LEFT <25>
MIC_R IGHT <25>

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

USB Port / IO connector

LA-5162P

29 60Monday , April 20, 2009

0.2

CLK_PC I_926

10_0402_5%~D

12

@

R272

15P_0402_50V8J~D

@

1

C282

2

+3VALW

R77 47K_0402_5%~D

R78 47K_0402_5%~D

R56 100K_0402_5%~D

R385 10K_0402_5%~D

+3VS

1 2

R309 100K_0402_5%~D

R65

R177 100K_0402_5%~D

KSO1

12

KSO2

12

KBD_DET#

12

LID_SW#

12

MSEN#

LAN_WAKEUP#

10K_04 02_5%~D

IOB_DETECT#

12

SPI Flash (2Mbyte*1)

FSEL#SP ICS# SPI_CS#

R439 15_0402_5%~D

FRD#S PI_SO S PI_SO

1 2

R275 15_0402_5%~D

+3VALW

R228

47K_0402_5%

C268

0.1U_0402_16V7K~D

12

0.1U_0402_16V7K~D

1

2

GATEA20<22>

KB_RST#<22>

SERIR Q<23>

LPC_FRAME#<22,28>

LPC_A D[0..3]<22,28>

0.1U_0402_16V7K~D

U37

CS#
SO
WP#
GND

KSO[0.. 16]<31>

VCC

HOLD#

SCLK

CLK_PC I_926<6>
PLT_RST#<10,21,27,34>

EC_SC I#<23>
PCI_C LKRUN#<23>

KSI [0..7]<31>

FAN_SPEED 1<18>

CAM_ ON/OFF#<28>

EC_TX_DATA<28>

3VS_D ELAY_ON<40>

1.1VS_GFX_ON<49>

LAN_WAKEUP#<27>

BATT_LOW_LED#<31>

1 2

SI

IOB_DETECT#<29>

C314

1 2

2

1

12

R437
10K_0402_5%~D

1
2
3
4

MX25L1605AM2C-12G_SO8

CPN:SA00002TO00
CIS Link:OK 01/07

+3VALW +EC_AVCC

1000P_0402_50V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

1

C277

C285

C281

2

2

GATEA20
KB_RST#
SERIR Q
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

CLK_PC I_926
PLT_RST#
EC_RST#
EC_SC I#
PCI_C LKRUN#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14

KSO15

KSO16

KBD_DET#<31>

SLP_S3#<23>
SLP_S5#<23>

EC_SMI#<23>

EC_RX_CLK<28>

ON_OF F<31>

FSTCHG<42>

EN_IN VPWR<19>

PWR_LED#<31>

LID_SW#<31>

TEST_BIST<19>
EC_PME#<21>

KBD_DET#

SLP_S3#
SLP_S5#
EC_SMI#
FAN_SPEED 1
CAM_ ON/OFF#
EC_TX_DATA
EC_RX_CLK
ON_O FF
3VS_D ELAY_ON

1.1VS_GFX_ON
MSEN#

MSEN#<19>

FSTCHG
EN_IN VPWR
LAN_WAKEUP#
BATT_LOW_LED#
PWR_LED#
SYS ON

SYSO N<27,32,45>

VR_ON

VR_ON<48>

AC IN

ACIN< 35,42>

LID_SW#
IOB_DETECT#
TEST_BIST
EC_PME#

1000P_0402_50V7K~D

1

1

C493

2

1

C269

C291

2

2

U29

1

GA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LFRAME#

5

LAD3

7

LAD2

8

LAD1

10

LAD0

12

PCICLK_EC

13

PCIRST#/GPIO05

37

ECRST#

20

SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23/TP_ISP

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

28

FAN_SPEED1/GPIO14

29

GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

ON_OFF/GPIO18

36

NUM_LED#/GPIO1A

73

CIR_RX/GPIO40

74

CAP_INT#/CIR_RLC_TX/GPIO41

89

FSTCHG/GPIO50

90

BATT_CHG_LED#/GPIO52

91

CAPS_LED#/GPIO53

92

BATT_LOW_LED#/GPIO54

93

PWR_LED#/GPIO55

95

SYSON/GPIO56

121

VR_ON/GPIO57

127

AC_IN/GPIO59

16

RLC_RX2/GPIO0A

17

ESB_CLK/GPIO0B

18

ESB_DAT/GPIO0C

19

RLC_TX2/GPIO0D

KB926QFD3_LQFP128_14X14

LPC & MISC

Int . K/B
Matr ix

9

22

33

96

111

125

VCC1

VCC2

VCC3

VCC4

VCC5

VCC6

PW M Outp ut

AD In put

DA Ou tpu t

PS 2 Inter fac e

SP I Fl as h ROM

GPXIO A

GP IO

GP XIOD

GND1

GND2

11

24

67

AVCC

INVT_PWM/PWM 0/GPIO0F

BEEP#/PWM1//GPIO10

PWM2/GPIO11

SUSP_LED#/PWM3/GPIO19

FANPWM0/GPIO12

ACOFF/FANPWM1//GPIO13

BATT_TEMP/AD0/GPI38

BATT_OVP/AD1/GPI39

ADP_I/AD2/GPI3A

DAC_BRIG/DA0/GPO3C

EN_DF/DA1/GPO3D

IREF/DA2/GPO3E

CHGVADJ/DA3/GPO3F

EC_MUTE#/GPIO4A

USB_EN#/GPIO4B

PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/GPIO4E

TP_DATA/GPIO4F

SPICLK/GPIO58

SCL1/GPIO44

SM Bu s

GND3

35

94

SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

WOL_EN/GPXIOA01

SBPWR_EN/GPXIOA02
EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04

EC_ON/GPXIOA05

EC_SWI#/GPXIOA06

ICH_PWROK/GPXIOA07

BKOFF#/GPXIOA08

RF_OFF#/GPXIOA09

LID_SW#/GPXIOD00

PM_SLP_S4#/GPXIOD01

ENBKL/GPXIOD02

EAPD/GPXIOD03

EC_THRM#/GPXIOD04

SUSP#/GPXIOD05

PBTN_OUT#/GPXIOD06

EC_PME#/GPXIOD07

AGND

GND4

GND5

69

113

ECAGND

AD3/GPI3B
AD4/GPI42
AD5/GPI43

SPIDI

SPIDO

SPICS#

GPXIOA00

GPXIOA10
GPXIOA11

V18R

XCLKI

XCLKO

CIS Link:OK

+3VALW+3VALW

12

R85
10K_0402_5%~D

8
7

SPI_CLK_R

6
5

1 2

R420 15_0402_5%~D

SPI_SI

1 2

R438 15_0402_5%~D

R419

@

SPI_CLK_R

1 2

15_0402_5%~D

15P_0402_50V8J~D

CPN:SA00001J580

SPI_CLK

FWR #SPI_SI

C507

@

1 2

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0.1U_0402_16V7K~D

1000P_0402_50V7K~D

FBM-11-160808-601-T_0603

1

1

C482

C481

2

2

FBM-11-160808-601-T_0603

ECAGND BATT_TEMP

1 2

C273 0.01U_0402_16V7K

INVT_PWM_R

21

BEEP

23

BATT_CHG_LED#

25
34

26

ACOF F

27

BATT_TEMP

63

BATT_OVP

64

ADP_I

65

AD_BI D

66

BT_DET#

75

CAM_DET#

76

CP_SEL

68

EN_DF AN1

70

IRE F

71

CHGVA DJ

72

EC_MUTE_R#

83

USB_EN1#

84

VGA_ON

85

LCD_CBL_D ET#

86

TP_CLK

87

TP_DATA

88

FRD#S PI_SO

119

FWR #SPI_SI

120

SPI_CLK

126

FSEL#SP ICS#

128

EC_SMB_CK1

77

EC_SMB_DA1

78

SMB_CLK_THERMAL

79

SMB_DATA_THERMAL

80

SPI_P ULLDOWN

97

EN_WOL#

98

BT_OFF#

99

EC_RSMRST#

100

EC_LID_OUT#

101

EC_ON

102

ANTIPOP

103

ICH_P WROK

104

BKOFF#

105

WL_O FF#

106

LCD_VCC_TEST_EN

107

PSID_ DISABLE#

108

VGATE

109

SLP_S4#

110

EC_ENBKL

112

USB_EN2#

114

EC_THERM#

115

SUSP#

116

PBTN_OUT#

117

PS_ID

118

V18R

124

122
123

XCLKI
XCLKO

C322 1U_0603_10V6K~D

C270 0.1U_0402_16V7K~D

2009/01/05 2009/01/05

12

L18

L19

12

R295

0_0402_5%

1 2

BEEP <25>
BATT_CHG_LED# <31>

ACOF F <42>

BATT_TEMP <50>
BATT_OVP <50>
ADP_I <42>

BT_DET# <28>

CAM_DET# <28>

CP_SEL <42>
EN_DF AN1 <18>
IREF <42>
CHGVA DJ <42>

EC_MUTE_R# <25>
USB_EN1# <2 9>
VGA_ON <47>
LCD_CBL_DET# <19>
TP_CLK <31>

TP_DATA <31>

EC_SMB_CK1 <50>

EC_SMB_DA1 <50>

SMB_CLK_THERMAL <18,39>

SMB_DATA_THERMAL <18,39>

R274 4.7K_0402_5%

EN_WOL# <26>
BT_OFF# <28>
EC_RSMRST# <23>
EC_LID_OUT# <23>
EC_ON <31>
ANTIPOP <25>
ICH_P WROK <10,23>
BKOFF# <19>
WL_OFF# <28>
LCD_VCC_TEST_EN <19>
PSID_ DISABLE# <41>

VGATE <23,48>
SLP_S4# <23>
EC_ENBKL <19>
USB_EN2# <2 9>
EC_THERM# <23>
SUSP# < 27,32,44,46>
PBTN_OUT# <23>
PS_ID <41>

R278

@

20M_0603_5%

1 2

12

Compal Secret Data

Deciphered Date

+3VALW

INVT_PWM <12,19>

12

R279

1 2

12

0_0402_5%

C297

1 2

22P_0402_50V8J

C292

1 2

22P_0402_50V8J

Board ID

0.1U_0402_16V7K~D

BOARD ID Table

BOARD ID

ID

0

0.1(X00)

1

0.2(X01)

2

0.3(X02)

3

1.0(A00)

SMB_CLK_THERMAL

SMB_DATA_THERMAL

BT_DET#

CAM_DET#

LCD_CBL_D ET#

EC_SMB_CK1

EC_SMB_DA1

EC_MUTE_R#

EC_PME#

TP_CLK

TP_DATA

X2

4

1

32.768 KHZ_12.5PF_1TJS125BJ4A421P

CPN: SJ100001U00

3

OUT

NC

2

IN

NC

Compal Electronics, Inc.

Title

Size Doc ument Number Re v

Cus tom

LA-5162P

Date: Sheet of

AD_BI D

1

C272

@

2

1 2

R265 2.2K_0402_5%~D

1 2

R264 2.2K_0402_5%~D

R266 100K_0402_5%~D

R308 100K_0402_5%~D

1 2

R159 100K_0402_5%~D

R262 4.7K_0402_5%

R263 4.7K_0402_5%

1 2

R277 10K_0402_5%~D @

R405 10K_0402_5%~D

1 2

R270 4.7K_0402_5%

1 2

R271 4.7K_0402_5%

EC KB926

R232

100K_0402_5%~D

R84

20K_0402_1%

NC
100K
100K
100K

12

12

12

12

12

+3VALW

RbRa

9.09K
20K

37.4K

Ra

1 2

12

Rb

0

+3VS

+5VALW

+3VALW

+5VS

0.25V

0.50V

0.82V

30 60Monday , April 20, 2009

Vab

0V

*

0.2

A

B

C

D

E

Internal KeyBoard Connector

KBD_DET#<30>

KSO[0.. 16]<30>

1 1

KSI [0..7]<30>

KSO[0.. 16]

KSI [0..7]

KBD_DET#
KSI7
KSI6
KSI4
KSI2
KSI5
KSI1
KSI3
KSI0
KSO5
KSO4
KSO7
KSO6
KSO8
KSO3
KSO1
KSO2
KSO0
KSO12
KSO16
KSO15
KSO13
KSO14
KSO9
KSO11
KSO10

DETECT GND

ME@

JKBD

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

GND

30

30

GND

JAE_FL4S 030HB3R3000

31
32

System LED

Power Button

+5VALW

R384

1 2

21

150_0402_5%~D

1 2

21

150_0402_5%~D

1 2

43

100_0402_5%

1 2

21

150_0402_5%~D

R471

R167

+5VS

R12

+5VALW

LED3

PWR_LED#

PWR_LED#<30>

SATA_LED#

SATA_LED#<22>

BATT_LOW_LED#<30>

BATT_CHG_LED#<30>

BATT_LOW_LED#

BATT_CHG_LED#

HT-F196BP5_WHITE

HT-263UD 5/BP5_AMBER-WHITE

CPN: SC500008F00

LED1

HT-F196BP5_WHITE

LED2

CIS Link:OK

03/03

KSO8

2 2

KSI3

KSO9

KSI2

KSI1

KSO10

KSO11

KSI0

KSO12

KSO13

KSO14

KSO15

KSO16

C449 100P_0402_25V8K@

C239 100P_0402_25V8K@

C249 100P_0402_25V8K@

C240 100P_0402_25V8K@

C248 100P_0402_25V8K@

C247 100P_0402_25V8K@

C242 100P_0402_25V8K@

C246 100P_0402_25V8K@

C245 100P_0402_25V8K@

C244 100P_0402_25V8K@

C243 100P_0402_25V8K@

C251 100P_0402_25V8K@

C235100P_0402_25V8K @

C236100P_0402_25V8K @

C237100P_0402_25V8K @

C441100P_0402_25V8K @

C442100P_0402_25V8K @C241 100P_0402_25V8K@

C443100P_0402_25V8K @

C238100P_0402_25V8K @

C444100P_0402_25V8K @

C445100P_0402_25V8K @

C446100P_0402_25V8K @

C447100P_0402_25V8K @

C448100P_0402_25V8K @

KSI7

KSI6

KSI5

KSO0

KSO1

KSO2

KSI4

KSO3

KSO4

KSO5

KSO6

KSO7

EC_ON<30>

PWR _ON-OFF_BTN#

+3VALW

@

4.7K_0402_5%

1 2

EC_ON

R296

1 2

0_0402_5%

R291

PWR _ON-OFF_BTN#<33>

+3VALW

D15

1

CHN20 2UPT SC-70

2

G

R1297
100K_0402_5%~D

1 2

2

3

1000P_0402_50V7K~D

13

D

Q26
SSM3K7002FU_SC70-3

S

2

1

12

C313

ON_OFF <30>

51ON# <41>

RLZ20A_LL34

D64

CIS Link:OK

PWR _ON-OFF_BTN#

2

3

D52
PESD24VS2UT_SOT23-3~D

1

12/29

SW1
SMT1-05-A_4P

3

4

CPN: SN100000W00

1

2

5

6

3 3

LID Switch Connector

Touch PAD Connector

CPN: SA032120010

CIS Link:OK

U50

+3VALW

0.1U_0402_16V7K~D

1

C274

2

4 4

A

A3212ELHLT-T_SOT23W-3

2

LID_SW#<30>

VDD

1

GND

OUTPUT

3

1

C1480

0.1U_0402_16V7K~D

2

B

+5VS

0.01U_0402_16V7K

1

2

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/01/05 2009/01/05

TP_CLK<30>
TP_DATA<30>

C300

Compal Secret Data

1 2

R421 100_0402_5%~D

1 2

R422 100_0402_5%~D

Deciphered Date

D

100P_0402_25V8K

1

@

2

TP_CLK_R
TP_DATA_R

100P_0402_25V8K

C309

1

@

C310

2

2

1

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

01/07

CIS Link:OK

ME@

JTP

1

1

2

2

3

5

3

GND

6

44GND

TYCO_2041084-4

3

D24
PJDLC05_SOT23-3

Compal Electronics, Inc.

Int KB / TP / LID SW / LED

LA-5162P

E

31 60Monday , April 20, 2009

0.2

A

B

C

D

E

+3VALW to +3VS Transfer

+3VALW

U40

SI4800 BDY-T1-E3_SO8

8

10U_0805_10V4Z~D

+B+_BIAS

330K_0402_5%

12

1 1

SUSP

R198

RU NON 3VS_GATE

13

D

Q18

2

G

SSM3K7002FU_SC70-3

S

1

C271

2

1 2

100K_0402_5%~D

7

5

R197

1
2
36

4

0.01U_0402_25V7K~D

1

C264

2

+3VS

0.1U_0402_16V7K~D

10U_0805_10V4Z~D

1

1

C465

C256

2

2

RUN ON<20>

+5VALW

10U_0805_10V4Z~D

1

2

1 2

U39

SI4800 BDY-T1-E3_SO8

8
7

5

C278

R267

47K_0402_5%

+5VS

1

0.1U_0402_16V7K~D

2
36

4

5VS_GATERU NON

0.01U_0402_25V7K~D

1

C279

2

10U_0805_10V4Z~D

1

1

C284

C283

2

2

+1.8V to +1.8VS Transfer+5VALW to +5VS Transfer

VGA_PWGOD#

SUSP

R1521

2@

1 2

0_0402_5%

R1522

1@

1 2

0_0402_5%

VGA_1.8VS_ON

+1.8V

10U_0805_10V4Z~D

2

G

+B+_BIAS

47K_0402_5%~D

1

CG727

2

RG559

1 2

1.8VS ON 1.8VS_GATE

13

D

SSM3K7002FU_SC70-3

S

QG48

RG608

1 2

100K_0402_5%~D

UG41

SI4800 BDY-T1-E3_SO8

8
7

5

4

CG696

+1.8VS

1
2
36

0.01U_0402_25V7K~D

1

2

10U_0805_10V4Z~D

0.1U_0402_16V7K~D

1

1

CG697

CG728

2

2

VGA Discharge circuit
SYSON>>>SUSP#>>>
VGA_ON>>>VGA_PWGOD

12

R646

2 2

+3VALW

12

R409
100K_0402_5%~D

SYSO N#

13

SYS ON

SYSON<27,30,45>

SUSP#

+5VALW

2

G

10K_0402_5%~D

R338

1 2

3 3

SUSP#< 27,30,44,46>

D

2

G

S

R365
10K_0402_5%~D

1 2

12

R340
100K_0402_5%~D

SUSP

13

D

Q32
SSM3K7002FU_SC70-3

S

Q42
SSM3K7002FU_SC70-3

SUSP <27,49>

Discharge circuit

+1.8VC CD_CB

12

R536

@

470_0402_5%

13

D

2

G

Q50

@

SSM3K7002FU_SC70-3

S

SYSO N#

2

G

SUSP

@

470_0402_5%

13

D

2

G

Q61

@

SSM3K7002FU_SC70-3

S

+1.8V +1.5VS

12

R133

@

470_0402_5%

13

D

Q12

@

SSM3K7002FU_SC70-3

S

+0.9VS

SUSP SUSPSUSP SUSP

2

G

+VGA_CORE+1.1VS_GFX_PCIE +1.8VS

12

R647

@

470_0402_5%

13

SUSP

12

@

470_0402_5%

13

D

S

D

2

G

@

SSM3K7002FU_SC70-3

S

R351

Q33

@

SSM3K7002FU_SC70-3

Q62

+5VS

12

R391

@

470_0402_5%

13

D

2

G

@

SSM3K7002FU_SC70-3

S

VGA_1.8VS_ON

Q39

2

G

SUSP

12

R609

@

470_0402_5%

13

D

Q65

@

SSM3K7002FU_SC70-3

S

+3VS

12

R383
39_0603_5%~D

13

D

2

G

S

Q38
SSM3K7002FU_SC70-3

12

@

470_0402_5%

13

D

2

G

SSM3K7002FU_SC70-3

S

R382

@

Q37

+5VALW +3VALW

12

12

4 4

VGA_PWGOD<47>

@

100K_0402_5%~D

VGA_PWGOD

A

R551

2

G

R668

2@

100K_0402_5%~D

VGA_PWGOD#

13

D

Q49

2@

SSM3K7002FU_SC70-3

S

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

DC/DC Circuits

LA-5162P

E

32 60Monday , April 20, 2009

0.2

5

4

3

2

1

Dual BOM Component

SD03415008L-1@

R74

SD028000080-2@

R75

Location

D D

R74

2@

0_0402_5%~D

C C

SD03415008L-1@
SD028000080-2@

R76

SD03415008L-1@
SD028000080-2@

R75

2@ R136

0_0402_5%~D

R76

2@

0_0402_5%~D

Dual BOM Component

SD03415008L-1@

R136

SD02815018L-@

R138

Location

@

1.5K_0402_5%~D

SD03415008L-1@
SD02815018L-@

R165 SD028000080-1@

SD028000080-@

@

1.5K_0402_5%~D

@

0_0402_5%~D

Dual BOM Component

R39 SD02800008L-1@

SD034470180-@

Location

4.7K_0402_1%

R334 SD03410018L-1@

R568 SD034470180-1@

R39

@

@R165

0_0402_5%~D

SD028000080-@

SD034470180-X76@

R334

R568

X76@R138

4.7K_0402_1%

Dual BOM Component

SD034499080-1@

R560

SD028470180-X76@

C1280

Location

X76@

4.7K_0402_5%

R560

SE00000888L-1@
SD028000080-X76@

U10

SA00002D700-1@
SA00002C610-X76@

C1280

X76@

0_0402_5%~D

U10

X76@

STHDLS101TQTR

H11

H16

H17

H_3P3

H1

H_3P0

H12

H_3P6

H19

H_1P6N

H_3P8

1

1

H2

H_3P0

1

1

H13

H_3P6

1

1

H20

H_2P5N

1

1

B B

A A

H_3P0

H3

H_3P0

H14

H_3P6

H18

H_3P0

1

1

H4

H5

H_2P8

H_3P0

1

1

H_3P6

1

1

H15

1

H6

H_3P0

1

H7

H_2P5X1P5N

1

H_3P0

H9

1

H10

H_3P0

1

FD1

1

FIDUC IAL MARK~D

Fiducial Mark

FD2

1

FIDUC IAL MARK~D

FD3

1

FIDUC IAL MARK~D

FD4

1

FIDUC IAL MARK~D

Power button switch for debug

PWR _ON-OFF_BTN#<31>

C655

100P_0402_50V8J~D@

1

2

PWR_S1

2

112

Place on Top

PWR_S2

2

112

Place on Bottom

Main Board PCB

ZZ Z

PCB

Liverpool_L A-5162P_REV0_M/B~D

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Doc ument Number Re v

Date: Sheet of

Compal Electronics, Inc.

Standoff and EE Design Part

LA-5162P

1

33 60Monday, A pril 20, 2009

1.0

5

D D

PEG_NTX_C_GRX_P[0..15]<12>

PEG_N TX_C_GRX_N[0..15]<12>

C C

B B

CLK_PC IE_ATI<6>
CLK_PC IE_ATI#<6>

4

PEG_NTX_C_GRX_P0
PEG_NTX_C_GRX_N0

PEG_NTX_C_GRX_P1
PEG_NTX_C_GRX_N1

PEG_NTX_C_GRX_P2
PEG_NTX_C_GRX_N2

PEG_NTX_C_GRX_P3
PEG_NTX_C_GRX_N3

PEG_NTX_C_GRX_P4
PEG_NTX_C_GRX_N4

PEG_NTX_C_GRX_P5
PEG_NTX_C_GRX_N5

PEG_NTX_C_GRX_P6
PEG_NTX_C_GRX_N6

PEG_NTX_C_GRX_P7
PEG_NTX_C_GRX_N7

PEG_NTX_C_GRX_P8
PEG_NTX_C_GRX_N8

PEG_NTX_C_GRX_P9
PEG_NTX_C_GRX_N9

PEG_NTX_C_GRX_P10
PEG_NTX_C_GRX_N10

PEG_NTX_C_GRX_P11
PEG_NTX_C_GRX_N11

PEG_NTX_C_GRX_P12
PEG_NTX_C_GRX_N12

PEG_NTX_C_GRX_P13
PEG_NTX_C_GRX_N13

PEG_NTX_C_GRX_P14
PEG_NTX_C_GRX_N14

PEG_NTX_C_GRX_P15
PEG_NTX_C_GRX_N15

PLT_RST#<10,21,27,30>

2@

UG5A

AF30

PCIE_RX0P

AE31

PCIE_RX0N

AE29

PCIE_RX1P

AD28

PCIE_RX1N

AD30

PCIE_RX2P

AC31

PCIE_RX2N

AC29

PCIE_RX3P

AB28

PCIE_RX3N

AB30

PCIE_RX4P

AA31

PCIE_RX4N

AA29

PCIE_RX5P

Y28

PCIE_RX5N

Y30

PCIE_RX6P

W31

PCIE_RX6N

W29

PCIE_RX7P

V28

PCIE_RX7N

V30

PCIE_RX8P

U31

PCIE_RX8N

U29

PCIE_RX9P

T28

PCIE_RX9N

T30

PCIE_RX10P

R31

PCIE_RX10N

R29

PCIE_RX11P

P28

PCIE_RX11N

P30

PCIE_RX12P

N31

PCIE_RX12N

N29

PCIE_RX13P

M28

PCIE_RX13N

M30

PCIE_RX14P

L31

PCIE_RX14N

L29

PCIE_RX15P

K30

PCIE_RX15N

CLOCK

AK30

PCIE_REFCLKP

AK32

PCIE_REFCLKN

L9

NC#1

N9

NC#2

N10

NC_PWRGOOD

AL27

PERSTB

216-07 28020 A12 M92-S2 LP_FCBGA631

PCI EXPRESS INTERFACE

PCIE_TX0P
PCIE_TX0N

PCIE_TX1P
PCIE_TX1N

PCIE_TX2P
PCIE_TX2N

PCIE_TX3P
PCIE_TX3N

PCIE_TX4P
PCIE_TX4N

PCIE_TX5P
PCIE_TX5N

PCIE_TX6P
PCIE_TX6N

PCIE_TX7P
PCIE_TX7N

PCIE_TX8P
PCIE_TX8N

PCIE_TX9P
PCIE_TX9N

PCIE_TX10P
PCIE_TX10N

PCIE_TX11P
PCIE_TX11N

PCIE_TX12P
PCIE_TX12N

PCIE_TX13P
PCIE_TX13N

PCIE_TX14P
PCIE_TX14N

PCIE_TX15P
PCIE_TX15N

CALIB RATION

PCIE_CALRP

PCIE_CALRN

3

PEG_NRX_C_GTX_P0

AH30

PEG_NRX_C_GTX_N0

AG31

AG29
AF28

PEG_NRX_C_GTX_P2

AF27

PEG_NRX_C_GTX_N2

AF26

AD27

PEG_NRX_C_GTX_N3

AD26

AC25

PEG_NRX_C_GTX_N4

AB25

Y23

PEG_NRX_C_GTX_N5 PEG_NRX_GTX_N5

Y24

PEG_NRX_C_GTX_P6

AB27

PEG_NRX_C_GTX_N6

AB26

PEG_NRX_C_GTX_P7

Y27
Y26

PEG_NRX_C_GTX_P8

W24

PEG_NRX_C_GTX_N8

W23

PEG_NRX_C_GTX_P9

V27

PEG_NRX_C_GTX_N9

U26

PEG_NRX_C_GTX_P10 PEG_NRX_GTX_P10

U24
U23

T26

PEG_NRX_C_GTX_N11

T27

T24

PEG_NRX_C_GTX_N12

T23

PEG_NRX_C_GTX_P13

P27

PEG_NRX_C_GTX_N13

P26

PEG_NRX_C_GTX_P14 PEG_NRX_GTX_P14

P24
P23

M27

PEG_NRX_C_GTX_N15 PEG_NRX_GTX_N15

N26

RG1 1.27K_04 02_1%2@

Y22

AA22

RG2 2K_ 0402_1%2@

1 2

1 2

CG1107 0.1U_0402_16V7K~D2@

1 2

CG1108 0.1U_0402_16V7K~D2@

1 2

CG1105 0.1U_0402_16V7K~D2@

1 2

CG1106 0.1U_0402_16V7K~D2@

1 2

CG1103 0.1U_0402_16V7K~D2@

1 2

CG1104 0.1U_0402_16V7K~D2@

1 2

CG1101 0.1U_0402_16V7K~D2@

1 2

CG1102 0.1U_0402_16V7K~D2@

1 2

CG1099 0.1U_0402_16V7K~D2@

1 2

CG1100 0.1U_0402_16V7K~D2@

1 2

CG1097 0.1U_0402_16V7K~D2@

1 2

CG1098 0.1U_0402_16V7K~D2@

1 2

CG1095 0.1U_0402_16V7K~D2@

1 2

CG1096 0.1U_0402_16V7K~D2@

1 2

CG1093 0.1U_0402_16V7K~D2@

1 2

CG1094 0.1U_0402_16V7K~D2@

1 2

CG1091 0.1U_0402_16V7K~D2@

1 2

CG1092 0.1U_0402_16V7K~D2@

1 2

CG1089 0.1U_0402_16V7K~D2@

1 2

CG1090 0.1U_0402_16V7K~D2@

1 2

CG1087 0.1U_0402_16V7K~D2@

1 2

CG1088 0.1U_0402_16V7K~D2@

1 2

CG1085 0.1U_0402_16V7K~D2@

1 2

CG1086 0.1U_0402_16V7K~D2@

1 2

CG1083 0.1U_0402_16V7K~D2@

1 2

CG1084 0.1U_0402_16V7K~D2@

1 2

CG1081 0.1U_0402_16V7K~D2@

1 2

CG1082 0.1U_0402_16V7K~D2@

1 2

CG1079 0.1U_0402_16V7K~D2@

1 2

CG1080 0.1U_0402_16V7K~D2@

1 2

CG1077 0.1U_0402_16V7K~D2@

1 2

CG1078 0.1U_0402_16V7K~D2@

1 2

+1.1VS_GFX_PCIE

2

PEG_NRX_GTX_P0
PEG_NRX_GTX_N0

PEG_NRX_GTX_P1PEG_NRX_C_GTX_P1
PEG_NRX_GTX_N1PEG_NRX_C_GTX_N1

PEG_NRX_GTX_P2
PEG_NRX_GTX_N2

PEG_NRX_GTX_P3PEG_NRX_C_GTX_P3
PEG_NRX_GTX_N3

PEG_NRX_GTX_P4PEG_NRX_C_GTX_P4
PEG_NRX_GTX_N4

PEG_NRX_GTX_P5PEG_NRX_C_GTX_P5

PEG_NRX_GTX_P6
PEG_NRX_GTX_N6

PEG_NRX_GTX_P7
PEG_NRX_GTX_N7PEG_NRX_C_GTX_N7

PEG_NRX_GTX_P8
PEG_NRX_GTX_N8

PEG_NRX_GTX_P9
PEG_NRX_GTX_N9

PEG_NRX_GTX_N10PEG_NRX_C_GTX_N10

PEG_NRX_GTX_P11PEG_NRX_C_GTX_P11
PEG_NRX_GTX_N11

PEG_NRX_GTX_P12PEG_NRX_C_GTX_P12
PEG_NRX_GTX_N12

PEG_NRX_GTX_P13
PEG_NRX_GTX_N13

PEG_NRX_GTX_N14PEG_NRX_C_GTX_N14

PEG_NRX_GTX_P15PEG_NRX_C_GTX_P15

PEG_NRX_GTX_P[0..15] <12>

PEG_NRX_GTX_N[0..15] <12>

1

CIS Link:OK

CPN:SA000030O10

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

2

Date: Sheet of

Compal Electronics, Inc.

M92 S2-LP PCIE interface

LA-5162P

1

34 60Monday , April 20, 2009

0.1

5

Q11A

2@

SSM6N7002FU_US6~D

ATI_ED ID_CLK_LCD<19>

ATI_EDID _DAT_LCD<19>

D D

+3VS_DELAY

1 2

RG3 4.7K_0402_5%2@

1 2

RG4 4.7K_0402_5%2@

1 2

RG8 10K_0402_5%~D2@

C C

B B

A A

RG9 10K_0402_5%2@

+1.8VS

2@

1 2

MCK1608471YZF 0603

+1.1VS_GFX_PCIE

2@

1 2

MCK1608471YZF 0603

XTALIN

1 2

CLK_ATI_27M_SS<6>

LG1

LG2

18P_0402_50V8

1

2

2@

CG53

6 1

+3VS_DELAY

354

2@

SSM6N7002FU_US6~D

+3VS_DELAY

RG188

2@

8.2K_0402_5%~D

1 2

B

2

E

3 1

C

ACIN<30,42>

QG13

2@

MMBT3904_NL_SOT23-3

AMD_ED ID_CLK_LCD

AMD_EDID_D AT_LCD

ATI_CLK_REQ#

ATI_ENBKL

RG84 0_0402_5%@

(1.8V@120mA +DPLL_PVDD)

10U_0603_6.3V6M

1U_0402_6.3V4Z

2@

2@

1

1

CG33

CG34

2

2

(1.1V@300mA +DPLL_VDDC)

10U_0603_6.3V6M

1U_0402_6.3V4Z

2@

2@

1

1

CG36

CG37

2

2

CLK_ATI_27M<6>

RG30

2@

1 2

1M_0402_5%

YG1

2@

4

GND

OUT

1

IN

GND

27MHz_16PF_6P27000126

Close to M92

1 2

+3VS_DELAY

0.1U_0402_10V6K

0.1U_0402_10V6K

3

2

2

Q11B

RG668

10K_0402_5%~D

1 2

ATI_ACIN

+DPLL_PVDD

2@

1

CG35

2

+1.8VS

+DPLL_VDDC

2@

1

CG38

2

+1.8VS

18P_0402_50V8

AMD_ED ID_CLK_LCD

AMD_EDID_D AT_LCD

2@

LVDS

ATI_SMBDATA<39>

ATI_SMBCLK<39>

ATI_GPIO11<39>
ATI_GPIO12<39>
ATI_GPIO13<39>

ATI_THM_ALERT#<39>

ATI_ROMCSB<39>

ATI_CLK_REQ#<6>

1 2

RG5 10K_0402_5%2@

1 2

RG12 10K_0402_5%@

ATI_HDM I_HPD<20>

CG47 0 .1U_0402_10V6K2@
RG19 249_0402_1%2@

1 2

RG17 499_0402_1%2@

1 2

RG93 75_0402_1%~D2@

1 2

RG103 0_0402_5%@

1 2

ATI_THERMAL_D+<39>
ATI_THERMAL_D-<39>

LG8

2@

(1.8V@20mA TSVDD)

12

BLM18PG121SN1D_0603

XTALOUT

2@

1

CG52

2

VRAM_ID0<39>
VRAM_ID1<39>
VRAM_ID2<39>
VRAM_ID3<39>

ATI_GPIO0<39>
ATI_GPIO1<39>
ATI_GPIO2<39>

ATI_ENBKL<19>

ATI_ROMSI<39>

GPU_VID0<47>

RG26 1K_0402_1%2@

1 2

10U_0603_6.3V6M

AMD_ED ID_CLK_LCD
AMD_EDID_D AT_LCD

1 2

1U_0402_6.3V4Z

2@

1

CG162

2

1

2

ATI_ACIN

ATI_ENBKL

T5

T3

T4
T6

T57

ATI_ROMCSB
ATI_CLK_REQ#

T1
T58
T59
T60

TESTEN

T70

+DPLL_PVDD

+DPLL_VDDC

XTALIN
XTALOUT

T86

0.1U_0402_10V6K

2@

2@

1

CG50

CG51

2

4

2@

UG5B

MUTI GFX

AA1

DVPCNTL_MVP_0

Y4

DVPCNTL_MVP_1

AC7

DVPCNTL_0

Y2

DVPCNTL_1

U5

DVPCNTL_2

U1

DVPCLK

Y7

DVPDATA_0

V2

DVPDATA_1

Y8

DVPDATA_2

V4

DVPDATA_3

AB7

DVPDATA_4

W1

DVPDATA_5

AB8

DVPDATA_6

W3

DVPDATA_7

AB9

DVPDATA_8

W5

DVPDATA_9

AC6

DVPDATA_10

W6

DVPDATA_11

AD7

DVPDATA_12

AA3

DVPDATA_13

AC8

DVPDATA_14

AA5

DVPDATA_15

AE8

DVPDATA_16

AA6

DVPDATA_17

AE9

DVPDATA_18

AB4

DVPDATA_19

AD9

DVPDATA_20

AB2

DVPDATA_21

AC10

DVPDATA_22

AC5

DVPDATA_23

I2C

R1

SCL

R3

SDA

GENERAL PURPOSE I/O

U6

GPIO_0

U10

GPIO_1

T10

GPIO_2

U8

GPIO_3_SMBDATA

U7

GPIO_4_SMBCLK

T9

GPIO_5_AC_BATT

T8

GPIO_6

T7

GPIO_7_BLON

P10

GPIO_8_ROMSO

P4

GPIO_9_ROMSI

P2

GPIO_10_ROMSCK

N6

GPIO_11

N5

GPIO_12

N3

GPIO_13

Y9

GPIO_14_HPD2

N1

GPIO_15_PWRCNTL_0

M4

GPIO_16_SSIN

R6

GPIO_17_THERMAL_INT

W10

GPIO_18_HPD3

M2

GPIO_19_CTF

P8

GPIO_20_PWRCNTL_1

P7

GPIO_21_BB_EN

N8

GPIO_22_ROMCSB

N7

GPIO_23_CLKREQB

T11

GPIO_29_DRM_0

R11

GPIO_30_DRM_1

L6

JTAG_TRSTB

L5

JTAG_TDI

L3

JTAG_TCK

L1

JTAG_TMS

K4

JTAG_TDO

AF24

TESTEN

AB13

GENERICA

W8

GENERICB

W9

GENERICC

W7

GENERICD

AD10

GENERICE_HPD4

AC14

HPD1

AC16

VREFG

PLL/CLOCK

AF14

DPLL_PVDD

AE14

DPLL_PVSS

AD14

DPLL_VDDC

AM28

XTALIN

AK28

XTALOUT

T4

DPLUS

THERMAL

DMINUS

TS_FDO
TSVDD
TSVSS

216-0728020 A12 M92-S2 LP_FCBGA631

AD17
AC17

T2

R5

DPA

DPB

DAC1

DAC2

DDC/AUX

TXCAP_DPA3P

TXCAM_DPA3N

TX0P_DPA2P

TX0M_DPA2N

TX1P_DPA1P

TX1M_DPA1N

TX2P_DPA0P

TX2M_DPA0N

TXCBP_DPB3P

TXCBM_DPB3N

TX3P_DPB2P

TX3M_DPB2N

TX4P_DPB1P

TX4M_DPB1N

TX5P_DPB0P

TX5M_DPB0N

HSYNC

VSYNC

RSET

AVDD

AVSSQ

VDD1DI
VSS1DI

COMP

H2SYNC
V2SYNC

VDD2DI
VSS2DI

A2VDD

A2VDDQ

A2VSSQ

R2SET

DDC1CLK

DDC1DATA

AUX1P

AUX1N

DDC2CLK

DDC2DATA

AUX2P

AUX2N

DDCAUX5P
DDCAUX5N

DDC6CLK

DDC6DATA

NC_DDCAUX7P

NC_DDCAUX7N

3

AF2
AF4

AG3
AG5

AH3
AH1

AK3
AK1

AK5
AM3

AK6
AM5

AJ7
AH6

AK8
AL7

AM26

R

AK26

RB

AL25

G

AJ25

GB

AH24

B

AG25

BB

AH26
AJ27

AD22

AG24
AE22

AE23
AD23

AM12

R2

AK12

R2B

AL11

G2

AJ11

G2B

AK10

B2

AL9

B2B

AH12

C

AM10

Y

AJ9

AL13
AJ13

+VDD2DI

AD19
AC19

+A2VDD

AE20

+A2VDDQ

AE17

AE19

AG13

RG28 715_0402_1%~D2@

AE6
AE5

AD2
AD4

AC11
AC13

AD13
AD11

AB22

NC1

AC22

NC2

AE16
AD16

AC1
AC3

AD20
AC20

RG6 499_0402_1%2@

+AVDD

+VDD1DI

1 2

RG18 150_0402_1%2@

RG10 150_0402_1%2@

RG11 150_0402_1%2@

1 2

ATI_HDMI_CLK+ <20>
ATI_HDMI_CLK- <20>

ATI_HDMI_TX0+ <20>
ATI_HDMI_TX0- <20>

ATI_HDMI_TX1+ <20>
ATI_HDMI_TX1- <20>

ATI_HDMI_TX2+ <20>
ATI_HDMI_TX2- <20>

1 2

1 2

1 2

ATI_HSY NC <19,39>
ATI_VSYNC <19,39>

ATI_DDC_CLK <19>
ATI_DDC_DAT <19>

HDMICLK_ATI <20>

HDMIDAT_ATI <20>

+3VS_DELAY

ATI_CRT_R <19>

ATI_CRT_G <19>

ATI_CRT_B <19>

(1.8V@70 mA +AVDD)

0.1U_0402_10V6K

10U_0603_6.3V6M

1U_0402_6.3V4Z

2@

2@

1

1

CG40

CG39

2

2

(1.8V@45mA +VDD1DI)

1U_0402_6.3V4Z

0.1U_0402_10V6K

10U_0603_6.3V6M

2@

2@

1

1

CG41

CG42

2

2

(1.8V@40mA +VDD2DI)

10U_0603_6.3V6M

1U_0402_6.3V4Z

0.1U_0402_10V6K

@

@

1

1

CG43

CG44

2

2

(1.8V@2mA +A2VDDQ)

CRT

HDMI

LG7

2@

0_0603_5%

2@

1 2

BLM18PG121SN1D_0603

2@

1

CG157

2

2@

1 2

BLM18PG121SN1D_0603

2@

1

CG158

2

2@

1 2

0_0603_5%

@

1

CG159

2

0.1U_0402_10V6K

1

2

(3.3V@65 mA +A2VDD)

12

@

1

CG161

2

LG3

LG5

1U_0402_6.3V4Z

2@

CG46

10U_0603_6.3V6M

@

CG48

2

2@

UG5F

LVDS CONTROL

VARY_BL

DIGON

TXCLK_UP_DPF3P
TXCLK_UN_DPF3N

TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N

TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N

TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N

TXOUT_U3P
TXOUT_U3N

LVTMDP

TXCLK_LP_DPE3P

TXCLK_LN_DPE3N

TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N

TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N

TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N

TXOUT_L3P

+1.8VS

216-0728020 A12 M92-S2 LP_FCBGA631

LG4

12

LG6

2@

BLM18PG121SN1D_0603

10U_0603_6.3V6M

2@

2@

1

1

CG160

CG45

2

2

+A2VDD

1U_0402_6.3V4Z

0.1U_0402_10V6K

@

1

1

CG49

2

2

TXOUT_L3N

AB11
AB12

AH20
AJ19

AL21
AK20

AH22
AJ21

AL23
AK22

AK24
AJ23

AL15
AK14

AH16
AJ15

AL17
AK16

AH18
AJ17

AL19
AK18

1

T76

ATI_LVDDEN <19>

ATI_LVDSAC+ <19>
ATI_LVDSAC- <19>

ATI_LVDSA0+ < 19>
ATI_LVDSA0- <19>

ATI_LVDSA1+ < 19>
ATI_LVDSA1- <19>

ATI_LVDSA2+ < 19>
ATI_LVDSA2- <19>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

M92 S2-LP LVDS/HDMI/CRT

Size D ocument Number Rev

2

Date: Sheet of

LA -51 62P

35 60Monday , April 20, 2009

1

0.1

5

2@

D D

+1.8VS

2@

2@

2@

2@

RG71

RG32

+1.8VS

RG63

RG36

12

+VDD_MEM18_REFD

12

1

2@

0.1U_0402_16V4Z

2

12

+VDD_MEM18_REF1

12

1

2@

0.1U_0402_16V4Z

2

+1.8VS

CG61

CG62

MDA[6 3..32]<38>

RG38 243_0 402_1%@
RG40 243_0 402_1%@

RG81 243_0 402_1%2@
RG42 243_0 402_1%@

RG45 4.7K_040 2_5%2@
RG46 4.7K_040 2_5%2@

1 2
1 2

1 2
1 2

1 2
1 2

+VDD_MEM18_REFD
+VDD_MEM18_REF1

C C

100_0402_1%

100_0402_1%

100_0402_1%

100_0402_1%

B B

UG5C

MDA0

K27

DQA_0

MDA1

J29

DQA_1

MDA2

H30

DQA_2

MDA3

H32

DQA_3

MDA4

G29

DQA_4

MDA5

F28

DQA_5

MDA6

F32

DQA_6

MDA7

F30

DQA_7

MDA8

C30

DQA_8

MDA9

F27

MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39 WDQSA4
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

DQA_9

A28

DQA_10

C28

DQA_11

E27

DQA_12

G26

DQA_13

D26

DQA_14

F25

DQA_15

A25

DQA_16

C25

DQA_17

E25

DQA_18

D24

DQA_19

E23

DQA_20

F23

DQA_21

D22

DQA_22

F21

DQA_23

E21

DQA_24

D20

DQA_25

F19

DQA_26

A19

DQA_27

D18

DQA_28

F17

DQA_29

A17

DQA_30

C17

DQA_31

E17

DQA_32

D16

DQA_33

F15

DQA_34

A15

DQA_35

D14

DQA_36

F13

DQA_37

A13

DQA_38

C13

DQA_39

E11

DQA_40

A11

DQA_41

C11

DQA_42

F11

DQA_43

A9

DQA_44

C9

DQA_45

F9

DQA_46

D8

DQA_47

E7

DQA_48

A7

DQA_49

C7

DQA_50

F7

DQA_51

A5

DQA_52

E5

DQA_53

C3

DQA_54

E1

DQA_55

G7

DQA_56

G6

DQA_57

G1

DQA_58

G3

DQA_59

J6

DQA_60

J1

DQA_61

J3

DQA_62

J5

DQA_63

K26

MVREFDA

J26

MVREFSA

J25

NC_MEM_CALRN0

K7

NC_MEM_CALRN1

J8

MEM_CALRP1

K25

NC_MEM_CALRP0

L10

DRAM_RST

K8

CLKTESTA

L7

CLKTESTB

216-072802 0 A12 M92-S2 LP_FCBGA631

MEMORY INTERFACE

MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8

MAA_9
MAA_10
MAA_11
MAA_12

MAA_13/BA2
MAA_14/BA0
MAA_15/BA1

DQMA_0
DQMA_1
DQMA_2
DQMA_3
DQMA_4
DQMA_5
DQMA_6
DQMA_7

RDQSA_0
RDQSA_1
RDQSA_2
RDQSA_3
RDQSA_4
RDQSA_5
RDQSA_6
RDQSA_7

WDQSA_0
WDQSA_1
WDQSA_2
WDQSA_3
WDQSA_4
WDQSA_5
WDQSA_6
WDQSA_7

ODTA0

ODTA1

CLKA0

CLKA0B

CLKA1

CLKA1B

RASA0B
RASA1B

CASA0B
CASA1B

CSA0B_0
CSA0B_1

CSA1B_0
CSA1B_1

CKEA0

CKEA1

WEA0B
WEA1B

RSVD#1
RSVD#2
RSVD#3

4

K17
J20
H23
G23
G24
H24
J19
K19
J14
K14
J11
J13
H11
G11
J16
L15

E32
E30
A21
C21
E13
D12
E3
F4

H28
C27
A23
E19
E15
D10
D6
G5

H27
A27
C23
C19
C15
E9
C5
H4

L18
K16

H26
H25

G9
H9

G22
G17

G19
G16

H22
J22

G13
K13

K20
J17

G25
H10

AB16
G14
G20

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
BA2
BA0
BA1

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

RDQSA0
RDQSA1
RDQSA2
RDQSA3
RDQSA4
RDQSA5
RDQSA6
RDQSA7

WDQSA0
WDQSA1
WDQSA2
WDQSA3

WDQSA5
WDQSA6
WDQSA7

ODTA0
ODTA1

CLKA0
CLKA0#

CLKA1
CLKA1#

RASA#0
RASA#1

CASA#0
CASA#1

CSA0#

CSA1#

CKEA0
CKEA1

WEA#0
WEA#1

T62
T63
T64

MAA[1 2..0] <37,38>MDA[3 1..0]<37>

BA2 <37,38>
BA0 <37,38>
BA1 <37,38>

DQMA#0 <37>
DQMA#1 <37>
DQMA#2 <37>
DQMA#3 <37>
DQMA#4 <38>
DQMA#5 <38>
DQMA#6 <38>
DQMA#7 <38>

RDQS A[3..0] <37>

RDQS A[7..4] <38>

WDQS A[3..0] <37>

WDQS A[7..4] <38>

ODTA0 <37>
ODTA1 <38>

CLKA0 <37>
CLKA0# <37>

CLKA1 <38>
CLKA1# <38>

RASA#0 <37>
RASA#1 <38>

CASA#0 <37>
CASA#1 <38>

CSA0# <37>

CSA1# <38>

CKEA0 <37>
CKEA1 <38>

WEA#0 <37>
WEA#1 <38>

3

+1.8VS

BLM18PG121SN1D_0603

+DPE_VDD18

2@

1 2

0_0402_5%

+1.1VS_GFX_PCIE +DPA_VDD10

2@

BLM18PG121SN1D_0603

+1.8VS +1.8VS

2@

BLM18PG121SN1D_0603

(1.8V@200mA +DPE_VDD18)

LG9

2@

12

RG37

10U_0603_6.3V6M

(1.1V@170mA +DPF_VDD10)

LG11

12

10U_0603_6.3V6M

LG12

(1.8V@20mA +DPE_PVDD)

12

10U_0603_6.3V6M

10U_0603_6.3V6M

1

2

1

2

1

2

+DPE_VDD18

1U_0402_6.3V4Z

0.1U_0402_10V6K

2@

2@

1

CG54

2

+DPF_V DD18

0.1U_0402_10V6K

@

1

CG71

2

0.1U_0402_10V6K

2@

1

CG59

2

0.1U_0402_10V6K

2@

1

CG263

2

2@

1

CG55

2

+DPF_V DD10

@

1

CG72

2

+DPF_V DD10

2@

1

CG60

2

RG34

2@

150_0402_1%

1 2

+DPE_PVDD

2@

1

+DPE_PVDD

CG64

2

1

CG163

2

1U_0402_6.3V4Z

@

CG266

1U_0402_6.3V4Z

2@

CG165

1U_0402_6.3V4Z

2@

CG166

2

2@

UG5G

AG15

DPE_VDD18#1

AG16

DPE_VDD18#2

AG20

DPE_VDD10#1

AG21

DPE_VDD10#2

AG14

DPE_VSSR#1

AH14

DPE_VSSR#2

AM14

DPE_VSSR#3

AM16

DPE_VSSR#4

AM18

DPE_VSSR#5

AF16

DPF_VDD18#1

AG17

DPF_VDD18#2

AF22

DPF_VDD10#1

AG22

DPF_VDD10#2

AF23

DPF_VSSR#1

AG23

DPF_VSSR#2

AM20

DPF_VSSR#3

AM22

DPF_VSSR#4

AM24

DPF_VSSR#5

AF17

DPEF_CALR

AG18

DPE_PVDD

AF19

DPE_PVSS

AG19

NC_DPF_PVDD

AF20

NC_DPF_PVSS

216-072802 0 A12 M92-S2 LP_FCBGA631

DP PL L POWER

DP A/ B POWERDP E/F P OWER

NC_DPA_VDD18#1
NC_DPA_VDD18#2

DPA_VDD10#1
DPA_VDD10#2

DPA_VSSR#1
DPA_VSSR#2
DPA_VSSR#3
DPA_VSSR#4
DPA_VSSR#5

NC_DPB_VDD18#1
NC_DPB_VDD18#2

DPB_VDD10#1
DPB_VDD10#2

DPB_VSSR#1
DPB_VSSR#2
DPB_VSSR#3
DPB_VSSR#4
DPB_VSSR#5

DPAB_CALR

DPA_PVDD
DPA_PVSS

DPB_PVDD
DPB_PVSS

AE11
AF11

(1.1V@ 200mA +DPA_VDD10)

+DPA_VDD10

AF6

10U_0603_6.3V6M

AF7

AE1
AE3
AG1
AG6
AH5

AE13
AF13

AF8
AF9

AF10
AG9
AH8
AM6
AM8

AE10

RG35

2@

150_0402_1%

1 2

2@

1

CG56

2

(1.8V@ 20mA +DPA_PVDD)

+DPA_PVDD

AG8
AG7

AG10
AG11

10U_0603_6.3V6M

1

2

(1.8V@20mA +DPB_PVDD)

+DPB_PVDD

10U_0603_6.3V6M

1

2

1

2@

0.1U_0402_10V6K

1U_0402_6.3V4Z

2@

1

CG57

2

1U_0402_6.3V4Z

2@

2@

1

CG265

CG366

2

1U_04 02_6.3V4Z

@

@

1

CG68

CG69

2

2@

1

CG58

2

0.1U_0402_10V6K
BLM18PG121SN1D_0603

2@

1

CG67

2

0.1U_0402_10V6K

@

1

CG70

2

BLM18PG121SN1D_0603

LG13

2@

LG14

2@

0_0603_5%~D

+1.1VS_GFX_PCIE

LG10

12

12

+1.8VS

12

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

2

Date: Sheet of

Compal Electronics, Inc.

M92 S2-LP MEM

LA-5162P

1

36 60Monday , April 20, 2009

0.1

5

4

3

2

1

D D

MAA[1 2..0]<36,38> MAA[1 2..0]<36,38>

C C

+1.8VS

4.99K_0402_1%

2@

12

R195

0.1U_0402_16V4Z

4.99K_0402_1%

B B

2@

2@

12

1

C122

R199

2

BA0<36,38>
BA1<36,38>

+VRAM_REF1

CLKA0#<36>
CLKA0<36>

CKEA0< 36>

CSA0#<36>

WEA#0<36>

RASA#0<36>

CASA#0<36>

DQMA#0<36>
DQMA#1<36>

ODTA0<36>

BA0
BA1

MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

RDQSA0
WDQSA0

RDQSA1
WDQSA1

CPN:SA00002UH00

UG12

2@

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

K3

WE

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

BA2

R3

NC#R3

R7

NC#R7

R8

NC#R8

K4N1G 164QQ-HC20_FBGA84

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDDQ10

VDD1
VDD2
VDD3
VDD4
VDD5

VDDL

VSSDL

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSSQ10

VSS1
VSS2
VSS3
VSS4
VSS5

CIS Link:OK

UG13

MDA12

B9

MDA10

B1

MDA13

D9

MDA8

D1

MDA9

D3

MDA15

D7

MDA11

C2

MDA14

C8

MDA5

F9

MDA4

F1

MDA0

H9

MDA7

H1

MDA6

H3

MDA1

H7

MDA3

G2

MDA2

G8

A9

+1.8VS +1.8VS

C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9
M9
R1

J1
J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

+1.8VS +1.8VS

0.1U_0402_16V4Z

2@

1

C195

2

MDA[3 1..0]

RD QSA[3..0]

WDQS A[3..0]

1U_04 02_6.3V4Z

2@

1

C194

2

CLKA0

CLKA0<36>

CLKA0#

CLKA0#<36>

56_0402_5%

12

470P_0402_50V7K

MDA[3 1..0] <36>

RDQS A[3..0] <36>

WDQS A[3..0] <36>

56_0402_5%

2@

2@

12

R190

R194

2@

1

C142

2

4.99K_0402_1%

4.99K_0402_1%

+1.8VS

12

12

BA0<36,38>
BA1<36,38>

2@

R192

0.1U_0402_16V4Z

2@

2@

1

C99

R196

2

CLKA0#<36>
CLKA0<36>

CKEA0< 36>

CSA0#<36>

WEA#0<36>

RASA#0<36>

CASA#0<36>

DQMA#2<36>
DQMA#3<36>

ODTA0<36>

+VRAM_REF2

BA0
BA1

MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

RDQSA2
WDQSA2

RDQSA3
WDQSA3

BA2<36,38>BA2<36,38>

2@

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

K3

WE

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

BA2

R3

NC#R3

R7

NC#R7

R8

NC#R8

K4N1G 164QQ-HC20_FBGA84

CIS Link:OK

CPN:SA00002UH00

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDDQ10

VDD1
VDD2
VDD3
VDD4
VDD5

VDDL

VSSDL

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSSQ10

VSS1
VSS2
VSS3
VSS4
VSS5

MDA28

B9

MDA27

B1

MDA31

D9

MDA26

D1

MDA24

D3

MDA29

D7

MDA25

C2

MDA30

C8

MDA22

F9

MDA16

F1

MDA23

H9

MDA17

H1

MDA19

H3

MDA21

H7

MDA18

G2

MDA20

G8

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9
M9
R1

J1
J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

0.1U_0402_16V4Z

1U_04 02_6.3V4Z

2@

2@

1

1

C161

C192

2

2

DDR2 64MX16(128MB)DDR2 64MX16(128MB)

+1.8VS+1.8VS

10U_0603_6.3V6M

A A

5

1U_04 02_6.3V4Z

10U_0603_6.3V6M

2@

2@

1

1

C94

C215

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2@

1

C1231

2

4

0.1U_0402_16V4Z

2@

2@

1

1

C115

C228

2

2

0.01U_0402_16V7K

0.1U_0402_16V4Z

2@

1

C207

2

2@

2@

1

1

C193

C210

2

2

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/02/06 201002/06

10U_0603_6.3V6M

Compal Secret Data

Deciphered Date

1U_04 02_6.3V4Z

10U_0603_6.3V6M

2@

2@

1

1

C217

C229

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2@

2@

1

1

C211

C230

2

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2@

1

C216

2

0.01U_0402_16V7K

2@

2@

1

C141

2

2@

1

1

C103

C224

2

2

Title

Size Doc ument Number Re v

Date: Sheet of

Compal Electronics, Inc.

DDR2-A

LA-5162P

1

37 60Monday , April 20, 2009

0.1

5

4

3

2

1

DDR2 64MX16(128MB)DDR2 64MX16(128MB)

UG15

D D

MAA[1 2..0]<36,37>

C C

+1.8VS

4.99K_0402_1%

2@

12

R200

0.1U_0402_16V4Z

4.99K_0402_1%

B B

2@

2@

12

1

C299

R205

2

BA0<36,37>
BA1<36,37>

+VRAM_REF3

BA0
BA1

MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

CLKA1#<36>
CLKA1<36>

CKEA1< 36>

CSA1#<36>

WEA#1<36>

RASA#1<36>

CASA#1<36>

DQMA#4<36>
DQMA#5<36>

ODTA1<36>

RDQSA4
WDQSA4

RDQSA5
WDQSA5

CPN:SA00002UH00

2@

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

K3

WE

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

BA2

R3

NC#R3

R7

NC#R7

R8

NC#R8

K4N1G 164QQ-HC20_FBGA84

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDDQ10

VDD1
VDD2
VDD3
VDD4
VDD5

VDDL

VSSDL

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSSQ10

VSS1
VSS2
VSS3
VSS4
VSS5

CIS Link:OK

MDA45

B9

MDA41

B1

MDA46

D9

MDA40

D1

MDA43

D3

MDA47

D7

MDA42

C2

MDA44

C8

MDA36

F9

MDA33

F1

MDA37

H9

MDA32

H1

MDA38

H3

MDA39

H7

MDA34

G2

MDA35

G8

A9

+1.8VS +1.8VS

C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9
M9
R1

J1
J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

+1.8VS +1.8VS

0.1U_0402_16V4Z

2@

1

C263

2

MDA[6 3..32]

RD QSA[7..4]

WDQS A[7..4]

1U_0402_6.3V4Z

2@

1

C265

2

CLKA1

CLKA1<36>

CLKA1#

CLKA1#<36>

56_0402_5%

12

470P_0402_50V7K

MDA[6 3..32] <36>

RDQS A[7..4] <36>

WDQS A[7..4] <36>

56_0402_5%

2@

2@

12

R201

R204

2@

1

C231

2

4.99K_0402_1%

4.99K_0402_1%

+1.8VS

12

12

BA0<36,37>
BA1<36,37>

MAA[1 2..0]<36,37>

2@

R206

0.1U_0402_16V4Z

2@

2@

1

R202

C298

2

CLKA1#<36>
CLKA1<36>

CKEA1< 36>

CSA1#<36>

WEA#1<36>

RASA#1<36>

CASA#1<36>

DQMA#7<36>
DQMA#6<36>

ODTA1<36>

+VRAM_REF4

BA0
BA1

MAA12MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

RDQSA7
WDQSA7

RDQSA6
WDQSA6

BA2<36,37>BA2<36,37>

CPN:SA00002UH00

UG16

2@

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

K3

WE

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC#A2

E2

NC#E2

L1

BA2

R3

NC#R3

R7

NC#R7

R8

NC#R8

K4N1G 164QQ-HC20_FBGA84

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDDQ10

VDD1
VDD2
VDD3
VDD4
VDD5

VDDL

VSSDL

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSSQ10

VSS1
VSS2
VSS3
VSS4
VSS5

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9
M9
R1

J1
J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

CIS Link:OK

MDA52
MDA51
MDA53
MDA50
MDA48
MDA55
MDA49
MDA54
MDA58
MDA56
MDA61
MDA60
MDA63
MDA62
MDA57
MDA59

0.1U_0402_16V4Z

1U_0402_6.3V4Z

2@

2@

1

1

C301

C303

2

2

+1.8VS+1.8VS

10U_0603_6.3V6M

10U_0603_6.3V6M

2@

1

C290

2

A A

5

0.1U_0402_16V4Z

1U_0402_6.3V4Z

2@

2@

1

1

C266

C302

2

2

4

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2@

2@

1

1

C286

C294

2

2

0.01U_0402_16V7K

0.1U_0402_16V4Z

2@

1

C260

2

2@

2@

1

1

C261

C267

2

2

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/02/06 201002/06

10U_0603_6.3V6M

Compal Secret Data

Deciphered Date

1U_0402_6.3V4Z

10U_0603_6.3V6M

2@

1

C288

2

0.1U_0402_16V4Z

2@

2@

1

1

C280

C293

2

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2@

2@

1

1

C289

C295

2

2

0.01U_0402_16V7K

0.1U_0402_16V4Z

2@

1

C253

2

2@

2@

1

1

C287

C304

2

2

Title

Size Doc ument Number Re v

Date: Sheet of

Compal Electronics, Inc.

DDR2-B

LA-5162P

1

38 60Monday , April 20, 2009

0.1

5

Q5A

2@

2N7002DW -T/R7_SOT363-6~D

SMB_CLK_THERMAL<18,30>

SMB_DATA_THERMAL<18,30>

D D

6 1

+3VS_DE LAY

3

2@

2N7002DW -T/R7_SOT363-6~D

Q5B

2

5

ATI_SMBCLK

ATI_SMBDATA

4

Configuration Straps

ATI_GPIO0<35>
ATI_GPIO1<35>
ATI_GPIO2<35>

ATI_ROMSI<35>
ATI_GPIO11<35>
ATI_GPIO12<35>
ATI_GPIO13<35>

ATI_ROMCSB<35>

ATI_V SYNC<19,35>
ATI_ HSYNC<19,35>

4

3

2

1

ATI-M92-S2 Strap Pin Table

Strap Name Pin Name

0 --> Driver woul d ing ore the value
sampled on DVPDATA_20 during reset.

RG50 10K_0402_5%@
RG51 10K_0402_5%@
RG52 10K_0402_5%~D@

RG54 10K_0402_5%@
RG55 10K_0402_5%2@
RG56 10K_0402_5%@
RG57 10K_0402_5%@

RG573 10K _0402_5%~D@

RG58 10K_0402_5%2@
RG159 10K _0402_5%2@

+3VS_ DELAY

12
12
12

12
12
12
12

12

12
12

VIP_DEVICE_STRAP_EN

VGA_DIS GPIO_9_ROMSI

TX_PWRS_ENB GPIO_0 0 --> 50% Tx output swing

V2SYNC

1 --> Driver woul d use the sampled value
sampled at reset from DVPDATA_20
to dete rmine whethe r or not.

0 --> VGA Co ntroll er capacity enabled.

1 --> The de vice w ill not be recog nized
as the system's VGA controller.

Transmi tter P ower Savings Enable

1 --> Full Tx output swing

Description Setting

0

0

0

*

*

*

PCI-Express Transmitter De-emphasis Enable

TX_DEEMPH_EN GPIO_1

VGA Thermal Sensor ADM1032ARMZ

+3VS_ DELAY

CG155

2@

C C

0.1U_0402_16V4Z

ATI_THM_ALERT#<35>

2@

4.7K_0402_5%

CIS Link:OK

12

12

2@

1

RG70

VDD1

6

ALERT#

4

THERM#

5

GND

ADM1032ARMZ-2REEL_MSOP8

UG1

SCLK

SDATA

2

D+

3

D-

8

7

12

CG1562200P_0402_50V7K 2@

ATI_THERMAL_D+ <35>

ATI_THERMAL_D- <35>

ATI_SMBCLK

ATI_SMBDATA

+3VS_DE LAY

2.2K_0402_5%~D

2@

12

RG87

2.2K_0402_5%~D

2@

12

RG88

ATI_SMBCLK <35>

ATI_SMBDATA <35>

CPN:SA010320120

+1.8VS

VRAM_ID0<35>

VRAM_ID1<35>

VRAM_ID2<35>

B B

Strap Name Pin Name

VRAM_ID3<35>

GDDR3 Size

Project

GPU Compal Part N umber

512M

12

RG1610K_0402_5%~D

12

RG3910K_0402_5%~D @

12

RG1510K_0402_5%~D @

12

RG1410K_0402_5%~D @

Vendor Part Number

Samsung - K4N1G164QE-HC20

SA000031O00(2nd)

VRAM_ID[3:0]

0 0 0 0

CONFIG[2:0] GPIO_[13:11]

BIOS_ROM_EN

AUD[1]
AUD[0]

GPIO_22_ROMCSB

HSYNC
VSYNC

BIF_GEN2_EN_A GPIO_2

RESERVED H2SYNC

RESERVED

GPIO_21_BB_EN

GENERICC

0 --> Tx de-emphasis disabled

1 --> Tx de-emphasis enable

GDDR3 me mory capacity :
128MB --> 000
256MB --> 001
64MB --> 010

BIOS_ROM_EN=0

Enabl e exter nal BIOS ROM devic e

0 --> Disabl e exter nal BIO S ROM device

1 --> Enable extern al BIOS ROM device

AUD[1:0] --> [HSYNC:VSYNC]
00 --> No Audio function
01 --> Audio for Display-Port and HDMI
if ada pter i s detected
10 --> Audio for Display-Port only
11 --> Audio for both Display-Port and HDMI

0 --> Adverti ses the PCIe device as 2.5GT/s
capa ble at powe r-on.

1 --> Adverti ses the PCIe device as 5.0GT/s
capa ble at powe r-on.

Internal use only.
This pad has an i nternal pull-down and
must be 0V at reset.

Internal use only.
This pad has an i nternal pull-down and
must be 0V at reset.

001

11

0

*

*

0

*

*

0

*

0

*

0

*

512M SA00002UH00(main)Hynix - H5PS1G63EFR-20L 0 0 0 1

VRAM_ID[3:0]

DVPDATA[23:20]

ATI
M92-S2-LP

KAM01

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

2

Date: Sheet of

Compal Electronics, Inc.

M92 S2-LP Filters / Strap

LA-5162P

1

39 60Monday , April 20, 2009

0.1

5

D D

4

3

2

2@

UG5E

1

AA27

PCIE_VSS#1

AB24

(1.8V@500mA +PCIE_GDDR)

+PCIE _GDDR

1U_0402_6.3V4Z

+1.8VS

1U_04 02_6.3V4Z

1U_04 02_6.3V4Z

1U_04 02_6.3V4Z

1U_04 02_6.3V4Z

C C

B B

A A

2@

2@

1

1

CG89

CG88

2

2

+1.8VS

1U_04 02_6.3V4Z

2@

2@

1

1

CG90

CG91

2

2

LG29

2@

BLM18PG121SN1D_0603

+1.8VS

BLM18PG121SN1D_0603

1

2

10U_0603_6.3V6M

12

2@

CG92

1

2

2@

1U_04 02_6.3V4Z

1

2

+1.8VS

1U_0402_6.3V4Z

2@

CG119

+1.8VS

10U_0603_6.3V6M

LG25

+3VS_DE LAY

(1.8 V@2200mA)

1U_04 02_6.3V4Z

1U_04 02_6.3V4Z

2@

2@

CG93

1

2

1

2

+VGA_CORE

1

1

CG94

2

2

LG20

2@

BLM18PG121SN1D_0603

1U_0402_6.3V4Z

1U_0402_6.3V4Z

2@

2@

1

CG121

CG120

2

LG22

2@

BLM18PG121SN1D_0603

+VDDR4

1U_04 02_6.3V4Z

0.1U_0402_10V6K

2@

2@

1

CG152

CG153

2

+1.8VS

12

10U_0603_6.3V6M

2@

1

CG138

2

2@

1 2

MCK1 608471YZF 0603

10U_0603_6.3V6M

10U_0603_6.3V6M

2@

CG95

10U_0603_6.3V6M

2@

2@

1

1

2

1

CG102

CG101

2

2

(1.8V@ 110mA +VDDC_CT)

12

2@

1

CG122

2

12

2@

1

CG154

2

BLM18PG121SN1D_0603

+PCIE_PV DD

1U_0402_6.3V4Z

1

2

LG26

+VDDC_CT

10U_0603_6.3V6M

1U_0402_6.3V4Z

2@

1

1

CG105

2

2

+VDDR5

1U_0402_6.3V4Z

10U_0603_6.3V6M

2@

1

1

CG123

2

2

LG23

2@

12

0.1U_0402_10V6K

2@

2@

1

CG140

CG139

2

10U_0603_6.3V6M

1U_0402_6.3V4Z

2@

1

1

CG146

2

2

1U_0402_6.3V4Z

2@

CG103

0.1U_0402_10V6K

2@

CG106

0.1U_0402_10V6K

2@

CG124

1U_0402_6.3V4Z

+SPV10

2@

CG147

1

2

10U_0603_6.3V6M

1

2

2@

1

CG108

2

2@

1

CG125

2

+VDDR HA

2@

1

CG136

2

0.1U_0402_10V6K

1

2

0.1U_0402_10V6K

2@

CG149

1

2

2@

UG5D

2@

CG104

2@

CG148

2@

CG150

MEM I /O

H13

VDDR1#1

H16

VDDR1#2

H19

VDDR1#3

J10

VDDR1#4

J23

VDDR1#5

J24

VDDR1#6

J9

VDDR1#7

K10

VDDR1#8

K23

VDDR1#9

K24

VDDR1#10

K9

VDDR1#11

L11

VDDR1#12

L12

VDDR1#13

L13

VDDR1#14

L20

VDDR1#15

L21

VDDR1#16

L22

VDDR1#17

LEVEL
TRANSLATION

AA20

VDD_CT#1

AA21

VDD_CT#2

AB20

VDD_CT#3

AB21

VDD_CT#4

I/O

AA17

VDDR3#1

AA18

VDDR3#2

AB17

VDDR3#3

AB18

VDDR3#4

U11

VDDR5#1

U12

VDDR5#2

V11

VDDR5#3

V12

VDDR5#4

AA11

VDDR4#1

AA12

VDDR4#2

Y11

VDDR4#3

Y12

VDDR4#4

MEM C LK

L17

VDDRHA

L16

VSSRHA

PLL

AM30

PCIE_PVDD

L8

NC_MPV18

H7

NC_SPV18

H8

SPV10

J7

SPVSS

BACK BIAS

M11

BBP#1

M12

BBP#2

216-072802 0 A12 M92-S2 LP_FCBGA631

POWER

PCIE

PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8

PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8

PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12

CORE

ISOLA TED
CORE I/O

VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8

VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23

VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8

AB23
AC23
AD24
AE24
AE25
AE26
AF25
AG26

L23
L24
L25
L26
M22
N22
N23
N24
R22
T22
U22
V22

AA15
N15
N17
R13
R16
R18
R21
T12
T15
T17
T20
U13
U16
U18
U21
V15
V17
V20
V21
Y13
Y16
Y18
Y21

M13
M15
M16
M17
M18
M20
M21
N20

0.1U_0402_10V6K

0.1U_0402_10V6K

1U_0402_6.3V4Z

1

2

10U_0603_6.3V6M

1

2

(+VGA_CORE@2000mA +VDDCI)

+VDDC I

1U_0402_6.3V4Z

1

2

10U_0603_6.3V6M

MCK2 012221YZF 0805

2@

2@

1

CG167

2

2@

1

1

CG86

CG87

2

2

(1.1V@ 2000mA +PCIE_VDDC)

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

2@

1

CG85

2

1U_0402_6.3V4Z

2@

CG109

10U_0603_6.3V6M

2@

CG126

1U_0402_6.3V4Z

2@

CG141

2@

2@

1

1

CG97

CG96

2

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

2@

2@

1

CG110

2

2@

1

CG127

2

2@

1

CG142

2

1

1

CG111

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

2@

1

1

CG128

2

2

1U_0402_6.3V4Z

10U_0603_6.3V6M

2@

1

1

CG143

2

2

3VS_D ELAY_ON<30>

+1.8VS

LG18

2@

1 2

+1.1VS_GFX_PCIE

10U_0603_6.3V6M

1U_0402_6.3V4Z

2@

2@

1

1

CG98

CG99

2

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

2@

2@

1

CG112

CG113

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

2@

2@

1

CG129

CG130

2

LG24

2@

1 2

MCK2 012221YZF 0805

2@

CG144

2@

1 2

0_0402_5%

2@

1

CG100

2

(+VGA_CORE@9000mA +VDDC)

1U_0402_6.3V4Z

1U_0402_6.3V4Z

2@

2@

1

2

1

2

RG49

CG114

2@

CG131

1

1

CG115

2

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

2@

1

1

CG132

2

2

2

0.1U_0402_10V6K

G

2@

1

CG151

2

1U_0402_6.3V4Z

2@

1

CG116

2

1U_0402_6.3V4Z

2@

1

CG133

2

+3VS_DE LAY

13

D

2@

2N7002_SOT23-3

S

1U_0402_6.3V4Z

2@

CG117

1U_0402_6.3V4Z

2@

CG134

QG2

+VGA_CORE

220U_Y_4VM

2@

1

1

+

CG118

2

2

2@

1

CG135

2

1 3

D

RG685

2@

1 2

1K_0402_5%~D

@

CG171

QG1 SI2301BDS-T1-E3_SOT23-32@

S

G

2

RG47

2@

100K_0402_5%

1 2

PCIE_VSS#2

AB32

PCIE_VSS#3

AC24

PCIE_VSS#4

AC26

PCIE_VSS#5

AC27

PCIE_VSS#6

AD25

PCIE_VSS#7

AD32

PCIE_VSS#8

AE27

PCIE_VSS#9

AF32

PCIE_VSS#10

AG27

PCIE_VSS#11

AH32

PCIE_VSS#12

K28

PCIE_VSS#13

K32

PCIE_VSS#14

L27

PCIE_VSS#15

M32

PCIE_VSS#16

N25

PCIE_VSS#17

N27

PCIE_VSS#18

P25

PCIE_VSS#19

P32

PCIE_VSS#20

R27

PCIE_VSS#21

T25

PCIE_VSS#22

T32

PCIE_VSS#23

U25

PCIE_VSS#24

U27

PCIE_VSS#25

V32

PCIE_VSS#26

W25

PCIE_VSS#27

W26

PCIE_VSS#28

W27

PCIE_VSS#29

Y25

PCIE_VSS#30

Y32

PCIE_VSS#31

M6

GND#56

N11

GND#57

N12

GND#58

N13

GND#59

N16

GND#60

N18

GND#61

N21

GND#62

P6

GND#63

P9

GND#64

R12

GND#65

R15

GND#66

R17

GND#67

R20

GND#68

T13

GND#69

T16

GND#70

T18

GND#71

T21

GND#72

T6

GND#73

U15

GND#74

U17

GND#75

U20

GND#76

U3

GND#77

U9

GND#78

V13

GND#79

V16

GND#80

V18

GND#81

V6

GND#82

Y10

GND#83

Y15

GND#84

Y17

GND#85

Y20

GND#86

Y6

GND#87

216-07 28020 A12 M92-S2 LP_FCBGA631

+3VS

1

2@

0.1U_0402_10V6K

2

GND

CG8

VSS_MECH#1
VSS_MECH#2
VSS_MECH#3

GND#1
GND#2
GND#3
GND#4
GND#5
GND#6
GND#7
GND#8

GND#9
GND#10
GND#11
GND#12
GND#13
GND#14
GND#15
GND#16
GND#17
GND#18
GND#19
GND#20
GND#21
GND#22
GND#23
GND#24
GND#25
GND#26
GND#27
GND#28
GND#29
GND#30
GND#31
GND#32
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55

A3
A30
AA13
AA16
AB10
AB15
AB6
AC9
AD6
AD8
AE7
AG12
AH10
AH28
B10
B12
B14
B16
B18
B20
B22
B24
B26
B6
B8
C1
C32
E28
F10
F12
F14
F16
F18
F2
F20
F22
F24
F26
F6
F8
G10
G27
G31
G8
H14
H17
H2
H20
H6
J27
J31
K11
K2
K22
K6

A32
AM1
AM32

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/05 2009/01/05

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

2

Date: Sheet of

Compal Electronics, Inc.

M92 S2-LP POWER/GND

LA-5162P

1

40 60Monday , April 20, 2009

0.1

5

4

3

2

1

ADPI N

PL1

12

SMB3025500YA_2P

PC5

1000P_0402_50V7K~D

1 2

12

PC6

100P_0402_50V8J~D

ME@

PJD CIN

1

1

2

2

3

3

4

4

5

5

6

6

7

D D

7

SUYIN_0 40017FR0 03Y100ZL_5P

BLM18BD102SN1D_0603~D

12

12

PC3

PC2

100P_0402_50V8J~D

12

PC4

1000P_0402_50V7K~D

100P_0402_50V8J~D

PL2

DOCK_ PSIDPSID

12

VIN

12

PC7

1000P_0402_50V7K~D

VIN

PD2

RLS4148_LL34-2

PD3

RLS4148_LL34-2

12

PQ1

TP0610K-T1-E3_SOT23-3

BATT+

C C

CHGRTC P

12

PR12

100K_0402_5%~D

PR13

22K_0402_5%~D

51ON#<31>

1 2

1 2

200_0805_5%

RTCVREF

12

B B

PC14

4.7U_08 05_6.3V6K~D

12

PC11

PR14

PU3
APL5156-33DI-TRL_SOT89-3

3

VOUT

GND

0.22U_1206_25V7K

2

12

VIN

12

APL5156_IN

2

1

1 2

12

PR10

68_1206_5%

13

12

PR15
200_0805_5%

PC13
1U_0805_25V4Z~D

12

PR11

68_1206_5%

PC12

0.1U_0603_25V7K~D

VS

+3VALW+5VALW

2

DOCK_ PSID

@

SM24_SOT23

PD5

PR16

@

1 2

0_0402_5%~D

D

1 3

33_0402_5%~D

S

PQ2
RHU002N06_S OT323-3

G

2

1 2

PR19

2

3

1

1 2

100K_0402_1%~D

C

PQ3

2

B

MMST3904-7-F_SOT323~D

E

3 1

PR21

1 2

15K_0402_1%~D

PR18

3

PD4

DA204U_SOT323~D

1

PR17

1 2

2.2K_0402_5%~D

PS_ID <30>

PR22

@

1 2

10K_0402_1%~D

+5VALW

2

3

PD6

@

DA204U_SOT323~D

1

PSID_ DISABLE# <30>

+5VALW

12

PR20

10K_0402_1%~D

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/10/1 2008/6/05

Compal Secret Data

Deciphered Date

Title

DCIN / Precharge

Size Doc ument Number Re v

2

Date: Sheet of

LA -516 1P

1

41 60Monday , April 20, 2009

0.1Cus tom

A

VIN

12

PR24

1 1

3.3_1210_5%~D

12

PR26

3.3_1210_5%~D

PC20

2.2U_0805_25V6K

1 2

90W adapter

Icharg e=(Vsrset/Vvdac)*(0.1/PR30)=3.3A

PC16

1 2

0.01U_0603_50V7K~D

PR35

Iadapt er=(Vacset/Vvdac)*(0.1/PR23)=4 .16A

Input OVP : 22.3V

2 2

Input UVP : 17.26V

Fsw : 300KH z

65W adapter(CP_SEL high)

Iadapt er=(Vacset/Vvdac)*(0.1/PR23)=3 A

VREF

PR38
47K_0402_1%~D

1 2

13

D

S

3 3

PR47

1 2

B+

100_0805_5%~D

+5VALW

PR53

PD8

1 2

220K_0402_5%

4 4

12

PC47

PR55

0.1U_0603_25V7K~D

GND

CELLS

VREF

CELLS

2

G

PQ10
SSM3K7002F_SC59-3

Cells selector

PR50

1 2

12

1SS355_SOD323-2

1 2

220K_0402_5%

3 Cell

4 Cell

3cell/4c ell# <50>

PQ12
TP0610K-T1-E3_SOT23-3

2

470K_0402_5%~D

13

D

PQ15

2

G

RHU002N06_S OT323-3

S

A

13

1 2

PQ4

FDS4435B Z_SO8

8

D

7

D

6

D

5

D

PR29

1 2

340K_0402_1%~D

ACDET

PR31

54.9K_0402_1%

1 2

CP_SEL <30>

@

0.1U_0402_10V7K~D

1 2

340K_0402_1%~D

OVPSET

PR36

54.9K_0402_1%

1 2

PR37

100K_0402_1%~D

1 2

0.1U_0603_25V7K~D

210K_0402_1%~D

CHGVA DJ<30>

+B+_BIAS

PC45

0.1U_0805_25V7M~N

ACOF F

0.1U_0402_16V7K~D

1

S

2

S

3

S

4

G

97.6K_0402_1%

CP_SEL

12

PC191

SI2301BDS-T1-E3_SOT23-3

GATE

PC41

ACGOOD#

REGN

PR45

1 2

100K_0402_1%~D

1 2

PC46

PC26

PR116

2

G

12

PR51

1 2

2

B

PVCC _CHG

FDS4435B Z_SO8

1
2
3
4

12

PR27

100K_0402_1%~D

0.01U_0402_25V7K~D

ACDR V_CHG#

+3VALW

1 2
1 2
13

D

0.01U_0402_25V7K~D

S

PQ38
SSM3K7002F_SC59-3

CP setting

PQ9

1 3

ACSET

12

@

PR43

0_0402_5%~D

VADJ

12

PR46
499K_0402_1%~D

VREF

VREF

12

2

G

12

PR54

340K_0402_1%~D

B

PQ5

8

S

D

7

S

D

6

S

D

5

G

D

12

PC18

PR32

60.4K_0402_1%

PC30

@

1U_0603_10V6K~D

+3VALW

12

PR48
200K_0402_1%~D

13

D

PQ14
SSM3K7002F_SC59-3

S

0.015_2512_1%

1

2

PC17

0.1U_0402_16V7K~D

1 2

0.1U_0603_25V7K~D

12

12

PC40

PR171

1 2

0_0402_5%~D

13

D

2

G

S

PR23

4

3

12

PC19

0.1U_0603_25V7K~D

ACN
ACP

ACSET

PR34
100K_0402_1%~D

1 2

PC35

0.47U_0603_16V7K~D

VREF

12

12

@

PR170

0_0402_5%~D

VADJ

/BATDRV

GATE

PQ13
SSM3K7002F_SC59-3

C

B+

PJP14

2

112

JUMP_43X118

PC21

PU4

CHGEN#

1

CHGEN

2

ACN

3

ACP

4

ACDRV

5

ACDET

6

ACSET

7

ACOP

8

OVPSET

9

AGND

10

VREF

11

VDAC

12

VADJ

13

ACGOOD

14

BATDRV

BQ24751ARH DR_QFN28_5X5

BAT54CW_SOT323~D

PVCC

BTST

HIDRV

PH

REGN

LODRV

PGND

LEARN

CELLS

SRP

SRN

BAT

TP

SRSET

IADAPT

ADP_I<30>

RTCVR EF

2

PD9

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

0.1U_0805_25V

28

1 2

PR28

1 2

27

2.2_0603_5%~D

DH_ CHG

26

LX_CHG

25

PD7

RLS4148_LL34-2

REGN

24

12

PC31
1U_0603_10V6K~D

DL_CH G

23

22

21

CELLS

20

SRP

19

SRN

18

17

12

PC42

0.1U_0603_25V7K~D

29

SRSET

16

15

1 2

PR44

10_0603_5%~D

PC44

100P_0402_50V8J~D

+COINC ELL

12

PR49
1K_0402_5%~D

Z4012

3

+RTCVCC

1

1

PC48
1U_0603_10V4Z~D

2

2006/10/1 2008/6/05

FDS8884_SO8

12

1 2

PC28

0.1U_0603_25V7K~D

FDS6690AS_N L_SO8

ACOF F <30>

ICHG setting

12

PR40

100K_0402_1%~D

12

+COINC ELL

Compal Secret Data

CHG_B+

578

PQ6

3 6

241

578

PQ8

3 6

241

49.9K_0402_1%~D

12

@

PC43

0.01U_0402_25V7K~D

IREF Current

3.3V 3.3A

COIN RTC Battery

1

+

SUYIN_0 60003FA002G201NL~D

Deciphered Date

D

PC274.7 U_1206_25V6K~D

1 2

12

PL3

10UH_ SIL1045RA-100PF_4.5A_30%

1 2

12

PR33

@

4.7_1206_5%~D

@

12

PC36

@

680P_0603_50V7K~D

PR39

12

IREF <30>

ME@

PJRTC

D

PC221000P_0402_50V7K~D

PC32

-

E

12

PC241000P_0402_50V7K~D

PC234.7 U_1206_25V6K~D

1 2

12

1 2

1 2

10U_1206_25V6M~D

12

PC38

0.1U_0603_25V7K~D

2

PC15

PC254.7 U_1206_25V6K~D

1 2

/BATDRV

PR30

0.02_2512_1%

1

2

PC33

10U_1206_25V6M~D

PC37

0.1U_0402_16V7K~D

1 2

PR41

47K_0402_1%~D

ACGOOD#

FSTCHG<30>

Title

Size Doc ument Number Re v

B

Date: Sheet of

PR25
100K_0402_1%~D

1 2

0.01U_0402_25V7K~D

3G4

5

4

3

12

PC39

0.1U_0603_25V7K~D

RTCVREF

VREF

12

2

G

2

G

PR42
47K_0402_1%~D

1 2

13

D

PQ11
SSM3K7002F_SC59-3

S

VREF

PR52
47K_0402_1%~D

1 2

CHGEN#

13

D

PQ16
SSM3K7002F_SC59-3

S

Compal Electronics, Inc.

Charger

Charger

ChargerCharger

LLLL A-5 161 P

A-51 6 1P

A-51 6 1PA-51 61P

PQ7

S1S2S

FDS4435B Z_SO8

D8D7D6D

12

PC34

10U_1206_25V6M~D

ACIN <30,35>

E

BATT+

12

PC29

10U_1206_25V6M~D

0.1

42 60Monday , April 20, 2009

5

4

3

2

1

B+

PJP15
JUMP_43 X118

2

PC5 9

112

12

12

12

PC 49

PC 50

PC 51

4.7 U_1206_ 25V6K~D

4.7_ 1206_5%~D

PD1 0

220 0P_0402_50V7 K~D

PR5 8

PC6 3

MAIN PWON<50>

2

4.7 U_1206_ 25V6K~D

PL5

1 2

3.3U H_PCM B064T-3R3M S 7A_20%

1

+

2

2

2

2

1 2

@

1 2

+5VALW

+3VALW

PR 61

0_0 402_5%~D

PR 63

10K _0402_1%~D

VS

680P_06 03_50V7K~D

RLZ 5.1B_LL34

1 2

D D

+3VALWP

C C

B B

+5VALW P

+3VALW P

330 U_D3L_6.3 VM_R25M

PJP4
JUMP_43 X118

112

PJP7
JUMP_43 X118

112

PJP8
JUMP_43 X118

112

3.3VALWP
Thermal Design Current=5A
Peak Current=7.14A

OCP min=9.28A
Fsw=300K

A A

Rds(on) = 14.2m ohm(max) ;
Rds(on) = 11.7m ohm(typical)

5

1 3

PD11

1 2

1SS 355_SOD323-2

TPS51427_B+

241

12

12

786

123

PR6 7

100K_04 02_1%~D

1 2

PQ21

TP0610K-T1-E3 _SOT23-3

4

578

3 6

5

PR 68

200 K_0402_5%~D

0_0402_ 5%~D

PQ17

AO4466_ SO8

PQ19
AO4710_ SO8

4

1 2

1 2

PR7 5

PR5 6

0_0805_ 5%

1 2

VL

PC5 2

0.1U _0603_25 V7K~D

PR5 7

BST3A

12

0_0603_ 5%~D

PC6 0

0.1U _0603_25 V7K~D

1 2

LX3

DL3

FB3

VL

2VREF_TPS51427

1 2

PC6 5 0 .22U_ 0603_10V7K~ D

47K_040 2_5%~D@

1 2

12

PC 68

EN_ LDO

TPS5142 7_EN1

@

PR7 1

0_0402_ 5%~D

PR7 6

@

0.0 47U_0603_ 16V7K~D

TPS5142 7_EN2

1 2

12

PC6 9

0.0 47U_040 2_16V7K~N

PC6 6

0.22 U_0603_25 V7-K

VL

PR 73

1 2

806K_ 0603_1%

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

1 2

PC 56

3

6

PU5

33

VIN

TP

26

DRVH2

24

VBST2

25

LL2

23

DRVL2

30

VOUT2

32

REFIN2

1

VREF2

8

LDOREFIN

20

NC

4

EN_LDO

14

EN1

27

EN2

PR7 2

1 2

0_0 402_5%~D

1U_ 0603_10V6K ~D

2VR EF_TPS5142 7

V5FILT

TONSE

VREF3

2

5

12

12

PR7 4

@

0_0402_ 5%~D

PC6 7

2VR EF_TPS5142 7

2006/10/1 2008/6/05

3

12

PC 57

1U_ 0603_10V6K ~D

7

SKIPSEL

PGOOD2

PGOOD1

21

4.7 U_0805 _6.3V6K~D

19

LDO

V5DRV

15

DRVH1

17

VBST1

16

LL1

18

DRVL1

22

PGND

10

VOUT1

11

FB1

9

VSW

29

28

13

12

TRIP1

31

TRIP2

GND

TPS5142 7_QFN32_5X5

Compal Secret Data

Deciphered Date

PC5 8

1U_ 0603_10V6K~ D

1 2

D H5D H3

PR60

BST5A

0.1U _0603_25 V7K~D

LX5

DL5

FB5

ILM1

ILIM 2

0_0603_ 5%~D

PC6 1

PR66

1 2

0_0402_ 5%~D

12

PR6 5

@

0_0402_ 5%~D

5VALWP
Thermai Design Current=5A
Peak Current=7.14A
OCP min=9.28A
Fsw=400K

Rds(on) = 14.2m ohm(max) ; Rds(on) = 11.7m ohm(typical)

AO4466_ SO8

AO4710_ SO8

1 2

12

PR6 9

294K_04 02_1%~D

12

PR7 0

12

287K_04 02_1%~D

2

PQ18

PQ20

4

578

3 6

241

786

5

123

VL

POK <23>

Da te: S heet of

TPS51427_B+

12

12

12

PC5 5

PC 54

PC 53

4.7 U_1206_ 25V6K~D

220 0P_0402_50V7 K~D

4.7 U_1206_ 25V6K~D

+5VALWP

PL4

3.3U H_PCM B064T-3R3M S 7A_20%

12

PR5 9

4.7_ 1206_5%~D

12

PC6 2

680P_06 03_50V7K~D

Compal Electronics, Inc.

Title

++++3VALWP, +5VALWP

3VALWP, +5VALWP

3VALWP, +5VALWP3VALWP, +5VALWP

Size Doc umen t Numb er R e v

Monday, April 20, 2009

12

LA-5161P

1

1

+

PC6 4
330 U_D3L_6.3 VM_R25M

2

43 60

PR 62

1 2

61. 9K_0402_1% ~D

PR 64

1 2

10K _0402_1%~D

0.1Cu stom

A

1 1

B

C

D

VCCP _B++

PJP16

12

B+

PAD -OPEN 4x4m

12

PC70

2 2

PR78

0_040 2_5%~D

SUSP #< 27,30,32, 46>

12

PR80

30.1K _0402_1%~D

12

@

0.1U_ 0402_16V7K ~D

PC73

12

TON_V CCP

PR81

+5VS

3 3

12

PC77

1U_06 03_10V6K~D

PC80

@

47P_0 402_50V8J~D

300_0 603_5%~D

1 2

V5F ILT_VCCP

FB_ VCCP

12

EN_ VCCP

2

3

4

5

6

PU6

TON

VOUT

V5FILT

VFB

PGOOD

PR77

267K_ 0402_1%~D

1 2

1

14TP15

EN_PSV

GND7PGND

TPS 51117RGY R_QFN14 _3.5x3.5

8

BST_V CCP

VBST

DRVH

LL

TRIP

V5DRV

DRVL

PR79

1 2

0_060 3_5%~D

UG_ VCCP

13

LX_VCCP

12

TR IP_VCCP

11

V5D RV_VCC P

10

LG_ VCCP

9

PC72

1 2

0.1U_ 0603_25V7K ~D

PR83

1 2

13.7K _0402_1%~D

+5VS

12

PR82
0_060 3_5%~D

12

PC79

4.7U_ 0805_10V 6K~D

578

PQ22
FDS62 98 1N_S O8

3 6

241

786

5

PQ23

AO4710_ SO8

4

4

123

12

PC71

10U_1 206_25V6M~D

5

786

123

10U_1 206_25V6M~D

PQ24

AO4710_ SO8

PL6

0.47U H_FDVE0 630-H-R 47M=P3 17.7A_20%

1 2

PR84

@

4.7_1 206_5%~D

1 2

@

PC78

680P_ 0603_50V8J~D

1 2

+VCC PP

1

1

+

2

PC74

220U_ D2_2.5VM~D

12

+

2

PC75

PC76

4.7U_0 805_6.3V 6K~D

220U_ D2_2.5VM~D

12

PR85

8.66K _0402_1%~D

12

PR86

21.5K _0402_1%~D

PJP5
JUMP_43X118

+VCC PP

VCCP
The rma l Desi g Current=14A
Pea k Cur rent=2 0A

4 4

OCP min=2 6A
Fsw =298KH z

<Vo =1.0 5V> V FB=0.75V
Vo= VFB *(1 +PR85 /PR86)= 0.75*( 1+8.66 K/21.5 K)=1.0 52V

112

PJP6
JUMP_43X118

112

2

+VCC P

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/2/5 2008/6/05

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size D ocum ent Nu mber R ev

Monday, April 20, 2009

Dat e: S heet o f

LA-5161P

+VCCP

44 60

D

0.1Cus tom

A

1 1

B

C

D

+1.8VP_B++

PJP17

12

B+

PAD -OPEN 4x4m

PC82

10U_1 206_25V6M~D

PL7

1 2

12

10U_1 206_25V6M~D

+1.8VP

PC85

1

+

PC86

PC154

PC155

12

12

12

2

220U_ D2_2.5VM~D

4.7U_0 805_6.3V 6K~D

4.7U_0 805_6.3V 6K~D

4.7U_0 805_6.3V 6K~D

12

PC81

2 2

PR88

0_040 2_5%~D

SYS ON<27, 30,32>

30.1K _0402_1%~D

PR91

+5VALW

3 3

1 2

300_0 603_5%~D

12

PR90

12

PC87

1U_06 03_10V6K~D

12

@

0.1U_ 0402_16V7K ~D

47P_0 402_50V8J~D

PC84

@

PC90

12

TON_1 .8

2

3

V5FILT _1.8

FB_ 1.8

4

5

6

12

EN_ 1.8

PU7

TON

VOUT

V5FILT

VFB

PGOOD

PR87

267K_ 0402_1%~D

1 2

BST_1.8

1

14TP15

EN_PSV

GND7PGND

TPS 51117RGY R_QFN14 _3.5x3.5

8

VBST

DRVH

TRIP

V5DRV

DRVL

LL

PR89

1 2

0_060 3_5%~D

UG_ 1.8

13

LX_1.8

12

TRIP_ 1.8

11

V5D RV_1.8

10

LG_1. 8

9

PC83

1 2

0.1U_ 0603_25V7K ~D

PR94

1 2

7.5K_ 0402_1%~D

+5VALW

12

PR92
0_060 3_5%~D

12

PC89

4.7U_ 0805_10V 6K~D

SI4634 DY-T1-E 3_SO8

PQ26

578

PQ25

FDS62 98 1N_S O8

3 6

241

786

5

4

0.75U H_FDVE0 630-H-R 75M=P3_13.4A _20%

PR93

@

4.7_1 206_5%~D

1 2

PC88

@

680P_ 0603_50V8J~D

1 2

123

12

PR95

30.1K _0402_1%~D

12

PR96

21.5K _0402_1%~D

PJP10
JUMP_43X118

+1.8VP

1.8V
The rma l Desi gn Current=9A
Pea k Cur rnet=1 2.9A
OCP min=1 6.77A

4 4

Fsw =297KH z

<Vo =1.8 V> VF B=0.75V
Vo= VFB *(1 +PR95 /PR96)= 0.75*( 1+30.1 K/21.5 K)=1.8 V
Fsw =297KH z

112

PJP12
JUMP_43X118

112

2

+1.8V

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/2/5 2008/6/05

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

+1.8VP

Size D ocum ent Nu mber R ev

Dat e: S heet o f

LA-5161P

Monday, April 20, 2009

D

45 60

0.1C usto m

A

1 1

B

C

D

+1.5VSP_B+ +

PJP18

12

B+

PAD -OPEN 4x4m

PC92

10U_1 206_25V6M~D

PL8

1 2

12

10U_1 206_25V6M~D

PC95

PC96

1

+

+1.5VSP

12

2

4.7U_0 805_6.3V 6K~D

220U_ D2_4VM~D

12

PC91

PR97

267K_ 0402_1%~D

1 2

PR98

0_040 2_5%~D

SUSP #< 27,30,32, 44>

2 2

12

PR100

30.1K _0402_1%~D

12

@

0.1U_ 0402_16V7K ~D

PC94

12

TON_1 .5

PR101

+5VS

300_0 603_5%~D

1 2

12

PC97

1U_06 03_10V6K~D

PC100

@

47P_0 402_50V8J~D

V5FILT _1.5

FB_ 1.5

12

2

3

4

5

6

EN_ 1.5

PU8

TON

VOUT

V5FILT

VFB

PGOOD

1

EN_PSV

GND7PGND

8

PR99

BST_1.5

1 2

0_060 3_5%~D

14TP15

DRVH

TRIP

DRVL

UG_ 1.5

13

LX_1.5

12

LL

TRIP_ 1.5

11

V5D RV_1.5

10

LG_1. 5

9

VBST

V5DRV

TPS 51117RGY R_QFN14 _3.5x3.5

PC93

1 2

0.1U_ 0603_25V7K ~D

PR104

1 2

12.7K _0402_1%~D

+5VS

12

PR102
0_060 3_5%~D

12

PC99

4.7U_ 0805_10V 6K~D

AO4710_ SO8

PQ28

578

PQ27
AO4466_ SO8

3 6

241

786

5

4.7UH _PCMC0 63T-4R7M N_5.5A_20%

PR103

@

4.7_1 206_5%~D

1 2

4

PC98

@

680P_ 0603_50V8J~D

1 2

123

12

PR105

22.1K _0402_1%~D

12

3 3

PR106

22.1K _0402_1%~D

PJP13
JUMP_43X118

2

+1.5VSP

1.5V
The rma l Desi gn Current=3. 9A
Pea k Cur rent=5 .57A
OCP min=7 .24A
Fsw =298KH z

<Vo =1.5 V> VF B=0.75V
Vo= VFB *(1 +PR10 5/PR106 )=0.75 *(1+22 .1K/22 .1K)=1 .5V

4 4

112

A

+1.5VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/2/5 2008/6/05

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size D ocum ent Nu mber R ev

Monday, April 20, 2009

Dat e: S heet o f

LA-5161P

1.5VSP

46 60

D

0.1Cus tom

5

4

3

2

1

D D

B+

C C

VGA _ON<30>

B B

PJP19

2@

1 2

PA D-OPE N 4x4m

PR1 14
0_0402_ 5%~D

2@

1 2

12

PC1 01

2@

12

PC1 04

2@

0.1U _0603_25 V7K~D

12

PC1 02

2@

10U _1206_25V6M~ D

0_0603_ 5%~D

12

PC106

2.2U _0603 _6.3V6K~D

2@

PC1 10

0.1U _0402_16 V7K~D

2@

12

PR1 10

2@

VGA_B++

6268_VG A

12

PR1 07

10K_040 2_1%~D

10U _1206_25V6M~ D

VGA _PWGOD<32>

12

VIN _VGA

6268_VG A

EN_ VGA

COMP_VG A

12

PC1 12

2@

22P _0402_50V_N PO

2@

2@

2

8

PU9

GND

3

VIN

4

VCC

ISL62 68CAZ-T_ SSOP16

5

EN

COMP6FB7FSET

12

PR1 17

2@

49. 9K_0402_1% ~D

12

PC1 14

220 0P_0402_50V7 K~D

PHA SE_VGA

PR108

2@

1 2

0_0603_ 5%~D

BOOT_VG A

PR1 09

2@

1UG16

PGOOD

2@

PR1 18

2@

15

BOOT

PHASE

9

FSE T_VGA

12

40. 2K_0402_1% ~D

14

PVCC

13

LG

12

PGND

11

ISEN

VO

10

12

PC113

0.01 U_0402_2 5V7K~D

2@

ISEN_ VGA

UG_ VGA

1 2

PC1 03

+5VS

0.1U _0603_25 V7K~D

12

PR111

4.7_ 0603_5%

0_0 603_5%~D

1 2

PC105

2@

PVC C_VGA

1 2

2.2U _0603 _6.3V6K~D

LG_VGA

1 2

PR1 12

5.1K _0402_1%~D

2@

2@

2@

6268_VG A

2@

FDMS867 0S_MLP8

FB_ VGA

PQ30

4

123 5

3 5

241

2@ for DSC

+VGA_COREP
Thermal Design C urrent=7.87A
Peak Current=11. 24A
OCP min=14.61A
Fsw=300KHz

0.90V 0.95V
GPU_VID_0 0 1

PQ29

2@

FDM S8692_PO WER56-8-5

2@

PL9

1UH _MPLC0 730L1R0_1 0.6A_20%

1 2

2@

PR1 13

4.7_ 1206_5%~D

1 2

2@

PC1 11
680P_06 03_50V7K~D

1 2

12

PR1 15
10_0402 _1%~D

2@

PR1 19
3K_0402 _1%

2@

1 2

2@

12

PC1 09

+VG A_COREP

4.7 U_0805 _6.3V6K~D

1

1

+

PC1 08

2@

+

PC1 07

2

2

2@

220U_X_ 2VM_R7M~D

220U_X_ 2VM_R7M~D

12

12

PR1 21

0_0402_ 5%~D

2@

+5VS

PR1 23
10K_040 2_5%~D

2@

1 2

GP U_VID0<35>

A A

PJP9
JUMP_43 X118

112

PJP11

+VG A_COREP

JUMP_43 X118

112

5

10K_040 2_5%~D

2

2

PR1 24

2@

+VG A_CORE

12

12

PR1 25

2@

1

2@

2

100 K_0402_5%~D

12

PR1 22

35.7 K_0402_1%

2@

13

D

PQ31

2

G

BSS 138W-7-F_S OT323~D

2@

S

PC1 16

0.0 1U_0402 _16V7K~D

4

820P_04 02_50V7K~D

12

2@

PC115

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/2/5 2008/06/05

3

Compal Secret Data

Deciphered Date

Title

Size Doc umen t Numb er R e v

2

Da te: S heet of

PR1 20

6.04 K_0402_1%

2@

Compal Electronics, Inc.

Monday, April 20, 2009

+VGA_COREP

LA-5161P

1

0.1

47 60

5

4

3

+5VS

2

1

PC1 17

@

12

5600P_0 402_25V7K

<30>

CP U_VID 4

CP U_VID 6

D D

+VCCP

DPR SLPVR<1 0,23>

H_D PRSTP#<8,10,2 2>

+3VS

12

PR1 39

68_0402 _1%~D

VGATE<23 ,30>

H_ PSI#<8>

C C

B B

A A

VR_TT#<7 >

1 2

4.22 K_0402_1%

@

0.01 5U_0402_1 6V7K

1000P_0 402_50V7K~D

VCC SENSE<8>

PC1 29

1U_ 0603_10V6K~ D

1 2

PR1 48

147K_04 02_1%~D

1 2

PR149

PC1 34

PH1

1 2

470 K_0603_5%_N CP18WM474

1 2

0.06 8U_0603_ 50V7K~D

1 2

PC1 37

1 2

PR1 53

1 2

11.3 K_0402_1%~ D

1 2

PC1 38

PR1 59

1 2

97.6 K_0402_1%~ D

1 2

PC1 43 100P _0402_50V8J ~D

PR1 61

1 2

100_040 2_1%~D

PR1 63 1K_040 2_1%~D

1 2

PR1 64 0_0603 _5%~D

VSS SENSE<8>

PR1 50

11.5 K_0402_1%~ D

1000P_0 402_50V7K~D

1 2

PR1 40

1 2

PR1 47

1 2

10K_040 2_1%~D

RB IAS_C PU

NT C_CPU

SOF T_CPU

PC1 35

OCS ET_CPU

1 2

270P_04 02_50V7K~D

12

PC1 40

2200P_0 402_50V7K~D

1 2

PC1 44

VCC _PRM

1.9 1K_0402_1%~ D

12

180 P_0402_50V8 J~D

PR1 27 499_04 02_1%~D

1 2

PR1 28 0_0402 _5%~D

1 2

PR1 33 0_0402 _5%~D

1 2

12

PC1 26

1U_ 0603_10V6K ~D

1

PGOOD

2

PMON _CPU

VW _CPU

COMP _CPU

FB _CPU

PSI#

3

PMON

4

RBIAS

5

VR_TT#

6

NTC

7

SOFT

8

OCSET

9

VW

10

COMP

11

FB

12

FB2

FB 2_CPU

12

PR1 60

1K_0402 _1%~D

PC1 46 330P_0 402_50V7K~D

1 2

PC1 47

330P_04 02_50V7K~D

PR166

1 2

0_0603_ 5%~D

1 2

PR1 68

1 2

1K_0402 _1%~D

PC1 51

0.22 U_0603_1 6V7K~D

T69

3V3 _CPU

DP RSLP VR_CPU

DPR STP#_C PU

45

46

47

48

49

3V3

GND

CLK_EN#

DPRSTP#

ISL62 66ACR Z-T_QFN48_7 X7

VDIFF13VSEN14RTN15DROOP16DFB17VO18VSUM19VIN20GND21VDD22ISEN223ISEN1

VD IFF_ CPU

DR OOP_ CPU

VS EN_CP U

RT N_CP U

12

PC1 48

0.0 1U_0402 _25V7K~D

PC149

PR1 69

1 2

3.57 K_0402_1%~ D

12

CP U_VID 5

VR _ON

12

12

12

12

0_0 402_5%~D

PR1 37 0_ 0402_5%~D

PR1 30 0_ 0402_5%~D

PR1 36 0_04 02_5%~D

PR1 29

VI D5

VI D4

VI D3

VI D6

VR _ON_ CPU

43

44

VR_ON

DPRSLPVR

DF B_C PU

VI N_CP U

12

PC145

0.1U _0603_25V 7K~D

VSUM

12

PR1 67

1 2

PC150 0. 068U_0 603_50V7K~D

12

PC1 52 0.2 2U_060 3_10V7K~D

<8>

<8>

CP U_VID 3

CP U_VID 2

CP U_VID 1

12

12

12

0_0 402_5%~D

PR1 31

PR1 34 0_04 02_5%~D

PR1 38 0_04 02_5%~D

VI D2

VI D1

BOOT1

UGATE1

PHASE1

PGND1

LGATE1

LGATE2

PGND2

PHASE2

UGATE2

BOOT2

VD D_C PU

1 2

PR1 58 1_0603 _5%~D

12

PC1 41
1U_ 0603_10V6K~ D

PR1 62

1 2

10_0603 _5%~D

12

PR1 65

2.61 K_0402_1%~ D

PH2

10K B_0603 _ERTJ1VR103J

11K _0402_1%~D

1 2

<8>

CP U_VID 0

12

VI D0

PVCC

24

<8>

<8>

<8>

<8>

12

12

PC1 19

0_0 402_5%~D

PR1 32

BOOT _CPU1

VID037VID138VID239VID340VID441VID542VID6

36

UGA TE_CPU1

35

PHA SE_CPU1

34

0.0 1U_0402 _25V7K~D

PR1 41

1 2

2.2_ 0603_5%~D

PC1 21

PC1 20

1U_ 0603_10V6K ~D

0.22 U_0603_1 0V7K~D

1 2

PC1 27

33

LGA TE_CPU1

32

PV CC_CP U

31

30

LGA TE_CPU2

29

BOOT _CPU2

2.2_ 0603_5%~D

+5VS

+CPU_B+

PHA SE_CPU2

UGA TE_CPU2

PR1 51

1 2

PC1 36

1 2

0.22 U_0603_1 0V7K~D

28

27

26

25

NC

PU1 0

29.1

ISE N1
ISE N2

PR1 26
1_0603_ 5%~D

1 2

12

12

12

PC1 22

1U_ 0603_10V6K ~D

0.0 1U_0402 _25V7K~D

3 5

241

5

5

D8D7D6D

S1S2S3G

4

4

PQ33

FDS 6676AS_S O8

3 5

241

5

5

D8D7D6D

S1S2S3G

4

4

PQ37

FDS 6676AS_S O8

12

PC1 23

10U _1206_25V6M~ D

PQ32
SI768 6DP-T1-E3_S O8

12

D8D7D6D

S1S2S3G

12

PQ34

FDS 6676AS_S O8

PQ35
SI768 6DP-T1-E3_S O8

12

D8D7D6D

S1S2S3G

12

PQ36

FDS 6676AS_S O8

PC1 24

@

10U _1206_25V6M~ D

PR1 42

@

4.7_ 1206_5%~D

PC128

@

680 P_0603_50V8 J~D

PR1 52

@

4.7_ 1206_5%~D

PC1 39

@

680 P_0603_50V8 J~D

+CPU_B+

1

12

+

PC1 25

10U _1206_25V6M~ D

PC1 31

10U _1206_25V6M ~D

PC1 18

2

100U_ 25V_M

12

PR1 43

12

12

PR1 44

3.6 5K_0805_1%
10K _0402_1%~D

VSUM

12

PC1 32

10U _1206_25V6M ~D

0.36 UH_ FD U1040 D-R36M _26A_20%

12

12

PR1 54

PR1 56

3.6 5K_0805_1%

VSUM

Ther mal Desi gn Curren t=34.01A
Peak Cur rnet=4 4A
OCP min= 57.2A
Fsw= 290KHz

1 2

+

PC1 53

100U_ 25V_M

1

2

PR146

PC1 30

12

PC1 33

@

10U_120 6_25V6M~D

1

2

PR157

PL10

12

PR1 45
1_0402_ 5%~D

VCC _PRM

+CPU_B+

12

PR1 55

1_0402_ 5%~D

VCC _PRM

FBMA-L18 -453215-900LMA 90T_1812

1

2

PL11

0.36 UH_ FD U1040 D-R36M _26A_20%

4

3

10K_040 2_1%~D

1 2

1 2

ISE N1

0.22 U_0603_1 6V7K~D

PL12

4

3

10K_040 2_1%~D

10K _0402_1%~D

1 2

PC1 42

1 2

0.22 U_0603_16 V7K~D

ISE N2

B+

+CPU _CORE

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/1/15 2008/6/05

3

Compal Secret Data

Deciphered Da te

Title

Size Doc umen t Numb er R e v

Cu stom

2

Da te: S heet of

Compal Electronics, Inc.

+CPU_CORE

LA-51 61P

1

0.1

48 60Mon day, Ap ril 20, 20 09

5

4

3

2

1

+1.5VS

1

PJP22

2@

1

JUMP_43X118

D D

1.1VS_GFX_ON<30>

C C

+1.1V_GFX_PCIEP

B B

A A

2

2

12

PC179

2@

10U_1206_6.3V6M~N

PR191

2@

1 2

4.7K_0402_1%~D

2@

2.2U_04 02_6.3V

PJP2
JUMP_43X118

112

+5VALW

+1.1V_VIN

PC176

2

12

PC177

2@

1U_0603_6.3V6M~N

+1.1V_EN

12

+1.1VS_GFX_PCIE

2@

PU14 APL5913-KAC-TRL_SO8

6

VCNTL

5

VIN

9

VIN

8

EN

7

POK

3

VOUT

4

VOUT

+1.1V_FB

2

FB

GND

1

2@

PR190

2@

3K_0402_1%

+1.1V_GFX_PCIEP

12

2@

12

PC180

PR192

1.15K_0402_1%

12

0.8V

0.01U_0402_25V7K~N

12

2@

PC178

22U_1206_6.3V6M~N

+1.8V

1

1

PJP23

+0.9VSP

SUSP<27,32>

PJP3
JUMP_43X118

112

JUMP_43X118

4.7U_08 05_6.3V6K~D

PR198

0_0402_5%~D

1 2

PC188

@

0.1U_0402_16V7K~D

2

+0.9VS

PC187

12

PQ39

2

2

12

2

G

2@for DSC

1.1V_GFX_PCIEP
Therma l Design Current=1.61A
Peak Currnet=2.3A
OCP min=2.76A

12

PR196

1K_0402_1%~D

13

D

S

12

PR197

RHU00 2N06_SOT323-3

PC190

12

1K_0402_1%~D

PU16

2

3

4

APL5331KAC-TRL_SO8~N

12

PC186

10U_0805_6.3V6M~D

0.1U_0402_16V7K~D

VIN1VCNTL

GND

VREF

VOUT

+0.9VSP

6

5

NC

7

NC

8

NC

9

TP

12

+3VALW

PC189

4.7U_08 05_6.3V6K~D

0.9VSP
Therma l Design Current=0.7A
Peak Currnet=1A
OCP min=1.3A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/1 2008/6/05

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

+0.9VSP/ +1.1V_G FX_ PCIEP

Size Doc ument Number Re v

2

Date: Sheet of

LA-5161P

Monday, April 20, 2009

1

49 60

0.1Cus tom

5

D D

PJPB1 battery connector

SM A

SM A R T

RT

SM ASM A

RTRT

Ba tt e ry :

Ba tt e ry :

Ba tt e ry :Ba t te ry :

9. B

9. B A T +

AT +

9. B9. B

AT +AT +

8. B

8. B A T +

AT +

8. B8. B

AT +AT +

7 .

7 . I D

ID

7 .7 .

IDI D

6666 .B/ I

.B / I

.B / I.B / I

5 .

5 . T S

TS

5 .5 .

C C

TST S

4 .

4 . S M D

SM D

4 .4 .

SM DS M D

3333 . S M C

.S M C

.S M C.S M C

2 .G

2 .G N D

ND

2 .G2 . G

NDND

1 .G

1 .G N D

ND

1 .G1 . G

NDND

PC167

@

PJBATT

10

GND

11

GND

SUYIN_2 00275MR009G186ZL_9P

BATT+

BATT+

12

12

PC168

100P_0402_50V8J~D

0.01U_0402_25V7K~D

1 2

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

PL13
SMB3025500YA_2P

4

2

3

1

EC_SMB_CK1<30>

PR179

1 2

BATT++

12

PC169

1000P_0402_50V7K~D

EC_SMB_DA1<30>

BATT_SMC

100_0402_5%~D

12

PC170

100P_0402_50V8J~D

@

DA204U_SOT323~D

PR178

BATT++

2

3

PD15

@

1

DA204U_SOT323~D

1K_0402_5%~D

1 2

1K_0402_5%~D

BATT_SMD

100_0402_5%~D

1 2

3

2

3

PD14

PR176

1 2

PD13

@

1

DA204U_SOT323~D

Pla ce cl os e to EC p in

BATT_TEMP

PR175

PR177 6.49K_0402_1%~D

1 2

BATT_TEMP <30>

PC171

@

1 2

0.1U_0402_16V7K~D

+3VALWP

2

3

1

+3VALWP

2

PD12

@

DA204U_SOT323~D

1

Battery Connect/OTP

+3VALWP

PR174
47K_0402_5%~D

1 2

BATT_B/I

3cell/4c ell# <42>

CPU

PH4 under CPU botten side :

CPU thermal protect ion at 90 +-3 degree C
Recovery at 50 +-3 degree C

VL VS

B B

VS

PC173

8

PR186

BATT_OVP<30>

A A

1 2

10K_0402_1%~D

BATT_OUT

7

PU13B

0

LM358ADR_SO8

5

P

+

6

-

G

4

BATT+

12

PR180

453K_0402_1%~D

12

12

PR182
499K_0402_1%~D

0.01U_0402_25V7K~D

BATT_IN

12

PR188

86.6K_0402_1%

PC174

1000P_0402_50V7K~D

12

CPU

12

PR181

10.7K_0402_1%~D

PR185

12

PH3

61.9K_0402_1%~D

1 2

1 2

VL

150K_0402_1%~D

150K_0402_1%~D

100K_0603_1%_TH11-4H104FT

PR187

PR189

OTP_IN OTP_IN+

PR183

147K_0402_1%~D

1 2

OTP_IN-

12

12

PC175

1U_0603_10V6K~D

3

2

8

P

+

-

G

PU13A

4

LM358ADR_SO8

PC172

0.1U_0603_25V7K~D

1 2

OTP_OUT

1

0

1SS355_SOD323-2

PD16

1 2

VL

PR184
205K_0402_1%~D

1 2

MAINPWON <43>

LI-4S :18V----BATT-OVP=1.5V

BATT-OVP=0.08338*BATT+

5

4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/1 2008/6/05

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

BATTERY CONN

Size Doc ument Number Re v

Date: Sheet of

LA-5161P

Monday, April 20, 2009

1

50 60

0.1Cus tom

5

Version Chang

Version Change List ( P. I. R. List )

Version ChangVersion Chang

It

It em

em Is

ItIt

D D

Page#01TTTTitle

emem

Page#Page#

e List ( P. I. R. List )

e List ( P. I. R. List )e List ( P. I. R. List )

Reque

Request

itle

itleitle

ate

ateate

RequeReque
OOOOwner

wner

wnerwner

Compal X012009-02-11 Change Board ID from 0.1(X00) to 0.2(X01)30 Board ID Change R232 to 100K, R84 to 9.09K.

st

stst

4

Is sue Description

sue DescriptionDDDDate

IsIs

sue Descriptionsue Description

3

2

So

So lution Description

lution Description RRRRev.

SoSo

lution Descriptionlution Description

1

ev.Page#

ev.ev.

02 20

03 22 ICH HDA Bus 2009-02-19 Compal HDMI no Audio issue

04 25 MIC Record 2009-02-24 Compal MIC can't Record ssue Add C39,C40 for Mic signal, follow IDT schematic connect. X01

05 31 EMI&ESD 2009-02-24 Compal EMI&ESD requirement. Add D52, Pop D24 X01

06 23 Audio 2009-02-27 IDT Vendor recommandation after review X00 schematic. Add R185,R186,Q2,Q4,Q17 X01

07 10,22 Audio 2009-03-03 Compal HDA Bus with HDCP only on UMA. Change R98,R103,R104,R105,R106 to 1@(UMA only). X01

C C

08 12,30 DPST 2009-03-04 Compal Power Saving DPST for Intel UMA Platform Add R295, R314 X01

09 19 LVDS 2009-03-05 Compal Panel power up sequence timing too fast. Change C206 value to 10uF, D22 to 0 ohm resistor. X01

10 6,14,35 GMCH 2009-03-05 Compal GM45 for DIS use.

11 19 CRT 2009-03-05 Compal R,G,B EA fail. Change L5,L6,L7 to BLM18BB050SN1D and D50 to RB491D. X01

12 20 HDMI 2009-03-05 Compal HDMI test requirement. Add Q16,C747,RG20. X01

13 27 Card Reader 2009-03-05 O2 OZ888GS0L3N sequence requirement. Add Q57,R170,C41. X01

14 30 Battery LED 2009-03-05 Compal Battery LED issue. Change BATT_CHG_LED# to pin 25 of U29. X01

B B

15 31

HDMI Level
Shifter

Keyboard
Connector

2009-02-19 Compal Add U10 2nd source ST HDMI Level Shifter and support component

2009-03-05 Compal Keyboard Connector issue. JKBD change type to JAE_FL4S030HB3R3000. X01

Add R165,R166,R161,R162,R163,R164, Change R560 to 4.3K ohm,
C1280 to 0 ohm when use ST HDMI Level Shifter.

ICH HDA_SDIN0(Pin AF4) for Codec
ICH HDA_SDIN2(Pin AH3) for GMCH.

R40,R41,R54,R60 always pop, RG44,RG119,RG163,RG103 de-pop
PJP21,PJP24 always short, RG30,YG1,CG53,CG52 always pop.

X01

X01

X01

16 35,36 GPU change 2009-03-05 ATI GPU schematic change after ATI review.

17 36,37,38 VRAM change 2009-03-05 Dell Change VRAM to DDR2(512MB). Add UG12,UG13,UG15,UG16, change RG71, RG63 change to 100 ohm. X01

18 12,30 DPST 2009-04-20 Compal GM45 driver not implement this function. Delete R314 and add R295 for UMA MB. X02

19

21 27

A A

21 27 Carder Reader 2009-04-20 O2 U46 need 1.8V source power from LDO(U2). Add U2, C42, C43, R229, R230, R231. X02

21,22
23,24

25 Codec change 2009-04-20 Compal We need support Aux mode function. Change U60 from SA00002QZ40(B5) to SA00002QZ50(A5).20

ICH9 change 2009-04-20 Compal ICH9ME-->Support IAMT, ICH9M-->Didn't support IAMT. Change ICH9ME to ICH9M, because we didn't support IAMT. X02

Carder Reader
chip change

2009-04-20 O2 O2 vendor change version because 1394 and SD card issue. Change U46 from SA000036M00(C) to SA000036M10(C1).

CG44,CG43,CG159CG48,CG49,CG161,RG37,CG266,CG71,CG72,CG68
CG69,CG70 de-pop, LG5,LG7 change to 0 ohm.

X01

X02

X02

DELL CONFIDENTIAL/PROPRIETARY

PROPR IETARY NOTE : THI S SHEE T OF ENGIN EERIN G DRAW ING A ND SP ECIFIC ATION S CON TAINS CONFIDENTIAL
TRADE SECRE T AND OTHE R PROP RIETA RY IN FORMA TION O F DEL L INC . ("DE LL") THIS DOCUME NT MAY NOT
BE TR ANSFER RED O R COP IED WI THOUT THE EXPRE SS WRI TTEN AUTHO RIZATI ON OF DELL . IN ADDITION,
NEITH ER THI S SHE ET NO R THE INFOR MATIO N IT CONTAI NS WA Y BE USED B Y OR DISCL OSED T O ANY THIRD
PARTY WITHO UT DE LL'S EXPRES S WRI TTEN CONSENT.

5

4

3

2

Title

Size Doc ument Number Re v

Date: Sheet of

Compal Electronics, Inc.

EE-Change History-1

LA-5162P

51 60Monday, A pril 20, 2009

1

1.0

5

Version Chang

Version Change List ( P. I. R. List )

Version ChangVersion Chang

It

It em

em Is

ItIt

D D

C C

Page#01TTTTitle

emem

Page#Page#

e List ( P. I. R. List )

e List ( P. I. R. List )e List ( P. I. R. List )

Reque

Request

itle

itleitle

ate

ateate

RequeReque
OOOOwner

wner

wnerwner

Compal X022009-04-20 Because SMBus address same as CPU sensor.39 GPU sensor Change UG1 from SA010320110(4C) to SA010320120(4D).

st

stst

4

Is sue Description

sue DescriptionDDDDate

IsIs

sue Descriptionsue Description

3

2

So

So lution Description

lution Description RRRRev.

SoSo

lution Descriptionlution Description

1

ev.Page#

ev.ev.

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPR IETARY NOTE : THI S SHEE T OF ENGIN EERIN G DRAW ING A ND SP ECIFIC ATION S CON TAINS CONFIDENTIAL
TRADE SECRE T AND OTHE R PROP RIETA RY IN FORMA TION O F DEL L INC . ("DE LL") THIS DOCUME NT MAY NOT
BE TR ANSFER RED O R COP IED WI THOUT THE EXPRE SS WRI TTEN AUTHO RIZATI ON OF DELL . IN ADDITION,
NEITH ER THI S SHE ET NO R THE INFOR MATIO N IT CONTAI NS WA Y BE USED B Y OR DISCL OSED T O ANY THIRD
PARTY WITHO UT DE LL'S EXPRES S WRI TTEN CONSENT.

5

4

3

2

Title

Size Doc ument Number Re v

Date: Sheet of

Compal Electronics, Inc.

EE-Change History-2

LA-5162P

52 60Monday, A pril 20, 2009

1

1.0

5

Version Chang

Version Change List ( P. I. R. List )

Version ChangVersion Chang

It

It em

em DDDDate

ItIt

D D

Page# TTTTitle

emem

Page#Page#

e List ( P. I. R. List )

e List ( P. I. R. List )e List ( P. I. R. List )

Reque

Request

itle

itleitle

ate So

ateate

2/101 41 Add net ACGOOD# and connect from PC41_pin2 to PQ11_pin2 X01Charger Compal

RequeReque
OOOOwner

wner

wnerwner

4

st

stst

Is

Is sue Description

sue Description

IsIs

sue Descriptionsue Description

can’t not boot

3

So lution Description

lution Description RRRRev.

SoSo

lution Descriptionlution Description

2

1

ev.Page#

ev.ev.

VCCPP HW update PWR BudgetCompal2 43 2/28

+1.8VP HW update PWR BudgetCompal2/28443 X01

C C

4 +VGA_CORE46 3/06 Compal HW to meet the properly power sequence

5 48 +1.1V_GFX

486

7 40 DCIN ME DCIN connector change

B B

_PCIEP

+1.1V_GFX
_PCIEP

VCCPP modify ocp settingCompal03/138 43 X02

3/06 Compal HW to meet the properly power sequence

HW to meet the properly power sequence Compal3/06

3/09 Compal

1.Change TDC from 5.85A to 14A
Peak Current from 8.35A to 20A
OCP min from 10.86A to 26A

2. Change PL6 from SH000003Y80(S COIL 1UH +-20% MPLC0730L1R0 10.6A)
to SH00000GQ00 (S COIL 0.47UH +-20% FDVE0630-H-R47M=P3 17.7A)

1. Change TDC from 5.85A to 9A
Peak Current from 8.35A to 12.9A
OCP min from 10.86A to 16.77A

2. Change PL7 from SH000003Y80(S COIL 1UH +-20% MPLC0730L1R0 10.6A)
to SH00000F40L (S COIL .75U 20% FDVE0630-H-R75M=P3 13.4A)

change PR114 from SD03422028L(S RES 1/16W 22K +-1% 0402) to
SD02800008L(S RES 1/16W 0 +-5% 0402)

change PR191 from SD02800008L(S RES 1/16W 0 +-5% 0402) to
SD03447018L(S RES 1/16W 4.7K +-1% 0402 )

change PC176 from SE076104K8L(S CER CAP .1U 16V K X7R 0402) to
SE00000888L(S CER CAP 2.2U 6.3V M X5R 0402 )

Modify DCIN connector PCB footprint and pin define

Change from (P/N :DC231000B00) FOX_JPD113E-LB103-7F_5P to
(P/N :DC231000L0L)SUYIN_040017FR003Y100ZL_5P

Change PR83 from SD00000068L(S RES 1/16W 8.45K +-1% 0402) to
SD03413728L (S RES 1/16W 13.7K +-1% 0402)

X01

X01

X01

X01

X01

modify ocp settingCompal03/13+1.8VP9 44

41 Charger Compal03/3110

4111 Charger 03/31 Compal

Change 90W CP setting from 4.4A to 4.16A

Add support 65W CP setting circuit :3A
(3.34A*0.9)

A A

44

VCCPP
+1.8VP

5

03/31 Compal12 43

H/S mosfet current rating not enough
(AO4466L Continuous Drain Current =9.4A)

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1.Change PQ26 from SB00000DU00(S TR AO4710 1N SO8) to
SB00000DA00 (S TR SI4634DY-T1-E3 1N SO8)

2.Change PR94 from SD03415028L(S RES 1/16W 15K +-1% 0402) to
SD034750180 (S RES 1/16W 7.5K +-1% 0402)

Change PR32 from SD03451128L(S RES 1/16W 51.1K +-1% 0402) to
SD034604280 (S RES 1/16W 60.4K +-1% 0402)

Add @PC191 SE102104K8L (S CER CAP .1U 10V +-10% X7R 0402)
Add PR116 SD03497628L (S RES 1/16W 97.6K +-1% 0402)
Add PQ38 SB000009080 (S TR SSM3K7002F 1N SC59-3)

Change PQ22, PQ25 from SB00000CG00 (S TR AO4466L 1N SO8)
to SB000006D8L (S TR FDS6298 1N SO8)

2006/10/1 2008/6/05

Compal Secret Data

Deciphered Date

2

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

Po

Po wer PIR

wer PIR

PoPo

wer PIRwer PIR

LLLL A-5 161 P

A-51 6 1P

A-51 6 1PA-51 61P

X02

X02

X02

X02

1

53 60Monday , April 20, 2009

0.1

5

Version Chang

Version Change List ( P. I. R. List )

Version ChangVersion Chang

It

It em

em DDDDate

ItIt

D D

C C

Page# TTTTitle

emem

Page#Page#

14

44

+1.8VP

e List ( P. I. R. List )

e List ( P. I. R. List )e List ( P. I. R. List )

Reque

Request

itle

itleitle

VCCPP

ate So

ateate

03/314313

03/31 Compal

RequeReque
OOOOwner

wner

wnerwner

Compal

4

st

stst

Is

Is sue Description

sue Description

IsIs

sue Descriptionsue Description

VCCPP output ripple over design spec. Change PC74, PC75 from SGA2022115L

+1.8VP output ripple over design spec.

3

So lution Description

lution Description RRRRev.

SoSo

lution Descriptionlution Description

(S POLY C 220U 4V M D2 PSL LESR15M H1.9) to SGA00003B00
(S POLY C 220U 2.5V M V LESR9M PSG H1.9 )

1. Change PC85 from SGA2022115L
(S POLY C 220U 4V M D2 PSL LESR15M H1.9) to SGA00003B00
(S POLY C 220U 2.5V M V LESR9M PSG H1.9 )

2. Add PC154, PC155 SE093475K8L
(S CER CAP 4.7U 6.3V +-10% X5R 0805 H.85 ) from +1.8VP to GND

2

1

ev.Page#

ev.ev.

X02

X02

B B

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/10/1 2008/6/05

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

Po

Po wer PIR

wer PIR

PoPo

wer PIRwer PIR

LLLL A-5 161 P

A-51 6 1P

A-51 6 1PA-51 61P

1

54 60Monday , April 20, 2009

0.1