Compal LA-5155P NAT02, Studio 1749 Schematic

1 1

Compal Confidential

2 2

NAT02 M/B Schematics Document

Intel Clarksfield Processor with DDRIII + Ibex Peak-M + Madison Pro

3 3

2009-08-20

REV:0.1

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/08/20 2010/08/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

157Monday, September 21, 2009

Block Diagram Compal confidential Model : NAT02

D D

CRT CONN

+5VS

P.34

FFS

+3VS

VGA

P.13

AMD

LVDS CONN

+LCDVDD +3.3V_ALW

P.34

DP CONN

+5VS

P.36

HDMI CONN

+5VS

C C

P.35

LVDS

DPB

DPA

To Card-reader subboard

8 IN 1 CONN

+3VS

IEEE1394

+3VS +1.8VS

CardBus

OZ888GS0

Madison Pro

29 x 29 mm

VRAM 64Mx16

P.29

FAN

+5VS +3VS

+1.1VS

P.37,38,39,40,41

P.42,43

P.13

PCI-E 2.0x16

5GT/s PER LANE

100MHz

PEG(DIS)

100MHz

PCI-Express x 8 (ABD PCIE1 2.5GT/S CKD PCIE1/2 2.5/5GT/S)

Intel Arrandale/ Clarksfield (DIS)

+CPU_CORE +1.1VS_VTT

Processor

rPGA988A

page 4,5,6,7,8,9

DMI x4

100MHz

1GB/s x4

Intel

Ibex Peak-M

+1.05VS

PCH

page 14,15,16,17 18,19,20,21,22

LPC BUS

+3VS 33MHz

IDT: 9LRS3199AKLFT SILEGO: SLG8SP587

133/120/100/96/14.318MHZ to PCH 48MHZ to CardReader

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 800/1066/1333

6.4G/8.5G/10.6G

100M/133M/166M(CFD)

USBx14 SATA x 6

(GEN1 1.5GT/S ,GEN2 3GT/S)

HD Audio

3.3V 48MHz 100MHz

3.3V 24MHz

SPI

SPI ROM x1

2MB

page 14

Clock Generator

Right Front Side.

Right behind side.

page 12

PCH XDP

page 22

DDRIII-DIMM X2

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8

+1.5V +0.75VS

USB Port X1

+5V_ALW

USB Port1 X1

+5V_ALW

Bluetooth

Touch Screen

Camera

P.10,11

P.29

P.31

P.29

Charge USB/E-SATA Ports X1

port 5

+5VALW

CPU XDP

133MHz

page 05

To Card-reader subboard

To Single USB subboard

P.29

Express Card

P.27

B B

RJ45

Mini Card 3

TV Tuner

+3VS

DC/DC Interface

A A

P.27 P.26 P.26

BATT IN

P.32 P.53

1.1VS_VTTPower Sequence

DC IN

RTL8111DL

+3VALW

Mini Card 2

WLAN

+3VS +1.5VS+1.5VS

USB[x]

P.50

P.45

P.23

PCIE1PCIE2PCIE3

Mini Card 1

WWAN

+3VS +1.5VS

USB[x]USB[x]

VCORE

CHARGER

1.5V/0.75V

P.52 P.49

3V/5V

GPU/1.1V 1.05V/1.8V

Int.KBD & BL

P.47P.46

P.48P.51

ENE KBC

KB926QFD3

+RTC_CELL +3VALW

P.30

SPI

SB3526

+3VS

To Cap Sensor subboard

page 31

Touch Pad

P.31P.31

Flash ROM 128KB

16Mx1sector

P.30

HeadPhone & MIC Jack

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/08/20 2010/08/20

Compal Secret Data

Deciphered Date

Azalia Codec

92HD73C

+3VS +VDDA

AMP

MAX4411x2

PCI Express BUS

P.24

port 4

E-ODD

+3VS +5VS

S-HDD-2

P.28 P.28 P.28

+5VS

AMP

MAX9736A

P.25

P.24

B+

AMP

MAX9736A

P.25

B+

Dig. MIC

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

401808

port 0port 1

S-HDD-1

+5VS

Speaker

Subwoofer

P.29

SCHEMATICS, MB A5155

257Monday, September 21, 2009

Voltage Rails

Power Plane Description

VIN

1 1

2 2

B+ +CPU_CORE +GPU_CORE Core voltage for GPU ON OFFOFF +0.75VS 0.75V switched power rail for DDR terminator +1.05VS +1.1VS_VTT 1.1V switched power rail (1.05 for AUB CPU) ON OFF OFF +1.1VS 1.1V power rail for PCIE of GUP ON OFF OFF +1.5V 1.5V power rail for DDRIII ON ON OFF +1.5VS +1.8VS 1.8V switched power rail +3VALW 3.3V always on power rail +LAN_IO 3.3V power rail for LAN ON ON +3VS +5VALW +5VS B+_BIAS B+ always on power rail ON ON* +RTCVCC RTC power

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Adapter power supply (19V) AC or battery power rail for power circuit. Core voltage for CPU

1.05V switched power rail for PCH

1.5V switched power rail

3.3V switched power rail 5V always on power rail 5V switched power rail

S1 S3 S5

N/A N/A N/A

ON OFF ON OFF OFF

ON OFF OFF ON ON

ON ON

N/AN/AN/A OFF

OFF

OFF ON ON*

ON* OFF

OFF ON

ON* OFFON

OFF

ONON

Board ID

X00 X01 X02 MP X00 X01 X02 MP

STATE

SIGNAL

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SLP_S1# SLP_S3#

SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH HIGH

LOW

HIGH

LOW LOW LOW LOW

HIGHHIGHHIGH

HIGH

LOWLOWLOW

HIGH

Board ID / SKU ID Table for AD channel

Vcc 3.3V +/- 5%

VGA

M96 M96 M96

M96 Madison Madison Madison Madison

100K +/- 1%Ra

Rb V min

AD_BID

8.2K +/- 1% 18K +/- 1% 33K +/- 1% 56K +/- 1% 100K +/- 1% 200K +/- 1%

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

0 V

V typ

OFF

AD_BID

ON ON

OFF

AD_BID

0 V 0.100 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

LOW

OFF

max

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupts

USB Port Table

EC SM Bus1 address

3 3

Device

Smart Battery

Address Address

0001 011X b

EC SM Bus2 address

Device

WWAN WLAN Express Card VGA thermal sensor

USB Port

0 1 2 3 4 5 6 7

Ibex SM Bus address

Device

Clock Generator (9LRS3191AKLFT, SLG8SP585)

DDR DIMM0 DDR DIMM1 Free Fall Sensor

4 4

CPU XDP PCH XDP XDCP_ISL90727 XDCP_ISL90728

Address

1101 0010b

1001 000Xb 1001 010Xb

0101 110Xb 0111 110Xb

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

8 9 10 11

2009/08/20 2010/08/20

Device USB&ESATA Reader/BD USB board WPAN WLAN WWAN NC NC Express Touch screen Bluetooth Camera

Compal Secret Data

Deciphered Date

BTO Option Table

BTO Item BOM Structure

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

401808

SCHEMATICS, MB A5155

357Monday, September 21, 2009

D D

SUSP#

TPS51117RGYR

(PU7)

SUSP#

ISL6268CAZ-T

(PU8)

ADAPTER

VR_ON

ISL62883HRZ-T (PU13)

BATTERY

B+

VGA_ON

SYSON

ISL6268CAZ-T (PU11)

ISL6268CAZ-T (PU10)

C C

SUSP#

CHARGER

SUSP#

TPS51117RGYR (PU6)

TPS51427

2500mA

15000mA

51000mA

20500mA

12800mA

5700mA

+1.8VS

+1.1VS_VTT

+CPU_CORE

+GPU_CORE

+1.5V

+1.05VS

SUSP#

0 Ohm

SI4800BDY (U25)

RT9025 (PU12)

RT9026 (PU10)

+1.05VS_CK505

8881mA

+1.5VS

913mA

+1.1VS

?mA

+0.75VS

(PU5)

+5VALW

RUNON

SI4800BDY

8400mA

B B

+5VS

(U22)

2000mA 8677mA160mA 20mA

USB_EN#

TPS2062ADR (U17)

+5V_CHGUSB

EN_EOL#

SI3456BDY (Q3)

+LAN_IO

EN_EOL#

RTL8111DL

FUSE

0 Ohm

+CRT_VCC

+AVDD_AUDIO

+5VS_KBL

(U9)

+LAN_VDD

+3VALW

SUSP

FBM-11-160808-601-T (L29)

+EC_AVCC

SUSP

SI4800BDY (U21)

+3VS

0 Ohm

+3VS_CK505

+DVDD_AUDIO

+3V_WLAN

VDDEN

SI2310BDS-T1-E3

(Q25)

+LCDVDD

EN_EOL#

SI2310BDS

(Q34)

+3VS_DELAY

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/08/20 2010/08/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

457Monday, September 21, 2009

JCPU1A

DMI_PTX_HRX_N0<17> DMI_PTX_HRX_N1<17> DMI_PTX_HRX_N2<17> DMI_PTX_HRX_N3<17>

DMI_PTX_HRX_P0<17> DMI_PTX_HRX_P1<17> DMI_PTX_HRX_P2<17>

D D

C C

B B

DMI_PTX_HRX_P3<17>

DMI_HTX_PRX_N0<17> DMI_HTX_PRX_N1<17> DMI_HTX_PRX_N2<17> DMI_HTX_PRX_N3<17>

DMI_HTX_PRX_P0<17> DMI_HTX_PRX_P1<17> DMI_HTX_PRX_P2<17> DMI_HTX_PRX_P3<17>

R2071K_0402_5%~D R2071K_0402_5%~D

CheckList0.8 1.22 Auburndale Graphics Disable

A24

DMI_RX#[0]

C23

DMI_RX#[1]

B22

DMI_RX#[2]

A21

DMI_RX#[3]

B24

DMI_RX[0]

D23

DMI_RX[1]

B23

DMI_RX[2]

A22

DMI_RX[3]

D24

DMI_TX#[0]

G24

DMI_TX#[1]

F23

DMI_TX#[2]

H23

DMI_TX#[3]

D25

DMI_TX[0]

F24

DMI_TX[1]

E23

DMI_TX[2]

G23

DMI_TX[3]

E22

FDI_TX#[0]

D21

FDI_TX#[1]

D19

FDI_TX#[2]

D18

FDI_TX#[3]

G21

FDI_TX#[4]

E19

FDI_TX#[5]

F21

FDI_TX#[6]

G18

FDI_TX#[7]

D22

FDI_TX[0]

C21

FDI_TX[1]

D20

FDI_TX[2]

C18

FDI_TX[3]

G22

FDI_TX[4]

E20

FDI_TX[5]

F20

FDI_TX[6]

G19

FDI_TX[7]

F17

FDI_FSYNC[0]

E17

FDI_FSYNC[1]

C17

FDI_INT

F18

FDI_LSYNC[0]

D17

FDI_LSYNC[1]

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9 CONN@

CONN@

DMI Intel(R) FDI

PCI EXPRESS -- GRAPHICS

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RBIAS PEG_RX#[0]

PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

B26 A26 B27 A25

PEG_GTX_C_HRX_N0

K35

PEG_GTX_C_HRX_N1

J34

PEG_GTX_C_HRX_N2

J33

PEG_GTX_C_HRX_N3

G35

PEG_GTX_C_HRX_N4

G32

PEG_GTX_C_HRX_N5

F34

PEG_GTX_C_HRX_N6

F31

PEG_GTX_C_HRX_N7

D35

PEG_GTX_C_HRX_N8

E33

PEG_GTX_C_HRX_N9

C33

PEG_GTX_C_HRX_N10

D32

PEG_GTX_C_HRX_N11

B32

PEG_GTX_C_HRX_N12

C31

PEG_GTX_C_HRX_N13

B28

PEG_GTX_C_HRX_N14

B30

PEG_GTX_C_HRX_N15

A31

PEG_GTX_C_HRX_P0

J35

PEG_GTX_C_HRX_P1

H34

PEG_GTX_C_HRX_P2

H33

PEG_GTX_C_HRX_P3

F35

PEG_GTX_C_HRX_P4

G33

PEG_GTX_C_HRX_P5

E34

PEG_GTX_C_HRX_P6

F32

PEG_GTX_C_HRX_P7

D34

PEG_GTX_C_HRX_P8

F33

PEG_GTX_C_HRX_P9

B33

PEG_GTX_C_HRX_P10

D31

PEG_GTX_C_HRX_P11

A32

PEG_GTX_C_HRX_P12

C30

PEG_GTX_C_HRX_P13

A28

PEG_GTX_C_HRX_P14

B29

PEG_GTX_C_HRX_P15

A30

PEG_HTX_GRX_N0

L33

PEG_HTX_GRX_N1

M35

PEG_HTX_GRX_N2

M33

PEG_HTX_GRX_N3

M30

PEG_HTX_GRX_N4

L31

PEG_HTX_GRX_N5

K32

PEG_HTX_GRX_N6

M29

PEG_HTX_GRX_N7

J31

PEG_HTX_GRX_N8

K29

PEG_HTX_GRX_N9

H30

PEG_HTX_GRX_N10

H29

PEG_HTX_GRX_N11

F29

PEG_HTX_GRX_N12

E28

PEG_HTX_GRX_N13

D29

PEG_HTX_GRX_N14

D27

PEG_HTX_GRX_N15

C26

PEG_HTX_GRX_P0

L34

PEG_HTX_GRX_P1

M34

PEG_HTX_GRX_P2

M32

PEG_HTX_GRX_P3

L30

PEG_HTX_GRX_P4

M31

PEG_HTX_GRX_P5

K31

PEG_HTX_GRX_P6

M28

PEG_HTX_GRX_P7

H31

PEG_HTX_GRX_P8

K28

PEG_HTX_GRX_P9

G30

PEG_HTX_GRX_P10

G29

PEG_HTX_GRX_P11

F28

PEG_HTX_GRX_P12

E27

PEG_HTX_GRX_P13

D28

PEG_HTX_GRX_P14

C27

PEG_HTX_GRX_P15

C25

PEG_IRCOMP

EXP_RBIAS

R605

49.9_0402_1%~D

1 2

R613

750_0402_1%~D

1 2

C980 0.1U_0402_16V7K~DC980 0.1U_0402_16V7K~D

1 2

C451 0.1U_0402_16V7K~DC451 0.1U_0402_16V7K~D

1 2

C981 0.1U_0402_16V7K~DC981 0.1U_0402_16V7K~D

1 2

C982 0.1U_0402_16V7K~DC982 0.1U_0402_16V7K~D

1 2

C983 0.1U_0402_16V7K~DC983 0.1U_0402_16V7K~D

1 2

C984 0.1U_0402_16V7K~DC984 0.1U_0402_16V7K~D

1 2

C985 0.1U_0402_16V7K~DC985 0.1U_0402_16V7K~D

1 2

C986 0.1U_0402_16V7K~DC986 0.1U_0402_16V7K~D

1 2

C987 0.1U_0402_16V7K~DC987 0.1U_0402_16V7K~D

1 2

C988 0.1U_0402_16V7K~DC988 0.1U_0402_16V7K~D

1 2

C989 0.1U_0402_16V7K~DC989 0.1U_0402_16V7K~D

1 2

C990 0.1U_0402_16V7K~DC990 0.1U_0402_16V7K~D

1 2

C991 0.1U_0402_16V7K~DC991 0.1U_0402_16V7K~D

1 2

C992 0.1U_0402_16V7K~DC992 0.1U_0402_16V7K~D

1 2

C993 0.1U_0402_16V7K~DC993 0.1U_0402_16V7K~D

1 2

C977 0.1U_0402_16V7K~DC977 0.1U_0402_16V7K~D

1 2

C994 0.1U_0402_16V7K~DC994 0.1U_0402_16V7K~D

1 2

C995 0.1U_0402_16V7K~DC995 0.1U_0402_16V7K~D

1 2

C996 0.1U_0402_16V7K~DC996 0.1U_0402_16V7K~D

1 2

C997 0.1U_0402_16V7K~DC997 0.1U_0402_16V7K~D

1 2

C998 0.1U_0402_16V7K~DC998 0.1U_0402_16V7K~D

1 2

C999 0.1U_0402_16V7K~DC999 0.1U_0402_16V7K~D

1 2

C1000 0.1U_0402_16V7K~DC1000 0.1U_0402_16V7K~D

1 2

C1001 0.1U_0402_16V7K~DC1001 0.1U_0402_16V7K~D

1 2

C1002 0.1U_0402_16V7K~DC1002 0.1U_0402_16V7K~D

1 2

C444 0.1U_0402_16V7K~DC444 0.1U_0402_16V7K~D

1 2

C1003 0.1U_0402_16V7K~DC1003 0.1U_0402_16V7K~D

1 2

C1004 0.1U_0402_16V7K~DC1004 0.1U_0402_16V7K~D

1 2

C1005 0.1U_0402_16V7K~DC1005 0.1U_0402_16V7K~D

1 2

C1006 0.1U_0402_16V7K~DC1006 0.1U_0402_16V7K~D

1 2

C1007 0.1U_0402_16V7K~DC1007 0.1U_0402_16V7K~D

1 2

C1008 0.1U_0402_16V7K~DC1008 0.1U_0402_16V7K~D

1 2

PEG_GTX_C_HRX_N0 <38> PEG_GTX_C_HRX_N1 <38> PEG_GTX_C_HRX_N2 <38> PEG_GTX_C_HRX_N3 <38> PEG_GTX_C_HRX_N4 <38> PEG_GTX_C_HRX_N5 <38> PEG_GTX_C_HRX_N6 <38> PEG_GTX_C_HRX_N7 <38> PEG_GTX_C_HRX_N8 <38> PEG_GTX_C_HRX_N9 <38> PEG_GTX_C_HRX_N10 <38> PEG_GTX_C_HRX_N11 <38> PEG_GTX_C_HRX_N12 <38> PEG_GTX_C_HRX_N13 <38> PEG_GTX_C_HRX_N14 <38> PEG_GTX_C_HRX_N15 <38>

PEG_GTX_C_HRX_P0 <38> PEG_GTX_C_HRX_P1 <38> PEG_GTX_C_HRX_P2 <38> PEG_GTX_C_HRX_P3 <38> PEG_GTX_C_HRX_P4 <38> PEG_GTX_C_HRX_P5 <38> PEG_GTX_C_HRX_P6 <38> PEG_GTX_C_HRX_P7 <38> PEG_GTX_C_HRX_P8 <38> PEG_GTX_C_HRX_P9 <38> PEG_GTX_C_HRX_P10 <38> PEG_GTX_C_HRX_P11 <38> PEG_GTX_C_HRX_P12 <38> PEG_GTX_C_HRX_P13 <38> PEG_GTX_C_HRX_P14 <38> PEG_GTX_C_HRX_P15 <38>

PEG_HTX_C_GRX_N0 <38> PEG_HTX_C_GRX_N1 <38> PEG_HTX_C_GRX_N2 <38> PEG_HTX_C_GRX_N3 <38> PEG_HTX_C_GRX_N4 <38> PEG_HTX_C_GRX_N5 <38> PEG_HTX_C_GRX_N6 <38> PEG_HTX_C_GRX_N7 <38> PEG_HTX_C_GRX_N8 <38> PEG_HTX_C_GRX_N9 <38> PEG_HTX_C_GRX_N10 <38> PEG_HTX_C_GRX_N11 <38> PEG_HTX_C_GRX_N12 <38> PEG_HTX_C_GRX_N13 <38> PEG_HTX_C_GRX_N14 <38> PEG_HTX_C_GRX_N15 <38>

PEG_HTX_C_GRX_P0 <38> PEG_HTX_C_GRX_P1 <38> PEG_HTX_C_GRX_P2 <38> PEG_HTX_C_GRX_P3 <38> PEG_HTX_C_GRX_P4 <38> PEG_HTX_C_GRX_P5 <38> PEG_HTX_C_GRX_P6 <38> PEG_HTX_C_GRX_P7 <38> PEG_HTX_C_GRX_P8 <38> PEG_HTX_C_GRX_P9 <38> PEG_HTX_C_GRX_P10 <38> PEG_HTX_C_GRX_P11 <38> PEG_HTX_C_GRX_P12 <38> PEG_HTX_C_GRX_P13 <38> PEG_HTX_C_GRX_P14 <38> PEG_HTX_C_GRX_P15 <38>

H_DIMMA_REF<11> H_DIMMB_REF<12>

R1035

3.01K_0402_1%~D @

3.01K_0402_1%~D @ R1036

R1036

3.01K_0402_1%~D @

3.01K_0402_1%~D @ R1037

3.01K_0402_1%~D

3.01K_0402_1%~D R1038

3.01K_0402_1%~D

WW41 Recommend not pull down PCIE2.0 Jitter is over on ES1

1 2

@R1037

1 2

@R1038

1 2

R212

R212 0_0402_5%~D

0_0402_5%~D

1 2

R213

R213 0_0402_5%~D

0_0402_5%~D

JCPU1E

AP25

RSVD1

AL25

RSVD2

AL24

RSVD3

AL22

RSVD4

AJ33

RSVD5

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18

AM30 AM28 AP31

AL32

AL30 AM31 AN29 AM32 AK32 AK31 AK28

AJ28 AN30 AN32

AJ32

AJ29

AJ30 AK30

AG9 M27 L28

H17 G25 G17 E31 E30

H16

B19 A19

A20 B20

AC9 AB9

A34 A33

C35 B35

J17

U9 T9

C1 A3

J29 J28

RSVD6 RSVD7 RSVD8

(SA_DIMM_VREF)

RSVD9

(SB_DIMM_VREF)

RSVD10 RSVD11 RSVD12 RSVD13 RSVD14

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] RSVD_TP_86

RSVD15 RSVD16

RSVD17 RSVD18

RSVD19 RSVD20

RSVD21 RSVD22

RSVD_NCTF_23 RSVD_NCTF_24

RSVD26 RSVD27

RSVD_NCTF_28 RSVD_NCTF_29

RSVD_NCTF_30 RSVD_NCTF_31

RSVD_NCTF_37

RSVD_NCTF_40 RSVD_NCTF_41

RSVD_NCTF_42 RSVD_NCTF_43

RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57

RESERVED

RSVD32 RSVD33

RSVD34 RSVD35

RSVD36

RSVD38 RSVD39

RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53

RSVD58

RSVD_TP_59 RSVD_TP_60

KEY RSVD62 RSVD63 RSVD64 RSVD65

RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75

RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85

VSS

AJ13 AJ12

AH25 AK26

AL26 AR2

AJ26 AJ27

AP1 AT2

AT3 AR1

AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32

E15 F15 A2 D15 C15 AJ15 AH15

AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3

V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9

AP34

PAD

R649

R649 0_0402_5%~D

0_0402_5%~D

@ @

R648

R648 0_0402_5%~D

0_0402_5%~D

T97

T97 T98

T98

T99

T99 T100

T100 T101

T101

T102

12 12

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9 CONN@

CONN@

CFG0 - PCI-Express Configuration Select

*1:Single PEG 0:Bifurcation enabled

CFG3 - PCI-Express Static Lane Reversal

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/07/29 2010/07/29

Compal Secret Data

*1 :Normal Operation 0 :Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

CFG4 - Display Port Presence

*1:Disabled; No Physical Display Port attached to Embedded Display Port 0:Enabled; An external Display Port device is connected to the Embedded Display Port

*:Default

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

557Monday, September 21, 2009

JCPU1B

H_COMP3 H_COMP2 H_COMP1 H_COMP0

PAD

R1039

1 2

0_0402_5%~D

R1042

1 2

0_0402_5%~D

R300

R300 0_0402_5%~D

0_0402_5%~D R263

R263 0_0402_5%~D

0_0402_5%~D R1043

R1043 0_0402_5%~D

0_0402_5%~D

R1045

1 2

0_0402_5%~D

R316

R316 0_0402_5%~D

0_0402_5%~D

R289

1 2

1.5K_0402_1%~D

1 2

D D

H_PECI<20>

H_PROCHOT#<55>

H_THERMTRIP#<20>

H_PM_SYNC<17>

C C

H_CPUPWRGD<20>

PM_DRAM_PWRGD<17>

H_VTTPWRGD<53>

H_PWRGD_XDP H_PWRGD_XDP_R

PLT_RST#<19,23,24,27,28,30,31>

SKTOCC#_R

H_CATERR#

H_PECI_R

H_PROCHOT#

H_THERMTRIP#_R

H_CPURST#

H_PM_SYNC_R

H_CPUPWRGD_1

H_CPUPWRGD_0

PM_DRAM_PWRGD_R

PLT_RST#_R

R1052

R1052 750_0402_1%~D

750_0402_1%~D

JCPU1B

AT23

COMP3

AT24

COMP2

G16

COMP1

AT26

COMP0

AH24

SKTOCC#

AK14

CATERR#

AT15

PECI

AN26

PROCHOT#

AK15

THERMTRIP#

AP26

RESET_OBS#

AL15

PM_SYNC

AN14

VCCPWRGOOD_1

AN27

VCCPWRGOOD_0

AK13

SM_DRAMPWROK

AM15

VTTPWRGOOD

AM26

TAPPWRGOOD

AL14

RSTIN#

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9 CONN@

CONN@

MISC THERMAL

CLOCKS

DDR3

MISC

DDR3

MISC

PWR MANAGEMENT

JTAG & BPM

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PM_EXT_TS#[0] PM_EXT_TS#[1]

PRDY# PREQ#

TMS

TRST#

TDO

TDI_M

TDO_M

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

TCK

CLK_CPU_BCLK_R

A16

CLK_CPU_BCLK#_R

B16

CLK_CPU_ITP_R

AR30

CLK_CPU_ITP#_R

AT30

CLK_CPU_DMI_R

E16

CLK_CPU_DMI#_R

D16 A18

A17

F6 AL1

AM1 AN1

AN15 AP15

AT28 AP27

AN28 AP28 AT27

AT29

TDI

AR27 AR29 AP29

AN25

AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23

1 2

CPU_SM_DRAMRST# SM_RCOMP_0

SM_RCOMP_1 SM_RCOMP_2

PM_EXTTS#0 PM_EXTTS#1_R

XDP_PRDY# XDP_PREQ#

XDP_TCLK XDP_TMS XDP_TRST#

XDP_TDI_R XDP_TDO_R XDP_TDI_M XDP_TDO_M

XDP_DBR#_R

R609 0_0402_5%~DR609 0_0402_5%~D

1 2

R610 0_0402_5%~DR610 0_0402_5%~D

1 2

R655 0_0402_5%~DR655 0_0402_5%~D

1 2

R654 0_0402_5%~DR654 0_0402_5%~D

1 2

R606 0_0402_5%~DR606 0_0402_5%~D

1 2

R607 0_0402_5%~DR607 0_0402_5%~D

R310

100K_0402_5%~D

1 2

R1060 0_0402_5%~DR1060 0_0402_5%~D

1 2

R1044 0_0402_5%~DR1044 0_0402_5%~D

1 2

R1046 0_0402_5%~DR1046 0_0402_5%~D

1 2

R1047 0_0402_5%~DR1047 0_0402_5%~D

1 2

R1048 0_0402_5%~DR1048 0_0402_5%~D

1 2

R1049 0_0402_5%~DR1049 0_0402_5%~D

1 2

R1050 0_0402_5%~DR1050 0_0402_5%~D

1 2

R1051 0_0402_5%~DR1051 0_0402_5%~D

1 2

R284 0_0402_5%~DR284 0_0402_5%~D

1 2

CLK_CPU_XDP CLK_CPU_XDP#

Q36BSS138_SOT23~D

1 2 1 2 1 2

XDP_DBRESET#

XDP_OBS0XDP_OBS0_R XDP_OBS1XDP_OBS1_R XDP_OBS2XDP_OBS2_R XDP_OBS3XDP_OBS3_R XDP_OBS4XDP_OBS4_R XDP_OBS5XDP_OBS5_R XDP_OBS6XDP_OBS6_R XDP_OBS7XDP_OBS7_R

Q36BSS138_SOT23~D

R1121 0_0402_5%~D R1121 0_0402_5%~D

1 2

R1040 10K_0402_5%~DR1040 10K_0402_5%~D R288 10K_0402_5%~DR288 10K_0402_5%~D R1041 0_0402_5%~DR1041 0_0402_5%~D

CLK_CPU_BCLK <20> CLK_CPU_BCLK# <20>

CLK_CPU_DMI <16> CLK_CPU_DMI# <16>

+1.1VS_VTT

XDP_DBRESET# <17,23>

1.5V_PWRGD<52>

DDR_RST_GATE <11,12,20>

SM_DRAMRST# <11,12>

PM_EXTTS#0_1 <11,12>

R1136

1 2

10K_0402_5%~D

74AHC1G08GW_SOT353-5~D

JTAG MAPPING

Scan Chain (Default)

CPU Only

GMCH Only

1 2 1 2 1 2 1 2

1 2

1 2 1 2

R290

@R290

750_0402_1%~D

PM_DRAM_PWRGD_R

R1103

@R1103

1 2

+1.1VS_VTT

XDP_TDO

+3VALW

C1142

1 2

0.1U_0402_10V6K~D

U63

IN1

1.5K_0402_1%~D

XDP_TMS XDP_TDI_R XDP_PREQ# XDP_TCLK

XDP_TRST#

XDP_TDI_R XDP_TDI XDP_TDO_M

XDP_TDI_M XDP_TDO_R

1.5K_0402_1%~D

IN2

R657 51_0402_1%~D@R657 51_0402_1%~D@ R653 51_0402_1%~D@R653 51_0402_1%~D@ R656 51_0402_1%~D@R656 51_0402_1%~D@ R669 51_0402_1%~D@R669 51_0402_1%~D@

R651 51_0402_1%~DR651 51_0402_1%~D

R661 0_0402_5%~DR661 0_0402_5%~D R662 0_0402_5%~D@R662 0_0402_5%~D@

R663

R663 0_0402_5%~D

0_0402_5%~D

R667 0_0402_5%~D

R667 0_0402_5%~D R668 0_0402_5%~DR668 0_0402_5%~D

STUFF -> R653, R657, R662 NO STUFF -> R655, R660

STUFF -> R653, R655 NO STUFF -> R657, R660, R662

STUFF -> R660, R662 NO STUFF -> R653, R655, R657

WW51.4 CRB Board Rework/workaround- Rev 0.1 has changed the resistors in RSTIN#

B B

+1.1VS_VTT

PBTN_OUT#<17,23,31>

+1.1VS_VTT

C315

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D @

R365

R365 1K_0402_5%~D

1K_0402_5%~D

H_CPUPWRGD

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2 1 2

R363 0_0402_5%~DR363 0_0402_5%~D

SMB_DATA_S3<23> SMB_CLK_S3<23>

Issued Date

+1.5V

R1054

1.1K_0402_1%~D

PM_DRAM_PWRGD_R

R1055

3K_0402_1%~D

A A

[Calpella] Platform – Design Guide Addendum / Update – Rev. 1.52

H_CATERR# H_PROCHOT# H_CPURST#

H_COMP0 H_COMP1 H_COMP2 H_COMP3

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

R1053 49.9_0402_1%~DR1053 49.9_0402_1%~D

1 2

R1061 68_0402_5%~DR1061 68_0402_5%~D

1 2

R1062 68_0402_5%~D@R1062 68_0402_5%~D@

1 2

R650 49.9_0402_1%~DR650 49.9_0402_1%~D

1 2

R234 49.9_0402_1%~DR234 49.9_0402_1%~D

1 2

R659 20_0402_1%~DR659 20_0402_1%~D

1 2

R658 20_0402_1%~DR658 20_0402_1%~D

1 2

R645 100_0402_1%~DR645 100_0402_1%~D

1 2

R646 24.9_0402_1%~DR646 24.9_0402_1%~D

1 2

R647 130_0402_1%~DR647 130_0402_1%~D

1 2

XDP_PREQ# XDP_PRDY#

XDP_OBS0 XDP_OBS1

XDP_OBS2 XDP_OBS3

XDP_OBS4 XDP_OBS5

XDP_OBS6 XDP_OBS7

H_PWRGOOD_R PBTN_OUT#_XDP

H_PWRGD_XDP

XDP_TCLK

2009/07/29 2010/07/29

XDP Connector

JP8

GND0

OBSFN_A0

OBSFN_A1

GND2

OBSDATA_A0

OBSDATA_A1

GND4

OBSDATA_A2

OBSDATA_A3

GND6

OBSFN_B0

OBSFN_B1

GND8

OBSDATA_B0

OBSDATA_B1

GND10

OBSDATA_B2

OBSDATA_B3

GND12

PWRGOOD/HOOK0

HOOK1

VCC_OBS_AB

HOOK2

HOOK3

GND14

SDA

SCL

TCK1

TCK0

GND16

Compal Secret Data

SAMTE_BSH-030-01-L-D-ACONN@

Deciphered Date

GND1 OBSFN_C0 OBSFN_C1

GND3

OBSDATA_C0 OBSDATA_C1

GND5

OBSDATA_C2 OBSDATA_C3

GND7 OBSFN_D0 OBSFN_D1

GND9

OBSDATA_D0 OBSDATA_D1

GND11 OBSDATA_D2 OBSDATA_D3

GND13

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND15

TRST#

TMS

GND17

TD0

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56

TDI

58 60

H_RESET#_R

CLK_CPU_XDP CLK_CPU_XDP#

H_RESET#_R XDP_DBRESET#

XDP_TDO XDP_TRST# XDP_TDI XDP_TMS

R1063

R1063 1K_0402_5%~D

1K_0402_5%~D

1 2 1 2

R362

R362 0_0402_5%~D

0_0402_5%~D

1 2 1 2

Title

Size Document Number Rev

Custom

Date: Sheet

H_CPURST#

R1064

R1064 1K_0402_5%~D

1K_0402_5%~D

R1065

R1065 51_0402_1%~D

51_0402_1%~D

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

PCI_PLTRST# <19>

+1.1VS_VTT

Leakage Issue

+3VS +1.1VS_VTT

657Monday, September 21, 2009

JCPU1C

A10

C10

B10

D10

E10

F10

H10

G10

AH5 AF5 AK6 AK7 AF6 AG5

AJ7 AJ6

AJ10

AJ9 AL10 AK12

AK8

AL7 AK11

AL8

AN8 AM10 AR11

AL11

AM9

AN9

AT11

AP12 AM12 AN12 AM13

AT14

AT12

AL13 AR14

AP14

AC3 AB2

AE1 AB3 AE9

C7 A7

A8 D8

E6 E9

B7 E7 C6

G8 K7

J10

M6 M8

K8 N8 P9

J7 L7

L9 L6

JCPU1C

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

DDR_A_D[0..63]<11> DDR_A_DM[0..7]<11>

DDR_A_DQS#[0..7]<11>

DDR_A_DQS[0..7]<11>

DDR_A_MA[0..15]<11>

DDR_A_D0 DDR_A_D1

D D

C C

B B

DDR_A_BS0<11> DDR_A_BS1<11> DDR_A_BS2<11>

DDR_A_CAS#<11> DDR_A_RAS#<11>

DDR_A_WE#<11>

DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

DDR_A_CAS# DDR_A_RAS# DDR_A_WE#

SA_CK[0] SA_CK#[0] SA_CKE[0]

SA_CK[1] SA_CK#[1] SA_CKE[1]

SA_CS#[0] SA_CS#[1]

SA_ODT[0] SA_ODT[1]

SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

AA6 AA7 P7

Y6 Y5 P6

AE2 AE8

AD8 AF9

B9 D7 H7 M7 AG6 AM7 AN10 AN13

C9 F8 J9 N9 AH7 AK9 AP11 AT13

C8 F9 H9 M9 AH8 AK10 AN11 AR13

Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDR_A_CLK0 <11> DDR_A_CLK0# <11> DDR_A_CKE0 <11>

DDR_A_CLK1 <11> DDR_A_CLK1# <11> DDR_A_CKE1 <11>

DDR_A_CS0# <11> DDR_A_CS1# <11>

DDR_A_ODT0 <11> DDR_A_ODT1 <11>

DDR_B_D[0..63]<12>

DDR_B_DM[0..7]<12>

DDR_B_DQS#[0..7]<12>

DDR_B_DQS[0..7]<12> DDR_B_MA[0..15]<12>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

DDR_B_BS0<12> DDR_B_BS1<12> DDR_B_BS2<12>

DDR_B_CAS#<12> DDR_B_RAS#<12>

DDR_B_WE#<12>

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

DDR_B_CAS# DDR_B_RAS# DDR_B_WE#

AF3

AG1

AK1 AG4 AG3

AH4

AK3

AK4 AM6 AN2

AK5

AK2 AM4 AM3

AP3 AN5

AT4 AN6 AN4 AN3

AT5

AT6 AN7

AP6

AP8

AT9

AT7

AP9

AR10

AT10

AB1

AC5 AC6

B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3 G4 H6 G2 J6 J3 G1 G5 J2 J1 J5 K2 L3

K4 M4 N5

AJ3

AJ4

JCPU1D

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE#

SB_CK[0]

SB_CK#[0]

SB_CKE[0]

SB_CK[1]

SB_CK#[1]

SB_CKE[1]

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

DDR SYSTEM MEMORY - B

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

W8 W9 M3

V7 V6 M2

AB8 AD6

AC7 AD1

D4 E1 H3 K1 AH1 AL2 AR4 AT8

D5 F4 J4 L4 AH2 AL4 AR5 AR8

C5 E3 H4 M5 AG2 AL5 AP5 AR7

U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

DDR_B_CLK0 <12> DDR_B_CLK0# <12> DDR_B_CKE0 <12>

DDR_B_CLK1 <12> DDR_B_CLK1# <12> DDR_B_CKE1 <12>

DDR_B_CS0# <12> DDR_B_CS1# <12>

DDR_B_ODT0 <12> DDR_B_ODT1 <12>

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9 CONN@

CONN@

A A

Security Classification

2009/07/29 2010/07/29

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/07/29 2010/07/29

Compal Secret Data

Deciphered Date

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9 CONN@

CONN@

Compal Electronics, Inc.

Title

SCHEMATICS, MB A5155

Size Document Number Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

401808

757Monday, September 21, 2009

JCPU1F

+CPU_CORE

WW15 MOW

48A Continuous 18A

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

D D

C C

B B

A A

AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26

VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

1.1V RAIL POWER

CPU CORE SUPPLY

POWER

CPU VIDS

SENSE LINES

Peak 21A

VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8

VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32

VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44

PSI#

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

PROC_DPRSLPVR

VTT_SELECT

ISENSE

VCC_SENSE

VSS_SENSE

VTT_SENSE

VSS_SENSE_VTT

AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15

AN33

AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34

H_VTTVID1

G15

H_VTTVID1 = low, 1.1V H_VTTVID1 = high, 1.05V

AN35

1 2

C1557 1000P_0402_50V7K~D@C1557 1000P_0402_50V7K~D@

VCCSENSE_R

AJ34

VSSSENSE_R

AJ35

B15

VSS_SENSE_VTT

A15

close to CPU side.

10U_0805_6.3V6M~D

C174

C183

10U_0805_6.3V6M~D

C222

22U_0805_6.3V6M~OK

10U_0805_6.3V6M~D

330U_X_2VM_R6M~OK

C1009

C1010

330U_X_2VM_R6M~OK

22U_0805_6.3V6M~OK

C240

IMVP_IMON <55>

R0.3 modify

R641 0_0402_5%~DR641 0_0402_5%~D

1 2

R642 0_0402_5%~DR642 0_0402_5%~D

1 2

R608 0_0402_5%~DR608 0_0402_5%~D

1 2

10U_0805_6.3V6M~D

C192

+1.1VS_VTT

C1011

330U_X_2VM_R6M~OK

+1.1VS_VTT

10U_0805_6.3V6M~D

C195

C203

10U_0805_6.3V6M~D

H_PSI# <55>

CPU_VID0 <55> CPU_VID1 <55> CPU_VID2 <55> CPU_VID3 <55> CPU_VID4 <55> CPU_VID5 <55> CPU_VID6 <55> H_DPRSLPVR <55>

H_VTTVID1 <53>

C211

10U_0805_6.3V6M~D

VTT Rail

Auburndale +1.1VS_VTT=1.05V Clarksfield +1.1VS_VTT=1.1V

1 2

R643 100_0402_1%~DR643 100_0402_1%~D

VCCSENSE VSSSENSE

1 2

VTT_SENSE <53>

R644 100_0402_1%~DR644 100_0402_1%~D

+1.1VS_VTT

1 2 1 2

+CPU_CORE

10U_0805_6.3V6M~D

C191

+CPU_CORE

470U_D2_2VM_R4.5M~OK

C1044

C159

CSC (Current Sense Configuration) 8/25

CPU_VID0

CPU_VID1

CPU_VID2

CPU_VID3

CPU_VID4

CPU_VID5

CPU_VID6

H_DPRSLPVR

H_PSI#

R1066 1K_0402_1%~DR1066 1K_0402_1%~D R1067 1K_0402_1%~D@R1067 1K_0402_1%~D@

R1068 1K_0402_1%~DR1068 1K_0402_1%~D R1069 1K_0402_1%~D@R1069 1K_0402_1%~D@

R1070 1K_0402_1%~DR1070 1K_0402_1%~D R1071 1K_0402_1%~D@R1071 1K_0402_1%~D@

R343 1K_0402_1%~D@R343 1K_0402_1%~D@ R1072 1K_0402_1%~DR1072 1K_0402_1%~D

R1073 1K_0402_1%~D@R1073 1K_0402_1%~D@ R1074 1K_0402_1%~DR1074 1K_0402_1%~D

R1075 1K_0402_1%~DR1075 1K_0402_1%~D R1076 1K_0402_1%~D@R1076 1K_0402_1%~D@

R1077 1K_0402_1%~D@R1077 1K_0402_1%~D@ R1078 1K_0402_1%~DR1078 1K_0402_1%~D

R347 1K_0402_1%~DR347 1K_0402_1%~D R1079 1K_0402_1%~D@R1079 1K_0402_1%~D@

R348 1K_0402_1%~D@R348 1K_0402_1%~D@ R1080 1K_0402_1%~DR1080 1K_0402_1%~D

+CPU_CORE

VCCSENSE <55>

VSSSENSE <55>

10U_0805_6.3V6M~D

C201

10U_0805_6.3V6M~D

+1.1VS_VTT

(Place these capacitors between inductor and socket on Bottom)

10U_0805_6.3V6M~D

4 x 470uF(4.5mohm@100kHz; 4.0mohm@SRF)

C251

470U_D2_2VM_R4.5M~OK

TOP side (under inductor)

10U_0805_6.3V6M~D

+CPU_CORE

C213

10U_0805_6.3V6M~D

C185

(Place these capacitors under CPU socket, top layer)

+CPU_CORE

22U_0805_6.3V6M~OK

C1034

22U_0805_6.3V6M~OK

(Place these capacitors on CPU cavity, Bottom Layer)

+CPU_CORE

22U_0805_6.3V6M~OK

C1039

22U_0805_6.3V6M~OK

+CPU-CORE Decoupling SPCAP,Polymer

C1012

470U_D2_2VM_R4.5M~OK

MLCC 0805 X5R

C245

C233

C194

C1035

C1040

(Place these capacitors on CPU cavity, Bottom Layer)

C245

10U_0805_6.3V6M~D

C199

10U_0805_6.3V6M~D

C1036

22U_0805_6.3V6M~OK

C1041

22U_0805_6.3V6M~OK

470U_D2_2VM_R4.5M~OK

C533

C,uF 4X470uF 4m ohm/4

16X22uF 16X10uF 3m ohm/16

10U_0805_6.3V6M~D

C190

C208

10U_0805_6.3V6M~D

22U_0805_6.3V6M~OK

C1037

22U_0805_6.3V6M~OK

C1042

470U_D2_2VM_R4.5M~OK

ESR, mohm

3m ohm/12

22U_0805_6.3V6M~OK

C200

10U_0805_6.3V6M~D

C214

C1062

C1063

C263

C263 @

22U_0805_6.3V6M~OK

Stuffing Option

2X470uF

10U_0805_6.3V6M~D

C232

C212

C223

C1038

C1043

470U_D2_2VM_R4.5M~OK

C232

C239

10U_0805_6.3V6M~D

C167

C167 @

Security Classification

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9 CONN@

CONN@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/07/29 2010/07/29

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

857Monday, September 21, 2009

D D

C C

22U_0805_6.3V6M~OK

B B

22U_0805_6.3V6M~OK

+1.1VS_VTT

C179

+1.1VS_VTT

C177

C178

C178 22U_0805_6.3V6M~OK

22U_0805_6.3V6M~OK

C176

C176 22U_0805_6.3V6M~OK

22U_0805_6.3V6M~OK

JCPU1G

AT21

VAXG1

AT19

VAXG2

AT18

VAXG3

AT16

VAXG4

AR21

VAXG5

AR19

VAXG6

AR18

VAXG7

AR16

VAXG8

AP21

VAXG9

AP19

VAXG10

AP18

VAXG11

AP16

VAXG12

AN21

VAXG13

AN19

VAXG14

AN18

VAXG15

AN16

VAXG16

AM21

VAXG17

AM19

VAXG18

AM18

VAXG19

AM16

VAXG20

AL21

VAXG21

AL19

VAXG22

AL18

VAXG23

AL16

VAXG24

AK21

VAXG25

AK19

VAXG26

AK18

VAXG27

AK16

VAXG28

AJ21

VAXG29

AJ19

VAXG30

AJ18

VAXG31

AJ16

VAXG32

AH21

VAXG33

AH19

VAXG34

AH18

VAXG35

AH16

VAXG36

J24

VTT1_45

J23

VTT1_46

H25

VTT1_47

K26

VTT1_48

J27

VTT1_49

J26

VTT1_50

J25

VTT1_51

H27

VTT1_52

G28

VTT1_53

G27

VTT1_54

G26

VTT1_55

F26

VTT1_56

E26

VTT1_57

E25

VTT1_58

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9 CONN@

CONN@

15A

GRAPHICS

FDI PEG & DMI

VAXG_SENSE

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6]

GFX_VR_EN

GFX_DPRSLPVR

GFX_IMON

GRAPHICS VIDs

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6

POWER

0.6A

VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18

DDR3 - 1.5V RAILS

VTT0_59 VTT0_60 VTT0_61 VTT0_62

VTT1_63 VTT1_64 VTT1_65

1.1V1.8V

VTT1_66 VTT1_67 VTT1_68

VCCPLL1 VCCPLL2 VCCPLL3

AR22 AT22

AM22 AP22 AN22 AP23 AM23 AP24 AN24

AR25 AT25 AM24

AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1

P10 N10 L10 K10

J22 J20 J18 H21 H20 H19

L26 L27 M26

R283 1K_0402_5%~DR283 1K_0402_5%~D

1 2

1U_0402_6.3V4Z~D

C193

C196

1U_0402_6.3V4Z~D

+1.1VS_VTT

C158

C158 22U_0805_6.3V6M~OK

22U_0805_6.3V6M~OK

+1.8VS_VCCSFR

C175

C182

1U_0402_6.3V4Z~D

C202

C209

1U_0402_6.3V4Z~D

C160

C160 10U_0805_6.3V6M~D

10U_0805_6.3V6M~D

2.2U_0603_6.3V6K~D

C168

C180

4.7U_0805_10V4Z~D

22U_0805_6.3V6M~OK

C216

C184

1U_0402_6.3V4Z~D

+1.5V_CPU_DDR

C224

22U_0805_6.3V6M~OK

R228

0.022_0805_1%~OK

1 2

C165

22U_0805_6.3V6M~OK

+1.5V

C1033

1 2

0.1U_0402_16V7K~D

C1143

1 2

0.1U_0402_16V7K~D

C1144

1 2

0.1U_0402_16V7K~D

C1145

1 2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D PJP12

PJP12 JUMP_43X118@

JUMP_43X118@

C250

330U_D2_2V_Y~OK

+1.8VS

112

PJP13

PJP13 JUMP_43X118@

JUMP_43X118@

112

PJP14

PJP14 JUMP_43X118@

JUMP_43X118@

112

A A

Security Classification

2009/07/29 2010/07/29

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/07/29 2010/07/29

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SCHEMATICS, MB A5155

Size Document Number Rev

Custom

401808

Date: Sheet

Compal Electronics, Inc.

957Monday, September 21, 2009

JCPU1H

AT20

VSS1

AT17

VSS2

AR31

VSS3

AR28

VSS4

AR26

VSS5

AR24

VSS6

D D

C C

B B

AR23 AR20 AR17 AR15 AR12

AR9 AR6

AR3 AP20 AP17 AP13 AP10

AP7

AP4

AP2 AN34 AN31 AN23 AN20 AN17

AM29 AM27 AM25 AM20 AM17 AM14 AM11

AM8

AM5

AM2 AL34 AL31 AL23 AL20 AL17 AL12

AL9 AL6

AL3 AK29 AK27 AK25 AK20 AK17 AJ31 AJ23 AJ20 AJ17 AJ14 AJ11

AJ8

AJ5

AJ2

AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13

AH9 AH6 AH3

AG10

AF8 AF4 AF2

AE35

VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80

VSS

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30

JCPU1I

K27

VSS161

VSS162

VSS163

VSS164

J32

VSS165

J30

VSS166

J21

VSS167

J19

VSS168

H35

VSS169

H32

VSS170

H28

VSS171

H26

VSS172

H24

VSS173

H22

VSS174

H18

VSS175

H15

VSS176

H13

VSS177

H11

VSS178

VSS179

VSS180

VSS181

G34

VSS182

G31

VSS183

G20

VSS184

VSS185

VSS186

VSS187

F30

VSS188

F27

VSS189

F25

VSS190

F22

VSS191

F19

VSS192

F16

VSS193

E35

VSS194

E32

VSS195

E29

VSS196

E24

VSS197

E21

VSS198

E18

VSS199

E13

VSS200

E11

VSS201

VSS202

VSS203

VSS204

D33

VSS205

D30

VSS206

D26

VSS207

VSS208

VSS209

VSS210

C34

VSS211

C32

VSS212

C29

VSS213

C28

VSS214

C24

VSS215

C22

VSS216

C20

VSS217

C19

VSS218

C16

VSS219

B31

VSS220

B25

VSS221

B21

VSS222

B18

VSS223

B17

VSS224

B13

VSS225

B11

VSS226

VSS227

VSS228

VSS229

A29

VSS230

A27

VSS231

A23

VSS232

VSS233

VSS

NCTF

VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7

AT35 AT1 AR34 B34 B2 B1 A35

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9 CONN@

CONN@

A A

Security Classification

2009/07/29 2010/07/29

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/07/29 2010/07/29

Compal Secret Data

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9 CONN@

CONN@

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

10 57Monday, September 21, 2009

M1 Circuit M3 Circuit

+1.5V

R170

1K_0402_1%~D

D D

+V_DDR3_DIMMA_REF

R169

R169 1K_0402_1%~D

1K_0402_1%~D

+V_DDR3_DIMMA_REF +V_DDR3_DIMMB_REF

M2 Circuit

+3V

C164

@C164

1U_0402_6.3V4Z~D

C C

Layout Note: Place near JDIMM1

B B

10U_0805_6.3V6M~D

Layout Note: Place near JDIMM1.203 & JDIMM1.204

A A

PCH_SMBCLK PCH_SMBDATA

PM_SLP_S4#<17>

10U_0805_6.3V6M~D

C204

C186

+0.75VS

1U_0603_10V4Z~D

C1015

1U_0603_10V4Z~D

+1.5V

U45

VDD

GND

SCL

ISL90727WIE627Z-TK_SC70-6@

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

10U_0805_6.3V6M~D

C171

C187

10U_0805_6.3V6M~D

1U_0603_10V4Z~D

C280

C1016

1U_0603_10V4Z~D

SDA

+5VALW

R226

@R226

100K_0402_5%~D

Q48B

@Q48B

@ 2N7002DW-7-F_SOT363-6~D

2N7002DW-7-F_SOT363-6~D

C170

10U_0805_6.3V6M~D

C1017

C281

10U_0805_6.3V6M~D

VREF_RW_POT0

PP_S4GT

10U_0805_6.3V6M~D

C205

1 2

0_0402_5%~D

+1.5V

R223

@R223

12.1K_0402_1%~D

R222

@R222

12.1K_0402_1%~D

0.1U_0402_16V4Z~D

DDR_A_DQS#[0..7]<7>

DDR_A_D[0..63]<7>

DDR_A_DM[0..7]<7> DDR_A_DQS[0..7]<7> DDR_A_MA[0..15]<7>

PCH_SMBCLK<12,16,23>

PCH_SMBDATA<12,16,23>

R1245

+5VALW

1 2

@U46A

@ LM358DT_SO8

LM358DT_SO8

VREF_OPAMP_POT0

PP_S4GT<12>

R230

@R230

1M_0402_5%~D

0.1U_0402_16V4Z~D

C1045

C1013

+V_DDR3_DIMMA_REF

C153

U46A

0.1U_0402_16V4Z~D

PCH_SMBCLK PCH_SMBDATA

R1229

1 2

0_0402_5%~D

1U_0402_6.3V4Z~D@

@R221

2.2_0402_5%~D

1 2

10_0402_5%~D

PP_S4GT

0.1U_0402_16V4Z~D

C1046

1 3

Q37

BSS138_SOT23~D

H_DIMMA_REF<5>

+V_DDR3_DIMMA_REF

+V_DDR3_DIMMB_REF2+V_DDR3_DIMMA_REF2

R1246

1 2

0_0402_5%~D

2008/9/8 #400755 Calpella Clarksfield DDR3 SO-DIMM VREFDQ Platform Design Guide Change Details

R221

R220

@R220

C1064

VREF_POT0_R

C163

C163 1U_0402_6.3V4Z~D

1U_0402_6.3V4Z~D @

PP_S4GT_Q_0

@ Q48A

Q48A 2N7002DW-7-F_SOT363-6~D

2N7002DW-7-F_SOT363-6~D

C197

C197 330U_D2_2V_Y~OK

330U_D2_2V_Y~OK

R313

@ R313

100K_0402_5%~D

1 2

VREF_POT0_R

M1 Circuit

1K_0402_1%~D

DDR_RST_GATE <6,12,20>

H_DIMMA_REF <5>

R178 0_0402_5%~D@R178 0_0402_5%~D@

1 2

R179 0_0402_5%~DR179 0_0402_5%~D

1 2

R227 0_0402_5%~D@R227 0_0402_5%~D@

1 2

C124

0.1U_0402_16V4Z~D

+1.5V

R1247

+V_DDR3_DIMMA_REF2

R1248

R1248 1K_0402_1%~D

1K_0402_1%~D

2.2U_0603_6.3V4Z~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C112

2.2U_0805_16V4Z~D

DDR_A_CKE0<7>

DDR_A_BS2<7>

DDR_A_CLK0<7> DDR_A_CLK0#<7>

DDR_A_BS0<7>

DDR_A_WE#<7>

DDR_A_CAS#<7> DDR_A_ODT0 <7>

DDR_A_CS1#<7>

+V_DDR3_DIMMA_REF2

+3VS

C1014

2009/07/29 2010/07/29

VREF_DQA

DDR_A_D0 DDR_A_D1

DDR_A_DM0 DDR_A_D2

DDR_A_D3 DDR_A_D8

DDR_A_D9 DDR_A_DQS#1

DDR_A_DQS1 DDR_A_D10

DDR_A_D11 DDR_A_D16

DDR_A_D17 DDR_A_DQS#2

DDR_A_DQS2 DDR_A_D18

DDR_A_D19 DDR_A_D24

DDR_A_D25 DDR_A_DM3 DDR_A_D26

DDR_A_D27 DDR_A_D31

DDR_A_CKE0

DDR_A_BS2 DDR_A_MA12

DDR_A_MA9 DDR_A_MA8

DDR_A_MA5 DDR_A_MA3

DDR_A_MA1 DDR_A_CLK0

DDR_A_CLK0# DDR_A_MA10

DDR_A_BS0 DDR_A_WE#

DDR_A_CAS# DDR_A_MA13

DDR_A_CS1#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5 DDR_A_D42

DDR_A_D43 DDR_A_D48

DDR_A_D49 DDR_A_DQS#6

DDR_A_DQS6 DDR_A_D50

DDR_A_D51 DDR_A_D56

DDR_A_D57 DDR_A_DM7 DDR_A_D58

DDR_A_D59

R1057 10K_0402_5%~DR1057 10K_0402_5%~D

1 2

C276

0.1U_0402_16V4Z~D

+1.5V +1.5V

11 13 15 17 19 21 23 25 27

33 35

39 41

45 47 49 51 53 55 57 59

63 67

73 75 77 79 81 83 85 87 89 91 93 95 97

99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201

R1081

R1081 10K_0402_5%~D

10K_0402_5%~D

Compal Secret Data

203 205

Deciphered Date

JDIMM1

VREF_DQ1VSS1

VSS2

DQ0

DQ1

VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS129RESET# VSS1131VSS12 DQ10 DQ11 VSS1337VSS14 DQ16 DQ17 VSS1543VSS16 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS2261DQS#3 DM3 VSS2365VSS24 DQ26 DQ27 VSS2571VSS26

CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1

FOX_AS0A626-U4RN-7F

FOX_AS0A626-U4RN-7F CONN@

CONN@

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6 DQ7

VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3 DQ30

DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

BA1

RAS#

VDD14

S0#

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

SCL

VTT2

DDR_A_D4

DDR_A_D5

6 8

DDR_A_DQS#0

DDR_A_DQS0

12 14

DDR_A_D6

DDR_A_D7

18 20

DDR_A_D12

DDR_A_D13

24 26

DDR_A_DM1

SM_DRAMRST#

30 32

DDR_A_D14

DDR_A_D15

36 38

DDR_A_D20

DDR_A_D21

42 44

DDR_A_DM2

46 48

DDR_A_D22

DDR_A_D23

52 54

DDR_A_D28

DDR_A_D29

58 60

DDR_A_DQS#3

DDR_A_DQS3

64 66

DDR_A_D30

68 70 72

DDR_A_CKE1

74 76

DDR_A_MA15

A15 A14

A11

A7 A6

A4 A2

80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_A_MA14 DDR_A_MA11

DDR_A_MA7 DDR_A_MA6

DDR_A_MA4 DDR_A_MA2

DDR_A_MA0 DDR_A_CLK1

DDR_A_CLK1# DDR_A_BS1

DDR_A_RAS# DDR_A_CS0#

DDR_A_ODT0 DDR_A_ODT1

DDR_VREF_CA_DIMMA DDR_A_D36

DDR_A_D37 DDR_A_DM4 DDR_A_D38

DDR_A_D39 DDR_A_D44DDR_A_D44

DDR_A_D45 DDR_A_DQS#5

DDR_A_DQS5 DDR_A_D46

DDR_A_D47 DDR_A_D52

DDR_A_D53 DDR_A_DM6 DDR_A_D54

DDR_A_D55 DDR_A_D60

DDR_A_D61 DDR_A_DQS#7

DDR_A_DQS7 DDR_A_D62

DDR_A_D63 PM_EXTTS#0_1

SMBDATA SMBCLK

+0.75VS

+1.5V

R56

@ R56

1K_0402_5%~D

1 2

DDR_A_CKE1 <7>

DDR_A_CLK1 <7> DDR_A_CLK1# <7>

DDR_A_BS1 <7> DDR_A_RAS# <7>

DDR_A_CS0# <7>

DDR_A_ODT1 <7>

R1056 0_0402_5%~DR1056 0_0402_5%~D

1 2

C230

2.2U_0603_6.3V4Z~D

PM_EXTTS#0_1 <6,12>

SMBDATA <12,13,14,16> SMBCLK <12,13,14,16>

SM_DRAMRST# <6,12>

+V_DDR3_DIMMA_REF2

C220

0.1U_0402_16V4Z~D

DDR3 SO-DIMM A Standard Type

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

11 57Monday, September 21, 2009

M1 Circuit

1K_0402_1%~D

D D

+V_DDR3_DIMMB_REF

M2 Circuit

C C

B B

10U_0805_6.3V6M~D

A A

C156

@C156

1U_0402_6.3V4Z~D

PCH_SMBCLK PCH_SMBDATA

C172

10U_0805_6.3V6M~D

Layout Note: Place near JDIMM2.203 & JDIMM2.204

C1018

1U_0603_10V4Z~D

+1.5V

R1230

+V_DDR3_DIMMB_REF

R1231

R1231 1K_0402_1%~D

1K_0402_1%~D

1 3

Q44

BSS138_SOT23~D@

+3V

@U8

2 3

ISL90728WIE627Z-TK_SC70-6

Layout Note: Place near JDIMM2

+1.5V

10U_0805_6.3V6M~D

C188

+0.75VS

C206

1U_0603_10V4Z~D

C282

C283

1U_0603_10V4Z~D

+V_DDR3_DIMMB_REF

@ R321

1 2

VDD

GND

SDA

SCL

10U_0805_6.3V6M~D

C173

10U_0805_6.3V6M~D

C1019

1U_0603_10V4Z~D

R321 100K_0402_5%~D

100K_0402_5%~D

6 5 4

C207

C189

10U_0805_6.3V6M~D

C298

10U_0805_6.3V6M~D

2008/9/8 #400755 Calpella Clarksfield DDR3 SO-DIMM VREFDQ Platform Design Guide Change Details

DDR_RST_GATE <6,11,20>

H_DIMMB_REF <5>

+1.5V

R196

@R196

12.1K_0402_1%~D

VREF_RW_POT1

R197

@R197

12.1K_0402_1%~D

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

0.1U_0402_16V4Z~D

C1047

+5VALW

VREF_OPAMP_POT1

PP_S4GT<11>

C1048

0.1U_0402_16V4Z~D

@U46B

0.1U_0402_16V4Z~D

DDR_B_DQS#[0..7]<7>

DDR_B_D[0..63]<7>

DDR_B_DM[0..7]<7> DDR_B_DQS[0..7]<7> DDR_B_MA[0..15]<7>

PCH_SMBDATA<11,16,23>

U46B LM358DT_SO8

LM358DT_SO8

PP_S4GT

C1049

PCH_SMBCLK<11,16,23>

R193

@R193

1 2

2.2_0402_5%~D

2.2_0402_5%~D R194

@ R194

10_0402_5%~D

C1050

0.1U_0402_16V4Z~D

+V_DDR3_DIMMB_REF

H_DIMMB_REF<5>

PCH_SMBCLK PCH_SMBDATA

VREF_POT1_R

PP_S4GT_Q_1

Q49

2N7002LT1G_SOT23-3

C198

C198 330U_D2_2V_Y~OK

330U_D2_2V_Y~OK

VREF_POT1_R

C128

C128 1U_0402_6.3V4Z~D

1U_0402_6.3V4Z~D @

M1 Circuit

R166 0_0402_5%~DR166 0_0402_5%~D

1 2

M3 Circuit

R165 0_0402_5%~D@R165 0_0402_5%~D@

1 2

R186 0_0402_5%~D@R186 0_0402_5%~D@

1 2

C110

2.2U_0805_16V4Z~D

DDR_B_BS2<7>

DDR_B_BS0<7>

DDR_B_WE#<7>

DDR_B_CAS#<7> DDR_B_ODT0 <7>

DDR_B_CS1#<7>

+3VS

C1020

2.2U_0603_6.3V4Z~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

VREF_DQB

DDR_B_D0 DDR_B_D1

DDR_B_DM0 DDR_B_D2

DDR_B_D3 DDR_B_D8

DDR_B_D9 DDR_B_DQS#1

C122

0.1U_0402_16V4Z~D

DDR_B_CLK0<7> DDR_B_CLK0#<7>

C277

0.1U_0402_16V4Z~D

DDR_B_DQS1 DDR_B_D10

DDR_B_D11 DDR_B_D16

DDR_B_D17 DDR_B_DQS#2

DDR_B_DQS2 DDR_B_D18

DDR_B_D19 DDR_B_D24

DDR_B_D25 DDR_B_DM3 DDR_B_D26

DDR_B_D27

DDR_B_BS2 DDR_B_MA12

DDR_B_MA9 DDR_B_MA8

DDR_B_MA5 DDR_B_MA3

DDR_B_MA1 DDR_B_CLK0

DDR_B_CLK0# DDR_B_MA10

DDR_B_BS0 DDR_B_WE#

DDR_B_CAS# DDR_B_MA13

DDR_B_CS1#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_DM5 DDR_B_D42

DDR_B_D43 DDR_B_D48

DDR_B_D49 DDR_B_DQS#6

DDR_B_DQS6 DDR_B_D50

DDR_B_D51 DDR_B_D56

DDR_B_D57 DDR_B_DM7 DDR_B_D58

DDR_B_D59

R1059 10K_0402_5%~DR1059 10K_0402_5%~D

1 2

R1082 10K_0402_5%~DR1082 10K_0402_5%~D

2009/07/29 2010/07/29

+1.5V

3 5 7

9 11 13 15 17 19 21 23 25 27

33 35

39 41

45 47 49 51 53 55 57 59

63 67

73 75 77 79 81 83 85 87 89 91 93 95 97 99

101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205

Compal Secret Data

Deciphered Date

JDIMM2

FOX_AS0A626-U8RN-7F

FOX_AS0A626-U8RN-7F CONN@

CONN@

VREF_DQ1VSS1 VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS129RESET# VSS1131VSS12 DQ10 DQ11 VSS1337VSS14 DQ16 DQ17 VSS1543VSS16 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS2261DQS#3 DM3 VSS2365VSS24 DQ26 DQ27 VSS2571VSS26

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6 DQ7

VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3 DQ30

DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

BA1

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA SCL

VTT2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78

A15

A14

82 84

A11

88 90

94 96

100 102 104 106 108 110 112 114

S0#

116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

+1.5V

DDR_B_D4 DDR_B_D5

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D6 DDR_B_D7

DDR_B_D12 DDR_B_D13

DDR_B_DM1 SM_DRAMRST#

DDR_B_D14 DDR_B_D15

DDR_B_D20 DDR_B_D21

DDR_B_DM2 DDR_B_D22

DDR_B_D23 DDR_B_D28

DDR_B_D29 DDR_B_DQS#3

DDR_B_DQS3 DDR_B_D30

DDR_B_D31

DDR_B_CKE1DDR_B_CKE0

DDR_B_MA15 DDR_B_MA14

DDR_B_MA11 DDR_B_MA7

DDR_B_MA6 DDR_B_MA4

DDR_B_MA2 DDR_B_MA0

DDR_B_CLK1 DDR_B_CLK1#

DDR_B_BS1 DDR_B_RAS#

DDR_B_CS0# DDR_B_ODT0

DDR_B_ODT1

DDR_VREF_CA_DIMMB

DDR_B_D36 DDR_B_D37

DDR_B_DM4 DDR_B_D38

DDR_B_D39 DDR_B_D44

DDR_B_D45 DDR_B_DQS#5

DDR_B_DQS5 DDR_B_D46

DDR_B_D47 DDR_B_D52

DDR_B_D53 DDR_B_DM6 DDR_B_D54

DDR_B_D55 DDR_B_D60

DDR_B_D61 DDR_B_DQS#7

DDR_B_DQS7 DDR_B_D62

DDR_B_D63 PM_EXTTS#0_1

SMBDATA SMBCLK

SM_DRAMRST# <6,11>

DDR_B_CKE1 <7>DDR_B_CKE0<7>

DDR_B_CLK1 <7> DDR_B_CLK1# <7>

DDR_B_BS1 <7> DDR_B_RAS# <7>

DDR_B_CS0# <7>

DDR_B_ODT1 <7>

R1058 0_0402_5%~DR1058 0_0402_5%~D

1 2

2.2U_0603_6.3V4Z~D

M1 Circuit

1K_0402_1%~D

PM_EXTTS#0_1 <6,11>

SMBDATA <11,13,14,16>

+0.75VS

SMBCLK <11,13,14,16>

R1249

+V_DDR3_DIMMB_REF2

C231

+1.5V

+V_DDR3_DIMMB_REF2

R1250

R1250 1K_0402_1%~D

1K_0402_1%~D

C221

0.1U_0402_16V4Z~D

+V_DDR3_DIMMB_REF2

DDR3 SO-DIMM B Standard Type

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

12 57Monday, September 21, 2009

+CLK_VDDSRC

L79

+1.05VS

1 1

CLK_BUF_DREF_96M<16> CLK_BUF_DREF_96M#<16>

2 2

3 3

CLK_BUF_PCIE_SATA<16> CLK_BUF_PCIE_SATA#<16>

CLK_BUF_CPU_DMI<16> CLK_BUF_CPU_DMI#<16>

L79 FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

C1051

C1051 10U_0805_10V4Z~D

10U_0805_10V4Z~D

CLK_BUF_DREF_96M CLK_BUF_DREF_96M#

CLK_BUF_PCIE_SATA

+CLK_VDD

Silego Have Internal Pull-Up

R627 10K_0402_5%~DR627 10K_0402_5%~D

+CLK_VDDSRC

R1140 10K_0402_5%~D

R634 10K_0402_5%~DR634 10K_0402_5%~D

1 2

C1052

10U_0805_10V4Z~D

0.1U_0402_16V4Z~D

Integrated 33ohm Resistor

R1004 0_0402_5%~DR1004 0_0402_5%~D

1 2

R1005 0_0402_5%~DR1005 0_0402_5%~D

1 2

R1006 0_0402_5%~DR1006 0_0402_5%~D

1 2

R1008 0_0402_5%~DR1008 0_0402_5%~D

1 2

R1010 0_0402_5%~DR1010 0_0402_5%~D

1 2

R1011 0_0402_5%~DR1011 0_0402_5%~D

1 2

Integrated 33ohm Resistor

H_STP_CPU#

REF_0/CPU_SEL

C1053

C979

0.1U_0402_16V4Z~D

+CLK_VDDSRC +CLK_VDD

+CLK_VDD

CLK_BUF_DREF_96M_R CLK_BUF_DREF_96M#_R

CLK_BUF_PCIE_SATA_R CLK_BUF_PCIE_SATA#_RCLK_BUF_PCIE_SATA#

CLK_BUF_CPU_DMI_RCLK_BUF_CPU_DMI CLK_BUF_CPU_DMI#_RCLK_BUF_CPU_DMI#

H_STP_CPU#

Clock Generator

U49

VDD_USB_48

VSS_48M

DOT_96

DOT_96#

VDD_27

27MHZ

27MHZ_SS

USB_48

VSS_27M

SATA

SATA#

VSS_SRC

SRC_1

SRC_1#

VDD_SRC_IO

CPU_STOP#

TGND

SLG8SP587VTR_QFN32_5X5

IDT: 9LRS3191AKLFT SILEGO: SLG8SP585

REF_0/CPU_SEL

CKPWRGD/PD#

+3VS

SCL SDA

VDD_REF

XTAL_IN

XTAL_OUT

VSS_REF

VDD_CPU

CPU_0

CPU_0#

VSS_CPU

CPU_1

CPU_1#

VDD_CPU_IO

VDD_SRC

L80

FBMA-L11-201209-221LMA30T_0805

C1065

C1065 10U_0805_10V4Z~D

10U_0805_10V4Z~D

+CLK_VDDSRC

32 31 30 29 28 27 26 25

24 23 22 21 20 19 18 17

SMBCLK SMBDATA REF_0/CPU_SEL

CLK_XTAL_IN CLK_XTAL_OUT

CK505_PWRGD

CLK_BUF_CPU_BCLK_R CLK_BUF_CPU_BCLK#_R

IDT Have Internal Pull-Down

CPU_1PIN 30 CPU_0

(Default)

0 133MHz

100MHz 100MHz

133MHz

+CLK_VDD

0.1U_0402_16V4Z~D

C1061

10U_0805_10V4Z~D

R633 33_0402_5%~DR633 33_0402_5%~D

1 2

R1007 0_0402_5%~DR1007 0_0402_5%~D

1 2

R1009 0_0402_5%~DR1009 0_0402_5%~D

1 2

Integrated 33ohm Resistor

+CLK_VDD

R631

R631 10K_0402_5%~D

10K_0402_5%~D

1 2

CK505_PWRGD

Q45

2N7002LT1G_SOT23-3

CLK_XTAL_IN

1M_0402_5%~D

CLK_XTAL_OUT

0.1U_0402_16V4Z~D

C1054

C1055

0.1U_0402_16V4Z~D

C1109

R1141

@R1141

C1056

0.1U_0402_16V4Z~D

10P_0402_50V8J~D

1 2

CLK_BUF_CPU_BCLK CLK_BUF_CPU_BCLK#

R632

R632 0_0402_5%~D

0_0402_5%~D

1 2

CLK_ENABLE# <55>

C1059 27P_0402_50V8J~DC1059 27P_0402_50V8J~D

14.31818MHz_20P_FSX8L14.318181M20FDB~OK

C1060 27P_0402_50V8J~DC1060 27P_0402_50V8J~D

C1057

VGATE <17,31,55>

C1058

0.1U_0402_16V4Z~D

SMBCLK <11,12,14,16>

SMBDATA <11,12,14,16>

CLK_BUF_ICH_14M <16>

CLK_BUF_CPU_BCLK <16> CLK_BUF_CPU_BCLK# <16>

4 4

Security Classification

2009/07/29 2010/07/29

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/07/29 2010/07/29

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

13 57Monday, September 21, 2009

FAN Control circuit

EN_DFAN1<31>

FAN_SPEED1<31>

0.1U_0402_16V4Z~D

EN_DFAN1

+3VS

R141

10K_0402_5%~D

C98

+FAN1_POWER

C77

10U_1206_16V4Z~D

C91

1000P_0402_50V7K~D

+5VS

40mil

+FAN1_POWER

1 2

C96 10U_1206_16V4Z~DC96 10U_1206_16V4Z~D U7

VEN

2 3 4

MOLEX_53261-0371~D

GND

VIN

GND GND

GND

VSET

RT9027BPS_SO8

JFAN1

33G

CONN@

4 5

Free Fall Sensor

+3VS

C1067

C1067 10U_0805_10V4Z~D

10U_0805_10V4Z~D

+3VS +3VS_ACL_IO

8 7 6 5

+3VS_ACL_IO

+3VS

ACCEL_INT#<19>

SMBDATA<11,12,13,16>

SMBCLK<11,12,13,16>

+3VS

1 2

R1135 10K_0402_5%~D

R1134

1 2

0_0603_5%~D

12 13 14

U50

DE351DLTR

VDD_IO

VDD

INT 1 INT 29GND

SDO SDA / SDI / SDO SCL / SPC

RSVD

DE351DLTR_LGA14_3X5

GND GND GND

2 4 5 10

3 11

C1066

0.1U_0402_16V4Z~D

+3VS

Must be placed in the center of the system.

P/N : SA000039C00 (S IC DE351DLTR LGA 14P MOTION SENSOR)

Power Button

for debug only

1 2

3 4

SWO1

SWO1 SMT1-05_4P

SMT1-05_4P

TOPBTN

1 2

SWO2

SMT1-05_4P

3 4

PWR_ON-OFF_BTN#

PWR_ON-OFF_BTN# <32>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/07/29 2010/07/29

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

14 57Monday, September 21, 2009

+RTCVCC

1 2

R46

R46 20K_0402_1%~D

20K_0402_1%~D

PCH_RTCRST#

RC Delay 18~25mS

close to RAM door

CMOS1@CMOS1

C15

1U_0603_10V6K~D

D D

+RTCVCC

close to RAM door

1 2

R36

R36 20K_0402_1%~D

20K_0402_1%~D

ME1 @ME1 @

C13

1U_0603_10V6K~D

1 2

32.768KHZ_12.5PF_Q13MC14610002

PCH_SRTCRST#

RC Delay 18~25mS

3 2

+RTCVCC

INTVRMEN - Integrated SUS 1.1V VRM Enable High - Enable Internal VRs

HDA for AUDIO

HDA_BITCLK_AUDIO<25>

HDA_SYNC_AUDIO<25> HDA_RST_AUDIO#<25>

HDA_SDOUT_AUDIO<25>

C C

HDA_BITCLK_AUDIO

1 2

R1083 33_0402_5%~DR1083 33_0402_5%~D

1 2

R1084 33_0402_5%~DR1084 33_0402_5%~D

1 2

R1085 33_0402_5%~DR1085 33_0402_5%~D

1 2

R1086 33_0402_5%~DR1086 33_0402_5%~D

TOUCHKEY_TINT<31,32>

10P_0402_50V8J~D

1 2

C1110

HDA_BITCLK_PCH HDA_SYNC_PCH HDA_RST_PCH# HDA_SDOUT_PCH

R1024 0_0402_5%~DR1024 0_0402_5%~D

1 2

GPIO33 pull down only for ME disable

C398

18P_0402_50V8J~D

OSC

C402

18P_0402_50V8J~D

R64 1M_0402_5%~DR64 1M_0402_5%~D

1 2

R51 330K_0402_5%~DR51 330K_0402_5%~D

1 2

PCH_SPKR<25>

HDA_SDIN0<25>

PCH_JTAG_TCK<23> PCH_JTAG_TMS<23>

PCH_JTAG_TDI<23>

PCH_JTAG_TDO<23>

PCH_JTAG_RST#<23>

PCH_RTCX1

4 1

10M_0402_5%~D

PCH_RTCX2

R1232 1K_0402_5%~D@R1232 1K_0402_5%~D@

1 2

R1100

PCH_RTCRST# PCH_SRTCRST# SM_INTRUDER# PCH_INTVRMEN

HDA_BITCLK_PCH HDA_SYNC_PCH PCH_SPKR HDA_RST_PCH#

HDA_SDOUT_PCH

PCH_JTAG_TCK

U47A

B13

RTCX1

D13

RTCX2

C14

RTCRST#

D17

SRTCRST#

A16

INTRUDER#

A14

INTVRMEN

A30

HDA_BCLK

D29

HDA_SYNC

SPKR

C30

HDA_RST#

G30

HDA_SDIN0

F30

HDA_SDIN1

E32

HDA_SDIN2

F32

HDA_SDIN3

B29

HDA_SDO

H32

HDA_DOCK_EN# / GPIO33

J30

HDA_DOCK_RST# / GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

TRST#

REV1.0

RTCIHDA

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

FWH4 / LFRAME#

LDRQ1# / GPIO23

LPC

SATA0RXN SATA0RXP SATA0TXN

SATA0TXP

SATA1RXN SATA1RXP SATA1TXN

SATA1TXP

SATA2RXN SATA2RXP SATA2TXN

SATA2TXP

SATA3RXN SATA3RXP SATA3TXN

SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN

SATA5TXP

SATAICOMPO

SATAICOMPI

LDRQ0#

SERIRQ

D33 B33 C32 A32

C34 A34

F34 AB9

AK7 AK6 AK11 AK9

AH6 AH5 AH9 AH8

AF11 AF9 AF7 AF6

AH3 AH1 AF3 AF1

AD9 AD8 AD6 AD5

AD3 AD1 AB3 AB1

AF16 AF15

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

LPC_FRAME#

SERIRQ

SATA_ITX_DRX_N0 SATA_ITX_DRX_P0

SATA_ITX_DRX_N1 SATA_ITX_DRX_P1

From PCH EDS 5.16, SATA port2 & 3 are not available in all sku.

SATA_ITX_DRX_N4 SATA_ITX_DRX_P4

SATA_ITX_DRX_N5 SATA_ITX_DRX_P5

SATA_COMP

LPC_AD0 <27,31> LPC_AD1 <27,31> LPC_AD2 <27,31> LPC_AD3 <27,31>

LPC_FRAME# <27,31>

SERIRQ <31>

C963 0.01U_0402_16V7K~DC963 0.01U_0402_16V7K~D C964 0.01U_0402_16V7K~DC964 0.01U_0402_16V7K~D

R139 37.4_0402_1%~OKR139 37.4_0402_1%~OK

1 2

SATA_IRX_DTX_N0 <29>

C9610.01U_0402_16V7K~D C9610.01U_0402_16V7K~D

1 2

C9620.01U_0402_16V7K~D C9620.01U_0402_16V7K~D

1 2

12 12

SATA_IRX_DTX_P0 <29> SATA_ITX_C_DRX_N0 <29> SATA_ITX_C_DRX_P0 <29>

SATA_IRX_DTX_N1 <29>

SATA_IRX_DTX_P1 <29> SATA_ITX_C_DRX_N1 <29> SATA_ITX_C_DRX_P1 <29>

SATA for HDD1

SATA for HDD2

R0.3 depop

1 2 1 2

C9650.01U_0402_16V7K~D C9650.01U_0402_16V7K~D C9660.01U_0402_16V7K~D C9660.01U_0402_16V7K~D

C9670.01U_0402_16V7K~D C9670.01U_0402_16V7K~D C9680.01U_0402_16V7K~D C9680.01U_0402_16V7K~D

+1.05VS

SATA_IRX_DTX_N4 <29>

SATA_IRX_DTX_P4 <29> SATA_ITX_C_DRX_N4 <29> SATA_ITX_C_DRX_P4 <29>

SATA_IRX_DTX_N5 <30>

SATA_IRX_DTX_P5 <30> SATA_ITX_C_DRX_N5 <30> SATA_ITX_C_DRX_P5 <30>

SATA for ODD

SATA for eSATA

R0.3 depop

PCH_SPI_CLK_1

+3VS

B B

A A

R1120

R1120 1K_0402_5%~D

1K_0402_5%~D

1 2 1 2

R115

R115 10K_0402_5%~D

10K_0402_5%~D

PCH_JTAG_TMS

PCH_JTAG_TDO

PCH_JTAG_TDI

PCH_JTAG_RST#

PCH_SPKR

SERIRQ

R1130 51_0402_1%~D@R1130 51_0402_1%~D@

1 2

R1101 200_0402_5%~DR1101 200_0402_5%~D

1 2

R1102 100_0402_1%~DR1102 100_0402_1%~D

1 2

R1131 51_0402_1%~D@R1131 51_0402_1%~D@

1 2

R1104 200_0402_5%~D R1104 200_0402_5%~D

1 2

R1105 100_0402_1%~DR1105 100_0402_1%~D

1 2

R1132 51_0402_1%~D@R1132 51_0402_1%~D@

1 2

R1106 200_0402_5%~DR1106 200_0402_5%~D

1 2

R1107 100_0402_1%~DR1107 100_0402_1%~D

1 2

R1133 51_0402_1%~D@R1133 51_0402_1%~D@

1 2

R1108 20K_0402_1%~DR1108 20K_0402_1%~D

1 2

R1109 10K_0402_5%~DR1109 10K_0402_5%~D

1 2

PCH_SPI_CS0#

PCH_SPI_MOSI_1 PCH_SPI_MISO_1 PCH_SPI_MISO

+3V

+1.05VS

2008 Intel MOW36/MOW50

TDO: Reserved on ES1 Sample Mount R1104, R1105 on ES2 Sample

MP mount R1130, R1131, R1132, R1133 and remove others

R584 0_0402_5%~DR584 0_0402_5%~D

1 2

R571 15_0402_5%~DR571 15_0402_5%~D

1 2

R575 15_0402_5%~DR575 15_0402_5%~D

1 2

R565 33_0402_5%~DR565 33_0402_5%~D

1 2

PCH_SPI_CLKPCH_SPI_CLK PCH_SPI_CS0#_R

PCH_SPI_MOSI

+3VS

BA2

SPI_CLK

AV3

SPI_CS0#

AY3

SPI_CS1#

AY1

SPI_MOSI

AV1

SPI_MISO

IBEXPEAK-M_FCBGA1071~D

R1110

1 2

3.3K_0402_5%~D

SPI JTAG

PCH_SPI_CS0# PCH_SPI_MISO_1

SPI_WP1#

SATALED#

SATA0GP / GPIO21 SATA1GP / GPIO19

U29

CS#

WP#

GND

MX25L1605AM2C-12G_SO8

VCC

HOLD#

SCLK

Y9 V1

PCH_SATALED#

+3VS

SPI_HOLD1#

PCH_SPI_CLK_1

PCH_SPI_MOSI_1

R129 10K_0402_5%~DR129 10K_0402_5%~D

1 2

PCH_GPIO21 <23> PCH_GPIO19 <23>

10K_0402_5%~D

R111

R11223.3K_0402_5%~D R11223.3K_0402_5%~D

+3VS

R82

R82 10K_0402_5%~D

10K_0402_5%~D

+3VS

R77 10K_0402_5%~D@R77 10K_0402_5%~D@

1 2

R116 10K_0402_5%~D@R116 10K_0402_5%~D@

1 2

+3VS

SPI Flash (16Mbit/2Mbyte)

Security Classification

PCH_SPI_MOSI

enable iTPM: SPI_MOSI High

R173 1K_0402_5%~D@R173 1K_0402_5%~D@

1 2

+3VS

PCH_JTAG_TCK

CRB 1.0 Change to 4.7K

R1111 4.7K_0402_5%~DR1111 4.7K_0402_5%~D

1 2

Security Classification

2009/07/29 2010/07/29

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/07/29 2010/07/29

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

401808

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

15 57Monday, September 21, 2009

MiniWWAN -->

MiniWLAN -->

D D

MiniWPAN -->

Card Reader -->

Express card -->

10/100/1G LAN -->

C C

MiniWWAN -->

MiniWLAN -->

MiniWPAN -->

Card Reader -->

Express card -->

B B

10/100/1G LAN -->

PCH_GPIO20 PCH_GPIO18

PCIE_IRX_WANTX_N1<27>

PCIE_IRX_WANTX_P1<27> PCIE_ITX_C_WANRX_N1<27> PCIE_ITX_C_WANRX_P1<27>

PCIE_IRX_WLANTX_N2<27>

PCIE_IRX_WLANTX_P2<27> PCIE_ITX_C_WLANRX_N2<27> PCIE_ITX_C_WLANRX_P2<27>

PCIE_IRX_WPANTX_N3<28>

PCIE_IRX_WPANTX_P3<28> PCIE_ITX_C_WPANRX_N3<28> PCIE_ITX_C_WPANRX_P3<28>

PCIE_IRX_CBTX_N4<30>

PCIE_IRX_CBTX_P4<30> PCIE_ITX_C_CBRX_N4<30> PCIE_ITX_C_CBRX_P4<30>

PCIE_IRX_EXPTX_N5<28> PCIE_IRX_EXPTX_P5<28>

PCIE_ITX_C_EXPRX_N5<28> PCIE_ITX_C_EXPRX_P5<28>

PCIE_IRX_GLANTX_N6<24>

PCIE_IRX_GLANTX_P6<24> PCIE_ITX_C_GLANRX_N6<24> PCIE_ITX_C_GLANRX_P6<24>

CLK_PCIE_WAN#<27> CLK_PCIE_WAN<27>

WWAN_CLKREQ#<27>

CLK_PCIE_WLAN#<27> CLK_PCIE_WLAN<27>

WLAN_CLKREQ#<27>

PCH_GPIO18<23>

CLK_PCIE_WPAN#<28> CLK_PCIE_WPAN<28>

WPAN_CLKREQ#<28>

PCH_GPIO20<23>

CLK_PCIE_CB#<30> CLK_PCIE_CB<30>

CB_CLKREQ#<30>

CLK_PCIE_EXPR#<28> CLK_PCIE_EXPR<28>

EXP_CLKREQ#<28>

CLK_PCIE_GLAN#<24> CLK_PCIE_GLAN<24>

GLAN_CLKREQ#<24>

R1112 10K_0402_5%~DR1112 10K_0402_5%~D

1 2

R1022 10K_0402_5%~DR1022 10K_0402_5%~D

1 2

C1021 0.1U_0402_16V7K~DC1021 0.1U_0402_16V7K~D C1022 0.1U_0402_16V7K~DC1022 0.1U_0402_16V7K~D

C1023 0.1U_0402_16V7K~DC1023 0.1U_0402_16V7K~D C1024 0.1U_0402_16V7K~DC1024 0.1U_0402_16V7K~D

C969 0.1U_0402_16V7K~DC969 0.1U_0402_16V7K~D C970 0.1U_0402_16V7K~DC970 0.1U_0402_16V7K~D

C971 0.1U_0402_16V7K~DC971 0.1U_0402_16V7K~D C972 0.1U_0402_16V7K~DC972 0.1U_0402_16V7K~D

C973 0.1U_0402_16V7K~DC973 0.1U_0402_16V7K~D C974 0.1U_0402_16V7K~DC974 0.1U_0402_16V7K~D

C1025 0.1U_0402_16V7K~DC1025 0.1U_0402_16V7K~D C1026 0.1U_0402_16V7K~DC1026 0.1U_0402_16V7K~D

R551 0_0402_5%~DR551 0_0402_5%~D

1 2

R550 0_0402_5%~DR550 0_0402_5%~D

1 2

R76 0_0402_5%~DR76 0_0402_5%~D

1 2

R1123 0_0402_5%~DR1123 0_0402_5%~D

1 2

R1124 0_0402_5%~DR1124 0_0402_5%~D

1 2

R93 0_0402_5%~DR93 0_0402_5%~D

1 2

R1012 0_0402_5%~DR1012 0_0402_5%~D

1 2

R1013 0_0402_5%~DR1013 0_0402_5%~D

1 2

R1014 0_0402_5%~DR1014 0_0402_5%~D

1 2

R1015 0_0402_5%~DR1015 0_0402_5%~D

1 2

R1016 0_0402_5%~DR1016 0_0402_5%~D

1 2

R1017 0_0402_5%~DR1017 0_0402_5%~D

1 2

R558 0_0402_5%~DR558 0_0402_5%~D

1 2

R563 0_0402_5%~DR563 0_0402_5%~D

1 2

R1018 0_0402_5%~DR1018 0_0402_5%~D

1 2

R1019 0_0402_5%~DR1019 0_0402_5%~D

1 2

R1020 0_0402_5%~DR1020 0_0402_5%~D

1 2

R1021 0_0402_5%~DR1021 0_0402_5%~D

1 2

+3VS

12 12

PCIE_IRX_WANTX_N1 PCIE_IRX_WANTX_P1 PCIE_ITX_WANRX_N1 PCIE_ITX_WANRX_P1

PCIE_IRX_WLANTX_N2 PCIE_IRX_WLANTX_P2 PCIE_ITX_WLANRX_N2 PCIE_ITX_WLANRX_P2

PCIE_IRX_WPANTX_N3 PCIE_IRX_WPANTX_P3 PCIE_ITX_WPANRX_N3 PCIE_ITX_WPANRX_P3

PCIE_IRX_CBTX_N4 PCIE_IRX_CBTX_P4 PCIE_ITX_CBRX_N4 PCIE_ITX_CBRX_P4

PCIE_IRX_EXPTX_N5 PCIE_IRX_EXPTX_P5 PCIE_ITX_EXPRX_N5 PCIE_ITX_EXPRX_P5

PCIE_IRX_GLANTX_N6 PCIE_IRX_GLANTX_P6 PCIE_ITX_GLANRX_N6 PCIE_ITX_GLANRX_P6

R_CLK_PCIE_WAN# R_CLK_PCIE_WAN

PCH_GPIO73

R_CLK_PCIE_WLAN# R_CLK_PCIE_WLAN

PCH_GPIO18

R_CLK_PCIE_WPAN# R_CLK_PCIE_WPAN

PCH_GPIO20

R_CLK_PCIE_CB# R_CLK_PCIE_CB

PCH_GPIO25

R_CLK_PCIE_EXPR# R_CLK_PCIE_EXPR

PCH_GPIO26

R_CLK_PCIE_GLAN# R_CLK_PCIE_GLAN

PCH_GPIO44

PCH_GPIO56

U47B

BG30

PERN1

BJ30

PERP1

BF29

PETN1

BH29

PETP1

AW30

PERN2

BA30

PERP2

BC30

PETN2

BD30

PETP2

AU30

PERN3

AT30

PERP3

AU32

PETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

PCIECLKRQ0# / GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

PCIECLKRQ1# / GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

PCIECLKRQ2# / GPIO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

PCIECLKRQ3# / GPIO25

AM51

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

PCIECLKRQ4# / GPIO26

AJ50

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

PCIECLKRQ5# / GPIO44

AK53

CLKOUT_PEG_B_N

AK51

CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ# / GPIO56

IBEXPEAK-M_FCBGA1071~D

REV1.0

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1ALERT# / GPIO74

SMBus

SML1DATA / GPIO75

PCI-E*

Link

Controller

PEG_A_CLKRQ# / GPIO47

PEG

CLKOUT_DP_N / CLKOUT_BCLK1_N

CLKOUT_DP_P / CLKOUT_BCLK1_P

From CLK BUFFER

CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P

CLKIN_PCILOOPBACK

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

Clock Flex

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK / GPIO58

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_BCLK_N CLKIN_BCLK_P

CLKIN_DOT_96N CLKIN_DOT_96P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

EC_LID_OUT#

B9 H14 C8

PCH_GPIO60

J14 C6 G8

PCH_GPIO74

M14

PCH_SML1CLK

E10

PCH_SML1DAT

G12

T13 T11 T9

PEG_CLKREQ#_R

AD43 AD45

AN4 AN2

AT1 AT3

AW24 BA24

AP3 AP1

F18 E18

AH13 AH12

P41

J42

AH51 AH53

XCLK_RCOMP

AF38

T45

P43

T42

N50

XTAL25_IN XTAL25_OUT

EC_LID_OUT# <31> PCH_SMBCLK <11,12,23> PCH_SMBDATA <11,12,23>

R43 10K_0402_5%~DR43 10K_0402_5%~D

1 2

CLK_PEG_VGA# <38> CLK_PEG_VGA <38>

CLK_CPU_DMI# <6> CLK_CPU_DMI <6>

CLK_BUF_CPU_DMI# <13> CLK_BUF_CPU_DMI <13>

CLK_BUF_CPU_BCLK# <13> CLK_BUF_CPU_BCLK <13>

CLK_BUF_DREF_96M# <13> CLK_BUF_DREF_96M <13>

CLK_BUF_PCIE_SATA# <13> CLK_BUF_PCIE_SATA <13>

CLK_BUF_ICH_14M <13>

CLK_PCI_FB <19>

R127 90.9_0402_1%~DR127 90.9_0402_1%~D

1 2

+1.05VS

1. Connect Directly XDCP of DDR3

2. Level Shift1, Pull-Up to +3VS CLOCK GEN, DIMM1, DIMM2, FFS

3. Level Shift2, Pull-Up to +3VS CPU & PCH XDP

R53

2.2K_0402_5%~D

+3V

R548

1M_0402_5%~D

2.2K_0402_5%~D

R52

2.2K_0402_5%~D

PCH_SMBCLK

R1147

2.2K_0402_5%~D

PCH_SML1CLK

R1149

2.2K_0402_5%~D

PCH_SML1DAT

1 3

C1027

C1027 0_0402_5%~D

0_0402_5%~D

1 2

Y2 25MHZ_20P

25MHZ_20P

1 2

C1028

C1028 27P_0402_50V8J~D

27P_0402_50V8J~D

+3VS

R638

4.7K_0402_5%~D

1 2

Q47

Q47 2N7002LT1G_SOT23-3

2N7002LT1G_SOT23-3

+3VS

R635

4.7K_0402_5%~D

1 2

Q46

Q46 2N7002LT1G_SOT23-3

2N7002LT1G_SOT23-3

+3VS

EC_SMB_CK2

Q57

Q57 2N7002LT1G_SOT23-3

2N7002LT1G_SOT23-3

+3VS

EC_SMB_DA2

Q58

Q58 2N7002LT1G_SOT23-3

2N7002LT1G_SOT23-3

R0.3 Modify

XTAL25_IN should be pulled to GND using a 0Ω resistor. (Calpella_Schematic_Checklist_Rev1.6)

SMBDATAPCH_SMBDATA

SMBCLK

+3VS

Note: remove 25MHz crystal for ES2 silicon

SMBDATA <11,12,13,14>

SMBCLK <11,12,13,14>

EC_SMB_CK2 <27,28,31,39>

EC_SMB_DA2 <27,28,31,39>

+3V

EC_LID_OUT# PCH_GPIO73

A A

PCH_GPIO60 PCH_GPIO25 PCH_GPIO26

PCH_GPIO74

PCH_GPIO44 PCH_GPIO56

R1113 10K_0402_5%~DR1113 10K_0402_5%~D

1 2

R81 10K_0402_5%~DR81 10K_0402_5%~D

1 2

R78 10K_0402_5%~DR78 10K_0402_5%~D

1 2

R1087 10K_0402_5%~DR1087 10K_0402_5%~D

1 2

R1023 10K_0402_5%~DR1023 10K_0402_5%~D

1 2

R84 10K_0402_5%~DR84 10K_0402_5%~D

1 2

R54 10K_0402_5%~DR54 10K_0402_5%~D

1 2

R95 10K_0402_5%~DR95 10K_0402_5%~D

1 2

+3VS

WWAN_CLKREQ# PCH_GPIO73

+3VS

CB_CLKREQ# PCH_GPIO25

1 2

R1203 10K_0402_5%~D

1 2

R1206 10K_0402_5%~D

1 2

R1209 10K_0402_5%~D

1 2

R1210 10K_0402_5%~D

Q64

2N7002LT1G_SOT23-3

Q67

2N7002LT1G_SOT23-3

+3VS +3VS

EXP_CLKREQ# PCH_GPIO26 GLAN_CLKREQ# PCH_GPIO44

1 2

R1204 10K_0402_5%~D

1 2

R1207 10K_0402_5%~D

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Q65

2N7002LT1G_SOT23-3

2009/07/29 2010/07/29

1 2

R1205 10K_0402_5%~D

1 2

R1208 10K_0402_5%~D

Compal Secret Data

Deciphered Date

Q66

2N7002LT1G_SOT23-3

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

16 57Monday, September 21, 2009

D D

+3VS

1 2

R110 10K_0402_5%~D

1 2

R1125 8.2K_0402_5%~D

1 2

R1211 10K_0402_5%~DR1211 10K_0402_5%~D

1 2

R1088 8.2K_0402_5%~DR1088 8.2K_0402_5%~D

1 2

R69 10K_0402_5%~D

C C

B B

A A

R69 10K_0402_5%~D

1 2

R1114 10K_0402_5%~DR1114 10K_0402_5%~D

1 2

R72 10K_0402_5%~DR72 10K_0402_5%~D

1 2

R55 1K_0402_5%~DR55 1K_0402_5%~D

10/2 Intel suggestion change to 10K

SYS_PWROK<23>

XDP_DBRESET# PM_CLKRUN#

PCH_GPIO72 PM_SLP_LAN#

SUS_PWR_ACK

EC_SWI#

ICH_PCIE_WAKE#

+3V

ACIN<25,31,39,48,49>

SYS_PWROK

SYS_PWROK VGATE

R66 10K_0402_5%~DR66 10K_0402_5%~D

CH751H-40PT_SOD323-2~D

R37 0_0402_5%~D@R37 0_0402_5%~D@

SYS_PWROK

ICH_PWROK

LAN_RST#

No used Integrated LAN, connecting LAN_RST# to GND

DMI_HTX_PRX_N0<5> DMI_HTX_PRX_N1<5> DMI_HTX_PRX_N2<5> DMI_HTX_PRX_N3<5>

DMI_HTX_PRX_P0<5> DMI_HTX_PRX_P1<5> DMI_HTX_PRX_P2<5> DMI_HTX_PRX_P3<5>

DMI_PTX_HRX_N0<5> DMI_PTX_HRX_N1<5> DMI_PTX_HRX_N2<5> DMI_PTX_HRX_N3<5>

DMI_PTX_HRX_P0<5> DMI_PTX_HRX_P1<5> DMI_PTX_HRX_P2<5> DMI_PTX_HRX_P3<5>

+1.05VS+3V

R590

49.9_0402_1%~D

1 2

XDP_DBRESET#<6,23>

R58 0_0402_5%~DR58 0_0402_5%~D R70 0_0402_5%~D@R70 0_0402_5%~D@

1 2

+3VS

1 2

R31 10K_0402_5%~DR31 10K_0402_5%~D

1 2

R41 10K_0402_5%~DR41 10K_0402_5%~D

1 2

R1115 10K_0402_5%~DR1115 10K_0402_5%~D

12 12

PM_DRAM_PWRGD<6>

SUS_PWR_ACK<31>

PBTN_OUT#<6,23,31>

D50

NC7SZ08P5X_NL_SC70-5

ICH_PWROK VGATE

DMI_COMP

XDP_DBRESET#

SYS_PWROK_R

SYS_PWROK

LAN_RST#

PCH_RSMRST#

SUS_PWR_ACK

PBTN_OUT#

PCH_ACIN

PCH_GPIO72

EC_SWI#

ICH_PWROK <31> VGATE <13,31,55>

U47C

BC24

DMI0RXN

BJ22

DMI1RXN

AW20

DMI2RXN

BJ20

DMI3RXN

BD24

DMI0RXP

BG22

DMI1RXP

BA20

DMI2RXP

BG20

DMI3RXP

BE22

DMI0TXN

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

SYS_RESET#

SYS_PWROK

B17

PWROK

MEPWROK

A10

LAN_RST#

DRAMPWROK

C16

RSMRST#

SUS_PWR_DN_ACK / GPIO30

PWRBTN#

ACPRESENT / GPIO31

BATLOW# / GPIO72

F14

RI#

IBEXPEAK-M_FCBGA1071~D

REV1.0

FDI_FSYNC0

DMI

FDI

DMI

FDI

FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Management

SLP_LAN# / GPIO29

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

FDI_INT

WAKE#

SLP_S4#

SLP_S3#

SLP_M#

TP23

PMSYNCH

BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12

BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12

BJ14 BF13 BH13 BJ12 BG14

ICH_PCIE_WAKE#

J12

PM_CLKRUN#

PCH_GPIO61

PCH_GPIO62

SLP_S5#

P12

PM_SLP_M#

PM_SLP_DSW#

BJ10

PM_SLP_LAN#

2009/07/29 2010/07/29

ICH_PCIE_WAKE# <24,27,28,31>

PAD

PM_SLP_S4# <11>

SLP_S3# <31>

PAD

H_PM_SYNC <6>

Compal Secret Data

Deciphered Date

EC_TX_P80_DATA<27,31>

R1234

PM_SLP_S4# SLP_S5#

R30 0_0402_5%~D

PCH_RSMRST#

R32

R32 10K_0402_5%~D

10K_0402_5%~D

+3V

C1125

0_0402_5%~D

Q50

Q50 MMBT3906_SOT23-3

MMBT3906_SOT23-3

123

R27 4.7K_0402_5%~DR27 4.7K_0402_5%~D

1 2

BAV99DW-7_SOT363

4 5

BAV99DW-7_SOT363

Title

Size Document Number Rev

Custom

Date: Sheet

1 2

0.1U_0402_10V6K~D

U62

IN1

IN2

74AHC1G08GW_SOT353-5~D

R1233 0_0402_5%~D

EC_RSMRST# <31>

1 2

D3A

D3B

R39

2.2K_0402_5%~D

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

PM_SLP_S5# <31>

+3V

17 57Monday, September 21, 2009

+ 37 hidden pages

Compal LA-5155P NAT02, Studio 1749 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual