COMPAL LA-5155P Schematics

A

1 1

B

C

D

E

Compal Confidential

2 2

NAT02 M/B Schematics Document

Intel Clarksfield Processor with DDRIII + Ibex Peak-M + Madison Pro

3 3

2009-08-20

REV:0.1

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/08/20 2010/08/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

A

of

157Monday, September 21, 2009

E

5

Block Diagram Compal confidential Model : NAT02

D D

CRT CONN

+5VS

P.34

FFS

+3VS

VGA

P.13

AMD

LVDS CONN

+LCDVDD +3.3V_ALW

P.34

DP CONN

+5VS

P.36

HDMI CONN

+5VS

C C

P.35

LVDS

DPB

DPA

To Card-reader subboard

8 IN 1 CONN

+3VS

IEEE1394

+3VS +1.8VS

CardBus

OZ888GS0

Madison Pro

29 x 29 mm

VRAM 64Mx16

P.29

4

FAN

+5VS +3VS

+1.1VS

P.37,38,39,40,41

P.42,43

P.13

PCI-E 2.0x16

5GT/s PER LANE

100MHz

PEG(DIS)

100MHz

PCI-Express x 8 (ABD PCIE1 2.5GT/S CKD PCIE1/2 2.5/5GT/S)

3

Intel Arrandale/ Clarksfield (DIS)

+CPU_CORE +1.1VS_VTT

Processor

rPGA988A

page 4,5,6,7,8,9

DMI x4

100MHz

1GB/s x4

Intel

Ibex Peak-M

+1.05VS

PCH

page 14,15,16,17 18,19,20,21,22

LPC BUS

+3VS 33MHz

IDT: 9LRS3199AKLFT SILEGO: SLG8SP587

133/120/100/96/14.318MHZ to PCH 48MHZ to CardReader

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 800/1066/1333

6.4G/8.5G/10.6G

100M/133M/166M(CFD)

USBx14 SATA x 6

(GEN1 1.5GT/S ,GEN2 3GT/S)

HD Audio

3.3V 48MHz 100MHz

3.3V 24MHz

SPI

SPI ROM x1

2MB

page 14

2

Clock Generator

Right Front Side.

Right behind side.

page 12

PCH XDP

page 22

DDRIII-DIMM X2

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8

+1.5V +0.75VS

USB Port X1

+5V_ALW

USB Port1 X1

+5V_ALW

Bluetooth

Touch Screen

Camera

P.10,11

P.29

P.31

P.29

Charge USB/E-SATA Ports X1

port 5

+5VALW

1

CPU XDP

133MHz

page 05

To Card-reader subboard

To Single USB subboard

P.29

Express Card

P.27

B B

RJ45

Mini Card 3

TV Tuner

+3VS

DC/DC Interface

A A

P.27 P.26 P.26

BATT IN

P.32 P.53

1.1VS_VTTPower Sequence

DC IN

5

RTL8111DL

+3VALW

Mini Card 2

WLAN

+3VS +1.5VS+1.5VS

USB[x]

P.50

P.45

P.23

PCIE1PCIE2PCIE3

Mini Card 1

WWAN

+3VS +1.5VS

USB[x]USB[x]

VCORE

CHARGER

1.5V/0.75V

P.52 P.49

3V/5V

GPU/1.1V 1.05V/1.8V

4

Int.KBD & BL

P.47P.46

P.48P.51

ENE KBC

KB926QFD3

+RTC_CELL +3VALW

P.30

SPI

SB3526

+3VS

To Cap Sensor subboard

page 31

Touch Pad

P.31P.31

Flash ROM 128KB

16Mx1sector

P.30

HeadPhone & MIC Jack

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/08/20 2010/08/20

Compal Secret Data

Deciphered Date

Azalia Codec

92HD73C

+3VS +VDDA

AMP

MAX4411x2

2

PCI Express BUS

P.24

port 4

E-ODD

+3VS +5VS

S-HDD-2

P.28 P.28 P.28

+5VS

AMP

MAX9736A

P.25

P.24

B+

AMP

MAX9736A

P.25

B+

Dig. MIC

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

401808

port 0port 1

S-HDD-1

+5VS

Speaker

Subwoofer

P.29

SCHEMATICS, MB A5155

of

257Monday, September 21, 2009

1

257Monday, September 21, 2009

A

Voltage Rails

Power Plane Description

VIN

1 1

2 2

B+ +CPU_CORE +GPU_CORE Core voltage for GPU ON OFFOFF +0.75VS 0.75V switched power rail for DDR terminator +1.05VS +1.1VS_VTT 1.1V switched power rail (1.05 for AUB CPU) ON OFF OFF +1.1VS 1.1V power rail for PCIE of GUP ON OFF OFF +1.5V 1.5V power rail for DDRIII ON ON OFF +1.5VS +1.8VS 1.8V switched power rail +3VALW 3.3V always on power rail +LAN_IO 3.3V power rail for LAN ON ON +3VS +5VALW +5VS B+_BIAS B+ always on power rail ON ON* +RTCVCC RTC power

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Adapter power supply (19V) AC or battery power rail for power circuit. Core voltage for CPU

1.05V switched power rail for PCH

1.5V switched power rail

3.3V switched power rail 5V always on power rail 5V switched power rail

B

S1 S3 S5

N/A N/A N/A

ON

ON OFF ON OFF OFF

ON OFF OFF ON ON

ON ON

N/AN/AN/A OFF

OFF

OFF ON ON*

ON* OFF

OFF ON

ON* OFFON

OFF

ONON

Board ID

X00 X01 X02 MP X00 X01 X02 MP

C

STATE

SIGNAL

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SLP_S1# SLP_S3#

SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH HIGH

LOW

HIGH

LOW LOW LOW LOW

D

HIGHHIGHHIGH

HIGH

LOWLOWLOW

HIGH

Board ID / SKU ID Table for AD channel

Vcc 3.3V +/- 5%

VGA

M96 M96 M96

M96 Madison Madison Madison Madison

100K +/- 1%Ra

Rb V min

AD_BID

0

8.2K +/- 1% 18K +/- 1% 33K +/- 1% 56K +/- 1% 100K +/- 1% 200K +/- 1%

NC

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

0 V

V typ

ON

OFF

V

AD_BID

ON ON

ON

OFF

ON

AD_BID

0 V 0.100 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

E

LOW

OFF

max

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupts

USB Port Table

EC SM Bus1 address

3 3

Device

Smart Battery

Address Address

0001 011X b

EC SM Bus2 address

Device

WWAN WLAN Express Card VGA thermal sensor

USB Port

0 1 2 3 4 5 6 7

Ibex SM Bus address

Device

Clock Generator (9LRS3191AKLFT, SLG8SP585)

DDR DIMM0 DDR DIMM1 Free Fall Sensor

4 4

CPU XDP PCH XDP XDCP_ISL90727 XDCP_ISL90728

A

Address

1101 0010b

1001 000Xb 1001 010Xb

0101 110Xb 0111 110Xb

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

8 9 10 11

2009/08/20 2010/08/20

C

Device USB&ESATA Reader/BD USB board WPAN WLAN WWAN NC NC Express Touch screen Bluetooth Camera

Compal Secret Data

Deciphered Date

D

BTO Option Table

BTO Item BOM Structure

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

401808

SCHEMATICS, MB A5155

of

357Monday, September 21, 2009

E

A

5

4

3

2

1

D D

SUSP#

TPS51117RGYR

(PU7)

SUSP#

ISL6268CAZ-T

(PU8)

ADAPTER

VR_ON

ISL62883HRZ-T (PU13)

BATTERY

B+

VGA_ON

SYSON

ISL6268CAZ-T (PU11)

ISL6268CAZ-T (PU10)

C C

SUSP#

CHARGER

SUSP#

TPS51117RGYR (PU6)

TPS51427

2500mA

15000mA

51000mA

20500mA

12800mA

5700mA

+1.8VS

+1.1VS_VTT

+CPU_CORE

+GPU_CORE

+1.5V

+1.05VS

SUSP#

0 Ohm

SI4800BDY (U25)

RT9025 (PU12)

RT9026 (PU10)

+1.05VS_CK505

8881mA

+1.5VS

913mA

+1.1VS

?mA

+0.75VS

(PU5)

+5VALW

RUNON

SI4800BDY

8400mA

B B

+5VS

(U22)

2000mA 8677mA160mA 20mA

USB_EN#

TPS2062ADR (U17)

+5V_CHGUSB

EN_EOL#

SI3456BDY (Q3)

+LAN_IO

EN_EOL#

RTL8111DL

FUSE

0 Ohm

+CRT_VCC

+AVDD_AUDIO

+5VS_KBL

(U9)

+LAN_VDD

+3VALW

SUSP

FBM-11-160808-601-T (L29)

+EC_AVCC

SUSP

SI4800BDY (U21)

+3VS

0 Ohm

+3VS_CK505

+DVDD_AUDIO

+3V_WLAN

VDDEN

SI2310BDS-T1-E3

(Q25)

+LCDVDD

EN_EOL#

SI2310BDS

(Q34)

+3VS_DELAY

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/08/20 2010/08/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

1

457Monday, September 21, 2009

A

of

457Monday, September 21, 2009

5

JCPU1A

DMI_PTX_HRX_N0<17> DMI_PTX_HRX_N1<17> DMI_PTX_HRX_N2<17> DMI_PTX_HRX_N3<17>

DMI_PTX_HRX_P0<17> DMI_PTX_HRX_P1<17> DMI_PTX_HRX_P2<17>

D D

C C

B B

DMI_PTX_HRX_P3<17>

DMI_HTX_PRX_N0<17> DMI_HTX_PRX_N1<17> DMI_HTX_PRX_N2<17> DMI_HTX_PRX_N3<17>

DMI_HTX_PRX_P0<17> DMI_HTX_PRX_P1<17> DMI_HTX_PRX_P2<17> DMI_HTX_PRX_P3<17>

R2071K_0402_5%~D R2071K_0402_5%~D

12

CheckList0.8 1.22 Auburndale Graphics Disable

A24

DMI_RX#[0]

C23

DMI_RX#[1]

B22

DMI_RX#[2]

A21

DMI_RX#[3]

B24

DMI_RX[0]

D23

DMI_RX[1]

B23

DMI_RX[2]

A22

DMI_RX[3]

D24

DMI_TX#[0]

G24

DMI_TX#[1]

F23

DMI_TX#[2]

H23

DMI_TX#[3]

D25

DMI_TX[0]

F24

DMI_TX[1]

E23

DMI_TX[2]

G23

DMI_TX[3]

E22

FDI_TX#[0]

D21

FDI_TX#[1]

D19

FDI_TX#[2]

D18

FDI_TX#[3]

G21

FDI_TX#[4]

E19

FDI_TX#[5]

F21

FDI_TX#[6]

G18

FDI_TX#[7]

D22

FDI_TX[0]

C21

FDI_TX[1]

D20

FDI_TX[2]

C18

FDI_TX[3]

G22

FDI_TX[4]

E20

FDI_TX[5]

F20

FDI_TX[6]

G19

FDI_TX[7]

F17

FDI_FSYNC[0]

E17

FDI_FSYNC[1]

C17

FDI_INT

F18

FDI_LSYNC[0]

D17

FDI_LSYNC[1]

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9 CONN@

CONN@

DMI Intel(R) FDI

PCI EXPRESS -- GRAPHICS

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RBIAS PEG_RX#[0]

PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

4

B26 A26 B27 A25

PEG_GTX_C_HRX_N0

K35

PEG_GTX_C_HRX_N1

J34

PEG_GTX_C_HRX_N2

J33

PEG_GTX_C_HRX_N3

G35

PEG_GTX_C_HRX_N4

G32

PEG_GTX_C_HRX_N5

F34

PEG_GTX_C_HRX_N6

F31

PEG_GTX_C_HRX_N7

D35

PEG_GTX_C_HRX_N8

E33

PEG_GTX_C_HRX_N9

C33

PEG_GTX_C_HRX_N10

D32

PEG_GTX_C_HRX_N11

B32

PEG_GTX_C_HRX_N12

C31

PEG_GTX_C_HRX_N13

B28

PEG_GTX_C_HRX_N14

B30

PEG_GTX_C_HRX_N15

A31

PEG_GTX_C_HRX_P0

J35

PEG_GTX_C_HRX_P1

H34

PEG_GTX_C_HRX_P2

H33

PEG_GTX_C_HRX_P3

F35

PEG_GTX_C_HRX_P4

G33

PEG_GTX_C_HRX_P5

E34

PEG_GTX_C_HRX_P6

F32

PEG_GTX_C_HRX_P7

D34

PEG_GTX_C_HRX_P8

F33

PEG_GTX_C_HRX_P9

B33

PEG_GTX_C_HRX_P10

D31

PEG_GTX_C_HRX_P11

A32

PEG_GTX_C_HRX_P12

C30

PEG_GTX_C_HRX_P13

A28

PEG_GTX_C_HRX_P14

B29

PEG_GTX_C_HRX_P15

A30

PEG_HTX_GRX_N0

L33

PEG_HTX_GRX_N1

M35

PEG_HTX_GRX_N2

M33

PEG_HTX_GRX_N3

M30

PEG_HTX_GRX_N4

L31

PEG_HTX_GRX_N5

K32

PEG_HTX_GRX_N6

M29

PEG_HTX_GRX_N7

J31

PEG_HTX_GRX_N8

K29

PEG_HTX_GRX_N9

H30

PEG_HTX_GRX_N10

H29

PEG_HTX_GRX_N11

F29

PEG_HTX_GRX_N12

E28

PEG_HTX_GRX_N13

D29

PEG_HTX_GRX_N14

D27

PEG_HTX_GRX_N15

C26

PEG_HTX_GRX_P0

L34

PEG_HTX_GRX_P1

M34

PEG_HTX_GRX_P2

M32

PEG_HTX_GRX_P3

L30

PEG_HTX_GRX_P4

M31

PEG_HTX_GRX_P5

K31

PEG_HTX_GRX_P6

M28

PEG_HTX_GRX_P7

H31

PEG_HTX_GRX_P8

K28

PEG_HTX_GRX_P9

G30

PEG_HTX_GRX_P10

G29

PEG_HTX_GRX_P11

F28

PEG_HTX_GRX_P12

E27

PEG_HTX_GRX_P13

D28

PEG_HTX_GRX_P14

C27

PEG_HTX_GRX_P15

C25

PEG_IRCOMP

EXP_RBIAS

R605

49.9_0402_1%~D

1 2

R613

750_0402_1%~D

1 2

C980 0.1U_0402_16V7K~DC980 0.1U_0402_16V7K~D

1 2

C451 0.1U_0402_16V7K~DC451 0.1U_0402_16V7K~D

1 2

C981 0.1U_0402_16V7K~DC981 0.1U_0402_16V7K~D

1 2

C982 0.1U_0402_16V7K~DC982 0.1U_0402_16V7K~D

1 2

C983 0.1U_0402_16V7K~DC983 0.1U_0402_16V7K~D

1 2

C984 0.1U_0402_16V7K~DC984 0.1U_0402_16V7K~D

1 2

C985 0.1U_0402_16V7K~DC985 0.1U_0402_16V7K~D

1 2

C986 0.1U_0402_16V7K~DC986 0.1U_0402_16V7K~D

1 2

C987 0.1U_0402_16V7K~DC987 0.1U_0402_16V7K~D

1 2

C988 0.1U_0402_16V7K~DC988 0.1U_0402_16V7K~D

1 2

C989 0.1U_0402_16V7K~DC989 0.1U_0402_16V7K~D

1 2

C990 0.1U_0402_16V7K~DC990 0.1U_0402_16V7K~D

1 2

C991 0.1U_0402_16V7K~DC991 0.1U_0402_16V7K~D

1 2

C992 0.1U_0402_16V7K~DC992 0.1U_0402_16V7K~D

1 2

C993 0.1U_0402_16V7K~DC993 0.1U_0402_16V7K~D

1 2

C977 0.1U_0402_16V7K~DC977 0.1U_0402_16V7K~D

1 2

C994 0.1U_0402_16V7K~DC994 0.1U_0402_16V7K~D

1 2

C995 0.1U_0402_16V7K~DC995 0.1U_0402_16V7K~D

1 2

C996 0.1U_0402_16V7K~DC996 0.1U_0402_16V7K~D

1 2

C997 0.1U_0402_16V7K~DC997 0.1U_0402_16V7K~D

1 2

C998 0.1U_0402_16V7K~DC998 0.1U_0402_16V7K~D

1 2

C999 0.1U_0402_16V7K~DC999 0.1U_0402_16V7K~D

1 2

C1000 0.1U_0402_16V7K~DC1000 0.1U_0402_16V7K~D

1 2

C1001 0.1U_0402_16V7K~DC1001 0.1U_0402_16V7K~D

1 2

C1002 0.1U_0402_16V7K~DC1002 0.1U_0402_16V7K~D

1 2

C444 0.1U_0402_16V7K~DC444 0.1U_0402_16V7K~D

1 2

C1003 0.1U_0402_16V7K~DC1003 0.1U_0402_16V7K~D

1 2

C1004 0.1U_0402_16V7K~DC1004 0.1U_0402_16V7K~D

1 2

C1005 0.1U_0402_16V7K~DC1005 0.1U_0402_16V7K~D

1 2

C1006 0.1U_0402_16V7K~DC1006 0.1U_0402_16V7K~D

1 2

C1007 0.1U_0402_16V7K~DC1007 0.1U_0402_16V7K~D

1 2

C1008 0.1U_0402_16V7K~DC1008 0.1U_0402_16V7K~D

1 2

3

PEG_GTX_C_HRX_N0 <38> PEG_GTX_C_HRX_N1 <38> PEG_GTX_C_HRX_N2 <38> PEG_GTX_C_HRX_N3 <38> PEG_GTX_C_HRX_N4 <38> PEG_GTX_C_HRX_N5 <38> PEG_GTX_C_HRX_N6 <38> PEG_GTX_C_HRX_N7 <38> PEG_GTX_C_HRX_N8 <38> PEG_GTX_C_HRX_N9 <38> PEG_GTX_C_HRX_N10 <38> PEG_GTX_C_HRX_N11 <38> PEG_GTX_C_HRX_N12 <38> PEG_GTX_C_HRX_N13 <38> PEG_GTX_C_HRX_N14 <38> PEG_GTX_C_HRX_N15 <38>

PEG_GTX_C_HRX_P0 <38> PEG_GTX_C_HRX_P1 <38> PEG_GTX_C_HRX_P2 <38> PEG_GTX_C_HRX_P3 <38> PEG_GTX_C_HRX_P4 <38> PEG_GTX_C_HRX_P5 <38> PEG_GTX_C_HRX_P6 <38> PEG_GTX_C_HRX_P7 <38> PEG_GTX_C_HRX_P8 <38> PEG_GTX_C_HRX_P9 <38> PEG_GTX_C_HRX_P10 <38> PEG_GTX_C_HRX_P11 <38> PEG_GTX_C_HRX_P12 <38> PEG_GTX_C_HRX_P13 <38> PEG_GTX_C_HRX_P14 <38> PEG_GTX_C_HRX_P15 <38>

PEG_HTX_C_GRX_N0 <38> PEG_HTX_C_GRX_N1 <38> PEG_HTX_C_GRX_N2 <38> PEG_HTX_C_GRX_N3 <38> PEG_HTX_C_GRX_N4 <38> PEG_HTX_C_GRX_N5 <38> PEG_HTX_C_GRX_N6 <38> PEG_HTX_C_GRX_N7 <38> PEG_HTX_C_GRX_N8 <38> PEG_HTX_C_GRX_N9 <38> PEG_HTX_C_GRX_N10 <38> PEG_HTX_C_GRX_N11 <38> PEG_HTX_C_GRX_N12 <38> PEG_HTX_C_GRX_N13 <38> PEG_HTX_C_GRX_N14 <38> PEG_HTX_C_GRX_N15 <38>

PEG_HTX_C_GRX_P0 <38> PEG_HTX_C_GRX_P1 <38> PEG_HTX_C_GRX_P2 <38> PEG_HTX_C_GRX_P3 <38> PEG_HTX_C_GRX_P4 <38> PEG_HTX_C_GRX_P5 <38> PEG_HTX_C_GRX_P6 <38> PEG_HTX_C_GRX_P7 <38> PEG_HTX_C_GRX_P8 <38> PEG_HTX_C_GRX_P9 <38> PEG_HTX_C_GRX_P10 <38> PEG_HTX_C_GRX_P11 <38> PEG_HTX_C_GRX_P12 <38> PEG_HTX_C_GRX_P13 <38> PEG_HTX_C_GRX_P14 <38> PEG_HTX_C_GRX_P15 <38>

H_DIMMA_REF<11> H_DIMMB_REF<12>

R1035

3.01K_0402_1%~D @

3.01K_0402_1%~D @ R1036

R1036

3.01K_0402_1%~D @

3.01K_0402_1%~D @ R1037

3.01K_0402_1%~D

3.01K_0402_1%~D R1038

3.01K_0402_1%~D

WW41 Recommend not pull down PCIE2.0 Jitter is over on ES1

1 2

@R1037

@

1 2

@R1038

@

1 2

R212

R212 0_0402_5%~D

0_0402_5%~D

@

1 2

@

1 2

R213

R213 0_0402_5%~D

0_0402_5%~D

2

JCPU1E

AP25

RSVD1

AL25

RSVD2

AL24

RSVD3

AL22

RSVD4

AJ33

RSVD5

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18

AM30 AM28 AP31

AL32

AL30 AM31 AN29 AM32 AK32 AK31 AK28

AJ28 AN30 AN32

AJ32

AJ29

AJ30 AK30

AG9 M27 L28

H17 G25 G17 E31 E30

H16

B19 A19

A20 B20

AC9 AB9

A34 A33

C35 B35

J17

U9 T9

C1 A3

J29 J28

RSVD6 RSVD7 RSVD8

(SA_DIMM_VREF)

RSVD9

(SB_DIMM_VREF)

RSVD10 RSVD11 RSVD12 RSVD13 RSVD14

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] RSVD_TP_86

RSVD15 RSVD16

RSVD17 RSVD18

RSVD19 RSVD20

RSVD21 RSVD22

RSVD_NCTF_23 RSVD_NCTF_24

RSVD26 RSVD27

RSVD_NCTF_28 RSVD_NCTF_29

RSVD_NCTF_30 RSVD_NCTF_31

RSVD_NCTF_37

RSVD_NCTF_40 RSVD_NCTF_41

RSVD_NCTF_42 RSVD_NCTF_43

RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57

RESERVED

RSVD32 RSVD33

RSVD34 RSVD35

RSVD36

RSVD38 RSVD39

RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53

RSVD58

RSVD_TP_59 RSVD_TP_60

KEY RSVD62 RSVD63 RSVD64 RSVD65

RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75

RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85

VSS

1

@

AJ13 AJ12

AH25 AK26

AL26 AR2

AJ26 AJ27

AP1 AT2

AT3 AR1

AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32

E15 F15 A2 D15 C15 AJ15 AH15

AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3

V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9

AP34

PAD

@

PAD

@

PAD

@

PAD

@

PAD

@

PAD

R649

R649 0_0402_5%~D

0_0402_5%~D

@

@ @

@

R648

R648 0_0402_5%~D

0_0402_5%~D

T97

T97 T98

T98

T99

T99 T100

T100 T101

T101

T102

12 12

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9 CONN@

CONN@

CFG0 - PCI-Express Configuration Select

*1:Single PEG 0:Bifurcation enabled

CFG3 - PCI-Express Static Lane Reversal

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/07/29 2010/07/29

Compal Secret Data

*1 :Normal Operation 0 :Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

CFG4 - Display Port Presence

*1:Disabled; No Physical Display Port attached to Embedded Display Port 0:Enabled; An external Display Port device is connected to the Embedded Display Port

*:Default

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

1

A

of

557Monday, September 21, 2009

5

JCPU1B

H_COMP3 H_COMP2 H_COMP1 H_COMP0

@

PAD

T5

R1039

1 2

0_0402_5%~D

R1042

1 2

0_0402_5%~D

R300

R300 0_0402_5%~D

0_0402_5%~D R263

R263 0_0402_5%~D

0_0402_5%~D R1043

R1043 0_0402_5%~D

0_0402_5%~D

R1045

1 2

0_0402_5%~D

R316

R316 0_0402_5%~D

0_0402_5%~D

R289

1 2

1.5K_0402_1%~D

T5

1 2

D D

H_PECI<20>

H_PROCHOT#<55>

H_THERMTRIP#<20>

H_PM_SYNC<17>

C C

H_CPUPWRGD<20>

PM_DRAM_PWRGD<17>

H_VTTPWRGD<53>

H_PWRGD_XDP H_PWRGD_XDP_R

PLT_RST#<19,23,24,27,28,30,31>

SKTOCC#_R

H_CATERR#

H_PECI_R

H_PROCHOT#

H_THERMTRIP#_R

H_CPURST#

H_PM_SYNC_R

H_CPUPWRGD_1

H_CPUPWRGD_0

PM_DRAM_PWRGD_R

PLT_RST#_R

12

R1052

R1052 750_0402_1%~D

750_0402_1%~D

JCPU1B

AT23

COMP3

AT24

COMP2

G16

COMP1

AT26

COMP0

AH24

SKTOCC#

AK14

CATERR#

AT15

PECI

AN26

PROCHOT#

AK15

THERMTRIP#

AP26

RESET_OBS#

AL15

PM_SYNC

AN14

VCCPWRGOOD_1

AN27

VCCPWRGOOD_0

AK13

SM_DRAMPWROK

AM15

VTTPWRGOOD

AM26

TAPPWRGOOD

AL14

RSTIN#

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9 CONN@

CONN@

4

MISC THERMAL

CLOCKS

DDR3

MISC

DDR3

MISC

PWR MANAGEMENT

JTAG & BPM

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PM_EXT_TS#[0] PM_EXT_TS#[1]

PRDY# PREQ#

TMS

TRST#

TDO

TDI_M

TDO_M

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

TCK

3

CLK_CPU_BCLK_R

A16

CLK_CPU_BCLK#_R

B16

CLK_CPU_ITP_R

AR30

CLK_CPU_ITP#_R

AT30

CLK_CPU_DMI_R

E16

CLK_CPU_DMI#_R

D16 A18

A17

F6 AL1

AM1 AN1

AN15 AP15

AT28 AP27

AN28 AP28 AT27

AT29

TDI

AR27 AR29 AP29

AN25

AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23

1 2

CPU_SM_DRAMRST# SM_RCOMP_0

SM_RCOMP_1 SM_RCOMP_2

PM_EXTTS#0 PM_EXTTS#1_R

XDP_PRDY# XDP_PREQ#

XDP_TCLK XDP_TMS XDP_TRST#

XDP_TDI_R XDP_TDO_R XDP_TDI_M XDP_TDO_M

XDP_DBR#_R

R609 0_0402_5%~DR609 0_0402_5%~D

1 2

R610 0_0402_5%~DR610 0_0402_5%~D

1 2

R655 0_0402_5%~DR655 0_0402_5%~D

1 2

R654 0_0402_5%~DR654 0_0402_5%~D

1 2

R606 0_0402_5%~DR606 0_0402_5%~D

1 2

R607 0_0402_5%~DR607 0_0402_5%~D

R310

100K_0402_5%~D

1 2

R1060 0_0402_5%~DR1060 0_0402_5%~D

1 2

R1044 0_0402_5%~DR1044 0_0402_5%~D

1 2

R1046 0_0402_5%~DR1046 0_0402_5%~D

1 2

R1047 0_0402_5%~DR1047 0_0402_5%~D

1 2

R1048 0_0402_5%~DR1048 0_0402_5%~D

1 2

R1049 0_0402_5%~DR1049 0_0402_5%~D

1 2

R1050 0_0402_5%~DR1050 0_0402_5%~D

1 2

R1051 0_0402_5%~DR1051 0_0402_5%~D

1 2

R284 0_0402_5%~DR284 0_0402_5%~D

1 2

CLK_CPU_XDP CLK_CPU_XDP#

G

2

@

13

D

S

D

S

Q36BSS138_SOT23~D

1 2 1 2 1 2

XDP_DBRESET#

XDP_OBS0XDP_OBS0_R XDP_OBS1XDP_OBS1_R XDP_OBS2XDP_OBS2_R XDP_OBS3XDP_OBS3_R XDP_OBS4XDP_OBS4_R XDP_OBS5XDP_OBS5_R XDP_OBS6XDP_OBS6_R XDP_OBS7XDP_OBS7_R

Q36BSS138_SOT23~D

R1121 0_0402_5%~D R1121 0_0402_5%~D

1 2

R1040 10K_0402_5%~DR1040 10K_0402_5%~D R288 10K_0402_5%~DR288 10K_0402_5%~D R1041 0_0402_5%~DR1041 0_0402_5%~D

CLK_CPU_BCLK <20> CLK_CPU_BCLK# <20>

CLK_CPU_DMI <16> CLK_CPU_DMI# <16>

+1.1VS_VTT

XDP_DBRESET# <17,23>

2

1.5V_PWRGD<52>

DDR_RST_GATE <11,12,20>

SM_DRAMRST# <11,12>

PM_EXTTS#0_1 <11,12>

R1136

1 2

10K_0402_5%~D

74AHC1G08GW_SOT353-5~D

JTAG MAPPING

Scan Chain (Default)

CPU Only

GMCH Only

1 2 1 2 1 2 1 2

1 2

1 2 1 2

@

1 2 1 2

1

R290

@R290

@

12

750_0402_1%~D

PM_DRAM_PWRGD_R

R1103

@R1103

@

1 2

+1.1VS_VTT

XDP_TDO

+3VALW

C1142

1 2

0.1U_0402_10V6K~D

5

U63

1

P

IN1

4

O

1.5K_0402_1%~D

2

XDP_TMS XDP_TDI_R XDP_PREQ# XDP_TCLK

XDP_TRST#

XDP_TDI_R XDP_TDI XDP_TDO_M

XDP_TDI_M XDP_TDO_R

1.5K_0402_1%~D

IN2

G

3

R657 51_0402_1%~D@R657 51_0402_1%~D@ R653 51_0402_1%~D@R653 51_0402_1%~D@ R656 51_0402_1%~D@R656 51_0402_1%~D@ R669 51_0402_1%~D@R669 51_0402_1%~D@

R651 51_0402_1%~DR651 51_0402_1%~D

R661 0_0402_5%~DR661 0_0402_5%~D R662 0_0402_5%~D@R662 0_0402_5%~D@

12

R663

R663 0_0402_5%~D

0_0402_5%~D

R667 0_0402_5%~D

R667 0_0402_5%~D R668 0_0402_5%~DR668 0_0402_5%~D

STUFF -> R653, R657, R662 NO STUFF -> R655, R660

STUFF -> R653, R655 NO STUFF -> R657, R660, R662

STUFF -> R660, R662 NO STUFF -> R653, R655, R657

WW51.4 CRB Board Rework/workaround- Rev 0.1 has changed the resistors in RSTIN#

B B

4

+1.1VS_VTT

PBTN_OUT#<17,23,31>

+1.1VS_VTT

C315

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D @

@

R365

R365 1K_0402_5%~D

1K_0402_5%~D

H_CPUPWRGD

1

2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2 1 2

R363 0_0402_5%~DR363 0_0402_5%~D

SMB_DATA_S3<23> SMB_CLK_S3<23>

Issued Date

+1.5V

12

R1054

1.1K_0402_1%~D

PM_DRAM_PWRGD_R

12

R1055

3K_0402_1%~D

A A

[Calpella] Platform – Design Guide Addendum / Update – Rev. 1.52

5

H_CATERR# H_PROCHOT# H_CPURST#

H_COMP0 H_COMP1 H_COMP2 H_COMP3

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

R1053 49.9_0402_1%~DR1053 49.9_0402_1%~D

1 2

R1061 68_0402_5%~DR1061 68_0402_5%~D

1 2

R1062 68_0402_5%~D@R1062 68_0402_5%~D@

1 2

R650 49.9_0402_1%~DR650 49.9_0402_1%~D

1 2

R234 49.9_0402_1%~DR234 49.9_0402_1%~D

1 2

R659 20_0402_1%~DR659 20_0402_1%~D

1 2

R658 20_0402_1%~DR658 20_0402_1%~D

1 2

R645 100_0402_1%~DR645 100_0402_1%~D

1 2

R646 24.9_0402_1%~DR646 24.9_0402_1%~D

1 2

R647 130_0402_1%~DR647 130_0402_1%~D

1 2

XDP_PREQ# XDP_PRDY#

XDP_OBS0 XDP_OBS1

XDP_OBS2 XDP_OBS3

XDP_OBS4 XDP_OBS5

XDP_OBS6 XDP_OBS7

H_PWRGOOD_R PBTN_OUT#_XDP

H_PWRGD_XDP

XDP_TCLK

2009/07/29 2010/07/29

3

XDP Connector

JP8

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

Compal Secret Data

SAMTE_BSH-030-01-L-D-ACONN@

Deciphered Date

GND1 OBSFN_C0 OBSFN_C1

GND3

OBSDATA_C0 OBSDATA_C1

GND5

OBSDATA_C2 OBSDATA_C3

GND7 OBSFN_D0 OBSFN_D1

GND9

OBSDATA_D0 OBSDATA_D1

GND11 OBSDATA_D2 OBSDATA_D3

GND13

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND15

TRST#

TMS

GND17

TD0

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56

TDI

58 60

2

H_RESET#_R

CLK_CPU_XDP CLK_CPU_XDP#

H_RESET#_R XDP_DBRESET#

XDP_TDO XDP_TRST# XDP_TDI XDP_TMS

R1063

R1063 1K_0402_5%~D

1K_0402_5%~D

1 2 1 2

R362

R362 0_0402_5%~D

0_0402_5%~D

1 2 1 2

Title

Size Document Number Rev

Custom

Date: Sheet

H_CPURST#

@

R1064

R1064 1K_0402_5%~D

1K_0402_5%~D

R1065

R1065 51_0402_1%~D

51_0402_1%~D

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

PCI_PLTRST# <19>

+1.1VS_VTT

Leakage Issue

+3VS +1.1VS_VTT

1

of

657Monday, September 21, 2009

A

5

JCPU1C

A10

C10

B10

D10

E10

F10

H10

G10

AH5 AF5 AK6 AK7 AF6 AG5

AJ7 AJ6

AJ10

AJ9 AL10 AK12

AK8

AL7 AK11

AL8

AN8 AM10 AR11

AL11

AM9

AN9

AT11

AP12 AM12 AN12 AM13

AT14

AT12

AL13 AR14

AP14

AC3 AB2

AE1 AB3 AE9

C7 A7

A8 D8

E6 E9

B7 E7 C6

G8 K7

G7

J10

M6 M8

K8 N8 P9

U7

F7

J8

J7 L7

L9 L6

JCPU1C

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

DDR_A_D[0..63]<11> DDR_A_DM[0..7]<11>

DDR_A_DQS#[0..7]<11>

DDR_A_DQS[0..7]<11>

DDR_A_MA[0..15]<11>

DDR_A_D0 DDR_A_D1

D D

C C

B B

DDR_A_BS0<11> DDR_A_BS1<11> DDR_A_BS2<11>

DDR_A_CAS#<11> DDR_A_RAS#<11>

DDR_A_WE#<11>

DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

DDR_A_CAS# DDR_A_RAS# DDR_A_WE#

SA_CK[0] SA_CK#[0] SA_CKE[0]

SA_CK[1] SA_CK#[1] SA_CKE[1]

SA_CS#[0] SA_CS#[1]

SA_ODT[0] SA_ODT[1]

SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

4

AA6 AA7 P7

Y6 Y5 P6

AE2 AE8

AD8 AF9

B9 D7 H7 M7 AG6 AM7 AN10 AN13

C9 F8 J9 N9 AH7 AK9 AP11 AT13

C8 F9 H9 M9 AH8 AK10 AN11 AR13

Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDR_A_CLK0 <11> DDR_A_CLK0# <11> DDR_A_CKE0 <11>

DDR_A_CLK1 <11> DDR_A_CLK1# <11> DDR_A_CKE1 <11>

DDR_A_CS0# <11> DDR_A_CS1# <11>

DDR_A_ODT0 <11> DDR_A_ODT1 <11>

3

DDR_B_D[0..63]<12>

DDR_B_DM[0..7]<12>

DDR_B_DQS#[0..7]<12>

DDR_B_DQS[0..7]<12> DDR_B_MA[0..15]<12>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

DDR_B_BS0<12> DDR_B_BS1<12> DDR_B_BS2<12>

DDR_B_CAS#<12> DDR_B_RAS#<12>

DDR_B_WE#<12>

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

DDR_B_CAS# DDR_B_RAS# DDR_B_WE#

AF3

AG1

AK1 AG4 AG3

AH4

AK3

AK4 AM6 AN2

AK5

AK2 AM4 AM3

AP3 AN5

AT4 AN6 AN4 AN3

AT5

AT6 AN7

AP6

AP8

AT9

AT7

AP9

AR10

AT10

AB1

AC5 AC6

B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3 G4 H6 G2 J6 J3 G1 G5 J2 J1 J5 K2 L3

M1

K5

K4 M4 N5

AJ3

AJ4

W5

R7

Y7

JCPU1D

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE#

2

SB_CK[0]

SB_CK#[0]

SB_CKE[0]

SB_CK[1]

SB_CK#[1]

SB_CKE[1]

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

DDR SYSTEM MEMORY - B

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

W8 W9 M3

V7 V6 M2

AB8 AD6

AC7 AD1

D4 E1 H3 K1 AH1 AL2 AR4 AT8

D5 F4 J4 L4 AH2 AL4 AR5 AR8

C5 E3 H4 M5 AG2 AL5 AP5 AR7

U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

1

DDR_B_CLK0 <12> DDR_B_CLK0# <12> DDR_B_CKE0 <12>

DDR_B_CLK1 <12> DDR_B_CLK1# <12> DDR_B_CKE1 <12>

DDR_B_CS0# <12> DDR_B_CS1# <12>

DDR_B_ODT0 <12> DDR_B_ODT1 <12>

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9 CONN@

CONN@

A A

Security Classification

2009/07/29 2010/07/29

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/07/29 2010/07/29

3

Compal Secret Data

Deciphered Date

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9 CONN@

CONN@

2

Compal Electronics, Inc.

Title

SCHEMATICS, MB A5155

Size Document Number Rev

B

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

401808

757Monday, September 21, 2009

of

1

of

A

5

JCPU1F

+CPU_CORE

WW15 MOW

48A Continuous 18A

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

D D

C C

B B

A A

AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26

VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

1.1V RAIL POWER

CPU CORE SUPPLY

POWER

CPU VIDS

SENSE LINES

Peak 21A

VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8

VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32

VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44

PSI#

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

PROC_DPRSLPVR

VTT_SELECT

ISENSE

VCC_SENSE

VSS_SENSE

VTT_SENSE

VSS_SENSE_VTT

4

AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15

AN33

AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34

H_VTTVID1

G15

H_VTTVID1 = low, 1.1V H_VTTVID1 = high, 1.05V

AN35

1 2

C1557 1000P_0402_50V7K~D@C1557 1000P_0402_50V7K~D@

VCCSENSE_R

AJ34

VSSSENSE_R

AJ35

B15

VSS_SENSE_VTT

A15

close to CPU side.

10U_0805_6.3V6M~D

1

C174

C183

2

10U_0805_6.3V6M~D

C222

22U_0805_6.3V6M~OK

10U_0805_6.3V6M~D

330U_X_2VM_R6M~OK

1

+

C1009

C1010

2

330U_X_2VM_R6M~OK

22U_0805_6.3V6M~OK

1

C240

2

IMVP_IMON <55>

R0.3 modify

R641 0_0402_5%~DR641 0_0402_5%~D

1 2

R642 0_0402_5%~DR642 0_0402_5%~D

1 2

R608 0_0402_5%~DR608 0_0402_5%~D

1 2

3

10U_0805_6.3V6M~D

1

C192

2

+1.1VS_VTT

1

+

C1011

@

2

330U_X_2VM_R6M~OK

+1.1VS_VTT

10U_0805_6.3V6M~D

1

C195

C203

2

10U_0805_6.3V6M~D

1

+

2

H_PSI# <55>

CPU_VID0 <55> CPU_VID1 <55> CPU_VID2 <55> CPU_VID3 <55> CPU_VID4 <55> CPU_VID5 <55> CPU_VID6 <55> H_DPRSLPVR <55>

H_VTTVID1 <53>

1

C211

2

10U_0805_6.3V6M~D

VTT Rail

Auburndale +1.1VS_VTT=1.05V Clarksfield +1.1VS_VTT=1.1V

1 2

R643 100_0402_1%~DR643 100_0402_1%~D

VCCSENSE VSSSENSE

1 2

VTT_SENSE <53>

R644 100_0402_1%~DR644 100_0402_1%~D

+1.1VS_VTT

1 2 1 2

+CPU_CORE

10U_0805_6.3V6M~D

1

C191

2

+CPU_CORE

470U_D2_2VM_R4.5M~OK

C1044

1

C159

2

CSC (Current Sense Configuration) 8/25

CPU_VID0

CPU_VID1

CPU_VID2

CPU_VID3

CPU_VID4

CPU_VID5

CPU_VID6

H_DPRSLPVR

H_PSI#

R1066 1K_0402_1%~DR1066 1K_0402_1%~D R1067 1K_0402_1%~D@R1067 1K_0402_1%~D@

R1068 1K_0402_1%~DR1068 1K_0402_1%~D R1069 1K_0402_1%~D@R1069 1K_0402_1%~D@

R1070 1K_0402_1%~DR1070 1K_0402_1%~D R1071 1K_0402_1%~D@R1071 1K_0402_1%~D@

R343 1K_0402_1%~D@R343 1K_0402_1%~D@ R1072 1K_0402_1%~DR1072 1K_0402_1%~D

R1073 1K_0402_1%~D@R1073 1K_0402_1%~D@ R1074 1K_0402_1%~DR1074 1K_0402_1%~D

R1075 1K_0402_1%~DR1075 1K_0402_1%~D R1076 1K_0402_1%~D@R1076 1K_0402_1%~D@

R1077 1K_0402_1%~D@R1077 1K_0402_1%~D@ R1078 1K_0402_1%~DR1078 1K_0402_1%~D

R347 1K_0402_1%~DR347 1K_0402_1%~D R1079 1K_0402_1%~D@R1079 1K_0402_1%~D@

R348 1K_0402_1%~D@R348 1K_0402_1%~D@ R1080 1K_0402_1%~DR1080 1K_0402_1%~D

+CPU_CORE

VCCSENSE <55>

VSSSENSE <55>

2

10U_0805_6.3V6M~D

1

C201

2

10U_0805_6.3V6M~D

+1.1VS_VTT

(Place these capacitors between inductor and socket on Bottom)

10U_0805_6.3V6M~D

4 x 470uF(4.5mohm@100kHz; 4.0mohm@SRF)

1

+

2

C251

470U_D2_2VM_R4.5M~OK

TOP side (under inductor)

10U_0805_6.3V6M~D

1

2

+CPU_CORE

1

2

C213

10U_0805_6.3V6M~D

C185

1

2

1

2

(Place these capacitors under CPU socket, top layer)

+CPU_CORE

22U_0805_6.3V6M~OK

1

C1034

2

22U_0805_6.3V6M~OK

(Place these capacitors on CPU cavity, Bottom Layer)

+CPU_CORE

22U_0805_6.3V6M~OK

1

C1039

2

22U_0805_6.3V6M~OK

1

+

2

+CPU-CORE Decoupling SPCAP,Polymer

C1012

470U_D2_2VM_R4.5M~OK

MLCC 0805 X5R

1

C245

C233

C194

C1035

C1040

(Place these capacitors on CPU cavity, Bottom Layer)

C245

2

10U_0805_6.3V6M~D

1

C199

2

10U_0805_6.3V6M~D

1

C1036

2

22U_0805_6.3V6M~OK

1

C1041

2

22U_0805_6.3V6M~OK

1

+

2

470U_D2_2VM_R4.5M~OK

1

2

1

2

C533

C,uF 4X470uF 4m ohm/4

16X22uF 16X10uF 3m ohm/16

10U_0805_6.3V6M~D

1

C190

2

1

C208

2

10U_0805_6.3V6M~D

22U_0805_6.3V6M~OK

1

C1037

2

22U_0805_6.3V6M~OK

1

C1042

2

1

+

2

470U_D2_2VM_R4.5M~OK

ESR, mohm

3m ohm/12

1

2

1

2

22U_0805_6.3V6M~OK

C200

10U_0805_6.3V6M~D

C214

1

C1062

2

1

C1063

2

1

+

C263

C263 @

@

2

1

2

1

2

22U_0805_6.3V6M~OK

Stuffing Option

2X470uF

10U_0805_6.3V6M~D

1

C232

C212

C223

C1038

C1043

470U_D2_2VM_R4.5M~OK

C232

2

1

C239

2

10U_0805_6.3V6M~D

1

2

1

2

1

+

C167

C167 @

@

2

Security Classification

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9 CONN@

CONN@

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/07/29 2010/07/29

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

1

A

of

857Monday, September 21, 2009

5

D D

C C

22U_0805_6.3V6M~OK

B B

22U_0805_6.3V6M~OK

+1.1VS_VTT

C179

+1.1VS_VTT

C177

4

1

2

1

2

1

C178

C178 22U_0805_6.3V6M~OK

22U_0805_6.3V6M~OK

2

1

C176

C176 22U_0805_6.3V6M~OK

22U_0805_6.3V6M~OK

2

JCPU1G

AT21

VAXG1

AT19

VAXG2

AT18

VAXG3

AT16

VAXG4

AR21

VAXG5

AR19

VAXG6

AR18

VAXG7

AR16

VAXG8

AP21

VAXG9

AP19

VAXG10

AP18

VAXG11

AP16

VAXG12

AN21

VAXG13

AN19

VAXG14

AN18

VAXG15

AN16

VAXG16

AM21

VAXG17

AM19

VAXG18

AM18

VAXG19

AM16

VAXG20

AL21

VAXG21

AL19

VAXG22

AL18

VAXG23

AL16

VAXG24

AK21

VAXG25

AK19

VAXG26

AK18

VAXG27

AK16

VAXG28

AJ21

VAXG29

AJ19

VAXG30

AJ18

VAXG31

AJ16

VAXG32

AH21

VAXG33

AH19

VAXG34

AH18

VAXG35

AH16

VAXG36

J24

VTT1_45

J23

VTT1_46

H25

VTT1_47

K26

VTT1_48

J27

VTT1_49

J26

VTT1_50

J25

VTT1_51

H27

VTT1_52

G28

VTT1_53

G27

VTT1_54

G26

VTT1_55

F26

VTT1_56

E26

VTT1_57

E25

VTT1_58

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9 CONN@

CONN@

3

15A

GRAPHICS

FDI PEG & DMI

VAXG_SENSE

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6]

GFX_VR_EN

GFX_DPRSLPVR

GFX_IMON

GRAPHICS VIDs

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6

3A

POWER

0.6A

VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18

DDR3 - 1.5V RAILS

VTT0_59 VTT0_60 VTT0_61 VTT0_62

VTT1_63 VTT1_64 VTT1_65

1.1V1.8V

VTT1_66 VTT1_67 VTT1_68

VCCPLL1 VCCPLL2 VCCPLL3

AR22 AT22

AM22 AP22 AN22 AP23 AM23 AP24 AN24

AR25 AT25 AM24

AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1

P10 N10 L10 K10

J22 J20 J18 H21 H20 H19

L26 L27 M26

R283 1K_0402_5%~DR283 1K_0402_5%~D

1 2

1U_0402_6.3V4Z~D

1

C193

C196

2

1U_0402_6.3V4Z~D

+1.1VS_VTT

1

C158

C158 22U_0805_6.3V6M~OK

22U_0805_6.3V6M~OK

2

+1.8VS_VCCSFR

1

C175

C182

1U_0402_6.3V4Z~D

2

1U_0402_6.3V4Z~D

2

1U_0402_6.3V4Z~D

1

C202

C209

2

1U_0402_6.3V4Z~D

1

C160

C160 10U_0805_6.3V6M~D

10U_0805_6.3V6M~D

2

2.2U_0603_6.3V6K~D

1

C168

C180

2

4.7U_0805_10V4Z~D

22U_0805_6.3V6M~OK

1

C216

C184

2

1U_0402_6.3V4Z~D

1

2

+1.5V_CPU_DDR

1

C224

2

22U_0805_6.3V6M~OK

R228

0.022_0805_1%~OK

1 2

C165

22U_0805_6.3V6M~OK

1

+1.5V

C1033

1 2

0.1U_0402_16V7K~D

C1143

1 2

0.1U_0402_16V7K~D

C1144

1 2

0.1U_0402_16V7K~D

C1145

1 2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D PJP12

PJP12 JUMP_43X118@

JUMP_43X118@

2

1

+

C250

2

330U_D2_2V_Y~OK

+1.8VS

112

PJP13

PJP13 JUMP_43X118@

JUMP_43X118@

112

PJP14

PJP14 JUMP_43X118@

JUMP_43X118@

112

2

A A

Security Classification

2009/07/29 2010/07/29

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/07/29 2010/07/29

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SCHEMATICS, MB A5155

Size Document Number Rev

Custom

401808

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

957Monday, September 21, 2009

1

A

of

5

JCPU1H

AT20

VSS1

AT17

VSS2

AR31

VSS3

AR28

VSS4

AR26

VSS5

AR24

VSS6

D D

C C

B B

AR23 AR20 AR17 AR15 AR12

AR9 AR6

AR3 AP20 AP17 AP13 AP10

AP7

AP4

AP2 AN34 AN31 AN23 AN20 AN17

AM29 AM27 AM25 AM20 AM17 AM14 AM11

AM8

AM5

AM2 AL34 AL31 AL23 AL20 AL17 AL12

AL9 AL6

AL3 AK29 AK27 AK25 AK20 AK17 AJ31 AJ23 AJ20 AJ17 AJ14 AJ11

AJ8

AJ5

AJ2

AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13

AH9 AH6 AH3

AG10

AF8 AF4 AF2

AE35

VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80

4

VSS

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30

3

JCPU1I

K27

VSS161

K9

VSS162

K6

VSS163

K3

VSS164

J32

VSS165

J30

VSS166

J21

VSS167

J19

VSS168

H35

VSS169

H32

VSS170

H28

VSS171

H26

VSS172

H24

VSS173

H22

VSS174

H18

VSS175

H15

VSS176

H13

VSS177

H11

VSS178

H8

VSS179

H5

VSS180

H2

VSS181

G34

VSS182

G31

VSS183

G20

VSS184

G9

VSS185

G6

VSS186

G3

VSS187

F30

VSS188

F27

VSS189

F25

VSS190

F22

VSS191

F19

VSS192

F16

VSS193

E35

VSS194

E32

VSS195

E29

VSS196

E24

VSS197

E21

VSS198

E18

VSS199

E13

VSS200

E11

VSS201

E8

VSS202

E5

VSS203

E2

VSS204

D33

VSS205

D30

VSS206

D26

VSS207

D9

VSS208

D6

VSS209

D3

VSS210

C34

VSS211

C32

VSS212

C29

VSS213

C28

VSS214

C24

VSS215

C22

VSS216

C20

VSS217

C19

VSS218

C16

VSS219

B31

VSS220

B25

VSS221

B21

VSS222

B18

VSS223

B17

VSS224

B13

VSS225

B11

VSS226

B8

VSS227

B6

VSS228

B4

VSS229

A29

VSS230

A27

VSS231

A23

VSS232

A9

VSS233

2

VSS

NCTF

VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7

AT35 AT1 AR34 B34 B2 B1 A35

1

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9 CONN@

CONN@

A A

Security Classification

2009/07/29 2010/07/29

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/07/29 2010/07/29

3

Compal Secret Data

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9 CONN@

CONN@

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

1

A

10 57Monday, September 21, 2009

of

5

M1 Circuit M3 Circuit

+1.5V

12

R170

1K_0402_1%~D

12

D D

+V_DDR3_DIMMA_REF

R169

R169 1K_0402_1%~D

1K_0402_1%~D

+V_DDR3_DIMMA_REF +V_DDR3_DIMMB_REF

M2 Circuit

+3V

1

C164

@C164

@

1U_0402_6.3V4Z~D

C C

Layout Note: Place near JDIMM1

B B

10U_0805_6.3V6M~D

Layout Note: Place near JDIMM1.203 & JDIMM1.204

A A

PCH_SMBCLK PCH_SMBDATA

PM_SLP_S4#<17>

10U_0805_6.3V6M~D

1

C204

C186

2

+0.75VS

1U_0603_10V4Z~D

2

C1015

1

1U_0603_10V4Z~D

2

+1.5V

U45

1

VDD

2

GND

3

SCL

ISL90727WIE627Z-TK_SC70-6@

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

10U_0805_6.3V6M~D

1

C171

C187

2

10U_0805_6.3V6M~D

1U_0603_10V4Z~D

2

C280

C1016

1

1U_0603_10V4Z~D

5

6

RH

5

RW

4

SDA

+5VALW

12

R226

@R226

@

100K_0402_5%~D

3

Q48B

@Q48B

@ 2N7002DW-7-F_SOT363-6~D

2N7002DW-7-F_SOT363-6~D

5

4

1

C170

2

10U_0805_6.3V6M~D

1

2

C1017

C281

10U_0805_6.3V6M~D

2

1

VREF_RW_POT0

PP_S4GT

10U_0805_6.3V6M~D

1

C205

2

1 2

0_0402_5%~D

+1.5V

12

R223

@R223

@

12.1K_0402_1%~D

12

R222

@R222

@

12.1K_0402_1%~D

1

2

0.1U_0402_16V4Z~D

DDR_A_DQS#[0..7]<7>

DDR_A_D[0..63]<7>

DDR_A_DM[0..7]<7> DDR_A_DQS[0..7]<7> DDR_A_MA[0..15]<7>

PCH_SMBCLK<12,16,23>

PCH_SMBDATA<12,16,23>

R1245

@

+5VALW

1 2

8

3

P

+

2

-

G

@U46A

@ LM358DT_SO8

LM358DT_SO8

4

VREF_OPAMP_POT0

PP_S4GT<12>

12

R230

@R230

@

1M_0402_5%~D

0.1U_0402_16V4Z~D

1

C1045

C1013

2

+V_DDR3_DIMMA_REF

C153

1

0

U46A

0.1U_0402_16V4Z~D

PCH_SMBCLK PCH_SMBDATA

R1229

1 2

0_0402_5%~D

@

1U_0402_6.3V4Z~D@

@R221

@

2.2_0402_5%~D

1 2

10_0402_5%~D

PP_S4GT

0.1U_0402_16V4Z~D

1

C1046

2

1 3

Q37

D

@

BSS138_SOT23~D

4

H_DIMMA_REF<5>

+V_DDR3_DIMMA_REF

+V_DDR3_DIMMB_REF2+V_DDR3_DIMMA_REF2

R1246

1 2

0_0402_5%~D

@

2008/9/8 #400755 Calpella Clarksfield DDR3 SO-DIMM VREFDQ Platform Design Guide Change Details

R221

1

2

R220

@R220

@

2

C1064

G

S

4

VREF_POT0_R

12

1

C163

C163 1U_0402_6.3V4Z~D

1U_0402_6.3V4Z~D @

@

2

PP_S4GT_Q_0

61

@

@ Q48A

Q48A 2N7002DW-7-F_SOT363-6~D

2N7002DW-7-F_SOT363-6~D

1

+

C197

C197 330U_D2_2V_Y~OK

330U_D2_2V_Y~OK

2

R313

@ R313

@

100K_0402_5%~D

1 2

VREF_POT0_R

M1 Circuit

1K_0402_1%~D

DDR_RST_GATE <6,12,20>

H_DIMMA_REF <5>

3

R178 0_0402_5%~D@R178 0_0402_5%~D@

1 2

R179 0_0402_5%~DR179 0_0402_5%~D

1 2

R227 0_0402_5%~D@R227 0_0402_5%~D@

1 2

1

C124

0.1U_0402_16V4Z~D

+1.5V

12

R1247

+V_DDR3_DIMMA_REF2

12

R1248

R1248 1K_0402_1%~D

1K_0402_1%~D

2.2U_0603_6.3V4Z~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C112

2.2U_0805_16V4Z~D

2

DDR_A_CKE0<7>

DDR_A_BS2<7>

DDR_A_CLK0<7> DDR_A_CLK0#<7>

DDR_A_BS0<7>

DDR_A_WE#<7>

DDR_A_CAS#<7> DDR_A_ODT0 <7>

DDR_A_CS1#<7>

+V_DDR3_DIMMA_REF2

+3VS

1

C1014

2

2009/07/29 2010/07/29

3

VREF_DQA

DDR_A_D0 DDR_A_D1

DDR_A_DM0 DDR_A_D2

DDR_A_D3 DDR_A_D8

DDR_A_D9 DDR_A_DQS#1

DDR_A_DQS1 DDR_A_D10

DDR_A_D11 DDR_A_D16

DDR_A_D17 DDR_A_DQS#2

DDR_A_DQS2 DDR_A_D18

DDR_A_D19 DDR_A_D24

DDR_A_D25 DDR_A_DM3 DDR_A_D26

DDR_A_D27 DDR_A_D31

DDR_A_CKE0

DDR_A_BS2 DDR_A_MA12

DDR_A_MA9 DDR_A_MA8

DDR_A_MA5 DDR_A_MA3

DDR_A_MA1 DDR_A_CLK0

DDR_A_CLK0# DDR_A_MA10

DDR_A_BS0 DDR_A_WE#

DDR_A_CAS# DDR_A_MA13

DDR_A_CS1#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5 DDR_A_D42

DDR_A_D43 DDR_A_D48

DDR_A_D49 DDR_A_DQS#6

DDR_A_DQS6 DDR_A_D50

DDR_A_D51 DDR_A_D56

DDR_A_D57 DDR_A_DM7 DDR_A_D58

DDR_A_D59

R1057 10K_0402_5%~DR1057 10K_0402_5%~D

1 2

1

C276

0.1U_0402_16V4Z~D

2

+1.5V +1.5V

11 13 15 17 19 21 23 25 27

33 35

39 41

45 47 49 51 53 55 57 59

63 67

69

73 75 77 79 81 83 85 87 89 91 93 95 97

99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201

12

R1081

R1081 10K_0402_5%~D

10K_0402_5%~D

Compal Secret Data

203 205

Deciphered Date

2

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS129RESET# VSS1131VSS12 DQ10 DQ11 VSS1337VSS14 DQ16 DQ17 VSS1543VSS16 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS2261DQS#3 DM3 VSS2365VSS24 DQ26 DQ27 VSS2571VSS26

CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1

G1

FOX_AS0A626-U4RN-7F

FOX_AS0A626-U4RN-7F CONN@

CONN@

2

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6 DQ7

VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3 DQ30

DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

BA1

RAS#

VDD14

S0#

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

SCL

VTT2

1

2

DDR_A_D4

4

DDR_A_D5

6 8

DDR_A_DQS#0

10

DDR_A_DQS0

12 14

DDR_A_D6

16

DDR_A_D7

18 20

DDR_A_D12

22

DDR_A_D13

24 26

DDR_A_DM1

28

SM_DRAMRST#

30 32

DDR_A_D14

34

DDR_A_D15

36 38

DDR_A_D20

40

DDR_A_D21

42 44

DDR_A_DM2

46 48

DDR_A_D22

50

DDR_A_D23

52 54

DDR_A_D28

56

DDR_A_D29

58 60

DDR_A_DQS#3

62

DDR_A_DQS3

64 66

DDR_A_D30

68 70 72

DDR_A_CKE1

74 76

DDR_A_MA15

78

A15 A14

A11

A7 A6

A4 A2

A0

G2

80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_A_MA14 DDR_A_MA11

DDR_A_MA7 DDR_A_MA6

DDR_A_MA4 DDR_A_MA2

DDR_A_MA0 DDR_A_CLK1

DDR_A_CLK1# DDR_A_BS1

DDR_A_RAS# DDR_A_CS0#

DDR_A_ODT0 DDR_A_ODT1

DDR_VREF_CA_DIMMA DDR_A_D36

DDR_A_D37 DDR_A_DM4 DDR_A_D38

DDR_A_D39 DDR_A_D44DDR_A_D44

DDR_A_D45 DDR_A_DQS#5

DDR_A_DQS5 DDR_A_D46

DDR_A_D47 DDR_A_D52

DDR_A_D53 DDR_A_DM6 DDR_A_D54

DDR_A_D55 DDR_A_D60

DDR_A_D61 DDR_A_DQS#7

DDR_A_DQS7 DDR_A_D62

DDR_A_D63 PM_EXTTS#0_1

SMBDATA SMBCLK

+0.75VS

+1.5V

R56

@ R56

@

1K_0402_5%~D

1 2

DDR_A_CKE1 <7>

DDR_A_CLK1 <7> DDR_A_CLK1# <7>

DDR_A_BS1 <7> DDR_A_RAS# <7>

DDR_A_CS0# <7>

DDR_A_ODT1 <7>

R1056 0_0402_5%~DR1056 0_0402_5%~D

1 2

1

C230

2.2U_0603_6.3V4Z~D

PM_EXTTS#0_1 <6,12>

SMBDATA <12,13,14,16> SMBCLK <12,13,14,16>

2

SM_DRAMRST# <6,12>

+V_DDR3_DIMMA_REF2

1

C220

0.1U_0402_16V4Z~D

2

DDR3 SO-DIMM A Standard Type

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

1

A

of

11 57Monday, September 21, 2009

M1 Circuit

1K_0402_1%~D

D D

+V_DDR3_DIMMB_REF

M2 Circuit

C C

B B

10U_0805_6.3V6M~D

A A

C156

@C156

@

1U_0402_6.3V4Z~D

PCH_SMBCLK PCH_SMBDATA

1

C172

2

10U_0805_6.3V6M~D

Layout Note: Place near JDIMM2.203 & JDIMM2.204

C1018

1U_0603_10V4Z~D

5

+1.5V

12

R1230

+V_DDR3_DIMMB_REF

12

R1231

R1231 1K_0402_1%~D

1K_0402_1%~D

1 3

Q44

D

BSS138_SOT23~D@

+3V

1

@U8

@

1

2

2 3

ISL90728WIE627Z-TK_SC70-6

Layout Note: Place near JDIMM2

+1.5V

10U_0805_6.3V6M~D

1

C188

+0.75VS

C206

2

1U_0603_10V4Z~D

C282

C283

2

1

1U_0603_10V4Z~D

5

+V_DDR3_DIMMB_REF

2

G

S

@ R321

@

1 2

U8

RH

VDD

RW

GND

SDA

SCL

10U_0805_6.3V6M~D

1

C173

2

10U_0805_6.3V6M~D

C1019

2

1

1U_0603_10V4Z~D

R321 100K_0402_5%~D

100K_0402_5%~D

6 5 4

1

C207

C189

2

10U_0805_6.3V6M~D

C298

1

10U_0805_6.3V6M~D

2

2008/9/8 #400755 Calpella Clarksfield DDR3 SO-DIMM VREFDQ Platform Design Guide Change Details

DDR_RST_GATE <6,11,20>

H_DIMMB_REF <5>

+1.5V

12

R196

@R196

@

12.1K_0402_1%~D

VREF_RW_POT1

12

R197

@R197

@

12.1K_0402_1%~D

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

0.1U_0402_16V4Z~D

1

C1047

2

+5VALW

8

5

P

+

6

-

G

4

VREF_OPAMP_POT1

PP_S4GT<11>

1

C1048

2

0.1U_0402_16V4Z~D

@U46B

@

0.1U_0402_16V4Z~D

DDR_B_DQS#[0..7]<7>

DDR_B_D[0..63]<7>

DDR_B_DM[0..7]<7> DDR_B_DQS[0..7]<7> DDR_B_MA[0..15]<7>

PCH_SMBDATA<11,16,23>

U46B LM358DT_SO8

LM358DT_SO8

7

0

PP_S4GT

1

C1049

2

4

PCH_SMBCLK<11,16,23>

R193

@R193

@

1 2

2.2_0402_5%~D

2.2_0402_5%~D R194

@ R194

@

10_0402_5%~D

2

G

1

C1050

2

0.1U_0402_16V4Z~D

4

+V_DDR3_DIMMB_REF

H_DIMMB_REF<5>

PCH_SMBCLK PCH_SMBDATA

VREF_POT1_R

12

1

2

PP_S4GT_Q_1

13

D

Q49

@

Q49

@

2N7002LT1G_SOT23-3

S

1

+

C198

C198 330U_D2_2V_Y~OK

330U_D2_2V_Y~OK

2

VREF_POT1_R

C128

C128 1U_0402_6.3V4Z~D

1U_0402_6.3V4Z~D @

@

3

M1 Circuit

R166 0_0402_5%~DR166 0_0402_5%~D

1 2

M3 Circuit

R165 0_0402_5%~D@R165 0_0402_5%~D@

1 2

R186 0_0402_5%~D@R186 0_0402_5%~D@

1 2

C110

2.2U_0805_16V4Z~D

DDR_B_BS2<7>

DDR_B_BS0<7>

DDR_B_WE#<7>

DDR_B_CAS#<7> DDR_B_ODT0 <7>

DDR_B_CS1#<7>

+3VS

C1020

2.2U_0603_6.3V4Z~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

VREF_DQB

DDR_B_D0 DDR_B_D1

DDR_B_DM0 DDR_B_D2

DDR_B_D3 DDR_B_D8

DDR_B_D9 DDR_B_DQS#1

1

C122

2

0.1U_0402_16V4Z~D

DDR_B_CLK0<7> DDR_B_CLK0#<7>

1

C277

0.1U_0402_16V4Z~D

2

DDR_B_DQS1 DDR_B_D10

DDR_B_D11 DDR_B_D16

DDR_B_D17 DDR_B_DQS#2

DDR_B_DQS2 DDR_B_D18

DDR_B_D19 DDR_B_D24

DDR_B_D25 DDR_B_DM3 DDR_B_D26

DDR_B_D27

DDR_B_BS2 DDR_B_MA12

DDR_B_MA9 DDR_B_MA8

DDR_B_MA5 DDR_B_MA3

DDR_B_MA1 DDR_B_CLK0

DDR_B_CLK0# DDR_B_MA10

DDR_B_BS0 DDR_B_WE#

DDR_B_CAS# DDR_B_MA13

DDR_B_CS1#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_DM5 DDR_B_D42

DDR_B_D43 DDR_B_D48

DDR_B_D49 DDR_B_DQS#6

DDR_B_DQS6 DDR_B_D50

DDR_B_D51 DDR_B_D56

DDR_B_D57 DDR_B_DM7 DDR_B_D58

DDR_B_D59

R1059 10K_0402_5%~DR1059 10K_0402_5%~D

1 2

R1082 10K_0402_5%~DR1082 10K_0402_5%~D

2009/07/29 2010/07/29

+1.5V

3 5 7

9 11 13 15 17 19 21 23 25 27

33 35

39 41

45 47 49 51 53 55 57 59

63 67

69

73 75 77 79 81 83 85 87 89 91 93 95 97 99

101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205

Compal Secret Data

Deciphered Date

JDIMM2

FOX_AS0A626-U8RN-7F

FOX_AS0A626-U8RN-7F CONN@

CONN@

2

VREF_DQ1VSS1 VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS129RESET# VSS1131VSS12 DQ10 DQ11 VSS1337VSS14 DQ16 DQ17 VSS1543VSS16 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS2261DQS#3 DM3 VSS2365VSS24 DQ26 DQ27 VSS2571VSS26

CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1

G1

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6 DQ7

VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3 DQ30

DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

BA1

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA SCL

VTT2

2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78

A15

80

A14

82 84

A11

86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100 102 104 106 108 110 112 114

S0#

116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

G2

+1.5V

DDR_B_D4 DDR_B_D5

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D6 DDR_B_D7

DDR_B_D12 DDR_B_D13

DDR_B_DM1 SM_DRAMRST#

DDR_B_D14 DDR_B_D15

DDR_B_D20 DDR_B_D21

DDR_B_DM2 DDR_B_D22

DDR_B_D23 DDR_B_D28

DDR_B_D29 DDR_B_DQS#3

DDR_B_DQS3 DDR_B_D30

DDR_B_D31

DDR_B_CKE1DDR_B_CKE0

DDR_B_MA15 DDR_B_MA14

DDR_B_MA11 DDR_B_MA7

DDR_B_MA6 DDR_B_MA4

DDR_B_MA2 DDR_B_MA0

DDR_B_CLK1 DDR_B_CLK1#

DDR_B_BS1 DDR_B_RAS#

DDR_B_CS0# DDR_B_ODT0

DDR_B_ODT1

DDR_VREF_CA_DIMMB

DDR_B_D36 DDR_B_D37

DDR_B_DM4 DDR_B_D38

DDR_B_D39 DDR_B_D44

DDR_B_D45 DDR_B_DQS#5

DDR_B_DQS5 DDR_B_D46

DDR_B_D47 DDR_B_D52

DDR_B_D53 DDR_B_DM6 DDR_B_D54

DDR_B_D55 DDR_B_D60

DDR_B_D61 DDR_B_DQS#7

DDR_B_DQS7 DDR_B_D62

DDR_B_D63 PM_EXTTS#0_1

SMBDATA SMBCLK

1

SM_DRAMRST# <6,11>

DDR_B_CKE1 <7>DDR_B_CKE0<7>

DDR_B_CLK1 <7> DDR_B_CLK1# <7>

DDR_B_BS1 <7> DDR_B_RAS# <7>

DDR_B_CS0# <7>

DDR_B_ODT1 <7>

R1058 0_0402_5%~DR1058 0_0402_5%~D

1 2

2.2U_0603_6.3V4Z~D

M1 Circuit

1K_0402_1%~D

PM_EXTTS#0_1 <6,11>

SMBDATA <11,13,14,16>

+0.75VS

SMBCLK <11,13,14,16>

R1249

+V_DDR3_DIMMB_REF2

1

C231

2

+1.5V

12

+V_DDR3_DIMMB_REF2

12

R1250

R1250 1K_0402_1%~D

1K_0402_1%~D

1

C221

0.1U_0402_16V4Z~D

2

+V_DDR3_DIMMB_REF2

DDR3 SO-DIMM B Standard Type

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

12 57Monday, September 21, 2009

1

of

A

B

C

D

E

F

G

H

+CLK_VDDSRC

L79

+1.05VS

1 1

CLK_BUF_DREF_96M<16> CLK_BUF_DREF_96M#<16>

2 2

3 3

CLK_BUF_PCIE_SATA<16> CLK_BUF_PCIE_SATA#<16>

CLK_BUF_CPU_DMI<16> CLK_BUF_CPU_DMI#<16>

L79 FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

1

C1051

C1051 10U_0805_10V4Z~D

10U_0805_10V4Z~D

2

CLK_BUF_DREF_96M CLK_BUF_DREF_96M#

CLK_BUF_PCIE_SATA

+CLK_VDD

Silego Have Internal Pull-Up

R627 10K_0402_5%~DR627 10K_0402_5%~D

+CLK_VDDSRC

R1140 10K_0402_5%~D

R634 10K_0402_5%~DR634 10K_0402_5%~D

1 2

@

1 2

12

1

C1052

10U_0805_10V4Z~D

2

0.1U_0402_16V4Z~D

Integrated 33ohm Resistor

R1004 0_0402_5%~DR1004 0_0402_5%~D

1 2

R1005 0_0402_5%~DR1005 0_0402_5%~D

1 2

R1006 0_0402_5%~DR1006 0_0402_5%~D

1 2

R1008 0_0402_5%~DR1008 0_0402_5%~D

1 2

R1010 0_0402_5%~DR1010 0_0402_5%~D

1 2

R1011 0_0402_5%~DR1011 0_0402_5%~D

1 2

Integrated 33ohm Resistor

H_STP_CPU#

REF_0/CPU_SEL

1

C1053

C979

0.1U_0402_16V4Z~D

2

+CLK_VDDSRC +CLK_VDD

+CLK_VDD

CLK_BUF_DREF_96M_R CLK_BUF_DREF_96M#_R

CLK_BUF_PCIE_SATA_R CLK_BUF_PCIE_SATA#_RCLK_BUF_PCIE_SATA#

CLK_BUF_CPU_DMI_RCLK_BUF_CPU_DMI CLK_BUF_CPU_DMI#_RCLK_BUF_CPU_DMI#

H_STP_CPU#

Clock Generator

U49

1

VDD_USB_48

2

VSS_48M

3

DOT_96

4

DOT_96#

5

VDD_27

6

27MHZ

7

27MHZ_SS

8

USB_48

9

VSS_27M

10

SATA

11

SATA#

12

VSS_SRC

13

SRC_1

14

SRC_1#

15

VDD_SRC_IO

16

CPU_STOP#

33

TGND

SLG8SP587VTR_QFN32_5X5

IDT: 9LRS3191AKLFT SILEGO: SLG8SP585

REF_0/CPU_SEL

CKPWRGD/PD#

+3VS

SCL SDA

VDD_REF

XTAL_IN

XTAL_OUT

VSS_REF

VDD_CPU

CPU_0

CPU_0#

VSS_CPU

CPU_1

CPU_1#

VDD_CPU_IO

VDD_SRC

L80

FBMA-L11-201209-221LMA30T_0805

1

C1065

C1065 10U_0805_10V4Z~D

10U_0805_10V4Z~D

2

+CLK_VDDSRC

32 31 30 29 28 27 26 25

24 23 22 21 20 19 18 17

SMBCLK SMBDATA REF_0/CPU_SEL

CLK_XTAL_IN CLK_XTAL_OUT

CK505_PWRGD

CLK_BUF_CPU_BCLK_R CLK_BUF_CPU_BCLK#_R

IDT Have Internal Pull-Down

CPU_1PIN 30 CPU_0

(Default)

0 133MHz

1

100MHz 100MHz

133MHz

+CLK_VDD

0.1U_0402_16V4Z~D

12

0.1U_0402_16V4Z~D

1

C1061

2

10U_0805_10V4Z~D

R633 33_0402_5%~DR633 33_0402_5%~D

1 2

R1007 0_0402_5%~DR1007 0_0402_5%~D

1 2

R1009 0_0402_5%~DR1009 0_0402_5%~D

1 2

Integrated 33ohm Resistor

+CLK_VDD

R631

R631 10K_0402_5%~D

10K_0402_5%~D

1 2

CK505_PWRGD

13

D

2

G

Q45

S

2N7002LT1G_SOT23-3

CLK_XTAL_IN

1M_0402_5%~D

CLK_XTAL_OUT

0.1U_0402_16V4Z~D

1

C1054

C1055

2

0.1U_0402_16V4Z~D

C1109

12

R1141

@R1141

@

1

C1056

2

0.1U_0402_16V4Z~D

10P_0402_50V8J~D

1 2

CLK_BUF_CPU_BCLK CLK_BUF_CPU_BCLK#

R632

R632 0_0402_5%~D

0_0402_5%~D

@

1 2

CLK_ENABLE# <55>

C1059 27P_0402_50V8J~DC1059 27P_0402_50V8J~D

12

Y6

14.31818MHz_20P_FSX8L14.318181M20FDB~OK

C1060 27P_0402_50V8J~DC1060 27P_0402_50V8J~D

C1057

2

VGATE <17,31,55>

12

1

C1058

0.1U_0402_16V4Z~D

2

SMBCLK <11,12,14,16>

SMBDATA <11,12,14,16>

CLK_BUF_ICH_14M <16>

CLK_BUF_CPU_BCLK <16> CLK_BUF_CPU_BCLK# <16>

4 4

Security Classification

2009/07/29 2010/07/29

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2009/07/29 2010/07/29

Compal Secret Data

Deciphered Date

E

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

F

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

G

A

13 57Monday, September 21, 2009

of

H

FAN Control circuit

EN_DFAN1<31>

FAN_SPEED1<31>

0.1U_0402_16V4Z~D

EN_DFAN1

+3VS

R141

10K_0402_5%~D

C98

12

2

1

+FAN1_POWER

C77

10U_1206_16V4Z~D

12

C91

1000P_0402_50V7K~D

12

+5VS

40mil

+FAN1_POWER

1 2

C96 10U_1206_16V4Z~DC96 10U_1206_16V4Z~D U7

U7

1

VEN

2 3 4

MOLEX_53261-0371~D

GND

VIN

GND GND

VO

GND

VSET

RT9027BPS_SO8

JFAN1

1

2

G

33G

CONN@

4 5

Free Fall Sensor

2

1

+3VS

1

C1067

C1067 10U_0805_10V4Z~D

10U_0805_10V4Z~D

2

+3VS +3VS_ACL_IO

8 7 6 5

+3VS_ACL_IO

+3VS

ACCEL_INT#<19>

SMBDATA<11,12,13,16>

SMBCLK<11,12,13,16>

+3VS

1 2

R1135 10K_0402_5%~D

R1134

1 2

0_0603_5%~D

12 13 14

U50

DE351DLTR

1

VDD_IO

6

VDD

8

INT 1 INT 29GND

SDO SDA / SDI / SDO SCL / SPC

7

RSVD

CS

RSVD

DE351DLTR_LGA14_3X5

GND GND GND

2 4 5 10

3 11

C1066

0.1U_0402_16V4Z~D

+3VS

Must be placed in the center of the system.

P/N : SA000039C00 (S IC DE351DLTR LGA 14P MOTION SENSOR)

Power Button

for debug only

1 2

5

6

3 4

SWO1

SWO1 SMT1-05_4P

SMT1-05_4P

TOPBTN

1 2

SWO2

5

6

SMT1-05_4P

3 4

PWR_ON-OFF_BTN#

PWR_ON-OFF_BTN# <32>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/07/29 2010/07/29

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

of

14 57Monday, September 21, 2009

A

5

+RTCVCC

1 2

R46

R46 20K_0402_1%~D

20K_0402_1%~D

PCH_RTCRST#

RC Delay 18~25mS

close to RAM door

12

CMOS1@CMOS1

@

C15

1U_0603_10V6K~D

D D

+RTCVCC

close to RAM door

1 2

R36

R36 20K_0402_1%~D

20K_0402_1%~D

ME1 @ME1 @

C13

1U_0603_10V6K~D

1 2

12

32.768KHZ_12.5PF_Q13MC14610002

PCH_SRTCRST#

RC Delay 18~25mS

3 2

+RTCVCC

INTVRMEN - Integrated SUS 1.1V VRM Enable High - Enable Internal VRs

HDA for AUDIO

HDA_BITCLK_AUDIO<25>

HDA_SYNC_AUDIO<25> HDA_RST_AUDIO#<25>

HDA_SDOUT_AUDIO<25>

C C

HDA_BITCLK_AUDIO

1 2

R1083 33_0402_5%~DR1083 33_0402_5%~D

1 2

R1084 33_0402_5%~DR1084 33_0402_5%~D

1 2

R1085 33_0402_5%~DR1085 33_0402_5%~D

1 2

R1086 33_0402_5%~DR1086 33_0402_5%~D

TOUCHKEY_TINT<31,32>

10P_0402_50V8J~D

1 2

C1110

@

HDA_BITCLK_PCH HDA_SYNC_PCH HDA_RST_PCH# HDA_SDOUT_PCH

R1024 0_0402_5%~DR1024 0_0402_5%~D

1 2

GPIO33 pull down only for ME disable

4

C398

18P_0402_50V8J~D

12

X2

OSC

NC

OSC

NC

C402

12

18P_0402_50V8J~D

R64 1M_0402_5%~DR64 1M_0402_5%~D

1 2

R51 330K_0402_5%~DR51 330K_0402_5%~D

1 2

PCH_SPKR<25>

HDA_SDIN0<25>

PCH_JTAG_TCK<23> PCH_JTAG_TMS<23>

PCH_JTAG_TDI<23>

PCH_JTAG_TDO<23>

PCH_JTAG_RST#<23>

PCH_RTCX1

4 1

10M_0402_5%~D

PCH_RTCX2

R1232 1K_0402_5%~D@R1232 1K_0402_5%~D@

1 2

R1100

12

PCH_RTCRST# PCH_SRTCRST# SM_INTRUDER# PCH_INTVRMEN

HDA_BITCLK_PCH HDA_SYNC_PCH PCH_SPKR HDA_RST_PCH#

HDA_SDOUT_PCH

PCH_JTAG_TCK

U47A

B13

RTCX1

D13

RTCX2

C14

RTCRST#

D17

SRTCRST#

A16

INTRUDER#

A14

INTVRMEN

A30

HDA_BCLK

D29

HDA_SYNC

P1

SPKR

C30

HDA_RST#

G30

HDA_SDIN0

F30

HDA_SDIN1

E32

HDA_SDIN2

F32

HDA_SDIN3

B29

HDA_SDO

H32

HDA_DOCK_EN# / GPIO33

J30

HDA_DOCK_RST# / GPIO13

M3

JTAG_TCK

K3

JTAG_TMS

K1

JTAG_TDI

J2

JTAG_TDO

J4

TRST#

REV1.0

3

RTCIHDA

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

FWH4 / LFRAME#

LDRQ1# / GPIO23

LPC

SATA0RXN SATA0RXP SATA0TXN

SATA0TXP

SATA1RXN SATA1RXP SATA1TXN

SATA1TXP

SATA2RXN SATA2RXP SATA2TXN

SATA2TXP

SATA3RXN SATA3RXP SATA3TXN

SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN

SATA5TXP

SATAICOMPO

SATAICOMPI

LDRQ0#

SERIRQ

D33 B33 C32 A32

C34 A34

F34 AB9

AK7 AK6 AK11 AK9

AH6 AH5 AH9 AH8

AF11 AF9 AF7 AF6

AH3 AH1 AF3 AF1

AD9 AD8 AD6 AD5

AD3 AD1 AB3 AB1

AF16 AF15

2

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

LPC_FRAME#

SERIRQ

SATA_ITX_DRX_N0 SATA_ITX_DRX_P0

SATA_ITX_DRX_N1 SATA_ITX_DRX_P1

From PCH EDS 5.16, SATA port2 & 3 are not available in all sku.

SATA_ITX_DRX_N4 SATA_ITX_DRX_P4

SATA_ITX_DRX_N5 SATA_ITX_DRX_P5

SATA_COMP

LPC_AD0 <27,31> LPC_AD1 <27,31> LPC_AD2 <27,31> LPC_AD3 <27,31>

LPC_FRAME# <27,31>

SERIRQ <31>

C963 0.01U_0402_16V7K~DC963 0.01U_0402_16V7K~D C964 0.01U_0402_16V7K~DC964 0.01U_0402_16V7K~D

R139 37.4_0402_1%~OKR139 37.4_0402_1%~OK

1 2

1

SATA_IRX_DTX_N0 <29>

C9610.01U_0402_16V7K~D C9610.01U_0402_16V7K~D

1 2

C9620.01U_0402_16V7K~D C9620.01U_0402_16V7K~D

1 2

12 12

SATA_IRX_DTX_P0 <29> SATA_ITX_C_DRX_N0 <29> SATA_ITX_C_DRX_P0 <29>

SATA_IRX_DTX_N1 <29>

SATA_IRX_DTX_P1 <29> SATA_ITX_C_DRX_N1 <29> SATA_ITX_C_DRX_P1 <29>

SATA for HDD1

SATA for HDD2

R0.3 depop

1 2 1 2

C9650.01U_0402_16V7K~D C9650.01U_0402_16V7K~D C9660.01U_0402_16V7K~D C9660.01U_0402_16V7K~D

C9670.01U_0402_16V7K~D C9670.01U_0402_16V7K~D C9680.01U_0402_16V7K~D C9680.01U_0402_16V7K~D

+1.05VS

SATA_IRX_DTX_N4 <29>

SATA_IRX_DTX_P4 <29> SATA_ITX_C_DRX_N4 <29> SATA_ITX_C_DRX_P4 <29>

SATA_IRX_DTX_N5 <30>

SATA_IRX_DTX_P5 <30> SATA_ITX_C_DRX_N5 <30> SATA_ITX_C_DRX_P5 <30>

SATA for ODD

SATA for eSATA

R0.3 depop

PCH_SPI_CLK_1

+3VS

B B

A A

R1120

R1120 1K_0402_5%~D

1K_0402_5%~D

1 2 1 2

R115

R115 10K_0402_5%~D

10K_0402_5%~D

PCH_JTAG_TMS

PCH_JTAG_TDO

PCH_JTAG_TDI

PCH_JTAG_RST#

PCH_SPKR

@

SERIRQ

R1130 51_0402_1%~D@R1130 51_0402_1%~D@

1 2

R1101 200_0402_5%~DR1101 200_0402_5%~D

1 2

R1102 100_0402_1%~DR1102 100_0402_1%~D

1 2

R1131 51_0402_1%~D@R1131 51_0402_1%~D@

1 2

R1104 200_0402_5%~D R1104 200_0402_5%~D

1 2

R1105 100_0402_1%~DR1105 100_0402_1%~D

1 2

R1132 51_0402_1%~D@R1132 51_0402_1%~D@

1 2

R1106 200_0402_5%~DR1106 200_0402_5%~D

1 2

R1107 100_0402_1%~DR1107 100_0402_1%~D

1 2

R1133 51_0402_1%~D@R1133 51_0402_1%~D@

1 2

R1108 20K_0402_1%~DR1108 20K_0402_1%~D

1 2

R1109 10K_0402_5%~DR1109 10K_0402_5%~D

1 2

PCH_SPI_CS0#

PCH_SPI_MOSI_1 PCH_SPI_MISO_1 PCH_SPI_MISO

+3V

+1.05VS

2008 Intel MOW36/MOW50

TDO: Reserved on ES1 Sample Mount R1104, R1105 on ES2 Sample

MP mount R1130, R1131, R1132, R1133 and remove others

R584 0_0402_5%~DR584 0_0402_5%~D

1 2

R571 15_0402_5%~DR571 15_0402_5%~D

1 2

R575 15_0402_5%~DR575 15_0402_5%~D

1 2

R565 33_0402_5%~DR565 33_0402_5%~D

1 2

PCH_SPI_CLKPCH_SPI_CLK PCH_SPI_CS0#_R

PCH_SPI_MOSI

+3VS

BA2

SPI_CLK

AV3

SPI_CS0#

AY3

SPI_CS1#

AY1

SPI_MOSI

AV1

SPI_MISO

IBEXPEAK-M_FCBGA1071~D

R1110

1 2

3.3K_0402_5%~D

SPI JTAG

PCH_SPI_CS0# PCH_SPI_MISO_1

SPI_WP1#

SATALED#

SATA0GP / GPIO21 SATA1GP / GPIO19

U29

1

CS#

2

SO

3

WP#

4

GND

MX25L1605AM2C-12G_SO8

VCC

HOLD#

SCLK

T3

Y9 V1

SI

PCH_SATALED#

+3VS

8

SPI_HOLD1#

7

PCH_SPI_CLK_1

6

PCH_SPI_MOSI_1

5

R129 10K_0402_5%~DR129 10K_0402_5%~D

1 2

PCH_GPIO21 <23> PCH_GPIO19 <23>

10K_0402_5%~D

R111

12

R11223.3K_0402_5%~D R11223.3K_0402_5%~D

12

+3VS

12

R82

R82 10K_0402_5%~D

10K_0402_5%~D

+3VS

R77 10K_0402_5%~D@R77 10K_0402_5%~D@

1 2

R116 10K_0402_5%~D@R116 10K_0402_5%~D@

1 2

+3VS

SPI Flash (16Mbit/2Mbyte)

Security Classification

PCH_SPI_MOSI

enable iTPM: SPI_MOSI High

R173 1K_0402_5%~D@R173 1K_0402_5%~D@

1 2

5

+3VS

PCH_JTAG_TCK

CRB 1.0 Change to 4.7K

R1111 4.7K_0402_5%~DR1111 4.7K_0402_5%~D

1 2

4

Security Classification

2009/07/29 2010/07/29

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/07/29 2010/07/29

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

401808

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

1

A

15 57Monday, September 21, 2009

of

5

MiniWWAN -->

MiniWLAN -->

D D

MiniWPAN -->

Card Reader -->

Express card -->

10/100/1G LAN -->

C C

MiniWWAN -->

MiniWLAN -->

MiniWPAN -->

Card Reader -->

Express card -->

B B

10/100/1G LAN -->

PCH_GPIO20 PCH_GPIO18

PCIE_IRX_WANTX_N1<27>

PCIE_IRX_WANTX_P1<27> PCIE_ITX_C_WANRX_N1<27> PCIE_ITX_C_WANRX_P1<27>

PCIE_IRX_WLANTX_N2<27>

PCIE_IRX_WLANTX_P2<27> PCIE_ITX_C_WLANRX_N2<27> PCIE_ITX_C_WLANRX_P2<27>

PCIE_IRX_WPANTX_N3<28>

PCIE_IRX_WPANTX_P3<28> PCIE_ITX_C_WPANRX_N3<28> PCIE_ITX_C_WPANRX_P3<28>

PCIE_IRX_CBTX_N4<30>

PCIE_IRX_CBTX_P4<30> PCIE_ITX_C_CBRX_N4<30> PCIE_ITX_C_CBRX_P4<30>

PCIE_IRX_EXPTX_N5<28> PCIE_IRX_EXPTX_P5<28>

PCIE_ITX_C_EXPRX_N5<28> PCIE_ITX_C_EXPRX_P5<28>

PCIE_IRX_GLANTX_N6<24>

PCIE_IRX_GLANTX_P6<24> PCIE_ITX_C_GLANRX_N6<24> PCIE_ITX_C_GLANRX_P6<24>

CLK_PCIE_WAN#<27> CLK_PCIE_WAN<27>

WWAN_CLKREQ#<27>

CLK_PCIE_WLAN#<27> CLK_PCIE_WLAN<27>

WLAN_CLKREQ#<27>

PCH_GPIO18<23>

CLK_PCIE_WPAN#<28> CLK_PCIE_WPAN<28>

WPAN_CLKREQ#<28>

PCH_GPIO20<23>

CLK_PCIE_CB#<30> CLK_PCIE_CB<30>

CB_CLKREQ#<30>

CLK_PCIE_EXPR#<28> CLK_PCIE_EXPR<28>

EXP_CLKREQ#<28>

CLK_PCIE_GLAN#<24> CLK_PCIE_GLAN<24>

GLAN_CLKREQ#<24>

R1112 10K_0402_5%~DR1112 10K_0402_5%~D

1 2

R1022 10K_0402_5%~DR1022 10K_0402_5%~D

1 2

C1021 0.1U_0402_16V7K~DC1021 0.1U_0402_16V7K~D C1022 0.1U_0402_16V7K~DC1022 0.1U_0402_16V7K~D

C1023 0.1U_0402_16V7K~DC1023 0.1U_0402_16V7K~D C1024 0.1U_0402_16V7K~DC1024 0.1U_0402_16V7K~D

C969 0.1U_0402_16V7K~DC969 0.1U_0402_16V7K~D C970 0.1U_0402_16V7K~DC970 0.1U_0402_16V7K~D

C971 0.1U_0402_16V7K~DC971 0.1U_0402_16V7K~D C972 0.1U_0402_16V7K~DC972 0.1U_0402_16V7K~D

C973 0.1U_0402_16V7K~DC973 0.1U_0402_16V7K~D C974 0.1U_0402_16V7K~DC974 0.1U_0402_16V7K~D

C1025 0.1U_0402_16V7K~DC1025 0.1U_0402_16V7K~D C1026 0.1U_0402_16V7K~DC1026 0.1U_0402_16V7K~D

R551 0_0402_5%~DR551 0_0402_5%~D

1 2

R550 0_0402_5%~DR550 0_0402_5%~D

1 2

R76 0_0402_5%~DR76 0_0402_5%~D

1 2

R1123 0_0402_5%~DR1123 0_0402_5%~D

1 2

R1124 0_0402_5%~DR1124 0_0402_5%~D

1 2

R93 0_0402_5%~DR93 0_0402_5%~D

1 2

R1012 0_0402_5%~DR1012 0_0402_5%~D

1 2

R1013 0_0402_5%~DR1013 0_0402_5%~D

1 2

R1014 0_0402_5%~DR1014 0_0402_5%~D

1 2

R1015 0_0402_5%~DR1015 0_0402_5%~D

1 2

R1016 0_0402_5%~DR1016 0_0402_5%~D

1 2

R1017 0_0402_5%~DR1017 0_0402_5%~D

1 2

R558 0_0402_5%~DR558 0_0402_5%~D

1 2

R563 0_0402_5%~DR563 0_0402_5%~D

1 2

R1018 0_0402_5%~DR1018 0_0402_5%~D

1 2

R1019 0_0402_5%~DR1019 0_0402_5%~D

1 2

R1020 0_0402_5%~DR1020 0_0402_5%~D

1 2

R1021 0_0402_5%~DR1021 0_0402_5%~D

1 2

+3VS

12 12

4

PCIE_IRX_WANTX_N1 PCIE_IRX_WANTX_P1 PCIE_ITX_WANRX_N1 PCIE_ITX_WANRX_P1

PCIE_IRX_WLANTX_N2 PCIE_IRX_WLANTX_P2 PCIE_ITX_WLANRX_N2 PCIE_ITX_WLANRX_P2

PCIE_IRX_WPANTX_N3 PCIE_IRX_WPANTX_P3 PCIE_ITX_WPANRX_N3 PCIE_ITX_WPANRX_P3

PCIE_IRX_CBTX_N4 PCIE_IRX_CBTX_P4 PCIE_ITX_CBRX_N4 PCIE_ITX_CBRX_P4

PCIE_IRX_EXPTX_N5 PCIE_IRX_EXPTX_P5 PCIE_ITX_EXPRX_N5 PCIE_ITX_EXPRX_P5

PCIE_IRX_GLANTX_N6 PCIE_IRX_GLANTX_P6 PCIE_ITX_GLANRX_N6 PCIE_ITX_GLANRX_P6

R_CLK_PCIE_WAN# R_CLK_PCIE_WAN

PCH_GPIO73

R_CLK_PCIE_WLAN# R_CLK_PCIE_WLAN

PCH_GPIO18

R_CLK_PCIE_WPAN# R_CLK_PCIE_WPAN

PCH_GPIO20

R_CLK_PCIE_CB# R_CLK_PCIE_CB

PCH_GPIO25

R_CLK_PCIE_EXPR# R_CLK_PCIE_EXPR

PCH_GPIO26

R_CLK_PCIE_GLAN# R_CLK_PCIE_GLAN

PCH_GPIO44

PCH_GPIO56

U47B

BG30

PERN1

BJ30

PERP1

BF29

PETN1

BH29

PETP1

AW30

PERN2

BA30

PERP2

BC30

PETN2

BD30

PETP2

AU30

PERN3

AT30

PERP3

AU32

PETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

P9

PCIECLKRQ0# / GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

U4

PCIECLKRQ1# / GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

N4

PCIECLKRQ2# / GPIO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

AM51

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

M9

PCIECLKRQ4# / GPIO26

AJ50

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

H6

PCIECLKRQ5# / GPIO44

AK53

CLKOUT_PEG_B_N

AK51

CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ# / GPIO56

IBEXPEAK-M_FCBGA1071~D

REV1.0

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1ALERT# / GPIO74

SMBus

SML1DATA / GPIO75

PCI-E*

Link

Controller

PEG_A_CLKRQ# / GPIO47

PEG

CLKOUT_DP_N / CLKOUT_BCLK1_N

CLKOUT_DP_P / CLKOUT_BCLK1_P

From CLK BUFFER

CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P

CLKIN_PCILOOPBACK

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

Clock Flex

3

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK / GPIO58

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_BCLK_N CLKIN_BCLK_P

CLKIN_DOT_96N CLKIN_DOT_96P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

EC_LID_OUT#

B9 H14 C8

PCH_GPIO60

J14 C6 G8

PCH_GPIO74

M14

PCH_SML1CLK

E10

PCH_SML1DAT

G12

T13 T11 T9

PEG_CLKREQ#_R

H1

AD43 AD45

AN4 AN2

AT1 AT3

AW24 BA24

AP3 AP1

F18 E18

AH13 AH12

P41

J42

AH51 AH53

XCLK_RCOMP

AF38

T45

P43

T42

N50

XTAL25_IN XTAL25_OUT

EC_LID_OUT# <31> PCH_SMBCLK <11,12,23> PCH_SMBDATA <11,12,23>

R43 10K_0402_5%~DR43 10K_0402_5%~D

1 2

CLK_PEG_VGA# <38> CLK_PEG_VGA <38>

CLK_CPU_DMI# <6> CLK_CPU_DMI <6>

CLK_BUF_CPU_DMI# <13> CLK_BUF_CPU_DMI <13>

CLK_BUF_CPU_BCLK# <13> CLK_BUF_CPU_BCLK <13>

CLK_BUF_DREF_96M# <13> CLK_BUF_DREF_96M <13>

CLK_BUF_PCIE_SATA# <13> CLK_BUF_PCIE_SATA <13>

CLK_BUF_ICH_14M <13>

CLK_PCI_FB <19>

R127 90.9_0402_1%~DR127 90.9_0402_1%~D

1 2

+1.05VS

2

1. Connect Directly XDCP of DDR3

2. Level Shift1, Pull-Up to +3VS CLOCK GEN, DIMM1, DIMM2, FFS

3. Level Shift2, Pull-Up to +3VS CPU & PCH XDP

R53

2.2K_0402_5%~D

+3V

R548

1M_0402_5%~D

@

2.2K_0402_5%~D

R52

2.2K_0402_5%~D

PCH_SMBCLK

R1147

2.2K_0402_5%~D

PCH_SML1CLK

R1149

2.2K_0402_5%~D

PCH_SML1DAT

12

1 3

12

1 3

12

1 3

12

1 3

C1027

C1027 0_0402_5%~D

0_0402_5%~D

1 2

Y2

Y2 25MHZ_20P

25MHZ_20P

@

1 2

C1028

C1028 27P_0402_50V8J~D

27P_0402_50V8J~D

@

1

+3VS

R638

4.7K_0402_5%~D

2

G

1 2

D

S

D

S

Q47

Q47 2N7002LT1G_SOT23-3

2N7002LT1G_SOT23-3

+3VS

R635

4.7K_0402_5%~D

2

G

1 2

D

S

D

S

Q46

Q46 2N7002LT1G_SOT23-3

2N7002LT1G_SOT23-3

+3VS

2

G

EC_SMB_CK2

D

S

D

S

Q57

Q57 2N7002LT1G_SOT23-3

2N7002LT1G_SOT23-3

+3VS

2

G

EC_SMB_DA2

D

S

D

S

Q58

Q58 2N7002LT1G_SOT23-3

2N7002LT1G_SOT23-3

R0.3 Modify

XTAL25_IN should be pulled to GND using a 0Ω resistor. (Calpella_Schematic_Checklist_Rev1.6)

SMBDATAPCH_SMBDATA

SMBCLK

+3VS

Note: remove 25MHz crystal for ES2 silicon

SMBDATA <11,12,13,14>

SMBCLK <11,12,13,14>

EC_SMB_CK2 <27,28,31,39>

EC_SMB_DA2 <27,28,31,39>

@

+3V

EC_LID_OUT# PCH_GPIO73

A A

PCH_GPIO60 PCH_GPIO25 PCH_GPIO26

PCH_GPIO74

PCH_GPIO44 PCH_GPIO56

R1113 10K_0402_5%~DR1113 10K_0402_5%~D

1 2

R81 10K_0402_5%~DR81 10K_0402_5%~D

1 2

R78 10K_0402_5%~DR78 10K_0402_5%~D

1 2

R1087 10K_0402_5%~DR1087 10K_0402_5%~D

1 2

R1023 10K_0402_5%~DR1023 10K_0402_5%~D

1 2

R84 10K_0402_5%~DR84 10K_0402_5%~D

1 2

R54 10K_0402_5%~DR54 10K_0402_5%~D

1 2

R95 10K_0402_5%~DR95 10K_0402_5%~D

1 2

5

+3VS

WWAN_CLKREQ# PCH_GPIO73

+3VS

CB_CLKREQ# PCH_GPIO25

@

1 2

R1203 10K_0402_5%~D

@

1 2

R1206 10K_0402_5%~D

@

1 2

R1209 10K_0402_5%~D

@

1 2

R1210 10K_0402_5%~D

G

S

@

G

S

@

4

2

Q64

13

D

2N7002LT1G_SOT23-3

2

Q67

13

D

2N7002LT1G_SOT23-3

+3VS +3VS

EXP_CLKREQ# PCH_GPIO26 GLAN_CLKREQ# PCH_GPIO44

@

1 2

R1204 10K_0402_5%~D

@

1 2

R1207 10K_0402_5%~D

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

G

2

S

@

Issued Date

Q65

13

D

2N7002LT1G_SOT23-3

3

2009/07/29 2010/07/29

@

1 2

R1205 10K_0402_5%~D

@

1 2

R1208 10K_0402_5%~D

Compal Secret Data

Deciphered Date

G

S

@

2

Q66

13

D

2N7002LT1G_SOT23-3

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

1

16 57Monday, September 21, 2009

of

A

5

D D

+3VS

@

1 2

R110 10K_0402_5%~D

@

1 2

R1125 8.2K_0402_5%~D

1 2

R1211 10K_0402_5%~DR1211 10K_0402_5%~D

1 2

R1088 8.2K_0402_5%~DR1088 8.2K_0402_5%~D

@

1 2

R69 10K_0402_5%~D

C C

B B

A A

R69 10K_0402_5%~D

1 2

R1114 10K_0402_5%~DR1114 10K_0402_5%~D

1 2

R72 10K_0402_5%~DR72 10K_0402_5%~D

1 2

R55 1K_0402_5%~DR55 1K_0402_5%~D

10/2 Intel suggestion change to 10K

SYS_PWROK<23>

XDP_DBRESET# PM_CLKRUN#

PCH_GPIO72 PM_SLP_LAN#

SUS_PWR_ACK

EC_SWI#

ICH_PCIE_WAKE#

+3V

ACIN<25,31,39,48,49>

SYS_PWROK

5

SYS_PWROK VGATE

R66 10K_0402_5%~DR66 10K_0402_5%~D

CH751H-40PT_SOD323-2~D

R37 0_0402_5%~D@R37 0_0402_5%~D@

SYS_PWROK

ICH_PWROK

LAN_RST#

No used Integrated LAN, connecting LAN_RST# to GND

DMI_HTX_PRX_N0<5> DMI_HTX_PRX_N1<5> DMI_HTX_PRX_N2<5> DMI_HTX_PRX_N3<5>

DMI_HTX_PRX_P0<5> DMI_HTX_PRX_P1<5> DMI_HTX_PRX_P2<5> DMI_HTX_PRX_P3<5>

DMI_PTX_HRX_N0<5> DMI_PTX_HRX_N1<5> DMI_PTX_HRX_N2<5> DMI_PTX_HRX_N3<5>

DMI_PTX_HRX_P0<5> DMI_PTX_HRX_P1<5> DMI_PTX_HRX_P2<5> DMI_PTX_HRX_P3<5>

+1.05VS+3V

R590

49.9_0402_1%~D

1 2

XDP_DBRESET#<6,23>

R58 0_0402_5%~DR58 0_0402_5%~D R70 0_0402_5%~D@R70 0_0402_5%~D@

1 2

+3VS

4

Y

1 2

R31 10K_0402_5%~DR31 10K_0402_5%~D

1 2

R41 10K_0402_5%~DR41 10K_0402_5%~D

1 2

R1115 10K_0402_5%~DR1115 10K_0402_5%~D

12 12

PM_DRAM_PWRGD<6>

SUS_PWR_ACK<31>

PBTN_OUT#<6,23,31>

21

D50

12

5

U2

2

P

B

1

A

G

NC7SZ08P5X_NL_SC70-5

3

ICH_PWROK VGATE

4

DMI_COMP

XDP_DBRESET#

SYS_PWROK_R

SYS_PWROK

LAN_RST#

PCH_RSMRST#

SUS_PWR_ACK

PBTN_OUT#

PCH_ACIN

PCH_GPIO72

EC_SWI#

ICH_PWROK <31> VGATE <13,31,55>

4

U47C

BC24

DMI0RXN

BJ22

DMI1RXN

AW20

DMI2RXN

BJ20

DMI3RXN

BD24

DMI0RXP

BG22

DMI1RXP

BA20

DMI2RXP

BG20

DMI3RXP

BE22

DMI0TXN

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

T6

SYS_RESET#

M6

SYS_PWROK

B17

PWROK

K5

MEPWROK

A10

LAN_RST#

D9

DRAMPWROK

C16

RSMRST#

M1

SUS_PWR_DN_ACK / GPIO30

P5

PWRBTN#

P7

ACPRESENT / GPIO31

A6

BATLOW# / GPIO72

F14

RI#

IBEXPEAK-M_FCBGA1071~D

3

REV1.0

FDI_FSYNC0

DMI

FDI

DMI

FDI

FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Management

SLP_LAN# / GPIO29

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

FDI_INT

WAKE#

SLP_S4#

SLP_S3#

SLP_M#

TP23

PMSYNCH

BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12

BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12

BJ14 BF13 BH13 BJ12 BG14

ICH_PCIE_WAKE#

J12

PM_CLKRUN#

Y1

PCH_GPIO61

P8

PCH_GPIO62

F3

SLP_S5#

E4

H7

P12

PM_SLP_M#

K8

PM_SLP_DSW#

N2

BJ10

PM_SLP_LAN#

F6

2009/07/29 2010/07/29

3

@

ICH_PCIE_WAKE# <24,27,28,31>

@

PAD

T4

PAD

T7

PM_SLP_S4# <11>

SLP_S3# <31>

@

PAD

T2

@

PAD

T8

H_PM_SYNC <6>

Compal Secret Data

Deciphered Date

EC_TX_P80_DATA<27,31>

2

@

R1234

PM_SLP_S4# SLP_S5#

R30 0_0402_5%~D

PCH_RSMRST#

R32

R32 10K_0402_5%~D

10K_0402_5%~D

12

1

+3V

C1125

0_0402_5%~D

12

Q50

Q50 MMBT3906_SOT23-3

MMBT3906_SOT23-3

123

C

E

B

R27 4.7K_0402_5%~DR27 4.7K_0402_5%~D

1 2

BAV99DW-7_SOT363

4 5

BAV99DW-7_SOT363

Title

Size Document Number Rev

Custom

Date: Sheet

1 2

0.1U_0402_10V6K~D

5

U62

1

P

IN1

4

O

2

IN2

G

74AHC1G08GW_SOT353-5~D

3

@

12

R1233 0_0402_5%~D

@

EC_RSMRST# <31>

1 2

D3A

6

D3B

3

12

R39

2.2K_0402_5%~D

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

PM_SLP_S5# <31>

+3V

1

17 57Monday, September 21, 2009

of

A

5

D D

C C

B B

4

AB48

AB46

AP39 AP41

AT43 AT42

AV53 AV51

BB47 BA52 AY48 AV47

BB48 BA50 AY49 AV48

AP48 AP47

AY53 AT49 AU52 AT53

AY51 AT48 AU50 AT51

AA52 AB53 AD53

CRT_IREF

AD48 AB51

12

R126

R126 1K_0402_0.5%~D

1K_0402_0.5%~D

3

U47D

T48

L_BKLTEN

T47

L_VDD_EN

Y48

L_BKLTCTL L_DDC_CLK

Y45

L_DDC_DATA L_CTRL_CLK

V48

L_CTRL_DATA LVD_IBG

LVD_VBG LVD_VREFH

LVD_VREFL

LVDSA_CLK# LVDSA_CLK

LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3

LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3

LVDSB_CLK# LVDSB_CLK

LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3

LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3

CRT_BLUE CRT_GREEN CRT_RED

V51

CRT_DDC_CLK

V53

CRT_DDC_DATA

Y53

CRT_HSYNC

Y51

CRT_VSYNC

DAC_IREF CRT_IRTN

IBEXPEAK-M_FCBGA1071~D

IBEXPEAK-M_FCBGA1071~D <BOM Structure>

DDPB_0N

DDPB_0P

DDPB_1N

DDPB_1P

DDPB_2N

DDPB_2P

DDPB_3N

DDPB_3P

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

BJ46 BG46

BJ48 BG48

BF45 BH45

T51 T53

BG44 BJ44 AU38

BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38

Y49 AB49

BE44 BD44 AV40

BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36

U50 U52

BC46 BD46 AT38

BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

DDPD_HPD

CRT

REV1.0

2

1

A A

Security Classification

2009/07/29 2010/07/29

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/07/29 2010/07/29

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SCHEMATICS, MB A5155

Size Document Number Rev

Custom

401808

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

18 57Monday, September 21, 2009

1

A

of

5

+3VS

RP5

PCI_PIRQA#

1 8

PCI_PIRQG#

2 7

PCI_PIRQC#

3 6

PCI_SERR#

4 5

8.2K_1206_8P4R_5%~D

RP4

D D

C C

B B

RP4

PCI_PLOCK#

1 8

PCI_PERR#

2 7

PCI_PIRQH#

3 6

PCI_STOP#

4 5

8.2K_1206_8P4R_5%~D

RP9

PCI_REQ0#

1 8

PCI_PIRQB#

2 7

PCI_PIRQF#

3 6

PCI_REQ3#

4 5

8.2K_1206_8P4R_5%~D

8.2K_1206_8P4R_5%~D RP6

RP6 1 8 2 7 3 6 4 5

1 8 2 7 3 6 4 5

1 2

R1239 8.2K_0402_5%~D

PCI_IRDY# PCI_PIRQD# PCI_REQ2# PCI_DEVSEL#

8.2K_1206_8P4R_5%~D

RP8

PCI_FRAME# PCI_REQ1#

PCI_TRDY#

8.2K_1206_8P4R_5%~D

ACCEL_INT#

Link to INT of G sensor

@

10P_0402_50V8J~D

C1111

C1111 C1112

C1112

1 2 1 2

@

10P_0402_50V8J~D 10P_0402_50V8J~D

10P_0402_50V8J~D

CLK_PCI_EC CLK_PCI_FB

CLK_DEBUG_PORT<27>

CLK_PCI_EC<31> CLK_PCI_FB<16>

ACCEL_INT#<14>

PCI_PLTRST#<6>

R1031 22_0402_5%~DR1031 22_0402_5%~D

1 2

R1116 22_0402_5%~DR1116 22_0402_5%~D

1 2

R99 22_0402_5%~DR99 22_0402_5%~D

1 2

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

PCI_REQ0# PCI_REQ1# PCI_REQ2# PCI_REQ3#

PCI_GNT0# PCI_GNT1#

PCI_GNT3#

PCI_PIRQF# PCI_PIRQG# PCI_PIRQH#

PCI_SERR# PCI_PERR#

PCI_IRDY# PCI_DEVSEL#

PCI_FRAME# PCI_PLOCK# PCI_STOP#

PCI_TRDY#

PCI_PLTRST#

R_CLK_DEBUG_PORT R_CLK_PCI_EC R_CLK_PCI_FB

2008/1/6 2009MOW01 change to 22 ohm

Boot BIOS Strap PCI_GNT#0 PCI_GNT#1 Boot BIOS Location

00

A A

01 10 11

*

A16 swap override Strap/Top-Block

Swap Override jumper PCI_GNT#3

Low = A16 swap High = Default

5

LPC Reserved (NAND) PCI SPI

PCI_GNT0# PCI_GNT1#

PCI_GNT3#

4

U47E

H40

AD0

N34

AD1

C44

AD2

A38

AD3

C36

AD4

J34

AD5

A40

AD6

D45

AD7

E36

AD8

H48

AD9

E40

AD10

C40

AD11

M48

AD12

M45

AD13

F53

AD14

M40

AD15

M43

AD16

J36

AD17

K48

AD18

F40

AD19

C42

AD20

K46

AD21

M51

AD22

J52

AD23

K51

AD24

L34

AD25

F42

AD26

J40

AD27

G46

AD28

F44

AD29

M47

AD30

H36

AD31

J50

C/BE0#

G42

C/BE1#

H47

C/BE2#

G34

C/BE3#

G38

PIRQA#

H51

PIRQB#

B37

PIRQC#

A44

PIRQD#

F51

REQ0#

A46

REQ1# / GPIO50

B45

REQ2# / GPIO52

M53

REQ3# / GPIO54

F48

GNT0#

K45

GNT1# / GPIO51

F36

GNT2# / GPIO53

H53

GNT3# / GPIO55

B41

PIRQE# / GPIO2

K53

PIRQF# / GPIO3

A36

PIRQG# / GPIO4

A48

PIRQH# / GPIO5

K6

PCIRST#

E44

SERR#

E50

PERR#

A42

IRDY#

H44

PAR

F46

DEVSEL#

C46

FRAME#

D49

PLOCK#

D41

STOP#

C48

TRDY#

M7

PME#

D5

PLTRST#

N52

CLKOUT_PCI0

P53

CLKOUT_PCI1

P46

CLKOUT_PCI2

P51

CLKOUT_PCI3

P48

CLKOUT_PCI4

IBEXPEAK-M_FCBGA1071~D

R75 1K_0402_5%~D@R75 1K_0402_5%~D@

1 2

R83 1K_0402_5%~D@R83 1K_0402_5%~D@

1 2

R1117 1K_0402_5%~D@R1117 1K_0402_5%~D@

1 2

4

REV1.0

PCI

NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3

NV_DQS0 NV_DQS1

NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8

NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11

NVRAM

NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15

NV_ALE NV_CLE

NV_RCOMP

NV_RB#

NV_WR#0_RE# NV_WR#1_RE#

NV_WE#_CK0 NV_WE#_CK1

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P

USB

USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43

OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

3

AY9 BD1 AP15 BD8

AV9 BG8

AP7 AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6 BD6 BB7 BC8 BJ8 BJ6 BG6

BD3 AY6

AU2 AV7 AY8

AY5 AV11

BF5

H18 J18 A18 C18 N20 P20 J20 L20 F20 G20 A20 C20 M22 N22 B21 D21 H22 J22 E22 F22 A22 C22 G24 H24 L24 M24 A24 C24

B25 D25

N16 J16 F16 L16 E14 G16 F12 T15

NV_ALE NV_CLE

NV_RCOMP

USBP0USBP0+ USBP1USBP1+ USBP2USBP2+ USBP3USBP3+ USBP4USBP4+ USBP5USBP5+

USBP8USBP8+ USBP9USBP9+ USBP10USBP10+ USBP11USBP11+

USB_BIAS

USB_OC0#_R USB_OC1#_R USB_OC2#_R USB_OC3# USB_OC4# USB_OC5# USB_OC6# USB_OC7#

Danbury Technology Enabled

NV_ALE

DMI Termination Voltage

NV_CLE

R167 1K_0402_5%~D@R167 1K_0402_5%~D@

1 2

R172 1K_0402_5%~D@R172 1K_0402_5%~D@

1 2

R153 32.4_0402_1%~OKR153 32.4_0402_1%~OK

1 2

USBP0- <30> USBP0+ <30> USBP1- <30> USBP1+ <30> USBP2- <30> USBP2+ <30> USBP3- <28> USBP3+ <28> USBP4- <27> USBP4+ <27> USBP5- <27>

From PCH EDS 5.18, USB port6 & 7 are not available in all sku.

USBP5+ <27>

USBP8- <28> USBP8+ <28> USBP9- <32> USBP9+ <32> USBP10- <30> USBP10+ <30> USBP11- <30> USBP11+ <30>

1 2

R63

22.6_0402_1%~D

R48 0_0402_5%~DR48 0_0402_5%~D

1 2

R67 0_0402_5%~DR67 0_0402_5%~D

1 2

R28 0_0402_5%~DR28 0_0402_5%~D

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

High = Enabled Low = Disabled

Set to Vss when LOW Set to Vcc when HIGH

+VCCQ_NAND

EHCI 1

EHCI 2

OC[0..3] use for EHCI 1 OC[4..7] use for EHCI 2

2009/07/29 2010/07/29

ESATA_USB_OC# <30> USB_OC1# <30> USB_OC2# <30> USB_OC3# <23> USB_OC4# <23> USB_OC5# <23> USB_OC6# <23> USB_OC7# <23>

Compal Secret Data

PCI_PLTRST#

Deciphered Date

2

1

C975

0.1U_0402_16V4Z~D

MC74VHC1G08DFT2G SC70 5P

0.1U_0402_16V4Z~D

USB Port

0 1 2 3 4 5 6 7 8 9 10 11

USB_OC0#_R USB_OC1#_R USB_OC2#_R

2

@

R1029 0_0402_5%~D

R1030 0_0402_5%~D

C976

12

1

2

@

12

Device USB&ESATA Reader board USB board WPAN WLAN WWAN NC NC Express Touch screen Bluetooth Camera

2

+3VS

5

U43

2

P

B

4

Y

1

A

G

3

+3VS

5

U44

2

P

B

4

Y

1

A

G

MC74VHC1G08DFT2G SC70 5P

3

USB_OC0#_R <23> USB_OC1#_R <23> USB_OC2#_R <23>

1

12

R1138

R1138 100K_0402_5%~D

100K_0402_5%~D

12

R1146

@

0_0402_5%~D

PLT_RST#

Title

SCHEMATICS, MB A5155

Size Document Number Rev

Custom

401808

Date: Sheet

VGA_RST# <38>

12

R1139

R1139 100K_0402_5%~D

100K_0402_5%~D

USB_OC0#_R USB_OC1#_R USB_OC2#_R USB_OC3#

USB_OC4# USB_OC5# USB_OC6# USB_OC7#

Compal Electronics, Inc.

PLT_RST# <6,23,24,27,28,30,31>

RP10

RP10 1 8 2 7 3 6 4 5

10K_1206_8P4R_5%~D

RP7

RP7 1 8 2 7 3 6 4 5

10K_1206_8P4R_5%~D

19 57Monday, September 21, 2009

1

19 57Monday, September 21, 2009

+3V

of

A

5

4

3

2

1

+3VS

R107 10K_0402_5%~DR107 10K_0402_5%~D

1 2

R62 10K_0402_5%~DR62 10K_0402_5%~D

1 2

R1126 10K_0402_5%~DR1126 10K_0402_5%~D

1 2

R73 10K_0402_5%~DR73 10K_0402_5%~D

1 2

R87 10K_0402_5%~DR87 10K_0402_5%~D

D D

C C

B B

1 2

R1127 10K_0402_5%~DR1127 10K_0402_5%~D

1 2

R1128 10K_0402_5%~DR1128 10K_0402_5%~D

1 2

R133 10K_0402_5%~DR133 10K_0402_5%~D

1 2

R128 10K_0402_5%~DR128 10K_0402_5%~D

1 2

R120 10K_0402_5%~DR120 10K_0402_5%~D

1 2

R1129 10K_0402_5%~DR1129 10K_0402_5%~D

1 2

R61 10K_0402_5%~DR61 10K_0402_5%~D

1 2

R100 10K_0402_5%~DR100 10K_0402_5%~D

1 2

R1032 10K_0402_5%~DR1032 10K_0402_5%~D

1 2

+3V

R59 10K_0402_5%~DR59 10K_0402_5%~D

1 2

R47 10K_0402_5%~DR47 10K_0402_5%~D

1 2

R86 1K_0402_5%~DR86 1K_0402_5%~D

1 2

10/7 Not Use PCH_GPIO15 PU 1K to +3V

R117 10K_0402_5%~DR117 10K_0402_5%~D

1 2

R1118 10K_0402_5%~DR1118 10K_0402_5%~D

1 2

R1119 10K_0402_5%~DR1119 10K_0402_5%~D

1 2

R106 10K_0402_5%~DR106 10K_0402_5%~D

1 2

R68 10K_0402_5%~DR68 10K_0402_5%~D

1 2

R134 10K_0402_5%~D@R134 10K_0402_5%~D@

1 2

GPIO27 (Have internal Pull-High) High: VCCVRM VR Enable Low: VCCVRM VR Disable

PCH_GPIO0 PCH_GPIO16

GPIO17 PCH_GPIO22 VGA_PRSNT_R# VGA_PRSNT_L# PCH_GPIO36 PCH_GPIO37 PCH_GPIO48 PCH_GPIO49 LAN_LOPWEN PCH_GPIO34 LAN_CABDT

EC_SCI# EC_SMI#

PCH_GPIO15

PCH_GPIO28 PCH_GPIO45

PCH_GPIO46

PCH_GPIO35 PCH_GPIO57

PCH_GPIO27

PCH_GPIO0<23>

LAN_LOPWEN<24> LAN_CABDT<24>

EC_SMI#<31> EC_SCI#<31>

PCH_GPIO16<23>

(Rev:1.0 GPIO24 Only)

PCH_GPIO28<23>

PCH_GPIO36<23> PCH_GPIO37<23>

DDR_RST_GATE<6,11,12>

PCH_GPIO49<23,31>

PCH_GPIO0 PCH_GPIO1PCH_GPIO1 LAN_LOPWEN LAN_CABDT EC_SMI# EC_SCI# PCH_GPIO15 PCH_GPIO16 GPIO17 PCH_GPIO22

PCH_GPIO27 PCH_GPIO28 PCH_GPIO34 PCH_GPIO35 PCH_GPIO36 PCH_GPIO37 VGA_PRSNT_R# VGA_PRSNT_L# PCH_GPIO45 PCH_GPIO46 PCH_GPIO48 PCH_GPIO49 PCH_GPIO57

U47F

Y3

BMBUSY# / GPIO0

C38

TACH1 / GPIO1

D37

TACH2 / GPIO6

J32

TACH3 / GPIO7

F10

GPIO8

K9

LAN_PHY_PWR_CTRL / GPIO12

T7

GPIO15

AA2

SATA4GP / GPIO16

F38

TACH0 / GPIO17

Y7

SCLOCK / GPIO22

H10

GPIO24

AB12

GPIO27

V13

GPIO28

M11

STP_PCI# / GPIO34

V6

SATACLKREQ# / GPIO35

AB7

SATA2GP / GPIO36

AB13

SATA3GP / GPIO37

V3

SLOAD / GPIO38

P3

SDATAOUT0 / GPIO39

H3

PCIECLKRQ6# / GPIO45

F1

PCIECLKRQ7# / GPIO46

AB6

SDATAOUT1 / GPIO48

AA4

SATA5GP / GPIO49

F8

GPIO57

A4

VSS_NCTF_1

A49

VSS_NCTF_2

A5

VSS_NCTF_3

A50

VSS_NCTF_4

A52

VSS_NCTF_5

A53

VSS_NCTF_6

B2

VSS_NCTF_7

B4

VSS_NCTF_8

B52

VSS_NCTF_9

B53

VSS_NCTF_10

BE1

VSS_NCTF_11

BE53

VSS_NCTF_12

BF1

VSS_NCTF_13

BF53

VSS_NCTF_14

BH1

VSS_NCTF_15

BH2

VSS_NCTF_16

BH52

VSS_NCTF_17

BH53

VSS_NCTF_18

BJ1

VSS_NCTF_19

BJ2

VSS_NCTF_20

BJ4

VSS_NCTF_21

BJ49

VSS_NCTF_22

BJ5

VSS_NCTF_23

BJ50

VSS_NCTF_24

BJ52

VSS_NCTF_25

BJ53

VSS_NCTF_26

D1

VSS_NCTF_27

D2

VSS_NCTF_28

D53

VSS_NCTF_29

E1

VSS_NCTF_30

E53

VSS_NCTF_31

IBEXPEAK-M_FCBGA1071~D

MISC

CLKOUT_BCLK0_N / CLKOUT_PCIE8N

CLKOUT_BCLK0_P / CLKOUT_PCIE8P

GPIO

CPU

NCTF

RSVD

REV1.0

CLKOUT_PCIE6N CLKOUT_PCIE6P

CLKOUT_PCIE7N CLKOUT_PCIE7P

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8

TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19

NC_1 NC_2 NC_3 NC_4 NC_5

INIT3_3V#

TP24

AH45 AH46

AF48 AF47

GATEA20

U2

AM3 AM1 BG10

KB_RST#

T1 BE10 BD10

BA22 AW22 BB22 AY45 AY46 AV43 AV45 AF13 M18 N18 AJ24 AK41 AK42 M32 N32 M30 N30 H12 AA23 AB45 AB38 AB42 AB41 T39

(Do not pull high)

P6

TP24_SST

C10

GATEA20 <31>

CLK_CPU_BCLK# <6> CLK_CPU_BCLK <6>

H_PECI <6> KB_RST# <31> H_CPUPWRGD <6>

R175 56_0402_1%~DR175 56_0402_1%~D

WW46 Platform/Design Updates 2008/11/17 54.9 1% ->56 5%

@

PAD

T6

12

H_THERMTRIP#THRMTRIP_PCH#

+1.1VS_VTT

GATEA20 KB_RST#

12

R183 56_0402_1%~DR183 56_0402_1%~D

R184

330_0402_5%~D@

1 2

H_THERMTRIP#

R101 10K_0402_5%~DR101 10K_0402_5%~D

1 2

R121 10K_0402_5%~DR121 10K_0402_5%~D

1 2

H_THERMTRIP# <6>

+1.1VS_VTT

MAINPWON <39,50,56>

1

C

Q51

2

B

E

2SC2411K_SOT23

3

@

+3VS

A A

Security Classification

2009/07/29 2010/07/29

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/07/29 2010/07/29

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SCHEMATICS, MB A5155

Size Document Number Rev

Custom

401808

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

20 57Monday, September 21, 2009

of

1

of

A

5

4

3

2

1

+1.05VS

POWER

U47G

10U_0805_10V4Z~D

D D

All Ibex Peak-M Power rails with netnames +1.1VS and +1.1V rails are actually +1.05VS and +1.05V rails

Intel suggest follow CRB 8/21

+1.05VS

1uH inductor, 405mA

DG 0.8 is 1uH Inductor (Page 291)

C C

10U_0805_10V4Z~D

C114

Top Side

Have Internal VRM (DG0.8 Page 293)

+1.05VS

1

2

Near AN20

C80

1U_0402_6.3V4Z~D

1

2

1U_0402_6.3V4Z~D

C85

1

2

1

2

Near AB24 Top Side

L81

@L81

@

1 2

1UH_CBC2012T1R0M_20%~D

C90

1U_0402_6.3V4Z~D

Near AN35

Follow Intel suggestion 8/21

B B

+1.05VS

L40 0_0805_5%~D

1uH inductor, 405mA Change to 0 ohm

for discrete

DG 0.8 is 1uH Inductor (Page 291) Have Internal VRM (DG0.8 Page 293)

C94

12

C978

C978 10U_0805_10V4Z~D

10U_0805_10V4Z~D @

@

1U_0402_6.3V4Z~D

C107

C63

Near AB24

1U_0402_6.3V4Z~D

1

C83

2

0.1U_0402_16V4Z~D

12

+VCCVRM

1

2

1

2

+1.05VS

+VCCAPLL_EXP

1

C1029

C1029 @

@

10U_0805_10V4Z~D

2

1

2

+3VS

+VCCAPLL_FDI

+1.05VS

U47G

AB24

VCCCORE[1]

AB26

VCCCORE[2]

AB28

VCCCORE[3]

AD26

VCCCORE[4]

AD28

VCCCORE[5]

AF26

VCCCORE[6]

AF28

VCCCORE[7]

AF30

VCCCORE[8]

AF31

VCCCORE[9]

AH26

VCCCORE[10]

AH28

VCCCORE[11]

AH30

VCCCORE[12]

AH31

VCCCORE[13]

AJ30

VCCCORE[14]

AJ31

VCCCORE[15]

AK24

VCCIO[24]

42mA

BJ24

VCCAPLLEXP

AN20

VCCIO[25]

AN22

VCCIO[26]

AN23

VCCIO[27]

AN24

VCCIO[28]

AN26

VCCIO[29]

AN28

VCCIO[30]

BJ26

VCCIO[31]

BJ28

VCCIO[32]

AT26

VCCIO[33]

AT28

VCCIO[34]

AU26

VCCIO[35]

AU28

VCCIO[36]

AV26

VCCIO[37]

AV28

VCCIO[38]

AW26

VCCIO[39]

AW28

VCCIO[40]

BA26

VCCIO[41]

BA28

VCCIO[42]

BB26

VCCIO[43]

BB28

VCCIO[44]

BC26

VCCIO[45]

BC28

VCCIO[46]

BD26

VCCIO[47]

BD28

VCCIO[48]

BE26

VCCIO[49]

BE28

VCCIO[50]

BG26

VCCIO[51]

BG28

VCCIO[52]

BH27

VCCIO[53]

AN30

VCCIO[54]

AN31

VCCIO[55]

AN35

VCC3_3[1]

AT22

VCCVRM[1]

BJ18

VCCFDIPLL

AM23

VCCIO[1]

IBEXPEAK-M_FCBGA1071~D

POWER

1524mA

3208mA

35mA

6mA

69mA

CRTLVDS

VCC CORE

HVCMOS

DMI

PCI E*

NAND / SPI

FDI

REV1.0

VCCADAC[1]

VCCADAC[2] VSSA_DAC[1] VSSA_DAC[2]

300mA

VCCALVDS

VSSA_LVDS

59mA

VCCTX_LVDS[1] VCCTX_LVDS[2] VCCTX_LVDS[3] VCCTX_LVDS[4]

VCC3_3[2] VCC3_3[3] VCC3_3[4]

35mA

VCCVRM[2]

61mA

VCCDMI[1] VCCDMI[2]

156mA

VCCPNAND[1] VCCPNAND[2] VCCPNAND[3] VCCPNAND[4] VCCPNAND[5] VCCPNAND[6] VCCPNAND[7] VCCPNAND[8] VCCPNAND[9]

85mA

VCCME3_3[1] VCCME3_3[2] VCCME3_3[3] VCCME3_3[4]

+VCCADAC

AE50 AE52 AF53 AF51

AH38 AH39

AP43 AP45 AT46 AT45

AB34 AB35 AD35

1

C58

0.1U_0402_16V4Z~D

2

+VCCVRM

AT24

AT16

+VCC_DMI

AU16

AM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM15

AM8 AM9 AP11 AP9

0.01U_0402_16V7K~D

12

C72

R125

R125 0_0402_5%~D

0_0402_5%~D @

@

+3VS

Near AB34

R174 0_0805_5%~D@R174 0_0805_5%~D@

1 2

R182 0_0805_5%~D@R182 0_0805_5%~D@

1 2

R188 0.022_0805_1%~OKR188 0.022_0805_1%~OK

1 2

1

C95

C95 1U_0402_6.3V4Z~D

1U_0402_6.3V4Z~D

2

Near AT16

1

C79

0.1U_0402_16V4Z~D

2

Near AK13

+3VS

1

C97

0.1U_0402_16V4Z~D

2

Near AM8

1

C69

0.1U_0402_16V4Z~D

2

R181 0.022_0805_1%~OKR181 0.022_0805_1%~OK

1 2

R189 0.022_0805_1%~OK@R189 0.022_0805_1%~OK@

1 2

R138 0.022_0805_1%~OKR138 0.022_0805_1%~OK

1 2

1

2

Near AE50

+1.05VS +1.5VS +1.8VS

60mA

1

C64

C64 10U_0805_10V4Z~D

10U_0805_10V4Z~D

2

+1.1VS_VTT

+1.05VS

+1.8VS+VCCQ_NAND

1 2

L9

L9 MBK1608601YZF_2P

MBK1608601YZF_2P

600 ohm bead,350mA

+3VS

CRB 0.9 is 180 ohm @ 100MHz DG0.8 is 600 ohm FB (Page 290)

A A

Security Classification

2009/07/29 2010/07/29

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/07/29 2010/07/29

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

1

A

21 57Monday, September 21, 2009

of

5

+1.05VS

L13

@L13

DG 0.8 is 10uH Inductor (Page 290) Have Internal VRM (DG0.8 Page 293)

+1.05VS

R124

@R124

@

1 2

0_0603_5%~D

D D

0_0402_5%~D

10uH inductor, 120mA

12

R131

@

1 2

10UH_LB2012T100MR_20%~D

C92

C92 10U_0805_10V4Z~D

10U_0805_10V4Z~D @

@

1

C65

C65 1U_0402_6.3V4Z~D

1U_0402_6.3V4Z~D

2

@

Near AF23

+1.05VS

22U_0805_6.3V6M~OK

1

C48

2

22U_0805_6.3V6M~OK

All Ibex Peak-M Power rails with netnames +1.1VS and +1.1V rails are actually +1.05VS and +1.05V rails

1

C60

2

Near AD38 Near V39

Follow Intel suggestion

1

C70

2

1U_0402_6.3V4Z~D

C40

C40 22U_0805_6.3V6M~OK

22U_0805_6.3V6M~OK

Near V9

C C

+1.05VS

1

C73

1U_0402_6.3V4Z~D

Near AH35

B B

A A

5

2

+1.1VS_VTT

C113

4.7U_0805_10V4Z~D

+RTCVCC

1U_0402_6.3V4Z~D

1

C74

2

1U_0402_6.3V4Z~D

+3V

0.1U_0402_16V4Z~D

+3VS

0.1U_0402_16V4Z~D

1

C89

2

0.1U_0402_16V4Z~D

1

C24

C19

2

0.1U_0402_16V4Z~D

4

+1.1VS_VCCACLK

1

C86

C86 1U_0402_6.3V4Z~D

1U_0402_6.3V4Z~D

2

@

Near AP51

+PCH_VCCD6W

1

C57

0.1U_0402_16V4Z~D

2

Near Y20

1

C49

2

1U_0402_6.3V4Z~D

C51

0.1U_0402_16V4Z~D

1 2

+VCCVRM

+VCCADPLLA

+VCCADPLLB

Near AH23Near AF32

1

C78

C78 1U_0402_6.3V4Z~D

1U_0402_6.3V4Z~D

2

1 2

C50

0.1U_0402_16V4Z~D

1 2

C56

0.1U_0402_16V4Z~D

1

C46

2

Near P18

1

C53

2

Near V15

1

C99

0.1U_0402_16V4Z~D

2

1

C25

0.1U_0402_16V4Z~D

2

4

1

2

1

2

+VCCRTCEXT

+VCCSST

Near V12

+VCCSUS

Near Y22

1

2

Near AT18

1

2

Near A12

3

POWER

U47J

52mA

AP51

VCCACLK[1]

AP53

VCCACLK[2]

344mA

AF23

VCCLAN[1]

AF24

VCCLAN[2]

Y20

DCPSUSBYP

1998mA

AD38

VCCME[1]

AD39

VCCME[2]

AD41

VCCME[3]

AF43

VCCME[4]

AF41

VCCME[5]

AF42

VCCME[6]

V39

VCCME[7]

V41

VCCME[8]

V42

VCCME[9]

Y39

VCCME[10]

Y41

VCCME[11]

Y42

VCCME[12]

V9

DCPRTC

AU24

VCCVRM[3]

BB51

VCCADPLLA[1]

BB53

VCCADPLLA[2]

BD51

VCCADPLLB[1]

BD53

VCCADPLLB[2]

AH23

VCCIO[21]

AJ35

VCCIO[22]

AH35

VCCIO[23]

AF34

VCCIO[2]

AH34

VCCIO[3]

AF32

VCCIO[4]

V12

DCPSST

Y22

DCPSUS

P18

VCCSUS3_3[29]

U19

VCCSUS3_3[30]

U20

VCCSUS3_3[31]

U22

VCCSUS3_3[32]

V15

VCC3_3[5]

V16

VCC3_3[6]

Y16

VCC3_3[7]

> 1mA

AT18

V_CPU_IO[1]

AU18

V_CPU_IO[2]

2mA

A12

VCCRTC

IBEXPEAK-M_FCBGA1071~D

POWER

REV1.0

VCCSUS3_3[1] VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5] VCCSUS3_3[6] VCCSUS3_3[7] VCCSUS3_3[8]

VCCSUS3_3[9] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13]

USB

VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16]

163mA

VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20] VCCSUS3_3[21] VCCSUS3_3[22] VCCSUS3_3[23] VCCSUS3_3[24] VCCSUS3_3[25] VCCSUS3_3[26] VCCSUS3_3[27]

VCCSUS3_3[28]

>1mA

V5REF_SUS

72mA

Clock and Miscellaneous

73mA

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Clock and Miscellaneous

PCI/GPIO/LPC

SATA

PCI/GPIO/LPC

CPU

RTC

Issued Date

HDA

VCC3_3[10] VCC3_3[11] VCC3_3[12] VCC3_3[13]

VCC3_3[14]

VCCSATAPLL[1] VCCSATAPLL[2]

VCCVRM[4]

VCCME[13] VCCME[14] VCCME[15] VCCME[16]

VCCSUSHDA

3

V24

VCCIO[5]

V26

VCCIO[6]

Y24

VCCIO[7]

Y26

VCCIO[8]

V28 U28 U26 U24 P28 P26 N28 N26 M28 M26 L28 L26 J28 J26 H28 H26 G28 G26 F28 F26 E28 E26 C28 C26 B27 A28 A26

U23 V23

VCCIO[56]

F24

>1mA

K49

V5REF

357mA

J38

VCC3_3[8]

L38

VCC3_3[9]

M36 N36 P36 U35

AD13

32mA

AK3 AK1

AH22

VCCIO[9]

AT20

AH19

VCCIO[10]

AD20

VCCIO[11]

AF22

VCCIO[12]

AD19

VCCIO[13]

AF20

VCCIO[14]

AF19

VCCIO[15]

AH20

VCCIO[16]

AB19

VCCIO[17]

AB20

VCCIO[18]

AB22

VCCIO[19]

AD22

VCCIO[20]

AA34 Y34 Y35 AA35

6mA

L30

2009/07/29 2010/07/29

+1.05VS

+VCC5REFSUS

+VCC5REF

Near J38

+VCCSATAPLL

PCH_VCCME13 PCH_VCCME14 PCH_VCCME15 PCH_VCCME16

Compal Secret Data

1

C54

C54 1U_0402_6.3V4Z~D

1U_0402_6.3V4Z~D

2

Near V24

1

C1031

0.1U_0402_16V4Z~D

2

Near A26

+3V

D48

21

CH751H-40PT_SOD323-2~D

1 2

C28

12

1U_0402_6.3V6K~D

Near F24

Change to 1U for power sequence issue on ICH9

+3VS

1

C38

0.1U_0402_16V4Z~D

2

1 2

C84

+1.05VS

C37 1U_0402_6.3V4Z~DC37 1U_0402_6.3V4Z~D

Deciphered Date

C84 10U_0805_10V4Z~D

10U_0805_10V4Z~D @

@

+VCCVRM

+1.05VS

1

C66

C66 1U_0402_6.3V4Z~D

1U_0402_6.3V4Z~D

2

Near AB19

R118 0_0603_5%~DR118 0_0603_5%~D

1 2

R92 0_0603_5%~DR92 0_0603_5%~D

1 2

R102 0_0603_5%~DR102 0_0603_5%~D

1 2

R109 0_0603_5%~DR109 0_0603_5%~D

1 2

2

+1.05VS

+3V

1

C47

0.1U_0402_16V4Z~D

2

Near U23

R49

R49 10_0402_5%~D

10_0402_5%~D

+3VS

Near AD13

C67

0.1U_0402_16V4Z~D

1

2

+1.05VS

+3V

Near L30

2

Follow Intel Suggestion 8/21

+5V

Near K49

L84

@L84

@

1 2

10UH_LB2012T100MR_20%~D

1

10uH inductor, 120mA

C75

C75 1U_0402_6.3V4Z~D

1U_0402_6.3V4Z~D

2

@

Near AK1

1

12

Near BD51

+5VALW

S

G

D

1 3

+5V

22 57Monday, September 21, 2009

of

+VCCADPLLA

R569

R569 0_0402_5%~D

0_0402_5%~D @

@

+VCCADPLLB

+1.05VS

1

+

2

1

+

2

+5VS

R1156

R1156 0_0402_5%~D

0_0402_5%~D

12

C1074

Near BB51

1

C104

C104 1U_0402_6.3V4Z~D

1U_0402_6.3V4Z~D

2

1

C109

C109 1U_0402_6.3V4Z~D

1U_0402_6.3V4Z~D

2

Q62

1

AO3413_SOT23-3

2

1

L82

1 2

10UH_LB2012T100MR_20%~D

10uH inductor, 120mA

C1030

220U_D2_4VM_R15~D

L83

1 2

10UH_LB2012T100MR_20%~D

10uH inductor, 120mA

C1032

220U_D2_4VM_R15~D

+3VS

21

D49

D49 CH751H-40PT_SOD323-2~D

CH751H-40PT_SOD323-2~D

R97

R97 10_0402_5%~D

10_0402_5%~D

1 2

C36

12

1U_0402_6.3V6K~D

SBPWR_EN#<33>

Title

SCHEMATICS, MB A5155

Size Document Number Rev

Custom

401808

Date: Sheet

Follow Intel Suggestion 8/21

+1.05VS

DG 0.8 is 10uH Inductor (Page 291) Have Internal VRM (DG0.8 Page 293)

0.1U_0402_16V4Z~D

Compal Electronics, Inc.

A

5

U47I

AY7

VSS[159]

B11

VSS[160]

B15

VSS[161]

B19

VSS[162]

B23

VSS[163]

B31

VSS[164]

B35

VSS[165]

B39

VSS[166]

B43

VSS[167]

B47

VSS[168]

B7

VSS[169]

D D

C C

B B

A A

BG12

VSS[170]

BB12

VSS[171]

BB16

VSS[172]

BB20

VSS[173]

BB24

VSS[174]

BB30

VSS[175]

BB34

VSS[176]

BB38

VSS[177]

BB42

VSS[178]

BB49

VSS[179]

BB5

VSS[180]

BC10

VSS[181]

BC14

VSS[182]

BC18

VSS[183]

BC2

VSS[184]

BC22

VSS[185]

BC32

VSS[186]

BC36

VSS[187]

BC40

VSS[188]

BC44

VSS[189]

BC52

VSS[190]

BH9

VSS[191]

BD48

VSS[192]

BD49

VSS[193]

BD5

VSS[194]

BE12

VSS[195]

BE16

VSS[196]

BE20

VSS[197]

BE24

VSS[198]

BE30

VSS[199]

BE34

VSS[200]

BE38

VSS[201]

BE42

VSS[202]

BE46

VSS[203]

BE48

VSS[204]

BE50

VSS[205]

BE6

VSS[206]

BE8

VSS[207]

BF3

VSS[208]

BF49

VSS[209]

BF51

VSS[210]

BG18

VSS[211]

BG24

VSS[212]

BG4

VSS[213]

BG50

VSS[214]

BH11

VSS[215]

BH15

VSS[216]

BH19

VSS[217]

BH23

VSS[218]

BH31

VSS[219]

BH35

VSS[220]

BH39

VSS[221]

BH43

VSS[222]

BH47

VSS[223]

BH7

VSS[224]

C12

VSS[225]

C50

VSS[226]

D51

VSS[227]

E12

VSS[228]

E16

VSS[229]

E20

VSS[230]

E24

VSS[231]

E30

VSS[232]

E34

VSS[233]

E38

VSS[234]

E42

VSS[235]

E46

VSS[236]

E48

VSS[237]

E6

VSS[238]

E8

VSS[239]

F49

VSS[240]

F5

VSS[241]

G10

VSS[242]

G14

VSS[243]

G18

VSS[244]

G2

VSS[245]

G22

VSS[246]

G32

VSS[247]

G36

VSS[248]

G40

VSS[249]

G44

VSS[250]

G52

VSS[251]

AF39

VSS[252]

H16

VSS[253]

H20

VSS[254]

H30

VSS[255]

H34

VSS[256]

H38

VSS[257]

H42

VSS[258]

IBEXPEAK-M_FCBGA1071~D

REV1.0

5

VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[326] VSS[327] VSS[328] VSS[329] VSS[330] VSS[331] VSS[332] VSS[333] VSS[334] VSS[335] VSS[336] VSS[337] VSS[338] VSS[339] VSS[340] VSS[341] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352] VSS[353] VSS[354] VSS[355] VSS[356] VSS[366]

H49 H5 J24 K11 K43 K47 K7 L14 L18 L2 L22 L32 L36 L40 L52 M12 M16 M20 N38 M34 M38 M42 M46 M49 M5 M8 N24 P11 AD15 P22 P30 P32 P34 P42 P45 P47 R2 R52 T12 T41 T46 T49 T5 T8 U30 U31 U32 U34 P38 V11 P16 V19 V20 V22 V30 V31 V32 V34 V35 V38 V43 V45 V46 V47 V49 V5 V7 V8 W2 W52 Y11 Y12 Y15 Y19 Y23 Y28 Y30 Y31 Y32 Y38 Y43 Y46 P49 Y5 Y6 Y8 P24 T43 AD51 AT8 AD47 Y47 AT12 AM6 AT13 AM5 AK45 AK39 AV14

4

U47H

AB16

VSS[0]

AA19

VSS[1]

AA20

VSS[2]

AA22

VSS[3]

AM19

VSS[4]

AA24

VSS[5]

AA26

VSS[6]

AA28

VSS[7]

AA30

VSS[8]

AA31

VSS[9]

AA32

VSS[10]

AB11

VSS[11]

AB15

VSS[12]

AB23

VSS[13]

AB30

VSS[14]

AB31

VSS[15]

AB32

VSS[16]

AB39

VSS[17]

AB43

VSS[18]

AB47

VSS[19]

AB5

VSS[20]

AB8

VSS[21]

AC2

VSS[22]

AC52

VSS[23]

AD11

VSS[24]

AD12

VSS[25]

AD16

VSS[26]

AD23

VSS[27]

AD30

VSS[28]

AD31

VSS[29]

AD32

VSS[30]

AD34

VSS[31]

AU22

VSS[32]

AD42

VSS[33]

AD46

VSS[34]

AD49

VSS[35]

AD7

VSS[36]

AE2

VSS[37]

AE4

VSS[38]

AF12

VSS[39]

Y13

VSS[40]

AH49

VSS[41]

AU4

VSS[42]

AF35

VSS[43]

AP13

VSS[44]

AN34

VSS[45]

AF45

VSS[46]

AF46

VSS[47]

AF49

VSS[48]

AF5

VSS[49]

AF8

VSS[50]

AG2

VSS[51]

AG52

VSS[52]

AH11

VSS[53]

AH15

VSS[54]

AH16

VSS[55]

AH24

VSS[56]

AH32

VSS[57]

AV18

VSS[58]

AH43

VSS[59]

AH47

VSS[60]

AH7

VSS[61]

AJ19

VSS[62]

AJ2

VSS[63]

AJ20

VSS[64]

AJ22

VSS[65]

AJ23

VSS[66]

AJ26

VSS[67]

AJ28

VSS[68]

AJ32

VSS[69]

AJ34

VSS[70]

AT5

VSS[71]

AJ4

VSS[72]

AK12

VSS[73]

AM41

VSS[74]

AN19

VSS[75]

AK26

VSS[76]

AK22

VSS[77]

AK23

VSS[78]

AK28

VSS[79]

IBEXPEAK-M_FCBGA1071~D

4

3

AK30

VSS[80]

AK31

VSS[81]

AK32

VSS[82]

AK34

VSS[83]

AK35

VSS[84]

AK38

VSS[85]

AK43

VSS[86]

AK46

VSS[87]

AK49

VSS[88]

AK5

VSS[89]

AK8

VSS[90]

AL2

VSS[91]

AL52

VSS[92]

AM11

VSS[93]

BB44

VSS[94]

AD24

VSS[95]

AM20

VSS[96]

AM22

VSS[97]

AM24

VSS[98]

AM26

VSS[99]

AM28

VSS[100]

BA42

VSS[101]

AM30

VSS[102]

AM31

VSS[103]

AM32

VSS[104]

AM34

VSS[105]

AM35

VSS[106]

AM38

VSS[107]

AM39

VSS[108]

AM42

VSS[109]

AU20

VSS[110]

AM46

VSS[111]

AV22

VSS[112]

AM49

VSS[113]

AM7

VSS[114]

AA50

VSS[115]

BB10

VSS[116]

AN32

VSS[117]

AN50

VSS[118]

AN52

VSS[119]

AP12

VSS[120]

AP42

VSS[121]

AP46

VSS[122]

AP49

VSS[123]

AP5

VSS[124]

AP8

VSS[125]

AR2

VSS[126]

AR52

VSS[127]

AT11

VSS[128]

BA12

VSS[129]

AH48

VSS[130]

AT32

VSS[131]

AT36

VSS[132]

AT41

VSS[133]

AT47

VSS[134]

AT7

VSS[135]

AV12

VSS[136]

AV16

VSS[137]

AV20

VSS[138]

AV24

VSS[139]

AV30

VSS[140]

AV34

VSS[141]

AV38

VSS[142]

AV42

VSS[143]

AV46

VSS[144]

AV49

VSS[145]

AV5

VSS[146]

AV8

VSS[147]

AW14

VSS[148]

AW18

VSS[149]

AW2

VSS[150]

BF9

VSS[151]

AW32

VSS[152]

AW36

VSS[153]

AW40

VSS[154]

AW52

VSS[155]

AY11

VSS[156]

AY43

VSS[157]

REV1.0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

VSS[158]

AY47

(XDP_FN3)

(XDP_FN5) (XDP_FN6)

(XDP_FN7)

SYS_PWROK<17>

PBTN_OUT#<6,17,31>

2009/07/29 2010/07/29

3

USB_OC3#<19>

USB_OC5#<19> USB_OC6#<19>

USB_OC7#<19>

1 2

+3VS

Compal Secret Data

R484 0_0402_5%~DR484 0_0402_5%~D

SMB_DATA_S3<6> SMB_CLK_S3<6>

Deciphered Date

USB_OC0#_R<19> USB_OC1#_R<19> USB_OC2#_R<19>

USB_OC4#<19>

PCH_GPIO20<16> PCH_GPIO18<16>

PCH_GPIO21<15> PCH_GPIO19<15>

PCH_JTAG_TCK<15> PCH_JTAG_TMS<15> PCH_JTAG_TDI<15>

PCH_JTAG_TDO<15>

PCH_JTAG_RST#<15>

XDP_FN0 XDP_FN1

XDP_FN2

XDP_FN4

PCH_JTAG_TCK_R

PCH_SMBDATA<11,12,16>

PCH_SMBCLK<11,12,16>

2

PCH XDP Port

R491 33_0402_5%~D@R491 33_0402_5%~D@

1 2

R1089 33_0402_5%~D@R1089 33_0402_5%~D@

1 2

R1090 33_0402_5%~D@R1090 33_0402_5%~D@

1 2

R1091 33_0402_5%~D@R1091 33_0402_5%~D@

1 2

R492 33_0402_5%~D@R492 33_0402_5%~D@

1 2

R490 33_0402_5%~D@R490 33_0402_5%~D@

1 2

R1092 33_0402_5%~D@R1092 33_0402_5%~D@

1 2

R1093 33_0402_5%~D@R1093 33_0402_5%~D@

1 2

R1094 0_0402_5%~DR1094 0_0402_5%~D

1 2

R1095 0_0402_5%~DR1095 0_0402_5%~D

1 2

R1096 0_0402_5%~DR1096 0_0402_5%~D

1 2

R482

JP2

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

2

1 2

R1097 0_0402_5%~D@R1097 0_0402_5%~D@

1 2

+3VS

2

1 3

D

+3VS

2

1 3

D

0_0402_5%~D

OBSFN_C0 OBSFN_C1

OBSDATA_C0 OBSDATA_C1

OBSDATA_C2 OBSDATA_C3

OBSFN_D0 OBSFN_D1

OBSDATA_D0 OBSDATA_D1

OBSDATA_D2 OBSDATA_D3

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

SAMTE_BSH-030-01-L-D-ACONN@

R480

4.7K_0402_5%~D

G

1 2

SMB_DATA_S3

S

Q52

Q52 2N7002LT1G_SOT23-3

2N7002LT1G_SOT23-3

R1099

4.7K_0402_5%~D

G

1 2

SMB_CLK_S3

S

Q53

Q53 2N7002LT1G_SOT23-3

2N7002LT1G_SOT23-3

Title

Size Document Number Rev

Custom

Date: Sheet

1

XDP_FN0 XDP_FN1 XDP_FN2

XDP_FN4

XDP_FN8 XDP_FN9 XDP_FN10 XDP_FN11

PCH_JTAG_TCK_R PCH_JTAG_TMS_R PCH_JTAG_TDI_R PCH_JTAG_TDO_R

PCH_JTAG_RST#_R

2

GND1

4 6 8

GND3

10 12 14

GND5

16 18 20

GND7

22 24 26

GND9

28 30 32

GND11

34 36 38

GND13

40 42 44 46 48 50

GND15

52

TD0

54

TRST#

56

TDI

58

TMS

60

GND17

+3VS

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

PCH_GPIO28 <20> PCH_GPIO0 <20>

XDP_FN8 XDP_FN9

XDP_FN10 XDP_FN11

PCH_GPIO36 <20> PCH_GPIO37 <20>

PCH_GPIO16 <20> PCH_GPIO49 <20,31>

12

R1098

R1098 1K_0402_5%~D

1K_0402_5%~D

PCH_JTAG_TDO_R PCH_JTAG_RST#_R PCH_JTAG_TDI_R PCH_JTAG_TMS_R

+3VS

1

(XDP_FN16) (XDP_FN17)

(XDP_FN12) (XDP_FN13)

(XDP_FN14) (XDP_FN15)

PLT_RST# <6,19,24,27,28,30,31> XDP_DBRESET# <6,17>

A

23 57Monday, September 21, 2009

of

A

B

C

D

E

W=60mils

1U_0603_10V6K~D

R236

470K_0402_5%

LAN_CABDT<20>

LAN_CKTAL1

LAN_CKTAL2

33P_0402_50V8J~D

12

2

G

12 12

C319

1 1

PCIE_IRX_GLANTX_P6<16>

PCIE_IRX_GLANTX_N6<16> PCIE_ITX_C_GLANRX_P6<16> PCIE_ITX_C_GLANRX_N6<16>

2 2

LAN_LOPWEN<20>

33P_0402_50V8J~D

B+_BIAS

EN_WOL#<31>

CLK_PCIE_GLAN<16> CLK_PCIE_GLAN#<16>

GLAN_CLKREQ#<16>

ICH_PCIE_WAKE#<17,27,28,31>

R240 1K_0402_5%~DR240 1K_0402_5%~D

+3VS

25MHZ_20P_1BX25000CK1A

1 2

R241 0_0402_5%~D@R241 0_0402_5%~D@

1 2

R242 15K_0402_5%R242 15K_0402_5%

1 2

Y3

1 2

C318

C304 0.1U_0402_16V7K~DC304 0.1U_0402_16V7K~D C305 0.1U_0402_16V7K~DC305 0.1U_0402_16V7K~D

PLT_RST#<6,19,23,27,28,30,31>

+3VALW

1

C284

2

EN_WOL

12

1.5M_0402_5%~D

13

D

S

1.5M_0402_5%~D

Q4

PMF3800SN_SC70-3

PCIE_IRX_C_GLANTX_P6 PCIE_IRX_C_GLANTX_N6 PCIE_ITX_C_GLANRX_P6 PCIE_ITX_C_GLANRX_N6

R239 2.49K_0402_1%R239 2.49K_0402_1%

1 2

R1033 0_0402_5%~D

1 2

@

R1142

6 2

1

ISOLATEB LAN_CKTAL1

LAN_CKTAL2

FBMA-L11-322513-201LMA40T_1210

D

S

45

Q3

G

SI3456BDV-T1-E3_TSOP6~D

3

1

C958

C958 2200P_0402_50V7K~D

2200P_0402_50V7K~D

2

20 21 15 16 17

18 25 27

46 26

28 41

42

23 24

14 31 47

22

R0.3 Modify

L10

1 2

U9

HSOP HSON HSIP HSIN REFCLK_P

REFCLK_N CLKREQB PERSTB

RSET LANWAKEB

ISOLATEB CKTAL1

CKTAL2

GPO NC

7

GND GND GND GND

EGND

RTL8111DL-GR_LQFP48_7X7

1

2

RTL8111DL

W=60mils

C285

@

22U_1206_6.3V6M~D

1

2

+LAN_IO

C286

1

2

LED3/EEDO

LED2/EEDI/AUX

LED1/EESK

MDIP0 MDIN0 MDIP1 MDIN1 MDIP2 MDIN2 MDIP3 MDIN3

SROUT12

EVDD12 DVDD12 DVDD12 DVDD12 AVDD12

AVDD12

VDDSR VDDSR

VDD33 VDD33

AVDD33 AVDD33

0.1U_0402_10V6K~D

EECS

LED0

FB12

ENSR

C287

3.6K_0402_5%

LAN_LED3

33

LAN_LED2

34

LAN_LED1

35 32

LAN_LED0

38

LAN_MDIP0

2

LAN_MDIN0

3

LAN_MDIP1

5

LAN_MDIN1

6

LAN_MDIP2

8

LAN_MDIN2

9

LAN_MDIP3

11

LAN_MDIN3

12 4 48 19

30 36 13 10

39 44

45 29

37 1

40 43

+LAN_IO

12

R947

+LAN_DVDD12

W=60mils

W=40mils

+LAN_IO

W=60mils

L11

4.7UH_1008HC-472EJFS-A_5%_1008

1 2

0.1U_0402_10V6K~D

C306

1

2

1

C307

C307 22U_1206_6.3V6M~D

22U_1206_6.3V6M~D

2

These components close to U9: Pin 48 ( Should be place within 200 mils )

W=30mils W=30mils

C310 1U_0603_10V6K~DC310 1U_0603_10V6K~D C311 1U_0603_10V6K~DC311 1U_0603_10V6K~D

1 2 1 2

R884

0_0603_5%~D

12

These caps close to U9: Pin 19

+LAN_DVDD12

C292

0.1U_0402_10V6K~D

C292

0.1U_0402_10V6K~D

C293

0.1U_0402_10V6K~D

C293

0.1U_0402_10V6K~D 1

1

2

C296

0.1U_0402_10V6K~D

+LAN_DVDD12 C295

0.1U_0402_10V6K~D

C295

0.1U_0402_10V6K~D

1

2

C294

0.1U_0402_10V6K~D

C294

0.1U_0402_10V6K~D

1

2

These caps close to U9: Pin 10, 13, 30, 36, 39

These caps close to U9: Pin 44.45 ( Should be place within 200 mils )

C308

22U_1206_6.3V6M~D

C308

22U_1206_6.3V6M~D

1

2

R942 0_0805_5%~DR942 0_0805_5%~D

1

C309

0.1U_0402_10V6K~D

2

+LAN_VDD

1

2

12

R235

0_0603_5%~D

12

+LAN_IO

+LAN_VDD

These caps close to U9: Pin 4

+LAN_DVDD12

1

2

R246

R245

2

1

+LAN_IO

C302

@C302

@

0.1U_0402_10V6K~D

220_0402_5%~D

LAN_LED0 LAN_ACTIVITY#

1 2

R244

R244 220_0402_5%~D

220_0402_5%~D

LED1_LED3 LINK_100_1000#

1 2

+LAN_IO

220_0402_5%~D

LED2_LED3 LINK_10_1000#

1 2

C303

@C303

@

0.01U_0402_16V7K~D

RJ45_TX3RJ45_TX3+ RJ45_RX1RJ45_TX2RJ45_TX2+ RJ45_RX1+ RJ45_TX0RJ45_TX0+

LINK OK

JRJ45

13

Yellow LED-

12

Yellow LED+

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

11

Orange LED-

10

Yellow LED+

9

Green LED-

FOX_JM3611A-R4953B-7F

CONN@

GND GND

14 15

3 3

TS1

C320 0.01U_0402_16V7K~DC320 0.01U_0402_16V7K~D

1 2

C321 0.01U_0402_16V7K~DC321 0.01U_0402_16V7K~D

1 2

C322 0.01U_0402_16V7K~DC322 0.01U_0402_16V7K~D

1 2

C324 0.01U_0402_16V7K~DC324 0.01U_0402_16V7K~D

1 2

4 4

A

V_DAC LAN_MDIN3 LAN_MDIP3

V_DAC LAN_MDIN2 LAN_MDIP2

V_DAC LAN_MDIN1 LAN_MDIP1

V_DAC LAN_MDIN0 LAN_MDIP0

TS1

1

TCT1

2

TD1+

3

TD1-

4

TCT2

5

TD2+ TD2-6MX2-

7

TCT3

8

TD3+

9

TD3-

10

TCT4

11

TD4+

12

TD4-

BOTH_GST5009-LF

LEDS1-0

LED0

LED1

LED2

LED3

24

MCT1 MX1+

MX1-

MCT2 MX2+

MCT3 MX3+

MX3-

MCT4 MX4+

MX4-

RJ45_TX3-

23

RJ45_TX3+

22 21

RJ45_TX2-

20

RJ45_TX2+

19 18

RJ45_RX1-

17

RJ45_RX1+

16 15

RJ45_TX0-

14

RJ45_TX0+

13

0 0 0 1 1 0 1 1

Tx / Rx

LINK100

LINK10

LINK1000

Tx / Rx

LINK10 /100 / 1000

LINK10 / 100

LINK1000

B

RP1

45 36 27 18

75_1206_8P4R_5%

Tx

LINK

Rx

FULL

2

C323

C323 1000P_1206_2KV7K

1000P_1206_2KV7K

1

LINK10 / ACT

LINK100 / ACT

FULL

LINK1000 / ACT

D4

LAN_LED2

CH751H-40PT_SOD323-2~D

D5

LAN_LED3

CH751H-40PT_SOD323-2~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

These caps close to U9: Pin 1.29, 37, 40

C289

0.1U_0402_10V6K~D

C289

0.1U_0402_10V6K~D

C288

0.1U_0402_10V6K~D

C288

0.1U_0402_10V6K~D

1

2

21

2009/07/29 2010/07/29

LAN_LED1

LAN_LED3

CH751H-40PT_SOD323-2~D

Compal Secret Data

+LAN_IO

C290

0.1U_0402_10V6K~D

C290

0.1U_0402_10V6K~D

C291

0.1U_0402_10V6K~D

C291

0.1U_0402_10V6K~D

1

2

D6

LED1_LED3LED2_LED3

CH751H-40PT_SOD323-2~D

21

D7

21

Deciphered Date

D

12/11 reserve for EMI as Dell Tony request.

LAN_MDIN3 LAN_MDIP3 LAN_MDIN1 LAN_MDIN2 LAN_MDIP2 LAN_MDIP1 LAN_MDIN0 LAN_MDIP0

C873 6.8PF_0402_50V9~DC873 6.8PF_0402_50V9~D

1 2

C874 6.8PF_0402_50V9~DC874 6.8PF_0402_50V9~D

1 2

C875 6.8PF_0402_50V9~DC875 6.8PF_0402_50V9~D

1 2

C876 6.8PF_0402_50V9~DC876 6.8PF_0402_50V9~D

1 2

C877 6.8PF_0402_50V9~DC877 6.8PF_0402_50V9~D

1 2

C878 6.8PF_0402_50V9~DC878 6.8PF_0402_50V9~D

1 2

C879 6.8PF_0402_50V9~DC879 6.8PF_0402_50V9~D

1 2

C880 6.8PF_0402_50V9~DC880 6.8PF_0402_50V9~D

1 2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

of

24 57Monday, September 21, 2009

E

24 57Monday, September 21, 2009

A

R0.3 Modify

R1217 20K_0402_1%~DR1217 20K_0402_1%~D

1 2

+3VS

EC_SPK_HP_MUTE#<31>

1 1

EC_SUB_MUTE#<31>

EA_EC_SPK_MUTE# HP_JD

EA_EC_SUB_MUTE#

2 2

HP_JD

3 3

MIC_JD

2N7002DW-7-F_SOT363-6~D

4 4

+3VS

HP1_JD HP2_JD

R1220

10K_0402_5%~D

HP_JD

2

G

SENSE_B

+3VS +3VS

100K_0402_5%~D

12

R978

SENSE_A

+3VS

100K_0402_5%~D

12

HP1_JD

EAPD#

EC_SPK_HP_MUTE#

1 2

R1218 10K_0402_5%~DR1218 10K_0402_5%~D

EAPD#

EC_SUB_MUTE#

1 2

R1219 10K_0402_5%~DR1219 10K_0402_5%~D

+3VS

C1117

1 2

0.1U_0402_10V6K~D

5

U58

1

P

IN1

4

O

2

IN2

G

74AHC1G08GW_SOT353-5~D

3

+3VS

C1118

1 2

0.1U_0402_10V6K~D

5

U59

1

P

IN1

4

O

2

IN2

G

74AHC1G08GW_SOT353-5~D

3

+3VS

C1075

0.1U_0402_10V6K~D

1 2

5

U53

1

P

INB

4

Y

2

INA

G

TC7SZ02FU_SSOP5

3

12

EA_EC_SPK_MUTE#

HP_JD#

13

D

Q69

Q69 PMF3800SN_SC70-3

PMF3800SN_SC70-3

S

20K_0402_1%~D

39.2K_0402_1%

12

R546

R547

61

3

2

Q42A

R971

Q42A

A

2

G

Q42B

4

2N7002DW-7-F_SOT363-6~D

1

39.2K_0402_1%

12

R544

2

13

D

Q43

Q43 PMF3800SN_SC70-3

PMF3800SN_SC70-3

S

1 2

SPK_AMP_MUTE# <26>

DMIC_CLK<30>

SUB_AMP_MUTE# <26>

HP_JD

1

IN1

2

IN2

R545

5.1K_0402_1%~D

1 2

1000P_0402_50V7K~D

1

C866

2

5

+AVDD_AUDIO

R543

5.1K_0402_1%~D

1 2

1000P_0402_50V7K~D

C865

B

+3VS

C1086

1 2

0.1U_0402_16V4Z~D

5

U56

P

IN1

EA_EC_SPK_MUTE#

4

O

IN2

G

74AHC1G08GW_SOT353-5~D

3

+3VS

C1087

1 2

5

0.1U_0402_16V4Z~D

U57

P

IN1

EA_EC_SUB_MUTE#

4

O

IN2

G

74AHC1G08GW_SOT353-5~D

3

HDA_BITCLK_AUDIO<15>

HDA_SDOUT_AUDIO<15>

HDA_SYNC_AUDIO<15>

HDA_RST_AUDIO#<15>

DMIC0<30>

+3VS+3VS

C1119

1 2

0.1U_0402_10V6K~D

5

U60

P

HP_AMP_MUTE#

4

O

G

74AHC1G08GW_SOT353-5~D

3

+AVDD_AUDIO

100K_0402_5%~D

12

R979

HP2_JD

BEEP#<31> PC_BEEP <26>

PCH_SPKR<15>

B

HDA_SDIN0<15>

1 2

R1240 0_0402_5%~DR1240 0_0402_5%~D

1 2

R1241 0_0402_5%~DR1241 0_0402_5%~D

2.2U_0805_10V7K~D

HP2_CD_R HP2_CD_L

2.2U_0805_10V7K~D

0.1U_0402_16V4Z~D

R247

0_0603_5%~D

1 2

R249 33_0402_5%~DR249 33_0402_5%~D

100P_0402_50V8J~D

@

C341

1

C342

2

EAPD#

Int. 60k pull up.

Reserved for TEST

GND AGND

C354

HP2_CD_L1

C355

C945

1 2

C946

BEEP_C#

SB_SPKR_C

499K_0402_1%~D

1 2

499K_0402_1%~D

C

+DVDD_AUDIO+3VS +5VS+AVDD_AUDIO

12

C326

0.1U_0402_10V6K~D

C326

0.1U_0402_10V6K~D

1

2

75mA

U11

6

HDA_SDIN0_R

SENSE_A SENSE_B

PC_BEEP

EAPD#

R268 0_0805_5%~DR268 0_0805_5%~D R269 0_0805_5%~D@R269 0_0805_5%~D@ R270 0_0805_5%~D@R270 0_0805_5%~D@

2K_0402_1%~D

1 2 1 2

2K_0402_1%~D

R264

R266

C

BITCLK

8

SDI_CODEC

5

SDO

10

SYNC

11

RESET#

2

VOL_UP/DMIC_CLK/GPIO1

4

VOL_DN/DMIC_0/GPIO2

30

DMIC1/GPIO5

13

SENSE_A

34

SENSE_B

32

SENSE_C

12

PCBEEP

47

EAPD/SPDIF IN/GPIO0

18

PORTI_L

19

PORTI_C

20

PORTI_R

7

DVSS

26

AVSS1

42

AVSS2

92HD73C1X5PRGXC1X8_QFP48_7X7

1 2 1 2 1 2

C1120 270P_0402_50V7K~DC1120 270P_0402_50V7K~D

R1221

HP2_CD_R2HP2_CD_R1 HP2_CD_L2

C1121 270P_0402_50V7K~DC1121 270P_0402_50V7K~D

R1222

C358 1U_0603_10V4Z~DC358 1U_0603_10V4Z~D

1 2

PC_BEEP

R267

R267 10K_0402_5%~D@

10K_0402_5%~D@

1 2

C330

1U_0402_6.3V6K~D

C330

1U_0402_6.3V6K~D

1 2

0.1U_0402_10V6K~D

3

DVDD_IO

+3VS

C331

1

2

1

2

1

9

DVDD_CORE

D

+AVDD_AUDIO

C327

0.1U_0402_10V6K~D

C327

0.1U_0402_10V6K~D

C333

1U_0402_6.3V6K~D

C333

1U_0402_6.3V6K~D

C332

10U_0603_6.3V6M~D

C332

10U_0603_6.3V6M~D

38

AVDD125AVDD2

VREFOUT-A

VREFOUT-B

VREFOUT-C

VREFOUT-E

SPDIF OUT0

SPDIF OUT1/GPIO3

U12

U12 14 18

15 13

1 3

D

1

2

1

2

132mA

HP1_CD_L

39

PORTA_L PORTA_R

PORTB_L PORTB_R

PORTC_L PORTC_R

PORTD_L PORTD_R

PORTE_L PORTE_R

PORTF_L PORTF_R

PORTG_L

PORTG_R

PORTH_L PORTH_R

VREFFILT

CAP2

SHDNR# SHDNL#

INR INL

C1P C1N

C360

1U_0603_10V4Z~D

C360

1U_0603_10V4Z~D

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HP1_CD_R

41 37

21 22 28

23 24 29

SPK_CD_L

35

SPK_CD_R

36

MIC_CD_L

14

MIC_CD_R

15 31

HP2_CD_L

16

HP2_CD_R

17 43

44 45

46

R1214 10K_0402_5%~DR1214 10K_0402_5%~D

D53

D53 CH751H-40PT_SOD323-2~D

CH751H-40PT_SOD323-2~D

48 40

1 2

R1163 0_0402_5%~D

27 33

1

C347

2

+3VS

2

1

10

19

SVDD

PVDD

PGND

PVss

SVss

SGND

2

5

7

17

1

2

Issued Date

Int. Speaker and Sub woofer

2 1

@

C351

C351 1U_0603_10V4Z~D

1U_0603_10V4Z~D

OUTR

OUTL

NC-12 NC-16 NC-20

MAX4411ETP+T_TQFN20_4X4

E

R248

12

0_0603_5%~D

C335

1U_0402_6.3V6K~D

C335

1U_0402_6.3V6K~D

C328

0.1U_0402_10V6K~D

C328

C334

10U_0603_6.3V6M~D

C334

10U_0603_6.3V6M~D

1 2

1U_0402_6.3V6K~D

PAD NC-4 NC-6 NC-8

0.1U_0402_10V6K~D

1

2

C336

2.2U_0805_10V7K~D

2.2U_0805_10V7K~D HP1_CD_R1HP1_CD_R

HP1_CD_L1HP1_CD_L

C337

2.2U_0805_10V7K~D

SPK_CD_L <26> SPK_CD_R <26>

R251

+MIC1_VREFO

2.2U_0603_10V7K~D

2.2U_0603_10V7K~D 1 2

1 2

2.2U_0603_10V7K~D

D32

1

PACDN042Y3R_SOT23-3~D@

68_0603_1%~D

1 2 1 2

68_0603_1%~D

D33

1

PACDN042Y3R_SOT23-3~D@

Deciphered Date

R251 68_0603_1%~D

68_0603_1%~D

1 2 1 2

R252

R252 68_0603_1%~D

68_0603_1%~D

C349

MIC_CD_L1 MIC_CD_R1

C350

3 2

R261

R262

3 2

+MIC1_VREFO

+3VS

1

C348

2

10U_0603_6.3V6M~D

HP2_AMP_R

11

HP2_AMP_LHP_AMP_MUTE#

9

21 4 6 8 12 16 20

2009/07/29 2010/07/29

E

Front

HP1_AMP_L HP1_AMP_L1_JKHP1_AMP_L1 HP1_AMP_R

ACIN <17,31,39,48,49>

+MIC1_VREFO W=10 mil

Rear or MIC

MIC_CD_R

Center

HP2_AMP_L HP2_AMP_L1_JKHP2_AMP_L1 HP2_AMP_R

Compal Secret Data

F

R1212

2K_0402_1%~D

1 2 1 2

R1213

2K_0402_1%~D

C338 1U_0603_10V4Z~DC338 1U_0603_10V4Z~D

HP1_AMP_R1 HP1_AMP_R1_JK

BLM18BD601SN1D_0603~D

Place close to Jack

D31

1

PACDN042Y3R_SOT23-3~D@

R256

4.7K_0402_5%~D

Place close to Jack

MIC_CD_L1_JK MIC_CD_R1_JK

HP2_AMP_R1 HP2_AMP_R1_JK

Place close to Jack

HP2_AMP_L1_JK HP2_AMP_R1_JK

F

C1107

C1107 270P_0402_50V7K~D

270P_0402_50V7K~D

1 2

HP1_CD_R2 HP1_CD_L2

C1108

C1108 270P_0402_50V7K~D

270P_0402_50V7K~D

1 2

L14

BLM18BD601SN1D_0603~D

1 2 1 2

L15

R0.3 Modify

HP1_AMP_L1_JK

3

HP1_AMP_R1_JK

2

1 2

C345 1000P_0402_50V7K~DC345 1000P_0402_50V7K~D

12

R257

4.7K_0402_5%~D

4.7K_0402_5%~D L16

L16

BLM18BD601SN1D_0603~D

1 2 1 2

L17

BLM18BD601SN1D_0603~D

L17

L19

BLM18BD601SN1D_0603~D

1 2 1 2

L18

BLM18BD601SN1D_0603~D

U10

14

SHDNR#

18

SHDNL#

15

INR

13

INL

1

C1P

3

C1N

C339

1U_0603_10V4Z~D

MIC_CD_L1_JKMIC_CD_L MIC_CD_R1_JK

R0.3 Modify

G

+3VS

2

C325

C325 1U_0603_10V4Z~D

1U_0603_10V4Z~D

1

10

19

HP1_AMP_R

11

OUTR

SVDD

PVDD

OUTL

PAD NC-4 NC-6 NC-8

NC-12 NC-16 NC-20

PGND

PVss

SVss

SGND

MAX4411ETP+T_TQFN20_4X4

2

5

7

17

12

HP1_JD

MIC_JD

HP2_JD

Title

Size Document Number Rev

Custom

Date: Sheet

1226 Modify

C343

1000P_0402_50V7K~D

C343

1000P_0402_50V7K~D

C344

1000P_0402_50V7K~D

C344

1000P_0402_50V7K~D

1

2

1226 Modify

100P_0402_50V8J~D

C352

100P_0402_50V8J~D

C352

100P_0402_50V8J~D

1

2

1226 Modify

C357

1000P_0402_50V7K~D

C357

1000P_0402_50V7K~D

C356

1000P_0402_50V7K~D

C356

1000P_0402_50V7K~D

1

2

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

G

C353

9

21 4 6 8 12 16 20

HP1_AMP_LHP_AMP_MUTE#

JHP1

JHP1 1 2 6 3

4 5

FOX_JA6333L-B5S4-7F

CONN@

JMIC1

JMIC1 1 2 6 3

4 5

FOX_JA6333L-B5S4-7F

CONN@

JHP2

JHP2 1 2 6 3

4 5

FOX_JA6333L-B5S4-7F

CONN@

H

SHLD1

SHLD1 SHLD2

SHLD2

NPTH1

NPTH1 NPTH2

NPTH2

25 57Monday, September 21, 2009

H

SHLD1

SHLD1 SHLD2

SHLD2

NPTH1

NPTH1 NPTH2

NPTH2

SHLD1

SHLD1 SHLD2

SHLD2 NPTH1

NPTH1 NPTH2

NPTH2

of

7 8 9 10

A

5

R0.3 Modify

D D

SPK_CD_L<25>

PC_BEEP<25>

SPK_CD_R<25>

PC_BEEP<25>

R0.3 Modify

1 2

C911

1U_0603_10V6K~D

PC_BEEP

1 2

C908 0.1U_0402_10V6K~DC908 0.1U_0402_10V6K~D

SPK_CD_R SPK_CD_R4

1 2

C915

PC_BEEP PC_BEEP_2

1 2

C912 0.1U_0402_10V6K~DC912 0.1U_0402_10V6K~D

B+

SPK_CD_L1

PC_BEEP_1

1U_0603_10V6K~D

19V

1A/40mil

2

C901

C901 22U_1210_25V6K~D

22U_1210_25V6K~D

1

1 2

16.5K_0402_1%

1 2

182K_0402_1%

1 2

16.5K_0402_1%

1 2

182K_0402_1%

R903

R901

R908

R906

2

C902

C902 22U_1210_25V6K~D

22U_1210_25V6K~D

1

SPK_CD_L2

1 2

R904 17.8K_0402_1%R904 17.8K_0402_1%

SPK_CD_R2

C913

2200P_0402_25V7K~D

1 2 1 2

R909 17.8K_0402_1%R909 17.8K_0402_1%

C909

2200P_0402_25V7K~D

1 2

High-Pass Filiter,fc=500Hz, Av=1.45V/V

D59

R0.3 add

SPK_AMP_MUTE#<25>

C C

B B

SPK_CD_R<25>

SPK_CD_L<25>

SPK_CD_L

D59

1 2

SDMK0340L-7-F_SOD323-2~D

R1567

1 2

330K_0402_5%

2

1

R0.3 Modify

C1095

SUB_FB_L SUB_FB_L1

1 2

1U_0603_10V6K~D

SUB_CD_R

1 2

C1098 0.47U_0603_10V7K~DC1098 0.47U_0603_10V7K~D

C1100 0.47U_0603_10V7K~DC1100 0.47U_0603_10V7K~D

1 2

SUB_CD_L

SPK_AMP_MUTE_R#

C1553

2.2U_0603_10V6K~D

10K_0402_1%~D

B+

2

22U_1210_25V6K~D

1

R1195

1 2

R1199

9.09K_0402_1%~D

1 2

R1201

9.09K_0402_1%~D

1A/40mil

C1089

For filterless modualation/spread-spectrum mode

High-Pass Filiter,fc=100 Hz, 500Hz, Av=1.45V/V

D60

@ D60

A A

R1.0 add

SUB_AMP_MUTE#<25>

5

@

1 2

SDMK0340L-7-F_SOD323-2~D

SDMK0340L-7-F_SOD323-2~D R1569

R1569

1 2

0_0402_5%~D

2

@

C1558

2.2U_0603_10V6K~D

1

SUB_AMP_MUTE_R#

4

2

C903

C903 22U_1210_25V6K~D

22U_1210_25V6K~D

1

1 2

11K_0402_1%

SPK_CD_R3SPK_CD_R1

1 2

0.047U_0402_16V7K~D

1

C904

0.1U_0603_50V4Z~D

2

R900

1 2

11K_0402_1%

C910

1 2

0.022U_0402_25V7K~D

R905

SPK_CD_R2_FBL

C914

1 2

0.022U_0402_25V7K~D

+3VS

For filterless modualation/spread-spectrum mode

Mono Select. Set MONO high for mono mode.

1

C923

C925

2

1U_0603_25V6-K~D

2

C1090

22U_1210_25V6K~D

1

SUB_FB_L2

C1096

SUB_FB_L3

0.047U_0402_16V7K~D

R1197

R1197 20K_0402_1%~D

20K_0402_1%~D

1 2

2

15.8K_0402_1%

C1101

0.1U_0402_16V7K~D

1

4

1

C905

0.1U_0603_50V4Z~D

2

SPKER_CD_L2_FBL

R902

1 2

182K_0402_1%

SPK_CD_L4SPK_CD_L3SPK_CD_L

R907

1 2

182K_0402_1%

SPK_AMP_MUTE# SPK_AMP_MUTE_R#

R910 0_0402_5%~DR910 0_0402_5%~D

1 2

Internal Regulator Output.

Internal 2V Bias.

1

C924

1

0.1U_0603_50V4Z~D

2

1U_0603_25V6-K~D

C1091

22U_1210_25V6K~D

1 2

11.5K_0402_1%

1 2

6.49K_0402_1%~D

R1200

+3VS

1U_0603_25V6-K~D

1

2

R1194

R1198

SUB_CD_R2SUB_CD_R1SPK_CD_R

C1104

2

1

2

C926

1U_0603_25V6-K~D

2

1

C1097

1 2

U13

27

PVDD1

30

PVDD2

28

PGND2

29

PGND1

5

FB_L

6

IN_L

19

FB_R

18

IN_R

10

SHDN#

11

REGEN

9

MUTE#

20

MODE

4

MONO

16

VS

15

REG

12

COM

21

C1N

22

C1P

13

AGND

14

AGND

MAX9736AETJ+T_TQFN32_7X7

1

C1092

0.1U_0603_50V4Z~D

2

1 2

100K_0402_1%~D

C1099 0.01U_0402_16V7K~DC1099 0.01U_0402_16V7K~D

R1202 0_0402_5%~DR1202 0_0402_5%~D

1 2

Internal Regulator Output.

Internal 2V Bias.

1U_0603_25V6-K~D

1

C1105

2

1

C1093

0.1U_0603_50V4Z~D

2

SUB_FB_L4 AMP_SW+ AMP_SW_JK+

R1196

SUB_IN_L

SUB_FB_L

1 2

SUB_IN_R

SUB_AMP_MUTE# SUB_AMP_MUTE_R#

1U_0603_25V6-K~D

1

C1103

C1106

0.1U_0603_50V4Z~D

2

3

1

OUTL-1

2

OUTL-2

31

OUTL+1

32

OUTL+2

7

NC1

8

NC2

17

NC3

25

OUTR+1

26

OUTR+2

23

OUTR-1

24

OUTR-2

3

BOOT

33

EP

U14

27

PVDD1

30

PVDD2

28

PGND2

29

PGND1

5

FB_L

6

IN_L

19

FB_R

18

IN_R

10

SHDN#

11

REGEN

9

MUTE#

20

MODE

4

MONO

16

VS

15

REG

12

COM

21

C1N

22

C1P

13

AGND

14

AGND

MAX9736AETJ+T_TQFN32_7X7

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

L67

L67 BLM18PG181SN1_0603~D

BLM18PG181SN1_0603~D

AMP_SPKL-

1 2

L68

L68 BLM18PG181SN1_0603~D

BLM18PG181SN1_0603~D

1 2

L69

BLM18PG181SN1_0603~D

1 2

L70

L70 BLM18PG181SN1_0603~D

BLM18PG181SN1_0603~D

AMP_SPKR-

1 2

C922

12

1U_0805_25V4Z~D

OUTL-1 OUTL-2

OUTL+1 OUTL+2

NC1 NC2 NC3

OUTR+1 OUTR+2

OUTR-1 OUTR-2

BOOT

EP

2009/07/29 2010/07/29

AMP_SPK_JK_L-

1

C906

C906 330P_0402_50V7K~D

330P_0402_50V7K~D

2

AMP_SPKL+_LAMP_SPKL+

1

C907

C907 330P_0402_50V7K~D

330P_0402_50V7K~D

2

AMP_SPKR+_R

1

C917

C917 330P_0402_50V7K~D

330P_0402_50V7K~D

2

AMP_SPK_JK_R-

1

C921

C921 330P_0402_50V7K~D

330P_0402_50V7K~D

2

AMP_SW-

1 2

31 32

7 8 17

25 26

23 24

3

33

Compal Secret Data

1 2

BLM18PG181SN1_0603~D

1 2

BLM18PG181SN1_0603~D

AMP_SW+

AMP_SW-

C1102

12

1U_0805_50V4Z~D

Deciphered Date

2

L85

1 2

22UH_LQH55PN220MR0L_0.85A_20%~D

L86

1 2

22UH_LQH55PN220MR0L_0.85A_20%~D

L87

L88

AMP_SPK_JK_L+

AMP_SPK_JK_R+AMP_SPKR+

PESD24VS2UT_SOT23-3~D

AMP_SW_JK-

1

C1088

C1088 330P_0402_50V7K~D

330P_0402_50V7K~D

2

1

C1094

C1094 330P_0402_50V7K~D

330P_0402_50V7K~D

2

SUB WOOFER amp impedance of JBL is 4 ohm.

2

AMP_SPK_JK_LAMP_SPK_JK_L+ AMP_SPK_JK_RAMP_SPK_JK_R+

D20

@D20

@

1

Speaker amp impedance of JBL is 4 ohm.

Speaker Connector

JSPK1

15 mils trace

2

3

2

3

1

Title

Size Document Number Rev

Custom

Date: Sheet

1

JWFER1

1

2

3

G1

4

G2

MOLEX_53398-0271~D

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

JSPK1

1

2

3

G5

4

G6

MOLEX_53261-0471

CONN@

D21

@D21

@ PESD24VS2UT_SOT23-3~D

PESD24VS2UT_SOT23-3~D

1

5 6

of

26 57Monday, September 21, 2009

A

+3VS

WWAN

1 1

ICH_PCIE_WAKE#<17,24,28,31>

WWAN_CLKREQ#<16>

CLK_PCIE_WAN#<16> CLK_PCIE_WAN<16>

PCIE_IRX_WANTX_N1<16> PCIE_IRX_WANTX_P1<16>

PCIE_ITX_C_WANRX_N1<16> PCIE_ITX_C_WANRX_P1<16>

2 2

EC_TX_P80_DATA<17,31> EC_RX_P80_DATA<31>

C1113

47P_0402_50V8J~D@C1113

47P_0402_50V8J~D

1

@

2

R287 0_0402_5%~DR287 0_0402_5%~D R286 0_0402_5%~DR286 0_0402_5%~D

C403

0.01U_0402_16V7K~D

C403

0.01U_0402_16V7K~D

1

2

ICH_PCIE_WAKE#

WWAN_CLKREQ# CLK_PCIE_WAN#

CLK_PCIE_WAN

PCIE_IRX_WANTX_N1 PCIE_IRX_WANTX_P1

PCIE_ITX_C_WANRX_N1 PCIE_ITX_C_WANRX_P1

1 2 1 2

.1U_0402_16V7K~D

C404

C405

4.7U_0805_10V4Z~D

C405

4.7U_0805_10V4Z~D

1

2

+3VS

C956

330U_D2E_6.3VM_R25~D+C956

330U_D2E_6.3VM_R25~D

1

+

2

1 3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

53

B

+1.5VS

C1114

47P_0402_50V8J~D@C1114

47P_0402_50V8J~D

1

@

2

JWWAN1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

GND1

GND2

TYCO_1775838-1~D

TYCO_1775838-1~D CONN@

CONN@

C407

0.01U_0402_16V7K~D

C407

0.01U_0402_16V7K~D

1

2

+1.5VS +3VS

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

54

C408

.1U_0402_16V7K~D

C408

.1U_0402_16V7K~D

1

2

C409

4.7U_0805_10V4Z~D

C409

4.7U_0805_10V4Z~D

1

2

Don't forget to remove R287 or disble debug port when doing SIM Pre-test and before RTS.

+UIM_PWR

UIM_DATA UIM_CLK UIM_RST

R285 0_0402_5%~DR285 0_0402_5%~D

1 2

WWAN_RADIO_OFF# PLT_RST#

R911 0_0402_5%~DR911 0_0402_5%~D

1 2

R912 0_0402_5%~DR912 0_0402_5%~D

1 2

USBP5_DUSBP5_D+

C

UIM_VPP

WWAN_RADIO_OFF# <31> PLT_RST# <6,19,23,24,28,30,31>

EC_SMB_CK2 <16,28,31,39> EC_SMB_DA2 <16,28,31,39>

L71

DLW21SN121SQ2L_4P~D

USBP5_D+

USBP5_D-

DLW21SN121SQ2L_4P~D

@L71

@

2

3

1 2

R913 0_0402_5%~DR913 0_0402_5%~D

1 2

R914 0_0402_5%~DR914 0_0402_5%~D

1

4

UIM_VPP UIM_DATA

33P_0402_50V8J~D

1

4

D

1

2

3

5 6 7 8 9

C410

10

Place as close as JSIM1

USBP5+ <19>

USBP5- <19>

D41

SRV05-4.TCT_SOT23-6~D

SRV05-4.TCT_SOT23-6~D JSIM1

JSIM1

GND VPP I/O NC GND GND

CONN@

Link ok

VCC RST CLK

NC

MOLEX_475531001

E

6

5

4

+UIM_PWR

1 2 3 4

UIM_RST UIM_CLK

C411

C411 33P_0402_50V8J~D

33P_0402_50V8J~D

4.7U_0805_10V4Z~D

C412

1

2

1

C413

C413 .1U_0402_16V7K~D

.1U_0402_16V7K~D

2

WLAN

+3V_WLAN +1.5VS +3V_WLAN

JWLAN1

ICH_PCIE_WAKE#<17,24,28,31>

COEX2_WLAN_ACTIVE<28,30>

3 3

4 4

WPAN_ACTIVE<28>

BT_ACTIVE<30>

A

WLAN_CLKREQ#<16>

CLK_PCIE_WLAN#<16> CLK_PCIE_WLAN<16>

CLK_DEBUG_PORT<19>

PCIE_IRX_WLANTX_N2<16> PCIE_IRX_WLANTX_P2<16>

PCIE_ITX_C_WLANRX_N2<16> PCIE_ITX_C_WLANRX_P2<16>

WPAN_ACTIVE

BT_ACTIVE

PLT_RST#<6,19,23,24,28,30,31>

D40

2

3

BAT54C-7-F_SOT23~D

ICH_PCIE_WAKE#

R291 0_0402_5%~DR291 0_0402_5%~D

1 2

COEX1_WLAN_ACTIVE WLAN_CLKREQ#

CLK_PCIE_WLAN# CLK_PCIE_WLAN

R918 0_0402_5%~DR918 0_0402_5%~D

1 2

R921 0_0402_5%~DR921 0_0402_5%~D

1 2

PCIE_IRX_WLANTX_N2 PCIE_IRX_WLANTX_P2

PCIE_ITX_C_WLANRX_N2 PCIE_ITX_C_WLANRX_P2

COEX1_WLAN_ACTIVE

1

12

R997

R997 10K_0402_5%~D

10K_0402_5%~D

B

JWLAN1

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

GND1

TYCO_1775838-1~D

TYCO_1775838-1~D CONN@

CONN@

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

GND2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R919 0_0402_5%~DR919 0_0402_5%~D

1 2

R920 0_0402_5%~DR920 0_0402_5%~D

1 2

R915 0_0402_5%~DR915 0_0402_5%~D

1 2

R916 0_0402_5%~DR916 0_0402_5%~D

1 2

R917 0_0402_5%~DR917 0_0402_5%~D

1 2

WLAN_RADIO_OFF#

R922 0_0402_5%~DR922 0_0402_5%~D

1 2

R923 0_0402_5%~DR923 0_0402_5%~D

1 2

USBP4_DUSBP4_D+

USBP4_D+

USBP4_D-

2009/07/29 2010/07/29

C

LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

WLAN_RADIO_OFF# <31> PLT_RST# <6,19,23,24,28,30,31>

L72

@L72

@

DLW21SN121SQ2L_4P~D

2

3

1 2

R924 0_0402_5%~DR924 0_0402_5%~D

1 2

R925 0_0402_5%~DR925 0_0402_5%~D

Compal Secret Data

1

4

Deciphered Date

EC_SMB_CK2 <16,28,31,39> EC_SMB_DA2 <16,28,31,39>

LPC_FRAME# <15,31>

LPC_AD[0..3] <15,31>

USBP4+ <19>

USBP4- <19>

D

+3V_WLAN

1 2

JP10@ JP10@

C416

4.7U_0805_10V4Z~D

C416

C1115

47P_0402_50V8J~D@C1115

47P_0402_50V8J~D

C414

0.01U_0402_16V7K~D

C414

0.01U_0402_16V7K~D

1

@

1

2

1

@

2

Title

Size Document Number Rev

Date: Sheet

SCHEMATICS, MB A5155

Custom

401808

4.7U_0805_10V4Z~D

C415

.1U_0402_16V7K~D

C415

.1U_0402_16V7K~D

1

2

+1.5VS

C1116

47P_0402_50V8J~D@C1116

47P_0402_50V8J~D

Compal Electronics, Inc.

C417

0.01U_0402_16V7K~D

C417

0.01U_0402_16V7K~D

1

2

C418

0.01U_0402_16V7K~D

C418

0.01U_0402_16V7K~D

1

2

E

+3VS

27 57Monday, September 21, 2009

of

A

5

4

3

2

1

+1.5VS

C419

0.047U_0402_16V4Z~D

C419

D D

ICH_PCIE_WAKE#<17,24,27,31>

COEX2_WLAN_ACTIVE<27,30>

WPAN_ACTIVE<27>

WPAN_CLKREQ#<16>

CLK_PCIE_WPAN#<16> CLK_PCIE_WPAN<16>

PCIE_IRX_WPANTX_N3<16> PCIE_IRX_WPANTX_P3<16>

PCIE_ITX_C_WPANRX_P3<16>

C C

ICH_PCIE_WAKE#

R292 0_0402_5%~DR292 0_0402_5%~D

1 2

R293 0_0402_5%~DR293 0_0402_5%~D

1 2

WPAN_CLKREQ# CLK_PCIE_WPAN#

CLK_PCIE_WPAN

PCIE_IRX_WPANTX_N3 PCIE_IRX_WPANTX_P3

PCIE_ITX_C_WPANRX_N3 PCIE_ITX_C_WPANRX_P3

WPAN_ACTIVE_R

WPAN Card

JWPAN1

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

GND1

TYCO_1775838-1~D

GND2

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

+1.5VS

+3VS+3VS

WPAN_RADIO_OFF#

1 2

R1162 0_0402_5%~DR1162 0_0402_5%~D

R294 0_0402_5%~DR294 0_0402_5%~D

1 2

R298 0_0402_5%~DR298 0_0402_5%~D

1 2

USBP3_DUSBP3_D+

USBP3_D-

USBP3_D+

WPAN_RADIO_OFF# <31>

PLT_RST# <6,19,23,24,27,30,31>

EC_SMB_CK2 <16,27,31,39> EC_SMB_DA2 <16,27,31,39>PCIE_ITX_C_WPANRX_N3<16>

DLW21SN121SQ2L_4P~D

2

3

L26

2

3

@L26

@

1

4

12

R2950_0402_5%~D R2950_0402_5%~D

12

R2960_0402_5%~D R2960_0402_5%~D

0.047U_0402_16V4Z~D

1

2

USBP3- <19>

USBP3+ <19>

+3VS

C422

0.047U_0402_16V4Z~D

C422

0.047U_0402_16V4Z~D

C423

0.1U_0402_16V4Z~D

C423

C421

0.047U_0402_16V4Z~D

C421

C420

0.047U_0402_16V4Z~D

C420

0.047U_0402_16V4Z~D

1

2

0.047U_0402_16V4Z~D

1

2

0.1U_0402_16V4Z~D

1

2

C425

4.7U_0603_6.3V6M~D

C425

4.7U_0603_6.3V6M~D

C424

0.1U_0402_16V4Z~D

C424

0.1U_0402_16V4Z~D 1

1

2

Express Card Power Switch

+3VALW

B B

A A

+1.5VS

0.1U_0402_16V4Z~D

C433

0.1U_0402_16V4Z~D

C433

0.1U_0402_16V4Z~D

1

2

1

2

PLT_RST#<6,19,23,24,27,30,31> SYSON<31,33,52> SUSP#<31,33,51,52,53,54>

+3VS

C432

0.1U_0402_16V4Z~D

C432

0.1U_0402_16V4Z~D

1

C431

2

U16

2

3.3Vin

17

3.3Vin

PLT_RST#

CPPE# EXPR_CPUSB#

+1.5V_CARD Max. 650mA , Average 500mA +3V_CARD Max. 1300mA, Average 1000mA

AUX_IN12AUX_OUT

6

SYSRST#

20

SHDNZ

1

STBYZ

10

CPPE#

9

CPUSB#

18

RCLKEN

P2231NL E2_QFN20_4X4

3.3Vout

OCZ

PERSTZ

GND

3 15

11 19

PERST#

8 4

NC

5

NC

13

NC

14

NC

16

NC

7

(1A)

(0.5A)

+3VS_CARD

C429

0.1U_0402_16V4Z~D

C429

0.1U_0402_16V4Z~D

1

2

+3VS_CARD_AUX

C434

0.1U_0402_16V4Z~D

C434

0.1U_0402_16V4Z~D

1

2

+1.5VS_CARD

C427

0.1U_0402_16V4Z~D

C427

0.1U_0402_16V4Z~D

1

2

4.7U_0805_10V4Z~D

1

2

C435

4.7U_0805_10V4Z~D

C435

4.7U_0805_10V4Z~D

1

2

C428

4.7U_0805_10V4Z~D

C428

4.7U_0805_10V4Z~D

1

2

PCIE_IRX_EXPTX_N5<16> PCIE_IRX_EXPTX_P5<16>

PCIE_ITX_C_EXPRX_N5<16> PCIE_ITX_C_EXPRX_P5<16>

USBP8-<19> USBP8+<19>

EC_SMB_CK2<16,27,31,39> EC_SMB_DA2<16,27,31,39>

+1.5VS_CARD

ICH_PCIE_WAKE#<17,24,27,31>

+3VS_CARD_AUX

EXP_CLKREQ#<16>

CLK_PCIE_EXPR#<16> CLK_PCIE_EXPR<16>

+3VS_CARD

EXP_CLKREQ# CPPE# CLK_PCIE_EXPR# CLK_PCIE_EXPR

PCIE_IRX_EXPTX_N5 PCIE_IRX_EXPTX_P5

PCIE_ITX_C_EXPRX_N5 PCIE_ITX_C_EXPRX_P5

USBP8USBP8+ EXPR_CPUSB#

EC_SMB_CK2 EC_SMB_DA2

PERST#

C430

Express Card

4.7U_0805_10V4Z~D

C430

JEXP1

1

GND

2

USB-

3

USB+

4

CPUSB#

5

REV

6

REV

7

SMBCLK

8

SMBDATE

9

+1.5V

10

+1.5V

11

WAKE#

12

+3.3VAUX

13

PERST#

14

+3.3V

15

+3.3V

16

CLKREQ#

17

CPPE#

18

REFCLK-

19

REFCLK+

20

GND

21

PERn0

22

PERp0

23

GND

24

PETn0

25

PETp0

26

GND

27

G1

28

G2

29

G3

30

G4

TAITW_PXPXAE-000LBS2ZZ4N0_NR

TAITW_PXPXAE-000LBS2ZZ4N0_NR CONN@

CONN@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/07/29 2010/07/29

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

1

A

of

28 57Monday, September 21, 2009

A

B

C

D

E

SATA ODD CONN

SATA_ITX_C_DRX_P4<15> SATA_ITX_C_DRX_N4<15>

SATA_IRX_DTX_N4<15> SATA_IRX_DTX_P4<15>

1 1

R0.3 Modify

C437 0.01U_0402_16V7K~DC437 0.01U_0402_16V7K~D

1 2

C436 0.01U_0402_16V7K~DC436 0.01U_0402_16V7K~D

1 2

SATA_ITX_C_DRX_P4 SATA_ITX_C_DRX_N4

SATA_IRX_C_DTX_N4 SATA_IRX_C_DTX_P4

+5VS

SATA HDD (On board)

SATA_ITX_C_DRX_P0<15> SATA_ITX_C_DRX_N0<15>

SATA_IRX_DTX_N0<15> SATA_IRX_DTX_P0<15>

2 2

Place close U55 pin 2 & pin3

SATA_ITX_C_DRX_P1 SATA_ITX_C_DRX_N1

SATA_IRX_DTX_P1 SATA_IRX_DTX_N1

R0.3 Modify

Output Swing Control

SEL2_ [A:B]

**

R0.3 Modify

3 3

4 4

SATA_ITX_C_DRX_P1<15> SATA_ITX_C_DRX_N1<15>

SATA_IRX_DTX_P1<15> SATA_IRX_DTX_N1<15>

+SATA_PWR

R1168 0_0402_5%~D@R1168 0_0402_5%~D@

1 2

R1170 0_0402_5%~D@R1170 0_0402_5%~D@

1 2

R1172 0_0402_5%~D@R1172 0_0402_5%~D@

1 2

R1174 0_0402_5%~D@R1174 0_0402_5%~D@

1 2

+1.8VS +SATA_PWR

Swing

SATA_ITX_C_DRX_P1 SATA_ITX_C_DRX_N1

SATA_IRX_C_DTX_P1

1 2

SATA_IRX_C_DTX_N1

1 2

1 2 1 2

1 2

1 2 1 2

1x

1.2x

0 1

C1083 0.01U_0402_16V7K~DC1083 0.01U_0402_16V7K~D

C1084 0.01U_0402_16V7K~DC1084 0.01U_0402_16V7K~D R1176 0_0402_5%~DR1176 0_0402_5%~D R1177 0_0402_5%~DR1177 0_0402_5%~D

R1178 0_0402_5%~D@R1178 0_0402_5%~D@ R1179 0_0402_5%~D@R1179 0_0402_5%~D@

R1180 0_0402_5%~DR1180 0_0402_5%~D R1181 0_0402_5%~DR1181 0_0402_5%~D

R1183 0_0402_5%~DR1183 0_0402_5%~D

R1185 0_0402_5%~DR1185 0_0402_5%~D R1187 5.1K_0402_1%~DR1187 5.1K_0402_1%~D

R1189 5.1K_0402_1%~DR1189 5.1K_0402_1%~D R1190 470_0402_5%~D@R1190 470_0402_5%~D@

R1191 0_0402_5%~D@R1191 0_0402_5%~D@

R1192 0_0402_5%~D@R1192 0_0402_5%~D@

R0.3 depop

R0.3 change to SA00002YQ0L (S IC PI2EQX3201BLZFEX TQFN 36P)

SEL0_ [A:B] SEL1_ [A:B]

00 01

*

1 11

A

SATA_ITX_R_DRX_P4 SATA_ITX_R_DRX_N4

SATA_IRX_R_DTX_P4 SATA_IRX_R_DTX_N4

JP11@JP11 1 2

@

Output De-emphasis Adjustment

SEL3_ [A:B]

0 1

U55

2

AI+

3

AI-

7

BO+

8

BO-

34

SEL0_A

13

SEL0_B

33

SEL1_A

14

SEL1_B

32

SEL2_A

15

SEL2_B

31

SEL3_A

16

SEL3_B

30

EN_A

29

EN_B

19

IREF

11

CLKIN+

12

CLKIN-

PI2EQX3201BZFEX_TQFN36_6X5

Equalizer Selection

Compliance Channel

R1169 0_0402_5%~D@R1169 0_0402_5%~D@

1 2

R1171 0_0402_5%~D@R1171 0_0402_5%~D@

1 2

R1173 0_0402_5%~D@R1173 0_0402_5%~D@

1 2

R1175 0_0402_5%~D@R1175 0_0402_5%~D@

1 2

De-emphasis

0dB

-3.5dB

1

VDD

6

VDD

10

VDD

23

VDD

28

VDD

5

AVDD

27

AO+

26

AO-

21

BI-

22

BI+

17

OUT+

18

OUT-

36

SD_A

35

SD_B

25

GND

20

GND

9

GND

4

GND

24

AGND

37

PAD

no equalization [0:2.5dB] @ 1.6 GHz

0

[2.5:4.5dB] @ 1.6 GHz [4.5:6.5dB] @ 1.6 GHz

B

ESATA_ITX_C_DRX_P4 ESATA_ITX_C_DRX_N4

ESATA_IRX_DTX_P4

R1182 0_0402_5%~D@R1182 0_0402_5%~D@ R1184 0_0402_5%~D@R1184 0_0402_5%~D@

R1186 0_0402_5%~D@R1186 0_0402_5%~D@ R1188 0_0402_5%~D@R1188 0_0402_5%~D@

ESATA_IRX_DTX_N4

1

C1076

2

10U_1206_16V4Z~D

1 2 1 2

1

C1077

2

12

1

2

0.1U_0402_16V4Z~D

R1193

R1193 470_0402_5%~D

470_0402_5%~D

Place close U55 pin 21 & pin22

+SATA_PWR

ESATA_ITX_DRX_P4 ESATA_ITX_DRX_N4

ESATA_IRX_DTX_N4 ESATA_IRX_DTX_P4

1

C1079

C1078

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D C1082

C1082 4700P_0402_25V7K~D

4700P_0402_25V7K~D

ESATA_ITX_C_DRX_P4

12

C1085

C1085 4700P_0402_25V7K~D

4700P_0402_25V7K~D

ESATA_ITX_C_DRX_N4

12

1

C1080

C1081

2

0.1U_0402_16V4Z~D

ESATA_IRX_DTX_N4 ESATA_IRX_DTX_P4 ESATA_IRX_C_DTX_P4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

C442 0.01U_0402_25V7K~DC442 0.01U_0402_25V7K~D

12

C443 0.01U_0402_25V7K~DC443 0.01U_0402_25V7K~D

12

SATA HDD

C449 0.01U_0402_25V7K~DC449 0.01U_0402_25V7K~D C450 0.01U_0402_25V7K~DC450 0.01U_0402_25V7K~D

2009/07/29 2010/07/29

12 12

Compal Secret Data

Deciphered Date

SATA_ITX_C_DRX_P0 SATA_ITX_C_DRX_N0

SATA_IRX_C_DTX_N0 SATA_IRX_C_DTX_P0

+5VS

ESATA_ITX_C_DRX_P4 ESATA_ITX_C_DRX_N4

ESATA_IRX_C_DTX_N4

+5VS

D

JODD1

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

DP

9

V5

10

V5

11

MD

12

GND

13

GND

MOLEX_47639-3000_13P

CONN@

JSATA2

1

GND

2

RX+

3

RX-

4

GND

5

TX-

6

TX+

7

GND

8

3.3V

9

3.3V

10

3.3V

11

GND

12

GND

13

GND

14

5V

15

5V

16

5V

17

GND

18

Reserved

19

GND

20

12V

21

12V

22

12V

TYCO_1770615-3~D

MOLEX_47662-2000_22P-T

JSATA1

SP010812230

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

V33

9

V33

10

V33

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

Reserved

19

GND

20

V12

21

V12

22

V12

MOLEX_47662-2000_NR

MOLEX_47662-2000_NR CONN@

CONN@

14

G1

15

G2

16

G3

23

GND1

24

GND2

23

GND

24

GND

25

GND

Title

Size Document Number Rev

Custom

401808

Date: Sheet

+5VS

C439

1U_0603_10V4Z~D

C439

1U_0603_10V4Z~D

C440

0.1U_0402_16V4Z~D

C440

C438

10U_0805_10V4Z~D

C438

10U_0805_10V4Z~D

1

2

0.1U_0402_16V4Z~D

1

2

Close to ODD Conn

+5VS

Close to JSATA2.

C453

0.1U_0402_16V7K~D

C453

0.1U_0402_16V7K~D

C454

0.1U_0402_16V7K~D

C454

C452

10U_0805_10V4Z~D

C452

10U_0805_10V4Z~D

1

2

+5VS

Close to JSATA1.

C445

10U_0805_10V4Z~D

C445

10U_0805_10V4Z~D

1

2

Compal Electronics, Inc.

SCHEMATICS, MB A5155

0.1U_0402_16V7K~D

1

2

C446

0.1U_0402_16V7K~D

C446

0.1U_0402_16V7K~D

C447

0.1U_0402_16V7K~D

C447

0.1U_0402_16V7K~D

1

2

29 57Monday, September 21, 2009

E

29 57Monday, September 21, 2009

C441

1000P_0402_50V7K~D

C441

1000P_0402_50V7K~D

C455

1000P_0402_50V7K~D

C455

1000P_0402_50V7K~D

C448

1000P_0402_50V7K~D

C448

1000P_0402_50V7K~D

1

2

A

of

Place close U40 pin 2 & pin3

Output Swing Control

SEL2_ [A:B]

0 1

*

SATA_ITX_C_DRX_P5<15> SATA_ITX_C_DRX_N5<15>

SATA_IRX_DTX_P5<15> SATA_IRX_DTX_N5<15>

+1.8VS

USB_DETECT#

C942 0.01U_0402_16V7K~DC942 0.01U_0402_16V7K~D

C943 0.01U_0402_16V7K~DC943 0.01U_0402_16V7K~D R954 0_0402_5%~DR954 0_0402_5%~D R955 0_0402_5%~DR955 0_0402_5%~D

R956 0_0402_5%~D@R956 0_0402_5%~D@ R957 0_0402_5%~D@R957 0_0402_5%~D@

R958 0_0402_5%~D@R958 0_0402_5%~D@ R959 0_0402_5%~D@R959 0_0402_5%~D@

R961 0_0402_5%~DR961 0_0402_5%~D

R963 0_0402_5%~DR963 0_0402_5%~D

R965 10K_0402_1%~DR965 10K_0402_1%~D

1 2

R967 10K_0402_1%~DR967 10K_0402_1%~D

1 2

R968 470_0402_5%~D@R968 470_0402_5%~D@

+1.8VS

R969 0_0402_5%~D@R969 0_0402_5%~D@

R970 0_0402_5%~D@R970 0_0402_5%~D@

13

D

2

G

S

Swing

1x

1.2x

SATA_ITX_C_DRX_P5 SATA_ITX_C_DRX_N5

SATA_IRX_C_DTX_P5

1 2

SATA_IRX_C_DTX_N5

1 2

1 2 1 2

USB_DETECT

1 2

1 2 1 2

R0.3 depop

USB_DETECT

Q63

@

Q63

@

PMF3800SN_SC70-3

R0.3 depop

SATA_ITX_C_DRX_P5 SATA_ITX_C_DRX_N5

SATA_IRX_DTX_P5 SATA_IRX_DTX_N5

Output De-emphasis Adjustment

R1164 0_0402_5%~D@R1164 0_0402_5%~D@

1 2

R1165 0_0402_5%~D@R1165 0_0402_5%~D@

1 2

R951 0_0402_5%~D@R951 0_0402_5%~D@

1 2

R952 0_0402_5%~D@R952 0_0402_5%~D@

1 2

SEL3_ [A:B]

0

*

1

U40

2

AI+

3

AI-

7

BO+

8

BO-

34

SEL0_A

13

SEL0_B

33

SEL1_A

14

SEL1_B

32

SEL2_A

15

SEL2_B

31

SEL3_A

16

SEL3_B

30

EN_A

29

EN_B

19

IREF

11

CLKIN+

12

CLKIN-

PI2EQX3201BZFEX_TQFN36_6X5

SATA_ITX_R_DRX_P5 SATA_ITX_R_DRX_N5

SATA_IRX_R_DTX_P5 SATA_IRX_R_DTX_N5

De-emphasis

0dB

-3.5dB

1

VDD

6

VDD

10

VDD

23

VDD

28

VDD

5

AVDD

27

AO+

26

AO-

21

BI-

22

BI+

17

OUT+

18

OUT-

36

SD_A

35

SD_B

25

GND

20

GND

9

GND

4

GND

24

AGND

37

PAD

+1.8VS

1

2

ESATA_ITX_DRX_P ESATA_ITX_DRX_N

ESATA_IRX_DTX_N

ESATA_IRX_DTX_P

R960 0_0402_5%~D@R960 0_0402_5%~D@

1 2

R962 0_0402_5%~D@R962 0_0402_5%~D@

1 2

R964 0_0402_5%~D@R964 0_0402_5%~D@

1 2

R966 0_0402_5%~D@R966 0_0402_5%~D@

1 2

C935

10U_0805_10V4Z~D

1

2

R0.3 change to SA00002YQ0L (S IC PI2EQX3201BLZFEX TQFN 36P)

Equalizer Selection

SEL0_ [A:B] SEL1_ [A:B]

00 01

*

1 11

Compliance Channel no equalization [0:2.5dB] @ 1.6 GHz [2.5:4.5dB] @ 1.6 GHz

0

[4.5:6.5dB] @ 1.6 GHz

R949 0_0402_5%~D@R949 0_0402_5%~D@ R950 0_0402_5%~D@R950 0_0402_5%~D@

R1166 0_0402_5%~D@R1166 0_0402_5%~D@ R1167 0_0402_5%~D@R1167 0_0402_5%~D@

C936

0.1U_0402_16V4Z~D

12

R953

R953 390_0402_5%

390_0402_5%

1 2 1 2

Place close U40 pin 21 & pin22

1

2

1

C937

C938

2

0.1U_0402_16V4Z~D

C941

C941 4700P_0402_25V7K~D

4700P_0402_25V7K~D

ESATA_ITX_C_DRX_P

12

C944

C944 4700P_0402_25V7K~D

4700P_0402_25V7K~D

ESATA_ITX_C_DRX_N

12

C939

0.1U_0402_16V4Z~D

Place close JESA1

ESATA_ITX_C_DRX_P ESATA_ITX_C_DRX_N

ESATA_IRX_DTX_P ESATA_IRX_DTX_N

1

C940

2

0.1U_0402_16V4Z~D

D34

1

CH1

2

Vn

3

CH2

CM1293-04SO_SOT23-6@

PWRSHARE_EN#<31>

R301

43.2K_0402_1%~D

R304

49.9K_0402_1%~D

4

CH4

5

Vp

6

CH3

+5V_CHGUSB

1 2

USBP0_D-

+5V_CHGUSB

USBP0_D+

+5VALW

0.1U_0402_16V4Z~D

10U_0805_10V4Z~D

C462

1

2

R302

R302 75K_0402_1%

75K_0402_1%

1 2

R305

49.9K_0402_1%~D

1 2

USBP0+<19> USBP0-<19>

USB_CHARGE_D+ USB_CHARGE_D- USBP0_D-

+5V_CHGUSB

1

+

C460

C460 150U_D2_6.3VM~D

150U_D2_6.3VM~D

2

ESATA_IRX_DTX_N ESATA_IRX_DTX_P

U17

1

GND

2

IN

3

EN1#

4

EN2#

TPS2062ADR_SO8~D

C463

C464 4700P_0402_25V7K~DC464 4700P_0402_25V7K~D C465 4700P_0402_25V7K~DC465 4700P_0402_25V7K~D

USB_DETECT#<32>

+5V_CHGUSB

ESATA_USB_OC#

8

OC1#

7

OUT1

6

OUT2

5

OC2#

U18

1

1D+

2

1D-

3

2D+

4

2D-

5

GND

TS3USB221RSER_QFN10_2x1P5~D

VCC

OE#

10 9

S

8

D+

7

D-

6

S Logic"1" Work from BKT

1

C461

0.1U_0402_16V4Z~D

2

USBP0_DUSBP0_D+

ESATA_ITX_C_DRX_P ESATA_ITX_C_DRX_N

ESATA_IRX_C_DTX_N

12

ESATA_IRX_C_DTX_P

12

C466

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D 1 2

+3VALW

PWRSHARE_OE#

USBP0_D+

S Function

OE#

X

L H

ESATA

JESA1

1

VBUS

2

D-

3

D+

4

GND

5

GND

6

A+

7

A-

8

GND

9

B-

10

B+

11

GND

12

DET1

13

DET2

FOX_3Q3813C-RB1C3B-7F

FOX_3Q3813C-RB1C3B-7F CONN@

CONN@

ESATA_USB_OC# <19>

12

H

Disconnect

D=1D

L

D=2D

L

USB

ESATA

14

GND

15

GND

16

GND

17

GND

R303

R303 100K_0402_5%~D

100K_0402_5%~D

PWRSHARE_OE# <31>

USBP_P11

USBP_N11

USBP11+ USBP11-

USBP11+<19> USBP11-<19>

+3VS

DMIC_CLK<25>

DMIC0<25>

Layout note: Pin5 thru individual via to GND layer

Place close JCAM1

L27 WCM2012F2S-900T04_0805@L27 WCM2012F2S-900T04_0805@

1

2

4

R297 0_0402_5%~DR297 0_0402_5%~D R299 0_0402_5%~DR299 0_0402_5%~D L28 BLM18BB221SN1D_2P~DL28 BLM18BB221SN1D_2P~D

D35

1

CH1

2

Vn

3

CH2

CM1293-04SO_SOT23-6@

3

4

12 12 12

4

CH4

5

Vp

6

CH3

2

3

@

C458

100P_0402_50V8J~D@C458

100P_0402_50V8J~D

1

2

DMIC_CLK

+3VS

DMIC0

Camera Conn

USBP_P11

USBP_N11 DMIC_CLK DMIC0

@

C459

100P_0402_50V8J~D@C459

100P_0402_50V8J~D

1

2

JCAM1

1

2

3

4

5

6

7

8

GND

9

GND

MOLEX_48227-0701

CONN@

Cardreader Connector

FOX_GS12301-1011A-9F~D

Bluetooth

JBT1

BT_DET#<31>

COEX2_WLAN_ACTIVE<27,28>

BT_RADIO_OFF#<31>

BT_OFF#<31>

R995

@R995

@

10K_0402_5%~D

1 2

USBP10-

USBP10+

BT_DET# BT_ACTIVE COEX2_WLAN_ACTIVE

BT_OFF# USBP10+ BT_RADIO_OFF# USBP10-

BT_ACTIVE

@

C457 47P_0402_50V8J~D

1 2

@

C456 47P_0402_50V8J~D

1 2

JBT1

2

112

4

334

6

556

8

778

10

9910

12

111112

14

131314

16

GND15GND

HRS_DF12(3.0)-14DP-0.5V(86)~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BT_ACTIVE <27>

+3VS

USBP10+ <19>

USBP10- <19>

PCIE_ITX_C_CBRX_P4<16> PCIE_ITX_C_CBRX_N4<16>

PCIE_IRX_CBTX_P4<16> PCIE_IRX_CBTX_N4<16>

CLK_PCIE_CB<16> CLK_PCIE_CB#<16>

CB_CLKREQ#<16>

Compal Secret Data

2009/07/29 2010/07/29

Compal Secret Data

PLT_RST#<6,19,23,24,27,28,31>

Deciphered Date

USB_EN#<31>

USB_OC1#<19>

USBP1+<19> USBP1-<19>

+5VALW

+3VS

PCIE_ITX_C_CBRX_P4

PCIE_ITX_C_CBRX_N4

PCIE_IRX_CBTX_P4 PCIE_IRX_CBTX_N4

CLK_PCIE_CB CLK_PCIE_CB#

CB_CLKREQ# PLT_RST#

FOX_GS12301-1011A-9F~D

30

34

30

G4

29

33

29

G3

28

32

28

G2

27

31

27

G1

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

JCARD1

JCARD1 CONN@

CONN@

USBP2-<19> USBP2+<19>

USB_EN#<31>

USB_OC2#<19> BATT_CHG_LED#<31> BATT_LOW_LED#<31>

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

to Single USB board

+5VALW

JSUSB1

1

2

3

4

5

6

7

8

9

10

11

G1

12

G2

FCI_10089709-010010-LF

CONN@

of

30 57Monday, September 21, 2009

A

+3VALW

R306 10K_0402_5%~DR306 10K_0402_5%~D

R307 470_0402_5%~DR307 470_0402_5%~D

1 2

R0.3 Modify

R1237 10K_0402_5%~D@R1237 10K_0402_5%~D@ R926 10K_0402_5%~DR926 10K_0402_5%~D R314 2.2K_0402_5%~DR314 2.2K_0402_5%~D R315 2.2K_0402_5%~DR315 2.2K_0402_5%~D R324 10K_0402_5%~DR324 10K_0402_5%~D

1 2

R308 47K_0402_5%R308 47K_0402_5%

1 2

R309 47K_0402_5%R309 47K_0402_5%

1 2

For ENE strape pin

R0.3 Modify

+3VS

R317 2.2K_0402_5%~DR317 2.2K_0402_5%~D R318 2.2K_0402_5%~DR318 2.2K_0402_5%~D R319 4.7K_0402_5%~D@ R319 4.7K_0402_5%~D@

R320 4.7K_0402_5%~DR320 4.7K_0402_5%~D

R339 4.7K_0402_5%~DR339 4.7K_0402_5%~D R342 4.7K_0402_5%~DR342 4.7K_0402_5%~D

+5VS

R325 4.7K_0402_5%~DR325 4.7K_0402_5%~D R326 4.7K_0402_5%~DR326 4.7K_0402_5%~D

R948 200K_0402_5%R948 200K_0402_5%

12 12

1 2

EC Adam_Yang request

ICH_PCIE_WAKE#<17,24,27,28>

CLK_PCI_EC

12

R327

@ R327

@

10_0402_5%~D

1

C478

@C478

@

15P_0402_50V8J~D

2

12

12 12 12 12

12 12 12

12

PCIE_PME#

EC_RST#

C475 0.1U_0402_16V4Z~DC475 0.1U_0402_16V4Z~D

12

USB_DET#_DELAY

EN_KBL# EC_SMB_DA1 EC_SMB_CK1 MSEN#

KSO2 KSO1

EC_SMB_DA2 EC_SMB_CK2 LCD_TST

BT_RADIO_OFF#

EC_FB_SCLK EC_FB_SDATA

TP_DATA TP_CLK

KSO5

R977 0_0402_5%~DR977 0_0402_5%~D

TOUCHKEY_TINT<15,32>

KSI[0..7]<32>

1 2

WLAN_RADIO_OFF#<27>

EC_TX_P80_DATA<17,27>

EC_RX_P80_DATA<27>

PWR_BTN_LED#<32>

R328

1 2

20M_0603_5%@

20M_0603_5%@ Y5

Y5

1

C479

33P_0402_50V8J~D

C479

33P_0402_50V8J~D

2

32.768KHZ_12.5PF_QTFM28-32768K1

4 3

GG

+3VALW

C472

1000P_0402_50V7K~D

C472

C468

0.1U_0402_16V4Z~D

C468

0.1U_0402_16V4Z~D

C467

0.1U_0402_16V4Z~D

C467

0.1U_0402_16V4Z~D

1

2

1

2

0.1U_0402_16V4Z~D

C469

C470

0.1U_0402_16V4Z~D

C470

0.1U_0402_16V4Z~D

1

2

1000P_0402_50V7K~D

C471

1000P_0402_50V7K~D

C471

1000P_0402_50V7K~D

1

2

+EC_AVCC

1000P_0402_50V7K~D

ECAGND

C473

R0.3 modify

1

2

R0.3 modify

9

22

33

96

111

125

U19

VCC

GATEA20<20>

KB_RST#<20>

SERIRQ<15>

LPC_FRAME#<15,27>

LPC_AD3<15,27> LPC_AD2<15,27> LPC_AD1<15,27> LPC_AD0<15,27>

CLK_PCI_EC<19> PLT_RST#<6,19,23,24,27,28,30>

EC_SCI#<20>

KSO[0..18]<32>

EC_SMB_CK1<56> EC_SMB_DA1<56> EC_SMB_CK2<16,27,28,39> EC_SMB_DA2<16,27,28,39>

SLP_S3#<17>

PM_SLP_S5#<17>

EC_SMI#<20>

LID_SW#<32> EC_FB_SCLK<32> EC_FB_SDATA<32>

KB_BL_PWM#<32>

FAN_SPEED1<14>

ON_OFF<32>

EN_KBL#<32>

XCLKIXCLKO

GATEA20 KB_RST# SERIRQ LPC_FRAME#LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

CLK_PCI_EC PLT_RST#

EC_RST# EC_SCI# TOUCHKEY_TINT

KSI[0..7]

KSO[0..18]

EC_SMB_CK1

EC_SMB_DA1

EC_SMB_CK2

EC_SMB_DA2

SLP_S3# EC_RSMRST# PM_SLP_S5# EC_SMI# EC_ON LID_SW# BT_RADIO_OFF# EC_FB_SCLK

EC_FB_SDATA

PCIE_PME# KB_BL_PWM# FAN_SPEED1 WLAN_RADIO_OFF# EC_TX_P80_DATA EC_RX_P80_DATA ON_OFF

PWR_BTN_LED# EN_KBL#

XCLKI XCLKO

C481

33P_0402_50V8J~D

C481

33P_0402_50V8J~D

1

GA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LFRAME#

5

LAD3

7

LAD2

8

LAD1

10

LPC & MISC

LAD0

12

PCICLK

13

PCIRST#/GPIO05

37

ECRST#

20

SCI#/GPIO0E

38

CLKRUN#/GPIO1D

KSI0

55

KSI0/GPIO30

KSI1

56

KSI1/GPIO31

KSI2

57

KSI2/GPIO32

KSI3

58

KSI3/GPIO33

KSI4

59

KSI4/GPIO34

KSI5

60

KSI5/GPIO35

KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 KSO18

61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82

77 78 79 80

6 14 15 16 17 18 19 25 28 29 30 31 32 34 36

122 123

KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 KSO6/GPIO26 KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49

SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47

PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A

XCLK1 XCLK0

KB926QFD3_LQFP128

Int. K/B

Int. K/B Matrix

Matrix

SM Bus

PS2 Interface

11

D3 Version : P/N : SA00001J580

67

VCC

AVCC

INVT_PWM/PWM1/GPIO0F

BEEP#/PWM2/GPIO10

ACOFF/FANPWM2/GPIO13

PWM Output

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

AD Input

SELIO2#/AD5/GPIO43

DAC_BRIG/DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

DA Output

TP_CLK/PSCLK3/GPIO4E

TP_DATA/PSDAT3/GPIO4F

SPI Device Interface

SPI Flash ROM

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

BATT_CHGI_LED#/GPIO52

CAPS_LED#/GPIO53

GPIO

BATT_LOW_LED#/GPIO54

SUSP_LED#/GPIO55

VR_ON/XCLK32K/GPIO57

EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04

ICH_PWROK/GPXO06

GPO

GPIO

PM_SLP_S4#/GPXID1

GPI

GND

AGND

GND

24

35

69

94

113

ECAGND

FANPWM1/GPIO12

ADP_I/AD2/GPIO3A

AD3/GPIO3B

AD4/GPIO42

IREF/DA2/GPIO3E

DA3/GPIO3F

PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C

PSDAT2/GPIO4D

SDICS#/GPXOA00 SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICLK/GPIO58

SPICS#

CIR_RX/GPIO40

SYSON/GPIO56

AC_IN/GPIO59

EC_ON/GPXO05

EC_SWI#/GPXO06

BKOFF#/GPXO08

WL_OFF#/GPXO09

GPXO10 GPXO11

ENBKL/GPXID2

GPXID3 GPXID4 GPXID5 GPXID6 GPXID7

V18R

EC_PWM

21

BEEP#

23

PWRSHARE_EN#

26

ACOFF

27

63 64 65 66 75 76

68 70 71 72

83 84 85 86 87 88

97 98 99 109

119 120 126 128

73 74 89 90 91 92 93 95 121 127

100 101 102 103 104 105 106 107 108

110 112 114 115 116 117 118

124

C522 0.01U_0402_16V7K~DC522 0.01U_0402_16V7K~D

C476 0.01U_0402_16V7K~DC476 0.01U_0402_16V7K~D BATT_TEMP BATT_OVP

ADP_I AD_BID MSEN# SUS_PWR_ACK_R

EC_SUB_MUTE# EN_DFAN1 IREF

LCD_TST USB_EN# VGA_ON KSO5 TP_CLK TP_DATA

WPAN_RADIO_OFF# EN_WOL# BT_OFF# VGATE

FRD#SPI_SO FWR#SPI_SI SPI_CLK FSEL#SPICS#

EC_SPK_HP_MUTE# USB_DET#_DELAY FSTCHG BATT_CHG_LED# PWRSHARE_OE# BATT_LOW_LED# BKLT_KB_DET# SYSON VR_ON EC_ACIN

EC_LID_OUT#

ICH_PWROK BKOFF# WWAN_RADIO_OFF# LCD_VCC_TEST_EN CP_SEL

PCH_GPIO49 EC_ENBKL BT_DET# SBPWR_EN SUSP#

PBTN_OUT#

PS_ID

C480 1U_0603_10V4Z~DC480 1U_0603_10V4Z~D

1 2

C482 0.1U_0402_16V4Z~DC482 0.1U_0402_16V4Z~D

L29

L29 BLM18BD601SN1D_0603~D

BLM18BD601SN1D_0603~D

2

C474

0.1U_0402_16V4Z~D

1

BLM18BD601SN1D_0603~D

1 2 1 2

1 2

R1575 0_0402_5%~DR1575 0_0402_5%~D

12

L30

EC_PWM <35> BEEP# <25> PWRSHARE_EN# <30> ACOFF <49>

BATT_TEMP <56> BATT_OVP <56> ADP_I <49>

MSEN# <35>

EC_SUB_MUTE# <25> EN_DFAN1 <14> IREF <49> CHGVADJ <49>

LCD_TST <35> USB_EN# <30> VGA_ON <54> KSO5 <32> TP_CLK <32> TP_DATA <32>

WPAN_RADIO_OFF# <28> EN_WOL# <24> BT_OFF# <30> VGATE <13,17,55>

EC_SPK_HP_MUTE# <25> USB_DET#_DELAY <32> FSTCHG <49> BATT_CHG_LED# <30> PWRSHARE_OE# <30> BATT_LOW_LED# <30> BKLT_KB_DET# <32> SYSON <28,33,52> VR_ON <39,55>

EC_RSMRST# <17> EC_LID_OUT# <16> EC_ON <32> BT_RADIO_OFF# <30> ICH_PWROK <17> BKOFF# <35> WWAN_RADIO_OFF# <27> LCD_VCC_TEST_EN <35> CP_SEL <49>

PCH_GPIO49 <20,23> BT_DET# <30>

SBPWR_EN <33> SUSP# <28,33,51,52,53,54> PBTN_OUT# <6,17,23> PS_ID <48>

*

ECAGND ECAGND

SUS_PWR_ACK <17>

place close U19

15_0402_5%~D

* *

1 2

C346 100P_0402_50V8J~DC346 100P_0402_50V8J~D

*

SPI Flash (1Mbit/128Kbyte)

FSEL#SPICS#

R333

+3VALW+EC_AVCC

*

12

*

SPI_CLK_R

1

22P_0402_50V8J~D

22P_0402_50V8J~D C1122

C1122

2

R331

R331 15_0402_5%~D

15_0402_5%~D

1 2

R332

R332 15_0402_5%~D

15_0402_5%~D

Ra

Rb

+3VALW

R311

R311 100K_0402_5%~D

100K_0402_5%~D

1 2

AD_BID

12

R312

R312 56K_0402_1%~D

56K_0402_1%~D

Board ID

R0.3 modify

VCC 3.3V+/-5% 0.6V~1.6V

Board ID X00 X01 X02 MP X00 X01 X02 MP

Ra VGA

M96 M96 M96

M96 Madison Madison Madison Madison

100K Rb 0 +/- 5%

8.2K+/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 1% 100K +/- 1% 200K +/- 1%NC2.2V

Follow the suggestion of EC team to follow JAT10 setting.

EC_ENBKL

R383

100K_0402_5%~D

10K_0402_5%~D

1 2

2 1

D54

D54 CH751H-40PT_SOD323-2~D

CH751H-40PT_SOD323-2~D

+3VALW

EC_ACIN

R1215

Place under u20

JP1

112 334 556 778

E&T_2941-G08N-00E~D

CONN@

20mils

+SPI_R

U20

1

CS#

2

SO

3

WP#

4

GND

MX25L1005AMC-12G_SO8

2

+SPI_R

4

SPI_CLK_R

6

SPI_SI

8

SPI_CLK_R

R329

10K_0402_5%~D

12

8

VCC

7

HOLD#

6

SCLK

5

SI

12

SPI_CS# SPI_SO +SPI_R

SPI_CS# SPI_SOFRD#SPI_SO

1

C477

0.1U_0402_16V4Z~D

2

0 V

0.250V

0.503V

0.819V

1.185V

1.650V

3.3V

R557

R557 0_0402_5%~D

0_0402_5%~D

1 2

ACIN <17,25,39,48,49>

+3VALW

R330

12

22_0402_5%~D

+3VALW

2

C484

0.1U_0402_16V4Z~D

1

SPI_CLK_R

1 2

R0.3 modify

VGA_ENBKL <39>

22P_0402_50V8J~D

12

C483

R334

R334 15_0402_5%~D

15_0402_5%~D

FWR#SPI_SISPI_SI

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/07/29 2010/07/29

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

of

31 57Monday, September 21, 2009

A

B

C

D

E

Power Button Circuit

+3VALW

To power board

R335

1 2

D11

2

100K_0402_5%~D

51ON#

3

13

D

Q6

2

PMF3800SN_SC70-3

G

S

ON_OFF <31>

51ON# <48>

EC_ON

R0.3 Modify

12

R337

R337 10K_0402_5%~D

10K_0402_5%~D

1

BAT54C-7-F_SOT23~D

1 2

R336

R336 0_0402_5%~D

0_0402_5%~D

R896

200_0402_5%~D

PWR_LED+

1 2

+5VALW

PWR_BTN_LED#<31>

1 1

D30

1

PESD24VS2UT_SOT23-3~D

PWR_BTN_LED# PWR_ON-OFF_BTN#

PWR_ON-OFF_BTN#

3 2

JPBTN1

1

2

3

G5

4

G6

MOLEX_53261-0471

MOLEX_53261-0471 CONN@

CONN@

5 6

PWR_ON-OFF_BTN#<14>

EC_ON<31>

Place close JPBTN1

RTCVREF RTCVREF RTCVREF RTCVREF

2 2

USB_DETECT#<30>

USB_DETECT#

12

R1143

10K_0402_1%~D R1143

10K_0402_1%~D

2.2U_0603_10V7K~D

C1069

220K_0402_5%

12

R1144

12

D51

SDMK0340L-7-F

D51

SDMK0340L-7-F

2 1

U51

TC7SZ14FU_SSOP5~D

U51

1

NC

2

A

3

2 1

D52

SDMK0340L-7-F

1

2

5

P

4

Y

G

100K_0402_5%~D

CLOSE TO U48

C1068

0.1U_0402_16V4Z~D

2

G

12

R1145

1 2

@ D58

@

SDMK0340L-7-F

13

D

Q56

Q56 2N7002LT1G_SOT23-3

2N7002LT1G_SOT23-3

S

0_0402_5%~D

R1238

21

D58

51ON#

R0.3 Modify

USB_DET#_DELAY

51ON# <48>

USB_DET#_DELAY <31>

Power share

3 3

Keyboard back light

+5VS

1U_0603_10V6K~D

R928

300K_0402_5%

R928

300K_0402_5%

1 2

13

D

Q40

PMF3800SN_SC70-3

S

A

1U_0603_10V6K~D

C928

EN_KBL

B+_BIAS

EN_KBL#<31>

4 4

2

G

Q38

SI3456BDV-T1-E3 1N TSOP6 W/D

D

6

S

1

2

S

2 1

G

3

2M_0402_5%

1 2

0.75A_24V_1812L075-24DR~OK

45

20mil

R931

1 2

0_0805_5%~D

KB_BL_PWM#<31>

@

@ F1

F1

R929

+5VS_KBL

12

BKLT_KB_DET

12

BKLT_KB_DET KB_BL_PWM

13

D

2

G

S

20mil

R930

R930 100K_0402_5%~D

100K_0402_5%~D

20mil

B

+3VS

12

R927

R927 10K_0402_5%~D

10K_0402_5%~D

BKLT_KB_DET#

13

D

2

G

S

+5VS_KBL

JKBL1

1

2

3

GND

44GND

TYCO_2041084-4

TYCO_2041084-4 CONN@

CONN@

Q41

Q41 MMBF170LT1G 1N SOT23-3

MMBF170LT1G 1N SOT23-3

Q39

Q39 MMBF170LT1G 1N SOT23-3

MMBF170LT1G 1N SOT23-3

5 6

BKLT_KB_DET# <31>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

INT_KB_Conn.1

KSI[0..7]<31>

KSO[0..18]<31>

KSI[0..7] KSO[0..18]

Touch Screen Connector

D36

1

2

3

CH1

Vn

CH2

CH4

CH3

CM1293-04SO_SOT23-6@

Place close JTCH1

Touch PAD/B Conn.

+HALL_VCC

+3VALW

1 2

R933 0_0402_5%~DR933 0_0402_5%~D R934 10K_0402_5%~DR934 10K_0402_5%~D

1

C521

0.1U_0402_16V4Z~D

2

1 2

LID_SW#

Cap Sensor

EC_FB_SDATA<31>

EC_FB_SCLK<31>

TOUCHKEY_TINT<15,31>

C959

33P_0402_50V8J~D

FB_SDATA

1 2

C960

33P_0402_50V8J~D

FB_SCLK

1 2

Compal Secret Data

2009/07/29 2010/07/29

Compal Secret Data

4

5

Vp

6

JAE_FL4S030HB3R3000

30

KSI7

29

KSI6

28

KSI4

27

KSI2

26

KSI5

25

KSI1

24

KSI3

23

KSI0

22

KSO5

21

KSO4

20

KSO7

19

KSO6

18

KSO8

17

KSO3

16

KSO1

15

KSO2

14

KSO0

13

KSO12

12

KSO16

11

KSO15

10

KSO13

9

KSO14

8

KSO9

7

KSO11

6

KSO10

5

KSO17

4

KSO18

3 2 1

USBP9-

+3VS

USBP9+

0.1U_0402_16V4Z~D

Deciphered Date

32

30

GND

31

29

GND 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

JKB1

CONN@

USBP9-<19> USBP9+<19>

+5VS

1

C512

2

L77 BLM18BD601SN1D_0603~DL77 BLM18BD601SN1D_0603~D

1 2

L78 BLM18BD601SN1D_0603~DL78 BLM18BD601SN1D_0603~D

1 2

TOUCHKEY_TINT

D

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5

R0.3 Modify

+3VS

R1236 0_0402_5%~D@ R1236 0_0402_5%~D@

TP_CLK<31> LID_SW#<31> TP_DATA<31>

PESD5V2S2UT_SOT23-3~D

R0.3 Modify

C485 100P_0402_50V8J~D@C485 100P_0402_50V8J~D@ C487 100P_0402_50V8J~D@C487 100P_0402_50V8J~D@ C489 100P_0402_50V8J~D@C489 100P_0402_50V8J~D@ C490 100P_0402_50V8J~D@C490 100P_0402_50V8J~D@ C491 100P_0402_50V8J~D@C491 100P_0402_50V8J~D@ C493 100P_0402_50V8J~D@C493 100P_0402_50V8J~D@ C495 100P_0402_50V8J~D@C495 100P_0402_50V8J~D@ C497 100P_0402_50V8J~D@C497 100P_0402_50V8J~D@ C499 100P_0402_50V8J~D@C499 100P_0402_50V8J~D@ C501 100P_0402_50V8J~D@C501 100P_0402_50V8J~D@ C503 100P_0402_50V8J~D@C503 100P_0402_50V8J~D@ C505 100P_0402_50V8J~D@C505 100P_0402_50V8J~D@ C507 100P_0402_50V8J~D@C507 100P_0402_50V8J~D@ C509 100P_0402_50V8J~D@C509 100P_0402_50V8J~D@ C511 100P_0402_50V8J~D@C511 100P_0402_50V8J~D@

KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 KSO18

For EMI

JTCH1

1 2

USBP9-

USBP9+

TP_CLK LID_SW# TP_DATA

+HALL_VCC

R0.3 Modify

D56

10

1

G2

2

3

4

5

6

7

8

G1

9

JST_SM08B-SURS-TF(LF)(SN)~D

JST_SM08B-SURS-TF(LF)(SN)~D CONN@

CONN@

2

3

D55

1

R1003 0_0402_5%~D@R1003 0_0402_5%~D@

2

3

1

Title

SCHEMATICS, MB A5155

Size Document Number Rev

Custom

401808

Date: Sheet

+3VS

C513

100P_0402_50V8J~D

C513

100P_0402_50V8J~D

1

2

+5VS +3VS

FB_SDATA FB_SCLK

1 2

Compal Electronics, Inc.

C486 100P_0402_50V8J~D@C486 100P_0402_50V8J~D@ C488 100P_0402_50V8J~D@C488 100P_0402_50V8J~D@

C492 100P_0402_50V8J~D@C492 100P_0402_50V8J~D@ C494 100P_0402_50V8J~D@C494 100P_0402_50V8J~D@ C496 100P_0402_50V8J~D@C496 100P_0402_50V8J~D@ C498 100P_0402_50V8J~D@C498 100P_0402_50V8J~D@ C500 100P_0402_50V8J~D@C500 100P_0402_50V8J~D@ C502 100P_0402_50V8J~D@C502 100P_0402_50V8J~D@ C504 100P_0402_50V8J~D@C504 100P_0402_50V8J~D@ C506 100P_0402_50V8J~D@C506 100P_0402_50V8J~D@ C508 100P_0402_50V8J~D@C508 100P_0402_50V8J~D@ C510 100P_0402_50V8J~D@C510 100P_0402_50V8J~D@

1

C927

0.1U_0402_16V4Z~D

2

C514

1

2

E

JTP1

1

2

3

4

5

7

5

G1

6

8

6

G2

TYCO_2041084-6~D

CONN@

JCAP1

6

8

6

G2

5

7

5

G1

4

3

2

1

TYCO_2041084-6

TYCO_2041084-6 CONN@

CONN@

of

32 57Monday, September 21, 2009

A

B

C

D

E

+3VALW to +3VS Transfer

B+_BIAS

12

R338

330K_0402_5%

1 1

SUSP

2

G

1

2

13

D

Q7

PMF3800SN_SC70-3

S

10U_0805_10V4Z~D

C515

U21

U21 8 7

5

AO4468 1N SO8

12

R340

2M_0402_5%~D

4

R0.3 modify

1

2

+3VS+3VALW

8.73A

3 2 16

1

2

C524

0.01U_0402_25V7K~D

0.1U_0402_16V4Z~D

C516

C517

10U_0805_10V4Z~D

C517

10U_0805_10V4Z~D

1

2

+3VALW to +3V Transfer (PCH AUX Power)

B+_BIAS

R1152

330K_0402_5%

SBPWR_EN#

2

G

+3VALW +3V

U52

U52 SI4800BDY-T1-E3_SO8

SI4800BDY-T1-E3_SO8

1

C1070

2

10U_0805_10V4Z~D

C1073

8 7

5

3V_GATE

1

2

12

1 2

R1153

R1153 0_0402_5%~D

0_0402_5%~D

13

D

Q60

PMF3800SN_SC70-3

S

JP9@ JP9@

1 2

169mA

10U_0805_10V4Z~D

1 2 36

1

C1071

C1072

4

12

0.1U_0402_16V4Z~D

R1235

2M_0402_5%~D

0.01U_0402_25V7K~D

C1072

2

100K_0402_5%~D

SYSON#

SYSON

R355

R355 10K_0402_5%~D

10K_0402_5%~D

1 2

+5VALW

R354

2

G

12

13

D

Q16

Q16 PMF3800SN_SC70-3

PMF3800SN_SC70-3

S

+5VALW

12

R1151

100K_0402_5%~D

SBPWR_EN#<22>

SBPWR_EN<31>

SBPWR_EN#

SBPWR_EN

2

G

R1154

R1154 10K_0402_5%~D

10K_0402_5%~D

1 2

13

D

Q59

Q59 PMF3800SN_SC70-3

PMF3800SN_SC70-3

S

SYSON<28,31,52>

+5VALW to +5VS Transfer

3 2 16

7.69A

+5VS+5VALW

C520

10U_0805_10V4Z~D

C520

10U_0805_10V4Z~D

C519

0.1U_0402_16V4Z~D

C519

0.1U_0402_16V4Z~D 1

1

2

100K_0402_5%~D

SUSP

B+_BIAS

10U_0805_10V4Z~D

12

C518

R1216

330K_0402_5%

2 2

SUSP

2

G

1

2

13

D

Q68

PMF3800SN_SC70-3

S

U22

U22 8 7

5

AO4468 1N SO8

12

@

R341

390K_0402_5%

4

R0.3 modify

1

C525

0.01U_0402_25V7K~D

2

R379

2

G

+3VALW

12

13

D

Q75

Q75 PMF3800SN_SC70-3

PMF3800SN_SC70-3

S

C1147

SUSP

1 2

+5VALW

12

R360

R360 100K_0402_5%~D

100K_0402_5%~D

13

D

2

G

S

R361

R361 10K_0402_5%~D

10K_0402_5%~D

Q21

Q21 PMF3800SN_SC70-3

PMF3800SN_SC70-3

+3VALW

C1146

1 2

0.1U_0402_10V6K~D

5

U64

1

P

IN1

4

O

2

IN2

G

74AHC1G08GW_SOT353-5~D

1

2

0.01U_0402_25V7K~D

74AHC1G08GW_SOT353-5~D

3

@

12

R1252 0_0402_5%~D

R396

1 2

100K_0402_5%~D

C1148

1.5VS_DDR_PWRGD <52>

1

13

D

SUSP

2

G

2

G

Q13

S

0.01U_0402_25V7K~D

PMF3800SN_SC70-3

SUSP#<28,31,51,52,53,54>

SUSP#

+1.5V to +1.5VS Transfer

B+_BIAS

12

3 3

13

D

SUSP

D

2

G

S

+1.5V

R344

R344 470K_0402_5%

470K_0402_5%

Q10

PMF3800SN_SC70-3

Q55

Q55 8 7

5

AO4468 1N SO8

12

R1157

2M_0402_5%~D

3 2 16

4

R0.3 modify

1

C532

C532 470P_0402_50V7K~D

470P_0402_50V7K~D

2

+1.5V to +1.5VS_DDR Transfer

B+_BIAS +1.5V +1.5V_CPU_DDR

12

R346

R346 470K_0402_5%

470K_0402_5%

4 4

13

D

2

G

D

Q11

PMF3800SN_SC70-3

S

SUSP

Q73

D D D D

SI4856ADY_SO8@

R1158

2M_0402_5%~D

1

S

2

S

3

S

4

G

R0.3 modify

1

C534

C534 470P_0402_50V7K~D

470P_0402_50V7K~D

2

8 7 6 5

12

A

C531

C536

+1.5VS

10U_0805_10V4Z~D

R345

20K_0402_1%~D

R345

20K_0402_1%~D

12

1

2

10U_0805_10V4Z~D

R349

20K_0402_1%~D

R349

20K_0402_1%~D

12

1

2

B

Discharge Circuit

+1.5V +1.05VS +1.1VS_VTT

12

R353

R353 470_0402_5%~D

470_0402_5%~D

13

D

2

G

+1.5V_CPU_DDR

2

G

C

D

Q15

S

PMF3800SN_SC70-3

12

220_0402_5%~D

220_0402_5%~D R364

R364

13

D

Q74

S

PMF3800SN_SC70-3

2009/07/29 2010/07/29

SBPWR_EN#

SUSP

SYSON#

SUSP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3V

12

R1155

R1155 470_0402_5%~D

470_0402_5%~D

13

D

2

G

Q61

S

PMF3800SN_SC70-3

+0.75VS

12

R358

R358 470_0603_5%

470_0603_5%

13

D

2

G

Q19

S

PMF3800SN_SC70-3

Compal Secret Data

Deciphered Date

SUSP

2

SUSP SUSP

2

D

12

13

G

+5VS

12

13

G

R352

R352 470_0402_5%~D

470_0402_5%~D

D

Q12

S

PMF3800SN_SC70-3

R359

R359 470_0402_5%~D

470_0402_5%~D

D

Q20

S

PMF3800SN_SC70-3

Title

Size Document Number Rev

Custom

401808

Date: Sheet

SUSP

Compal Electronics, Inc.

SCHEMATICS, MB A5155

2

G

+3VS

2

G

E

R1034

R1034 470_0603_5%

470_0603_5%

1 2 13

D

Q54

S

PMF3800SN_SC70-3

12

R356

R356 470_0402_5%~D

470_0402_5%~D

13

D

Q17

S

PMF3800SN_SC70-3

A

33 57Monday, September 21, 2009

A

of

5

FD2

FD3

FD1

FD1 FIDUCAL

FIDUCAL

@

D D

H_2P2

H37

H37 HOLEA@

HOLEA@

1

H38

H38 HOLEA@

HOLEA@

1

H_2P2

FIDUCAL

1

H6 HOLEA@H6HOLEA@

1

FD3 FIDUCAL

FIDUCAL

@

4

FD4

FD4 FIDUCAL

FIDUCAL

@

1

3

ZZZ

PCB

2

1

H_3P1

C C

H_1P6N

H_3P0

H_3P2

B B

H_4P0

H_3P0X4P0

H2 HOLEA@H2HOLEA@

H7 HOLEA@H7HOLEA@

H17

H17 HOLEA@

HOLEA@

H25

H25 HOLEA@

HOLEA@

H29

H29 HOLEA@

HOLEA@

1

H10

H8

H9

HOLEA@H8HOLEA@

HOLEA@H9HOLEA@

H26

H26 HOLEA@

HOLEA@

H18

H18 HOLEA@

HOLEA@

H3 HOLEA@H3HOLEA@

1

H19

H19 HOLEA@

HOLEA@

1

H4 HOLEA@H4HOLEA@

1

H27

H27 HOLEA@

HOLEA@

1

H10 HOLEA@

HOLEA@

1

H24

H24 HOLEA@

HOLEA@

1

H20

H20 HOLEA@

HOLEA@

1

H28

H28 HOLEA@

HOLEA@

1

H11

H11 HOLEA@

HOLEA@

H21

H21 HOLEA@

HOLEA@

1

H30

H30 HOLEA@

HOLEA@

H12

H12 HOLEA@

HOLEA@

1

H31

H31 HOLEA@

HOLEA@

1

H5 HOLEA@H5HOLEA@

H23

H23 HOLEA@

HOLEA@

1

H32

H32 HOLEA@

HOLEA@

H14

H14 HOLEA@

HOLEA@

1

H33

H33 HOLEA@

HOLEA@

1

H15

H15 HOLEA@

HOLEA@

H35

H35 HOLEA@

HOLEA@

H16

H16 HOLEA@

HOLEA@

1

H36

H36 HOLEA@

HOLEA@

1

A A

Security Classification

2009/08/20 2010/08/20

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/08/20 2010/08/20

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

A

34 57Monday, September 21, 2009

of

1

of

5

C R T

D D

C C

VGA_CRT_R<39>

VGA_CRT_G<39>

VGA_CRT_B<39>

+3VS_DELAY +CRT_VCC+3VS_DELAY +CRT_VCC+3VS_DELAY

CRT_DDC_DATA<39>

CRT_DDC_CLK<39>

1 2

R893 0_0603_5%~DR893 0_0603_5%~D

1 2

R894 0_0603_5%~DR894 0_0603_5%~D

1 2

R895 0_0603_5%~DR895 0_0603_5%~D

2.2K_0402_5%~D

R369

2.2K_0402_5%~D

R369

2.2K_0402_5%~D

1 2

S

R370

S

G

2

PMF3800SN_SC70-3

13

D

Q23

PMF3800SN_SC70-3

R366

150_0402_1%~D

R366

150_0402_1%~D

R367

150_0402_1%~D

R367

150_0402_1%~D

12

R371

2K_0402_1%~D

R371

2K_0402_1%~D

G

1 2

2

13

D

Q22

CRT_R

CRT_G

CRT_B

R368

1

2

2K_0402_1%~D

1 2

CRT_DDC_DATA_C

CRT_DDC_CLK_C

22P_0402_50V8J~D

R372

4

+3VS_DELAY

L31

BLM18BA220SN1D_2P~D

1 2

BLM18BA220SN1D_2P~D

1 2

BLM18BA220SN1D_2P~D

1 2

22P_0402_50V8J~D

@

C537

@

C539

C538

1

2

CRT_HSYNC<39>

CRT_VSYNC<39>

L32

L33

CRT_R_L

CRT_G_L

CRT_B_L

For EMI

@D14

@

DAN217_SC59-3

4.7P_0402_50V8C~D

1

2

C545

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D 1 2

CRT_HSYNC

C546

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D 1 2

CRT_VSYNC

D14

DAN217_SC59-3

1

2

3

C540

1

2

+CRT_VCC

1

5

P

OE#

A2Y

G

74AHCT1G125GW_SOT353-5

3

+CRT_VCC

1

5

P

OE#

A2Y

G

3

D15

@D15

@

2

C541

4.7P_0402_50V8C~D

C541

4.7P_0402_50V8C~D

U26

U27

U27 74AHCT1G125GW_SOT353-5

74AHCT1G125GW_SOT353-5

1

3

4

D16

@D16

@

DAN217_SC59-3

1

2

C542

4.7P_0402_50V8C~D

C542

4.7P_0402_50V8C~D

1

2

R373

10K_0402_5%~D

1 2

3

2

+5VS

W=40mils

MSEN#<31>

R1160

D_CRT_HSYNC HSYNC_L

D_CRT_VSYNC

R1160

1 2

R1161

1 2

0_0603_5%~D

MSEN# CRT_R_L

CRT_DDC_DATA_C CRT_G_L

HSYNC_L CRT_B_L

VSYNC_L

CRT_DDC_CLK_C

C543

100P_0402_50V8J~D

C543

100P_0402_50V8J~D

VSYNC_L

C547

15P_0402_50V8J~D

C547

15P_0402_50V8J~D

1

2

D17

D17 2 1 3

NC

BAT1000-7-F_SOT23-3~D

C544

100P_0402_50V8J~D

C544

100P_0402_50V8J~D

1

2

C548

15P_0402_50V8J~D

C548

15P_0402_50V8J~D

1

2

W=40mils

+CRT_VCC

1

2

6

11

1 7

12

2 8

13

3 9

14

4 10 15

5

C535

1U_0603_10V6K~D

JCRT1

16

G

17

G

TYCO_1775763-2

TYCO_1775763-2 CONN@

CONN@

1

+LCDVDD +5V

R376

R376 470_0805_5%

R0.3 Modify

SSM3K7002FU_SC70-3~D

B B

VGA_LVDDEN<38>

LCD_VCC_TEST_EN<31>

A A

BKOFF#<31>

VGA_LVDDEN

LCD_VCC_TEST_EN

BKOFF# DISPOFF#

CH751H-40PT_SOD323-2~D

5

SSM3K7002FU_SC70-3~D

D37

2

3

BAT54C-7-F_SOT23~D

D19

21

1

+3VS

12

R382

4.7K_0402_5%~D

470_0805_5%

1 2 13

D

Q24

S

R380

10K_0402_5%~D

G

R377

R377 47K_0402_5%

47K_0402_5%

1 2

R378

R378 56K_0402_5%

56K_0402_5%

2

13

D

2

G

12

S

12

Q26

Q26 BSS138_SOT23~D

BSS138_SOT23~D

R0.3 Modify

VGA_PWM<38> EC_PWM<31>

4

W=60mils

+3VS

S

AO3413_SOT23-3

G

Q25

2

C549

0.1U_0402_16V4Z~D

C549

0.1U_0402_16V4Z~D

1

2

1 2

74AHC1G32GW_SOT353-5~D

D

1 3

+LCDVDD

1

C550

4.7U_0805_10V4Z~D

2

+3VS +3VS

5

U54

P

INA

4

O

INB

G

3

R944

@R944

@ 0_0402_5%~D

0_0402_5%~D

12

R945

@R945

@ 0_0402_5%~D

0_0402_5%~D

12

6.5

W=60mils

+LCDVDD

1

2

12

R394

@R394

@ 10K_0402_5%~D

10K_0402_5%~D

INVT_PWM

1000P_0402_50V7K~D

1

C551

0.1U_0402_16V4Z~D

2

+LCDVDD

R02: Add

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R381 0_0805_5%~D@R381 0_0805_5%~D@

B+ +INV_PWR_SRC

40mil

C1126

2

G

3

1 2

Q70

Q70 SI3457BDV-T1-E3_TSOP6~D

B+

12

13

D

S

SI3457BDV-T1-E3_TSOP6~D

D

6

S

4 5

R1242

100K_0402_5%

R1242

100K_0402_5%

PWR_SRC_ON

R1243

R1243 100K_0402_5%

100K_0402_5%

Q71

Q71 2N7002W-7-F_SOT323-3~D

2N7002W-7-F_SOT323-3~D

2 1

G

3

2009/07/29 2010/07/29

40mil

+INV_PWR_SRC

1

C1127

0.1U_0603_50V4Z~D

2

Compal Secret Data

Deciphered Date

LCD_TST<31>

LVDS_DDC_CLK<39>

LVDS_DDC_DATA<39>

@

1 2

C1128 5P_0402_50V8C

C1128 5P_0402_50V8C @

@

1 2

C1129 5P_0402_50V8C

@

1 2

C1130 5P_0402_50V8C

C1130 5P_0402_50V8C @

@

1 2

C1131 5P_0402_50V8C

Reserve for EMI (Place close to JLVDS1)

2

40

+LCDVDD

+3VS

LCD_TST R374 0_0402_5%~DR374 0_0402_5%~D R375 0_0402_5%~DR375 0_0402_5%~D

LVDS_A0-<38> LVDS_A0+<38>

LVDS_A1-<38> LVDS_A1+<38>

LVDS_A2-<38> LVDS_A2+<38>

LVDS_ACLK-<38> LVDS_ACLK+<38>

LVDS_B0-<38> LVDS_B0+<38>

LVDS_B1-<38> LVDS_B1+<38>

LVDS_B2-<38> LVDS_B2+<38>

LVDS_BCLK-<38> LVDS_BCLK+<38>

+INV_PWR_SRC

12 12

EDID_CLK_LCD

EDID_DATA_LCD

LVDS_A0LVDS_A0+

LVDS_A1LVDS_A1+

LVDS_A2LVDS_A2+

LVDS_ACLK-

LVDS_ACLK+

LVDS_B0LVDS_B0+

LVDS_B1LVDS_B1+

LVDS_B2LVDS_B2+

LVDS_BCLK-

LVDS_BCLK+

INVT_PWM DISPOFF#

W=60mils

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

JLVDS1

JLVDS1 JAE_FI-G40SB-VF25-R2000

JAE_FI-G40SB-VF25-R2000 CONN@

CONN@

1

49

G9

48

G8

47

G7

46

G6

45

G5

44

G4

43

G3

42

G2

41

G1

A

of

35 57Monday, September 21, 2009

5

D D

HDMI_A3N_VGA<39> HDMI_A3P_VGA<39> HDMI_A2N_VGA<39> HDMI_A2P_VGA<39> HDMI_A1N_VGA<39> HDMI_A1P_VGA<39> HDMI_A0N_VGA<39>

+5VS

C C

B B

A A

100K_0402_5%~D

R390

12

HDMI_A0P_VGA<39>

13

D

2

G

Q27

G

Q27

PMF3800SN_SC70-3

S

DP_AUX PULLUP POWER RAIL MUST BE UP BEFORE CORE POWER RAIL

HDMI_DDC_CLK<39>

HDMI_DDC_DATA<39>

C552 0.1U_0402_10V6K~DC552 0.1U_0402_10V6K~D C553 0.1U_0402_10V6K~DC553 0.1U_0402_10V6K~D C554 0.1U_0402_10V6K~DC554 0.1U_0402_10V6K~D C555 0.1U_0402_10V6K~DC555 0.1U_0402_10V6K~D C557 0.1U_0402_10V6K~DC557 0.1U_0402_10V6K~D C558 0.1U_0402_10V6K~DC558 0.1U_0402_10V6K~D C559 0.1U_0402_10V6K~DC559 0.1U_0402_10V6K~D C560 0.1U_0402_10V6K~DC560 0.1U_0402_10V6K~D

R385 499_0402_1%~DR385 499_0402_1%~D R386 499_0402_1%~DR386 499_0402_1%~D R387 499_0402_1%~DR387 499_0402_1%~D R388 499_0402_1%~DR388 499_0402_1%~D R389 499_0402_1%~DR389 499_0402_1%~D R391 499_0402_1%~DR391 499_0402_1%~D R392 499_0402_1%~DR392 499_0402_1%~D R393 499_0402_1%~DR393 499_0402_1%~D

+3VS_DELAY

2N7002DW-7-F_SOT363-6~D

1 2

R399 0_0402_5%~DR399 0_0402_5%~D

4

@Q28B

@

2N7002DW-7-F_SOT363-6~D

1 2

4

PLACE AC CAP CLOSE TO CONNECTOR

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

12 12 12 12 12 12 12 12

+5VS

Close to Connect

2

Q28A

@Q28A

@

+3VS_DELAY

Close to Connect

5

Q28B

R408 0_0402_5%~DR408 0_0402_5%~D

12

R395

61

+5VS

12

R406

3

2K_0402_1%~D

DDC_CLK_HDMI

2K_0402_1%~D

DDC_DAT_HDMI

3

TMDS_TXCN TMDS_TXCP TMDS_TX0N TMDS_TX0P TMDS_TX1N TMDS_TX1P TMDS_TX2N TMDS_TX2P

PLACE PULL DOWN RESISTORS CLOSE TO DIFFERENTIAL PAIRS CONNECTED TO SOLID GROUND FLOOD WHICH IS CONTROLLED BY THE FET AVOID STUBS TO ALL DIFFERENTIAL TRACES

Place close JHDMI1

@

R986 0_0402_5%~D

1 2

L73

TMDS_TXCN

TMDS_TXCP

TMDS_TX0N TMDS_L_TX0N

TMDS_TX0P

TMDS_TX1N

TMDS_TX1P

TMDS_TX2N

TMDS_TX2P

L73

1

4

MURATA DLW21SN900HQ2L

@

R987 0_0402_5%~D

1 2

@

R988 0_0402_5%~D

1 2

L74

1

4

MURATA DLW21SN900HQ2L

@

R989 0_0402_5%~D

1 2

@

R990 0_0402_5%~D

1 2

L75

1

4

MURATA DLW21SN900HQ2L

@

R991 0_0402_5%~D

1 2

@

R992 0_0402_5%~D

1 2

L76

1

4

MURATA DLW21SN900HQ2L

@

R993 0_0402_5%~D

1 2

2

+3VS_DELAY

R400

150K_0402_5%

2

1 2

B

R404

R404 10K_0402_5%~D

10K_0402_5%~D

Co-lay

HDMI_HPLUG

DDC_DAT_HDMI DDC_CLK_HDMI

TMDS_L_TXCN TMDS_L_TXCP

TMDS_L_TX0N TMDS_L_TX0P

TMDS_L_TX1N TMDS_L_TX1P

TMDS_L_TX2N TMDS_L_TX2P

R400

HDMI_HPLUG

12

R402

@R402

@ 365K_0402_1%

365K_0402_1%

19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

C

Q29

MMBT3904_NL_SOT23-3

R401 0_0402_5%~DR401 0_0402_5%~D

HDMI_HPD<39>

TMDS_L_TXCN

2

TMDS_L_TXCP

3

2

TMDS_L_TX0P

3

TMDS_L_TX1N

2

TMDS_L_TX1P

3

TMDS_L_TX2N

2

TMDS_L_TX2P

3

1 2

+5VS

Q29

F3

@F3

@

1.5A_6V_1206L150PR~D

1.5A_6V_1206L150PR~D 12

R384

0_1206_5%~D

12

C556

1U_0402_6.3V6K~D

1 2

E

3 1

12

1

JHDMI1

HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKCK_shield CK+ D0D0_shield D0+ D1D1_shield D1+

GND

D2-

GND

D2_shield

GND

D2+

GND

FOX_QJ5119L-NVBT-7F

FOX_QJ5119L-NVBT-7F CONN@

CONN@

20 21 22 23

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/07/29 2010/07/29

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

A

of

36 57Monday, September 21, 2009

1

5

D D

4

3

2

1

Place close JDP1

D38

@8D38

@

1 2

DISP_DDC_EN

C571

4 5 3

8

RCLAMP0524P.TCT~D

D39

@8D39

@

1 2 4 5 3

8

RCLAMP0524P.TCT~D

+5VS

12

61

1

2

C561 0.1U_0402_10V6K~DC561 0.1U_0402_10V6K~D

DISP_A0N_VGA<39> DISP_A0P_VGA<39>

DISP_A1N_VGA<39> DISP_A1P_VGA<39>

DISP_A2N_VGA<39> DISP_A2P_VGA<39>

DISP_A3N_VGA<39>

C C

DISP_A3P_VGA<39>

12

C562 0.1U_0402_10V6K~DC562 0.1U_0402_10V6K~D

12

C563 0.1U_0402_10V6K~DC563 0.1U_0402_10V6K~D

12

C564 0.1U_0402_10V6K~DC564 0.1U_0402_10V6K~D

12

C566 0.1U_0402_10V6K~DC566 0.1U_0402_10V6K~D

12

C568 0.1U_0402_10V6K~DC568 0.1U_0402_10V6K~D

12

C569 0.1U_0402_10V6K~DC569 0.1U_0402_10V6K~D

12

C570 0.1U_0402_10V6K~DC570 0.1U_0402_10V6K~D

12

DISP_A0N DISP_A0P

DISP_A1N DISP_A1P

DISP_A2N DISP_A2P

DISP_A3N DISP_A3P

DISP_A1N DISP_A1N

DISP_A2P DISP_A2P DISP_A2N DISP_A2N DISP_A3P DISP_A3P DISP_A3N DISP_A3N

2

Q31A

@Q31A

@ 2N7002DW-7-F_SOT363-6~D

2N7002DW-7-F_SOT363-6~D

DISP_DDC_EN

R411

0_0402_5%~D

B B

DP_DDC_CLK<39> DP_DDC_DATA<39>

1 2 1 2

0_0402_5%~D

R412

DP_DDC_CLK_R DP_DDC_DATA_R

DISP_DDC_EN

6 1 3

@Q31B

@

2N7002DW-7-F_SOT363-6~D

5

0.1U_0402_10V6K~D

4

0.1U_0402_10V6K~D

2

@Q32A

@

2N7002DW-7-F_SOT363-6~D

6 1 3

@Q32B

@

2N7002DW-7-F_SOT363-6~D

5

Q31B

Q32A

Q32B

C565

C567

12

R410

R410 100K_0402_1%~D

100K_0402_1%~D

12 12

DISP_DDC_CLK_C DISP_DDC_DAT_C

12

R413

R413 100K_0402_1%~D

100K_0402_1%~D

0.1U_0402_10V6K~D

+3VS_DELAY

4

DISP_A0PDISP_A0P

10

DISP_A0NDISP_A0N

9

DISP_A1PDISP_A1P

7 6

10 9 7 6

R414

R414 100K_0402_1%~D

100K_0402_1%~D

2

Q30A

Q30A 2N7002DW-7-F_SOT363-6~D

2N7002DW-7-F_SOT363-6~D

+3VS_DELAY

+5VS

12

R415

R415 100K_0402_1%~D

100K_0402_1%~D

3

5

2N7002DW-7-F_SOT363-6~D

4

Q30B

Close connect

+3VS

Co-lay

F2

1 2

1.5A_6V_1206L150PR~D

R409 0_1206_5%~D@R409 0_1206_5%~D@

DISP_A0P DISP_A0N

DISP_A1P DISP_A1N

DISP_A2P DISP_A2N

DISP_A3P DISP_A3N

DISP_EN DISP_CEC DISP_DDC_CLK_C

DISP_DDC_DAT_C DISP_HD

+3VS_DP

12

R416 5.1M_0402_5%R416 5.1M_0402_5%

12

+3VS_DP

C953

0.1U_0402_16V4Z~D

C953

0.1U_0402_16V4Z~D

C952

10U_0805_10V4Z~D

C952

10U_0805_10V4Z~D

1

2

JDP1

1

LANE0_P

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

21

R943 1M_0402_5%~DR943 1M_0402_5%~D

C573 22U_0805_6.3V6M~DC573 22U_0805_6.3V6M~D

C572 0.1U_0402_10V6K~DC572 0.1U_0402_10V6K~D

12

1

2

22 23 24

GND

LANE0_N

LANE1_P

GND

LANE1_N

LANE2_P

GND

LANE2_N

LANE3_P

GND

LANE3_N

CONFIG1

CONFIG2

AUXCH_P

GND

AUXCH_N

HPD

RETURN

DP_PWR

GROUND

FOX_3V102P1-RB2BT-8F

FOX_3V102P1-RB2BT-8F CONN@

CONN@

R417

C

Q33

MMBT3904_NL_SOT23-3

R418 0_0402_5%~DR418 0_0402_5%~D

DP_HPD<39>

1 2

Q33

E

3 1

12

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/07/29 2010/07/29

Compal Secret Data

R417

150K_0402_5%

1 2

2

B

R421

R421 10K_0402_5%~D

10K_0402_5%~D

Deciphered Date

R419

@R419

@

365K_0402_1%

2

12

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

1

37 57Monday, September 21, 2009

A

of

37 57Monday, September 21, 2009

5

D D

U28A

4

3

2

1

PEG_HTX_C_GRX_P0<5> PEG_HTX_C_GRX_N0<5>

PEG_HTX_C_GRX_P1<5> PEG_HTX_C_GRX_N1<5>

PEG_HTX_C_GRX_P2<5> PEG_HTX_C_GRX_N2<5>

PEG_HTX_C_GRX_P3<5> PEG_HTX_C_GRX_N3<5>

PEG_HTX_C_GRX_P4<5> PEG_HTX_C_GRX_N4<5>

C C

B B

PEG_HTX_C_GRX_P5<5> PEG_HTX_C_GRX_N5<5>

PEG_HTX_C_GRX_P6<5> PEG_HTX_C_GRX_N6<5>

PEG_HTX_C_GRX_P7<5> PEG_HTX_C_GRX_N7<5>

PEG_HTX_C_GRX_P8<5> PEG_HTX_C_GRX_N8<5>

PEG_HTX_C_GRX_P9<5> PEG_HTX_C_GRX_N9<5>

PEG_HTX_C_GRX_P10<5> PEG_HTX_C_GRX_N10<5>

PEG_HTX_C_GRX_P11<5> PEG_HTX_C_GRX_N11<5>

PEG_HTX_C_GRX_P12<5> PEG_HTX_C_GRX_N12<5>

PEG_HTX_C_GRX_P13<5> PEG_HTX_C_GRX_N13<5>

PEG_HTX_C_GRX_P14<5> PEG_HTX_C_GRX_N14<5>

PEG_HTX_C_GRX_P15<5> PEG_HTX_C_GRX_N15<5>

CLK_PEG_VGA<16> CLK_PEG_VGA#<16>

Madison

VGA_RST#<19>

madison@

12

R1571 10K_0402_5%~D

AA38

PCIE_RX0P

Y37

PCIE_RX0N

Y35

PCIE_RX1P

W36

PCIE_RX1N

W38

PCIE_RX2P

V37

PCIE_RX2N

V35

PCIE_RX3P

U36

PCIE_RX3N

U38

PCIE_RX4P

T37

PCIE_RX4N

T35

PCIE_RX5P

R36

PCIE_RX5N

R38

PCIE_RX6P

P37

PCIE_RX6N

P35

PCIE_RX7P

N36

PCIE_RX7N

N38

PCIE_RX8P

M37

PCIE_RX8N

M35

PCIE_RX9P

L36

PCIE_RX9N

L38

PCIE_RX10P

K37

PCIE_RX10N

K35

PCIE_RX11P

J36

PCIE_RX11N

J38

PCIE_RX12P

H37

PCIE_RX12N

H35

PCIE_RX13P

G36

PCIE_RX13N

G38

PCIE_RX14P

F37

PCIE_RX14N

F35

PCIE_RX15P

E37

PCIE_RX15N

CLOCK

AB35

PCIE_REFCLKP

AA36

PCIE_REFCLKN

AJ21

NC#1

AK21

NC#2

AH16

NC_PWRGOOD

AA30

PERSTB

216-0729002 A12 M96_BGA962

216-0729002 A12 M96_BGA962 madison@

madison@

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P

PCI EXPRESS INTERFACE

PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

PCIE_TX8P PCIE_TX8N

PCIE_TX9P PCIE_TX9N

PCIE_TX10P PCIE_TX10N

PCIE_TX11P PCIE_TX11N

PCIE_TX12P PCIE_TX12N

PCIE_TX13P PCIE_TX13N

PCIE_TX14P PCIE_TX14N

PCIE_TX15P PCIE_TX15N

CALIBRATION

PCIE_CALRP PCIE_CALRN

PEG_GTX_HRX_P0

Y33

PEG_GTX_HRX_N0

Y32

PEG_GTX_HRX_P1

W33

PEG_GTX_HRX_N1

W32

PEG_GTX_HRX_P2

U33

PEG_GTX_HRX_N2

U32

PEG_GTX_HRX_P3

U30

PEG_GTX_HRX_N3

U29

PEG_GTX_HRX_P4

T33

PEG_GTX_HRX_N4

T32

PEG_GTX_HRX_P5

T30

PEG_GTX_HRX_N5

T29

PEG_GTX_HRX_P6

P33

PEG_GTX_HRX_N6

P32

PEG_GTX_HRX_P7

P30

PEG_GTX_HRX_N7

P29

PEG_GTX_HRX_P8

N33

PEG_GTX_HRX_N8

N32

PEG_GTX_HRX_P9

N30

PEG_GTX_HRX_N9

N29

PEG_GTX_HRX_P10

L33

PEG_GTX_HRX_N10

L32

PEG_GTX_HRX_P11

L30

PEG_GTX_HRX_N11

L29

PEG_GTX_HRX_P12

K33

PEG_GTX_HRX_N12

K32

PEG_GTX_HRX_P13

J33

PEG_GTX_HRX_N13

J32

PEG_GTX_HRX_P14

K30

PEG_GTX_HRX_N14

K29

PEG_GTX_HRX_P15

H33

PEG_GTX_HRX_N15

H32

R424 1.27K_0402_1%R424 1.27K_0402_1%

Y30

1 2

R426 2K_0402_1%~DR426 2K_0402_1%~D

Y29

1 2

C574 0.1U_0402_16V7K~DC574 0.1U_0402_16V7K~D

1 2

C575 0.1U_0402_16V7K~DC575 0.1U_0402_16V7K~D

1 2

C576 0.1U_0402_16V7K~DC576 0.1U_0402_16V7K~D

1 2

C577 0.1U_0402_16V7K~DC577 0.1U_0402_16V7K~D

1 2

C578 0.1U_0402_16V7K~DC578 0.1U_0402_16V7K~D

1 2

C579 0.1U_0402_16V7K~DC579 0.1U_0402_16V7K~D

1 2

C580 0.1U_0402_16V7K~DC580 0.1U_0402_16V7K~D

1 2

C581 0.1U_0402_16V7K~DC581 0.1U_0402_16V7K~D

1 2

C582 0.1U_0402_16V7K~DC582 0.1U_0402_16V7K~D

1 2

C583 0.1U_0402_16V7K~DC583 0.1U_0402_16V7K~D

1 2

C584 0.1U_0402_16V7K~DC584 0.1U_0402_16V7K~D

1 2

C585 0.1U_0402_16V7K~DC585 0.1U_0402_16V7K~D

1 2

C586 0.1U_0402_16V7K~DC586 0.1U_0402_16V7K~D

1 2

C587 0.1U_0402_16V7K~DC587 0.1U_0402_16V7K~D

1 2

C588 0.1U_0402_16V7K~DC588 0.1U_0402_16V7K~D

1 2

C589 0.1U_0402_16V7K~DC589 0.1U_0402_16V7K~D

1 2

C590 0.1U_0402_16V7K~DC590 0.1U_0402_16V7K~D

1 2

C591 0.1U_0402_16V7K~DC591 0.1U_0402_16V7K~D

1 2

C592 0.1U_0402_16V7K~DC592 0.1U_0402_16V7K~D

1 2

C593 0.1U_0402_16V7K~DC593 0.1U_0402_16V7K~D

1 2

C594 0.1U_0402_16V7K~DC594 0.1U_0402_16V7K~D

1 2

C595 0.1U_0402_16V7K~DC595 0.1U_0402_16V7K~D

1 2

C596 0.1U_0402_16V7K~DC596 0.1U_0402_16V7K~D

1 2

C597 0.1U_0402_16V7K~DC597 0.1U_0402_16V7K~D

1 2

C598 0.1U_0402_16V7K~DC598 0.1U_0402_16V7K~D

1 2

C599 0.1U_0402_16V7K~DC599 0.1U_0402_16V7K~D

1 2

C600 0.1U_0402_16V7K~DC600 0.1U_0402_16V7K~D

1 2

C601 0.1U_0402_16V7K~DC601 0.1U_0402_16V7K~D

1 2

C602 0.1U_0402_16V7K~DC602 0.1U_0402_16V7K~D

1 2

C603 0.1U_0402_16V7K~DC603 0.1U_0402_16V7K~D

1 2

C604 0.1U_0402_16V7K~DC604 0.1U_0402_16V7K~D

1 2

C605 0.1U_0402_16V7K~DC605 0.1U_0402_16V7K~D

1 2

+1.1VS

PEG_GTX_C_HRX_P0 <5> PEG_GTX_C_HRX_N0 <5>

PEG_GTX_C_HRX_P1 <5> PEG_GTX_C_HRX_N1 <5>

PEG_GTX_C_HRX_P2 <5> PEG_GTX_C_HRX_N2 <5>

PEG_GTX_C_HRX_P3 <5> PEG_GTX_C_HRX_N3 <5>

PEG_GTX_C_HRX_P4 <5> PEG_GTX_C_HRX_N4 <5>

PEG_GTX_C_HRX_P5 <5> PEG_GTX_C_HRX_N5 <5>

PEG_GTX_C_HRX_P6 <5> PEG_GTX_C_HRX_N6 <5>

PEG_GTX_C_HRX_P7 <5> PEG_GTX_C_HRX_N7 <5>

PEG_GTX_C_HRX_P8 <5> PEG_GTX_C_HRX_N8 <5>

PEG_GTX_C_HRX_P9 <5> PEG_GTX_C_HRX_N9 <5>

PEG_GTX_C_HRX_P10 <5> PEG_GTX_C_HRX_N10 <5>

PEG_GTX_C_HRX_P11 <5> PEG_GTX_C_HRX_N11 <5>

PEG_GTX_C_HRX_P12 <5> PEG_GTX_C_HRX_N12 <5>

PEG_GTX_C_HRX_P13 <5> PEG_GTX_C_HRX_N13 <5>

PEG_GTX_C_HRX_P14 <5> PEG_GTX_C_HRX_N14 <5>

PEG_GTX_C_HRX_P15 <5> PEG_GTX_C_HRX_N15 <5>

U28G

LVDS CONTROL

TXCLK_UP_DPF3P

TXCLK_UN_DPF3N

TXOUT_U0P_DPF2P TXOUT_U0N_DPF2N

TXOUT_U1P_DPF1P TXOUT_U1N_DPF1N

TXOUT_U2P_DPF0P TXOUT_U2N_DPF0N

TXOUT_U3P

TXOUT_U3N

LVTMDP

TXCLK_LP_DPE3P

TXCLK_LN_DPE3N

TXOUT_L0P_DPE2P

TXOUT_L0N_DPE2N

TXOUT_L1P_DPE1P

TXOUT_L1N_DPE1N

TXOUT_L2P_DPE0P

TXOUT_L2N_DPE0N

TXOUT_L3P TXOUT_L3N

216-0729002 A12 M96_BGA962

216-0729002 A12 M96_BGA962 madison@

madison@

VARY_BL

DIGON

12/22 add for DPST support.

R946

10K_0402_5%~D

1 2

AK27 AJ27

AK35 AL36

AJ38 AK37

AH35 AJ36

AG38 AH37

AF35 AG36

AP34 AR34

AW37 AU35

AR37 AU39

AP35 AR35

AN36 AP37

1 2

LVDS_BCLK+ LVDS_BCLK-

LVDS_B0+ LVDS_B0-

LVDS_B1+ LVDS_B1-

LVDS_B2+ LVDS_B2-

T95@T95 T96@T96

@ @

LVDS_ACLK+ LVDS_ACLK-

LVDS_A0+ LVDS_A0-

LVDS_A1+ LVDS_A1-

LVDS_A2+ LVDS_A2-

@ @

R423

10K_0402_5%~D

T86@T86 T87@T87

VGA_PWM <35> VGA_LVDDEN <35>

LVDS_BCLK+ <35> LVDS_BCLK- <35>

LVDS_B0+ <35> LVDS_B0- <35>

LVDS_B1+ <35> LVDS_B1- <35>

LVDS_B2+ <35> LVDS_B2- <35>

LVDS_ACLK+ <35> LVDS_ACLK- <35>

LVDS_A0+ <35> LVDS_A0- <35>

LVDS_A1+ <35> LVDS_A1- <35>

LVDS_A2+ <35> LVDS_A2- <35>

A A

5

Madison P/N : SA00003M30L (S IC 216-0772000 MADISON PRO FCBGA GPU )

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

2009/06/12 2010/06/12

3

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

1

38 57Monday, September 21, 2009

A

of

38 57Monday, September 21, 2009

5

Strap Name

TX_PWRS_ENB

TX_DEEMPH_EN

BIF_GEN2_EN

STRAP_BIF _CLK_PM_EN

D D

CONFIG[2] CONFIG[1] CONFIG[0]

BIOS_ROM_EN

AUD[1] AUD(0)

CCBYPASS SMS_EN_HARD

VIP_DEVICE _STRAP_DIS

Location VRAM Samsung HYNIX O O O1

C C

+1.8VS

+3VS_DELAY

B B

XTALIN

XTALOUT

A A

SSC_OUT

18P_0402_50V8J~D

MEM_ID0

R430 10K_0402_5%~D

R430 10K_0402_5%~D R432 10K_0402_5%~D@R432 10K_0402_5%~D@ R433 10K_0402_5%~D@R433 10K_0402_5%~D@ R434 10K_0402_5%~D@R434 10K_0402_5%~D@

+1.8VS

10K_0402_5%~D

12

10K_0402_5%~D@R889

10K_0402_5%~D

12

@

R438 10K_0402_5%~D@ R438 10K_0402_5%~D@

1 2

R439 10K_0402_5%~D@ R439 10K_0402_5%~D@

1 2

R440 10K_0402_5%~D@ R440 10K_0402_5%~D@

1 2

R552 10K_0402_5%~D R552 10K_0402_5%~D

1 2

R442 10K_0402_5%~D@ R442 10K_0402_5%~D@

1 2

R443 10K_0402_5%~D@ R443 10K_0402_5%~D@

1 2

R444 10K_0402_5%~DR444 10K_0402_5%~D

1 2

R445 10K_0402_5%~D@ R445 10K_0402_5%~D@

1 2

R446 10K_0402_5%~D@ R446 10K_0402_5%~D@

1 2

R451 10K_0402_5%~D@ R451 10K_0402_5%~D@

1 2

R452 10K_0402_5%~D@ R452 10K_0402_5%~D@

1 2

R1223 22_0402_5%~D R1223 22_0402_5%~D 1 2

SSC_OUT SSC_IN

R1225

@R1225

@

0_0402_5%~D

1 2

R1227

0_0402_5%~D

1 2

C621

Transmitter Power Saving Enable 0: 50% Tx output swing for mobile mode

GPIO0

1: full Tx output swing (Default setting for Desktop) PCI Express Transmitter De-emphasis Enable

GPIO1

0: Tx de-emphasis diabled for mobile mode 1: Tx de-emphasis enabled (Defailt setting for desktop)

0= Advertises the PCI-E device as 2.5 GT/s capable at power-on

GPIO2

5.0 GT/s capability will be controlled by software Enable CLKREQ# Power Management

GPIO22

0: CLKREQ# power management capability is disabled 1: CLKREQ# power management capability is enabled

GPIO13,12,11 (config 2,1,0) :

GPIO13

a) If BIOS_ROM_EN = 1, then Config[2:0] defines

GPIO12

the ROM type.

GPIO11

b) If BIOS_ROM_EN = 0, then Config[2:0] defines the primary memory aperture size.

GPIO22

Enable external BIOS ROM device 0: Diable, 1: Enable

00: No audio function; 10: Audio for DisplayPort only;

HSYNC

01: Audio for DisplayPort and HDMI if adapter is detected;

VSYNC

11: Audio for both DisplayPort and HDMI

GENERICC H2SYNC

If VIP_DEVICE_STRAP_EN is set to ?? then this pin is used to sense

V2SYNC

whether a VIP slave device is connected to the VIP Host interface. If VIP_DEVICE_STRAP_EN is set to ?? then this pin is not used as a strap at all (i.e. its value during reset is unimportant), and it can be used as a regular GPIO

MEM_ID1

O

1 2 1 2 1 2 1 2

R885

R886

10K_0402_5%~D@R886

10K_0402_5%~D

10K_0402_5%~D@R887

10K_0402_5%~D

12

@

10K_0402_5%~D@R891

10K_0402_5%~D

R889

R890

10K_0402_5%~D@R890

10K_0402_5%~D

12

@

ROMSE_GPIO22

U61

1

REFOUT

2

XOUT

3

XIN/CLKIN

ASM3P2872AF-06OR_TSOT-23-6

XTALOUT_R

3

OUT

2

GND

27MHz_16PF_6P27000126

18P_0402_50V8J~D

5

MEM_ID2

R887

10K_0402_5%~D@R888

10K_0402_5%~D

12

@

R891

10K_0402_5%~D@R892

10K_0402_5%~D

12

@

VGA_GPIO0 VGA_GPIO1 VGA_GPIO2

VGA_AC_DET SOUT_GPIO8 SIN_GPIO9 VGA_GPIO11

VGA_GPIO12 VGA_GPIO13

GENERICC

MODOUT

0.01U_0402_16V7K~D

R4651M_0603_5%~OK R4651M_0603_5%~OK

Y4

GND

IN

Pin Straps description

O

MEM_ID0 MEM_ID1 MEM_ID2 MEM_ID3

R888

VRAM_ID0 VRAM_ID1 VRAM_ID2 VRAM_DEC

R892

6

VSS

5 4

VDD

C1123

XTALIN_R

4 1

C622

MEM_ID3

O

+3VS_DELAY

1 2

DDR3

VRAM_DEC 1

Madison

1 2

R457 10K_0402_5%~DR457 10K_0402_5%~D

1 2

R458 10K_0402_5%~D@ R458 10K_0402_5%~D@

1 2

R460 10K_0402_5%~D@ R460 10K_0402_5%~D@

C617

1 2

R1224

33_0402_5%~D

27M_SSC_R

+3VS_DELAY

1

C1124

0.1U_0402_16V4Z~D

2

R1226

@R1226

@

0_0402_5%~D

XTALIN

R1228

0_0402_5%~D

SSC_IN

memory apertures CONFIG[3:0] 128 MB 000 256 MB 001 64 MB 010

CTF

GPU_VID1

100P_0402_50V8J~D

+1.8VS

+1.1VS

+1.8VS

ACIN<17,25,31,48,49>

VGA_THERM#

CLKREQ_GPIO23

10U_0603_6.3V6M~D

BLM18PG121SN1D_0603

4

Default

0

01= Advertises the PCI-E device as 5.0 GT/s capable at power-on

0

001

0

11

0 0

0

+3VS_DELAY

LVDS_DDC_CLK<35> LVDS_DDC_DATA<35>

CH751H-40PT_SOD323-2~D

@ D57

@

VGA_ENBKL<31>

HDMI_HPD<36>

GPU_VID0<54>

DP_HPD<37>

GPU_VID1<54>

R455 499_0402_1%~DR455 499_0402_1%~D

+1.8VS

R456 249_0402_1%R456 249_0402_1%

C613 0.1U_0402_16V4Z~DC613 0.1U_0402_16V4Z~D

L41

BLM18PG121SN1D_0603

12

C614

L42

12

L43

BLM18PG121SN1D_0603

12

10U_0603_6.3V6M~D

1

2

4

VRAM_DEC VRAM_ID0 VRAM_ID1 VRAM_ID2

R428 4.7K_0402_5%~DR428 4.7K_0402_5%~D

1 2

R429 4.7K_0402_5%~DR429 4.7K_0402_5%~D

1 2

LVDS_DDC_CLK LVDS_DDC_DATA

VGA_GPIO0 VGA_GPIO1 VGA_GPIO2

21

VGA_AC_DET

D57

VGA_ENBKL SOUT_GPIO8 SIN_GPIO9

VGA_GPIO11 VGA_GPIO12 VGA_GPIO13 HDMI_HPD GPU_VID0 27M_SSC_R VGA_THERM# DP_HPD

GPU_VID1 BB_EN

T88@T88

ROMSE_GPIO22

@

CLKREQ_GPIO23 T90@T90 T91@T91

@ @

T92@T92 T93@T93

@

T94@T94

@ @

GENERICC

T89@T89

@

1 2 1 2 1 2

DPLL_PVDD

C615

0.1U_0402_16V4Z~D

C615

0.1U_0402_16V4Z~D

C616

1U_0402_6.3V4Z~D

C616

1U_0402_6.3V4Z~D

1

2

10U_0603_6.3V6M~D

1

2

C623

C618

1

2

C619

0.1U_0402_16V4Z~D

C619

0.1U_0402_16V4Z~D

1

2

GPU_THERM_D+ GPU_THERM_D-

TSVDD

C624

1U_0402_6.3V4Z~D

C624

1U_0402_6.3V4Z~D

1

2

C620

1U_0402_6.3V4Z~D

C620

1U_0402_6.3V4Z~D

1

2

C625

0.1U_0402_16V4Z~D

C625

0.1U_0402_16V4Z~D

1

2

MEM_ID0 MEM_ID1 MEM_ID2 MEM_ID3

VGA_VREF

75mA

125mA

DPLL_VDDC

XTALIN XTALOUT

20mA

U28B

MUTI GFX

AR8

DVPCNTL_MVP_0

AU8

DVPCNTL_MVP_1

AP8

DVPCNTL_0

AW8

DVPCNTL_1

AR3

DVPCNTL_2

AR1

DVPCLK

AU1

DVPDATA_0

AU3

DVPDATA_1

AW3

DVPDATA_2

AP6

DVPDATA_3

AW5

DVPDATA_4

AU5

DVPDATA_5

AR6

DVPDATA_6

AW6

DVPDATA_7

AU6

DVPDATA_8

AT7

DVPDATA_9

AV7

DVPDATA_10

AN7

DVPDATA_11

AV9

DVPDATA_12

AT9

DVPDATA_13

AR10

DVPDATA_14

AW10

DVPDATA_15

AU10

DVPDATA_16

AP10

DVPDATA_17

AV11

DVPDATA_18

AT11

DVPDATA_19

AR12

DVPDATA_20

AW12

DVPDATA_21

AU12

DVPDATA_22

AP12

DVPDATA_23

I2C

AK26

SCL

AJ26

SDA

GENERAL PURPOSE I/O

AH20

GPIO_0

AH18

GPIO_1

AN16

GPIO_2

AH23

GPIO_3_SMBDATA

AJ23

GPIO_4_SMBCLK

AH17

GPIO_5_AC_BATT

AJ17

GPIO_6

AK17

GPIO_7_BLON

AJ13

GPIO_8_ROMSO

AH15

GPIO_9_ROMSI

AJ16

GPIO_10_ROMSCK

AK16

GPIO_11

AL16

GPIO_12

AM16

GPIO_13

AM14

GPIO_14_HPD2

AM13

GPIO_15_PWRCNTL_0

AK14

GPIO_16_SSIN

AG30

GPIO_17_THERMAL_INT

AN14

GPIO_18_HPD3

AM17

GPIO_19_CTF

AL13

GPIO_20_PWRCNTL_1

AJ14

GPIO_21_BB_EN

AK13

GPIO_22_ROMCSB

AN13

GPIO_23_CLKREQB

AM23

JTAG_TRSTB

AN23

JTAG_TDI

AK23

JTAG_TCK

AL24

JTAG_TMS

AM24

JTAG_TDO

AJ19

GENERICA

AK19

GENERICB

AJ20

GENERICC

AK20

GENERICD

AJ24

GENERICE_HPD4

AH26

GENERICF

AH24

GENERICG

AK24

HPD1

AH13

VREFG

PLL/CLOCK

AM32

DPLL_PVDD

AN32

DPLL_PVSS

AN31

DPLL_VDDC

AV33

XTALIN

AU34

XTALOUT

AF29

DPLUS

AG29

DMINUS

AK32

TS_FDO

AJ32

TSVDD

AJ33

TSVSS

216-0729002 A12 M96_BGA962

216-0729002 A12 M96_BGA962 madison@

madison@

THERMAL

3

AU24

TXCAP_DPA3P

TXCAM_DPA3N

DPA

TXCBM_DPB3N

DPB

TXCCM_DPC3N

DPC

TXCDM_DPD3N

DPD

DAC1

DAC2

DDC/AUX

DDCCLK_AUX3P

DDCDATA_AUX3N

DDCCLK_AUX4P

DDCDATA_AUX4N

DDCCLK_AUX5P

DDCDATA_AUX5N

NC_DDCCLK_AUX7P

NC_DDCDATA_AUX7N

3

AV23 AT25

TX0P_DPA2P

AR24

TX0M_DPA2N

AU26

TX1P_DPA1P

AV25

TX1M_DPA1N

AT27

TX2P_DPA0P

AR26

TX2M_DPA0N

AR30

TXCBP_DPB3P

AT29 AV31

TX3P_DPB2P

AU30

TX3M_DPB2N

AR32

TX4P_DPB1P

AT31

TX4M_DPB1N

AT33

TX5P_DPB0P

AU32

TX5M_DPB0N

AU14

TXCCP_DPC3P

AV13 AT15

TX0P_DPC2P

AR14

TX0M_DPC2N

AU16

TX1P_DPC1P

AV15

TX1M_DPC1N

AT17

TX2P_DPC0P

AR16

TX2M_DPC0N

AU20

TXCDP_DPD3P

AT19 AT21

TX3P_DPD2P

AR20

TX3M_DPD2N

AU22

TX4P_DPD1P

AV21

TX4M_DPD1N

AT23

TX5P_DPD0P

AR22

TX5M_DPD0N

AD39

R

AD37

RB

AE36

G

AD35

GB

AF37

B

AE38

BB

AC36

HSYNC

AC38

VSYNC

AB34

RSET

AD34

AVDD

AE34

AVSSQ

AC33

VDD1DI

AC34

VSS1DI

AC30

R2

AC31

R2B

AD30

G2

AD31

G2B

AF30

B2

AF31

B2B

AC32

C

AD32

Y

AF32

COMP

AD29

H2SYNC

AC29

V2SYNC

AG31

VDD2DI

AG32

VSS2DI

AG33

A2VDD

AD33

A2VDDQ

AF33

A2VSSQ

AA29

R2SET

AM26

DDC1CLK

AN26

DDC1DATA

AM27

AUX1P

AL27

AUX1N

AM19

DDC2CLK

AL19

DDC2DATA

AN20

AUX2P

AM20

AUX2N

AL30 AM30

AL29 AM29

AN21 AM21

AJ30

DDC6CLK

AJ31

DDC6DATA

AK30 AK29

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HDMI_A3P_VGA <36> HDMI_A3N_VGA <36>

HDMI_A2P_VGA <36> HDMI_A2N_VGA <36>

HDMI_A1P_VGA <36> HDMI_A1N_VGA <36>

HDMI_A0P_VGA <36> HDMI_A0N_VGA <36>

DISP_A3P_VGA <37> DISP_A3N_VGA <37>

DISP_A2P_VGA <37> DISP_A2N_VGA <37>

DISP_A1P_VGA <37> DISP_A1N_VGA <37>

DISP_A0P_VGA <37> DISP_A0N_VGA <37>

VGA_CRT_R <35>

VGA_CRT_G <35>

VGA_CRT_B <35>

CRT_HSYNC <35> CRT_VSYNC <35>

R441 499_0402_1%~DR441 499_0402_1%~D

1 2

70mA

+AVDD

+VDD1DI

H2SYNC V2SYNC

VDD2DI

A2VDD +A2VDDQ

R459

715_0402_1%

1 2

CRT_DDC_CLK CRT_DDC_DATA

CRT

HDMI_DDC_CLK HDMI_DDC_DATA

HDMI

45mA

50mA

130mA

1

2

1

2

0_0603_5%~D

CRT_DDC_CLK <35> CRT_DDC_DATA <35>

HDMI_DDC_CLK <36> HDMI_DDC_DATA <36>

M96 only

DP_DDC_CLK DP_DDC_DATA

DP_DDC_CLK <37> DP_DDC_DATA <37>

2009/06/12 2010/06/12

R02 : Add

C607

1U_0402_6.3V4Z~D

C607

1U_0402_6.3V4Z~D

1

2

C610

1U_0402_6.3V4Z~D

C610

1U_0402_6.3V4Z~D

1

2

R984

R985

0_0603_5%~D

1U_0402_6.3V4Z~D

1

2

Compal Secret Data

0.1U_0402_16V4Z~D

C881

C608

1

2

C611

1

2

+1.8VS

+3VS_DELAY

1

2

L36

L36 BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

C609

10U_0603_6.3V6M~D

C609

10U_0603_6.3V6M~D

L37

L37 BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

C612

10U_0603_6.3V6M~D

C612

10U_0603_6.3V6M~D

C882

0.1U_0402_16V4Z~D

C882

0.1U_0402_16V4Z~D

C883

10U_0603_6.3V6M~D

C883

10U_0603_6.3V6M~D

1

2

Deciphered Date

2

C867

0.1U_0402_16V4Z~D

GPU_THERM_D+

2200P_0402_50V7K~D

1 2

C868

GPU_THERM_D-

R976

1 2

+3VS

10K_0402_5%~D

VGA_THERM_STP#

12

+1.8VS

12

+1.8VS

L63

L63 BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

12

+1.8VS

External VGA Thermal Sensor

+3VS

2

U38

1

1 2 3 4

VGA_THERM_STP#

VR_ON<31,55>

VDD D+ DTHERM#

ADM1032ARMZ-1REEL7_MSOP8

SCLK

SDATA

ALERT#

GND

D

S

D

S

13

G

Q72

2

2N7002W-7-F_SOT323-3~D

8 7 6 5

R1244

0_0402_5%

1 2

+3VS_DELAY

100K_0402_5%~D

R431

R431 100K_0402_5%~D@

100K_0402_5%~D@

1.1VS_RUN_PWRGD<54>

1 2

0.1U_0402_16V4Z~D

C606

@

PWR Sequence

V2SYNC H2SYNC

CRT_VSYNC CRT_HSYNC

HDMI_DDC_CLK HDMI_DDC_DATA

VGA_CRT_R VGA_CRT_G VGA_CRT_B

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

1

EC_SMB_CK2 EC_SMB_DA2

R119 0_0603_5%~DR119 0_0603_5%~D

1 2

SI2301BDS_SOT23 @

R427

@

1 2

2

G

1

2

R449 10K_0402_5%~D@ R449 10K_0402_5%~D@

1 2

R450 10K_0402_5%~D@ R450 10K_0402_5%~D@

1 2

R447 10K_0402_5%~DR447 10K_0402_5%~D

1 2

R448 10K_0402_5%~DR448 10K_0402_5%~D

1 2

R463 10K_0402_5%~D@ R463 10K_0402_5%~D@

1 2

R464 10K_0402_5%~D@ R464 10K_0402_5%~D@

1 2

R553 150_0402_1%~DR553 150_0402_1%~D

1 2

R554 150_0402_1%~DR554 150_0402_1%~D

1 2

R555 150_0402_1%~DR555 150_0402_1%~D

1 2

MAINPWON <20,50,56>

10K_0402_5%~D

1 2

R1576

Q34

S

G

2

13

D

Q35

Q35 PMF3800SN_SC70-3

PMF3800SN_SC70-3

S

1

EC_SMB_CK2 <16,27,28,31> EC_SMB_DA2 <16,27,28,31>

100mA

D

13

@

+3VS_DELAY VGA_CORE (VDDC) +1.8VS

+3VS_DELAY+3VS

+3VS_DELAY

39 57Monday, September 21, 2009

of

A

5

U28C

12 R1254

R1254

243_0402_1%~OK

madison@

243_0402_1%~OK

madison@

MDA[0..63]

12 R1255

R1255

243_0402_1%~OK

madison@

243_0402_1%~OK

madison@

12 R1256

R1256

243_0402_1%~OK

madison@

243_0402_1%~OK

madison@

12 R1257

R1257

243_0402_1%~OK

madison@

243_0402_1%~OK

madison@

MDA0 MDA1 MDA2 MDA3 MDA4 MDA5 MDA6 MDA7 MDA8 MDA9 MDA10 MDA11 MDA12 MDA13 MDA14 MDA15 MDA16 MDA17 MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63

MVREFDA MVREFSA

12 R1258

R1258

243_0402_1%~OK

madison@

243_0402_1%~OK

madison@

C37

DQA_0

C35

DQA_1

A35

DQA_2

E34

DQA_3

G32

DQA_4

D33

DQA_5

F32

DQA_6

E32

DQA_7

D31

DQA_8

F30

DQA_9

C30

DQA_10

A30

DQA_11

F28

DQA_12

C28

DQA_13

A28

DQA_14

E28

DQA_15

D27

DQA_16

F26

DQA_17

C26

DQA_18

A26

DQA_19

F24

DQA_20

C24

DQA_21

A24

DQA_22

E24

DQA_23

C22

DQA_24

A22

DQA_25

F22

DQA_26

D21

DQA_27

A20

DQA_28

F20

DQA_29

D19

DQA_30

E18

DQA_31

C18

DQA_32

A18

DQA_33

F18

DQA_34

D17

DQA_35

A16

DQA_36

F16

DQA_37

D15

DQA_38

E14

DQA_39

F14

DQA_40

D13

DQA_41

F12

DQA_42

A12

DQA_43

D11

DQA_44

F10

DQA_45

A10

DQA_46

C10

DQA_47

G13

DQA_48

H13

DQA_49

J13

DQA_50

H11

DQA_51

G10

DQA_52

G8

DQA_53

K9

DQA_54

K10

DQA_55

G9

DQA_56

A8

DQA_57

C8

DQA_58

E8

DQA_59

A6

DQA_60

C6

DQA_61

E6

DQA_62

A5

DQA_63

L18

MVREFDA

L20

MVREFSA

L27

NC_MEM_CALRN0

N12

NC_MEM_CALRN1

AG12

NC_MEM_CALRN2

M12

MEM_CALRP1

M27

NC_MEM_CALRP0

AH12

NC_MEM_CALRP2

216-0729002 A12 M96_BGA962

216-0729002 A12 M96_BGA962 madison@

madison@

D D

100_0402_1%~D

C C

100_0402_1%~D

B B

MDA[0..63]<43> MDB[0..63]<44>

+1.5VS

R3

40.2_0402_1%~D

MVREFDA

12

1

R469

R478

C626

0.1U_0402_16V4Z~D

2

+1.5VS

R4

40.2_0402_1%~D

MVREFSA QSB#7

12

1

C629

0.1U_0402_16V4Z~D

2

+1.5VS

12 R1253

R1253

243_0402_1%~OK

madison@

243_0402_1%~OK

madison@

Madison

4

MAA0

G24

MAA_0 MAA_1 MAA_2 MAA_3 MAA_4 MAA_5 MAA_6 MAA_7 MAA_8

MAA_9 MAA_10 MAA_11 MAA_12

MAA_13/BA2 MAA_14/BA0 MAA_15/BA1

DQMA_0 DQMA_1 DQMA_2 DQMA_3 DQMA_4 DQMA_5 DQMA_6

MEMORY INTERFACE A

DQMA_7

QSA_0/RDQSA_0 QSA_1/RDQSA_1 QSA_2/RDQSA_2 QSA_3/RDQSA_3 QSA_4/RDQSA_4 QSA_5/RDQSA_5 QSA_6/RDQSA_6 QSA_7/RDQSA_7

QSA_0B/WDQSA_0 QSA_1B/WDQSA_1 QSA_2B/WDQSA_2 QSA_3B/WDQSA_3 QSA_4B/WDQSA_4 QSA_5B/WDQSA_5 QSA_6B/WDQSA_6 QSA_7B/WDQSA_7

ODTA0 ODTA1

CLKA0 CLKA0B

CLKA1 CLKA1B

RASA0B RASA1B

CASA0B CASA1B

CSA0B_0 CSA0B_1

CSA1B_0 CSA1B_1

CKEA0

CKEA1

WEA0B WEA1B

RSVD#1 RSVD#2 RSVD#3

RSVD#5 RSVD#6

RSVD#9

RSVD#11

MAA1

J23

MAA2

H24

MAA3

J24

MAA4

H26

MAA5

J26

MAA6

H21

MAA7

G21 H19 H20 L13

MAA11 MAB11

G16

MAA12

J16

A_BA2

H16

A_BA0

J17

A_BA1

H17

DQMA#0

A32

DQMA#1

C32

DQMA#2

D23

DQMA#3

E22

DQMA#4

C14

DQMA#5

A14

DQMA#6

E10

DQMA#7

D9

QSA0

C34

QSA1

D29

QSA2

D25

QSA3

E20

QSA4

E16

QSA5

E12

QSA6

J10

QSA7

D7

QSA#0

A34

QSA#1

E30

QSA#2

E26

QSA#3

C20

QSA#4

C16

QSA#5

C12

QSA#6

J11

QSA#7

F8

ODTA0

J21

ODTA1

G19

CLKA0

H27

CLKA0#

G27

CLKA1

J14

CLKA1#

H14

RASA0#

K23

RASA1#

K19

CASA0#

K20

CASA1#

K17

CSA0#_0

K24 K27

CSA1#_0

M13 K16

CKEA0

K21

CKEA1

J20

WEA0#

K26

WEA1#

L15 AF28

AG28 AL31

H23 J19

T8 W8

reserve 128Mx16 DDR3 for next generation of M96

MAA[0..12]

A_BA[0..2]

DQMA#[0..7]

QSA[0..7]

QSA#[0..7]

ODTA0 <43> ODTA1 <43>

CLKA0 <43> CLKA0# <43>

CLKA1 <43> CLKA1# <43>

RASA0# <43> RASA1# <43>

CASA0# <43> CASA1# <43>

CSA0#_0 <43>

CSA1#_0 <43>

CKEA0 <43> CKEA1 <43>

WEA0# <43> WEA1# <43>

MAB13 <44>

MAA[0..12] <43>

A_BA[0..2] <43>

DQMA#[0..7] <43>

QSA[0..7] <43>

QSA#[0..7] <43>

+1.5VS

R470

100_0402_1%~D

+1.5VS

R479

100_0402_1%~D

3

R5

40.2_0402_1%~D

MVREFDB

12

1

C627

0.1U_0402_16V4Z~D

2

R2

40.2_0402_1%~D

MVREFSB

12

1

C630

0.1U_0402_16V4Z~D

2

MDB[0..63]

1K_0402_5%~D

1 2

C1187

0.1U_0402_16V7K~D

C1187

R476

51_0402_1%~D

R471

1

2

1 2

MDB0 MDB1 MDB2 MDB3 MDB4 MDB5 MDB6 MDB7 MDB8 MDB9 MDB10 MDB11 MDB12 MDB13 MDB14 MDB15 MDB16 MDB17 MDB18 MDB19 MDB20 MDB21 MDB22 MDB23 MDB24 MDB25 MDB26 MDB27 MDB28 MDB29 MDB30 MDB31 MDB32 MDB33 MDB34 MDB35 MDB36 MDB37 MDB38 MDB39 MDB40 MDB41 MDB42 MDB43 MDB44 MDB45 MDB46 MDB47 MDB48 MDB49 MDB50 MDB51 MDB52 MDB53 MDB54 MDB55 MDB56 MDB57 MDB58 MDB59 MDB60 MDB61 MDB62 MDB63

MVREFDB MVREFSB

TESTEN TEST_MCLK

TEST_YCLK

1

C1188

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D 2

R473

R473 51_0402_1%~D

51_0402_1%~D

1 2

AMD update 06/05

2

U28D

C5

DQB_0

C3

DQB_1

E3

DQB_2

E1

DQB_3

F1

DQB_4

F3

DQB_5

F5

DQB_6

G4

DQB_7

H5

DQB_8

H6

DQB_9

J4

DQB_10

K6

DQB_11

K5

DQB_12

L4

DQB_13

M6

DQB_14

M1

DQB_15

M3

DQB_16

M5

DQB_17

N4

DQB_18

P6

DQB_19

P5

DQB_20

R4

DQB_21

T6

DQB_22

T1

DQB_23

U4

DQB_24

V6

DQB_25

V1

DQB_26

V3

DQB_27

Y6

DQB_28

Y1

DQB_29

Y3

DQB_30

Y5

DQB_31

AA4

DQB_32

AB6

DQB_33

AB1

DQB_34

AB3

DQB_35

AD6

DQB_36

AD1

DQB_37

AD3

DQB_38

AD5

DQB_39

AF1

DQB_40

AF3

DQB_41

AF6

DQB_42

AG4

DQB_43

AH5

DQB_44

AH6

DQB_45

AJ4

DQB_46

AK3

DQB_47

AF8

DQB_48

AF9

DQB_49

AG8

DQB_50

AG7

DQB_51

AK9

DQB_52

AL7

DQB_53

AM8

DQB_54

AM7

DQB_55

AK1

DQB_56

AL4

DQB_57

AM6

DQB_58

AM1

DQB_59

AN4

DQB_60

AP3

DQB_61

AP1

DQB_62

AP5

DQB_63

Y12

MVREFDB

AA12

MVREFSB

AD28

TESTEN

AK10

CLKTESTA

AL10

CLKTESTB

216-0729002 A12 M96_BGA962

216-0729002 A12 M96_BGA962 madison@

madison@

MAB_0 MAB_1 MAB_2 MAB_3 MAB_4 MAB_5 MAB_6 MAB_7 MAB_8

MAB_9 MAB_10 MAB_11 MAB_12

MAB_13/BA2 MAB_14/BA0 MAB_15/BA1

DQMB_0 DQMB_1 DQMB_2 DQMB_3 DQMB_4 DQMB_5 DQMB_6

MEMORY INTERFACE B

DQMB_7

QSB_0/RDQSB_0 QSB_1/RDQSB_1 QSB_2/RDQSB_2 QSB_3/RDQSB_3 QSB_4/RDQSB_4 QSB_5/RDQSB_5 QSB_6/RDQSB_6 QSB_7/RDQSB_7

QSB_0B/WDQSB_0 QSB_1B/WDQSB_1 QSB_2B/WDQSB_2 QSB_3B/WDQSB_3 QSB_4B/WDQSB_4 QSB_5B/WDQSB_5 QSB_6B/WDQSB_6 QSB_7B/WDQSB_7

ODTB0 ODTB1

CLKB0 CLKB0B

CLKB1 CLKB1B

RASB0B RASB1B

CASB0B CASB1B

CSB0B_0 CSB0B_1

CSB1B_0 CSB1B_1

CKEB0

CKEB1

WEB0B WEB1B

DRAM_RST

2200P_0402_50V7K~D

T9 P9 N7 N8 N9 U9 U8 Y9 W9 AC8 AC9 AA7 AA8 Y8 AA9

H3 H1 T3 T5 AE4 AF5 AK6 AK5

F6 K3 P3 V5 AB5 AH1 AJ9 AM5

G7 K1 P1 W4 AC4 AH3 AJ8 AM3

T7 W7

L9 L8

AD8 AD7

T10 Y10

W10 AA10

P10 L10

AD10 AC10

U10 AA11

N10 AB11

AH11

C628

1

2

MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8MAA8 MAB9MAA9 MAB10MAA10

MAB12 B_BA2 B_BA0 B_BA1

DQMB#0 DQMB#1 DQMB#2 DQMB#3 DQMB#4 DQMB#5 DQMB#6 DQMB#7

QSB0 QSB1 QSB2 QSB3 QSB4 QSB5 QSB6 QSB7

QSB#0 QSB#1 QSB#2 QSB#3 QSB#4 QSB#5 QSB#6

ODTB0 ODTB1

CLKB0 CLKB0#

CLKB1 CLKB1#

RASB0# RASB1#

CASB0# CASB1#

CSB0#_0

CSB1#_0

CKEB0 CKEB1

WEB0# WEB1#

R472

4.7K_0402_5%~D

1 2

12

R477

4.7K_0402_5%~D

4.7K_0402_5%~D @

@

MAB0

P8

ref134-0 schematic suggested

ref1347-04 schematic suggested

MAB[0..12]

B_BA[0..2]

DQMB#[0..7]

QSB[0..7]

QSB#[0..7]

ODTB0 <44> ODTB1 <44>

CLKB0 <44> CLKB0# <44>

CLKB1 <44> CLKB1# <44>

RASB0# <44> RASB1# <44>

CASB0# <44> CASB1# <44>

CSB0#_0 <44>

CSB1#_0 <44>

CKEB0 <44> CKEB1 <44>

WEB0# <44> WEB1# <44>

1

MAB[0..12] <44>

B_BA[0..2] <44>

DQMB#[0..7] <44>

QSB[0..7] <44>

QSB#[0..7] <44>

+1.5VS

VRAM_RST# <43,44>MAA13 <43>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/06/12 2010/06/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

1

40 57Monday, September 21, 2009

A

of

40 57Monday, September 21, 2009

5

For DDR3 , MVDDQ=1.5V

+1.5VS

D D

C668

10U_0805_6.3V6M~D

C668

10U_0805_6.3V6M~D

1

2

+1.8VS

BLM18PG121SN1D_0603

+3VS_DELAY

C C

+1.8VS

madison@

12

L89

L89 BLM18PG121SN1D_0603

BLM18PG121SN1D_0603 madison@

madison@

C1152

10U_0603_6.3V6M~D

C1152

10U_0603_6.3V6M~D

C1153

0.1U_0402_16V4Z~D

C1153

0.1U_0402_16V4Z~D

2

1

+1.8VS

12

L91

L91 BLM18PG121SN1D_0603

BLM18PG121SN1D_0603 madison@

madison@

0.1U_0402_16V4Z~D

C1164

10U_0603_6.3V6M~D

C1164

10U_0603_6.3V6M~D

2

1

1U_0402_6.3V4Z~D

2

1

C1165

2

1

madison@

C1154

madison@

C1166

1U_0402_6.3V4Z~D

C1166

1U_0402_6.3V4Z~D

+SPV18

Madison

0.1U_0402_16V4Z~D

2

1

C1167

+1.8VS

+1.1VS

+GPU_CORE

C1168

1U_0402_6.3V4Z~D

C1168

1U_0402_6.3V4Z~D

2

madison@

1

BLM18PG121SN1D_0603

+MPV18

B B

A A

Madison

5

C751

0.1U_0402_16V4Z~D

C751

0.1U_0402_16V4Z~D

C752

0.1U_0402_16V4Z~D

C752

0.1U_0402_16V4Z~D

1

2

1U_0402_6.3V4Z~D

1

2

10U_0805_6.3V6M~D

1

2

1

2

C646

1U_0402_6.3V4Z~D

C646

1U_0402_6.3V4Z~D

C645

1

2

C659

C669

10U_0805_6.3V6M~D

C669

10U_0805_6.3V6M~D

1

2

12

L45

BLM18PG121SN1D_0603

L50

BLM18PG121SN1D_0603

Madison

L90

madison@L90

madison@

BLM18PG121SN1D_0603

12

L55

only-M96@L55

only-M96@

12

VGA_GPIO21= 0V FOR BACK BIASING DISABLED N FET A = OFF, P FET B = OFF, N FET C = ON +BBP = +VGA_CORE

VGA_GPIO21= +3.3V FOR BACK BIASING ENABLED N FET A = ON, P FET B = ON, N FET C = OFF +BBP = +1.8VS

0.1U_0402_16V4Z~D

1U_0402_6.3V4Z~D

10U_0805_6.3V6M~D

L46

L47

C750

C647

C660

4

U28E

C729

0.1U_0402_16V4Z~D

C729

0.1U_0402_16V4Z~D

C730

0.1U_0402_16V4Z~D

C730

0.1U_0402_16V4Z~D 1

1

2

C649

1U_0402_6.3V4Z~D

C649

1U_0402_6.3V4Z~D

C648

1U_0402_6.3V4Z~D

C648

1U_0402_6.3V4Z~D

1

2

C670

10U_0805_6.3V6M~D

C670

10U_0805_6.3V6M~D

C661

1U_0402_6.3V4Z~D

C661

1U_0402_6.3V4Z~D

1

2

C888

1U_0402_6.3V4Z~D

C888

1U_0402_6.3V4Z~D

C673

10U_0805_6.3V6M~D

C673

10U_0805_6.3V6M~D

1

2

12

C686

10U_0805_6.3V6M~D

C686

10U_0805_6.3V6M~D

1

2

12

C723

10U_0603_6.3V6M~D

C723

10U_0603_6.3V6M~D

2

1

C734

10U_0603_6.3V6M~D

C734

10U_0603_6.3V6M~D

C735

0.1U_0402_16V4Z~D

C735

0.1U_0402_16V4Z~D

2

1

4

C727

0.1U_0402_16V4Z~D

C727

0.1U_0402_16V4Z~D

C728

0.1U_0402_16V4Z~D

C728

0.1U_0402_16V4Z~D

1

2

C650

1U_0402_6.3V4Z~D

C650

1U_0402_6.3V4Z~D

1

2

C671

1U_0402_6.3V4Z~D

C671

1U_0402_6.3V4Z~D

1

2

C887

1U_0402_6.3V4Z~D

C887

1U_0402_6.3V4Z~D

1

2

1U_0402_6.3V4Z~D

C889

1

2

C700

1U_0402_6.3V4Z~D

C700

1U_0402_6.3V4Z~D

1

2

C724

0.1U_0402_16V4Z~D

C724

0.1U_0402_16V4Z~D

2

1

C736

1U_0402_6.3V4Z~D

C736

1U_0402_6.3V4Z~D

2

1

2

0.1U_0402_16V4Z~D

1

2

1U_0402_6.3V4Z~D

1

2

1U_0402_6.3V4Z~D

1

2

1U_0402_6.3V4Z~D

1

2

0.1U_0402_16V4Z~D

1

2

1U_0402_6.3V4Z~D

2

1

0.1U_0402_16V4Z~D

1

2

0.1U_0402_16V4Z~D

C886

1

2

1U_0402_6.3V4Z~D

C672

1

2

C674

0.1U_0402_16V4Z~D

1

2

1U_0402_6.3V4Z~D

C687

1

2

C701

+VDDR4_5

C725

+PCIE_PVDD

+MPV18

+SPV18

+GPU_CORE

C726

C864

C662

C675

C688

+SPV10

0_0603_5%~D

R1573

+VDD_CT

+VDDR3

40mA 150mA

50mA

100mA

12

4000mA

AD11 AG10

17mA

AF26 AF27 AG26 AG27

60mA

AF23 AF24 AG23 AG24

AF13 AF15 AG13 AG15

AD12 AF11 AF12 AG11

AB37

AM10

AN10

AA13

1U_0402_6.3V4Z~D

1

2

AC7 AF7

AK8 AL9 G11 G14 G17 G20 G23 G26 G29 H10

K11 K13

M11 N11

R11 U11

Y11

M20 M21

V12 U12

AN9

Y13

C737

AJ7

J7 J9

K8 L12 L16 L21 L23 L26

L7

P7

U7

Y7

H7

H8

U28E

VDDR1#1 VDDR1#2 VDDR1#3 VDDR1#4 VDDR1#5 VDDR1#6 VDDR1#7 VDDR1#8 VDDR1#9 VDDR1#10 VDDR1#11 VDDR1#12 VDDR1#13 VDDR1#14 VDDR1#15 VDDR1#16 VDDR1#17 VDDR1#18 VDDR1#19 VDDR1#20 VDDR1#21 VDDR1#22 VDDR1#23 VDDR1#24 VDDR1#25 VDDR1#26 VDDR1#27 VDDR1#28 VDDR1#29 VDDR1#30 VDDR1#31 VDDR1#32 VDDR1#33 VDDR1#34

LEVEL

LEVEL TRANSLATION

TRANSLATION

VDD_CT#1 VDD_CT#2 VDD_CT#3 VDD_CT#4

VDDR3#1 VDDR3#2 VDDR3#3 VDDR3#4

VDDR5#1 VDDR5#2 VDDR5#3 VDDR5#4

VDDR4#1 VDDR4#2 VDDR4#3 VDDR4#4

MEM CLK

VDDRHA VSSRHA

VDDRHB VSSRHB

PCIE_PVDD NC_MPV18#1

NC_MPV18#2

NC_SPV18 SPV10 SPVSS

BACK BIAS

BBP#1 BBP#2

216-0729002 A12 M96_BGA962

216-0729002 A12 M96_BGA962 madison@

madison@

3

MEM I/O

I/O

PLL

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

PCIE

PCIE_VDDR#1 PCIE_VDDR#2 PCIE_VDDR#3 PCIE_VDDR#4 PCIE_VDDR#5 PCIE_VDDR#6 PCIE_VDDR#7 PCIE_VDDR#8

PCIE_VDDC#1 PCIE_VDDC#2 PCIE_VDDC#3 PCIE_VDDC#4 PCIE_VDDC#5 PCIE_VDDC#6 PCIE_VDDC#7 PCIE_VDDC#8

PCIE_VDDC#9 PCIE_VDDC#10 PCIE_VDDC#11 PCIE_VDDC#12

VDDC#1

CORE

VDDC#2 VDDC#3 VDDC#4 VDDC#5 VDDC#6 VDDC#7 VDDC#8

VDDC#9 VDDC#10 VDDC#11 VDDC#12 VDDC#13 VDDC#14 VDDC#15

POWER

VDDC#16 VDDC#17 VDDC#18 VDDC#19 VDDC#20 VDDC#21 VDDC#22 VDDC#23 VDDC#24 VDDC#25 VDDC#26 VDDC#27 VDDC#28 VDDC#29 VDDC#30 VDDC#31 VDDC#32 VDDC#33 VDDC#34 VDDC#35 VDDC#36 VDDC#37 VDDC#38 VDDC#39 VDDC#40 VDDC#41 VDDC#42 VDDC#43 VDDC#44 VDDC#45 VDDC#46 VDDC#47 VDDC#48 VDDC#49 VDDC#50 VDDC#51 VDDC#52 VDDC#53 VDDC#54 VDDC#55 VDDC#56 VDDC#57 VDDC#58 VDDC#59 VDDC#60 VDDC#61 VDDC#62 VDDC#63 VDDC#64 VDDC#65 VDDC#66 VDDC#67 VDDC#68 VDDC#69 VDDC#70 VDDC#71 VDDC#72 VDDC#73 VDDC#74

VDDCI#1

ISOLATED

VDDCI#2

CORE I/O

VDDCI#3

VDDCI#4

2009/06/12 2010/06/12

500mA

AA31 AA32 AA33 AA34 V28 W29 W30 Y31

2000mA

G30 G31 H29 H30 J29 J30 L28 M28 N28 R28 T28 U28

AA15 AA17 AA20 AA22 AA24 AA27 AB13 AB16 AB18 AB21 AB23 AB26 AB28 AC12 AC15 AC17 AC20 AC22 AC24 AC27 AD13 AD16 AD18 AD21 AD23 AD26 AF17 AF20 AF22 AG16 AG18 AG21 AH22 M16 M18 M23 M26 N15 N17 N20 N22 N24 N27 R13 R16 R18 R21 R23 R26 T15 T17 T20 T22 T24 T27 U16 U18 U21 U23 U26 V15 V17 V20 V22 V24 V27 Y16 Y18 Y21 Y23 Y26 Y28 AH27 AH28

+VDDC1

M15 N13 R12 T12

Compal Secret Data

+PCIE_VDDR

10U_0805_6.3V6M~D

1

2

2000mA

1

2

Deciphered Date

C714

1U_0402_6.3V4Z~D

0.1U_0402_16V4Z~D

1

2

1U_0402_6.3V4Z~D

1

2

1U_0402_6.3V4Z~D

1

2

1U_0402_6.3V4Z~D

1

2

1U_0402_6.3V4Z~D

1

2

1

2

1

2

C731

2

C638

0.1U_0402_16V4Z~D

C638

0.1U_0402_16V4Z~D

C637

1

2

C654

1U_0402_6.3V4Z~D

C654

1U_0402_6.3V4Z~D

C665

1

2

C677

1U_0402_6.3V4Z~D

C677

1U_0402_6.3V4Z~D

C676

1

2

C689

C690

1U_0402_6.3V4Z~D

C690

1U_0402_6.3V4Z~D

1

2

C703

1U_0402_6.3V4Z~D

C703

1U_0402_6.3V4Z~D

C702

1

2

C1133

1U_0402_6.3V4Z~D

C1133

1U_0402_6.3V4Z~D

1

2

10U_0805_6.3V6M~D

C715

10U_0805_6.3V6M~D

C715

10U_0805_6.3V6M~D

1

2

VDDCI and VDDC should have seperate regulators with a merge option on PCB For Madison, VDDCI and VDDC can share one common regulator

C732

10U_0805_6.3V6M~D

C732

10U_0805_6.3V6M~D

1

2

1

2

C1134

C716

1

2

1U_0402_6.3V4Z~D

1

2

1

2

1

2

10U_0805_6.3V6M~D

C655

C733

1U_0402_6.3V4Z~D

1

2

1

2

C639

1U_0402_6.3V4Z~D

C639

1U_0402_6.3V4Z~D

C640

1U_0402_6.3V4Z~D

C640

1U_0402_6.3V4Z~D

1

2

C656

1U_0402_6.3V4Z~D

C656

1U_0402_6.3V4Z~D

C666

1U_0402_6.3V4Z~D

C666

1U_0402_6.3V4Z~D

1

2

C679

1U_0402_6.3V4Z~D

C679

1U_0402_6.3V4Z~D

C678

1

2

C692

1U_0402_6.3V4Z~D

C692

1U_0402_6.3V4Z~D

C691

1

2

C704

C705

1U_0402_6.3V4Z~D

C705

1U_0402_6.3V4Z~D

1

2

C1135

1U_0402_6.3V4Z~D

C1135

1U_0402_6.3V4Z~D

C1136

1U_0402_6.3V4Z~D

C1136

1U_0402_6.3V4Z~D

1

2

C717

10U_0805_6.3V6M~D

C717

10U_0805_6.3V6M~D

C718

10U_0805_6.3V6M~D

C718

10U_0805_6.3V6M~D

1

2

L54

BLM18PG121SN1D_0603

10U_0805_6.3V6M~D

C890

1

2

1

L44

BLM18PG121SN1D_0603

C641

1U_0402_6.3V4Z~D

C641

1U_0402_6.3V4Z~D

1

2

1

2

10U_0805_6.3V6M~D

C644

12

+1.8VS

PCIE_VDDC

C657

1U_0402_6.3V4Z~D

C657

1U_0402_6.3V4Z~D

1

2

C680

1U_0402_6.3V4Z~D

C680

1U_0402_6.3V4Z~D

1

2

C693

1U_0402_6.3V4Z~D

C693

1U_0402_6.3V4Z~D

1

2

C706

1U_0402_6.3V4Z~D

C706

1U_0402_6.3V4Z~D

1

2

C1137

1U_0402_6.3V4Z~D

C1137

1U_0402_6.3V4Z~D

1

2

C719

10U_0805_6.3V6M~D

C719

10U_0805_6.3V6M~D

1

2

12

C667

10U_0805_6.3V6M~D

C667

10U_0805_6.3V6M~D

C658

1U_0402_6.3V4Z~D

C658

1U_0402_6.3V4Z~D

1

2

C681

1U_0402_6.3V4Z~D

C681

1U_0402_6.3V4Z~D

C682

1U_0402_6.3V4Z~D

C682

1U_0402_6.3V4Z~D

1

2

C694

1U_0402_6.3V4Z~D

C694

1U_0402_6.3V4Z~D

C695

1U_0402_6.3V4Z~D

C695

1U_0402_6.3V4Z~D

1

2

C707

1U_0402_6.3V4Z~D

C707

1U_0402_6.3V4Z~D

C708

1U_0402_6.3V4Z~D

C708

1U_0402_6.3V4Z~D

1

2

C1138

1U_0402_6.3V4Z~D

C1138

1U_0402_6.3V4Z~D

1

2

22U_0805_6.3V6M~OK

C720

10U_0805_6.3V6M~D

C720

10U_0805_6.3V6M~D

1

2

+GPU_CORE

Title

Size Document Number Rev

Custom

401808

Date: Sheet

+1.1VS

C683

1U_0402_6.3V4Z~D

C683

1U_0402_6.3V4Z~D

C684

1U_0402_6.3V4Z~D

C684

1U_0402_6.3V4Z~D

1

2

C697

1U_0402_6.3V4Z~D

C697

1U_0402_6.3V4Z~D

C696

1U_0402_6.3V4Z~D

C696

1U_0402_6.3V4Z~D

1

2

C709

1U_0402_6.3V4Z~D

C709

1U_0402_6.3V4Z~D

1

2

1U_0402_6.3V4Z~D

C1139

1

2

10U_0805_6.3V6M~D

C61

1

2

Compal Electronics, Inc.

1

2

C710

1U_0402_6.3V4Z~D

C710

1U_0402_6.3V4Z~D

1

2

C1140

10U_0805_6.3V6M~D

C892

C891

1

@

2

SCHEMATICS, MB A5155

1

1U_0402_6.3V4Z~D

C685

C698

C711

R02 add

of

41 57Monday, September 21, 2009

+GPU_CORE

A

5

U28F

AB39

PCIE_VSS#1

E39

PCIE_VSS#2

F34

PCIE_VSS#3

F39

PCIE_VSS#4

G33

PCIE_VSS#5

G34

PCIE_VSS#6

H31

PCIE_VSS#7

H34

PCIE_VSS#8

H39

PCIE_VSS#9

J31

PCIE_VSS#10

J34

D D

C C

B B

A A

PCIE_VSS#11

K31

PCIE_VSS#12

K34

PCIE_VSS#13

K39

PCIE_VSS#14

L31

PCIE_VSS#15

L34

PCIE_VSS#16

M34

PCIE_VSS#17

M39

PCIE_VSS#18

N31

PCIE_VSS#19

N34

PCIE_VSS#20

P31

PCIE_VSS#21

P34

PCIE_VSS#22

P39

PCIE_VSS#23

R34

PCIE_VSS#24

T31

PCIE_VSS#25

T34

PCIE_VSS#26

T39

PCIE_VSS#27

U31

PCIE_VSS#28

U34

PCIE_VSS#29

V34

PCIE_VSS#30

V39

PCIE_VSS#31

W31

PCIE_VSS#32

W34

PCIE_VSS#33

Y34

PCIE_VSS#34

Y39

PCIE_VSS#35

F15

GND#101

F17

GND#102

F19

GND#103

F21

GND#104

F23

GND#105

F25

GND#106

F27

GND#107

F29

GND#108

F31

GND#109

F33

GND#110

F7

GND#111

F9

GND#112

G2

GND#113

G6

GND#114

H9

GND#115

J2

GND#116

J27

GND#117

J6

GND#118

J8

GND#119

K14

GND#120

K7

GND#121

L11

GND#122

L17

GND#123

L2

GND#124

L22

GND#125

L24

GND#126

L6

GND#127

M17

GND#128

M22

GND#129

M24

GND#130

N16

GND#131

N18

GND#132

N2

GND#133

N21

GND#134

N23

GND#135

N26

GND#136

N6

GND#137

R15

GND#138

R17

GND#139

R2

GND#140

R20

GND#141

R22

GND#142

R24

GND#143

R27

GND#144

R6

GND#145

T11

GND#146

T13

GND#147

T16

GND#148

T18

GND#149

T21

GND#150

T23

GND#151

T26

GND#152

U15

GND#153

U17

GND#154

U2

GND#155

U20

GND#156

U22

GND#157

U24

GND#158

U27

GND#159

U6

GND#160

V11

GND#161

V16

GND#162

V18

GND#163

V21

GND#164

V23

GND#165

V26

GND#166

W2

GND#167

W6

GND#168

Y15

GND#169

Y17

GND#170

Y20

GND#171

Y22

GND#172

Y24

GND#173

Y27

GND#174

U13

GND#175

V13

GND#176

216-0729002 A12 M96_BGA962

216-0729002 A12 M96_BGA962 madison@

madison@

5

GND

VSS_MECH#1 VSS_MECH#2 VSS_MECH#3

GND#1 GND#2 GND#3 GND#4 GND#5 GND#6 GND#7 GND#8

GND#9 GND#10 GND#11 GND#12 GND#13 GND#14 GND#15 GND#16 GND#17 GND#18 GND#19 GND#20 GND#21 GND#22 GND#23 GND#24 GND#25 GND#26 GND#27 GND#28 GND#29 GND#30 GND#31 GND#32 GND#33 GND#34 GND#35 GND#36 GND#37 GND#38 GND#39 GND#40 GND#41 GND#42 GND#43 GND#44 GND#45 GND#46 GND#47 GND#48 GND#49 GND#50 GND#51 GND#52 GND#53 GND#54 GND#55 GND#56 GND#57 GND#58 GND#59 GND#60 GND#61 GND#62 GND#63 GND#64 GND#65 GND#66 GND#67 GND#68 GND#69 GND#70 GND#71 GND#72 GND#73 GND#74 GND#75 GND#76 GND#77 GND#78 GND#79 GND#80 GND#81 GND#82 GND#83 GND#84 GND#85 GND#86 GND#87 GND#88 GND#89 GND#90 GND#91 GND#92 GND#93 GND#94 GND#95 GND#96 GND#97 GND#98 GND#99

GND#100

A3 A37 AA16 AA18 AA2 AA21 AA23 AA26 AA28 AA6 AB12 AB15 AB17 AB20 AB22 AB24 AB27 AC11 AC13 AC16 AC18 AC2 AC21 AC23 AC26 AC28 AC6 AD15 AD17 AD20 AD22 AD24 AD27 AD9 AE2 AE6 AF10 AF16 AF18 AF21 AG17 AG2 AG20 AG22 AG6 AG9 AH21 AH29 AJ10 AJ11 AJ2 AJ28 AJ6 AK11 AK31 AK7 AL11 AL14 AL17 AL2 AL20 AL21 AL23 AL26 AL32 AL6 AL8 AM11 AM31 AM9 AN11 AN2 AN30 AN6 AN8 AP11 AP7 AP9 AR5 AW34 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B7 B9 C1 C39 E35 E5 F11 F13

A39 AW1 AW39

4

FB_GND, only for Madison if unused, leave NC.

L62

BLM18PG121SN1D_0603

+1.8VS

only-M96@

1 2

R1574

R1574 0_0402_5%

0_0402_5%

BLM18PG121SN1D_0603

+1.1VS

12

madison@

0_0402_5%

0_0402_5% R1570

R1570

PowerXpress control signal for madison only if not used, can be disconnected.

4

3

U28H

R542

0_0603_5%~D

+1.8VS

+1.1VS

+1.8VS

+1.1VS

12

C871

10U_0603_6.3V6M~D

C871

10U_0603_6.3V6M~D

C870

0.1U_0402_16V4Z~D

C870

0.1U_0402_16V4Z~D

1

2

L58

12

10U_0603_6.3V6M~D

1

2

0_0603_5%~D

R483

0_0603_5%~D

R1260

0_0603_5%~D

R485 0_0603_5%~DR485 0_0603_5%~D

+DPE_VDD18

C869

1U_0402_6.3V4Z~D

C869

1U_0402_6.3V4Z~D

1

2

+DPE_VDD18

+DPE_VDD10

C746

C747

0.1U_0402_16V4Z~D

C747

0.1U_0402_16V4Z~D

C748

1U_0402_6.3V4Z~D

C748

1U_0402_6.3V4Z~D

1

2

+DPF_VDD18

+DPF_VDD10

+DPE_VDD10

+DPC_VDD18

+DPC_VDD10

+DPD_VDD18

+DPD_VDD10+DPD_VDD10

R486

150_0402_1%~D

+DPE_VDD10

+DPE_VDD18

12

R1568

R1568 0_0402_5%~D

0_0402_5%~D madison@

madison@

+DPF_VDD18

+DPF_VDD10

R1572

madison@R1572

madison@

12

0_0402_5%~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

110mA

130mA

110mA

12

200mA

120mA

200mA

120mA

R493

12

150_0402_1%~D

3

AP20

NC_DPC_VDD18#1

AP21

NC_DPC_VDD18#2

AP13

DPC_VDD10#1

AT13

DPC_VDD10#2

AN17

DPC_VSSR#1

AP16

DPC_VSSR#2

AP17

DPC_VSSR#3

AW14

DPC_VSSR#4

AW16

DPC_VSSR#5

AP22

NC_DPD_VDD18#1

AP23

NC_DPD_VDD18#2

AP14

DPD_VDD10#1

AP15

DPD_VDD10#2

AN19

DPD_VSSR#1

AP18

DPD_VSSR#2

AP19

DPD_VSSR#3

AW20

DPD_VSSR#4

AW22

DPD_VSSR#5

AW18

DPCD_CALR

DP E/F POWER

AH34

DPE_VDD18#1

AJ34

DPE_VDD18#2

AL33

DPE_VDD10#1

AM33

DPE_VDD10#2

AN34

DPE_VSSR#1

AP39

DPE_VSSR#2

AR39

DPE_VSSR#3

AU37

DPE_VSSR#4

AW35

DPE_VSSR#5

AF34

DPF_VDD18#1

AG34

DPF_VDD18#2

AK33

DPF_VDD10#1

AK34

DPF_VDD10#2

AF39

DPF_VSSR#1

AH39

DPF_VSSR#2

AK39

DPF_VSSR#3

AL34

DPF_VSSR#4

AM34

DPF_VSSR#5

AM39

DPEF_CALR

216-0729002 A12 M96_BGA962

216-0729002 A12 M96_BGA962 madison@

madison@

2009/06/12 2010/06/12

DP A/B POWERDP C/D POWER

NC_DPA_VDD18#1 NC_DPA_VDD18#2

DPA_VDD10#1 DPA_VDD10#2

DPA_VSSR#1 DPA_VSSR#2 DPA_VSSR#3 DPA_VSSR#4 DPA_VSSR#5

NC_DPB_VDD18#1 NC_DPB_VDD18#2

DPB_VDD10#1 DPB_VDD10#2

DPB_VSSR#1 DPB_VSSR#2 DPB_VSSR#3 DPB_VSSR#4 DPB_VSSR#5

DPAB_CALR

DP PLL POWER

DPA_PVDD DPA_PVSS

DPB_PVDD DPB_PVSS

DPC_PVDD

DPC_PVSS

DPD_PVDD

DPD_PVSS

DPE_PVDD DPE_PVSS

NC_DPF_PVDD

NC_DPF_PVSS

Compal Secret Data

Deciphered Date

AN24 AP24

AP31 AP32

AN27 AP27 AP28 AW24 AW26

AP25 AP26

AN33 AP33

AN29 AP29 AP30 AW30 AW32

AW28

AU28 AV27

AV29 AR28

AU18 AV17

AV19 AR18

AM37 AN38

AL38 AM35

130mA130mA

+DPA_VDD10

110mA

130mA

110mA

20mA

2

Madison

+DPB_VDD10

R487

R487 150_0402_1%~D

150_0402_1%~D

1 2

+DPA_PVDD

+DPB_PVDD

+DPC_PVDD

+DPD_PVDD

+DPE_PVDD

+DPF_PVDD

2

+DPA_VDD18

madison@

C739

0.1U_0402_16V4Z~D

C739

0.1U_0402_16V4Z~D

1

2

C742

0.1U_0402_16V4Z~D

C742

0.1U_0402_16V4Z~D

2

1

2

0.1U_0402_16V4Z~D

1

2

1

C1200

1U_0402_6.3V4Z~D

C740

C743

1

2

1

2

1

2

1

L93

L93 BLM18PG121SN1D_0603

madison@

C1172

0.1U_0402_16V4Z~D

C1172

0.1U_0402_16V4Z~D 2

1

L56

BLM18PG121SN1D_0603

C741

10U_0603_6.3V6M~D

C741

10U_0603_6.3V6M~D

BLM18PG121SN1D_0603

C744

10U_0603_6.3V6M~D

C744

10U_0603_6.3V6M~D

C749

0.1U_0402_16V4Z~D

C749

0.1U_0402_16V4Z~D

1

2

BLM18PG121SN1D_0603

12

madison@

C1174

10U_0603_6.3V6M~D

C1174

10U_0603_6.3V6M~D

C1173

1U_0402_6.3V4Z~D

C1173

1U_0402_6.3V4Z~D

1

madison@

2

12

+1.1VS

+DPB_VDD18

madison@

L57

12

+1.1VS

C755

0.1U_0402_16V4Z~D

C755

0.1U_0402_16V4Z~D

1

2

C757

0.1U_0402_16V4Z~D

C757

0.1U_0402_16V4Z~D

1

2

C745

0.1U_0402_16V4Z~D

C745

0.1U_0402_16V4Z~D

1

2

R489

C753

0.1U_0402_16V4Z~D

C753

0.1U_0402_16V4Z~D

1U_0402_6.3V4Z~D

1

2

1

Title

Size Document Number Rev

Custom

401808

Date: Sheet

+1.8VS

For M96/92, DPx_VDD=1.1V

madison@

C1178

0.1U_0402_16V4Z~D

C1178

0.1U_0402_16V4Z~D

C1179

1U_0402_6.3V4Z~D

C1179

1U_0402_6.3V4Z~D

1

2

C756

1U_0402_6.3V4Z~D

C756

1U_0402_6.3V4Z~D

2

1

C759

1U_0402_6.3V4Z~D

C759

1U_0402_6.3V4Z~D

2

1

R488

0_0603_5%~D

10U_0603_6.3V6M~D

C884

1

2

Compal Electronics, Inc.

SCHEMATICS, MB A5155

1

2

1

L60

L60 BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

C754

10U_0603_6.3V6M~D

C754

10U_0603_6.3V6M~D

1

2

L61

BLM18PG121SN1D_0603

C758

10U_0603_6.3V6M~D

C758

10U_0603_6.3V6M~D

1

2

0_0603_5%~D

L64

BLM18PG121SN1D_0603

12

C885

1

L95

L95 BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

madison@

C1180

10U_0603_6.3V6M~D

C1180

10U_0603_6.3V6M~D

madison@

12

+1.8VS

42 57Monday, September 21, 2009

Madison

12

+1.8VS

of

+1.8VS

A

5

VREFCA_A1 VREFDA_Q1

D D

A_BA0<40> A_BA1<40> A_BA2<40>

MDA[0..63]<40>

MAA[13..0]<40>

DQMA#[7..0]<40>

QSA[7..0]<40>

C C

QSA#[7..0]<40>

B B

CLKA0<40>

CLKA0#<40>

CLKA1<40>

A A

CLKA1#<40>

MDA[0..63]

VRAM_RST#<40,44>

R514

M96@ R514

M96@

56_0402_1%~D

1 2

R515

M96@ R515

M96@

56_0402_1%~D

1 2

R516 56_0402_1%~D

56_0402_1%~D

1 2

R517 56_0402_1%~D

56_0402_1%~D

1 2

R494

R494 243_0402_1%~OK

243_0402_1%~OK

M96@

4.99K_0402_1%~OK

M96@R516

M96@

M96@R517

M96@

CLKA0<40> CLKA0#<40> CKEA0<40>

ODTA0<40> CSA0#_0<40> RASA0#<40> CASA0#<40> WEA0#<40>

QSA2 QSA0

DQMA#2 DQMA#0

QSA#2 QSA#0

VRAM_RST#

12

+1.5VS +1.5VS

12

M96@

M96@ R498

R498

12

M96@

M96@ R506

R506

C768

0.01U_0402_25V7K~D

1

M96@C768

M96@

2

C801

0.01U_0402_25V7K~D

1

M96@C801

M96@

2

U30

M8

VREFCA

H1

VREFDQ

MAA0

N3

A0

MAA1

P7

A1

MAA2

P3

A2

N2

A3

MAA4

P8

A4

MAA5

P2

A5

MAA6

R8

A6

MAA7

R2

A7

MAA8

T8

A8

MAA9 MAA9

R3 MAA10 MAA11 MAA12 MAA13 MAA13 MAA13 MAA13

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

K4B1G1646E-HC12_FBGA96

4.99K_0402_1%~OK

VREFCA_A1 VREFDA_Q1

0.1U_0402_10V6K~D

1

M96@

M96@ C760

C760

4.99K_0402_1%~OK

2

+1.5VS +1.5VS

C769

1U_0402_6.3V6K~D

1

M96@C769

M96@

2

+1.5VS

C802

10U_0603_6.3V6M~D

1

M96@C802

M96@

2

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

M96@

M96@ R499

R499

M96@

M96@ R507

R507

C770

1U_0402_6.3V6K~D

1

M96@C770

M96@

2

C803

10U_0603_6.3V6M~D

1

M96@C803

M96@

2

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

12

C771

1U_0402_6.3V6K~D

1

M96@C771

M96@

2

C804

10U_0603_6.3V6M~D

M96@C804

M96@

4

MDA22

E3

MDA19

F7

MDA21

F2

MDA18

F8

MDA23

H3

MDA16

H8

MDA20

G2

MDA17

H7

MDA0

D7

MDA5

C3

MDA1

C8

MDA7

C2

MDA3

A7

MDA4

A2

MDA2

B8

MDA6

A3

+1.5VS

B2 D9 G7 K2 K8 N1 N9 R1 R9

+1.5VS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

M96@

M96@ C761

C761

C772

1U_0402_6.3V6K~D

M96@C772

M96@

10U_0603_6.3V6M~D

1

2

1

2

C805

M96@C805

M96@

1

2

1U_0402_6.3V6K~D

1

2

0.1U_0402_10V6K~D

C773

M96@C773

M96@

10U_0603_6.3V6M~D

1

2

C806

M96@C806

M96@

R495

R495 243_0402_1%~OK

243_0402_1%~OK

1U_0402_6.3V6K~D

VREFCA_A2 VREFDA_Q2

MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8

MAA9 MAA10 MAA11 MAA12

A_BA0 A_BA1 A_BA2

CLKA0 CLKA0# CKEA0

ODTA0 CSA0#_0 RASA0# CASA0# WEA0#

QSA3 QSA1

DQMA#3 DQMA#1

QSA#3 QSA#1

VRAM_RST#

12

M96@

M96@ R500

R500

4.99K_0402_1%~OK

M96@

M96@ R508

R508

4.99K_0402_1%~OK

C774

C775

1U_0402_6.3V6K~D

C776

1U_0402_6.3V6K~D

1

M96@C774

M96@

M96@C775

M96@

M96@C776

M96@

2

VRAM P/N : Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P) Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )

U31

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

K4B1G1646E-HC12_FBGA96

12

VREFCA_A2 VREFDA_Q2

1

12

M96@

M96@ C762

C762

2

1U_0402_6.3V6K~D

1

2

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

4.99K_0402_1%~OK

0.1U_0402_10V6K~D

4.99K_0402_1%~OK

C778

1U_0402_6.3V6K~D

C777

1

M96@C778

M96@

M96@C777

M96@

2

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

+1.5VS+1.5VS +1.5VS+1.5VS

M96@

M96@ R501

R501

M96@

M96@ R509

R509

1U_0402_6.3V6K~D

1

2

C779

M96@C779

M96@

3

MDA25

E3

MDA30

F7

MDA24

F2

MDA29

F8

MDA26

H3

MDA31

H8

MDA27

G2

MDA28

H7

MDA15

D7

MDA11

C3

MDA14

C8

MDA10

C2

MDA13

A7

MDA9

A2

MDA12

B8

MDA8

A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

+1.5VS

R496

R496 243_0402_1%~OK

243_0402_1%~OK

12

0.1U_0402_10V6K~D

1

12

M96@

M96@ C763

C763

2

C781

1U_0402_6.3V6K~D

C780

1U_0402_6.3V6K~D

1

M96@C781

M96@

M96@C780

M96@

2

VREFCA_A3 VREFDA_Q3

MAA0 MAA1 MAA2 MAA3MAA3 MAA4 MAA5 MAA6 MAA7 MAA8

MAA9 MAA10 MAA11 MAA12

A_BA0 A_BA1 A_BA2

CLKA1<40> CLKA1#<40> CKEA1<40>

ODTA1<40> CSA1#_0<40> RASA1#<40> CASA1#<40> WEA1#<40>

QSA4 QSA5

DQMA#4 DQMA#5

QSA#4 QSA#5

VRAM_RST#

12

M96@

4.99K_0402_1%~OK

C782

1U_0402_6.3V6K~D

C783

1U_0402_6.3V6K~D

M96@C782

M96@

1

M96@C783

M96@

2

1

2

1U_0402_6.3V6K~D

M96@

M96@ R502

R502

M96@

M96@ R510

R510

+1.5VS

C784

M96@C784

M96@

+1.5VS

M8

H1 N3

P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7

M7

M2

N8

M3

J7 K7 K9

K1 L2 J3 K3 L3

F3 C7

E7 D3

G3

B7

T2 L8

J1 L1 J9 L9

1

2

1

2

U32

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

1

M96@

M96@ C764

C764

2

C785

1U_0402_6.3V6K~D

1

M96@C785

M96@

2

C807

10U_0603_6.3V6M~D

1

M96@C807

M96@

2

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

4.99K_0402_1%~OK

0.1U_0402_10V6K~D

4.99K_0402_1%~OK

1U_0402_6.3V6K~D

C786

1

M96@C786

M96@

2

10U_0603_6.3V6M~D

C808

1

M96@C808

M96@

2

C787

M96@C787

M96@

C809

M96@C809

M96@

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

BA0 BA1 BA2

CK CK CKE/CKE0

ODT/ODT0 CS/CS0 RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET ZQ/ZQ0

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

K4B1G1646E-HC12_FBGA96

12

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

1

2

1

2

M96@

M96@ R503

R503

M96@

M96@ R511

R511

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

C788

M96@C788

M96@

C810

M96@C810

M96@

1

2

1

2

MDA35 MDA32 MDA38 MDA34 MDA37 MDA36 MDA39 MDA33

MDA43 MDA44 MDA40 MDA45 MDA42 MDA46 MDA41 MDA47

12

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

M96@

M96@ C765

C765

C789

M96@C789

M96@

C811

M96@C811

M96@

2

+1.5VS

R497

R497 243_0402_1%~OK

243_0402_1%~OK

M96@

VREFDA_Q3VREFCA_A3

0.1U_0402_10V6K~D

1

2

C790

1U_0402_6.3V6K~D

1

M96@C790

M96@

2

1U_0402_6.3V6K~D

12

C791

M96@C791

M96@

VREFCA_A4 VREFDA_Q4

MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8

MAA10 MAA11 MAA12

A_BA0 A_BA1 A_BA2

CLKA1 CLKA1# CKEA1

ODTA1 CSA1#_0 RASA1# CASA1# WEA1#

QSA6 QSA7

DQMA#6 DQMA#7

QSA#6 QSA#7

VRAM_RST#

4.99K_0402_1%~OK

C792

1U_0402_6.3V6K~D

1

M96@C792

M96@

2

U33

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4B1G1646E-HC12_FBGA96

12

M96@

M96@ R504

R504

12

M96@

M96@ C766

C766

R512

+1.5VS

C793

1U_0402_6.3V6K~D

1

M96@C793

M96@

2

1

MDA48

E3

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VREFCA_A4 VREFDA_Q4

1

2

C794

1U_0402_6.3V6K~D

M96@C794

M96@

F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

4.99K_0402_1%~OK

0.1U_0402_10V6K~D

4.99K_0402_1%~OK

C795

1U_0402_6.3V6K~D

1

M96@C795

M96@

2

MDA51 MDA55 MDA54 MDA50 MDA52 MDA49

MDA63 MDA58 MDA60 MDA59 MDA61 MDA56 MDA62 MDA57

M96@

M96@ R505

R505

M96@

M96@ R513

R513

1U_0402_6.3V6K~D

MDA53

+1.5VS+1.5VS

C796

M96@C796

M96@

+1.5VS

12

0.1U_0402_10V6K~D

1

12

M96@

M96@ C767

C767

2

C797

1U_0402_6.3V6K~D

C798

1U_0402_6.3V6K~D

M96@C797

M96@

1

M96@C798

M96@

2

1

2

1U_0402_6.3V6K~D

C799

M96@C799

M96@

C800

1U_0402_6.3V6K~D

1

M96@C800

M96@

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/06/12 2010/06/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

1

A

of

43 57Monday, September 21, 2009

5

VREFCB_A1 VREFDB_Q1

D D

B_BA0<40> B_BA1<40>

MDB[0..63]<40>

MAB[13..0]<40>

DQMB#[7..0]<40>

QSB[7..0]<40>

C C

B B

A A

QSB#[7..0]<40>

CLKB0<40>

CLKB0#<40>

CLKB1<40>

CLKB1#<40>

MDB[0..63]

VRAM_RST#<40,43>

R538

R538 56_0402_1%~D

56_0402_1%~D

1 2

R539

R539 56_0402_1%~D

56_0402_1%~D

1 2

R540

R540 56_0402_1%~D

56_0402_1%~D

1 2

R541

R541 56_0402_1%~D

56_0402_1%~D

1 2

B_BA2<40>

CLKB0<40> CLKB1<40> CLKB0#<40> CKEB0<40>

ODTB0<40> CSB0#_0<40> RASB0#<40> CASB0#<40> WEB0#<40>

QSB3 QSB1

DQMB#3 DQMB#1

QSB#3 QSB#1

VRAM_RST#

12

R518

243_0402_1%~OK

+1.5VS +1.5VS

12

R522

4.99K_0402_1%~OK

12

R530

4.99K_0402_1%~OK

C820

0.01U_0402_25V7K~D

C820

0.01U_0402_25V7K~D

1

2

C853

0.01U_0402_25V7K~D

C853

0.01U_0402_25V7K~D

1

2

U34

M8

VREFCA

H1

VREFDQ

MAB0

N3

A0

MAB1

P7

A1

MAB2

P3

A2

MAB3

N2

A3

MAB4

P8

A4

MAB5

P2

A5

MAB6

R8

A6

MAB7

R2

A7

MAB8

T8

A8

MAB9

R3

A9

MAB10

L7

A10/AP

MAB11

R7

A11

MAB12

N7

A12

MAB13 MAB13 MAB13 MAB13

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

K4B1G1646E-HC12_FBGA96

4.99K_0402_1%~OK

VREFCB_A1

0.1U_0402_10V6K~D

1

C812

4.99K_0402_1%~OK

2

+1.5VS +1.5VS

C821

1U_0402_6.3V6K~D

C821

1U_0402_6.3V6K~D

1

2

+1.5VS

C854

10U_0603_6.3V6M~D

C854

10U_0603_6.3V6M~D

1

2

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

R523

R531

C822

1U_0402_6.3V6K~D

C822

1U_0402_6.3V6K~D

1

2

C855

10U_0603_6.3V6M~D

C855

10U_0603_6.3V6M~D

1

2

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

12

C823

1U_0402_6.3V6K~D

C823

1U_0402_6.3V6K~D

1

2

C856

10U_0603_6.3V6M~D

C856

10U_0603_6.3V6M~D

4

MDB26

E3

MDB28

F7

MDB27

F2

MDB31

F8

MDB25

H3

MDB30

H8

MDB24

G2

MDB29

H7

MDB15

D7

MDB10

C3

MDB12

C8

MDB11

C2

MDB13

A7

MDB9

A2

MDB14

B8

MDB8

A3

+1.5VS

B2 D9 G7 K2 K8 N1 N9 R1 R9

+1.5VS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

C813

C824

1U_0402_6.3V6K~D

C824

1U_0402_6.3V6K~D

1

2

C857

10U_0603_6.3V6M~D

C857

10U_0603_6.3V6M~D

1

2

VREFDB_Q1

0.1U_0402_10V6K~D

1

2

C825

1U_0402_6.3V6K~D

C825

1U_0402_6.3V6K~D

1

2

C858

10U_0603_6.3V6M~D

C858

10U_0603_6.3V6M~D

1

2

243_0402_1%~OK

C826

1U_0402_6.3V6K~D

C826

1U_0402_6.3V6K~D

1

2

VREFCB_A2 VREFDB_Q2

B_BA0<40> B_BA1<40> B_BA2<40>

CLKB0<40> CLKB0#<40> CKEB0<40> CKEB1<40>

ODTB0<40> CSB0#_0<40> RASB0#<40> CASB0#<40> WEB0#<40>

QSB2 QSB0

DQMB#2 DQMB#0

QSB#2 QSB#0

VRAM_RST#

12

R519

R524

4.99K_0402_1%~OK

R532

4.99K_0402_1%~OK

C827

1U_0402_6.3V6K~D

C827

1U_0402_6.3V6K~D

C828

1U_0402_6.3V6K~D

C828

1U_0402_6.3V6K~D

1

2

U35

M8

VREFCA

H1

VREFDQ

MAB0

N3

A0

MAB1

P7

A1

MAB2

P3

A2

MAB3

N2

A3

MAB4

P8

A4

MAB5

P2

A5

MAB6

R8

A6

MAB7

R2

A7

MAB8

T8

A8

MAB9

R3

A9

MAB10

L7

A10/AP

MAB11

R7

A11

MAB12

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

K4B1G1646E-HC12_FBGA96

12

VREFCB_A2 VREFDB_Q2

0.1U_0402_10V6K~D

1

12

C814

2

C829

1U_0402_6.3V6K~D

C829

1U_0402_6.3V6K~D

1

2

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

+1.5VS+1.5VS +1.5VS +1.5VS

R525

4.99K_0402_1%~OK

R533

4.99K_0402_1%~OK

C830

1U_0402_6.3V6K~D

C830

1U_0402_6.3V6K~D

1

2

VDD VDD VDD VDD VDD VDD VDD VDD VDD

C831

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

3

MDB22

E3

MDB20

F7

MDB21

F2

MDB18

F8

MDB19

H3

MDB17

H8

MDB23

G2

MDB16

H7

MDB1

D7

MDB6

C3

MDB0

C8

MDB4

C2

MDB3

A7

MDB7

A2

MDB2

B8

MDB5

A3

+1.5VS

B2 D9 G7 K2 K8 N1 N9 R1 R9

+1.5VS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

12

0.1U_0402_10V6K~D

1

12

C815

2

C832

1U_0402_6.3V6K~D

C832

1U_0402_6.3V6K~D

C833

1U_0402_6.3V6K~D

C833

1U_0402_6.3V6K~D

1

2

1

2

C834

1U_0402_6.3V6K~D

C834

1U_0402_6.3V6K~D

R520

243_0402_1%~OK

C835

1U_0402_6.3V6K~D

C835

1U_0402_6.3V6K~D

1

2

VREFCB_A3 VREFDB_Q3

B_BA0<40> B_BA1<40> B_BA2<40>

CLKB1<40> CLKB1#<40>

ODTB1<40> CSB1#_0<40> RASB1#<40> CASB1#<40> WEB1#<40>

QSB4 QSB5

DQMB#4 DQMB#5

QSB#4 QSB#5

VRAM_RST#

12

R526

4.99K_0402_1%~OK

R534

4.99K_0402_1%~OK

+1.5VS

C836

1U_0402_6.3V6K~D

C836

1U_0402_6.3V6K~D

1

2

+1.5VS

1

2

1

2

MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12

12

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

C837

C859

C816

M8 H1

N3

P7 P3

N2

P8

P2 R8 R2

T8 R3

L7 R7 N7

T3

T7 M7

M2 N8 M3

K7

K9

K1

L2

K3

L3

F3 C7

E7 D3

G3

B7

T2

L8

L1

L9

1

2

1

2

U36

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

BA0 BA1 BA2

J7

CK CK CKE/CKE0

ODT/ODT0 CS/CS0

J3

RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET ZQ/ZQ0

J1

NC/ODT1 NC/CS1

J9

NC/CE1 NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4B1G1646E-HC12_FBGA96

4.99K_0402_1%~OK

0.1U_0402_10V6K~D

1

4.99K_0402_1%~OK

2

C839

1U_0402_6.3V6K~D

C839

1U_0402_6.3V6K~D

C838

1U_0402_6.3V6K~D

C838

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

C860

1

2

C861

10U_0603_6.3V6M~D

C861

10U_0603_6.3V6M~D

1

2

R527

R535

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

C840

C862

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

2

B_BA0<40> B_BA1<40> B_BA2<40>

CLKB1#<40> CKEB1<40>

ODTB1<40> CSB1#_0<40> RASB1#<40> CASB1#<40> WEB1#<40>

R528

R536

+1.5VS

VREFCB_A4 VREFDB_Q4

QSB6 QSB7

DQMB#6 DQMB#7

QSB#6 QSB#7

VRAM_RST#

12

C845

1U_0402_6.3V6K~D

C845

1U_0402_6.3V6K~D

1

2

MDB34

E3

MDB37

F7

MDB32

F2

MDB39

F8

MDB35

H3

MDB38

H8

MDB33

G2

MDB36

H7

MDB44

D7

MDB43

C3

MDB47

C8

MDB41

C2

MDB45

A7

MDB40

A2

MDB46

B8

MDB42

A3

+1.5VS

B2 D9 G7 K2 K8 N1 N9 R1 R9

+1.5VS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

12

VREFDB_Q3VREFCB_A3

0.1U_0402_10V6K~D

1

12

C817

2

C842

1U_0402_6.3V6K~D

C842

1U_0402_6.3V6K~D

C841

1U_0402_6.3V6K~D

C841

1U_0402_6.3V6K~D

1

2

10U_0603_6.3V6M~D

1

2

C863

1

2

C843

1U_0402_6.3V6K~D

C843

1U_0402_6.3V6K~D

R521

R521 243_0402_1%~OK

243_0402_1%~OK

4.99K_0402_1%~OK

C844

1U_0402_6.3V6K~D

C844

1U_0402_6.3V6K~D

1

2

U37

M8

VREFCA

H1

VREFDQ

MAB0

N3

A0

MAB1

P7

A1

MAB2

P3

A2

MAB3

N2

A3

MAB4

P8

A4

MAB5

P2

A5

MAB6

R8

A6

MAB7

R2

A7

MAB8

T8

A8

MAB9

R3

A9

MAB10

L7

A10/AP

MAB11

R7

A11

MAB12

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4B1G1646E-HC12_FBGA96

4.99K_0402_1%~OK

VREFCB_A4 VREFDB_Q4

0.1U_0402_10V6K~D

1

C818

4.99K_0402_1%~OK

2

C847

1U_0402_6.3V6K~D

C847

1U_0402_6.3V6K~D

C846

1U_0402_6.3V6K~D

C846

1U_0402_6.3V6K~D

1

2

1

MDB52

E3

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

+1.5VS+1.5VS

12

R529

12

R537

C848

1U_0402_6.3V6K~D

C848

1U_0402_6.3V6K~D

1

2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

C819

C849

MDB51

F7

MDB55

F2

MDB48

F8

MDB53

H3

MDB49

H8

MDB54

G2

MDB50

H7

MDB56

D7

MDB59

C3

MDB63

C8

MDB62

C2

MDB57

A7

MDB61

A2

MDB58

B8

MDB60

A3

+1.5VS

B2 D9 G7 K2 K8 N1 N9 R1 R9

+1.5VS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

0.1U_0402_10V6K~D

1

2

C850

1U_0402_6.3V6K~D

C850

1U_0402_6.3V6K~D

1

2

C852

1U_0402_6.3V6K~D

C852

1U_0402_6.3V6K~D

C851

1U_0402_6.3V6K~D

C851

1U_0402_6.3V6K~D

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/06/12 2010/06/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc. SCHEMATICS, MB A5155

SCHEMATICS, MB A5155

401808

1

44 57Monday, September 21, 2009

A

of

44 57Monday, September 21, 2009

5

7

6

5

D D

C C

5

4

3

2

1

MOLEX_87438-0743

PJPDC1

@PJPDC1

@

12

PL2

BLM18BD102SN1D_0603~D

DOCK_PSIDPSID

12

PC2

100P_0402_50V8J~D

4

ADPIN

PL1

PC5

1 2

1000P_0402_50V7K~D

PL1

12

PC6

100P_0402_50V8J~D

FBMA-L18-453215-900LMA90T_1812~D

12

PC3

12

PC4

1000P_0402_50V7K~D

100P_0402_50V8J~D

3

VIN

12

PC7

1000P_0402_50V7K~D

DOCK_PSID

2

1

3

PD5

@PD5

@ SM24_SOT23

SM24_SOT23

PR18

1 2

100K_0402_1%~D

PR20

1 2

15K_0402_1%~D

2

PR15

@PR15

@

1 2

0_0402_5%~D

PQ2

D

1 3

FDV301N_NL_SOT23-3~D

G

2

C

PQ3

2

B

MMST3904-7-F_SOT323~D

E

3 1

S

PR17

33_0402_5%~D

1 2

PD4

DA204U_SOT323~D

1

+3VALW+5VALW

2

3

1

+5VALW

12

PR19

10K_0402_1%~D

@PR21

@

1 2

10K_0402_1%~D

PR21

PR16

@

1 2

2.2K_0402_5%~D

+5VALW

PD6

DA204U_SOT323~D

PS_ID <31>

2

3

1

VIN

PD2

PJP1

12

PC11

0.22U_1206_25V7K

1 2

PR14 0_0402_5%~DPR14 0_0402_5%~D

PJP1 JUMP_43X118@

JUMP_43X118@

112

2

TP0610K-T1-E3_SOT23-3

32.8

12

4

PD3

BATT+

RLS4148_LL34-2

B B

51ON#<32>

RTCVREF

12

PC13

A A

PC13

4.7U_0805_6.3V6K~D

5

PU3

3

OUT

4

5/3+

2

12

CHGRTCP

12

PR11

100K_0402_5%~D

PR12

22K_0402_5%~D

1 2

MAX1615_IN

1

IN

MAX1615_#SHDN

5

#SHDN GND

MAX1615EUK+_SOT23-5~D

1 2 12

68_1206_5%~D

PQ1

13

12

PC14

PC14 1U_0805_25V4Z~D

1U_0805_25V4Z~D

PD2

RLS4148_LL34-2

PR10

PC12

0.1U_0603_25V7K~D

12

PR13

PR13 200_0805_5%

200_0805_5%

12

PR208

68_1206_5%~D

VS

PC194

@

.1U_0402_16V7K~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

VIN

12

PR191

@PR191

@

82.5K_0402_1%~D

82.5K_0402_1%~D PR193

@PR193

@

22K_0402_1%~D

1 2

12

PR206

19.6K_0402_1%~D

8

@ PU17B

@

P

G

LM393DR_SO8

4

PU17B

O

12

7

Compal Secret Data

12

@

32.3

5

+

6

-

2009/07/29 2010/07/29

PC193

@

2200P_0402_50V7K~D

1 2

VinDe_IN3N41 VinDe_Ref

PC191

@PC191

@

1000P_0402_50V7K~D

@PR204

@ 56K_0402_5%~D

56K_0402_5%~D

1 2

PR202

@ PR202

@ 1M_0402_1%~D

1M_0402_1%~D

1 2

VS

8

3

P

+

2

-

G

LM393DR_SO8

4

PR201

@PR201

@ 10K_0402_5%~D

10K_0402_5%~D

12

PR204

PC192

@

O

PU17A

@PU17A

@

12

0.01U_0402_25V7K~D

1

RLZ4.3B_LL34

RTCVREF

3.3V

Vin Detector Max. typ. Min.

L-->H 18.234 17.841 17.449 H-->L 17.597 17.210 16.813

Deciphered Date

2

@PD1

@

PD1

VIN

12

PR205

@PR205

@

10K_0402_5%~D

12

Title

Size Document Number Rev

Custom

Date: Sheet

PR192

@PR192

@

1K_0402_5%~D

1 2

VinDe_Out

12

PR203

@PR203

@

10K_0402_5%~D

401808

ACIN <17,25,31,39,49>

Compal Electronics, Inc.

SCHEMATICS, MB A5155

1

A

of

48 57Monday, September 21, 2009

A

VIN

12

PR23

1 1

3.3_1210_5%~D

12

PR27

3.3_1210_5%~D

PC19

2.2U_0805_25V6K

1 2

PC16

0.01U_0603_50V7K~D

PQ4

8

D

7

D

6

D

5

D

FDS6675BZ_SO8

PR28

PR28 340K_0402_1%~D

340K_0402_1%~D

1 2

ACDET

1

S

2

S

3

S

4

G

CP setting

PR31

54.9K_0402_1%

PR34

PR34 340K_0402_1%~D

340K_0402_1%~D

1 2

2 2

PR35

54.9K_0402_1%

1 2

90W adapter Icharge=(Vsrset/Vvdac)*(0.1/PR29)=3.3A Iadapter=(Vacset/Vvdac)*(0.1/PR22)=4.16A Input OVP : 22.3V Input UVP : 16.98V Fsw : 300KHz

3 3

PR46

1 2

B+

100_0805_5%~D

+5VALW

PR48

1 2

12

470K_0402_5%~D

1 2

220K_0402_5%

470K_0402_5%~D

2

G

A

PD8

1SS355TE-17_SOD323-2

PR52

1 2

220K_0402_5%

4 4

12

PC47

PR54

0.1U_0603_25V7K~D

PQ12

TP0610K-T1-E3_SOT23-3

13

32.8

2

13

D

PQ15

PQ15 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

PC44

CHGVADJ<31>

1 2

0.1U_0805_25V7M~N

1 2

CP_SEL<31>

PR36

100K_0402_1%~D

1 2

0.1U_0603_25V7K~D

ACGOOD#

PR44

210K_0402_1%~D

1 2

B+_BIAS

ACOFF

1 2

.1U_0402_16V7K~D

CP_SEL

@

SI2301BDS-T1-E3_SOT23-3

GATE

PC40

REGN

100K_0402_1%~D

PC45

PC190

PC25

0.1U_0402_10V7K~D

12

PR50

0.022U_0603_50V7K~D

12

B

12

1 2

PR26

2

G

PQ9

2

ACSET

12

PR43

PR43 0_0402_5%~D@

0_0402_5%~D@

VADJ

12

PR45

PR45 499K_0402_1%~D

499K_0402_1%~D

VREF

12

PR53

340K_0402_1%~D

B

1

S

2

S

3

S

4

G

SI4459ADY_SO8

100K_0402_1%~D

PC82

1000P_0603_50V7K~D

1 2

PR37

1K_0603_1%~D

1 2

PR89

PR89 143K_0402_1%~D

143K_0402_1%~D

1 2 13

D

S

PQ25

+3VALW

SSM3K7002FU_SC70-3

+3VALW

1 3

VREF

12

PR49

PR49 200K_0402_1%~D

200K_0402_1%~D

13

D

2

G

S

PQ5

12

0.015_2512_1%

8

D

7

D

6

1

D

5

D

2

.1U_0402_16V7K~D

1 2

12

PC26

0.1U_0603_25V7K~D

ACDRV_CHG#

12

PC33

PR30

@ PC33

@

60.4K_0402_1%

0.01U_0402_25V7K~D

PC39

1U_0603_10V6K~D

1 2

PR87

0_0402_5%~D

13

D

2

G

S

PQ14

PQ14 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

1 2

PR93

4.7_1206_5%~D

4.7_1206_5%~D PR22

PR22

4 3

PC24

12

ACN ACP

ACSET

12

PR33

PR33 100K_0402_1%~D

100K_0402_1%~D

1 2

PC34

0.47U_0603_16V7K~D

VREF

12

VADJ

/BATDRV

GATE

PQ13

PQ13 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

C

B+

PJP17

2

112

JUMP_43X118@

PC20

PU4

CHGEN#

1

CHGEN

PC27

0.1U_0603_25V7K~D

2

ACN

3

ACP

4

ACDRV

5

ACDET

6

ACSET

7

ACOP

8

OVPSET

9

AGND

10

VREF

PR86

PR86 0_0402_5%~D@

0_0402_5%~D@

11

VDAC

12

VADJ

13

ACGOOD

14

BATDRV

BQ24751ARHDR_QFN28_5X5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PVCC

BTST

HIDRV

PH

REGN

LODRV

PGND

LEARN

CELLS

SRP SRN

BAT

TP

SRSET

IADAPT

ADP_I<31>

+COINCELL

RTCVREF

2

PD9

BAT54CW_SOT323~D

C

28

27

26

25

24

23

22

21

20

19 18 17

29

16

15

100P_0402_50V8J~D

1

PC20

0.22U_0603_25V7K~D

1 2

PR25

2.2_0603_5%~D

1 2

DH_CHG

LX_CHG

PD7

RLS4148_LL34-2

REGN

12

PC29

PC29 1U_0603_10V6K~D

1U_0603_10V6K~D

DL_CHG

CELLS

1 2

SRP SRN

12

PC41

0.1U_0603_25V7K~D

0_0402_5%~D

12

ACOFF <31>

PR88

FDS8884_SO8

1 2

0.1U_0603_25V7K~D

FDS6690AS_1N_SO8

ICHG setting

SRSET

1 2

PR39

10_0603_5%~D

PC43

12

PR47

PR47 1K_0402_5%~D

1K_0402_5%~D

Z4012

3

+RTCVCC

1

PC46

PC46 1U_0603_10V4Z~D

1U_0603_10V4Z~D

2

2009/07/29 2010/07/29

12

PR40

PR40 100K_0402_1%~D

100K_0402_1%~D

12

Compal Secret Data

578

PQ6

3 6

241

PC28

578

PQ8

3 6

241

51.1K_0402_1%~D

12

@PC42

@

0.01U_0402_25V7K~D

IREF Current

3.3V 3.3A

COIN RTC Battery

+COINCELL

Deciphered Date

PR38

12

PC42

PJPRTC

@PJPRTC

@ 1 2 3 4

MOLEX_53398-0271_2P

1 2 G1 G2

PC189

D

12

2200P_0402_50V7K~D

D

PR32

4.7_1206_5%~D

PC35

680P_0603_50V7K~D

IREF <31>

CHG_B+

12

PC188

0.1U_0603_25V7K~D

10U_919AS-100M-P3_4.5A_20%

1 2

12

PC171000P_0402_50V7K~D PC171000P_0402_50V7K~D

PC214.7U_1206_25V6K~D PC214.7U_1206_25V6K~D

1 2

12

PL3

1 2

12

FSTCHG<31>

E

12

PR24

PR24 100K_0402_1%~D

1 2

PC15

/BATDRV

4 3

VREF

1 2

13

D

S

1 2

13

D

S

100K_0402_1%~D

0.01U_0402_25V7K~D

12

PC38

0.1U_0603_25V7K~D

PR42

47K_0402_1%~D

PQ11

PQ11 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

PR51

PR51 47K_0402_1%~D

47K_0402_1%~D

CHGEN#

PQ16

PQ16 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

E

4

3

S1S2S

G

PQ7

D8D7D6D

FDS6675BZ_SO8

5

BATT+

12

ACIN <17,25,31,39,48>

PC32

PC31

10U_1206_25V6M~D

of

49 57Monday, September 21, 2009

PC234.7U_1206_25V6K~D PC234.7U_1206_25V6K~D

PC181000P_0402_50V7K~D PC181000P_0402_50V7K~D

PC224.7U_1206_25V6K~D PC224.7U_1206_25V6K~D

1 2

12

PR29

0.02_2512_1%

0.02_2512_1% 1 2

PC30

10U_1206_25V6M~D

PC36

.1U_0402_16V7K~D

1 2

PC37

0.1U_0603_25V7K~D

RTCVREF

12

PR41

47K_0402_1%~D

ACGOOD#

Title

Size Document Number Rev

B

401808

Date: Sheet

2

G

2

G

Compal Electronics, Inc.

SCHEMATICS, MB A5155

10U_1206_25V6M~D

A

5

4

3

2

1

TPS51427_B+

12

PC53

PC52

PC51

2200P_0402_50V7K~D

4.7U_1206_25V6K~D

PL5

2.2UH_MPLC1040L2R2_11A_20%~D

12

PR58

4.7_1206_5%~D

12

PC62

680P_0603_50V7K~D

Title

Size Document Number Rev

Custom

401808

Date: Sheet

12

Compal Electronics, Inc.

SCHEMATICS, MB A5155

12

PC197

0.1U_0603_25V7K~D

PR61

1 2

61.9K_0402_1%~D

PR63

1 2

10K_0402_1%~D

1

+5VALWP

12

PC80

0.1U_0402_10V7K~D

50 57Monday, September 21, 2009

of

1

+

2

PC63

330U_D_6.3VM_R18M~D

A

12

PR66

100K_0402_1%~D

1 2

MAINPWON<20,39,56>

PQ21

TP0610K-T1-E3_SOT23-3

4

TPS51427_B+

578

PQ17

PQ17 SI4686DY-T1-E3_SO8

SI4686DY-T1-E3_SO8

3 6

241

PQ19

8

FDS6670AS_1N_SO8

D6D5D7D

4

G

S

3

2

1

PR67

1 2

200K_0402_5%~D

PR73

0_0402_5%~D

PR55

0_0805_5%

1 2

VL

PC54

0.1U_0603_25V7K~D

PR59

1 2

2.2_0603_5%~D

PC57

0.1U_0603_25V7K~D

1 2

0.1U_0603_25V7K~D

BST3A

LX3

DL3

FB3

VL

1 2

PU5

33

TP

26

DRVH2

24

VBST2

25

LL2

23

DRVL2

30

VOUT2

32

REFIN2

1 2

PC55

3

6

VIN

V5FILT

2VREF_TPS51427

1 2

PC64 0.22U_0603_10V7K~DPC64 0.22U_0603_10V7K~D

EN_LDO

PC65

0.22U_0603_25V7K~D

1 2

VL

PR72

1 2

806K_0603_1%

12

TPS51427_EN1

PR70

@PR70

@ 0_0402_5%~D

0_0402_5%~D

PR74

@PR74

@

47K_0402_5%~D

1 2

12

PC67

PC68

@

0.047U_0402_16V7K~N

0.047U_0603_16V7K~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

TPS51427_EN2

1 2

12

2VREF_TPS51427

1

VREF2

8

LDOREFIN

20

NC

4

EN_LDO

14

EN1

27

EN2

TONSE

VREF3

2

5

PR71

0_0402_5%~D

12

@

PC66

1U_0603_10V6K~D

2009/07/29 2010/07/29

3

@

0_0402_5%~D

2VREF_TPS51427

12

PC56

1U_0603_10V6K~D

7

4.7U_0805_6.3V6K~D

19

LDO

V5DRV

15

DRVH1

17

VBST1

16

LL1

18

DRVL1

22

PGND

10

VOUT1

11

FB1

9

VSW

29

SKIPSEL

28

PGOOD2

13

PGOOD1

12

TRIP1

31

TRIP2

GND

TPS51427_QFN32_5X5

21

PR75

Compal Secret Data

Deciphered Date

PC59

1U_0603_10V6K~D

1 2

DH5DH3

PR60

BST5A

1 2

2.2_0603_5%~D

2.2_0603_5%~D PC61

PC61

0.1U_0603_25V7K~D

LX5

DL5

FB5

PR64 0_0402_5%~D@ PR64 0_0402_5%~D@

PR65 0_0402_5%~DPR65 0_0402_5%~D

1 2

PR68

210K_0402_1%~D

ILM1

ILIM2

255K_0402_1%~D

5VALWP Thermai Design Current=6.88A OCP min=9A Fsw=400K

Rds(on) = 11.5m ohm(max) ; Rds(on) = 9m ohm(typical)

PR69

578

PQ18

3 6

241

SI4686DY-T1-E3_SO8

8

D6D5D7D

4

1 2

12

2

PQ20

G

S

3

2

1

FDS6670AS_1N_SO8

VL

B+

PL22

D D

+3VALWP

PC60

330U_D_6.3VM_R18M~D

C C

B B

1 2

FBMA-L18-453215-900LMA90T_1812

PC84

0.1U_0603_25V7K~D

1

12

+

2

PC79

0.1U_0402_10V7K~D

PR57

0_0402_5%~D

1 2

PR62

@

1 2

10K_0402_1%~D

VS

12

PC48

4.7U_1206_25V6K~D

1 2

2.2UH_MPLC1040L2R2_11A_20%~D

12

PC49

4.7U_1206_25V6K~D

PL4

PD10

RLZ5.1B_LL34

1 2

PC50

12

2200P_0402_50V7K~D

PR56

4.7_1206_5%~D

PC58

680P_0603_50V7K~D

3.3VALWP Thermal Design Current=8.5A OCP min=11A Fsw=300K

Rds(on) = 11.5m ohm(max) Rds(on) = 9m ohm(typical)

PJP5

PJP5 JUMP_43X118@

JUMP_43X118@

+5VALWP

A A

+3VALWP

112

PJP7

PJP7 JUMP_43X118@

JUMP_43X118@

112

PJP11

PJP11 JUMP_43X118@

JUMP_43X118@

112

PJP9

PJP9 JUMP_43X118@

JUMP_43X118@

112

5

2

+5VALW

+3VALW

2

1 3

PD11

1 2

1SS355TE-17_SOD323-2

A

+1.05VSP Thermal Desig Current=5.7A OCP min=7.5A Fsw=300KHz

1 1

PR77

0_0402_5%~D

SUSP#<28,31,33,52,53,54>

PR80

PR80 300_0603_5%~D

300_0603_5%~D

1 2

+5VS

2 2

12

PR79

30.1K_0402_1%~D

12

PC76

1U_0603_10V6K~D

12

@PC72

@

.1U_0402_16V7K~D

12

PC72

PC78

@PC78

@

47P_0402_50V8J~D

12

TON_VCCP

V5FILT_VCCP FB_VCCP

2 3 4 5 6

EN_VCCP

PU6

TON VOUT V5FILT VFB PGOOD

B

PR76

267K_0402_1%~D

1 2

15

1

TP

EN_PSV

GND7PGND

PR78

BST_VCCP

1 2 0_0603_5%~D

0_0603_5%~D

14

DRVH

TRIP

DRVL

UG_VCCP

13

LX_VCCP

12

LL

TRIP_VCCP

11

V5DRV_VCCP

10

LG_VCCP

9

VBST

V5DRV

TPS51117RGYR_QFN14_3.5x3.5

8

1 2

PC71 0.1U_0603_25V7K~DPC71 0.1U_0603_25V7K~D

PR81

1 2

10K_0402_1%~D

+5VS

12

PR82

PR82 0_0603_5%~D

0_0603_5%~D

12

PC77

4.7U_0805_10V6K~D

C

4

578

G

VCCP_B++

3 6

241

D6D5D7D

S

3

2

PQ22

PQ22 SI4686DY-T1-E3_SO8

SI4686DY-T1-E3_SO8

8

PQ23

S

FDS6670AS_1N_SO8

1

12

PC69

10U_1206_25V6M~D

12

PR83

4.7_1206_5%~D

4.7_1206_5%~D 12

PC75

680P_0603_50V7K~D

12

2.2UH_MPLC1040L2R2_11A_20%~D

PC70

10U_1206_25V6M~D

PL6

1 2

12

PC86

PC85

0.1U_0603_25V7K~D

12

2200P_0402_50V7K~D

D

PAD-OPEN 4x4m

1

+

PC73

2

220U_D2_4VM

PJP20

@PJP20

@

PC74

12

4.7U_0805_6.3V6K~D

B+

+1.05VSP

12

PC81

0.1U_0402_10V7K~D

12

PR84

8.66K_0402_1%~D

12

PR85

21.5K_0402_1%~D

+1.8VSP Thermal Desig Current=2.5A OCP min=3.3A Fsw=300KHz

PR210

267K_0402_1%~D

EN_1.8VSP

PU18

2 3 4 5 6

TON VOUT V5FILT VFB PGOOD

1 2

1

EN_PSV

GND7PGND

B

BST_1.8VSP

1 2 0_0603_5%~D

0_0603_5%~D

14

15

TP

VBST

13

DRVH

12

LL

11

TRIP

10

V5DRV

9

DRVL

TPS51117RGYR_QFN14_3.5x3.5

8

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PR212

UG_1.8VSP LX_1.8VSP TRIP_1.8VSP V5DRV_1.8VSP LG_1.8VSP

Issued Date

1 2

PC203 0.1U_0603_25V7K~DPC203 0.1U_0603_25V7K~D

PR216

1 2

5.11K_0402_1%~D

+5VS

12

PR215

PR215 0_0603_5%~D

0_0603_5%~D

12

PC208

4.7U_0805_10V6K~D

Compal Secret Data

2009/07/29 2010/07/29

Compal Secret Data

3 3

SUSP#<28,31,33,52,53,54>

1 2

+5VS

PJP10

@PJP10

@

JUMP_43X118

+1.05VSP

4 4

+1.8VSP

112

PJP25

@PJP25

@

JUMP_43X118

112

PJP28

@PJP28

@

JUMP_43X118

112

2

A

0_0402_5%~D

30.1K_0402_1%~D

PR214

PR214 300_0603_5%~D

300_0603_5%~D

+1.05VS

+1.8VS

PR211

12

PR213

12

PC207

1U_0603_10V6K~D

20.5K_0402_1%~D

12

@PC204

@

.1U_0402_16V7K~D

12

PR219

12

PC204

PC210

@PC210

@

47P_0402_50V8J~D

12

PR218

28.7K_0402_1%~D

TON_1.8VSP

V5FILT_1.8VSP FB_1.8VSP

12

578

3 6

578

PQ49

3 6

Deciphered Date

C

1.8VSP_B++

PQ48

PQ48 FDS8884_SO8

FDS8884_SO8

241

PR217

FDS6690AS_1N_SO8

PC209

12

PC199

10U_1206_25V6M~D

12

4.7_1206_5%~D

4.7_1206_5%~D 12

680P_0603_50V7K~D

PC200

10U_1206_25V6M~D

12

PC201

PC202

0.1U_0603_25V7K~D

PL14

12

Title

Size Document Number Rev

Custom

Date: Sheet

12

3.3UH_MPL73-3R3_6A_20%~D

12

2200P_0402_50V7K~D

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

PAD-OPEN 4x4m

1

+

PC205

2

220U_D2_4VM

D

PJP27

@PJP27

@

12

PC206

0.1U_0402_10V7K~D

B+

+1.8VSP

A

of

51 57Monday, September 21, 2009

A

PL23

B+

1 1

2 2

1 2

FBMA-L18-453215-900LMA90T_1812

12

PC211

0.1U_0603_25V7K~D

PR225

0_0402_5%~D

SYSON<28,31,33>

1 2

12

PC213

PC212

2200P_0402_50V7K~D

12

PC217

@PC217

@

0.1U_0603_25V7K~D

12

10U_1206_25V6M~D

@

PC222

PC222 .1U_0402_16V7K~D

.1U_0402_16V7K~D

PC214

10U_1206_25V6M~D

PR222

0_0603_5%~D

6268_1.5VP

12

PC218

2.2U_0603_6.3V6K~D

6268_1.5VP_B+

6268_1.5VP

1.5V_PWRGD<6>

12

PC224

68P_0402_50V8J~D

B

PR220

10K_0402_1%~D

8

GND

3

VIN

4

VCC

5

EN

COMP6FB7FSET

12

PR228

PR228 33K_0402_1%~D

33K_0402_1%~D

12

PC227

2200P_0402_50V7K~D

12

1

2

PHASE

PGOOD

9

12

PR229

45.3K_0402_1%~D

PHASE_1.5VP

BOOT_1.5VP

16

15

UG

BOOT

PVCC

PGND

VO

10

12

PR221

1 2

0_0603_5%~D

+5VALW

12

14

2.2U_0603_6.3V6K~D

13

LG

12

ISEN_1.5VP

11

ISEN

3.01K_0402_1%~D

PU19

PU19 ISL6268CAZ-T_SSOP16

ISL6268CAZ-T_SSOP16

PC228

0.01U_0402_25V7K~D

UG_1.5VP

1 2

PC215

0.1U_0603_25V7K~D

PR223

0_0603_5%~D

PR224 4.7_0603_5%~DPR224 4.7_0603_5%~D

6268_1.5VP

1 2

PC216

1 2

LG_1.5VP

PR226

1 2

C

1.5VP Thermal Design Current=12.8A OCP min=16A Fsw=300KHz

PQ50

PQ50 FDMS8692_POWER56-8-5~D

FDMS8692_POWER56-8-5~D

PL15

3 5

241

PQ51

4

PQ51

4

123 5

FDMS8670S-T1-E3_SO8

1UH_FDUE1040D-1R0M-P3_21.3A_20%

PQ52

123 5

FDMS8670S-T1-E3_SO8

1 2

12

PR227

4.7_1206_5%~D

12

PC223

680P_0603_50V7K~D

PL15

PR230

1.5K_0402_1%~D

1.5K_0402_1%~D 1 2

D

+1.5VP

PC219

PC225

10U_0805_6.3V6M~D

330U_Y_2.5VM

+1.5VP

12

10U_0805_6.3V6M~D

330U_Y_2.5VM

1

+

2

12

PC221

0.1U_0402_10V7K~D

12

PC220

1

+

PC226

2

12

PR231

1K_0402_1%~D

3 3

PU10

RT9026_MSOP10

PJP18

@PJP18

@

+1.5VP

+0.75VSP

PC141

PJP22

@PJP22

@ JUMP_43X118

JUMP_43X118

2

4 4

+1.5VP

+0.75VSP

112

PJP35

@PJP35

@ JUMP_43X118

JUMP_43X118

112

PJP21

@PJP21

@

2 1

PAD-OPEN 2x2m~D

A

+1.5V

2

+0.75VS

2

112

JUMP_43X118

12

10U_0805_10V6K~D

PC142

10U_0805_10V6K~D

PC138

12

PC139

@

4.7U_0805_6.3V6K~D

B

RT9026_MSOP10

1

VDDQSNS

2

VLDOIN

3

VTT

5

VTTSNS

4

10

VIN

PC140

8

GND

6

VTTREF

PR130

9

S5

7

S3

PGND

GND

11

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

PR130

0_0402_5%~D

PR131

@PR131

@ 0_0402_5%~D

0_0402_5%~D

PC144

@PC144

@

.1U_0402_16V7K~D

2009/07/29 2010/07/29

12

PC140

1U_0603_10V6K~D

12

PC143

0.1U_0402_16V7K~D

1.5VS_DDR_PWRGD <33>

SUSP# <28,31,33,51,53,54>

Compal Secret Data

Deciphered Date

C

+3VALW

12

+0.75VSP Thermal Design Current:0.7A Peak current:1A Vout=VDDQSNS/2=1.5V/2=0.75V

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

D

of

52 57Monday, September 21, 2009

A

5

PL21

1 2

B+

FBMA-L18-453215-900LMA90T_1812

D D

12

PC231

PC230

PC229

2200P_0402_50V7K~D

0.1U_0603_25V7K~D

PR237

0_0402_5%~D

C C

SUSP#<28,31,33,51,52,54>

1 2

PC231

12

PC235

@PC235

@

0.1U_0603_25V7K~D

@

12

10U_1206_25V6M~D

PC240

PC240 .1U_0402_16V7K~D

.1U_0402_16V7K~D

12

PC286

PC232

10U_1206_25V6M~D

PR234

0_0603_5%~D

6268_1.1VS_VTTP

12

PC236

2.2U_0603_6.3V6K~D

10U_1206_25V6M~D

12

6268_1.1VS_VTTP_B+

H_VTTPWRGD<6>

12

PC242

4

6268_1.1VS_VTTP

68P_0402_50V8J~D

10K_0402_1%~D

3

VIN

4

VCC

5

EN

12

PC245

2200P_0402_50V7K~D

12

PR232

2

8

GND

COMP6FB7FSET

PR240

PR240 33K_0402_1%~D

33K_0402_1%~D

45.3K_0402_1%~D

PGOOD

PR241

1

PHASE

PHASE_1.1VS_VTTP

BOOT_1.1VS_VTTP

15

16

UG

BOOT

PVCC

PGND

ISEN

VO

9

10

12

PC246

0.01U_0402_25V7K~D

PR233

1 2

2.2_0603_5%~D

2.2_0603_5%~D +5VS

12

14

2.2U_0603_6.3V6K~D

13

LG

12

ISEN_1.1VS_VTTP

11

4.75K_0402_1%~D

PU20

PU20 ISL6268CAZ-T_SSOP16

ISL6268CAZ-T_SSOP16

3

UG_1.1VS_VTTP

1 2

PC233

0.1U_0603_25V7K~D

PR235

0_0603_5%~D

PR236 4.7_0603_5%~DPR236 4.7_0603_5%~D

1 2

PC234

1 2

LG_1.1VS_VTTP

1 2

PR238

6268_1.1VS_VTTP

2

1.1VS_VTTP Thermal Design Current=15A OCP min=20A Fsw=300KHz

PQ53

PQ53 FDMS8692_POWER56-8-5~D

FDMS8692_POWER56-8-5~D

PL16

PC241

12

680P_0603_50V7K~D

PL16

1 2

PR239

4.7_1206_5%~D

1.5K_0402_1%~D

PR242

+1.1VS_VTTP

12

PR305

10_0402_5%~D

1 2

12

PC238

PC237

10U_0805_6.3V6M~D

1

+

PC243

PC244

2

330U_Y_2.5VM

3 5

241

PQ54

4

123 5

FDMS8670S-T1-E3_SO8

1UH_FDUE1040D-1R0M-P3_21.3A_20%

PQ55

123 5

FDMS8670S-T1-E3_SO8

10U_0805_6.3V6M~D

330U_Y_2.5VM

1

+1.1VS_VTTP

12

PC239

0.1U_0402_10V7K~D

1

+

2

12

PR243

2K_0402_1%~D

B B

PJP31

PJP31 JUMP_43X118@

JUMP_43X118@

+1.1VS_VTTP

A A

5

112

PJP32

PJP32 JUMP_43X118@

JUMP_43X118@

112

PJP33

PJP33 JUMP_43X118@

JUMP_43X118@

112

2

+1.1VS_VTT

H_VTTVID1 = "High" , Vo = 1.05V H_VTTVID1 = "Low" , Vo = 1.1V

PR250

H_VTTVID1<8>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

PR250

1 2

10K_0402_5%~D

2009/07/29 2010/07/29

PR248

PR248 10K_0402_5%~D

10K_0402_5%~D

1 2

12

PC248

1 2

.01U_0402_16V7K~D

Compal Secret Data

Deciphered Date

+3VS

PQ57

2

G

PR251

PR251 100K_0402_5%~D

100K_0402_5%~D

PR246

PR246 10K_0402_5%~D

10K_0402_5%~D

1 2

13

D

10K_0402_5%~D

SSM3K7002FU_SC70-3

S

2

PR249

PR247

17.8K_0402_5%~D

1 2

PQ56

13

D

2

G

SSM3K7002FU_SC70-3

S

PC247

0.068U_0402_16V7K~D

1 2

Title

Size Document Number Rev

Custom

401808

Date: Sheet of

Date: Sheet

PR244

1 2

0_0402_5%~D

@

PR245

1 2

17.8K_0402_5%~D

Compal Electronics, Inc.

SCHEMATICS, MB A5155

1

VTT_SENSE <8>

H_VTTVID1 <8>

53 57Monday, September 21, 2009

A

of

5

PL20

1 2

B+

FBMA-L18-453215-900LMA90T_1812

12

PC100

10U_1206_25V6K~D

0_0603_5%~D

12

1

PC117

2

.01U_0402_16V7K~D

12

PC180 @ PC180

@

.1U_0402_16V7K~D

12

PC118

10U_1206_25V6K~D

PR109

PC104

2.2U_0603_6.3V6K~D

12

PR124

8.87K_0402_1%~D

PQ33

13

D

2

G

S

+5VS

12

PC182

10U_1206_25V6M~D

12

PC99

PC186

PC187

2200P_0402_50V7K~D

10U_1206_25V6K~D

PR111

PR127

10U_1206_25V6K~D

12

@PC103

@

0.1U_0603_25V7K~D

12

PR129

PJP26

@PJP26

@

JUMP_43X118

112

1 2

PR194

0_0402_5%~D

PC103

@

PC110

.1U_0402_16V7K~D

100K_0402_5%~D

2

0.1U_0603_25V7K~D

SUSP#<28,31,33,51,52,53>

0.1U_0603_25V7K~D

0_0402_5%~D

1 2

+3VS

PR126

10K_0402_5%~D

1 2

10K_0402_5%~D

+1.5VP

D D

VGA_ON<31>

C C

GPU_VID0<39>

B B

A A

+1.1VSP Imax=0.91A Vout=0.8*(PR196+PR195)/PR195=0.8*(1k+2.61k)/2.61k=1.107V

5

4

12

VIN_VGA

6268_VGA

EN_VGA

12

PC111

SSM3K7002FU_SC70-3

5

PU15 RT9025PU15 RT9025

NC

VIN3VOUT

2

EN

4

PGOOD

VDD

GND

9

12

PC179

PC179 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

4

COMP_VGA

33P_0402_50V8J~D

ADJ

8

6268_VGA

10K_0402_1%~D

PU9

3

VIN

4

VCC

5

EN

12

PR116

12.1K_0402_1%~D

12

PC113

2200P_0402_50V7K~D

0_0402_5%~D

PC115

@PC115

@

820P_0402_50V7K~D

6

7

1

PR209

1 2

100K_0402_1%~D

+3VS

1.1VS_RUN_PWRGD

3

VGA_B++

12

PR106

2

8

GND

ISL6268CAZ-T_SSOP16

COMP6FB7FSET

PR121

PD18

@PD18

@

1 2

1SS355TE-17_SOD323-2

12

PHASE_VGA

UG_VGA

PR107

1 2

2.2_0603_5%~D

BOOT_VGA

1

PGOOD

PR117

45.3K_0402_1%~D

12

10K_0402_5%~D

12

PC181 @ PC181

@

.1U_0402_16V7K~D

12

PR195

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

15

16

UG

PHASE

9

10

FSET_VGA

12

PR90

@PR90

@

PR91

@

12

PR196

1K_0402_1%~D

<39>

2.61K_0402_1%~D

BOOT

14

PVCC

13

LG

12

PGND

11

ISEN

VO

PC112

0.01U_0402_25V7K~D

+3VS

@PR92

@

18.2K_0402_1%~D

1 2

1

12

2

@

100K_0402_5%~D

12

PC176

10U_1206_25V6M~D

PC198

1 2

PC101 0.1U_0603_25V7K~DPC101 0.1U_0603_25V7K~D

+5VS

12

PR108

PR108 0_0603_5%~D

0_0603_5%~D

PR110

4.7_0603_5%~D

1 2

PVCC_VGA

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D LG_VGA

ISEN_VGA

1 2

PR113

7.15K_0402_1%~D

PR92

2

G

.01U_0402_16V7K~D

+1.1VSP

12

PC178

2009/07/29 2010/07/29

3

6268_VGA

PC102

1 2

12

PQ47

@

PQ47

@

13

D

SSM3K7002FU_SC70-3

S

PD17

@PD17

@

1SS355TE-17_SOD323-2

GPU_VID1<39>

10U_1206_25V6M~D

+1.1VSP

4

123 5

+3VS

1 2

12

PJP36

@PJP36

@

2 1

PAD-OPEN 2x2m~D

Compal Secret Data

Deciphered Date

4

123 5

PQ30

4

FDMS8670S-T1-E3_SO8

PR123

10K_0402_5%~D

PR125

10K_0402_5%~D

PR128

2

PQ29

4

FDMS8692_POWER56-8-5~D

PQ31

123 5

FB_VGA

12

100K_0402_5%~D

+1.1VS

2

+VGA_COREP Thermal Design Current=24A OCP min=31A Fsw=300KHz

0.9V 1V 1.1V GPU_VID_0 0 1 0 1 GPU_VID_1 0 0 1 1

PQ34

FDMS8670S-T1-E3_SO8

1

2

123 5

0.36UH_FDUE1030D-R36M=P3 32A_20%

FDMS8692_POWER56-8-5~D

4.7_1206_5%~D

1 2 12

PC109

680P_0603_50V7K~D

PR122

8.87K_0402_1%~D

2

G

PC116

.01U_0402_16V7K~D

PL9

1 2

PR112

12

PR119

PR119 0_0402_5%~D

0_0402_5%~D

12

PC114

@PC114

@

820P_0402_50V7K~D

13

D

PQ32

PQ32 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

+GPU_COREP

Title

Size Document Number Rev

Custom

401808

Date: Sheet

Date: Sheet of

1

+GPU_COREP

1

+

2

330U_Y_2VM

PC107

1

+

2

330U_Y_2VM

1 2

PR120

+GPU_CORE

54 57Monday, September 21, 2009

PC108

4.7U_0805_6.3V6K~D

PC195

12

1

+

PC105

PC106

2

12

330U_Y_2VM

PR114

PR114 10_0402_1%~D

10_0402_1%~D

1 2

PR118

1.5K_0402_1%~D

3.01K_0402_1%~D

Compal Electronics, Inc.

SCHEMATICS, MB A5155

12

10U_0603_6.3V6M~D

of

12

PC83

0.1U_0402_10V7K~D

PC196

1 2

10U_0603_6.3V6M~D

A

8

H H

CPU_VID0<8> CPU_VID1<8> CPU_VID2<8> CPU_VID3<8> CPU_VID4<8> CPU_VID5<8> CPU_VID6<8>

G G

H_DPRSLPVR<8>

CLK_ENABLE#<13>

F F

E E

12

PR278

249K_0402_1%~D

@ PR278

@

D D

150P_0402_50V8J~D

Layout Note: PH3 place near Phase1 L-MOS

+CPU_CORE

C C

VCCSENSE<8>

B B

VSSSENSE<8>

PR252 0_0402_5%~DPR252 0_0402_5%~D PR253 0_0402_5%~DPR253 0_0402_5%~D PR254 0_0402_5%~DPR254 0_0402_5%~D PR255 0_0402_5%~DPR255 0_0402_5%~D PR256 0_0402_5%~DPR256 0_0402_5%~D PR257 0_0402_5%~DPR257 0_0402_5%~D PR258 0_0402_5%~DPR258 0_0402_5%~D

PR260 0_0402_5%~DPR260 0_0402_5%~D

VR_ON<31,39>

PR261 499_0402_1%~DPR261 499_0402_1%~D

+3VS

PR269

PR269 0_0402_5%~D

0_0402_5%~D

VGATE<13,17,31>

1 2

PR272

1 2

147K_0402_1%~D

+1.1VS_VTT

H_PROCHOT#<6>

PC259 56P_0402_50V8~D@PC259 56P_0402_50V8~D@

1 2

PR276 4.02K_0402_1%~DPR276 4.02K_0402_1%~D

1 2

470K_0402_5%_ERTJ0EV474J~D

12

PR279

8.06K_0402_1%~D

1 2

PC264

10P_0402_50V8J~D

1 2

PC265

412K_0402_1%~D

PR289 10_0402_5%~DPR289 10_0402_5%~D

PR292 0_0402_5%~DPR292 0_0402_5%~D

PR265

1.91K_0402_1%~D

12

+1.1VS_VTT

H_PSI#<8>

PR273 68_0402_5%~DPR273 68_0402_5%~D

PR274 0_0402_5%~DPR274 0_0402_5%~D

PH4

PC261

562_0402_1%~D

1 2

1000P_0402_50V7K~D

3.4K_0402_1%~D

3.4K_0402_1%~D 1 2

ISEN2 ISEN1

PR285

1 2

PR302 0_0402_5%~DPR302 0_0402_5%~D

1 2

1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2

PR268

10K_0402_5%~D

PR270 100K_0402_5%~D@PR270 100K_0402_5%~D@

1 2

PR271 0_0402_5%~DPR271 0_0402_5%~D

1 2

12

22P_0402_50V8J~D

PR280

1 2

390P_0402_50V7K~D

PR282

PR284 0_0402_5%~DPR284 0_0402_5%~D

1 2 1 2

PR286 0_0402_5%~DPR286 0_0402_5%~D

330P_0402_50V7K~D

1000P_0402_50V7K~D

PR303 10_0402_5%~DPR303 10_0402_5%~D

1 2

PC263

1 2

H_PROCHOT#_R

PC260

12

PC266

0.22U_0402_10V6K~D

PC279

PC281

7

CLK_ENABLE#

PU21

1

PGOOD

2

PSI#

3

RBIAS

4

VR_TT#

5

NTC

6

VW

7

COMP

8

FB

9

ISEN3

10

ISEN2

41

AGND

12

PC267

0.22U_0402_10V6K~D

12

1200P_0402_50V7K~D

39

40

CLK_EN#

ISEN111VSEN12RTN13ISUM-14ISUM+15VDD

PC282

330P_0402_50V7K~D

PC284

@PC284

@

38

VR_ON

DPRSLPVR

PR290

37

12

1 2

35

16

12

82.5_0402_5%~D

VID4

VIN

17

PC280

PR298

1.15K_0402_1%~D

1 2

@PR304

@ 100_0402_1%~D

100_0402_1%~D

VID031VID132VID233VID334VID536VID6

30

BOOT2

29

UGATE2

28

PHASE2

27

VSSP2

26

LGATE2

25

VCCP

24

PWM3

23

LGATE1

22

VSSP1

21

PHASE1

ISL62883HRZ-T_QFN40_5X5~D

IMON18BOOT119UGATE1

20

PR283 0_0402_5%~DPR283 0_0402_5%~D

1 2

PR287 1_0402_5%~DPR287 1_0402_5%~D

1 2

12

PC269

PC268

1U_0603_10V6K~D

0.22U_0603_25V7K~D

12

PC276

2700P_0402_50V7K~D

.01U_0402_16V7K~D

PR304

6

OCP calculation: Assume DCR=0.88mOhm G1=Rn/(Rn+Rsum/3), where Rn=PR224//(PR171+PH5); Rsum=PR143,PR215 DROOP=2*(DCR/2)*G1*Rdroop/Ri=1.896mOhm where Rdroop=PR161;Ri=PR212 Iocp=42.7u*Rdroop/DROOP=~68A.

PC258

PC258 1U_0603_10V6K~D

1U_0603_10V6K~D

1 2

PR275

PR275 0_0402_5%~D

PR277 0_0402_5%~DPR277 0_0402_5%~D

1 2

12

PC262

1U_0603_10V6K~D

+CPU_B+

+5VS

11.5K_0402_1%~D

VSSSENSE

PC278

PC277

0.33U_0603_10V7K

PR299

0_0402_5%~D

PR288

12

0.047U_0603_25V7K~D

12

PR300

12

PC285

0_0402_5%~D

1 2

PR281 0_0402_5%~DPR281 0_0402_5%~D

1 2

IMVP_IMON<8>

12

PC270

0.033U_0603_25V7K~D

VSUM+

12

PR293

2.87K_0402_1%~D

12

PH5

PH5 10K_0603_1%_ERTJ1VG103FA~D

10K_0603_1%_ERTJ1VG103FA~D

1 2

Layout Note:

11K_0402_1%~D

Place near Phase1 Choke

5

0_0603_5%~D

BOOT2 BOOT2_2

VSUM-

0_0603_5%~D

+5VS

BOOT1

UGATE1

PHASE1

LGATE1

PR259

12

PR291

PR291 0_0603_5%~D

0_0603_5%~D

LGATE2

0.22U_0603_10V7K~D

1 2

UGATE2

BOOT1_1

12

4

PC256

PC275

0.22U_0603_10V7K

1 2

3

+CPU_B+

12

3

D

2

G

S

1

3

D

2

G

S

1

2

G

2

G

3

D

2

PQ58

FDMS8692_POWER56-8-5~D

PQ59

FDMS8670S_ POWER56-8~D

3

D

S

1

3

D

S

1

2

PQ61

PQ62

PQ64

G

S

1

FDMS8692_POWER56-8-5~D

PHASE2

3

D

G

S

1

PQ60

FDMS8670S_ POWER56-8~D

3

D

2

PQ65

G

S

1

FDMS8692_POWER56-8-5~D

2

FDMS8670S_ POWER56-8~D

FDMS8692_POWER56-8-5~D

3

D

G

S

1

PQ63

FDMS8670S_ POWER56-8~D

12

PC251

PC249

0.1U_0603_25V7K~D

PR262

4.7_1206_5%~D

PC257

680P_0603_50V7K~D

PC271

0.1U_0603_25V7K~D

PC283

PC251

PC250

10U_1206_25V6K~D

2200P_0402_50V7K~D

12

PR263

3.65K_0603_1%~D

12

VSUM+

ISEN2

12

PC273

PC272

10U_1206_25V6K~D

2200P_0402_50V7K~D

12

PR294

PR295

4.7_1206_5%~D

12

3.65K_0603_1%~D

680P_0603_50V7K~D

VSUM+

2

12

PC287

PC252

10U_1206_25V6K~D

PL18

0.36UH_ETQP4LR36AFC_28A_20%~D

0.36UH_ETQP4LR36AFC_28A_20%~D 4 3

PR267

@ PR267

@

PR266

0_0402_5%~D

1 2

10K_0402_5%~D

+CPU_B+

12

PC274

10U_1206_25V6K~D

PL19

0.36UH_ETQP4LR36AFC_28A_20%~D

0.36UH_ETQP4LR36AFC_28A_20%~D 4 3

12

PR296

10K_0402_5%~D

ISEN1

PL17

FBMA-L18-453215-900LMA90T_1812~D

1 2

1

+

PC253

2

100U_25V_M~D

1 2

PR301

@ PR301

@ 0_0402_5%~D

0_0402_5%~D

1 2

V1N

1

+

PC255

PC254

@

2

100U_25V_M~D

Iccmax= TBD I_TDC=TDB OCP=68A, Intel spec=TDB

V2N

VSUM-

V1N

12

V2N

VSUM-

+CPU_CORE

12

PR264

PR264 1_0402_5%~D

1_0402_5%~D

+CPU_CORE

PR297

PR297 1_0402_5%~D

1_0402_5%~D

1

B+

.1U_0402_16V7K~D

A A

8

7

6

.1U_0402_16V7K~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

2009/07/29 2010/07/29

Compal Secret Data

Deciphered Date

3

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet

2

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

55 57Monday, September 21, 2009

of

1

A

5

4

3

2

1

Battery Connect/OTP

+3VALWP

D D

2

PD13

@

DA204U_SOT323~D

BATT_SMC

PR177

1K_0402_5%~D

3

1

@

PD14

DA204U_SOT323~D

2

3

1

Place clsoe to EC pin

BATT_TEMP

1 2

PR176

1K_0402_5%~D

1 2

12

1 2

PR178

6.49K_0402_1%~D

2

3

PD12

@

PR179

PR180

1 2

@

PR175

PR175 1K_0402_5%~D

1K_0402_5%~D

DA204U_SOT323~D

BATT_B/I

1

BATT_SMD

EC_SMB_DA1 <31>

EC_SMB_CK1 <31>

BATT+

PL13

FBMA-L18-453215-900LMA90T_1812~D

BATT+

12

PC161

100P_0402_50V8J~D

PJPB1 battery connector

SMART Battery:

C C

9.BAT+

8.BAT+

7.ID

6.B/I

5.TS

4.SMD

3.SMC

2.GND

1.GND

PL13

1 2

PC163

0.01U_0402_25V7K~D

SUYIN_200275MR009F50PZR~D

BATT++

12

PC162

PC162 1000P_0402_50V7K~D

1000P_0402_50V7K~D

GND GND

PJPB1

9 8 7 6 5 4 3 2 1

BATT++

12

PC164

100P_0402_50V8J~D

11 10 9 8 7 6 5 4 3 2 1

1 2

100_0402_5%~D

1 2

100_0402_5%~D

2

3

PD15

@

DA204U_SOT323~D

1

BATT_TEMP <31>

PC165

@PC165

@

.1U_0402_16V7K~D

+3VALWP

1000P_0402_50V7K~D

PC168

PH3 under CPU botten side :

CPU thermal protection at 90 +-3 degree C Recovery at 50 +-3 degree C

VL VS

12

CPU

12

PR182

10.7K_0402_1%~D

PR186

61.9K_0402_1%~D

OTP_IN OTP_IN+

61.9K_0402_1%~D

1 2

VL

PR188

12

PH3

PH3 100K_0402_1%_TH11-4H104FT

100K_0402_1%_TH11-4H104FT

PR188

150K_0402_1%~D

PR190

PR184

147K_0402_1%~D

1 2

OTP_IN-

12

8

3

P

+

0

2

-

G

PU12A

4

LM358ADR_SO8

PC169

PC169 1U_0603_10V6K~D

1U_0603_10V6K~D

PC166

0.1U_0603_25V7K~D

1 2

OTP_OUT

1

1 2

1SS355TE-17_SOD323-2

PD16

VL

PR185

PR185 205K_0402_1%~D

205K_0402_1%~D

1 2

MAINPWON <20,39,50>

BATT+

12

PR181

PR181 453K_0402_1%~D

0.01U_0402_25V7K~D

4

453K_0402_1%~D

12

PR183

499K_0402_1%~D

BATT_IN

12

PR189

86.6K_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/07/29 2010/07/29

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A5155

401808

of

56 57Monday, September 21, 2009

1

56 57Monday, September 21, 2009

A

B B

BATT_OUT

BATT_OVP<31>

A A

5

1 2

PR187

10K_0402_1%~D

7

PU12B

LI-3S :13.5V----BATT_OVP=1.126V

BATT_OVP=0.08338*BATT+

0

VS

8

LM358ADR_SO8

5

P

+

6

-

G

4

12

PC167

COMPAL LA-5155P Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual