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A
TFT LCD Approval Specification
MODEL NO.: V400H1 - PH2
ʳ
ʳ
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Issued Date: Nov. 19, 2009
Model No.: V400H1 - PH2
Approval
ʳ
Customer:
pproved by:
Note:
Approved By
TVHD
CC Chung
QA Dept. Product Development Div.
Reviewed By
Hsin-nan Chen WT Lin
LCD TV Marketing and Product Management Div.
Prepared By
Josh Chi Karen Liao
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Issued Date: Nov. 19, 2009
Model No.: V400H1 - PH2
Approval
- CONTENTS -
REVISION HISTORY
1. GENERAL DESCRIPTION
1.1 OVERVIEW
1.2 CHARACTERISTICS
1.3 MECHANICAL SPECIFICATIONS
2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT (BASED ON CMO MODULE V400H1-LH9)
2.2
PACKAGE STORAGE
2.3 ELECTRICAL ABSOLUTE RATINGS (OPEN CELL)
3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD OPEN CELL
4. BLOCK DIAGRAM
4.1 TFT LCD OPEN CELL
5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD MODULE
5.2 LVDS INTERFACE
5.3 COLOR DATA INPUT ASSIGNMENT
6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
6.2 POWER ON/OFF SEQUENCE
-------------------------------------------------------
-------------------------------------------------------
-------------------------------------------------------
-------------------------------------------------------
-------------------------------------------------------
-------------------------------------------------------
-------------------------------------------------------
3
4
5
7
9
10
15
7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
7.2 OPTICAL SPECIFICATIONS
8. DEFINITION OF LABELS
8.1 OPEN CELL LABEL
8.2 CARTON LABEL
9. PACKAGING
9.1 PACKING SPECIFICATIONS
9.2 PACKING METHOD
10. PRECAUTIONS
10.1 ASSEMBLY AND HANDLING PRECAUTIONS
10.2 SAFETY PRECAUTIONS
-------------------------------------------------------
-------------------------------------------------------
-------------------------------------------------------
-------------------------------------------------------
19
22
23
25
11. MECHANICAL CHARACTERISTICS ------------------------------------------------------- 26
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Issued Date: Nov. 19, 2009
Model No.: V400H1 - PH2
Approval
REVISION HISTORY
Version Date
Ver 2.0 Nov. 19,’09 All All Tentative Specification was first issued.
Page
(New)
Section Description
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1. GENERAL DESCRIPTION
1.1 OVERVIEW
V400H1-PH2 is a 40” TFT Liquid Crystal Display cell with driver ICs and 4ch-LVDS interface. This product
supports 1920 x 1080 Full HDTV format and can display 1.07G colors (8-bit+Hi-FRC/color). The backlight
unit is not built-in.
1.2 CHARACTERISTICS
CHARACTERISTICS ITEMS SPECIFICATIONS
Screen Diagonal [in] 40
Pixels [lines] 1920 x 1080
Active Area [mm] 885.6(H) x 498.15 (V) (40” diagonal)
Sub -Pixel Pitch [mm] 0.15375 (H) x 0.46125 (V)
Pixel Arrangement RGB vertical stripe
Weight [g] TYP. 1908
Physical Size [mm] Reference 2D Drawing
Display Mode Transmissive mode / Normally black
Contrast Ratio
Glass thickness (Array/CF) [mm] 0.7 / 0.7
Viewing Angle (CR>20)
Color Chromaticity
Cell Transparency [и]
Polarizer (CF side)
Polarizer (TFT side) Super Wide View, 1030.18(H) x 586.37(w).
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Issued Date: Nov. 19, 2009
Model No.: V400H1 - PH2
Approval
6500:1 Typ.
(Typical value measured at CMO’s module)
+88/-88(H),+88/-88(V) Typ.
(Typical value measured at CMO’s module)
R=(0.635, 0.323)
G=(0.285, 0.602)
B=(0.148, 0.056)
W=(0.280, 0.290)
(Typical value measured at CMO’s module)
4.6% Typ.
(Typical value measured at CMO’s module)
Super Wide View Glare coating, 1030.18 (H) x 586.37(w)..
Hardness: 3H
1.3 MECHANICAL SPECIFICATIONS
Item Min. Typ. Max. Unit Note
Weight 2260 2560 2860 g -
I/F connector mounting position
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
(2) Connector mounting position
The mounting inclination of the connector makes
the screen center within ±0.5mm as the horizontal.
+/- 0.5mm
4
(2)
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Issued Date: Nov. 19, 2009
Model No.: V400H1 - PH2
2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT (BASE ON CMO MODULE V400H1-LH9)
Value
Item Symbol
Min. Max.
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 50 ºC (1), (2)
Shock (Non-Operating) SNOP - 30 G (3), (5)
Vibration (Non-Operating) VNOP - 1.0 G (4), (5)
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta Љ 40 ºC).
Approval
Unit Note
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature
of display area from being over 65 ºC. The range of operating temperature may degrade in case of
improper thermal management in final product design.
Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.
Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that
the module would not be twisted or bent by the fixture.
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2.2 PACKAGE STORAGE
Storage condition: With shipping package.
Storage temperature rang: 255к
Storage humidity range: 5010%RH
Shelf life: a month
2.3 ELECTRICAL ABSOLUTE RATINGS (OPEN CELL)
Item Symbol
Min. Max.
Power Supply Voltage VCC -0.3 13.5 V
Logic Input Voltage VIN -0.3 3.6 V
Issued Date: Nov. 19, 2009
Model No.: V400H1 - PH2
Approval
Value
Unit Note
(1)
Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation
should be restricted to the conditions described under Normal Operating Conditions.
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3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD OPEN CELL
(Ta = 25 ± 2 ºC)
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Issued Date: Nov. 19, 2009
Model No.: V400H1 - PH2
Approval
Parameter Symbol
Unit Note
Min. Typ. Max.
Power Supply Voltage VCC 10.8 12 13.2 V (1)
Value
Rush Current I
White Pattern
Power Supply Current
Horizontal Stripe
Black Pattern
Differential Input High
Threshold Voltage
Differential Input Low
LVDS
interface
Threshold Voltage
Common Input Voltage VCM 1.0 1.2 1.4 V
- - 4.84 A (2)
RUSH
-
-
-
V
LVTH
V
- - -100 mV
LVTL
- 0.97 - A
- 1.72 2.236 A
- 0.44 - A
+100 - - mV
(3)
(4)
Differential input voltage |VID| 200 - 600 mV
Terminating Resistor R
- 100 - ohm
T
Input High Threshold Voltage VIH 2.7 - 3.3 V CMOS
interface
Input Low Threshold Voltage V
0 - 0.7 V
IL
Note (1) The module should be always operated within the above ranges.
Note (2) Measurement condition:
+12V
R1
1k
(Low to High)
Control Signal
SW
R2
Vcc
Q1 Si4485DY
Fuse
VR1
47k
Q2
2N7002
1k
C1
0.01uF
(LCD Module Input)
C3
1uF
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GND
Note (3) The specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 ± 2 ºC, fv = 120 Hz,
whereas a power dissipation check pattern below is displayed.
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Issued Date: Nov. 19, 2009
Model No.: V400H1 - PH2
Approval
Vcc rising time is 470us
Vcc
0.9Vcc
0.1Vcc
470us
a. White Pattern
Active Area
c. Horizontal Pattern
b. Black Pattern
Active Area
Note (4) The LVDS input characteristics are as follows:
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_
)
_
)
_
)
_
)
4. BLOCK DIAGRAM
4.1 TFT LCD OPEN CELL
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Issued Date: Nov. 19, 2009
Model No.: V400H1 - PH2
Approval
TFT LCD PANEL
(1920x3x1080)
CH1_0(+/-)
CH1_1(+/-)
CH1_2(+/-)
CH1_3(+/-)
CH1_4(+/-)
CLK(+/-
CH1
X(R) Board X(L) Board
C Board
INPUT CONNECTOR
(40550-8210,UJU(ڙࡶ)) or equivalent
CH2_0(+/-)
CH2_1(+/-)
CH2_2(+/-)
CH2_3(+/-)
CH2_4(+/-)
CLK(+/-
CH2
CH3_0(+/-)
CH3_1(+/-)
CH3_2(+/-)
CH3_3(+/-)
CH3_4(+/-)
CLK(+/-
CH3
CH4_0(+/-)
CH4_1(+/-)
CH4_2(+/-)
CH4_3(+/-)
CH4_4(+/-)
CLK(+/-
CH4
SELLVDS
VCC
GND
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5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD Module
CNF1 Connector Pin Assignment (40550-8210,UJU(ڙࡶ) or equivalent)
Pin Name Description Note
1 VCC +12V power supply
2 VCC +12V power supply
3 VCC +12V power supply
4 VCC +12V power supply
5 VCC +12V power supply
6 N.C. No Connection (1)
7 GND Ground
8 GND Ground
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Model No.: V400H1 - PH2
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9 GND Ground
10 CH1[0]- First pixel Negative LVDS differential data input. Pair 0
11 CH1[0]+ First pixel Positive LVDS differential data input. Pair 0
12 CH1[1]- First pixel Negative LVDS differential data input. Pair 1
13 CH1[1]+ First pixel Positive LVDS differential data input. Pair 1
14 CH1[2]- First pixel Negative LVDS differential data input. Pair 2
15 CH1[2]+ First pixel Positive LVDS differential data input. Pair 2
16 GND Ground
17 CH1CLK- First pixel Negative LVDS differential clock input.
18 CH1CLK+ First pixel Positive LVDS differential clock input.
19 GND Ground
20 CH1[3]- First pixel Negative LVDS differential data input. Pair 3
21 CH1[3]+ First pixel Positive LVDS differential data input. Pair 3
22 CH1[4]- First pixel Negative LVDS differential data input. Pair 4
23 CH1[4]+ First pixel Positive LVDS differential data input. Pair 4
24 GND Ground
25 CH3[0]- Third pixel Negative LVDS differential data input. Pair 0
26 CH3[0]+ Third pixel Positive LVDS differential data input. Pair 0
27 CH3[1]- Third pixel Negative LVDS differential data input. Pair 1
28 CH3[1]+ Third pixel Positive LVDS differential data input. Pair 1
29 CH3[2]- Third pixel Negative LVDS differential data input. Pair 2
30 CH3[2]+ Third pixel Positive LVDS differential data input. Pair 2
31 GND Ground
32 CH3CLK- Third pixel Negative LVDS differential clock input.
33 CH3CLK+ Third pixel Positive LVDS differential clock input.
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34 GND Ground
35 CH3[3]- Third pixel Negative LVDS differential data input. Pair 3
36 CH3[3]+ Third pixel Positive LVDS differential data input. Pair 3
37 CH3[4]- Third pixel Negative LVDS differential data input. Pair 4
38 CH3[4]+ Third pixel Positive LVDS differential data input. Pair 4
39 GND Ground
40 SCL I2C Bus
41 N.C. No Connection (1)
42 N.C. No Connection (1)
43 WP Write Protection for EEPROM
44 SDA I2C Bus
45 LVDS_SEL LVDS Data Format Selection (2)
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46 N.C. No Connection (1)
47 N.C. No Connection (1)
48 N.C. No Connection (1)
49 N.C. No Connection (1)
50 N.C. No Connection (1)
51 N.C. No Connection (1)
52 GND Ground
53 CH4[4]+ Fourth pixel Positive LVDS differential data input. Pair 4
54 CH4[4]- Fourth pixel Negative LVDS differential data input. Pair 4
55 CH4[3]+ Fourth pixel Positive LVDS differential data input. Pair 3
56 CH4[3]- Fourth pixel Negative LVDS differential data input. Pair 3
57 GND Ground
58 CH4CLK+ Fourth pixel Positive LVDS differential clock input.
59 CH4CLK- Fourth pixel Negative LVDS differential clock input.
60 GND Ground
61 CH4[2]+ Fourth pixel Positive LVDS differential data input. Pair 2
62 CH4[2]- Fourth pixel Negative LVDS differential data input. Pair 2
63 CH4[1]+ Fourth pixel Positive LVDS differential data input. Pair 1
64 CH4[1]- Fourth pixel Negative LVDS differential data input. Pair 1
65 CH4[0]+ Fourth pixel Positive LVDS differential data input. Pair 0
66 CH4[0]- Fourth pixel Negative LVDS differential data input. Pair 0
67 GND Ground
68 CH2[4]+ Second pixel Positive LVDS differential data input. Pair 4
69 CH2[4]- Second pixel Negative LVDS differential data input. Pair 4
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70 CH2[3]+ Second pixel Positive LVDS differential data input. Pair 3
71 CH2[3]- Second pixel Negative LVDS differential data input. Pair 3
72 GND Ground
73 CH2CLK+ Second pixel Positive LVDS differential clock input.
74 CH2CLK- Second pixel Negative LVDS differential clock input.
75 GND Ground
76 CH2[2]+ Second pixel Positive LVDS differential data input. Pair 2
77 CH2[2]- Second pixel Negative LVDS differential data input. Pair 2
78 CH2[1]+ Second pixel Positive LVDS differential data input. Pair 1
79 CH2[1]- Second pixel Negative LVDS differential data input. Pair 1
80 CH2[0]+ Second pixel Positive LVDS differential data input. Pair 0
81 CH2[0]- Second pixel Negative LVDS differential data input. Pair 0
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82 GND Ground
Note (1) Reserved for internal use. Please leave it open.
Note (2) High=connect to +3.3V or Open : VESA Format Ι Low= connect to GND : JEIDA Format.
Note (3) Interface optional pin has internal scheme as following diagram. Customer should keep the interface
voltage level requirement as below.
System Board Panel Board
1K ohm
Interface Voltage Level
VH > 3.0V
VL < 0.7V
IC
>20K ohm
Note (4) LVDS 4-port Data Mapping
Port Channel of LVDS Data Stream
1st Port First Pixel 1, 5, 9, ……1913, 1917
2nd Port Second Pixel 2, 6, 10, ….1914, 1918
3rd Port Third Pixel 3, 7, 11, ….1915, 1919
4th Port Fourth Pixel 4, 8, 12, ….1916, 1920
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5.2 LVDS INTERFACE
VESA Format : SELLVDS = H or Open
JEIDA Format : SELLVDS = L
ʳ
VESA Format
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Issued Date: Nov. 19, 2009
Model No.: V400H1 - PH2
Approval
Current Cycle
AR 0P
AR 0N
AR 1P
AR 1N
AR 2P
AR 2N
AR 3P
AR 3N
AR 4P
AR 4N
JEIDA Format
AR 0P
AR 0N
AR 1P
AR 1N
AR0
AG1
AB2
AR6
AR4
AG5
AG0 AR5
AB1
DE VS HS AB5 AB4 AB3 AB2
REV AB7 AB6 AG7 AG6 AR7 AR6
REV AB9 AB8 AG9 AG8 AR9 AR8AR8 REV
AG4 AR7
AB5
AB0 AG5 AG4 AG3 AG2 AG1
AB4 AG7 AG6 AG5AG9 AG8
AR4 AR3 AR2 AR1 AR0
AR6 AR5 AR4AR9 AR8
AG0
AB1
DE
REV
AG4
AB5
AR 2P
AR 2N
AR 3P
AR 3N
AR 4P
AR 4N
AR0~AR9: First Pixel R Data (9; MSB, 0; LSB)
AG0~AG9: First Pixel G Data (9; MSB, 0; LSB)
AB0~AB9: First Pixel B Data (9; MSB, 0; LSB)
DE: Data enable signal
DCLK: Data clock signal
RSV: Reserved
AB6
AR2
DE VS HS AB7 AB6AB9 AB8
REV AB3 AB2 AG3 AG2 AR3 AR2
REV AB1 AB0 AG1 AG0 AR1 AR0AR0 REV
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5.3 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 10-bit gray scale data input for
the color. The higher the binary input, the brighter the color. The table below provides the assignment of color
versus data input.
Color
Black
Red
Basic
Colors
Gray
Scale
Of
Red
Gray
Scale
Of
Green
Gray
Scale
Of
Blue
Green
Blue
Cyan
Magenta
Yellow
White
Red (0) / Dark
Red (1)
Red (2)
:
:
Red (1021)
Red (1022)
Red (1023)
Green (0) / Dark
Green (1)
Green (2)
:
:
Green (1021)
Green (1022)
Green (1023)
Blue (0) / Dark
Blue (1)
Blue (2)
:
:
Blue (1021)
Blue (1022)
Blue (1023)
Note (1) 0: Low Level Voltage, 1: High Level Voltage
R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0
0
0
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
:
:
0
0
0
0
0
0
:
:
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
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0
0
1
0
1
0
1
1
0
0
0
:
:
0
0
0
0
0
0
:
:
1
1
1
0
0
0
:
:
0
0
0
Data Signal
0
0
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
1
1
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
1
1
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
:
:
:
:
:
:
1
1
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
0
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
;
:
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
:
:
:
:
:
:
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
1
1
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
Red Green Blue
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
:
:
1
1
1
0
0
0
:
:
0
0
0
0
0
0
:
:
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
1
1
1
0
1
1
1
1
1
1
0
0
0
0
1
0
0
0
1
:
:
:
:
:
:
0
1
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
Approval
0
0
0
0
0
1
1
1
0
1
0
0
0
:
:
0
0
0
0
0
0
:
:
0
0
0
0
0
0
:
:
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
:
:
:
:
:
:
1
1
0
1
1
1
1
1
1
0
0
0
1
1
1
0
1
0
0
0
:
:
0
0
0
0
0
0
:
:
0
0
0
0
1
0
:
:
1
0
1
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6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal Item Symbol Min. Typ. Max. Unit Note
Frequency
LVDS
Receiver
Clock
LVDS
Receiver
Data
Ver t ical
Active
Display
Term
Input cycle to
cycle jitter
Spread spectrum
modulation range
Spread spectrum
modulation frequency
Setup Time Tlvsu 600 - - ps
Hold Time Tlvhd 600 - - ps
Frame Rate
Total Tv 1115 1125 1135 Th Tv=Tvd+Tvb
Display Tvd 1080 1080 1080 Th
Blank Tvb 35 45 55 Th
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Issued Date: Nov. 19, 2009
Model No.: V400H1 - PH2
F
clkin
(=1/TC)
- - 200 ps
T
rcl
clkin_mod
F
F
- - 200 KHz
SSM
Fr5 97 100 103 Hz
F
117 120 123 Hz
r6
60 74.25 80 MHz
F
-2% - F
clkin
+2% MHz
clkin
Approval
(3)
(4)
(5)
(6)
Ё
Ё
Horizontal
Active
Total Th 540 550 575 Tc Th=Thd+Thb
Display Thd 480 480 480 Tc
Ё
Display
Term
Blank Thb 60 70 95 Tc
Ё
Note (1) Since the module is operated in DE only mode, Hsync and Vsync input signals should be set to low logic
level. Otherwise, this module would operate abnormally.
Note (2) Please make sure the range of pixel clock has follow the below equation:
Fclkin(max) Њ Fr6 Ѽ Tv Ѽ Th
Fr5 Ѽ Tv Ѽ Th Њ Fclkin(min)ʳ
ʳ
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DE
T
h
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INPUT SIGNAL TIMING DIAGRAM
T
v
T
vd
Issued Date: Nov. 19, 2009
Model No.: V400H1 - PH2
Approval
T
vb
DCLK
T
hd
DE
DATA
Note (3) The input clock cycle-to-cycle jitter is defined as below figures. Trcl = I T1 – TI
Valid display data (480 clocks)
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Note (4) The SSCG (Spread spectrum clock generator) is defined as below figures.
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Issued Date: Nov. 19, 2009
Model No.: V400H1 - PH2
Approval
Note (5) The LVDS timing diagram and setup/hold time is defined and showing as the following figures.
LVDS RECEIVER INTERFACE TIMING DIAGRAM
Tc
RXCLK+/-
RXn+/-
Tlvsu
Tlvhd
1T
3T
5T
7T
9T
11T
13T
14
Note (6) (ODSEL) = H/L or open for 100/120Hz frame rate. Please refer to 5.1 for detail information.
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14
14
17
14
14
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6.2 POWER ON/OFF SEQUENCE
(Ta = 25 ± 2 ºC)
To prevent a latch-up or DC operation of LCD module, the power on/off sequence should be as the diagram
below.
0V
0.5ЉЉЉЉT1ЉЉЉЉ10ms
0ЉЉЉЉT
0ЉЉЉЉT
500ms ЉЉЉЉT
2
ЉЉЉЉ50ms
3
ЉЉЉЉ50ms
4
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0.1V
CC
T
1
T
2
Issued Date: Nov. 19, 2009
Model No.: V400H1 - PH2
Approval
0.1V
cc
T
3
T
4
LVDS Signals
0ЉЉЉЉT7ЉЉЉЉT
0ЉЉЉЉT8ЉЉЉЉT
0V
2
3
Option Signals
(SELLVDS…)
Backlight (Recommended)
500msЉЉЉЉT
100ms
ЉЉЉЉ
5
T6
Power On
T
7
VA L I D
Power Off
T
8
50%
T
5
50%
T
6
Note (1) The supply voltage of the external system for the module input should follow the definition of Vcc.
Note (2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD
operation or the LCD turns off before the backlight turns off, the display may momentarily become
abnormal screen.
Note (3) In case of Vcc is in off level, please keep the level of input signals on the low or high impedance. If T2<0,
that maybe cause electrical overstress failure.
Note (4) T4 should be measured after the module has been fully discharged between power off and on period.
Note (5) Interface signal shall not be kept at high impedance when the power is on.
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7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Item Symbol Value Unit
Ambient Temperature Ta
Ambient Humidity Ha
Supply Voltage V
Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"
Vertical Frame Rate Fr 120 Hz
7.2 OPTICAL SPECIFICATIONS
The relative measurement methods of optical characteristics are shown in 7.2. The following items should be
measured under the test conditions described in 7.1 and stable environment shown in Note (7).
Item Symbol Condition Min. Typ. Max. Unit Note
Contrast Ratio CR 4600 6500
Response Time
Center Transmittance T%
White Variation
Red
Gray to
gray
δW
Rcx
Rcy
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CC
θ
=0°, θY =0°
x
With CMO Module
Issued Date: Nov. 19, 2009
Model No.: V400H1 - PH2
Approval
o
-
C
%RH
- (2), (4)
(2)
(2), (7)
-
-
25±2
50±10
12 V
- 4.5 9 ms (5)
- 4.6 - %
- - 1.3 -
0.647
0.327
Color
Chromaticity
Green
Blue
Gcx
Gcy
Bcx
Bcy
Wcx
θ
=0°, θY =0°
x
CS-1000T
Standard light source “C”
Typ -
0.03
0.296
0.600
0.144
0.083
0.335
Typ +
0.03
-
(1),(6)
-
-
-
White
-
Deg. (2), (3)
Viewing Angle
Horizontal
Ver t ical
Wcy
θx+
-
θ
x
θY+
-
θ
Y
CR≥20
With CMO Module
0.379
80 88
80
80
80
88
88
88
-
-
-
-
Note (1) Light source is the standard light source “C” which is defined by CIE and driving voltages are based on
suitable gamma voltages. The calculating method is as followingǺ
1. Measure Module’s and BLU’s spectrums. W, R, G, B are with signal input. BLU (for V400H1-LH9) is
supplied by CMO.
2. Calculate cell’s spectrum.
3. Calculate cell’s chromaticity by using the spectrum of standard light source “C”
Note (2) Light source is the BLU which is supplied by CMO and driving voltages are based on suitable gamma
voltages.
Note (3) Definition of Viewing Angle (θx, θy):
Viewing angles are measured by Autronic Conoscope Cono-80
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T
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Issued Date: Nov. 19, 2009
Model No.: V400H1 - PH2
Approval
Normal
θx = θy = 0º
θy- θy+
θx- = 90º
6 o’clock
θy- = 90º
Note (4) Definition of Contrast Ratio (CR):
The contrast ratio can be calculated by the following expression.
Contrast Ratio (CR) = L255 / L0
L1023: Luminance of gray level 255
L 0: Luminance of gray level 0
CR = CR (1), where CR (X) is corresponding to the Contrast Ratio of the point X at Figure in Note (7).
Note (5) Definition of Gray to Gray Switching Time:
x-
θx−
y-
θx+
y+
12 o’clock direction
θy+ = 90º
x+
θx+ = 90º
100%
90%
Optical
Response
10%
0%
Gray to Gray
Switching Time
The driving signal means the signal of gray level 0, 63, 127, 191, 255.
Gray to gray average time means the average switching time of gray level 0, 63, 127, 191, 255 to each
other.
20
Gray to Gray
Switching Time
ime
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Note (6) Measurement Setup:
The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature
change during measuring. In order to stabilize the luminance, the measurement should be
executed after lighting backlight for 1 hour in a windless room.
LCD Module
LCD Panel
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Issued Date: Nov. 19, 2009
Model No.: V400H1 - PH2
Approval
CS-2000
Field of View = 1º
500 mm
Note (7) Definition of White Variation (δW):
Measure the luminance of gray level 255 at 5 points
δW = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]
D/4 D/2 3D/4
W/4
W/2
W
Vertical Line
3W/4
Light Shield Room
(Ambient Luminance < 2lux)
Horizontal Line
D
12
: Test Point
5
34
X
X=1 to 5
Active Area
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8. DEFINITION OF LABELS
8.1 OPEN CELL LABEL
The barcode nameplate is pasted on each open cell as illustration for CMO internal control.
8.2 CARTON LABEL
The barcode nameplate is pasted on each box as illustration, and its definitions are as following explanation
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Issued Date: Nov. 19, 2009
Model No.: V400H1 - PH2
Approval
V400H1-PH2
XXXXXXXXXXXXXX
(a) Model Name: V400H1– PH2
P.O. NO.
Parts ID.
Carton ID. Quantities 12
XXXXXXXXXXXXXX
Made in Taiwan
(b) Carton ID: CMO internal control
(c) Quantities: 12
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9. PACKAGING
9.1 PACKING SPECIFICATIONS
(1) 12pcs LCD TV Panels / 1 Box
(2) Box dimensions: 1108 (L) X 738 (W) X 252 (H)
(3) Weight: approximately 36 Kg
9.2 PACKING METHOD
Figures 9-1 and 9-2 are the packing method
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Issued Date: Nov. 19, 2009
Model No.: V400H1 - PH2
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Figure.9-1 packing method
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Issued Date: Nov. 19, 2009
Model No.: V400H1 - PH2
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Figure. 9-2 Packing method
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Issued Date: Nov. 19, 2009
Model No.: V400H1 - PH2
Approval
10. PRECAUTIONS
10.1 ASSEMBLY AND HANDLING PRECAUTIONS
(1) Do not apply rough force such as bending or twisting to the product during assembly.
(2) To assemble backlight or install module into user’s system can be only in clean working areas. The dust
and oil may cause electrical short or worsen the polarizer.
(3) It’s not permitted to have pressure or impulse on the module because the LCD panel will be damaged.
(4) Always follow the correct power sequence when the product is connecting and operating. This can
prevent damage to the CMOS LSI chips during latch-up.
(5) Do not pull the I/F connector in or out while the module is operating.
(6) Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and
easily scratched.
(7) It is dangerous that moisture come into or contacted the product, because moisture may damage the
product when it is operating.
(8) High temperature or humidity may reduce the performance of module. Please store this product within
the specified storage conditions.
(9) When ambient temperature is lower than 10ºC may reduce the display quality. For example, the
response time will become slowly.
10.2 SAFETY PRECAUTIONS
(1) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In case
of contact with hands, skin or clothes, it has to be washed away thoroughly with soap.
(2) After the product’s end of life, it is not harmful in case of normal operation and storage.
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11. MECHANICAL CHARACTERISTICS
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Issued Date: Nov. 19, 2009
Model No.: V400H1 - PH2
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ڻႝηިҽԖϦљ
CHI MEI
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Issued Date: Nov. 19, 2009
Model No.: V400H1 - PH2
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CHI MEI
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