Physical Size [mm] 592(W) x 339.8(H) x 1.84(D) Typ.
Display Mode TN, Normally White
Contrast Ratio 800:1 Typ.
(Typical value measured at CMO’s module)
Glass thickness (Array/CF) [mm] 0.7/0.7
Viewing Angle (CR>10) +80/-80(H), +80/-70(V) Typ.
(Typical value measured at CMO’s module)
Color Chromaticity R=(0.649, 0.328)
G=(0.269,0.583)
B=(0.150,0.088)
W=(0.308,0.321)
*Please refer to “color chromaticity” on p.17
Approval
Cell Transparency [и] 6.2%Typ.
(Typical value measured at CMO’s module)
Polarizer (CF side) Anti-Glare coating,
587.4(H) x 335.2(w). Hardness: 3H
Polarizer (TFT side) 587.4(H) x 335.2(w).
1.3 MECHANICAL SPECIFICATIONS
Item Min. Typ. Max. Unit Note
Weight - 830 - g
I/F connector mounting position
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
(2) Connector mounting position
The mounting inclination of the connector makes
the screen center within ±0.5mm as the horizontal.
+/- 0.5mm
(2)
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2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item Symbol
Storage Temperature TST -20 +60 ºC (1), (3)
Operating Ambient Temperature TOP 0 50 ºC (1), (2), (3)
Altitude Operating A OP 0 5000 M (3)
Altitude Storage A ST 0 12000 M (3)
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta Љ 40 ºC).
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Min. Max.
Relative Humidity (%RH)
100
90
Value
Unit Note
80
60
Operating Range
40
20
10
Storage Range
Temperature (ºC)
Note (2) The maximum operating temperature is based on the test condition that the surface temperature
of display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled
chamber. Thermal management should be considered in your product design to prevent the
8060-20 400 20-40
surface temperature of display area from being over 65 ºC. The range of operating temperature
may degrade in case of improper thermal management in your product design.
Note (3) The rating of environment is base on LCD module. Leave LCD cell alone, this environment
condition can’t be guaranteed. Except LCD cell, the customer has to consider the ability of other
parts of LCD module and LCD module process.
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2.2 ABSOLUTE RATINGS OF ENVIRONMENT (OPEN CELL)
Storage Condition : With shipping package.
Storage temperature range : 25±5 к
Storage humidity range : 50±10%RH
Shelf life : a month
2.3 ELECTRICAL ABSOLUTE RATINGS (OPEN CELL)
Item Symbol
Power Supply Voltage Vcc -0.3 13.5 V
Input Signal Voltage VIN -0.3 3.6 V
Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation
should be restricted to the conditions described under Normal Operating Conditions.
Min. Max.
Value
Unit Note
(1)
Approval
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Model No.: V260B1 – P31
3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
Parameter Symbol
Power Supply Voltage VCC 10.8 12.0 13.2 V (1)
Power Supply Ripple Voltage V
Rush Current I
White
Power Supply Current
Differential Input High
LVDS
Interface
Threshold Voltage
Differential Input Low
Threshold Voltage
Common Input Voltage V
Terminating Resistor R
CMOS
interface
Input High Threshold Voltage VIH 2.7
Input Low Threshold Voltage V
Note (1) The module should be always operated within above ranges.
Black
Vertical Stripe
Ta = 25 ± 2 ºC
Value
Min. Typ. Max.
RP
RUSH
I
CC
+100
V
LVT H
V
LVTL
1.125 1.25 1.375 V
LVC
T
ЁЁ
ЁЁ
Ё
Ё
Ё
0.20 0.25 A
0.25 0.30 A
0.25 0.30 A
ЁЁ
ЁЁ
Ё
100
Ё
0
IL
Ё
300 mV
3.0 A (2)
-100 mV
Ё
3.3 V
0.7 V
Unit Note
mV
ohm
Approval
(3)
Note (2) Measurement Conditions:
+12.0V
R1
200K
(Low to High)
(Control Signal)
SW
R2
1K
Vcc rising time is 470us
Q1 AO4409
2N7002
Q2
47K
VR1
C1
10uF
+12V
FUSE
C3
1uF
Vcc
(LCD Module Input)
0.9Vcc
0.1Vcc
GND
470us
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Note (3) The specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 ± 2 ºC, fv = 60
Hz, whereas a power dissipation check pattern below is displayed.
a. White Pattern
Active Area
b. Black Pattern
Active Area
c. Vertical Stripe Pattern
Active Area
Note (4) The LVDS input characteristics are as follows:
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Model No.: V260B1 – P31
4. BLOCK DIAGRAM
4.1 TFT LCD MODULE
TFT LCD PANEL
(1366x3x768)
X BOARD
LVDS SIGNAL INPUT
Connector Part No.: P-TWO 187053-30091 or Compatible
Approval
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y
(2)
(2)
(2)
g
g
(2)
(3)
(2)
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Model No.: V260B1 – P31
5. INTERFACE PIN CONNECTION
5.1 TFT LCD MODULE
CN1 Connector Pin Assignment
Pin No.S
1NC No connection
2NC No connection
3NC No connection
4GND Ground
5RX0- Ne
6RX0+ Positive transmission data of pixel 0
7GND Ground
8RX1- Ne
9RX1+ Positive transmission data of pixel 1
10GND Ground
11RX2- Negative transmission data of pixel 2
12RX2+ Positive transmission data of pixel 2
13GND Ground
14RXCLK- Negative of clock
15RXCLK+ Positive of clock
16GND Ground
17RX3- Negative transmission data of pixel 3
18RX3+ Positive transmission data of pixel 3
19GND Ground
20NC No connection
21SELLVDS Select LVDS data format
22NC No connection
23GND Ground
24GND Ground
25GND Ground
26VCC Power supply: +12V
27VCCPower supply: +12V
28VCCPower supply: +12V
29VCCPower supply: +12V
30VCCPower supply: +12V
Note (1) Connector Part No.: P-TWO, 187053-30091 or compatible
mbolDescriptionNote
ative transmission data of pixel 0
ative transmission data of pixel 1
Approval
Note (2) Reserved for internal use. Please leave it open.
Note (3) High or OPEN: Normal, Ground: JEIDA LVDS format
Please refer to 5.3 LVDS INTERFACE (Page 12)
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Model No.: V260B1 – P31
5.2 BLOCK DIAGRAM OF INTERFACE
R0-R7
-
B0-B7
DE
CNF1
Rx0+
-
Rx1+
Rx1-
Rx2+
Rx2-
Rx3+
Rx3-
Approval
51Ө
100pF
51Ө
51Ө
F
100
51Ө
51Ө
100pF
51Ө
51Ө
100pF
51Ө
RxOUT
R0-R7
G0-G7
B0-B7
DE
Host
Graphics
Controller
CLK+
CLK-
51Ө
51Ө
100pF
DCLK
Timing
Controller
LVDS Transmitter
THC63LVDM83A
LVDS Receiver
THC63LVDF84A
(LVDF83A)
R0~R7 : Pixel R Data
G0~G7 : Pixel G Data
B0~B7 : Pixel B Data
DE : Data Enable Signal
Note (1) The system must have the transmitter to drive the module.
Note (2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it is
used differentially.
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5.3 LVDS INTERFACE
VESA LVDS formatΚ(SELLVDS pin=H or Open)
XCLK
XCLK
R
R
ORX0
ORX0
ORX1
ORX1
ORX2
ORX2
ORX3
ORX3
ERX0
ERX0
ERX1
ERX1
ERX2
ERX2
Current ˶˶˿˸
Current ˶˶˿˸
R5G0R4R3R2R1
R5G0R4R3R2R1
B0G5B1
B0G5B1
E
E
R5G0R4R3R2R1
R5G0R4R3R2R1
B0G5B1
B0G5B1
Approval
R0
R0
G3G2G4
G3G2G4
G3G2G4
G3G2G4
G1
G1
B2B4B3B5VSHSD
B2B4B3B5VSHSD
R6G6R7G7B7B6RSVD
R6G6R7G7B7B6RSVD
R0
R0
G1
G1
B2B4B3B5VSHSDE
B2B4B3B5VSHSDE
ERX3
ERX3
JEDIA LVDS formatΚ(SELLVDS pin=L)
RXCLK
RXCLK
ORX0
ORX0
ORX1
ORX1
ORX2
ORX2
ORX3
ORX3
ERX0
ERX0
ERX1
ERX1
ERX2
ERX2
ERX3
ERX3
Current ˶˶˿˸
Current ˶˶˿˸
R7G2R6R5R4R3
R7G2R6R5R4R3
B2G7B3
B2G7B3
R7G2R6R5R4R3
R7G2R6R5R4R3
B2G7B3
B2G7B3
G5G4G6
G5G4G6
G5G4G6
G5G4G6
R6G6R7G7B7B6RSVD
R6G6R7G7B7B6RSVD
R2
R2
G3
G3
B4B6B5B7VSHSDE
B4B6B5B7VSHSDE
R0G0R1G1B1B0RSVD
R0G0R1G1B1B0RSVD
R2
R2
G3
G3
B4B6B5B7VSHSDE
B4B6B5B7VSHSDE
R0G0R1G1B1B0RSVD
R0G0R1G1B1B0RSVD
R0~R7: Pixel R Data (7; MSB, 0; LSB)
G0~G7: Pixel G Data (7; MSB, 0; LSB)
B0~B7: Pixel B Data (7; MSB, 0; LSB)
DE : Data enable signal
Notes(1) RSVD(reserved)pins on the transmitter shall be “H” or “L”.
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5.4 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 8-bit gray scale data input for
the color. The higher the binary input, the brighter the color. The table below provides the assignment of